arch/arm/mach-at91/at91cap9_devices.c

   1 /*
   2  * arch/arm/mach-at91/at91cap9_devices.c
   3  *
   4  *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
   5  *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
   6  *  Copyright (C) 2007 Atmel Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  */
  14 #include <asm/mach/arch.h>
  15 #include <asm/mach/map.h>
  16 #include <asm/mach/irq.h>
  17
  18 #include <linux/dma-mapping.h>
  19 #include <linux/gpio.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/i2c-gpio.h>
  22
  23 #include <video/atmel_lcdc.h>
  24
  25 #include <mach/board.h>
  26 #include <mach/cpu.h>
  27 #include <mach/at91cap9.h>
  28 #include <mach/at91cap9_matrix.h>
  29 #include <mach/at91sam9_smc.h>
  30
  31 #include "generic.h"
  32
  33
  34 /* --------------------------------------------------------------------
  35  *  USB Host
  36  * -------------------------------------------------------------------- */
  37
  38 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  39 static u64 ohci_dmamask = DMA_BIT_MASK(32);
  40 static struct at91_usbh_data usbh_data;
  41
  42 static struct resource usbh_resources[] = {
  43         [0] = {
  44                 .start  = AT91CAP9_UHP_BASE,
  45                 .end    = AT91CAP9_UHP_BASE + SZ_1M - 1,
  46                 .flags  = IORESOURCE_MEM,
  47         },
  48         [1] = {
  49                 .start  = AT91CAP9_ID_UHP,
  50                 .end    = AT91CAP9_ID_UHP,
  51                 .flags  = IORESOURCE_IRQ,
  52         },
  53 };
  54
  55 static struct platform_device at91_usbh_device = {
  56         .name           = "at91_ohci",
  57         .id             = -1,
  58         .dev            = {
  59                                 .dma_mask               = &ohci_dmamask,
  60                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
  61                                 .platform_data          = &usbh_data,
  62         },
  63         .resource       = usbh_resources,
  64         .num_resources  = ARRAY_SIZE(usbh_resources),
  65 };
  66
  67 void __init at91_add_device_usbh(struct at91_usbh_data *data)
  68 {
  69         int i;
  70
  71         if (!data)
  72                 return;
  73
  74         if (cpu_is_at91cap9_revB())
  75                 irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
  76
  77         /* Enable VBus control for UHP ports */
  78         for (i = 0; i < data->ports; i++) {
  79                 if (data->vbus_pin[i])
  80                         at91_set_gpio_output(data->vbus_pin[i], 0);
  81         }
  82
  83         /* Enable overcurrent notification */
  84         for (i = 0; i < data->ports; i++) {
  85                 if (data->overcurrent_pin[i])
  86                         at91_set_gpio_input(data->overcurrent_pin[i], 1);
  87         }
  88
  89         usbh_data = *data;
  90         platform_device_register(&at91_usbh_device);
  91 }
  92 #else
  93 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
  94 #endif
  95
  96
  97 /* --------------------------------------------------------------------
  98  *  USB HS Device (Gadget)
  99  * -------------------------------------------------------------------- */
 100
 101 #if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
 102
 103 static struct resource usba_udc_resources[] = {
 104         [0] = {
 105                 .start  = AT91CAP9_UDPHS_FIFO,
 106                 .end    = AT91CAP9_UDPHS_FIFO + SZ_512K - 1,
 107                 .flags  = IORESOURCE_MEM,
 108         },
 109         [1] = {
 110                 .start  = AT91CAP9_BASE_UDPHS,
 111                 .end    = AT91CAP9_BASE_UDPHS + SZ_1K - 1,
 112                 .flags  = IORESOURCE_MEM,
 113         },
 114         [2] = {
 115                 .start  = AT91CAP9_ID_UDPHS,
 116                 .end    = AT91CAP9_ID_UDPHS,
 117                 .flags  = IORESOURCE_IRQ,
 118         },
 119 };
 120
 121 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
 122         [idx] = {                                               \
 123                 .name           = nam,                          \
 124                 .index          = idx,                          \
 125                 .fifo_size      = maxpkt,                       \
 126                 .nr_banks       = maxbk,                        \
 127                 .can_dma        = dma,                          \
 128                 .can_isoc       = isoc,                         \
 129         }
 130
 131 static struct usba_ep_data usba_udc_ep[] = {
 132         EP("ep0", 0,   64, 1, 0, 0),
 133         EP("ep1", 1, 1024, 3, 1, 1),
 134         EP("ep2", 2, 1024, 3, 1, 1),
 135         EP("ep3", 3, 1024, 2, 1, 1),
 136         EP("ep4", 4, 1024, 2, 1, 1),
 137         EP("ep5", 5, 1024, 2, 1, 0),
 138         EP("ep6", 6, 1024, 2, 1, 0),
 139         EP("ep7", 7, 1024, 2, 0, 0),
 140 };
 141
 142 #undef EP
 143
 144 /*
 145  * pdata doesn't have room for any endpoints, so we need to
 146  * append room for the ones we need right after it.
 147  */
 148 static struct {
 149         struct usba_platform_data pdata;
 150         struct usba_ep_data ep[8];
 151 } usba_udc_data;
 152
 153 static struct platform_device at91_usba_udc_device = {
 154         .name           = "atmel_usba_udc",
 155         .id             = -1,
 156         .dev            = {
 157                                 .platform_data  = &usba_udc_data.pdata,
 158         },
 159         .resource       = usba_udc_resources,
 160         .num_resources  = ARRAY_SIZE(usba_udc_resources),
 161 };
 162
 163 void __init at91_add_device_usba(struct usba_platform_data *data)
 164 {
 165         if (cpu_is_at91cap9_revB()) {
 166                 irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
 167                 at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
 168                                                   AT91_MATRIX_UDPHS_BYPASS_LOCK);
 169         }
 170         else
 171                 at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS);
 172
 173         /*
 174          * Invalid pins are 0 on AT91, but the usba driver is shared
 175          * with AVR32, which use negative values instead. Once/if
 176          * gpio_is_valid() is ported to AT91, revisit this code.
 177          */
 178         usba_udc_data.pdata.vbus_pin = -EINVAL;
 179         usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
 180         memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
 181
 182         if (data && data->vbus_pin > 0) {
 183                 at91_set_gpio_input(data->vbus_pin, 0);
 184                 at91_set_deglitch(data->vbus_pin, 1);
 185                 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
 186         }
 187
 188         /* Pullup pin is handled internally by USB device peripheral */
 189
 190         platform_device_register(&at91_usba_udc_device);
 191 }
 192 #else
 193 void __init at91_add_device_usba(struct usba_platform_data *data) {}
 194 #endif
 195
 196
 197 /* --------------------------------------------------------------------
 198  *  Ethernet
 199  * -------------------------------------------------------------------- */
 200
 201 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
 202 static u64 eth_dmamask = DMA_BIT_MASK(32);
 203 static struct at91_eth_data eth_data;
 204
 205 static struct resource eth_resources[] = {
 206         [0] = {
 207                 .start  = AT91CAP9_BASE_EMAC,
 208                 .end    = AT91CAP9_BASE_EMAC + SZ_16K - 1,
 209                 .flags  = IORESOURCE_MEM,
 210         },
 211         [1] = {
 212                 .start  = AT91CAP9_ID_EMAC,
 213                 .end    = AT91CAP9_ID_EMAC,
 214                 .flags  = IORESOURCE_IRQ,
 215         },
 216 };
 217
 218 static struct platform_device at91cap9_eth_device = {
 219         .name           = "macb",
 220         .id             = -1,
 221         .dev            = {
 222                                 .dma_mask               = &eth_dmamask,
 223                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 224                                 .platform_data          = &eth_data,
 225         },
 226         .resource       = eth_resources,
 227         .num_resources  = ARRAY_SIZE(eth_resources),
 228 };
 229
 230 void __init at91_add_device_eth(struct at91_eth_data *data)
 231 {
 232         if (!data)
 233                 return;
 234
 235         if (data->phy_irq_pin) {
 236                 at91_set_gpio_input(data->phy_irq_pin, 0);
 237                 at91_set_deglitch(data->phy_irq_pin, 1);
 238         }
 239
 240         /* Pins used for MII and RMII */
 241         at91_set_A_periph(AT91_PIN_PB21, 0);    /* ETXCK_EREFCK */
 242         at91_set_A_periph(AT91_PIN_PB22, 0);    /* ERXDV */
 243         at91_set_A_periph(AT91_PIN_PB25, 0);    /* ERX0 */
 244         at91_set_A_periph(AT91_PIN_PB26, 0);    /* ERX1 */
 245         at91_set_A_periph(AT91_PIN_PB27, 0);    /* ERXER */
 246         at91_set_A_periph(AT91_PIN_PB28, 0);    /* ETXEN */
 247         at91_set_A_periph(AT91_PIN_PB23, 0);    /* ETX0 */
 248         at91_set_A_periph(AT91_PIN_PB24, 0);    /* ETX1 */
 249         at91_set_A_periph(AT91_PIN_PB30, 0);    /* EMDIO */
 250         at91_set_A_periph(AT91_PIN_PB29, 0);    /* EMDC */
 251
 252         if (!data->is_rmii) {
 253                 at91_set_B_periph(AT91_PIN_PC25, 0);    /* ECRS */
 254                 at91_set_B_periph(AT91_PIN_PC26, 0);    /* ECOL */
 255                 at91_set_B_periph(AT91_PIN_PC22, 0);    /* ERX2 */
 256                 at91_set_B_periph(AT91_PIN_PC23, 0);    /* ERX3 */
 257                 at91_set_B_periph(AT91_PIN_PC27, 0);    /* ERXCK */
 258                 at91_set_B_periph(AT91_PIN_PC20, 0);    /* ETX2 */
 259                 at91_set_B_periph(AT91_PIN_PC21, 0);    /* ETX3 */
 260                 at91_set_B_periph(AT91_PIN_PC24, 0);    /* ETXER */
 261         }
 262
 263         eth_data = *data;
 264         platform_device_register(&at91cap9_eth_device);
 265 }
 266 #else
 267 void __init at91_add_device_eth(struct at91_eth_data *data) {}
 268 #endif
 269
 270
 271 /* --------------------------------------------------------------------
 272  *  MMC / SD
 273  * -------------------------------------------------------------------- */
 274
 275 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
 276 static u64 mmc_dmamask = DMA_BIT_MASK(32);
 277 static struct at91_mmc_data mmc0_data, mmc1_data;
 278
 279 static struct resource mmc0_resources[] = {
 280         [0] = {
 281                 .start  = AT91CAP9_BASE_MCI0,
 282                 .end    = AT91CAP9_BASE_MCI0 + SZ_16K - 1,
 283                 .flags  = IORESOURCE_MEM,
 284         },
 285         [1] = {
 286                 .start  = AT91CAP9_ID_MCI0,
 287                 .end    = AT91CAP9_ID_MCI0,
 288                 .flags  = IORESOURCE_IRQ,
 289         },
 290 };
 291
 292 static struct platform_device at91cap9_mmc0_device = {
 293         .name           = "at91_mci",
 294         .id             = 0,
 295         .dev            = {
 296                                 .dma_mask               = &mmc_dmamask,
 297                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 298                                 .platform_data          = &mmc0_data,
 299         },
 300         .resource       = mmc0_resources,
 301         .num_resources  = ARRAY_SIZE(mmc0_resources),
 302 };
 303
 304 static struct resource mmc1_resources[] = {
 305         [0] = {
 306                 .start  = AT91CAP9_BASE_MCI1,
 307                 .end    = AT91CAP9_BASE_MCI1 + SZ_16K - 1,
 308                 .flags  = IORESOURCE_MEM,
 309         },
 310         [1] = {
 311                 .start  = AT91CAP9_ID_MCI1,
 312                 .end    = AT91CAP9_ID_MCI1,
 313                 .flags  = IORESOURCE_IRQ,
 314         },
 315 };
 316
 317 static struct platform_device at91cap9_mmc1_device = {
 318         .name           = "at91_mci",
 319         .id             = 1,
 320         .dev            = {
 321                                 .dma_mask               = &mmc_dmamask,
 322                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 323                                 .platform_data          = &mmc1_data,
 324         },
 325         .resource       = mmc1_resources,
 326         .num_resources  = ARRAY_SIZE(mmc1_resources),
 327 };
 328
 329 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
 330 {
 331         if (!data)
 332                 return;
 333
 334         /* input/irq */
 335         if (data->det_pin) {
 336                 at91_set_gpio_input(data->det_pin, 1);
 337                 at91_set_deglitch(data->det_pin, 1);
 338         }
 339         if (data->wp_pin)
 340                 at91_set_gpio_input(data->wp_pin, 1);
 341         if (data->vcc_pin)
 342                 at91_set_gpio_output(data->vcc_pin, 0);
 343
 344         if (mmc_id == 0) {              /* MCI0 */
 345                 /* CLK */
 346                 at91_set_A_periph(AT91_PIN_PA2, 0);
 347
 348                 /* CMD */
 349                 at91_set_A_periph(AT91_PIN_PA1, 1);
 350
 351                 /* DAT0, maybe DAT1..DAT3 */
 352                 at91_set_A_periph(AT91_PIN_PA0, 1);
 353                 if (data->wire4) {
 354                         at91_set_A_periph(AT91_PIN_PA3, 1);
 355                         at91_set_A_periph(AT91_PIN_PA4, 1);
 356                         at91_set_A_periph(AT91_PIN_PA5, 1);
 357                 }
 358
 359                 mmc0_data = *data;
 360                 platform_device_register(&at91cap9_mmc0_device);
 361         } else {                        /* MCI1 */
 362                 /* CLK */
 363                 at91_set_A_periph(AT91_PIN_PA16, 0);
 364
 365                 /* CMD */
 366                 at91_set_A_periph(AT91_PIN_PA17, 1);
 367
 368                 /* DAT0, maybe DAT1..DAT3 */
 369                 at91_set_A_periph(AT91_PIN_PA18, 1);
 370                 if (data->wire4) {
 371                         at91_set_A_periph(AT91_PIN_PA19, 1);
 372                         at91_set_A_periph(AT91_PIN_PA20, 1);
 373                         at91_set_A_periph(AT91_PIN_PA21, 1);
 374                 }
 375
 376                 mmc1_data = *data;
 377                 platform_device_register(&at91cap9_mmc1_device);
 378         }
 379 }
 380 #else
 381 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
 382 #endif
 383
 384
 385 /* --------------------------------------------------------------------
 386  *  NAND / SmartMedia
 387  * -------------------------------------------------------------------- */
 388
 389 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
 390 static struct atmel_nand_data nand_data;
 391
 392 #define NAND_BASE       AT91_CHIPSELECT_3
 393
 394 static struct resource nand_resources[] = {
 395         [0] = {
 396                 .start  = NAND_BASE,
 397                 .end    = NAND_BASE + SZ_256M - 1,
 398                 .flags  = IORESOURCE_MEM,
 399         },
 400         [1] = {
 401                 .start  = AT91_BASE_SYS + AT91_ECC,
 402                 .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
 403                 .flags  = IORESOURCE_MEM,
 404         }
 405 };
 406
 407 static struct platform_device at91cap9_nand_device = {
 408         .name           = "atmel_nand",
 409         .id             = -1,
 410         .dev            = {
 411                                 .platform_data  = &nand_data,
 412         },
 413         .resource       = nand_resources,
 414         .num_resources  = ARRAY_SIZE(nand_resources),
 415 };
 416
 417 void __init at91_add_device_nand(struct atmel_nand_data *data)
 418 {
 419         unsigned long csa;
 420
 421         if (!data)
 422                 return;
 423
 424         csa = at91_sys_read(AT91_MATRIX_EBICSA);
 425         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
 426
 427         /* enable pin */
 428         if (data->enable_pin)
 429                 at91_set_gpio_output(data->enable_pin, 1);
 430
 431         /* ready/busy pin */
 432         if (data->rdy_pin)
 433                 at91_set_gpio_input(data->rdy_pin, 1);
 434
 435         /* card detect pin */
 436         if (data->det_pin)
 437                 at91_set_gpio_input(data->det_pin, 1);
 438
 439         nand_data = *data;
 440         platform_device_register(&at91cap9_nand_device);
 441 }
 442 #else
 443 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
 444 #endif
 445
 446
 447 /* --------------------------------------------------------------------
 448  *  TWI (i2c)
 449  * -------------------------------------------------------------------- */
 450
 451 /*
 452  * Prefer the GPIO code since the TWI controller isn't robust
 453  * (gets overruns and underruns under load) and can only issue
 454  * repeated STARTs in one scenario (the driver doesn't yet handle them).
 455  */
 456 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
 457
 458 static struct i2c_gpio_platform_data pdata = {
 459         .sda_pin                = AT91_PIN_PB4,
 460         .sda_is_open_drain      = 1,
 461         .scl_pin                = AT91_PIN_PB5,
 462         .scl_is_open_drain      = 1,
 463         .udelay                 = 2,            /* ~100 kHz */
 464 };
 465
 466 static struct platform_device at91cap9_twi_device = {
 467         .name                   = "i2c-gpio",
 468         .id                     = -1,
 469         .dev.platform_data      = &pdata,
 470 };
 471
 472 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 473 {
 474         at91_set_GPIO_periph(AT91_PIN_PB4, 1);          /* TWD (SDA) */
 475         at91_set_multi_drive(AT91_PIN_PB4, 1);
 476
 477         at91_set_GPIO_periph(AT91_PIN_PB5, 1);          /* TWCK (SCL) */
 478         at91_set_multi_drive(AT91_PIN_PB5, 1);
 479
 480         i2c_register_board_info(0, devices, nr_devices);
 481         platform_device_register(&at91cap9_twi_device);
 482 }
 483
 484 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
 485
 486 static struct resource twi_resources[] = {
 487         [0] = {
 488                 .start  = AT91CAP9_BASE_TWI,
 489                 .end    = AT91CAP9_BASE_TWI + SZ_16K - 1,
 490                 .flags  = IORESOURCE_MEM,
 491         },
 492         [1] = {
 493                 .start  = AT91CAP9_ID_TWI,
 494                 .end    = AT91CAP9_ID_TWI,
 495                 .flags  = IORESOURCE_IRQ,
 496         },
 497 };
 498
 499 static struct platform_device at91cap9_twi_device = {
 500         .name           = "at91_i2c",
 501         .id             = -1,
 502         .resource       = twi_resources,
 503         .num_resources  = ARRAY_SIZE(twi_resources),
 504 };
 505
 506 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 507 {
 508         /* pins used for TWI interface */
 509         at91_set_B_periph(AT91_PIN_PB4, 0);             /* TWD */
 510         at91_set_multi_drive(AT91_PIN_PB4, 1);
 511
 512         at91_set_B_periph(AT91_PIN_PB5, 0);             /* TWCK */
 513         at91_set_multi_drive(AT91_PIN_PB5, 1);
 514
 515         i2c_register_board_info(0, devices, nr_devices);
 516         platform_device_register(&at91cap9_twi_device);
 517 }
 518 #else
 519 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
 520 #endif
 521
 522 /* --------------------------------------------------------------------
 523  *  SPI
 524  * -------------------------------------------------------------------- */
 525
 526 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
 527 static u64 spi_dmamask = DMA_BIT_MASK(32);
 528
 529 static struct resource spi0_resources[] = {
 530         [0] = {
 531                 .start  = AT91CAP9_BASE_SPI0,
 532                 .end    = AT91CAP9_BASE_SPI0 + SZ_16K - 1,
 533                 .flags  = IORESOURCE_MEM,
 534         },
 535         [1] = {
 536                 .start  = AT91CAP9_ID_SPI0,
 537                 .end    = AT91CAP9_ID_SPI0,
 538                 .flags  = IORESOURCE_IRQ,
 539         },
 540 };
 541
 542 static struct platform_device at91cap9_spi0_device = {
 543         .name           = "atmel_spi",
 544         .id             = 0,
 545         .dev            = {
 546                                 .dma_mask               = &spi_dmamask,
 547                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 548         },
 549         .resource       = spi0_resources,
 550         .num_resources  = ARRAY_SIZE(spi0_resources),
 551 };
 552
 553 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PD0, AT91_PIN_PD1 };
 554
 555 static struct resource spi1_resources[] = {
 556         [0] = {
 557                 .start  = AT91CAP9_BASE_SPI1,
 558                 .end    = AT91CAP9_BASE_SPI1 + SZ_16K - 1,
 559                 .flags  = IORESOURCE_MEM,
 560         },
 561         [1] = {
 562                 .start  = AT91CAP9_ID_SPI1,
 563                 .end    = AT91CAP9_ID_SPI1,
 564                 .flags  = IORESOURCE_IRQ,
 565         },
 566 };
 567
 568 static struct platform_device at91cap9_spi1_device = {
 569         .name           = "atmel_spi",
 570         .id             = 1,
 571         .dev            = {
 572                                 .dma_mask               = &spi_dmamask,
 573                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 574         },
 575         .resource       = spi1_resources,
 576         .num_resources  = ARRAY_SIZE(spi1_resources),
 577 };
 578
 579 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
 580
 581 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 582 {
 583         int i;
 584         unsigned long cs_pin;
 585         short enable_spi0 = 0;
 586         short enable_spi1 = 0;
 587
 588         /* Choose SPI chip-selects */
 589         for (i = 0; i < nr_devices; i++) {
 590                 if (devices[i].controller_data)
 591                         cs_pin = (unsigned long) devices[i].controller_data;
 592                 else if (devices[i].bus_num == 0)
 593                         cs_pin = spi0_standard_cs[devices[i].chip_select];
 594                 else
 595                         cs_pin = spi1_standard_cs[devices[i].chip_select];
 596
 597                 if (devices[i].bus_num == 0)
 598                         enable_spi0 = 1;
 599                 else
 600                         enable_spi1 = 1;
 601
 602                 /* enable chip-select pin */
 603                 at91_set_gpio_output(cs_pin, 1);
 604
 605                 /* pass chip-select pin to driver */
 606                 devices[i].controller_data = (void *) cs_pin;
 607         }
 608
 609         spi_register_board_info(devices, nr_devices);
 610
 611         /* Configure SPI bus(es) */
 612         if (enable_spi0) {
 613                 at91_set_B_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
 614                 at91_set_B_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
 615                 at91_set_B_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
 616
 617                 platform_device_register(&at91cap9_spi0_device);
 618         }
 619         if (enable_spi1) {
 620                 at91_set_A_periph(AT91_PIN_PB12, 0);    /* SPI1_MISO */
 621                 at91_set_A_periph(AT91_PIN_PB13, 0);    /* SPI1_MOSI */
 622                 at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_SPCK */
 623
 624                 platform_device_register(&at91cap9_spi1_device);
 625         }
 626 }
 627 #else
 628 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
 629 #endif
 630
 631
 632 /* --------------------------------------------------------------------
 633  *  Timer/Counter block
 634  * -------------------------------------------------------------------- */
 635
 636 #ifdef CONFIG_ATMEL_TCLIB
 637
 638 static struct resource tcb_resources[] = {
 639         [0] = {
 640                 .start  = AT91CAP9_BASE_TCB0,
 641                 .end    = AT91CAP9_BASE_TCB0 + SZ_16K - 1,
 642                 .flags  = IORESOURCE_MEM,
 643         },
 644         [1] = {
 645                 .start  = AT91CAP9_ID_TCB,
 646                 .end    = AT91CAP9_ID_TCB,
 647                 .flags  = IORESOURCE_IRQ,
 648         },
 649 };
 650
 651 static struct platform_device at91cap9_tcb_device = {
 652         .name           = "atmel_tcb",
 653         .id             = 0,
 654         .resource       = tcb_resources,
 655         .num_resources  = ARRAY_SIZE(tcb_resources),
 656 };
 657
 658 static void __init at91_add_device_tc(void)
 659 {
 660         platform_device_register(&at91cap9_tcb_device);
 661 }
 662 #else
 663 static void __init at91_add_device_tc(void) { }
 664 #endif
 665
 666
 667 /* --------------------------------------------------------------------
 668  *  RTT
 669  * -------------------------------------------------------------------- */
 670
 671 static struct resource rtt_resources[] = {
 672         {
 673                 .start  = AT91_BASE_SYS + AT91_RTT,
 674                 .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
 675                 .flags  = IORESOURCE_MEM,
 676         }
 677 };
 678
 679 static struct platform_device at91cap9_rtt_device = {
 680         .name           = "at91_rtt",
 681         .id             = 0,
 682         .resource       = rtt_resources,
 683         .num_resources  = ARRAY_SIZE(rtt_resources),
 684 };
 685
 686 static void __init at91_add_device_rtt(void)
 687 {
 688         platform_device_register(&at91cap9_rtt_device);
 689 }
 690
 691
 692 /* --------------------------------------------------------------------
 693  *  Watchdog
 694  * -------------------------------------------------------------------- */
 695
 696 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
 697 static struct platform_device at91cap9_wdt_device = {
 698         .name           = "at91_wdt",
 699         .id             = -1,
 700         .num_resources  = 0,
 701 };
 702
 703 static void __init at91_add_device_watchdog(void)
 704 {
 705         platform_device_register(&at91cap9_wdt_device);
 706 }
 707 #else
 708 static void __init at91_add_device_watchdog(void) {}
 709 #endif
 710
 711
 712 /* --------------------------------------------------------------------
 713  *  PWM
 714  * --------------------------------------------------------------------*/
 715
 716 #if defined(CONFIG_ATMEL_PWM)
 717 static u32 pwm_mask;
 718
 719 static struct resource pwm_resources[] = {
 720         [0] = {
 721                 .start  = AT91CAP9_BASE_PWMC,
 722                 .end    = AT91CAP9_BASE_PWMC + SZ_16K - 1,
 723                 .flags  = IORESOURCE_MEM,
 724         },
 725         [1] = {
 726                 .start  = AT91CAP9_ID_PWMC,
 727                 .end    = AT91CAP9_ID_PWMC,
 728                 .flags  = IORESOURCE_IRQ,
 729         },
 730 };
 731
 732 static struct platform_device at91cap9_pwm0_device = {
 733         .name   = "atmel_pwm",
 734         .id     = -1,
 735         .dev    = {
 736                 .platform_data          = &pwm_mask,
 737         },
 738         .resource       = pwm_resources,
 739         .num_resources  = ARRAY_SIZE(pwm_resources),
 740 };
 741
 742 void __init at91_add_device_pwm(u32 mask)
 743 {
 744         if (mask & (1 << AT91_PWM0))
 745                 at91_set_A_periph(AT91_PIN_PB19, 1);    /* enable PWM0 */
 746
 747         if (mask & (1 << AT91_PWM1))
 748                 at91_set_B_periph(AT91_PIN_PB8, 1);     /* enable PWM1 */
 749
 750         if (mask & (1 << AT91_PWM2))
 751                 at91_set_B_periph(AT91_PIN_PC29, 1);    /* enable PWM2 */
 752
 753         if (mask & (1 << AT91_PWM3))
 754                 at91_set_B_periph(AT91_PIN_PA11, 1);    /* enable PWM3 */
 755
 756         pwm_mask = mask;
 757
 758         platform_device_register(&at91cap9_pwm0_device);
 759 }
 760 #else
 761 void __init at91_add_device_pwm(u32 mask) {}
 762 #endif
 763
 764
 765
 766 /* --------------------------------------------------------------------
 767  *  AC97
 768  * -------------------------------------------------------------------- */
 769
 770 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
 771 static u64 ac97_dmamask = DMA_BIT_MASK(32);
 772 static struct ac97c_platform_data ac97_data;
 773
 774 static struct resource ac97_resources[] = {
 775         [0] = {
 776                 .start  = AT91CAP9_BASE_AC97C,
 777                 .end    = AT91CAP9_BASE_AC97C + SZ_16K - 1,
 778                 .flags  = IORESOURCE_MEM,
 779         },
 780         [1] = {
 781                 .start  = AT91CAP9_ID_AC97C,
 782                 .end    = AT91CAP9_ID_AC97C,
 783                 .flags  = IORESOURCE_IRQ,
 784         },
 785 };
 786
 787 static struct platform_device at91cap9_ac97_device = {
 788         .name           = "atmel_ac97c",
 789         .id             = 1,
 790         .dev            = {
 791                                 .dma_mask               = &ac97_dmamask,
 792                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 793                                 .platform_data          = &ac97_data,
 794         },
 795         .resource       = ac97_resources,
 796         .num_resources  = ARRAY_SIZE(ac97_resources),
 797 };
 798
 799 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
 800 {
 801         if (!data)
 802                 return;
 803
 804         at91_set_A_periph(AT91_PIN_PA6, 0);     /* AC97FS */
 805         at91_set_A_periph(AT91_PIN_PA7, 0);     /* AC97CK */
 806         at91_set_A_periph(AT91_PIN_PA8, 0);     /* AC97TX */
 807         at91_set_A_periph(AT91_PIN_PA9, 0);     /* AC97RX */
 808
 809         /* reset */
 810         if (data->reset_pin)
 811                 at91_set_gpio_output(data->reset_pin, 0);
 812
 813         ac97_data = *data;
 814         platform_device_register(&at91cap9_ac97_device);
 815 }
 816 #else
 817 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
 818 #endif
 819
 820
 821 /* --------------------------------------------------------------------
 822  *  LCD Controller
 823  * -------------------------------------------------------------------- */
 824
 825 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
 826 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
 827 static struct atmel_lcdfb_info lcdc_data;
 828
 829 static struct resource lcdc_resources[] = {
 830         [0] = {
 831                 .start  = AT91CAP9_LCDC_BASE,
 832                 .end    = AT91CAP9_LCDC_BASE + SZ_4K - 1,
 833                 .flags  = IORESOURCE_MEM,
 834         },
 835         [1] = {
 836                 .start  = AT91CAP9_ID_LCDC,
 837                 .end    = AT91CAP9_ID_LCDC,
 838                 .flags  = IORESOURCE_IRQ,
 839         },
 840 };
 841
 842 static struct platform_device at91_lcdc_device = {
 843         .name           = "atmel_lcdfb",
 844         .id             = 0,
 845         .dev            = {
 846                                 .dma_mask               = &lcdc_dmamask,
 847                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 848                                 .platform_data          = &lcdc_data,
 849         },
 850         .resource       = lcdc_resources,
 851         .num_resources  = ARRAY_SIZE(lcdc_resources),
 852 };
 853
 854 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
 855 {
 856         if (!data)
 857                 return;
 858
 859         if (cpu_is_at91cap9_revB())
 860                 irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
 861
 862         at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
 863         at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
 864         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
 865         at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
 866         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
 867         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
 868         at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
 869         at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
 870         at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
 871         at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
 872         at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
 873         at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 874         at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 875         at91_set_A_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
 876         at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 877         at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 878         at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
 879         at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
 880         at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
 881         at91_set_A_periph(AT91_PIN_PC25, 0);    /* LCDD21 */
 882         at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
 883         at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
 884
 885         lcdc_data = *data;
 886         platform_device_register(&at91_lcdc_device);
 887 }
 888 #else
 889 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 890 #endif
 891
 892
 893 /* --------------------------------------------------------------------
 894  *  SSC -- Synchronous Serial Controller
 895  * -------------------------------------------------------------------- */
 896
 897 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
 898 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
 899
 900 static struct resource ssc0_resources[] = {
 901         [0] = {
 902                 .start  = AT91CAP9_BASE_SSC0,
 903                 .end    = AT91CAP9_BASE_SSC0 + SZ_16K - 1,
 904                 .flags  = IORESOURCE_MEM,
 905         },
 906         [1] = {
 907                 .start  = AT91CAP9_ID_SSC0,
 908                 .end    = AT91CAP9_ID_SSC0,
 909                 .flags  = IORESOURCE_IRQ,
 910         },
 911 };
 912
 913 static struct platform_device at91cap9_ssc0_device = {
 914         .name   = "ssc",
 915         .id     = 0,
 916         .dev    = {
 917                 .dma_mask               = &ssc0_dmamask,
 918                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 919         },
 920         .resource       = ssc0_resources,
 921         .num_resources  = ARRAY_SIZE(ssc0_resources),
 922 };
 923
 924 static inline void configure_ssc0_pins(unsigned pins)
 925 {
 926         if (pins & ATMEL_SSC_TF)
 927                 at91_set_A_periph(AT91_PIN_PB0, 1);
 928         if (pins & ATMEL_SSC_TK)
 929                 at91_set_A_periph(AT91_PIN_PB1, 1);
 930         if (pins & ATMEL_SSC_TD)
 931                 at91_set_A_periph(AT91_PIN_PB2, 1);
 932         if (pins & ATMEL_SSC_RD)
 933                 at91_set_A_periph(AT91_PIN_PB3, 1);
 934         if (pins & ATMEL_SSC_RK)
 935                 at91_set_A_periph(AT91_PIN_PB4, 1);
 936         if (pins & ATMEL_SSC_RF)
 937                 at91_set_A_periph(AT91_PIN_PB5, 1);
 938 }
 939
 940 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
 941
 942 static struct resource ssc1_resources[] = {
 943         [0] = {
 944                 .start  = AT91CAP9_BASE_SSC1,
 945                 .end    = AT91CAP9_BASE_SSC1 + SZ_16K - 1,
 946                 .flags  = IORESOURCE_MEM,
 947         },
 948         [1] = {
 949                 .start  = AT91CAP9_ID_SSC1,
 950                 .end    = AT91CAP9_ID_SSC1,
 951                 .flags  = IORESOURCE_IRQ,
 952         },
 953 };
 954
 955 static struct platform_device at91cap9_ssc1_device = {
 956         .name   = "ssc",
 957         .id     = 1,
 958         .dev    = {
 959                 .dma_mask               = &ssc1_dmamask,
 960                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 961         },
 962         .resource       = ssc1_resources,
 963         .num_resources  = ARRAY_SIZE(ssc1_resources),
 964 };
 965
 966 static inline void configure_ssc1_pins(unsigned pins)
 967 {
 968         if (pins & ATMEL_SSC_TF)
 969                 at91_set_A_periph(AT91_PIN_PB6, 1);
 970         if (pins & ATMEL_SSC_TK)
 971                 at91_set_A_periph(AT91_PIN_PB7, 1);
 972         if (pins & ATMEL_SSC_TD)
 973                 at91_set_A_periph(AT91_PIN_PB8, 1);
 974         if (pins & ATMEL_SSC_RD)
 975                 at91_set_A_periph(AT91_PIN_PB9, 1);
 976         if (pins & ATMEL_SSC_RK)
 977                 at91_set_A_periph(AT91_PIN_PB10, 1);
 978         if (pins & ATMEL_SSC_RF)
 979                 at91_set_A_periph(AT91_PIN_PB11, 1);
 980 }
 981
 982 /*
 983  * SSC controllers are accessed through library code, instead of any
 984  * kind of all-singing/all-dancing driver.  For example one could be
 985  * used by a particular I2S audio codec's driver, while another one
 986  * on the same system might be used by a custom data capture driver.
 987  */
 988 void __init at91_add_device_ssc(unsigned id, unsigned pins)
 989 {
 990         struct platform_device *pdev;
 991
 992         /*
 993          * NOTE: caller is responsible for passing information matching
 994          * "pins" to whatever will be using each particular controller.
 995          */
 996         switch (id) {
 997         case AT91CAP9_ID_SSC0:
 998                 pdev = &at91cap9_ssc0_device;
 999                 configure_ssc0_pins(pins);
1000                 break;
1001         case AT91CAP9_ID_SSC1:
1002                 pdev = &at91cap9_ssc1_device;
1003                 configure_ssc1_pins(pins);
1004                 break;
1005         default:
1006                 return;
1007         }
1008
1009         platform_device_register(pdev);
1010 }
1011
1012 #else
1013 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1014 #endif
1015
1016
1017 /* --------------------------------------------------------------------
1018  *  UART
1019  * -------------------------------------------------------------------- */
1020
1021 #if defined(CONFIG_SERIAL_ATMEL)
1022 static struct resource dbgu_resources[] = {
1023         [0] = {
1024                 .start  = AT91_BASE_SYS + AT91_DBGU,
1025                 .end    = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
1026                 .flags  = IORESOURCE_MEM,
1027         },
1028         [1] = {
1029                 .start  = AT91_ID_SYS,
1030                 .end    = AT91_ID_SYS,
1031                 .flags  = IORESOURCE_IRQ,
1032         },
1033 };
1034
1035 static struct atmel_uart_data dbgu_data = {
1036         .use_dma_tx     = 0,
1037         .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
1038 };
1039
1040 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1041
1042 static struct platform_device at91cap9_dbgu_device = {
1043         .name           = "atmel_usart",
1044         .id             = 0,
1045         .dev            = {
1046                                 .dma_mask               = &dbgu_dmamask,
1047                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1048                                 .platform_data          = &dbgu_data,
1049         },
1050         .resource       = dbgu_resources,
1051         .num_resources  = ARRAY_SIZE(dbgu_resources),
1052 };
1053
1054 static inline void configure_dbgu_pins(void)
1055 {
1056         at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
1057         at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
1058 }
1059
1060 static struct resource uart0_resources[] = {
1061         [0] = {
1062                 .start  = AT91CAP9_BASE_US0,
1063                 .end    = AT91CAP9_BASE_US0 + SZ_16K - 1,
1064                 .flags  = IORESOURCE_MEM,
1065         },
1066         [1] = {
1067                 .start  = AT91CAP9_ID_US0,
1068                 .end    = AT91CAP9_ID_US0,
1069                 .flags  = IORESOURCE_IRQ,
1070         },
1071 };
1072
1073 static struct atmel_uart_data uart0_data = {
1074         .use_dma_tx     = 1,
1075         .use_dma_rx     = 1,
1076 };
1077
1078 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1079
1080 static struct platform_device at91cap9_uart0_device = {
1081         .name           = "atmel_usart",
1082         .id             = 1,
1083         .dev            = {
1084                                 .dma_mask               = &uart0_dmamask,
1085                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1086                                 .platform_data          = &uart0_data,
1087         },
1088         .resource       = uart0_resources,
1089         .num_resources  = ARRAY_SIZE(uart0_resources),
1090 };
1091
1092 static inline void configure_usart0_pins(unsigned pins)
1093 {
1094         at91_set_A_periph(AT91_PIN_PA22, 1);            /* TXD0 */
1095         at91_set_A_periph(AT91_PIN_PA23, 0);            /* RXD0 */
1096
1097         if (pins & ATMEL_UART_RTS)
1098                 at91_set_A_periph(AT91_PIN_PA24, 0);    /* RTS0 */
1099         if (pins & ATMEL_UART_CTS)
1100                 at91_set_A_periph(AT91_PIN_PA25, 0);    /* CTS0 */
1101 }
1102
1103 static struct resource uart1_resources[] = {
1104         [0] = {
1105                 .start  = AT91CAP9_BASE_US1,
1106                 .end    = AT91CAP9_BASE_US1 + SZ_16K - 1,
1107                 .flags  = IORESOURCE_MEM,
1108         },
1109         [1] = {
1110                 .start  = AT91CAP9_ID_US1,
1111                 .end    = AT91CAP9_ID_US1,
1112                 .flags  = IORESOURCE_IRQ,
1113         },
1114 };
1115
1116 static struct atmel_uart_data uart1_data = {
1117         .use_dma_tx     = 1,
1118         .use_dma_rx     = 1,
1119 };
1120
1121 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1122
1123 static struct platform_device at91cap9_uart1_device = {
1124         .name           = "atmel_usart",
1125         .id             = 2,
1126         .dev            = {
1127                                 .dma_mask               = &uart1_dmamask,
1128                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1129                                 .platform_data          = &uart1_data,
1130         },
1131         .resource       = uart1_resources,
1132         .num_resources  = ARRAY_SIZE(uart1_resources),
1133 };
1134
1135 static inline void configure_usart1_pins(unsigned pins)
1136 {
1137         at91_set_A_periph(AT91_PIN_PD0, 1);             /* TXD1 */
1138         at91_set_A_periph(AT91_PIN_PD1, 0);             /* RXD1 */
1139
1140         if (pins & ATMEL_UART_RTS)
1141                 at91_set_B_periph(AT91_PIN_PD7, 0);     /* RTS1 */
1142         if (pins & ATMEL_UART_CTS)
1143                 at91_set_B_periph(AT91_PIN_PD8, 0);     /* CTS1 */
1144 }
1145
1146 static struct resource uart2_resources[] = {
1147         [0] = {
1148                 .start  = AT91CAP9_BASE_US2,
1149                 .end    = AT91CAP9_BASE_US2 + SZ_16K - 1,
1150                 .flags  = IORESOURCE_MEM,
1151         },
1152         [1] = {
1153                 .start  = AT91CAP9_ID_US2,
1154                 .end    = AT91CAP9_ID_US2,
1155                 .flags  = IORESOURCE_IRQ,
1156         },
1157 };
1158
1159 static struct atmel_uart_data uart2_data = {
1160         .use_dma_tx     = 1,
1161         .use_dma_rx     = 1,
1162 };
1163
1164 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1165
1166 static struct platform_device at91cap9_uart2_device = {
1167         .name           = "atmel_usart",
1168         .id             = 3,
1169         .dev            = {
1170                                 .dma_mask               = &uart2_dmamask,
1171                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1172                                 .platform_data          = &uart2_data,
1173         },
1174         .resource       = uart2_resources,
1175         .num_resources  = ARRAY_SIZE(uart2_resources),
1176 };
1177
1178 static inline void configure_usart2_pins(unsigned pins)
1179 {
1180         at91_set_A_periph(AT91_PIN_PD2, 1);             /* TXD2 */
1181         at91_set_A_periph(AT91_PIN_PD3, 0);             /* RXD2 */
1182
1183         if (pins & ATMEL_UART_RTS)
1184                 at91_set_B_periph(AT91_PIN_PD5, 0);     /* RTS2 */
1185         if (pins & ATMEL_UART_CTS)
1186                 at91_set_B_periph(AT91_PIN_PD6, 0);     /* CTS2 */
1187 }
1188
1189 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
1190 struct platform_device *atmel_default_console_device;   /* the serial console device */
1191
1192 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1193 {
1194         struct platform_device *pdev;
1195         struct atmel_uart_data *pdata;
1196
1197         switch (id) {
1198                 case 0:         /* DBGU */
1199                         pdev = &at91cap9_dbgu_device;
1200                         configure_dbgu_pins();
1201                         break;
1202                 case AT91CAP9_ID_US0:
1203                         pdev = &at91cap9_uart0_device;
1204                         configure_usart0_pins(pins);
1205                         break;
1206                 case AT91CAP9_ID_US1:
1207                         pdev = &at91cap9_uart1_device;
1208                         configure_usart1_pins(pins);
1209                         break;
1210                 case AT91CAP9_ID_US2:
1211                         pdev = &at91cap9_uart2_device;
1212                         configure_usart2_pins(pins);
1213                         break;
1214                 default:
1215                         return;
1216         }
1217         pdata = pdev->dev.platform_data;
1218         pdata->num = portnr;            /* update to mapped ID */
1219
1220         if (portnr < ATMEL_MAX_UART)
1221                 at91_uarts[portnr] = pdev;
1222 }
1223
1224 void __init at91_set_serial_console(unsigned portnr)
1225 {
1226         if (portnr < ATMEL_MAX_UART) {
1227                 atmel_default_console_device = at91_uarts[portnr];
1228                 at91cap9_set_console_clock(at91_uarts[portnr]->id);
1229         }
1230 }
1231
1232 void __init at91_add_device_serial(void)
1233 {
1234         int i;
1235
1236         for (i = 0; i < ATMEL_MAX_UART; i++) {
1237                 if (at91_uarts[i])
1238                         platform_device_register(at91_uarts[i]);
1239         }
1240
1241         if (!atmel_default_console_device)
1242                 printk(KERN_INFO "AT91: No default serial console defined.\n");
1243 }
1244 #else
1245 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1246 void __init at91_set_serial_console(unsigned portnr) {}
1247 void __init at91_add_device_serial(void) {}
1248 #endif
1249
1250
1251 /* -------------------------------------------------------------------- */
1252 /*
1253  * These devices are always present and don't need any board-specific
1254  * setup.
1255  */
1256 static int __init at91_add_standard_devices(void)
1257 {
1258         at91_add_device_rtt();
1259         at91_add_device_watchdog();
1260         at91_add_device_tc();
1261         return 0;
1262 }
1263
1264 arch_initcall(at91_add_standard_devices);