arch/arm/mach-at91/at91cap9.c

   1 /*
   2  * arch/arm/mach-at91/at91cap9.c
   3  *
   4  *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
   5  *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
   6  *  Copyright (C) 2007 Atmel Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/pm.h>
  17
  18 #include <asm/irq.h>
  19 #include <asm/mach/arch.h>
  20 #include <asm/mach/map.h>
  21
  22 #include <mach/cpu.h>
  23 #include <mach/at91cap9.h>
  24 #include <mach/at91_pmc.h>
  25 #include <mach/at91_rstc.h>
  26 #include <mach/at91_shdwc.h>
  27
  28 #include "soc.h"
  29 #include "generic.h"
  30 #include "clock.h"
  31
  32 static struct map_desc at91cap9_sram_desc[] __initdata = {
  33         {
  34                 .virtual        = AT91_IO_VIRT_BASE - AT91CAP9_SRAM_SIZE,
  35                 .pfn            = __phys_to_pfn(AT91CAP9_SRAM_BASE),
  36                 .length         = AT91CAP9_SRAM_SIZE,
  37                 .type           = MT_DEVICE,
  38         },
  39 };
  40
  41 /* --------------------------------------------------------------------
  42  *  Clocks
  43  * -------------------------------------------------------------------- */
  44
  45 /*
  46  * The peripheral clocks.
  47  */
  48 static struct clk pioABCD_clk = {
  49         .name           = "pioABCD_clk",
  50         .pmc_mask       = 1 << AT91CAP9_ID_PIOABCD,
  51         .type           = CLK_TYPE_PERIPHERAL,
  52 };
  53 static struct clk mpb0_clk = {
  54         .name           = "mpb0_clk",
  55         .pmc_mask       = 1 << AT91CAP9_ID_MPB0,
  56         .type           = CLK_TYPE_PERIPHERAL,
  57 };
  58 static struct clk mpb1_clk = {
  59         .name           = "mpb1_clk",
  60         .pmc_mask       = 1 << AT91CAP9_ID_MPB1,
  61         .type           = CLK_TYPE_PERIPHERAL,
  62 };
  63 static struct clk mpb2_clk = {
  64         .name           = "mpb2_clk",
  65         .pmc_mask       = 1 << AT91CAP9_ID_MPB2,
  66         .type           = CLK_TYPE_PERIPHERAL,
  67 };
  68 static struct clk mpb3_clk = {
  69         .name           = "mpb3_clk",
  70         .pmc_mask       = 1 << AT91CAP9_ID_MPB3,
  71         .type           = CLK_TYPE_PERIPHERAL,
  72 };
  73 static struct clk mpb4_clk = {
  74         .name           = "mpb4_clk",
  75         .pmc_mask       = 1 << AT91CAP9_ID_MPB4,
  76         .type           = CLK_TYPE_PERIPHERAL,
  77 };
  78 static struct clk usart0_clk = {
  79         .name           = "usart0_clk",
  80         .pmc_mask       = 1 << AT91CAP9_ID_US0,
  81         .type           = CLK_TYPE_PERIPHERAL,
  82 };
  83 static struct clk usart1_clk = {
  84         .name           = "usart1_clk",
  85         .pmc_mask       = 1 << AT91CAP9_ID_US1,
  86         .type           = CLK_TYPE_PERIPHERAL,
  87 };
  88 static struct clk usart2_clk = {
  89         .name           = "usart2_clk",
  90         .pmc_mask       = 1 << AT91CAP9_ID_US2,
  91         .type           = CLK_TYPE_PERIPHERAL,
  92 };
  93 static struct clk mmc0_clk = {
  94         .name           = "mci0_clk",
  95         .pmc_mask       = 1 << AT91CAP9_ID_MCI0,
  96         .type           = CLK_TYPE_PERIPHERAL,
  97 };
  98 static struct clk mmc1_clk = {
  99         .name           = "mci1_clk",
 100         .pmc_mask       = 1 << AT91CAP9_ID_MCI1,
 101         .type           = CLK_TYPE_PERIPHERAL,
 102 };
 103 static struct clk can_clk = {
 104         .name           = "can_clk",
 105         .pmc_mask       = 1 << AT91CAP9_ID_CAN,
 106         .type           = CLK_TYPE_PERIPHERAL,
 107 };
 108 static struct clk twi_clk = {
 109         .name           = "twi_clk",
 110         .pmc_mask       = 1 << AT91CAP9_ID_TWI,
 111         .type           = CLK_TYPE_PERIPHERAL,
 112 };
 113 static struct clk spi0_clk = {
 114         .name           = "spi0_clk",
 115         .pmc_mask       = 1 << AT91CAP9_ID_SPI0,
 116         .type           = CLK_TYPE_PERIPHERAL,
 117 };
 118 static struct clk spi1_clk = {
 119         .name           = "spi1_clk",
 120         .pmc_mask       = 1 << AT91CAP9_ID_SPI1,
 121         .type           = CLK_TYPE_PERIPHERAL,
 122 };
 123 static struct clk ssc0_clk = {
 124         .name           = "ssc0_clk",
 125         .pmc_mask       = 1 << AT91CAP9_ID_SSC0,
 126         .type           = CLK_TYPE_PERIPHERAL,
 127 };
 128 static struct clk ssc1_clk = {
 129         .name           = "ssc1_clk",
 130         .pmc_mask       = 1 << AT91CAP9_ID_SSC1,
 131         .type           = CLK_TYPE_PERIPHERAL,
 132 };
 133 static struct clk ac97_clk = {
 134         .name           = "ac97_clk",
 135         .pmc_mask       = 1 << AT91CAP9_ID_AC97C,
 136         .type           = CLK_TYPE_PERIPHERAL,
 137 };
 138 static struct clk tcb_clk = {
 139         .name           = "tcb_clk",
 140         .pmc_mask       = 1 << AT91CAP9_ID_TCB,
 141         .type           = CLK_TYPE_PERIPHERAL,
 142 };
 143 static struct clk pwm_clk = {
 144         .name           = "pwm_clk",
 145         .pmc_mask       = 1 << AT91CAP9_ID_PWMC,
 146         .type           = CLK_TYPE_PERIPHERAL,
 147 };
 148 static struct clk macb_clk = {
 149         .name           = "macb_clk",
 150         .pmc_mask       = 1 << AT91CAP9_ID_EMAC,
 151         .type           = CLK_TYPE_PERIPHERAL,
 152 };
 153 static struct clk aestdes_clk = {
 154         .name           = "aestdes_clk",
 155         .pmc_mask       = 1 << AT91CAP9_ID_AESTDES,
 156         .type           = CLK_TYPE_PERIPHERAL,
 157 };
 158 static struct clk adc_clk = {
 159         .name           = "adc_clk",
 160         .pmc_mask       = 1 << AT91CAP9_ID_ADC,
 161         .type           = CLK_TYPE_PERIPHERAL,
 162 };
 163 static struct clk isi_clk = {
 164         .name           = "isi_clk",
 165         .pmc_mask       = 1 << AT91CAP9_ID_ISI,
 166         .type           = CLK_TYPE_PERIPHERAL,
 167 };
 168 static struct clk lcdc_clk = {
 169         .name           = "lcdc_clk",
 170         .pmc_mask       = 1 << AT91CAP9_ID_LCDC,
 171         .type           = CLK_TYPE_PERIPHERAL,
 172 };
 173 static struct clk dma_clk = {
 174         .name           = "dma_clk",
 175         .pmc_mask       = 1 << AT91CAP9_ID_DMA,
 176         .type           = CLK_TYPE_PERIPHERAL,
 177 };
 178 static struct clk udphs_clk = {
 179         .name           = "udphs_clk",
 180         .pmc_mask       = 1 << AT91CAP9_ID_UDPHS,
 181         .type           = CLK_TYPE_PERIPHERAL,
 182 };
 183 static struct clk ohci_clk = {
 184         .name           = "ohci_clk",
 185         .pmc_mask       = 1 << AT91CAP9_ID_UHP,
 186         .type           = CLK_TYPE_PERIPHERAL,
 187 };
 188
 189 static struct clk *periph_clocks[] __initdata = {
 190         &pioABCD_clk,
 191         &mpb0_clk,
 192         &mpb1_clk,
 193         &mpb2_clk,
 194         &mpb3_clk,
 195         &mpb4_clk,
 196         &usart0_clk,
 197         &usart1_clk,
 198         &usart2_clk,
 199         &mmc0_clk,
 200         &mmc1_clk,
 201         &can_clk,
 202         &twi_clk,
 203         &spi0_clk,
 204         &spi1_clk,
 205         &ssc0_clk,
 206         &ssc1_clk,
 207         &ac97_clk,
 208         &tcb_clk,
 209         &pwm_clk,
 210         &macb_clk,
 211         &aestdes_clk,
 212         &adc_clk,
 213         &isi_clk,
 214         &lcdc_clk,
 215         &dma_clk,
 216         &udphs_clk,
 217         &ohci_clk,
 218         // irq0 .. irq1
 219 };
 220
 221 static struct clk_lookup periph_clocks_lookups[] = {
 222         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
 223         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
 224         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
 225         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
 226         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 227         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 228         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
 229         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 230         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 231 };
 232
 233 static struct clk_lookup usart_clocks_lookups[] = {
 234         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 235         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 236         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 237         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 238 };
 239
 240 /*
 241  * The four programmable clocks.
 242  * You must configure pin multiplexing to bring these signals out.
 243  */
 244 static struct clk pck0 = {
 245         .name           = "pck0",
 246         .pmc_mask       = AT91_PMC_PCK0,
 247         .type           = CLK_TYPE_PROGRAMMABLE,
 248         .id             = 0,
 249 };
 250 static struct clk pck1 = {
 251         .name           = "pck1",
 252         .pmc_mask       = AT91_PMC_PCK1,
 253         .type           = CLK_TYPE_PROGRAMMABLE,
 254         .id             = 1,
 255 };
 256 static struct clk pck2 = {
 257         .name           = "pck2",
 258         .pmc_mask       = AT91_PMC_PCK2,
 259         .type           = CLK_TYPE_PROGRAMMABLE,
 260         .id             = 2,
 261 };
 262 static struct clk pck3 = {
 263         .name           = "pck3",
 264         .pmc_mask       = AT91_PMC_PCK3,
 265         .type           = CLK_TYPE_PROGRAMMABLE,
 266         .id             = 3,
 267 };
 268
 269 static void __init at91cap9_register_clocks(void)
 270 {
 271         int i;
 272
 273         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 274                 clk_register(periph_clocks[i]);
 275
 276         clkdev_add_table(periph_clocks_lookups,
 277                          ARRAY_SIZE(periph_clocks_lookups));
 278         clkdev_add_table(usart_clocks_lookups,
 279                          ARRAY_SIZE(usart_clocks_lookups));
 280
 281         clk_register(&pck0);
 282         clk_register(&pck1);
 283         clk_register(&pck2);
 284         clk_register(&pck3);
 285 }
 286
 287 static struct clk_lookup console_clock_lookup;
 288
 289 void __init at91cap9_set_console_clock(int id)
 290 {
 291         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 292                 return;
 293
 294         console_clock_lookup.con_id = "usart";
 295         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 296         clkdev_add(&console_clock_lookup);
 297 }
 298
 299 /* --------------------------------------------------------------------
 300  *  GPIO
 301  * -------------------------------------------------------------------- */
 302
 303 static struct at91_gpio_bank at91cap9_gpio[] = {
 304         {
 305                 .id             = AT91CAP9_ID_PIOABCD,
 306                 .offset         = AT91_PIOA,
 307                 .clock          = &pioABCD_clk,
 308         }, {
 309                 .id             = AT91CAP9_ID_PIOABCD,
 310                 .offset         = AT91_PIOB,
 311                 .clock          = &pioABCD_clk,
 312         }, {
 313                 .id             = AT91CAP9_ID_PIOABCD,
 314                 .offset         = AT91_PIOC,
 315                 .clock          = &pioABCD_clk,
 316         }, {
 317                 .id             = AT91CAP9_ID_PIOABCD,
 318                 .offset         = AT91_PIOD,
 319                 .clock          = &pioABCD_clk,
 320         }
 321 };
 322
 323 static void at91cap9_reset(void)
 324 {
 325         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 326 }
 327
 328 static void at91cap9_poweroff(void)
 329 {
 330         at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 331 }
 332
 333
 334 /* --------------------------------------------------------------------
 335  *  AT91CAP9 processor initialization
 336  * -------------------------------------------------------------------- */
 337
 338 static void __init at91cap9_map_io(void)
 339 {
 340         iotable_init(at91cap9_sram_desc, ARRAY_SIZE(at91cap9_sram_desc));
 341 }
 342
 343 static void __init at91cap9_initialize(unsigned long main_clock)
 344         at91_arch_reset = at91cap9_reset;
 345         pm_power_off = at91cap9_poweroff;
 346         at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
 347
 348         /* Init clock subsystem */
 349         at91_clock_init(main_clock);
 350
 351         /* Register the processor-specific clocks */
 352         at91cap9_register_clocks();
 353
 354         /* Register GPIO subsystem */
 355         at91_gpio_init(at91cap9_gpio, 4);
 356
 357         /* Remember the silicon revision */
 358         if (cpu_is_at91cap9_revB())
 359                 system_rev = 0xB;
 360         else if (cpu_is_at91cap9_revC())
 361                 system_rev = 0xC;
 362 }
 363
 364 /* --------------------------------------------------------------------
 365  *  Interrupt initialization
 366  * -------------------------------------------------------------------- */
 367
 368 /*
 369  * The default interrupt priority levels (0 = lowest, 7 = highest).
 370  */
 371 static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
 372         7,      /* Advanced Interrupt Controller (FIQ) */
 373         7,      /* System Peripherals */
 374         1,      /* Parallel IO Controller A, B, C and D */
 375         0,      /* MP Block Peripheral 0 */
 376         0,      /* MP Block Peripheral 1 */
 377         0,      /* MP Block Peripheral 2 */
 378         0,      /* MP Block Peripheral 3 */
 379         0,      /* MP Block Peripheral 4 */
 380         5,      /* USART 0 */
 381         5,      /* USART 1 */
 382         5,      /* USART 2 */
 383         0,      /* Multimedia Card Interface 0 */
 384         0,      /* Multimedia Card Interface 1 */
 385         3,      /* CAN */
 386         6,      /* Two-Wire Interface */
 387         5,      /* Serial Peripheral Interface 0 */
 388         5,      /* Serial Peripheral Interface 1 */
 389         4,      /* Serial Synchronous Controller 0 */
 390         4,      /* Serial Synchronous Controller 1 */
 391         5,      /* AC97 Controller */
 392         0,      /* Timer Counter 0, 1 and 2 */
 393         0,      /* Pulse Width Modulation Controller */
 394         3,      /* Ethernet */
 395         0,      /* Advanced Encryption Standard, Triple DES*/
 396         0,      /* Analog-to-Digital Converter */
 397         0,      /* Image Sensor Interface */
 398         3,      /* LCD Controller */
 399         0,      /* DMA Controller */
 400         2,      /* USB Device Port */
 401         2,      /* USB Host port */
 402         0,      /* Advanced Interrupt Controller (IRQ0) */
 403         0,      /* Advanced Interrupt Controller (IRQ1) */
 404 };
 405
 406 struct at91_soc __initdata at91cap9_soc = {
 407         .map_io = at91cap9_map_io,
 408         .default_irq_priority = at91cap9_default_irq_priority,
 409         .init = at91cap9_initialize,
 410 };