2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2009, 2010 ARM Limited
17 * Author: Will Deacon <will.deacon@arm.com>
21 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
22 * using the CPU's debug registers.
24 #define pr_fmt(fmt) "hw-breakpoint: " fmt
26 #include <linux/errno.h>
27 #include <linux/hardirq.h>
28 #include <linux/perf_event.h>
29 #include <linux/hw_breakpoint.h>
30 #include <linux/smp.h>
32 #include <asm/cacheflush.h>
33 #include <asm/cputype.h>
34 #include <asm/current.h>
35 #include <asm/hw_breakpoint.h>
36 #include <asm/kdebug.h>
37 #include <asm/system.h>
38 #include <asm/traps.h>
40 /* Breakpoint currently in use for each BRP. */
41 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
43 /* Watchpoint currently in use for each WRP. */
44 static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
46 /* Number of BRP/WRP registers on this CPU. */
47 static int core_num_brps;
48 static int core_num_wrps;
50 /* Debug architecture version. */
53 /* Maximum supported watchpoint length. */
54 static u8 max_watchpoint_len;
56 #define READ_WB_REG_CASE(OP2, M, VAL) \
57 case ((OP2 << 4) + M): \
58 ARM_DBG_READ(c ## M, OP2, VAL); \
61 #define WRITE_WB_REG_CASE(OP2, M, VAL) \
62 case ((OP2 << 4) + M): \
63 ARM_DBG_WRITE(c ## M, OP2, VAL);\
66 #define GEN_READ_WB_REG_CASES(OP2, VAL) \
67 READ_WB_REG_CASE(OP2, 0, VAL); \
68 READ_WB_REG_CASE(OP2, 1, VAL); \
69 READ_WB_REG_CASE(OP2, 2, VAL); \
70 READ_WB_REG_CASE(OP2, 3, VAL); \
71 READ_WB_REG_CASE(OP2, 4, VAL); \
72 READ_WB_REG_CASE(OP2, 5, VAL); \
73 READ_WB_REG_CASE(OP2, 6, VAL); \
74 READ_WB_REG_CASE(OP2, 7, VAL); \
75 READ_WB_REG_CASE(OP2, 8, VAL); \
76 READ_WB_REG_CASE(OP2, 9, VAL); \
77 READ_WB_REG_CASE(OP2, 10, VAL); \
78 READ_WB_REG_CASE(OP2, 11, VAL); \
79 READ_WB_REG_CASE(OP2, 12, VAL); \
80 READ_WB_REG_CASE(OP2, 13, VAL); \
81 READ_WB_REG_CASE(OP2, 14, VAL); \
82 READ_WB_REG_CASE(OP2, 15, VAL)
84 #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \
85 WRITE_WB_REG_CASE(OP2, 0, VAL); \
86 WRITE_WB_REG_CASE(OP2, 1, VAL); \
87 WRITE_WB_REG_CASE(OP2, 2, VAL); \
88 WRITE_WB_REG_CASE(OP2, 3, VAL); \
89 WRITE_WB_REG_CASE(OP2, 4, VAL); \
90 WRITE_WB_REG_CASE(OP2, 5, VAL); \
91 WRITE_WB_REG_CASE(OP2, 6, VAL); \
92 WRITE_WB_REG_CASE(OP2, 7, VAL); \
93 WRITE_WB_REG_CASE(OP2, 8, VAL); \
94 WRITE_WB_REG_CASE(OP2, 9, VAL); \
95 WRITE_WB_REG_CASE(OP2, 10, VAL); \
96 WRITE_WB_REG_CASE(OP2, 11, VAL); \
97 WRITE_WB_REG_CASE(OP2, 12, VAL); \
98 WRITE_WB_REG_CASE(OP2, 13, VAL); \
99 WRITE_WB_REG_CASE(OP2, 14, VAL); \
100 WRITE_WB_REG_CASE(OP2, 15, VAL)
102 static u32 read_wb_reg(int n)
107 GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val);
108 GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val);
109 GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val);
110 GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val);
112 pr_warning("attempt to read from unknown breakpoint "
119 static void write_wb_reg(int n, u32 val)
122 GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val);
123 GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val);
124 GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val);
125 GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val);
127 pr_warning("attempt to write to unknown breakpoint "
133 /* Determine debug architecture. */
134 static u8 get_debug_arch(void)
138 /* Do we implement the extended CPUID interface? */
139 if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
140 pr_warning("CPUID feature registers not supported. "
141 "Assuming v6 debug is present.\n");
142 return ARM_DEBUG_ARCH_V6;
145 ARM_DBG_READ(c0, 0, didr);
146 return (didr >> 16) & 0xf;
149 u8 arch_get_debug_arch(void)
154 static int debug_arch_supported(void)
156 u8 arch = get_debug_arch();
158 /* We don't support the memory-mapped interface. */
159 return (arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14) ||
160 arch >= ARM_DEBUG_ARCH_V7_1;
163 /* Can we determine the watchpoint access type from the fsr? */
164 static int debug_exception_updates_fsr(void)
169 /* Determine number of WRP registers available. */
170 static int get_num_wrp_resources(void)
173 ARM_DBG_READ(c0, 0, didr);
174 return ((didr >> 28) & 0xf) + 1;
177 /* Determine number of BRP registers available. */
178 static int get_num_brp_resources(void)
181 ARM_DBG_READ(c0, 0, didr);
182 return ((didr >> 24) & 0xf) + 1;
185 /* Does this core support mismatch breakpoints? */
186 static int core_has_mismatch_brps(void)
188 return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 &&
189 get_num_brp_resources() > 1);
192 /* Determine number of usable WRPs available. */
193 static int get_num_wrps(void)
196 * On debug architectures prior to 7.1, when a watchpoint fires, the
197 * only way to work out which watchpoint it was is by disassembling
198 * the faulting instruction and working out the address of the memory
201 * Furthermore, we can only do this if the watchpoint was precise
202 * since imprecise watchpoints prevent us from calculating register
205 * Providing we have more than 1 breakpoint register, we only report
206 * a single watchpoint register for the time being. This way, we always
207 * know which watchpoint fired. In the future we can either add a
208 * disassembler and address generation emulator, or we can insert a
209 * check to see if the DFAR is set on watchpoint exception entry
210 * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows
211 * that it is set on some implementations].
213 if (get_debug_arch() < ARM_DEBUG_ARCH_V7_1)
216 return get_num_wrp_resources();
219 /* Determine number of usable BRPs available. */
220 static int get_num_brps(void)
222 int brps = get_num_brp_resources();
223 return core_has_mismatch_brps() ? brps - 1 : brps;
227 * In order to access the breakpoint/watchpoint control registers,
228 * we must be running in debug monitor mode. Unfortunately, we can
229 * be put into halting debug mode at any time by an external debugger
230 * but there is nothing we can do to prevent that.
232 static int enable_monitor_mode(void)
237 ARM_DBG_READ(c1, 0, dscr);
239 /* Ensure that halting mode is disabled. */
240 if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN,
241 "halting debug mode enabled. Unable to access hardware resources.\n")) {
246 /* If monitor mode is already enabled, just return. */
247 if (dscr & ARM_DSCR_MDBGEN)
250 /* Write to the corresponding DSCR. */
251 switch (get_debug_arch()) {
252 case ARM_DEBUG_ARCH_V6:
253 case ARM_DEBUG_ARCH_V6_1:
254 ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN));
256 case ARM_DEBUG_ARCH_V7_ECP14:
257 case ARM_DEBUG_ARCH_V7_1:
258 ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN));
265 /* Check that the write made it through. */
266 ARM_DBG_READ(c1, 0, dscr);
267 if (!(dscr & ARM_DSCR_MDBGEN))
274 int hw_breakpoint_slots(int type)
276 if (!debug_arch_supported())
280 * We can be called early, so don't rely on
281 * our static variables being initialised.
285 return get_num_brps();
287 return get_num_wrps();
289 pr_warning("unknown slot type: %d\n", type);
295 * Check if 8-bit byte-address select is available.
296 * This clobbers WRP 0.
298 static u8 get_max_wp_len(void)
301 struct arch_hw_breakpoint_ctrl ctrl;
304 if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
307 memset(&ctrl, 0, sizeof(ctrl));
308 ctrl.len = ARM_BREAKPOINT_LEN_8;
309 ctrl_reg = encode_ctrl_reg(ctrl);
311 write_wb_reg(ARM_BASE_WVR, 0);
312 write_wb_reg(ARM_BASE_WCR, ctrl_reg);
313 if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg)
320 u8 arch_get_max_wp_len(void)
322 return max_watchpoint_len;
326 * Install a perf counter breakpoint.
328 int arch_install_hw_breakpoint(struct perf_event *bp)
330 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
331 struct perf_event **slot, **slots;
332 int i, max_slots, ctrl_base, val_base, ret = 0;
335 /* Ensure that we are in monitor mode and halting mode is disabled. */
336 ret = enable_monitor_mode();
340 addr = info->address;
341 ctrl = encode_ctrl_reg(info->ctrl) | 0x1;
343 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
345 ctrl_base = ARM_BASE_BCR;
346 val_base = ARM_BASE_BVR;
347 slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
348 max_slots = core_num_brps;
351 ctrl_base = ARM_BASE_WCR;
352 val_base = ARM_BASE_WVR;
353 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
354 max_slots = core_num_wrps;
357 for (i = 0; i < max_slots; ++i) {
366 if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n")) {
371 /* Override the breakpoint data with the step data. */
372 if (info->step_ctrl.enabled) {
373 addr = info->trigger & ~0x3;
374 ctrl = encode_ctrl_reg(info->step_ctrl);
375 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE) {
377 ctrl_base = ARM_BASE_BCR + core_num_brps;
378 val_base = ARM_BASE_BVR + core_num_brps;
382 /* Setup the address register. */
383 write_wb_reg(val_base + i, addr);
385 /* Setup the control register. */
386 write_wb_reg(ctrl_base + i, ctrl);
392 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
394 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
395 struct perf_event **slot, **slots;
396 int i, max_slots, base;
398 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
401 slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
402 max_slots = core_num_brps;
406 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
407 max_slots = core_num_wrps;
410 /* Remove the breakpoint. */
411 for (i = 0; i < max_slots; ++i) {
420 if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n"))
423 /* Ensure that we disable the mismatch breakpoint. */
424 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE &&
425 info->step_ctrl.enabled) {
427 base = ARM_BASE_BCR + core_num_brps;
430 /* Reset the control register. */
431 write_wb_reg(base + i, 0);
434 static int get_hbp_len(u8 hbp_len)
436 unsigned int len_in_bytes = 0;
439 case ARM_BREAKPOINT_LEN_1:
442 case ARM_BREAKPOINT_LEN_2:
445 case ARM_BREAKPOINT_LEN_4:
448 case ARM_BREAKPOINT_LEN_8:
457 * Check whether bp virtual address is in kernel space.
459 int arch_check_bp_in_kernelspace(struct perf_event *bp)
463 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
466 len = get_hbp_len(info->ctrl.len);
468 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
472 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
473 * Hopefully this will disappear when ptrace can bypass the conversion
474 * to generic breakpoint descriptions.
476 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
477 int *gen_len, int *gen_type)
481 case ARM_BREAKPOINT_EXECUTE:
482 *gen_type = HW_BREAKPOINT_X;
484 case ARM_BREAKPOINT_LOAD:
485 *gen_type = HW_BREAKPOINT_R;
487 case ARM_BREAKPOINT_STORE:
488 *gen_type = HW_BREAKPOINT_W;
490 case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
491 *gen_type = HW_BREAKPOINT_RW;
499 case ARM_BREAKPOINT_LEN_1:
500 *gen_len = HW_BREAKPOINT_LEN_1;
502 case ARM_BREAKPOINT_LEN_2:
503 *gen_len = HW_BREAKPOINT_LEN_2;
505 case ARM_BREAKPOINT_LEN_4:
506 *gen_len = HW_BREAKPOINT_LEN_4;
508 case ARM_BREAKPOINT_LEN_8:
509 *gen_len = HW_BREAKPOINT_LEN_8;
519 * Construct an arch_hw_breakpoint from a perf_event.
521 static int arch_build_bp_info(struct perf_event *bp)
523 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
526 switch (bp->attr.bp_type) {
527 case HW_BREAKPOINT_X:
528 info->ctrl.type = ARM_BREAKPOINT_EXECUTE;
530 case HW_BREAKPOINT_R:
531 info->ctrl.type = ARM_BREAKPOINT_LOAD;
533 case HW_BREAKPOINT_W:
534 info->ctrl.type = ARM_BREAKPOINT_STORE;
536 case HW_BREAKPOINT_RW:
537 info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
544 switch (bp->attr.bp_len) {
545 case HW_BREAKPOINT_LEN_1:
546 info->ctrl.len = ARM_BREAKPOINT_LEN_1;
548 case HW_BREAKPOINT_LEN_2:
549 info->ctrl.len = ARM_BREAKPOINT_LEN_2;
551 case HW_BREAKPOINT_LEN_4:
552 info->ctrl.len = ARM_BREAKPOINT_LEN_4;
554 case HW_BREAKPOINT_LEN_8:
555 info->ctrl.len = ARM_BREAKPOINT_LEN_8;
556 if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE)
557 && max_watchpoint_len >= 8)
564 * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes.
565 * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported
566 * by the hardware and must be aligned to the appropriate number of
569 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE &&
570 info->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
571 info->ctrl.len != ARM_BREAKPOINT_LEN_4)
575 info->address = bp->attr.bp_addr;
578 info->ctrl.privilege = ARM_BREAKPOINT_USER;
579 if (arch_check_bp_in_kernelspace(bp))
580 info->ctrl.privilege |= ARM_BREAKPOINT_PRIV;
583 info->ctrl.enabled = !bp->attr.disabled;
586 info->ctrl.mismatch = 0;
592 * Validate the arch-specific HW Breakpoint register settings.
594 int arch_validate_hwbkpt_settings(struct perf_event *bp)
596 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
598 u32 offset, alignment_mask = 0x3;
600 /* Build the arch_hw_breakpoint. */
601 ret = arch_build_bp_info(bp);
605 /* Check address alignment. */
606 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
607 alignment_mask = 0x7;
608 offset = info->address & alignment_mask;
614 /* Allow single byte watchpoint. */
615 if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
618 /* Allow halfword watchpoints and breakpoints. */
619 if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
626 info->address &= ~alignment_mask;
627 info->ctrl.len <<= offset;
629 if (!bp->overflow_handler) {
631 * Mismatch breakpoints are required for single-stepping
634 if (!core_has_mismatch_brps())
637 /* We don't allow mismatch breakpoints in kernel space. */
638 if (arch_check_bp_in_kernelspace(bp))
642 * Per-cpu breakpoints are not supported by our stepping
645 if (!bp->hw.bp_target)
649 * We only support specific access types if the fsr
652 if (!debug_exception_updates_fsr() &&
653 (info->ctrl.type == ARM_BREAKPOINT_LOAD ||
654 info->ctrl.type == ARM_BREAKPOINT_STORE))
663 * Enable/disable single-stepping over the breakpoint bp at address addr.
665 static void enable_single_step(struct perf_event *bp, u32 addr)
667 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
669 arch_uninstall_hw_breakpoint(bp);
670 info->step_ctrl.mismatch = 1;
671 info->step_ctrl.len = ARM_BREAKPOINT_LEN_4;
672 info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE;
673 info->step_ctrl.privilege = info->ctrl.privilege;
674 info->step_ctrl.enabled = 1;
675 info->trigger = addr;
676 arch_install_hw_breakpoint(bp);
679 static void disable_single_step(struct perf_event *bp)
681 arch_uninstall_hw_breakpoint(bp);
682 counter_arch_bp(bp)->step_ctrl.enabled = 0;
683 arch_install_hw_breakpoint(bp);
686 static void watchpoint_handler(unsigned long addr, unsigned int fsr,
687 struct pt_regs *regs)
690 u32 val, ctrl_reg, alignment_mask;
691 struct perf_event *wp, **slots;
692 struct arch_hw_breakpoint *info;
693 struct arch_hw_breakpoint_ctrl ctrl;
695 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
697 for (i = 0; i < core_num_wrps; ++i) {
705 info = counter_arch_bp(wp);
707 * The DFAR is an unknown value on debug architectures prior
708 * to 7.1. Since we only allow a single watchpoint on these
709 * older CPUs, we can set the trigger to the lowest possible
712 if (debug_arch < ARM_DEBUG_ARCH_V7_1) {
714 info->trigger = wp->attr.bp_addr;
716 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
717 alignment_mask = 0x7;
719 alignment_mask = 0x3;
721 /* Check if the watchpoint value matches. */
722 val = read_wb_reg(ARM_BASE_WVR + i);
723 if (val != (addr & ~alignment_mask))
726 /* Possible match, check the byte address select. */
727 ctrl_reg = read_wb_reg(ARM_BASE_WCR + i);
728 decode_ctrl_reg(ctrl_reg, &ctrl);
729 if (!((1 << (addr & alignment_mask)) & ctrl.len))
732 /* Check that the access type matches. */
733 if (debug_exception_updates_fsr()) {
734 access = (fsr & ARM_FSR_ACCESS_MASK) ?
735 HW_BREAKPOINT_W : HW_BREAKPOINT_R;
736 if (!(access & hw_breakpoint_type(wp)))
740 /* We have a winner. */
741 info->trigger = addr;
744 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
745 perf_bp_event(wp, regs);
748 * If no overflow handler is present, insert a temporary
749 * mismatch breakpoint so we can single-step over the
750 * watchpoint trigger.
752 if (!wp->overflow_handler)
753 enable_single_step(wp, instruction_pointer(regs));
760 static void watchpoint_single_step_handler(unsigned long pc)
763 struct perf_event *wp, **slots;
764 struct arch_hw_breakpoint *info;
766 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
768 for (i = 0; i < core_num_wrps; ++i) {
776 info = counter_arch_bp(wp);
777 if (!info->step_ctrl.enabled)
781 * Restore the original watchpoint if we've completed the
784 if (info->trigger != pc)
785 disable_single_step(wp);
792 static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
795 u32 ctrl_reg, val, addr;
796 struct perf_event *bp, **slots;
797 struct arch_hw_breakpoint *info;
798 struct arch_hw_breakpoint_ctrl ctrl;
800 slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
802 /* The exception entry code places the amended lr in the PC. */
805 /* Check the currently installed breakpoints first. */
806 for (i = 0; i < core_num_brps; ++i) {
814 info = counter_arch_bp(bp);
816 /* Check if the breakpoint value matches. */
817 val = read_wb_reg(ARM_BASE_BVR + i);
818 if (val != (addr & ~0x3))
821 /* Possible match, check the byte address select to confirm. */
822 ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
823 decode_ctrl_reg(ctrl_reg, &ctrl);
824 if ((1 << (addr & 0x3)) & ctrl.len) {
825 info->trigger = addr;
826 pr_debug("breakpoint fired: address = 0x%x\n", addr);
827 perf_bp_event(bp, regs);
828 if (!bp->overflow_handler)
829 enable_single_step(bp, addr);
834 /* If we're stepping a breakpoint, it can now be restored. */
835 if (info->step_ctrl.enabled)
836 disable_single_step(bp);
841 /* Handle any pending watchpoint single-step breakpoints. */
842 watchpoint_single_step_handler(addr);
846 * Called from either the Data Abort Handler [watchpoint] or the
847 * Prefetch Abort Handler [breakpoint] with interrupts disabled.
849 static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
850 struct pt_regs *regs)
857 if (interrupts_enabled(regs))
860 /* We only handle watchpoints and hardware breakpoints. */
861 ARM_DBG_READ(c1, 0, dscr);
863 /* Perform perf callbacks. */
864 switch (ARM_DSCR_MOE(dscr)) {
865 case ARM_ENTRY_BREAKPOINT:
866 breakpoint_handler(addr, regs);
868 case ARM_ENTRY_ASYNC_WATCHPOINT:
869 WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
870 case ARM_ENTRY_SYNC_WATCHPOINT:
871 watchpoint_handler(addr, fsr, regs);
874 ret = 1; /* Unhandled fault. */
883 * One-time initialisation.
885 static cpumask_t debug_err_mask;
887 static int debug_reg_trap(struct pt_regs *regs, unsigned int instr)
889 int cpu = smp_processor_id();
891 pr_warning("Debug register access (0x%x) caused undefined instruction on CPU %d\n",
894 /* Set the error flag for this CPU and skip the faulting instruction. */
895 cpumask_set_cpu(cpu, &debug_err_mask);
896 instruction_pointer(regs) += 4;
900 static struct undef_hook debug_reg_hook = {
901 .instr_mask = 0x0fe80f10,
902 .instr_val = 0x0e000e10,
903 .fn = debug_reg_trap,
906 static void reset_ctrl_regs(void *unused)
908 int i, raw_num_brps, err = 0, cpu = smp_processor_id();
912 * v7 debug contains save and restore registers so that debug state
913 * can be maintained across low-power modes without leaving the debug
914 * logic powered up. It is IMPLEMENTATION DEFINED whether we can access
915 * the debug registers out of reset, so we must unlock the OS Lock
916 * Access Register to avoid taking undefined instruction exceptions
919 switch (debug_arch) {
920 case ARM_DEBUG_ARCH_V6:
921 case ARM_DEBUG_ARCH_V6_1:
922 /* ARMv6 cores just need to reset the registers. */
924 case ARM_DEBUG_ARCH_V7_ECP14:
926 * Ensure sticky power-down is clear (i.e. debug logic is
929 asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power));
930 if ((dbg_power & 0x1) == 0)
933 case ARM_DEBUG_ARCH_V7_1:
935 * Ensure the OS double lock is clear.
937 asm volatile("mrc p14, 0, %0, c1, c3, 4" : "=r" (dbg_power));
938 if ((dbg_power & 0x1) == 1)
944 pr_warning("CPU %d debug is powered down!\n", cpu);
945 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
950 * Unconditionally clear the lock by writing a value
951 * other than 0xC5ACCE55 to the access register.
953 asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0));
957 * Clear any configured vector-catch events before
958 * enabling monitor mode.
960 asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0));
964 if (enable_monitor_mode())
967 /* We must also reset any reserved registers. */
968 raw_num_brps = get_num_brp_resources();
969 for (i = 0; i < raw_num_brps; ++i) {
970 write_wb_reg(ARM_BASE_BCR + i, 0UL);
971 write_wb_reg(ARM_BASE_BVR + i, 0UL);
974 for (i = 0; i < core_num_wrps; ++i) {
975 write_wb_reg(ARM_BASE_WCR + i, 0UL);
976 write_wb_reg(ARM_BASE_WVR + i, 0UL);
980 static int __cpuinit dbg_reset_notify(struct notifier_block *self,
981 unsigned long action, void *cpu)
983 if (action == CPU_ONLINE)
984 smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1);
989 static struct notifier_block __cpuinitdata dbg_reset_nb = {
990 .notifier_call = dbg_reset_notify,
993 static int __init arch_hw_breakpoint_init(void)
997 debug_arch = get_debug_arch();
999 if (!debug_arch_supported()) {
1000 pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
1004 /* Determine how many BRPs/WRPs are available. */
1005 core_num_brps = get_num_brps();
1006 core_num_wrps = get_num_wrps();
1009 * We need to tread carefully here because DBGSWENABLE may be
1010 * driven low on this core and there isn't an architected way to
1013 register_undef_hook(&debug_reg_hook);
1016 * Reset the breakpoint resources. We assume that a halting
1017 * debugger will leave the world in a nice state for us.
1019 on_each_cpu(reset_ctrl_regs, NULL, 1);
1020 unregister_undef_hook(&debug_reg_hook);
1021 if (!cpumask_empty(&debug_err_mask)) {
1027 pr_info("found %d " "%s" "breakpoint and %d watchpoint registers.\n",
1028 core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " :
1031 ARM_DBG_READ(c1, 0, dscr);
1032 if (dscr & ARM_DSCR_HDBGEN) {
1033 max_watchpoint_len = 4;
1034 pr_warning("halting debug mode enabled. Assuming maximum watchpoint size of %u bytes.\n",
1035 max_watchpoint_len);
1037 /* Work out the maximum supported watchpoint length. */
1038 max_watchpoint_len = get_max_wp_len();
1039 pr_info("maximum watchpoint size is %u bytes.\n",
1040 max_watchpoint_len);
1043 /* Register debug fault handler. */
1044 hook_fault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
1045 "watchpoint debug exception");
1046 hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
1047 "breakpoint debug exception");
1049 /* Register hotplug notifier. */
1050 register_cpu_notifier(&dbg_reset_nb);
1053 arch_initcall(arch_hw_breakpoint_init);
1055 void hw_breakpoint_pmu_read(struct perf_event *bp)
1060 * Dummy function to register with die_notifier.
1062 int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
1063 unsigned long val, void *data)