2 * arch/arm/include/asm/pgtable-3level.h
4 * Copyright (C) 2011 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #ifndef _ASM_PGTABLE_3LEVEL_H
21 #define _ASM_PGTABLE_3LEVEL_H
24 * With LPAE, there are 3 levels of page tables. Each level has 512 entries of
25 * 8 bytes each, occupying a 4K page. The first level table covers a range of
26 * 512GB, each entry representing 1GB. Since we are limited to 4GB input
27 * address range, only 4 entries in the PGD are used.
29 * There are enough spare bits in a page table entry for the kernel specific
32 #define PTRS_PER_PTE 512
33 #define PTRS_PER_PMD 512
34 #define PTRS_PER_PGD 4
36 #define PTE_HWTABLE_PTRS (PTRS_PER_PTE)
37 #define PTE_HWTABLE_OFF (0)
38 #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64))
41 * PGDIR_SHIFT determines the size a top-level page table entry can map.
43 #define PGDIR_SHIFT 30
46 * PMD_SHIFT determines the size a middle-level page table entry can map.
50 #define PMD_SIZE (1UL << PMD_SHIFT)
51 #define PMD_MASK (~(PMD_SIZE-1))
52 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
53 #define PGDIR_MASK (~(PGDIR_SIZE-1))
56 * section address mask and size definitions.
58 #define SECTION_SHIFT 21
59 #define SECTION_SIZE (1UL << SECTION_SHIFT)
60 #define SECTION_MASK (~(SECTION_SIZE-1))
62 #define USER_PTRS_PER_PGD (PAGE_OFFSET / PGDIR_SIZE)
65 * Hugetlb definitions.
67 #define HPAGE_SHIFT PMD_SHIFT
68 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
69 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
70 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
73 * "Linux" PTE definitions for LPAE.
75 * These bits overlap with the hardware bits but the naming is preserved for
76 * consistency with the classic page table format.
78 #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */
79 #define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Present */
80 #define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */
81 #define L_PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */
82 #define L_PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */
83 #define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
84 #define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */
85 #define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
86 #define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */
87 #define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */
88 #define L_PTE_DIRTY (_AT(pteval_t, 1) << 55) /* unused */
89 #define L_PTE_SPECIAL (_AT(pteval_t, 1) << 56) /* unused */
91 #define PMD_SECT_DIRTY (_AT(pmdval_t, 1) << 55)
92 #define PMD_SECT_SPLITTING (_AT(pmdval_t, 1) << 57)
95 * To be used in assembly code with the upper page attributes.
97 #define L_PTE_XN_HIGH (1 << (54 - 32))
98 #define L_PTE_DIRTY_HIGH (1 << (55 - 32))
101 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
103 #define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */
104 #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
105 #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */
106 #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */
107 #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */
108 #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */
109 #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */
110 #define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
111 #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */
112 #define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2)
115 * Software PGD flags.
117 #define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */
121 #define pud_none(pud) (!pud_val(pud))
122 #define pud_bad(pud) (!(pud_val(pud) & 2))
123 #define pud_present(pud) (pud_val(pud))
125 #define pud_clear(pudp) \
128 clean_pmd_entry(pudp); \
131 #define set_pud(pudp, pud) \
134 flush_pmd_entry(pudp); \
137 static inline pmd_t *pud_page_vaddr(pud_t pud)
139 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
142 /* Find an entry in the second-level page table.. */
143 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
144 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
146 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
149 #define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
151 #define copy_pmd(pmdpd,pmdps) \
154 flush_pmd_entry(pmdpd); \
157 #define pmd_clear(pmdp) \
160 clean_pmd_entry(pmdp); \
164 * For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes
165 * that are written to a page table but not for ptes created with mk_pte.
167 * In hugetlb_no_page, a new huge pte (new_pte) is generated and passed to
168 * hugetlb_cow, where it is compared with an entry in a page table.
169 * This comparison test fails erroneously leading ultimately to a memory leak.
171 * To correct this behaviour, we mask off PTE_EXT_NG for any pte that is
172 * present before running the comparison.
174 #define __HAVE_ARCH_PTE_SAME
175 #define pte_same(pte_a,pte_b) ((pte_present(pte_a) ? pte_val(pte_a) & ~PTE_EXT_NG \
177 == (pte_present(pte_b) ? pte_val(pte_b) & ~PTE_EXT_NG \
180 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
182 #define pte_huge(pte) ((pte_val(pte) & PMD_TYPE_MASK) == PMD_TYPE_SECT)
184 #define pte_mkhuge(pte) (__pte((pte_val(pte) & ~PMD_TYPE_MASK) | PMD_TYPE_SECT))
187 #define pmd_present(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) != PMD_TYPE_FAULT)
188 #define pmd_young(pmd) (pmd_val(pmd) & PMD_SECT_AF)
190 #define __HAVE_ARCH_PMD_WRITE
191 #define pmd_write(pmd) (!(pmd_val(pmd) & PMD_SECT_RDONLY))
193 #define pmd_hugewillfault(pmd) ( !pmd_young(pmd) || !pmd_write(pmd) )
194 #define pmd_thp_or_huge(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == PMD_TYPE_SECT)
196 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
197 #define pmd_trans_huge(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == PMD_TYPE_SECT)
198 #define pmd_trans_splitting(pmd) (pmd_val(pmd) & PMD_SECT_SPLITTING)
201 #define PMD_BIT_FUNC(fn,op) \
202 static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
204 PMD_BIT_FUNC(wrprotect, |= PMD_SECT_RDONLY);
205 PMD_BIT_FUNC(mkold, &= ~PMD_SECT_AF);
206 PMD_BIT_FUNC(mksplitting, |= PMD_SECT_SPLITTING);
207 PMD_BIT_FUNC(mkwrite, &= ~PMD_SECT_RDONLY);
208 PMD_BIT_FUNC(mkdirty, |= PMD_SECT_DIRTY);
209 PMD_BIT_FUNC(mkyoung, |= PMD_SECT_AF);
210 PMD_BIT_FUNC(mknotpresent, &= ~PMD_TYPE_MASK);
212 #define pmd_mkhuge(pmd) (__pmd((pmd_val(pmd) & ~PMD_TYPE_MASK) | PMD_TYPE_SECT))
214 #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
215 #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
216 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
218 #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
220 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
222 const pmdval_t mask = PMD_SECT_USER | PMD_SECT_XN | PMD_SECT_RDONLY;
223 pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
227 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
228 pmd_t *pmdp, pmd_t pmd)
230 BUG_ON(addr >= TASK_SIZE);
231 *pmdp = __pmd(pmd_val(pmd) | PMD_SECT_nG);
232 flush_pmd_entry(pmdp);
235 static inline int has_transparent_hugepage(void)
240 #endif /* __ASSEMBLY__ */
242 #endif /* _ASM_PGTABLE_3LEVEL_H */