arch/arm/include/asm/cputype.h

   1 #ifndef __ASM_ARM_CPUTYPE_H
   2 #define __ASM_ARM_CPUTYPE_H
   3
   4 #include <linux/stringify.h>
   5
   6 #define CPUID_ID        0
   7 #define CPUID_CACHETYPE 1
   8 #define CPUID_TCM       2
   9 #define CPUID_TLBTYPE   3
  10
  11 #define CPUID_EXT_PFR0  "c1, 0"
  12 #define CPUID_EXT_PFR1  "c1, 1"
  13 #define CPUID_EXT_DFR0  "c1, 2"
  14 #define CPUID_EXT_AFR0  "c1, 3"
  15 #define CPUID_EXT_MMFR0 "c1, 4"
  16 #define CPUID_EXT_MMFR1 "c1, 5"
  17 #define CPUID_EXT_MMFR2 "c1, 6"
  18 #define CPUID_EXT_MMFR3 "c1, 7"
  19 #define CPUID_EXT_ISAR0 "c2, 0"
  20 #define CPUID_EXT_ISAR1 "c2, 1"
  21 #define CPUID_EXT_ISAR2 "c2, 2"
  22 #define CPUID_EXT_ISAR3 "c2, 3"
  23 #define CPUID_EXT_ISAR4 "c2, 4"
  24 #define CPUID_EXT_ISAR5 "c2, 5"
  25
  26 extern unsigned int processor_id;
  27
  28 #ifdef CONFIG_CPU_CP15
  29 #define read_cpuid(reg)                                                 \
  30         ({                                                              \
  31                 unsigned int __val;                                     \
  32                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
  33                     : "=r" (__val)                                      \
  34                     :                                                   \
  35                     : "cc");                                            \
  36                 __val;                                                  \
  37         })
  38 #define read_cpuid_ext(ext_reg)                                         \
  39         ({                                                              \
  40                 unsigned int __val;                                     \
  41                 asm("mrc        p15, 0, %0, c0, " ext_reg               \
  42                     : "=r" (__val)                                      \
  43                     :                                                   \
  44                     : "cc");                                            \
  45                 __val;                                                  \
  46         })
  47 #else
  48 #define read_cpuid(reg) (processor_id)
  49 #define read_cpuid_ext(reg) 0
  50 #endif
  51
  52 /*
  53  * The CPU ID never changes at run time, so we might as well tell the
  54  * compiler that it's constant.  Use this function to read the CPU ID
  55  * rather than directly reading processor_id or read_cpuid() directly.
  56  */
  57 static inline unsigned int __attribute_const__ read_cpuid_id(void)
  58 {
  59         return read_cpuid(CPUID_ID);
  60 }
  61
  62 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
  63 {
  64         return read_cpuid(CPUID_CACHETYPE);
  65 }
  66
  67 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
  68 {
  69         return read_cpuid(CPUID_TCM);
  70 }
  71
  72 /*
  73  * Intel's XScale3 core supports some v6 features (supersections, L2)
  74  * but advertises itself as v5 as it does not support the v6 ISA.  For
  75  * this reason, we need a way to explicitly test for this type of CPU.
  76  */
  77 #ifndef CONFIG_CPU_XSC3
  78 #define cpu_is_xsc3()   0
  79 #else
  80 static inline int cpu_is_xsc3(void)
  81 {
  82         unsigned int id;
  83         id = read_cpuid_id() & 0xffffe000;
  84         /* It covers both Intel ID and Marvell ID */
  85         if ((id == 0x69056000) || (id == 0x56056000))
  86                 return 1;
  87
  88         return 0;
  89 }
  90 #endif
  91
  92 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
  93 #define cpu_is_xscale() 0
  94 #else
  95 #define cpu_is_xscale() 1
  96 #endif
  97
  98 #endif