ARM: 8634/1: hw_breakpoint: blacklist Scorpion CPUs
[pandora-kernel.git] / arch / arm / include / asm / cputype.h
1 #ifndef __ASM_ARM_CPUTYPE_H
2 #define __ASM_ARM_CPUTYPE_H
3
4 #include <linux/stringify.h>
5 #include <linux/kernel.h>
6
7 #define CPUID_ID        0
8 #define CPUID_CACHETYPE 1
9 #define CPUID_TCM       2
10 #define CPUID_TLBTYPE   3
11 #define CPUID_MPIDR     5
12
13 #define CPUID_EXT_PFR0  "c1, 0"
14 #define CPUID_EXT_PFR1  "c1, 1"
15 #define CPUID_EXT_DFR0  "c1, 2"
16 #define CPUID_EXT_AFR0  "c1, 3"
17 #define CPUID_EXT_MMFR0 "c1, 4"
18 #define CPUID_EXT_MMFR1 "c1, 5"
19 #define CPUID_EXT_MMFR2 "c1, 6"
20 #define CPUID_EXT_MMFR3 "c1, 7"
21 #define CPUID_EXT_ISAR0 "c2, 0"
22 #define CPUID_EXT_ISAR1 "c2, 1"
23 #define CPUID_EXT_ISAR2 "c2, 2"
24 #define CPUID_EXT_ISAR3 "c2, 3"
25 #define CPUID_EXT_ISAR4 "c2, 4"
26 #define CPUID_EXT_ISAR5 "c2, 5"
27
28 /* Qualcomm implemented cores */
29 #define ARM_CPU_PART_SCORPION           0x510002d0
30
31 extern unsigned int processor_id;
32
33 #ifdef CONFIG_CPU_CP15
34 #define read_cpuid(reg)                                                 \
35         ({                                                              \
36                 unsigned int __val;                                     \
37                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
38                     : "=r" (__val)                                      \
39                     :                                                   \
40                     : "cc");                                            \
41                 __val;                                                  \
42         })
43 #define read_cpuid_ext(ext_reg)                                         \
44         ({                                                              \
45                 unsigned int __val;                                     \
46                 asm("mrc        p15, 0, %0, c0, " ext_reg               \
47                     : "=r" (__val)                                      \
48                     :                                                   \
49                     : "cc");                                            \
50                 __val;                                                  \
51         })
52 #else
53 #define read_cpuid(reg) (processor_id)
54 #define read_cpuid_ext(reg) 0
55 #endif
56
57 /*
58  * The CPU ID never changes at run time, so we might as well tell the
59  * compiler that it's constant.  Use this function to read the CPU ID
60  * rather than directly reading processor_id or read_cpuid() directly.
61  */
62 static inline unsigned int __attribute_const__ read_cpuid_id(void)
63 {
64         return read_cpuid(CPUID_ID);
65 }
66
67 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
68 {
69         return read_cpuid(CPUID_CACHETYPE);
70 }
71
72 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
73 {
74         return read_cpuid(CPUID_TCM);
75 }
76
77 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
78 {
79         return read_cpuid(CPUID_MPIDR);
80 }
81
82 /*
83  * Intel's XScale3 core supports some v6 features (supersections, L2)
84  * but advertises itself as v5 as it does not support the v6 ISA.  For
85  * this reason, we need a way to explicitly test for this type of CPU.
86  */
87 #ifndef CONFIG_CPU_XSC3
88 #define cpu_is_xsc3()   0
89 #else
90 static inline int cpu_is_xsc3(void)
91 {
92         unsigned int id;
93         id = read_cpuid_id() & 0xffffe000;
94         /* It covers both Intel ID and Marvell ID */
95         if ((id == 0x69056000) || (id == 0x56056000))
96                 return 1;
97
98         return 0;
99 }
100 #endif
101
102 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
103 #define cpu_is_xscale() 0
104 #else
105 #define cpu_is_xscale() 1
106 #endif
107
108 #endif