5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
8 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
9 select CMA if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_KPROBES if !XIP_KERNEL
17 select HAVE_KRETPROBES if (HAVE_KPROBES)
18 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
19 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
20 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
21 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
22 select HAVE_GENERIC_DMA_COHERENT
23 select HAVE_KERNEL_GZIP
24 select HAVE_KERNEL_LZO
25 select HAVE_KERNEL_LZMA
27 select HAVE_PERF_EVENTS
28 select PERF_USE_VMALLOC
29 select HAVE_REGS_AND_STACK_ACCESS_API
30 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
31 select HAVE_C_RECORDMCOUNT
32 select HAVE_GENERIC_HARDIRQS
33 select HAVE_SPARSE_IRQ
34 select GENERIC_IRQ_SHOW
35 select CPU_PM if (SUSPEND || CPU_IDLE)
37 The ARM series is a line of low-power-consumption RISC chip designs
38 licensed by ARM Ltd and targeted at embedded applications and
39 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
40 manufactured, but legacy ARM-based PC hardware remains popular in
41 Europe. There is an ARM Linux project with a web page at
42 <http://www.arm.linux.org.uk/>.
44 config ARM_HAS_SG_CHAIN
47 config NEED_SG_DMA_LENGTH
50 config ARM_DMA_USE_IOMMU
51 select NEED_SG_DMA_LENGTH
52 select ARM_HAS_SG_CHAIN
61 config SYS_SUPPORTS_APM_EMULATION
64 config HAVE_SCHED_CLOCK
70 config ARCH_USES_GETTIMEOFFSET
74 config GENERIC_CLOCKEVENTS
77 config GENERIC_CLOCKEVENTS_BROADCAST
79 depends on GENERIC_CLOCKEVENTS
88 select GENERIC_ALLOCATOR
99 The Extended Industry Standard Architecture (EISA) bus was
100 developed as an open alternative to the IBM MicroChannel bus.
102 The EISA bus provided some of the features of the IBM MicroChannel
103 bus while maintaining backward compatibility with cards made for
104 the older ISA bus. The EISA bus saw limited use between 1988 and
105 1995 when it was made obsolete by the PCI bus.
107 Say Y here if you are building a kernel for an EISA-based machine.
117 MicroChannel Architecture is found in some IBM PS/2 machines and
118 laptops. It is a bus system similar to PCI or ISA. See
119 <file:Documentation/mca.txt> (and especially the web page given
120 there) before attempting to build an MCA bus kernel.
122 config STACKTRACE_SUPPORT
126 config HAVE_LATENCYTOP_SUPPORT
131 config LOCKDEP_SUPPORT
135 config TRACE_IRQFLAGS_SUPPORT
139 config HARDIRQS_SW_RESEND
143 config GENERIC_IRQ_PROBE
147 config GENERIC_LOCKBREAK
150 depends on SMP && PREEMPT
152 config RWSEM_GENERIC_SPINLOCK
156 config RWSEM_XCHGADD_ALGORITHM
159 config ARCH_HAS_ILOG2_U32
162 config ARCH_HAS_ILOG2_U64
165 config ARCH_HAS_CPUFREQ
168 Internal node to signify that the ARCH has CPUFREQ support
169 and that the relevant menu configurations are displayed for
172 config ARCH_HAS_CPU_IDLE_WAIT
175 config GENERIC_HWEIGHT
179 config GENERIC_CALIBRATE_DELAY
183 config ARCH_MAY_HAVE_PC_FDC
189 config NEED_DMA_MAP_STATE
192 config ARCH_HAS_DMA_SET_COHERENT_MASK
195 config GENERIC_ISA_DMA
206 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
207 default DRAM_BASE if REMAP_VECTORS_TO_RAM
210 The base address of exception vectors.
212 config ARM_PATCH_PHYS_VIRT
213 bool "Patch physical to virtual translations at runtime" if EMBEDDED
215 depends on !XIP_KERNEL && MMU
216 depends on !ARCH_REALVIEW || !SPARSEMEM
218 Patch phys-to-virt and virt-to-phys translation functions at
219 boot and module load time according to the position of the
220 kernel in system memory.
222 This can only be used with non-XIP MMU kernels where the base
223 of physical memory is at a 16MB boundary.
225 Only disable this option if you know that you do not require
226 this feature (eg, building a kernel for a single machine) and
227 you need to shrink the kernel to the minimal size.
229 config NEED_MACH_MEMORY_H
232 Select this when mach/memory.h is required to provide special
233 definitions for this platform. The need for mach/memory.h should
234 be avoided when possible.
237 hex "Physical address of main memory" if MMU
238 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
239 default DRAM_BASE if !MMU
241 Please provide the physical address corresponding to the
242 location of main memory in your system.
248 source "init/Kconfig"
250 source "kernel/Kconfig.freezer"
255 bool "MMU-based Paged Memory Management Support"
258 Select if you want MMU-based virtualised addressing space
259 support by paged memory management. If unsure, say 'Y'.
262 # The "ARM system type" choice list is ordered alphabetically by option
263 # text. Please add new entries in the option alphabetic order.
266 prompt "ARM system type"
267 default ARCH_VERSATILE
269 config ARCH_INTEGRATOR
270 bool "ARM Ltd. Integrator family"
272 select ARCH_HAS_CPUFREQ
274 select HAVE_MACH_CLKDEV
276 select GENERIC_CLOCKEVENTS
277 select PLAT_VERSATILE
278 select PLAT_VERSATILE_FPGA_IRQ
279 select NEED_MACH_MEMORY_H
281 Support for ARM's Integrator platform.
284 bool "ARM Ltd. RealView family"
287 select HAVE_MACH_CLKDEV
289 select GENERIC_CLOCKEVENTS
290 select ARCH_WANT_OPTIONAL_GPIOLIB
291 select PLAT_VERSATILE
292 select PLAT_VERSATILE_CLCD
293 select ARM_TIMER_SP804
294 select GPIO_PL061 if GPIOLIB
295 select NEED_MACH_MEMORY_H
297 This enables support for ARM Ltd RealView boards.
299 config ARCH_VERSATILE
300 bool "ARM Ltd. Versatile family"
304 select HAVE_MACH_CLKDEV
306 select GENERIC_CLOCKEVENTS
307 select ARCH_WANT_OPTIONAL_GPIOLIB
308 select PLAT_VERSATILE
309 select PLAT_VERSATILE_CLCD
310 select PLAT_VERSATILE_FPGA_IRQ
311 select ARM_TIMER_SP804
313 This enables support for ARM Ltd Versatile board.
316 bool "ARM Ltd. Versatile Express family"
317 select ARCH_WANT_OPTIONAL_GPIOLIB
319 select ARM_TIMER_SP804
321 select HAVE_MACH_CLKDEV
322 select GENERIC_CLOCKEVENTS
324 select HAVE_PATA_PLATFORM
326 select PLAT_VERSATILE
327 select PLAT_VERSATILE_CLCD
329 This enables support for the ARM Ltd Versatile Express boards.
333 select ARCH_REQUIRE_GPIOLIB
337 This enables support for systems based on the Atmel AT91RM9200,
338 AT91SAM9 and AT91CAP9 processors.
341 bool "Broadcom BCMRING"
345 select ARM_TIMER_SP804
347 select GENERIC_CLOCKEVENTS
348 select ARCH_WANT_OPTIONAL_GPIOLIB
350 Support for Broadcom's BCMRing platform.
353 bool "Calxeda Highbank-based"
354 select ARCH_WANT_OPTIONAL_GPIOLIB
357 select ARM_TIMER_SP804
360 select GENERIC_CLOCKEVENTS
364 Support for the Calxeda Highbank SoC based boards.
367 bool "Cirrus Logic CLPS711x/EP721x-based"
369 select ARCH_USES_GETTIMEOFFSET
370 select NEED_MACH_MEMORY_H
372 Support for Cirrus Logic 711x/721x based boards.
375 bool "Cavium Networks CNS3XXX family"
377 select GENERIC_CLOCKEVENTS
379 select MIGHT_HAVE_PCI
380 select PCI_DOMAINS if PCI
382 Support for Cavium Networks CNS3XXX platform.
385 bool "Cortina Systems Gemini"
387 select ARCH_REQUIRE_GPIOLIB
388 select ARCH_USES_GETTIMEOFFSET
390 Support for the Cortina Systems Gemini family SoCs
393 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
396 select GENERIC_CLOCKEVENTS
398 select GENERIC_IRQ_CHIP
402 Support for CSR SiRFSoC ARM Cortex A9 Platform
409 select ARCH_USES_GETTIMEOFFSET
410 select NEED_MACH_MEMORY_H
412 This is an evaluation board for the StrongARM processor available
413 from Digital. It has limited hardware on-board, including an
414 Ethernet interface, two PCMCIA sockets, two serial ports and a
423 select ARCH_REQUIRE_GPIOLIB
424 select ARCH_HAS_HOLES_MEMORYMODEL
425 select ARCH_USES_GETTIMEOFFSET
426 select NEED_MACH_MEMORY_H
428 This enables support for the Cirrus EP93xx series of CPUs.
430 config ARCH_FOOTBRIDGE
434 select GENERIC_CLOCKEVENTS
436 select NEED_MACH_MEMORY_H
438 Support for systems based on the DC21285 companion chip
439 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
442 bool "Freescale MXC/iMX-based"
443 select GENERIC_CLOCKEVENTS
444 select ARCH_REQUIRE_GPIOLIB
447 select GENERIC_IRQ_CHIP
448 select HAVE_SCHED_CLOCK
449 select MULTI_IRQ_HANDLER
451 Support for Freescale MXC/iMX-based family of processors
454 bool "Freescale MXS-based"
455 select GENERIC_CLOCKEVENTS
456 select ARCH_REQUIRE_GPIOLIB
460 Support for Freescale MXS-based family of processors
463 bool "Hilscher NetX based"
467 select GENERIC_CLOCKEVENTS
469 This enables support for systems based on the Hilscher NetX Soc
472 bool "Hynix HMS720x-based"
475 select ARCH_USES_GETTIMEOFFSET
477 This enables support for systems based on the Hynix HMS720x
485 select ARCH_SUPPORTS_MSI
487 select NEED_MACH_MEMORY_H
489 Support for Intel's IOP13XX (XScale) family of processors.
497 select ARCH_REQUIRE_GPIOLIB
499 Support for Intel's 80219 and IOP32X (XScale) family of
508 select ARCH_REQUIRE_GPIOLIB
510 Support for Intel's IOP33X (XScale) family of processors.
517 select ARCH_USES_GETTIMEOFFSET
518 select NEED_MACH_MEMORY_H
520 Support for Intel's IXP23xx (XScale) family of processors.
523 bool "IXP2400/2800-based"
527 select ARCH_USES_GETTIMEOFFSET
528 select NEED_MACH_MEMORY_H
530 Support for Intel's IXP2400/2800 (XScale) family of processors.
535 select ARCH_HAS_DMA_SET_COHERENT_MASK
538 select ARCH_REQUIRE_GPIOLIB
539 select GENERIC_CLOCKEVENTS
540 select HAVE_SCHED_CLOCK
541 select MIGHT_HAVE_PCI
542 select DMABOUNCE if PCI
544 Support for Intel's IXP4XX (XScale) family of processors.
550 select ARCH_REQUIRE_GPIOLIB
551 select GENERIC_CLOCKEVENTS
554 Support for the Marvell Dove SoC 88AP510
557 bool "Marvell Kirkwood"
561 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
565 Support for the following Marvell Kirkwood series SoCs:
566 88F6180, 88F6192 and 88F6281.
572 select ARCH_REQUIRE_GPIOLIB
575 select USB_ARCH_HAS_OHCI
577 select GENERIC_CLOCKEVENTS
579 Support for the NXP LPC32XX family of processors
582 bool "Marvell MV78xx0"
585 select ARCH_REQUIRE_GPIOLIB
586 select GENERIC_CLOCKEVENTS
589 Support for the following Marvell MV78xx0 series SoCs:
597 select ARCH_REQUIRE_GPIOLIB
598 select GENERIC_CLOCKEVENTS
601 Support for the following Marvell Orion 5x series SoCs:
602 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
603 Orion-2 (5281), Orion-1-90 (6183).
606 bool "Marvell PXA168/910/MMP2"
608 select ARCH_REQUIRE_GPIOLIB
610 select GENERIC_CLOCKEVENTS
611 select HAVE_SCHED_CLOCK
615 select GENERIC_ALLOCATOR
617 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
620 bool "Micrel/Kendin KS8695"
622 select ARCH_REQUIRE_GPIOLIB
623 select ARCH_USES_GETTIMEOFFSET
624 select NEED_MACH_MEMORY_H
626 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
627 System-on-Chip devices.
630 bool "Nuvoton W90X900 CPU"
632 select ARCH_REQUIRE_GPIOLIB
635 select GENERIC_CLOCKEVENTS
637 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
638 At present, the w90x900 has been renamed nuc900, regarding
639 the ARM series product line, you can login the following
640 link address to know more.
642 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
643 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
649 select GENERIC_CLOCKEVENTS
652 select HAVE_SCHED_CLOCK
653 select ARCH_HAS_CPUFREQ
655 This enables support for NVIDIA Tegra based systems (Tegra APX,
656 Tegra 6xx and Tegra 2 series).
658 config ARCH_PICOXCELL
659 bool "Picochip picoXcell"
660 select ARCH_REQUIRE_GPIOLIB
661 select ARM_PATCH_PHYS_VIRT
665 select GENERIC_CLOCKEVENTS
667 select HAVE_SCHED_CLOCK
672 This enables support for systems based on the Picochip picoXcell
673 family of Femtocell devices. The picoxcell support requires device tree
677 bool "Philips Nexperia PNX4008 Mobile"
680 select ARCH_USES_GETTIMEOFFSET
682 This enables support for Philips PNX4008 mobile platform.
685 bool "PXA2xx/PXA3xx-based"
688 select ARCH_HAS_CPUFREQ
691 select ARCH_REQUIRE_GPIOLIB
692 select GENERIC_CLOCKEVENTS
693 select HAVE_SCHED_CLOCK
698 select MULTI_IRQ_HANDLER
699 select ARM_CPU_SUSPEND if PM
702 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
707 select GENERIC_CLOCKEVENTS
708 select ARCH_REQUIRE_GPIOLIB
711 Support for Qualcomm MSM/QSD based systems. This runs on the
712 apps processor of the MSM/QSD and depends on a shared memory
713 interface to the modem processor which runs the baseband
714 stack and controls some vital subsystems
715 (clock and power control, etc).
718 bool "Renesas SH-Mobile / R-Mobile"
721 select HAVE_MACH_CLKDEV
722 select GENERIC_CLOCKEVENTS
725 select MULTI_IRQ_HANDLER
726 select PM_GENERIC_DOMAINS if PM
727 select NEED_MACH_MEMORY_H
729 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
736 select ARCH_MAY_HAVE_PC_FDC
737 select HAVE_PATA_PLATFORM
740 select ARCH_SPARSEMEM_ENABLE
741 select ARCH_USES_GETTIMEOFFSET
743 select NEED_MACH_MEMORY_H
745 On the Acorn Risc-PC, Linux can support the internal IDE disk and
746 CD-ROM interface, serial and parallel port, and the floppy drive.
753 select ARCH_SPARSEMEM_ENABLE
755 select ARCH_HAS_CPUFREQ
757 select GENERIC_CLOCKEVENTS
759 select HAVE_SCHED_CLOCK
761 select ARCH_REQUIRE_GPIOLIB
763 select NEED_MACH_MEMORY_H
765 Support for StrongARM 11x0 based boards.
768 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
770 select ARCH_HAS_CPUFREQ
773 select ARCH_USES_GETTIMEOFFSET
774 select HAVE_S3C2410_I2C if I2C
776 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
777 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
778 the Samsung SMDK2410 development board (and derivatives).
780 Note, the S3C2416 and the S3C2450 are so close that they even share
781 the same SoC ID code. This means that there is no separate machine
782 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
785 bool "Samsung S3C64XX"
793 select ARCH_USES_GETTIMEOFFSET
794 select ARCH_HAS_CPUFREQ
795 select ARCH_REQUIRE_GPIOLIB
796 select SAMSUNG_CLKSRC
797 select SAMSUNG_IRQ_VIC_TIMER
798 select S3C_GPIO_TRACK
800 select USB_ARCH_HAS_OHCI
801 select SAMSUNG_GPIOLIB_4BIT
802 select HAVE_S3C2410_I2C if I2C
803 select HAVE_S3C2410_WATCHDOG if WATCHDOG
805 Samsung S3C64XX series based systems
808 bool "Samsung S5P6440 S5P6450"
814 select HAVE_S3C2410_WATCHDOG if WATCHDOG
815 select GENERIC_CLOCKEVENTS
816 select HAVE_SCHED_CLOCK
817 select HAVE_S3C2410_I2C if I2C
818 select HAVE_S3C_RTC if RTC_CLASS
820 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
824 bool "Samsung S5PC100"
829 select ARM_L1_CACHE_SHIFT_6
830 select ARCH_USES_GETTIMEOFFSET
831 select HAVE_S3C2410_I2C if I2C
832 select HAVE_S3C_RTC if RTC_CLASS
833 select HAVE_S3C2410_WATCHDOG if WATCHDOG
835 Samsung S5PC100 series based systems
838 bool "Samsung S5PV210/S5PC110"
840 select ARCH_SPARSEMEM_ENABLE
841 select ARCH_HAS_HOLES_MEMORYMODEL
846 select ARM_L1_CACHE_SHIFT_6
847 select ARCH_HAS_CPUFREQ
848 select GENERIC_CLOCKEVENTS
849 select HAVE_SCHED_CLOCK
850 select HAVE_S3C2410_I2C if I2C
851 select HAVE_S3C_RTC if RTC_CLASS
852 select HAVE_S3C2410_WATCHDOG if WATCHDOG
853 select NEED_MACH_MEMORY_H
855 Samsung S5PV210/S5PC110 series based systems
858 bool "SAMSUNG EXYNOS"
860 select ARCH_SPARSEMEM_ENABLE
861 select ARCH_HAS_HOLES_MEMORYMODEL
865 select ARCH_HAS_CPUFREQ
866 select GENERIC_CLOCKEVENTS
867 select HAVE_S3C_RTC if RTC_CLASS
868 select HAVE_S3C2410_I2C if I2C
869 select HAVE_S3C2410_WATCHDOG if WATCHDOG
870 select NEED_MACH_MEMORY_H
872 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
881 select ARCH_USES_GETTIMEOFFSET
882 select NEED_MACH_MEMORY_H
884 Support for the StrongARM based Digital DNARD machine, also known
885 as "Shark" (<http://www.shark-linux.de/shark.html>).
888 bool "Telechips TCC ARM926-based systems"
893 select GENERIC_CLOCKEVENTS
895 Support for Telechips TCC ARM926-based systems.
898 bool "ST-Ericsson U300 Series"
902 select HAVE_SCHED_CLOCK
905 select ARM_PATCH_PHYS_VIRT
907 select GENERIC_CLOCKEVENTS
909 select HAVE_MACH_CLKDEV
911 select ARCH_REQUIRE_GPIOLIB
912 select NEED_MACH_MEMORY_H
914 Support for ST-Ericsson U300 series mobile platforms.
917 bool "ST-Ericsson U8500 Series"
920 select GENERIC_CLOCKEVENTS
922 select ARCH_REQUIRE_GPIOLIB
923 select ARCH_HAS_CPUFREQ
925 Support for ST-Ericsson's Ux500 architecture
928 bool "STMicroelectronics Nomadik"
933 select GENERIC_CLOCKEVENTS
934 select ARCH_REQUIRE_GPIOLIB
936 Support for the Nomadik platform by ST-Ericsson
940 select GENERIC_CLOCKEVENTS
941 select ARCH_REQUIRE_GPIOLIB
945 select GENERIC_ALLOCATOR
946 select GENERIC_IRQ_CHIP
947 select ARCH_HAS_HOLES_MEMORYMODEL
949 Support for TI's DaVinci platform.
954 select ARCH_REQUIRE_GPIOLIB
955 select ARCH_HAS_CPUFREQ
957 select GENERIC_CLOCKEVENTS
958 select HAVE_SCHED_CLOCK
959 select ARCH_HAS_HOLES_MEMORYMODEL
961 Support for TI's OMAP platform (OMAP1/2/3/4).
966 select ARCH_REQUIRE_GPIOLIB
969 select GENERIC_CLOCKEVENTS
972 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
975 bool "VIA/WonderMedia 85xx"
978 select ARCH_HAS_CPUFREQ
979 select GENERIC_CLOCKEVENTS
980 select ARCH_REQUIRE_GPIOLIB
983 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
986 bool "Xilinx Zynq ARM Cortex A9 Platform"
988 select GENERIC_CLOCKEVENTS
995 Support for Xilinx Zynq ARM Cortex A9 Platform
999 # This is sorted alphabetically by mach-* pathname. However, plat-*
1000 # Kconfigs may be included either alphabetically (according to the
1001 # plat- suffix) or along side the corresponding mach-* source.
1003 source "arch/arm/mach-at91/Kconfig"
1005 source "arch/arm/mach-bcmring/Kconfig"
1007 source "arch/arm/mach-clps711x/Kconfig"
1009 source "arch/arm/mach-cns3xxx/Kconfig"
1011 source "arch/arm/mach-davinci/Kconfig"
1013 source "arch/arm/mach-dove/Kconfig"
1015 source "arch/arm/mach-ep93xx/Kconfig"
1017 source "arch/arm/mach-footbridge/Kconfig"
1019 source "arch/arm/mach-gemini/Kconfig"
1021 source "arch/arm/mach-h720x/Kconfig"
1023 source "arch/arm/mach-integrator/Kconfig"
1025 source "arch/arm/mach-iop32x/Kconfig"
1027 source "arch/arm/mach-iop33x/Kconfig"
1029 source "arch/arm/mach-iop13xx/Kconfig"
1031 source "arch/arm/mach-ixp4xx/Kconfig"
1033 source "arch/arm/mach-ixp2000/Kconfig"
1035 source "arch/arm/mach-ixp23xx/Kconfig"
1037 source "arch/arm/mach-kirkwood/Kconfig"
1039 source "arch/arm/mach-ks8695/Kconfig"
1041 source "arch/arm/mach-lpc32xx/Kconfig"
1043 source "arch/arm/mach-msm/Kconfig"
1045 source "arch/arm/mach-mv78xx0/Kconfig"
1047 source "arch/arm/plat-mxc/Kconfig"
1049 source "arch/arm/mach-mxs/Kconfig"
1051 source "arch/arm/mach-netx/Kconfig"
1053 source "arch/arm/mach-nomadik/Kconfig"
1054 source "arch/arm/plat-nomadik/Kconfig"
1056 source "arch/arm/plat-omap/Kconfig"
1058 source "arch/arm/mach-omap1/Kconfig"
1060 source "arch/arm/mach-omap2/Kconfig"
1062 source "arch/arm/mach-orion5x/Kconfig"
1064 source "arch/arm/mach-pxa/Kconfig"
1065 source "arch/arm/plat-pxa/Kconfig"
1067 source "arch/arm/mach-mmp/Kconfig"
1069 source "arch/arm/mach-realview/Kconfig"
1071 source "arch/arm/mach-sa1100/Kconfig"
1073 source "arch/arm/plat-samsung/Kconfig"
1074 source "arch/arm/plat-s3c24xx/Kconfig"
1075 source "arch/arm/plat-s5p/Kconfig"
1077 source "arch/arm/plat-spear/Kconfig"
1079 source "arch/arm/plat-tcc/Kconfig"
1082 source "arch/arm/mach-s3c2410/Kconfig"
1083 source "arch/arm/mach-s3c2412/Kconfig"
1084 source "arch/arm/mach-s3c2416/Kconfig"
1085 source "arch/arm/mach-s3c2440/Kconfig"
1086 source "arch/arm/mach-s3c2443/Kconfig"
1090 source "arch/arm/mach-s3c64xx/Kconfig"
1093 source "arch/arm/mach-s5p64x0/Kconfig"
1095 source "arch/arm/mach-s5pc100/Kconfig"
1097 source "arch/arm/mach-s5pv210/Kconfig"
1099 source "arch/arm/mach-exynos/Kconfig"
1101 source "arch/arm/mach-shmobile/Kconfig"
1103 source "arch/arm/mach-tegra/Kconfig"
1105 source "arch/arm/mach-u300/Kconfig"
1107 source "arch/arm/mach-ux500/Kconfig"
1109 source "arch/arm/mach-versatile/Kconfig"
1111 source "arch/arm/mach-vexpress/Kconfig"
1112 source "arch/arm/plat-versatile/Kconfig"
1114 source "arch/arm/mach-vt8500/Kconfig"
1116 source "arch/arm/mach-w90x900/Kconfig"
1118 # Definitions to make life easier
1124 select GENERIC_CLOCKEVENTS
1125 select HAVE_SCHED_CLOCK
1130 select GENERIC_IRQ_CHIP
1131 select HAVE_SCHED_CLOCK
1136 config PLAT_VERSATILE
1139 config ARM_TIMER_SP804
1143 source arch/arm/mm/Kconfig
1146 bool "Enable iWMMXt support"
1147 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1148 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1150 Enable support for iWMMXt context switching at run time if
1151 running on a CPU that supports it.
1153 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1156 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1160 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1161 (!ARCH_OMAP3 || OMAP3_EMU)
1165 config MULTI_IRQ_HANDLER
1168 Allow each machine to specify it's own IRQ handler at run time.
1171 source "arch/arm/Kconfig-nommu"
1174 config ARM_ERRATA_326103
1175 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1178 Executing a SWP instruction to read-only memory does not set bit 11
1179 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1180 treat the access as a read, preventing a COW from occurring and
1181 causing the faulting task to livelock.
1183 config ARM_ERRATA_411920
1184 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1185 depends on CPU_V6 || CPU_V6K
1187 Invalidation of the Instruction Cache operation can
1188 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1189 It does not affect the MPCore. This option enables the ARM Ltd.
1190 recommended workaround.
1192 config ARM_ERRATA_430973
1193 bool "ARM errata: Stale prediction on replaced interworking branch"
1196 This option enables the workaround for the 430973 Cortex-A8
1197 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1198 interworking branch is replaced with another code sequence at the
1199 same virtual address, whether due to self-modifying code or virtual
1200 to physical address re-mapping, Cortex-A8 does not recover from the
1201 stale interworking branch prediction. This results in Cortex-A8
1202 executing the new code sequence in the incorrect ARM or Thumb state.
1203 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1204 and also flushes the branch target cache at every context switch.
1205 Note that setting specific bits in the ACTLR register may not be
1206 available in non-secure mode.
1208 config ARM_ERRATA_458693
1209 bool "ARM errata: Processor deadlock when a false hazard is created"
1212 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1213 erratum. For very specific sequences of memory operations, it is
1214 possible for a hazard condition intended for a cache line to instead
1215 be incorrectly associated with a different cache line. This false
1216 hazard might then cause a processor deadlock. The workaround enables
1217 the L1 caching of the NEON accesses and disables the PLD instruction
1218 in the ACTLR register. Note that setting specific bits in the ACTLR
1219 register may not be available in non-secure mode.
1221 config ARM_ERRATA_460075
1222 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1225 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1226 erratum. Any asynchronous access to the L2 cache may encounter a
1227 situation in which recent store transactions to the L2 cache are lost
1228 and overwritten with stale memory contents from external memory. The
1229 workaround disables the write-allocate mode for the L2 cache via the
1230 ACTLR register. Note that setting specific bits in the ACTLR register
1231 may not be available in non-secure mode.
1233 config ARM_ERRATA_742230
1234 bool "ARM errata: DMB operation may be faulty"
1235 depends on CPU_V7 && SMP
1237 This option enables the workaround for the 742230 Cortex-A9
1238 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1239 between two write operations may not ensure the correct visibility
1240 ordering of the two writes. This workaround sets a specific bit in
1241 the diagnostic register of the Cortex-A9 which causes the DMB
1242 instruction to behave as a DSB, ensuring the correct behaviour of
1245 config ARM_ERRATA_742231
1246 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1247 depends on CPU_V7 && SMP
1249 This option enables the workaround for the 742231 Cortex-A9
1250 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1251 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1252 accessing some data located in the same cache line, may get corrupted
1253 data due to bad handling of the address hazard when the line gets
1254 replaced from one of the CPUs at the same time as another CPU is
1255 accessing it. This workaround sets specific bits in the diagnostic
1256 register of the Cortex-A9 which reduces the linefill issuing
1257 capabilities of the processor.
1259 config PL310_ERRATA_588369
1260 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1261 depends on CACHE_L2X0
1263 The PL310 L2 cache controller implements three types of Clean &
1264 Invalidate maintenance operations: by Physical Address
1265 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1266 They are architecturally defined to behave as the execution of a
1267 clean operation followed immediately by an invalidate operation,
1268 both performing to the same memory location. This functionality
1269 is not correctly implemented in PL310 as clean lines are not
1270 invalidated as a result of these operations.
1272 config ARM_ERRATA_720789
1273 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1276 This option enables the workaround for the 720789 Cortex-A9 (prior to
1277 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1278 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1279 As a consequence of this erratum, some TLB entries which should be
1280 invalidated are not, resulting in an incoherency in the system page
1281 tables. The workaround changes the TLB flushing routines to invalidate
1282 entries regardless of the ASID.
1284 config PL310_ERRATA_727915
1285 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1286 depends on CACHE_L2X0
1288 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1289 operation (offset 0x7FC). This operation runs in background so that
1290 PL310 can handle normal accesses while it is in progress. Under very
1291 rare circumstances, due to this erratum, write data can be lost when
1292 PL310 treats a cacheable write transaction during a Clean &
1293 Invalidate by Way operation.
1295 config ARM_ERRATA_743622
1296 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1299 This option enables the workaround for the 743622 Cortex-A9
1300 (r2p*) erratum. Under very rare conditions, a faulty
1301 optimisation in the Cortex-A9 Store Buffer may lead to data
1302 corruption. This workaround sets a specific bit in the diagnostic
1303 register of the Cortex-A9 which disables the Store Buffer
1304 optimisation, preventing the defect from occurring. This has no
1305 visible impact on the overall performance or power consumption of the
1308 config ARM_ERRATA_751472
1309 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1312 This option enables the workaround for the 751472 Cortex-A9 (prior
1313 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1314 completion of a following broadcasted operation if the second
1315 operation is received by a CPU before the ICIALLUIS has completed,
1316 potentially leading to corrupted entries in the cache or TLB.
1318 config PL310_ERRATA_753970
1319 bool "PL310 errata: cache sync operation may be faulty"
1320 depends on CACHE_PL310
1322 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1324 Under some condition the effect of cache sync operation on
1325 the store buffer still remains when the operation completes.
1326 This means that the store buffer is always asked to drain and
1327 this prevents it from merging any further writes. The workaround
1328 is to replace the normal offset of cache sync operation (0x730)
1329 by another offset targeting an unmapped PL310 register 0x740.
1330 This has the same effect as the cache sync operation: store buffer
1331 drain and waiting for all buffers empty.
1333 config ARM_ERRATA_754322
1334 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1337 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1338 r3p*) erratum. A speculative memory access may cause a page table walk
1339 which starts prior to an ASID switch but completes afterwards. This
1340 can populate the micro-TLB with a stale entry which may be hit with
1341 the new ASID. This workaround places two dsb instructions in the mm
1342 switching code so that no page table walks can cross the ASID switch.
1344 config ARM_ERRATA_754327
1345 bool "ARM errata: no automatic Store Buffer drain"
1346 depends on CPU_V7 && SMP
1348 This option enables the workaround for the 754327 Cortex-A9 (prior to
1349 r2p0) erratum. The Store Buffer does not have any automatic draining
1350 mechanism and therefore a livelock may occur if an external agent
1351 continuously polls a memory location waiting to observe an update.
1352 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1353 written polling loops from denying visibility of updates to memory.
1355 config ARM_ERRATA_364296
1356 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1357 depends on CPU_V6 && !SMP
1359 This options enables the workaround for the 364296 ARM1136
1360 r0p2 erratum (possible cache data corruption with
1361 hit-under-miss enabled). It sets the undocumented bit 31 in
1362 the auxiliary control register and the FI bit in the control
1363 register, thus disabling hit-under-miss without putting the
1364 processor into full low interrupt latency mode. ARM11MPCore
1367 config ARM_ERRATA_764369
1368 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1369 depends on CPU_V7 && SMP
1371 This option enables the workaround for erratum 764369
1372 affecting Cortex-A9 MPCore with two or more processors (all
1373 current revisions). Under certain timing circumstances, a data
1374 cache line maintenance operation by MVA targeting an Inner
1375 Shareable memory region may fail to proceed up to either the
1376 Point of Coherency or to the Point of Unification of the
1377 system. This workaround adds a DSB instruction before the
1378 relevant cache maintenance functions and sets a specific bit
1379 in the diagnostic control register of the SCU.
1381 config PL310_ERRATA_769419
1382 bool "PL310 errata: no automatic Store Buffer drain"
1383 depends on CACHE_L2X0
1385 On revisions of the PL310 prior to r3p2, the Store Buffer does
1386 not automatically drain. This can cause normal, non-cacheable
1387 writes to be retained when the memory system is idle, leading
1388 to suboptimal I/O performance for drivers using coherent DMA.
1389 This option adds a write barrier to the cpu_idle loop so that,
1390 on systems with an outer cache, the store buffer is drained
1395 source "arch/arm/common/Kconfig"
1405 Find out whether you have ISA slots on your motherboard. ISA is the
1406 name of a bus system, i.e. the way the CPU talks to the other stuff
1407 inside your box. Other bus systems are PCI, EISA, MicroChannel
1408 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1409 newer boards don't support it. If you have ISA, say Y, otherwise N.
1411 # Select ISA DMA controller support
1416 # Select ISA DMA interface
1421 bool "PCI support" if MIGHT_HAVE_PCI
1423 Find out whether you have a PCI motherboard. PCI is the name of a
1424 bus system, i.e. the way the CPU talks to the other stuff inside
1425 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1426 VESA. If you have PCI, say Y, otherwise N.
1432 config PCI_NANOENGINE
1433 bool "BSE nanoEngine PCI support"
1434 depends on SA1100_NANOENGINE
1436 Enable PCI on the BSE nanoEngine board.
1441 # Select the host bridge type
1442 config PCI_HOST_VIA82C505
1444 depends on PCI && ARCH_SHARK
1447 config PCI_HOST_ITE8152
1449 depends on PCI && MACH_ARMCORE
1453 source "drivers/pci/Kconfig"
1455 source "drivers/pcmcia/Kconfig"
1459 menu "Kernel Features"
1461 source "kernel/time/Kconfig"
1464 bool "Symmetric Multi-Processing"
1465 depends on CPU_V6K || CPU_V7
1466 depends on GENERIC_CLOCKEVENTS
1467 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1468 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1469 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1470 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
1472 select USE_GENERIC_SMP_HELPERS
1473 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1475 This enables support for systems with more than one CPU. If you have
1476 a system with only one CPU, like most personal computers, say N. If
1477 you have a system with more than one CPU, say Y.
1479 If you say N here, the kernel will run on single and multiprocessor
1480 machines, but will use only one CPU of a multiprocessor machine. If
1481 you say Y here, the kernel will run on many, but not all, single
1482 processor machines. On a single processor machine, the kernel will
1483 run faster if you say N here.
1485 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1486 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1487 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1489 If you don't know what to do here, say N.
1492 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1493 depends on EXPERIMENTAL
1494 depends on SMP && !XIP_KERNEL
1497 SMP kernels contain instructions which fail on non-SMP processors.
1498 Enabling this option allows the kernel to modify itself to make
1499 these instructions safe. Disabling it allows about 1K of space
1502 If you don't know what to do here, say Y.
1504 config ARM_CPU_TOPOLOGY
1505 bool "Support cpu topology definition"
1506 depends on SMP && CPU_V7
1509 Support ARM cpu topology definition. The MPIDR register defines
1510 affinity between processors which is then used to describe the cpu
1511 topology of an ARM System.
1514 bool "Multi-core scheduler support"
1515 depends on ARM_CPU_TOPOLOGY
1517 Multi-core scheduler support improves the CPU scheduler's decision
1518 making when dealing with multi-core CPU chips at a cost of slightly
1519 increased overhead in some places. If unsure say N here.
1522 bool "SMT scheduler support"
1523 depends on ARM_CPU_TOPOLOGY
1525 Improves the CPU scheduler's decision making when dealing with
1526 MultiThreading at a cost of slightly increased overhead in some
1527 places. If unsure say N here.
1532 This option enables support for the ARM system coherency unit
1539 This options enables support for the ARM timer and watchdog unit
1542 prompt "Memory split"
1545 Select the desired split between kernel and user memory.
1547 If you are not absolutely sure what you are doing, leave this
1551 bool "3G/1G user/kernel split"
1553 bool "2G/2G user/kernel split"
1555 bool "1G/3G user/kernel split"
1560 default 0x40000000 if VMSPLIT_1G
1561 default 0x80000000 if VMSPLIT_2G
1565 int "Maximum number of CPUs (2-32)"
1571 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1572 depends on SMP && HOTPLUG && EXPERIMENTAL
1574 Say Y here to experiment with turning CPUs off and on. CPUs
1575 can be controlled through /sys/devices/system/cpu.
1578 bool "Use local timer interrupts"
1581 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1583 Enable support for local timers on SMP platforms, rather then the
1584 legacy IPI broadcast method. Local timers allows the system
1585 accounting to be spread across the timer interval, preventing a
1586 "thundering herd" at every timer tick.
1588 source kernel/Kconfig.preempt
1592 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1593 ARCH_S5PV210 || ARCH_EXYNOS4
1594 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1595 default AT91_TIMER_HZ if ARCH_AT91
1596 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1599 config THUMB2_KERNEL
1600 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1601 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1603 select ARM_ASM_UNIFIED
1606 By enabling this option, the kernel will be compiled in
1607 Thumb-2 mode. A compiler/assembler that understand the unified
1608 ARM-Thumb syntax is needed.
1612 config THUMB2_AVOID_R_ARM_THM_JUMP11
1613 bool "Work around buggy Thumb-2 short branch relocations in gas"
1614 depends on THUMB2_KERNEL && MODULES
1617 Various binutils versions can resolve Thumb-2 branches to
1618 locally-defined, preemptible global symbols as short-range "b.n"
1619 branch instructions.
1621 This is a problem, because there's no guarantee the final
1622 destination of the symbol, or any candidate locations for a
1623 trampoline, are within range of the branch. For this reason, the
1624 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1625 relocation in modules at all, and it makes little sense to add
1628 The symptom is that the kernel fails with an "unsupported
1629 relocation" error when loading some modules.
1631 Until fixed tools are available, passing
1632 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1633 code which hits this problem, at the cost of a bit of extra runtime
1634 stack usage in some cases.
1636 The problem is described in more detail at:
1637 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1639 Only Thumb-2 kernels are affected.
1641 Unless you are sure your tools don't have this problem, say Y.
1643 config ARM_ASM_UNIFIED
1647 bool "Use the ARM EABI to compile the kernel"
1649 This option allows for the kernel to be compiled using the latest
1650 ARM ABI (aka EABI). This is only useful if you are using a user
1651 space environment that is also compiled with EABI.
1653 Since there are major incompatibilities between the legacy ABI and
1654 EABI, especially with regard to structure member alignment, this
1655 option also changes the kernel syscall calling convention to
1656 disambiguate both ABIs and allow for backward compatibility support
1657 (selected with CONFIG_OABI_COMPAT).
1659 To use this you need GCC version 4.0.0 or later.
1662 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1663 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1666 This option preserves the old syscall interface along with the
1667 new (ARM EABI) one. It also provides a compatibility layer to
1668 intercept syscalls that have structure arguments which layout
1669 in memory differs between the legacy ABI and the new ARM EABI
1670 (only for non "thumb" binaries). This option adds a tiny
1671 overhead to all syscalls and produces a slightly larger kernel.
1672 If you know you'll be using only pure EABI user space then you
1673 can say N here. If this option is not selected and you attempt
1674 to execute a legacy ABI binary then the result will be
1675 UNPREDICTABLE (in fact it can be predicted that it won't work
1676 at all). If in doubt say Y.
1678 config ARCH_HAS_HOLES_MEMORYMODEL
1681 config ARCH_SPARSEMEM_ENABLE
1684 config ARCH_SPARSEMEM_DEFAULT
1685 def_bool ARCH_SPARSEMEM_ENABLE
1687 config ARCH_SELECT_MEMORY_MODEL
1688 def_bool ARCH_SPARSEMEM_ENABLE
1690 config HAVE_ARCH_PFN_VALID
1691 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1694 bool "High Memory Support"
1697 The address space of ARM processors is only 4 Gigabytes large
1698 and it has to accommodate user address space, kernel address
1699 space as well as some memory mapped IO. That means that, if you
1700 have a large amount of physical memory and/or IO, not all of the
1701 memory can be "permanently mapped" by the kernel. The physical
1702 memory that is not permanently mapped is called "high memory".
1704 Depending on the selected kernel/user memory split, minimum
1705 vmalloc space and actual amount of RAM, you may not need this
1706 option which should result in a slightly faster kernel.
1711 bool "Allocate 2nd-level pagetables from highmem"
1714 config HW_PERF_EVENTS
1715 bool "Enable hardware performance counter support for perf events"
1716 depends on PERF_EVENTS && CPU_HAS_PMU
1719 Enable hardware performance counter support for perf events. If
1720 disabled, perf events will use software events only.
1722 config SYS_SUPPORTS_HUGETLBFS
1724 depends on ARM_LPAE || (!CPU_USE_DOMAINS && !MEMORY_FAILURE)
1726 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1728 depends on SYS_SUPPORTS_HUGETLBFS
1732 config FORCE_MAX_ZONEORDER
1733 int "Maximum zone order" if ARCH_SHMOBILE
1734 range 11 64 if ARCH_SHMOBILE
1735 default "9" if SA1111
1738 The kernel memory allocator divides physically contiguous memory
1739 blocks into "zones", where each zone is a power of two number of
1740 pages. This option selects the largest power of two that the kernel
1741 keeps in the memory allocator. If you need to allocate very large
1742 blocks of physically contiguous memory, then you may need to
1743 increase this value.
1745 This config option is actually maximum order plus one. For example,
1746 a value of 11 means that the largest free memory block is 2^10 pages.
1749 bool "Timer and CPU usage LEDs"
1750 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1751 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1752 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1753 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1754 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1755 ARCH_AT91 || ARCH_DAVINCI || \
1756 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1758 If you say Y here, the LEDs on your machine will be used
1759 to provide useful information about your current system status.
1761 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1762 be able to select which LEDs are active using the options below. If
1763 you are compiling a kernel for the EBSA-110 or the LART however, the
1764 red LED will simply flash regularly to indicate that the system is
1765 still functional. It is safe to say Y here if you have a CATS
1766 system, but the driver will do nothing.
1769 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1770 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1771 || MACH_OMAP_PERSEUS2
1773 depends on !GENERIC_CLOCKEVENTS
1774 default y if ARCH_EBSA110
1776 If you say Y here, one of the system LEDs (the green one on the
1777 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1778 will flash regularly to indicate that the system is still
1779 operational. This is mainly useful to kernel hackers who are
1780 debugging unstable kernels.
1782 The LART uses the same LED for both Timer LED and CPU usage LED
1783 functions. You may choose to use both, but the Timer LED function
1784 will overrule the CPU usage LED.
1787 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1789 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1790 || MACH_OMAP_PERSEUS2
1793 If you say Y here, the red LED will be used to give a good real
1794 time indication of CPU usage, by lighting whenever the idle task
1795 is not currently executing.
1797 The LART uses the same LED for both Timer LED and CPU usage LED
1798 functions. You may choose to use both, but the Timer LED function
1799 will overrule the CPU usage LED.
1801 config ALIGNMENT_TRAP
1802 bool "Enable alignment trap"
1803 depends on CPU_CP15_MMU
1804 default y if !ARCH_EBSA110
1805 select HAVE_PROC_CPU if PROC_FS
1807 ARM processors cannot fetch/store information which is not
1808 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1809 address divisible by 4. On 32-bit ARM processors, these non-aligned
1810 fetch/store instructions will be emulated in software if you say
1811 here, which has a severe performance impact. This is necessary for
1812 correct operation of some network protocols. With an IP-only
1813 configuration it is safe to say N, otherwise say Y.
1815 config UACCESS_WITH_MEMCPY
1816 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1817 depends on MMU && EXPERIMENTAL
1818 default y if CPU_FEROCEON
1820 Implement faster copy_to_user and clear_user methods for CPU
1821 cores where a 8-word STM instruction give significantly higher
1822 memory write throughput than a sequence of individual 32bit stores.
1824 A possible side effect is a slight increase in scheduling latency
1825 between threads sharing the same address space if they invoke
1826 such copy operations with large buffers.
1828 However, if the CPU data cache is using a write-allocate mode,
1829 this option is unlikely to provide any performance gain.
1833 prompt "Enable seccomp to safely compute untrusted bytecode"
1835 This kernel feature is useful for number crunching applications
1836 that may need to compute untrusted bytecode during their
1837 execution. By using pipes or other transports made available to
1838 the process as file descriptors supporting the read/write
1839 syscalls, it's possible to isolate those applications in
1840 their own address space using seccomp. Once seccomp is
1841 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1842 and the task is only allowed to execute a few safe syscalls
1843 defined by each seccomp mode.
1845 config CC_STACKPROTECTOR
1846 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1847 depends on EXPERIMENTAL
1849 This option turns on the -fstack-protector GCC feature. This
1850 feature puts, at the beginning of functions, a canary value on
1851 the stack just before the return address, and validates
1852 the value just before actually returning. Stack based buffer
1853 overflows (that need to overwrite this return address) now also
1854 overwrite the canary, which gets detected and the attack is then
1855 neutralized via a kernel panic.
1856 This feature requires gcc version 4.2 or above.
1858 config DEPRECATED_PARAM_STRUCT
1859 bool "Provide old way to pass kernel parameters"
1861 This was deprecated in 2001 and announced to live on for 5 years.
1862 Some old boot loaders still use this way.
1866 depends on CPU_V7 && SYSFS
1874 bool "Flattened Device Tree support"
1876 select OF_EARLY_FLATTREE
1879 Include support for flattened device tree machine descriptions.
1881 # Compressed boot loader in ROM. Yes, we really want to ask about
1882 # TEXT and BSS so we preserve their values in the config files.
1883 config ZBOOT_ROM_TEXT
1884 hex "Compressed ROM boot loader base address"
1887 The physical address at which the ROM-able zImage is to be
1888 placed in the target. Platforms which normally make use of
1889 ROM-able zImage formats normally set this to a suitable
1890 value in their defconfig file.
1892 If ZBOOT_ROM is not enabled, this has no effect.
1894 config ZBOOT_ROM_BSS
1895 hex "Compressed ROM boot loader BSS address"
1898 The base address of an area of read/write memory in the target
1899 for the ROM-able zImage which must be available while the
1900 decompressor is running. It must be large enough to hold the
1901 entire decompressed kernel plus an additional 128 KiB.
1902 Platforms which normally make use of ROM-able zImage formats
1903 normally set this to a suitable value in their defconfig file.
1905 If ZBOOT_ROM is not enabled, this has no effect.
1908 bool "Compressed boot loader in ROM/flash"
1909 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1911 Say Y here if you intend to execute your compressed kernel image
1912 (zImage) directly from ROM or flash. If unsure, say N.
1915 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1916 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1917 default ZBOOT_ROM_NONE
1919 Include experimental SD/MMC loading code in the ROM-able zImage.
1920 With this enabled it is possible to write the the ROM-able zImage
1921 kernel image to an MMC or SD card and boot the kernel straight
1922 from the reset vector. At reset the processor Mask ROM will load
1923 the first part of the the ROM-able zImage which in turn loads the
1924 rest the kernel image to RAM.
1926 config ZBOOT_ROM_NONE
1927 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1929 Do not load image from SD or MMC
1931 config ZBOOT_ROM_MMCIF
1932 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1934 Load image from MMCIF hardware block.
1936 config ZBOOT_ROM_SH_MOBILE_SDHI
1937 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1939 Load image from SDHI hardware block
1943 config ARM_APPENDED_DTB
1944 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1945 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1947 With this option, the boot code will look for a device tree binary
1948 (DTB) appended to zImage
1949 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1951 This is meant as a backward compatibility convenience for those
1952 systems with a bootloader that can't be upgraded to accommodate
1953 the documented boot protocol using a device tree.
1955 Beware that there is very little in terms of protection against
1956 this option being confused by leftover garbage in memory that might
1957 look like a DTB header after a reboot if no actual DTB is appended
1958 to zImage. Do not leave this option active in a production kernel
1959 if you don't intend to always append a DTB. Proper passing of the
1960 location into r2 of a bootloader provided DTB is always preferable
1963 config ARM_ATAG_DTB_COMPAT
1964 bool "Supplement the appended DTB with traditional ATAG information"
1965 depends on ARM_APPENDED_DTB
1967 Some old bootloaders can't be updated to a DTB capable one, yet
1968 they provide ATAGs with memory configuration, the ramdisk address,
1969 the kernel cmdline string, etc. Such information is dynamically
1970 provided by the bootloader and can't always be stored in a static
1971 DTB. To allow a device tree enabled kernel to be used with such
1972 bootloaders, this option allows zImage to extract the information
1973 from the ATAG list and store it at run time into the appended DTB.
1976 string "Default kernel command string"
1979 On some architectures (EBSA110 and CATS), there is currently no way
1980 for the boot loader to pass arguments to the kernel. For these
1981 architectures, you should supply some command-line options at build
1982 time by entering them here. As a minimum, you should specify the
1983 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1986 prompt "Kernel command line type" if CMDLINE != ""
1987 default CMDLINE_FROM_BOOTLOADER
1989 config CMDLINE_FROM_BOOTLOADER
1990 bool "Use bootloader kernel arguments if available"
1992 Uses the command-line options passed by the boot loader. If
1993 the boot loader doesn't provide any, the default kernel command
1994 string provided in CMDLINE will be used.
1996 config CMDLINE_EXTEND
1997 bool "Extend bootloader kernel arguments"
1999 The command-line arguments provided by the boot loader will be
2000 appended to the default kernel command string.
2002 config CMDLINE_FORCE
2003 bool "Always use the default kernel command string"
2005 Always use the default kernel command string, even if the boot
2006 loader passes other arguments to the kernel.
2007 This is useful if you cannot or don't want to change the
2008 command-line options your boot loader passes to the kernel.
2012 bool "Kernel Execute-In-Place from ROM"
2013 depends on !ZBOOT_ROM && !ARM_LPAE
2015 Execute-In-Place allows the kernel to run from non-volatile storage
2016 directly addressable by the CPU, such as NOR flash. This saves RAM
2017 space since the text section of the kernel is not loaded from flash
2018 to RAM. Read-write sections, such as the data section and stack,
2019 are still copied to RAM. The XIP kernel is not compressed since
2020 it has to run directly from flash, so it will take more space to
2021 store it. The flash address used to link the kernel object files,
2022 and for storing it, is configuration dependent. Therefore, if you
2023 say Y here, you must know the proper physical address where to
2024 store the kernel image depending on your own flash memory usage.
2026 Also note that the make target becomes "make xipImage" rather than
2027 "make zImage" or "make Image". The final kernel binary to put in
2028 ROM memory will be arch/arm/boot/xipImage.
2032 config XIP_PHYS_ADDR
2033 hex "XIP Kernel Physical Location"
2034 depends on XIP_KERNEL
2035 default "0x00080000"
2037 This is the physical address in your flash memory the kernel will
2038 be linked for and stored to. This address is dependent on your
2042 bool "Kexec system call (EXPERIMENTAL)"
2043 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2045 kexec is a system call that implements the ability to shutdown your
2046 current kernel, and to start another kernel. It is like a reboot
2047 but it is independent of the system firmware. And like a reboot
2048 you can start any kernel with it, not just Linux.
2050 It is an ongoing process to be certain the hardware in a machine
2051 is properly shutdown, so do not be surprised if this code does not
2052 initially work for you. It may help to enable device hotplugging
2056 bool "Export atags in procfs"
2060 Should the atags used to boot the kernel be exported in an "atags"
2061 file in procfs. Useful with kexec.
2064 bool "Build kdump crash kernel (EXPERIMENTAL)"
2065 depends on EXPERIMENTAL
2067 Generate crash dump after being started by kexec. This should
2068 be normally only set in special crash dump kernels which are
2069 loaded in the main kernel with kexec-tools into a specially
2070 reserved region and then later executed after a crash by
2071 kdump/kexec. The crash dump kernel must be compiled to a
2072 memory address not used by the main kernel
2074 For more details see Documentation/kdump/kdump.txt
2076 config AUTO_ZRELADDR
2077 bool "Auto calculation of the decompressed kernel image address"
2078 depends on !ZBOOT_ROM && !ARCH_U300
2080 ZRELADDR is the physical address where the decompressed kernel
2081 image will be placed. If AUTO_ZRELADDR is selected, the address
2082 will be determined at run-time by masking the current IP with
2083 0xf8000000. This assumes the zImage being placed in the first 128MB
2084 from start of memory.
2088 menu "CPU Power Management"
2092 source "drivers/cpufreq/Kconfig"
2095 tristate "CPUfreq driver for i.MX CPUs"
2096 depends on ARCH_MXC && CPU_FREQ
2097 select CPU_FREQ_TABLE
2099 This enables the CPUfreq driver for i.MX CPUs.
2101 config CPU_FREQ_SA1100
2104 config CPU_FREQ_SA1110
2107 config CPU_FREQ_INTEGRATOR
2108 tristate "CPUfreq driver for ARM Integrator CPUs"
2109 depends on ARCH_INTEGRATOR && CPU_FREQ
2112 This enables the CPUfreq driver for ARM Integrator CPUs.
2114 For details, take a look at <file:Documentation/cpu-freq>.
2120 depends on CPU_FREQ && ARCH_PXA && PXA25x
2122 select CPU_FREQ_TABLE
2123 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2128 Internal configuration node for common cpufreq on Samsung SoC
2130 config CPU_FREQ_S3C24XX
2131 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2132 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2135 This enables the CPUfreq driver for the Samsung S3C24XX family
2138 For details, take a look at <file:Documentation/cpu-freq>.
2142 config CPU_FREQ_S3C24XX_PLL
2143 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2144 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2146 Compile in support for changing the PLL frequency from the
2147 S3C24XX series CPUfreq driver. The PLL takes time to settle
2148 after a frequency change, so by default it is not enabled.
2150 This also means that the PLL tables for the selected CPU(s) will
2151 be built which may increase the size of the kernel image.
2153 config CPU_FREQ_S3C24XX_DEBUG
2154 bool "Debug CPUfreq Samsung driver core"
2155 depends on CPU_FREQ_S3C24XX
2157 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2159 config CPU_FREQ_S3C24XX_IODEBUG
2160 bool "Debug CPUfreq Samsung driver IO timing"
2161 depends on CPU_FREQ_S3C24XX
2163 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2165 config CPU_FREQ_S3C24XX_DEBUGFS
2166 bool "Export debugfs for CPUFreq"
2167 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2169 Export status information via debugfs.
2173 source "drivers/cpuidle/Kconfig"
2177 menu "Floating point emulation"
2179 comment "At least one emulation must be selected"
2182 bool "NWFPE math emulation"
2183 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2185 Say Y to include the NWFPE floating point emulator in the kernel.
2186 This is necessary to run most binaries. Linux does not currently
2187 support floating point hardware so you need to say Y here even if
2188 your machine has an FPA or floating point co-processor podule.
2190 You may say N here if you are going to load the Acorn FPEmulator
2191 early in the bootup.
2194 bool "Support extended precision"
2195 depends on FPE_NWFPE
2197 Say Y to include 80-bit support in the kernel floating-point
2198 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2199 Note that gcc does not generate 80-bit operations by default,
2200 so in most cases this option only enlarges the size of the
2201 floating point emulator without any good reason.
2203 You almost surely want to say N here.
2206 bool "FastFPE math emulation (EXPERIMENTAL)"
2207 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2209 Say Y here to include the FAST floating point emulator in the kernel.
2210 This is an experimental much faster emulator which now also has full
2211 precision for the mantissa. It does not support any exceptions.
2212 It is very simple, and approximately 3-6 times faster than NWFPE.
2214 It should be sufficient for most programs. It may be not suitable
2215 for scientific calculations, but you have to check this for yourself.
2216 If you do not feel you need a faster FP emulation you should better
2220 bool "VFP-format floating point maths"
2221 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2223 Say Y to include VFP support code in the kernel. This is needed
2224 if your hardware includes a VFP unit.
2226 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2227 release notes and additional status information.
2229 Say N if your target does not have VFP hardware.
2237 bool "Advanced SIMD (NEON) Extension support"
2238 depends on VFPv3 && CPU_V7
2240 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2245 menu "Userspace binary formats"
2247 source "fs/Kconfig.binfmt"
2250 tristate "RISC OS personality"
2253 Say Y here to include the kernel code necessary if you want to run
2254 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2255 experimental; if this sounds frightening, say N and sleep in peace.
2256 You can also say M here to compile this support as a module (which
2257 will be called arthur).
2261 menu "Power management options"
2263 source "kernel/power/Kconfig"
2265 config ARCH_SUSPEND_POSSIBLE
2266 depends on !ARCH_S5PC100
2267 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2268 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2271 config ARM_CPU_SUSPEND
2276 source "net/Kconfig"
2278 source "drivers/Kconfig"
2282 source "arch/arm/Kconfig.debug"
2284 source "security/Kconfig"
2286 source "crypto/Kconfig"
2288 source "lib/Kconfig"