5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
41 config ARM_HAS_SG_CHAIN
50 config SYS_SUPPORTS_APM_EMULATION
53 config HAVE_SCHED_CLOCK
59 config ARCH_USES_GETTIMEOFFSET
63 config GENERIC_CLOCKEVENTS
66 config GENERIC_CLOCKEVENTS_BROADCAST
68 depends on GENERIC_CLOCKEVENTS
77 select GENERIC_ALLOCATOR
88 The Extended Industry Standard Architecture (EISA) bus was
89 developed as an open alternative to the IBM MicroChannel bus.
91 The EISA bus provided some of the features of the IBM MicroChannel
92 bus while maintaining backward compatibility with cards made for
93 the older ISA bus. The EISA bus saw limited use between 1988 and
94 1995 when it was made obsolete by the PCI bus.
96 Say Y here if you are building a kernel for an EISA-based machine.
106 MicroChannel Architecture is found in some IBM PS/2 machines and
107 laptops. It is a bus system similar to PCI or ISA. See
108 <file:Documentation/mca.txt> (and especially the web page given
109 there) before attempting to build an MCA bus kernel.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config HARDIRQS_SW_RESEND
132 config GENERIC_IRQ_PROBE
136 config GENERIC_LOCKBREAK
139 depends on SMP && PREEMPT
141 config RWSEM_GENERIC_SPINLOCK
145 config RWSEM_XCHGADD_ALGORITHM
148 config ARCH_HAS_ILOG2_U32
151 config ARCH_HAS_ILOG2_U64
154 config ARCH_HAS_CPUFREQ
157 Internal node to signify that the ARCH has CPUFREQ support
158 and that the relevant menu configurations are displayed for
161 config ARCH_HAS_CPU_IDLE_WAIT
164 config GENERIC_HWEIGHT
168 config GENERIC_CALIBRATE_DELAY
172 config ARCH_MAY_HAVE_PC_FDC
178 config NEED_DMA_MAP_STATE
181 config GENERIC_ISA_DMA
192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
193 default DRAM_BASE if REMAP_VECTORS_TO_RAM
196 The base address of exception vectors.
198 config ARM_PATCH_PHYS_VIRT
199 bool "Patch physical to virtual translations at runtime" if EMBEDDED
201 depends on !XIP_KERNEL && MMU
202 depends on !ARCH_REALVIEW || !SPARSEMEM
204 Patch phys-to-virt and virt-to-phys translation functions at
205 boot and module load time according to the position of the
206 kernel in system memory.
208 This can only be used with non-XIP MMU kernels where the base
209 of physical memory is at a 16MB boundary.
211 Only disable this option if you know that you do not require
212 this feature (eg, building a kernel for a single machine) and
213 you need to shrink the kernel to the minimal size.
215 config NEED_MACH_MEMORY_H
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
223 hex "Physical address of main memory" if MMU
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
225 default DRAM_BASE if !MMU
227 Please provide the physical address corresponding to the
228 location of main memory in your system.
234 source "init/Kconfig"
236 source "kernel/Kconfig.freezer"
241 bool "MMU-based Paged Memory Management Support"
244 Select if you want MMU-based virtualised addressing space
245 support by paged memory management. If unsure, say 'Y'.
248 # The "ARM system type" choice list is ordered alphabetically by option
249 # text. Please add new entries in the option alphabetic order.
252 prompt "ARM system type"
253 default ARCH_VERSATILE
255 config ARCH_INTEGRATOR
256 bool "ARM Ltd. Integrator family"
258 select ARCH_HAS_CPUFREQ
260 select HAVE_MACH_CLKDEV
262 select GENERIC_CLOCKEVENTS
263 select PLAT_VERSATILE
264 select PLAT_VERSATILE_FPGA_IRQ
265 select NEED_MACH_MEMORY_H
267 Support for ARM's Integrator platform.
270 bool "ARM Ltd. RealView family"
273 select HAVE_MACH_CLKDEV
275 select GENERIC_CLOCKEVENTS
276 select ARCH_WANT_OPTIONAL_GPIOLIB
277 select PLAT_VERSATILE
278 select PLAT_VERSATILE_CLCD
279 select ARM_TIMER_SP804
280 select GPIO_PL061 if GPIOLIB
281 select NEED_MACH_MEMORY_H
283 This enables support for ARM Ltd RealView boards.
285 config ARCH_VERSATILE
286 bool "ARM Ltd. Versatile family"
290 select HAVE_MACH_CLKDEV
292 select GENERIC_CLOCKEVENTS
293 select ARCH_WANT_OPTIONAL_GPIOLIB
294 select PLAT_VERSATILE
295 select PLAT_VERSATILE_CLCD
296 select PLAT_VERSATILE_FPGA_IRQ
297 select ARM_TIMER_SP804
299 This enables support for ARM Ltd Versatile board.
302 bool "ARM Ltd. Versatile Express family"
303 select ARCH_WANT_OPTIONAL_GPIOLIB
305 select ARM_TIMER_SP804
307 select HAVE_MACH_CLKDEV
308 select GENERIC_CLOCKEVENTS
310 select HAVE_PATA_PLATFORM
312 select PLAT_VERSATILE
313 select PLAT_VERSATILE_CLCD
315 This enables support for the ARM Ltd Versatile Express boards.
319 select ARCH_REQUIRE_GPIOLIB
323 This enables support for systems based on the Atmel AT91RM9200,
324 AT91SAM9 and AT91CAP9 processors.
327 bool "Broadcom BCMRING"
331 select ARM_TIMER_SP804
333 select GENERIC_CLOCKEVENTS
334 select ARCH_WANT_OPTIONAL_GPIOLIB
336 Support for Broadcom's BCMRing platform.
339 bool "Calxeda Highbank-based"
340 select ARCH_WANT_OPTIONAL_GPIOLIB
343 select ARM_TIMER_SP804
346 select GENERIC_CLOCKEVENTS
350 Support for the Calxeda Highbank SoC based boards.
353 bool "Cirrus Logic CLPS711x/EP721x-based"
355 select ARCH_USES_GETTIMEOFFSET
356 select NEED_MACH_MEMORY_H
358 Support for Cirrus Logic 711x/721x based boards.
361 bool "Cavium Networks CNS3XXX family"
363 select GENERIC_CLOCKEVENTS
365 select MIGHT_HAVE_PCI
366 select PCI_DOMAINS if PCI
368 Support for Cavium Networks CNS3XXX platform.
371 bool "Cortina Systems Gemini"
373 select ARCH_REQUIRE_GPIOLIB
374 select ARCH_USES_GETTIMEOFFSET
376 Support for the Cortina Systems Gemini family SoCs
379 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
382 select GENERIC_CLOCKEVENTS
384 select GENERIC_IRQ_CHIP
388 Support for CSR SiRFSoC ARM Cortex A9 Platform
395 select ARCH_USES_GETTIMEOFFSET
396 select NEED_MACH_MEMORY_H
398 This is an evaluation board for the StrongARM processor available
399 from Digital. It has limited hardware on-board, including an
400 Ethernet interface, two PCMCIA sockets, two serial ports and a
409 select ARCH_REQUIRE_GPIOLIB
410 select ARCH_HAS_HOLES_MEMORYMODEL
411 select ARCH_USES_GETTIMEOFFSET
412 select NEED_MACH_MEMORY_H
414 This enables support for the Cirrus EP93xx series of CPUs.
416 config ARCH_FOOTBRIDGE
420 select GENERIC_CLOCKEVENTS
422 select NEED_MACH_MEMORY_H
424 Support for systems based on the DC21285 companion chip
425 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
428 bool "Freescale MXC/iMX-based"
429 select GENERIC_CLOCKEVENTS
430 select ARCH_REQUIRE_GPIOLIB
433 select GENERIC_IRQ_CHIP
434 select HAVE_SCHED_CLOCK
435 select MULTI_IRQ_HANDLER
437 Support for Freescale MXC/iMX-based family of processors
440 bool "Freescale MXS-based"
441 select GENERIC_CLOCKEVENTS
442 select ARCH_REQUIRE_GPIOLIB
446 Support for Freescale MXS-based family of processors
449 bool "Hilscher NetX based"
453 select GENERIC_CLOCKEVENTS
455 This enables support for systems based on the Hilscher NetX Soc
458 bool "Hynix HMS720x-based"
461 select ARCH_USES_GETTIMEOFFSET
463 This enables support for systems based on the Hynix HMS720x
471 select ARCH_SUPPORTS_MSI
473 select NEED_MACH_MEMORY_H
475 Support for Intel's IOP13XX (XScale) family of processors.
483 select ARCH_REQUIRE_GPIOLIB
485 Support for Intel's 80219 and IOP32X (XScale) family of
494 select ARCH_REQUIRE_GPIOLIB
496 Support for Intel's IOP33X (XScale) family of processors.
503 select ARCH_USES_GETTIMEOFFSET
504 select NEED_MACH_MEMORY_H
506 Support for Intel's IXP23xx (XScale) family of processors.
509 bool "IXP2400/2800-based"
513 select ARCH_USES_GETTIMEOFFSET
514 select NEED_MACH_MEMORY_H
516 Support for Intel's IXP2400/2800 (XScale) family of processors.
523 select ARCH_REQUIRE_GPIOLIB
524 select GENERIC_CLOCKEVENTS
525 select HAVE_SCHED_CLOCK
526 select MIGHT_HAVE_PCI
527 select DMABOUNCE if PCI
529 Support for Intel's IXP4XX (XScale) family of processors.
535 select ARCH_REQUIRE_GPIOLIB
536 select GENERIC_CLOCKEVENTS
539 Support for the Marvell Dove SoC 88AP510
542 bool "Marvell Kirkwood"
545 select ARCH_REQUIRE_GPIOLIB
546 select GENERIC_CLOCKEVENTS
549 Support for the following Marvell Kirkwood series SoCs:
550 88F6180, 88F6192 and 88F6281.
556 select ARCH_REQUIRE_GPIOLIB
559 select USB_ARCH_HAS_OHCI
561 select GENERIC_CLOCKEVENTS
563 Support for the NXP LPC32XX family of processors
566 bool "Marvell MV78xx0"
569 select ARCH_REQUIRE_GPIOLIB
570 select GENERIC_CLOCKEVENTS
573 Support for the following Marvell MV78xx0 series SoCs:
581 select ARCH_REQUIRE_GPIOLIB
582 select GENERIC_CLOCKEVENTS
585 Support for the following Marvell Orion 5x series SoCs:
586 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
587 Orion-2 (5281), Orion-1-90 (6183).
590 bool "Marvell PXA168/910/MMP2"
592 select ARCH_REQUIRE_GPIOLIB
594 select GENERIC_CLOCKEVENTS
595 select HAVE_SCHED_CLOCK
599 select GENERIC_ALLOCATOR
601 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
604 bool "Micrel/Kendin KS8695"
606 select ARCH_REQUIRE_GPIOLIB
607 select ARCH_USES_GETTIMEOFFSET
608 select NEED_MACH_MEMORY_H
610 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
611 System-on-Chip devices.
614 bool "Nuvoton W90X900 CPU"
616 select ARCH_REQUIRE_GPIOLIB
619 select GENERIC_CLOCKEVENTS
621 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
622 At present, the w90x900 has been renamed nuc900, regarding
623 the ARM series product line, you can login the following
624 link address to know more.
626 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
627 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
633 select GENERIC_CLOCKEVENTS
636 select HAVE_SCHED_CLOCK
637 select ARCH_HAS_CPUFREQ
639 This enables support for NVIDIA Tegra based systems (Tegra APX,
640 Tegra 6xx and Tegra 2 series).
642 config ARCH_PICOXCELL
643 bool "Picochip picoXcell"
644 select ARCH_REQUIRE_GPIOLIB
645 select ARM_PATCH_PHYS_VIRT
649 select GENERIC_CLOCKEVENTS
651 select HAVE_SCHED_CLOCK
656 This enables support for systems based on the Picochip picoXcell
657 family of Femtocell devices. The picoxcell support requires device tree
661 bool "Philips Nexperia PNX4008 Mobile"
664 select ARCH_USES_GETTIMEOFFSET
666 This enables support for Philips PNX4008 mobile platform.
669 bool "PXA2xx/PXA3xx-based"
672 select ARCH_HAS_CPUFREQ
675 select ARCH_REQUIRE_GPIOLIB
676 select GENERIC_CLOCKEVENTS
677 select HAVE_SCHED_CLOCK
682 select MULTI_IRQ_HANDLER
683 select ARM_CPU_SUSPEND if PM
686 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
691 select GENERIC_CLOCKEVENTS
692 select ARCH_REQUIRE_GPIOLIB
695 Support for Qualcomm MSM/QSD based systems. This runs on the
696 apps processor of the MSM/QSD and depends on a shared memory
697 interface to the modem processor which runs the baseband
698 stack and controls some vital subsystems
699 (clock and power control, etc).
702 bool "Renesas SH-Mobile / R-Mobile"
705 select HAVE_MACH_CLKDEV
706 select GENERIC_CLOCKEVENTS
709 select MULTI_IRQ_HANDLER
710 select PM_GENERIC_DOMAINS if PM
711 select NEED_MACH_MEMORY_H
713 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
720 select ARCH_MAY_HAVE_PC_FDC
721 select HAVE_PATA_PLATFORM
724 select ARCH_SPARSEMEM_ENABLE
725 select ARCH_USES_GETTIMEOFFSET
727 select NEED_MACH_MEMORY_H
729 On the Acorn Risc-PC, Linux can support the internal IDE disk and
730 CD-ROM interface, serial and parallel port, and the floppy drive.
737 select ARCH_SPARSEMEM_ENABLE
739 select ARCH_HAS_CPUFREQ
741 select GENERIC_CLOCKEVENTS
743 select HAVE_SCHED_CLOCK
745 select ARCH_REQUIRE_GPIOLIB
747 select NEED_MACH_MEMORY_H
749 Support for StrongARM 11x0 based boards.
752 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
754 select ARCH_HAS_CPUFREQ
757 select ARCH_USES_GETTIMEOFFSET
758 select HAVE_S3C2410_I2C if I2C
760 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
761 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
762 the Samsung SMDK2410 development board (and derivatives).
764 Note, the S3C2416 and the S3C2450 are so close that they even share
765 the same SoC ID code. This means that there is no separate machine
766 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
769 bool "Samsung S3C64XX"
777 select ARCH_USES_GETTIMEOFFSET
778 select ARCH_HAS_CPUFREQ
779 select ARCH_REQUIRE_GPIOLIB
780 select SAMSUNG_CLKSRC
781 select SAMSUNG_IRQ_VIC_TIMER
782 select S3C_GPIO_TRACK
784 select USB_ARCH_HAS_OHCI
785 select SAMSUNG_GPIOLIB_4BIT
786 select HAVE_S3C2410_I2C if I2C
787 select HAVE_S3C2410_WATCHDOG if WATCHDOG
789 Samsung S3C64XX series based systems
792 bool "Samsung S5P6440 S5P6450"
798 select HAVE_S3C2410_WATCHDOG if WATCHDOG
799 select GENERIC_CLOCKEVENTS
800 select HAVE_SCHED_CLOCK
801 select HAVE_S3C2410_I2C if I2C
802 select HAVE_S3C_RTC if RTC_CLASS
804 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
808 bool "Samsung S5PC100"
813 select ARM_L1_CACHE_SHIFT_6
814 select ARCH_USES_GETTIMEOFFSET
815 select HAVE_S3C2410_I2C if I2C
816 select HAVE_S3C_RTC if RTC_CLASS
817 select HAVE_S3C2410_WATCHDOG if WATCHDOG
819 Samsung S5PC100 series based systems
822 bool "Samsung S5PV210/S5PC110"
824 select ARCH_SPARSEMEM_ENABLE
825 select ARCH_HAS_HOLES_MEMORYMODEL
830 select ARM_L1_CACHE_SHIFT_6
831 select ARCH_HAS_CPUFREQ
832 select GENERIC_CLOCKEVENTS
833 select HAVE_SCHED_CLOCK
834 select HAVE_S3C2410_I2C if I2C
835 select HAVE_S3C_RTC if RTC_CLASS
836 select HAVE_S3C2410_WATCHDOG if WATCHDOG
837 select NEED_MACH_MEMORY_H
839 Samsung S5PV210/S5PC110 series based systems
842 bool "SAMSUNG EXYNOS"
844 select ARCH_SPARSEMEM_ENABLE
845 select ARCH_HAS_HOLES_MEMORYMODEL
849 select ARCH_HAS_CPUFREQ
850 select GENERIC_CLOCKEVENTS
851 select HAVE_S3C_RTC if RTC_CLASS
852 select HAVE_S3C2410_I2C if I2C
853 select HAVE_S3C2410_WATCHDOG if WATCHDOG
854 select NEED_MACH_MEMORY_H
856 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
865 select ARCH_USES_GETTIMEOFFSET
866 select NEED_MACH_MEMORY_H
868 Support for the StrongARM based Digital DNARD machine, also known
869 as "Shark" (<http://www.shark-linux.de/shark.html>).
872 bool "Telechips TCC ARM926-based systems"
877 select GENERIC_CLOCKEVENTS
879 Support for Telechips TCC ARM926-based systems.
882 bool "ST-Ericsson U300 Series"
886 select HAVE_SCHED_CLOCK
889 select ARM_PATCH_PHYS_VIRT
891 select GENERIC_CLOCKEVENTS
893 select HAVE_MACH_CLKDEV
895 select ARCH_REQUIRE_GPIOLIB
896 select NEED_MACH_MEMORY_H
898 Support for ST-Ericsson U300 series mobile platforms.
901 bool "ST-Ericsson U8500 Series"
904 select GENERIC_CLOCKEVENTS
906 select ARCH_REQUIRE_GPIOLIB
907 select ARCH_HAS_CPUFREQ
909 Support for ST-Ericsson's Ux500 architecture
912 bool "STMicroelectronics Nomadik"
917 select GENERIC_CLOCKEVENTS
918 select ARCH_REQUIRE_GPIOLIB
920 Support for the Nomadik platform by ST-Ericsson
924 select GENERIC_CLOCKEVENTS
925 select ARCH_REQUIRE_GPIOLIB
929 select GENERIC_ALLOCATOR
930 select GENERIC_IRQ_CHIP
931 select ARCH_HAS_HOLES_MEMORYMODEL
933 Support for TI's DaVinci platform.
938 select ARCH_REQUIRE_GPIOLIB
939 select ARCH_HAS_CPUFREQ
941 select GENERIC_CLOCKEVENTS
942 select HAVE_SCHED_CLOCK
943 select ARCH_HAS_HOLES_MEMORYMODEL
945 Support for TI's OMAP platform (OMAP1/2/3/4).
950 select ARCH_REQUIRE_GPIOLIB
953 select GENERIC_CLOCKEVENTS
956 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
959 bool "VIA/WonderMedia 85xx"
962 select ARCH_HAS_CPUFREQ
963 select GENERIC_CLOCKEVENTS
964 select ARCH_REQUIRE_GPIOLIB
967 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
970 bool "Xilinx Zynq ARM Cortex A9 Platform"
972 select GENERIC_CLOCKEVENTS
979 Support for Xilinx Zynq ARM Cortex A9 Platform
982 config SYS_SUPPORTS_HUGETLBFS
985 config ARM_HUGETLB_SUPPORT
986 bool "Support HUGETLB for ARMv7 (EXPERIMENTAL)"
987 depends on CPU_V7 && EXPERIMENTAL
988 select SYS_SUPPORTS_HUGETLBFS
993 prompt "Huge Page Size"
994 depends on ARM_HUGETLB_SUPPORT
995 default HUGEPAGE_SIZE_2MB
997 config HUGEPAGE_SIZE_2MB
999 depends on ARM_HUGETLB_SUPPORT
1001 This option select huge page size in 2MB units
1003 config HUGEPAGE_SIZE_16MB
1005 depends on ARM_HUGETLB_SUPPORT
1007 This option select huge page size in 16MB units
1012 # This is sorted alphabetically by mach-* pathname. However, plat-*
1013 # Kconfigs may be included either alphabetically (according to the
1014 # plat- suffix) or along side the corresponding mach-* source.
1016 source "arch/arm/mach-at91/Kconfig"
1018 source "arch/arm/mach-bcmring/Kconfig"
1020 source "arch/arm/mach-clps711x/Kconfig"
1022 source "arch/arm/mach-cns3xxx/Kconfig"
1024 source "arch/arm/mach-davinci/Kconfig"
1026 source "arch/arm/mach-dove/Kconfig"
1028 source "arch/arm/mach-ep93xx/Kconfig"
1030 source "arch/arm/mach-footbridge/Kconfig"
1032 source "arch/arm/mach-gemini/Kconfig"
1034 source "arch/arm/mach-h720x/Kconfig"
1036 source "arch/arm/mach-integrator/Kconfig"
1038 source "arch/arm/mach-iop32x/Kconfig"
1040 source "arch/arm/mach-iop33x/Kconfig"
1042 source "arch/arm/mach-iop13xx/Kconfig"
1044 source "arch/arm/mach-ixp4xx/Kconfig"
1046 source "arch/arm/mach-ixp2000/Kconfig"
1048 source "arch/arm/mach-ixp23xx/Kconfig"
1050 source "arch/arm/mach-kirkwood/Kconfig"
1052 source "arch/arm/mach-ks8695/Kconfig"
1054 source "arch/arm/mach-lpc32xx/Kconfig"
1056 source "arch/arm/mach-msm/Kconfig"
1058 source "arch/arm/mach-mv78xx0/Kconfig"
1060 source "arch/arm/plat-mxc/Kconfig"
1062 source "arch/arm/mach-mxs/Kconfig"
1064 source "arch/arm/mach-netx/Kconfig"
1066 source "arch/arm/mach-nomadik/Kconfig"
1067 source "arch/arm/plat-nomadik/Kconfig"
1069 source "arch/arm/plat-omap/Kconfig"
1071 source "arch/arm/mach-omap1/Kconfig"
1073 source "arch/arm/mach-omap2/Kconfig"
1075 source "arch/arm/mach-orion5x/Kconfig"
1077 source "arch/arm/mach-pxa/Kconfig"
1078 source "arch/arm/plat-pxa/Kconfig"
1080 source "arch/arm/mach-mmp/Kconfig"
1082 source "arch/arm/mach-realview/Kconfig"
1084 source "arch/arm/mach-sa1100/Kconfig"
1086 source "arch/arm/plat-samsung/Kconfig"
1087 source "arch/arm/plat-s3c24xx/Kconfig"
1088 source "arch/arm/plat-s5p/Kconfig"
1090 source "arch/arm/plat-spear/Kconfig"
1092 source "arch/arm/plat-tcc/Kconfig"
1095 source "arch/arm/mach-s3c2410/Kconfig"
1096 source "arch/arm/mach-s3c2412/Kconfig"
1097 source "arch/arm/mach-s3c2416/Kconfig"
1098 source "arch/arm/mach-s3c2440/Kconfig"
1099 source "arch/arm/mach-s3c2443/Kconfig"
1103 source "arch/arm/mach-s3c64xx/Kconfig"
1106 source "arch/arm/mach-s5p64x0/Kconfig"
1108 source "arch/arm/mach-s5pc100/Kconfig"
1110 source "arch/arm/mach-s5pv210/Kconfig"
1112 source "arch/arm/mach-exynos/Kconfig"
1114 source "arch/arm/mach-shmobile/Kconfig"
1116 source "arch/arm/mach-tegra/Kconfig"
1118 source "arch/arm/mach-u300/Kconfig"
1120 source "arch/arm/mach-ux500/Kconfig"
1122 source "arch/arm/mach-versatile/Kconfig"
1124 source "arch/arm/mach-vexpress/Kconfig"
1125 source "arch/arm/plat-versatile/Kconfig"
1127 source "arch/arm/mach-vt8500/Kconfig"
1129 source "arch/arm/mach-w90x900/Kconfig"
1131 # Definitions to make life easier
1137 select GENERIC_CLOCKEVENTS
1138 select HAVE_SCHED_CLOCK
1143 select GENERIC_IRQ_CHIP
1144 select HAVE_SCHED_CLOCK
1149 config PLAT_VERSATILE
1152 config ARM_TIMER_SP804
1156 source arch/arm/mm/Kconfig
1159 bool "Enable iWMMXt support"
1160 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1161 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1163 Enable support for iWMMXt context switching at run time if
1164 running on a CPU that supports it.
1166 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1169 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1173 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1174 (!ARCH_OMAP3 || OMAP3_EMU)
1178 config MULTI_IRQ_HANDLER
1181 Allow each machine to specify it's own IRQ handler at run time.
1184 source "arch/arm/Kconfig-nommu"
1187 config ARM_ERRATA_326103
1188 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1191 Executing a SWP instruction to read-only memory does not set bit 11
1192 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1193 treat the access as a read, preventing a COW from occurring and
1194 causing the faulting task to livelock.
1196 config ARM_ERRATA_411920
1197 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1198 depends on CPU_V6 || CPU_V6K
1200 Invalidation of the Instruction Cache operation can
1201 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1202 It does not affect the MPCore. This option enables the ARM Ltd.
1203 recommended workaround.
1205 config ARM_ERRATA_430973
1206 bool "ARM errata: Stale prediction on replaced interworking branch"
1209 This option enables the workaround for the 430973 Cortex-A8
1210 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1211 interworking branch is replaced with another code sequence at the
1212 same virtual address, whether due to self-modifying code or virtual
1213 to physical address re-mapping, Cortex-A8 does not recover from the
1214 stale interworking branch prediction. This results in Cortex-A8
1215 executing the new code sequence in the incorrect ARM or Thumb state.
1216 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1217 and also flushes the branch target cache at every context switch.
1218 Note that setting specific bits in the ACTLR register may not be
1219 available in non-secure mode.
1221 config ARM_ERRATA_458693
1222 bool "ARM errata: Processor deadlock when a false hazard is created"
1225 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1226 erratum. For very specific sequences of memory operations, it is
1227 possible for a hazard condition intended for a cache line to instead
1228 be incorrectly associated with a different cache line. This false
1229 hazard might then cause a processor deadlock. The workaround enables
1230 the L1 caching of the NEON accesses and disables the PLD instruction
1231 in the ACTLR register. Note that setting specific bits in the ACTLR
1232 register may not be available in non-secure mode.
1234 config ARM_ERRATA_460075
1235 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1238 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1239 erratum. Any asynchronous access to the L2 cache may encounter a
1240 situation in which recent store transactions to the L2 cache are lost
1241 and overwritten with stale memory contents from external memory. The
1242 workaround disables the write-allocate mode for the L2 cache via the
1243 ACTLR register. Note that setting specific bits in the ACTLR register
1244 may not be available in non-secure mode.
1246 config ARM_ERRATA_742230
1247 bool "ARM errata: DMB operation may be faulty"
1248 depends on CPU_V7 && SMP
1250 This option enables the workaround for the 742230 Cortex-A9
1251 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1252 between two write operations may not ensure the correct visibility
1253 ordering of the two writes. This workaround sets a specific bit in
1254 the diagnostic register of the Cortex-A9 which causes the DMB
1255 instruction to behave as a DSB, ensuring the correct behaviour of
1258 config ARM_ERRATA_742231
1259 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1260 depends on CPU_V7 && SMP
1262 This option enables the workaround for the 742231 Cortex-A9
1263 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1264 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1265 accessing some data located in the same cache line, may get corrupted
1266 data due to bad handling of the address hazard when the line gets
1267 replaced from one of the CPUs at the same time as another CPU is
1268 accessing it. This workaround sets specific bits in the diagnostic
1269 register of the Cortex-A9 which reduces the linefill issuing
1270 capabilities of the processor.
1272 config PL310_ERRATA_588369
1273 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1274 depends on CACHE_L2X0
1276 The PL310 L2 cache controller implements three types of Clean &
1277 Invalidate maintenance operations: by Physical Address
1278 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1279 They are architecturally defined to behave as the execution of a
1280 clean operation followed immediately by an invalidate operation,
1281 both performing to the same memory location. This functionality
1282 is not correctly implemented in PL310 as clean lines are not
1283 invalidated as a result of these operations.
1285 config ARM_ERRATA_720789
1286 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1289 This option enables the workaround for the 720789 Cortex-A9 (prior to
1290 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1291 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1292 As a consequence of this erratum, some TLB entries which should be
1293 invalidated are not, resulting in an incoherency in the system page
1294 tables. The workaround changes the TLB flushing routines to invalidate
1295 entries regardless of the ASID.
1297 config PL310_ERRATA_727915
1298 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1299 depends on CACHE_L2X0
1301 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1302 operation (offset 0x7FC). This operation runs in background so that
1303 PL310 can handle normal accesses while it is in progress. Under very
1304 rare circumstances, due to this erratum, write data can be lost when
1305 PL310 treats a cacheable write transaction during a Clean &
1306 Invalidate by Way operation.
1308 config ARM_ERRATA_743622
1309 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1312 This option enables the workaround for the 743622 Cortex-A9
1313 (r2p*) erratum. Under very rare conditions, a faulty
1314 optimisation in the Cortex-A9 Store Buffer may lead to data
1315 corruption. This workaround sets a specific bit in the diagnostic
1316 register of the Cortex-A9 which disables the Store Buffer
1317 optimisation, preventing the defect from occurring. This has no
1318 visible impact on the overall performance or power consumption of the
1321 config ARM_ERRATA_751472
1322 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1325 This option enables the workaround for the 751472 Cortex-A9 (prior
1326 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1327 completion of a following broadcasted operation if the second
1328 operation is received by a CPU before the ICIALLUIS has completed,
1329 potentially leading to corrupted entries in the cache or TLB.
1331 config PL310_ERRATA_753970
1332 bool "PL310 errata: cache sync operation may be faulty"
1333 depends on CACHE_PL310
1335 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1337 Under some condition the effect of cache sync operation on
1338 the store buffer still remains when the operation completes.
1339 This means that the store buffer is always asked to drain and
1340 this prevents it from merging any further writes. The workaround
1341 is to replace the normal offset of cache sync operation (0x730)
1342 by another offset targeting an unmapped PL310 register 0x740.
1343 This has the same effect as the cache sync operation: store buffer
1344 drain and waiting for all buffers empty.
1346 config ARM_ERRATA_754322
1347 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1350 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1351 r3p*) erratum. A speculative memory access may cause a page table walk
1352 which starts prior to an ASID switch but completes afterwards. This
1353 can populate the micro-TLB with a stale entry which may be hit with
1354 the new ASID. This workaround places two dsb instructions in the mm
1355 switching code so that no page table walks can cross the ASID switch.
1357 config ARM_ERRATA_754327
1358 bool "ARM errata: no automatic Store Buffer drain"
1359 depends on CPU_V7 && SMP
1361 This option enables the workaround for the 754327 Cortex-A9 (prior to
1362 r2p0) erratum. The Store Buffer does not have any automatic draining
1363 mechanism and therefore a livelock may occur if an external agent
1364 continuously polls a memory location waiting to observe an update.
1365 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1366 written polling loops from denying visibility of updates to memory.
1368 config ARM_ERRATA_364296
1369 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1370 depends on CPU_V6 && !SMP
1372 This options enables the workaround for the 364296 ARM1136
1373 r0p2 erratum (possible cache data corruption with
1374 hit-under-miss enabled). It sets the undocumented bit 31 in
1375 the auxiliary control register and the FI bit in the control
1376 register, thus disabling hit-under-miss without putting the
1377 processor into full low interrupt latency mode. ARM11MPCore
1380 config ARM_ERRATA_764369
1381 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1382 depends on CPU_V7 && SMP
1384 This option enables the workaround for erratum 764369
1385 affecting Cortex-A9 MPCore with two or more processors (all
1386 current revisions). Under certain timing circumstances, a data
1387 cache line maintenance operation by MVA targeting an Inner
1388 Shareable memory region may fail to proceed up to either the
1389 Point of Coherency or to the Point of Unification of the
1390 system. This workaround adds a DSB instruction before the
1391 relevant cache maintenance functions and sets a specific bit
1392 in the diagnostic control register of the SCU.
1394 config PL310_ERRATA_769419
1395 bool "PL310 errata: no automatic Store Buffer drain"
1396 depends on CACHE_L2X0
1398 On revisions of the PL310 prior to r3p2, the Store Buffer does
1399 not automatically drain. This can cause normal, non-cacheable
1400 writes to be retained when the memory system is idle, leading
1401 to suboptimal I/O performance for drivers using coherent DMA.
1402 This option adds a write barrier to the cpu_idle loop so that,
1403 on systems with an outer cache, the store buffer is drained
1408 source "arch/arm/common/Kconfig"
1418 Find out whether you have ISA slots on your motherboard. ISA is the
1419 name of a bus system, i.e. the way the CPU talks to the other stuff
1420 inside your box. Other bus systems are PCI, EISA, MicroChannel
1421 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1422 newer boards don't support it. If you have ISA, say Y, otherwise N.
1424 # Select ISA DMA controller support
1429 # Select ISA DMA interface
1434 bool "PCI support" if MIGHT_HAVE_PCI
1436 Find out whether you have a PCI motherboard. PCI is the name of a
1437 bus system, i.e. the way the CPU talks to the other stuff inside
1438 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1439 VESA. If you have PCI, say Y, otherwise N.
1445 config PCI_NANOENGINE
1446 bool "BSE nanoEngine PCI support"
1447 depends on SA1100_NANOENGINE
1449 Enable PCI on the BSE nanoEngine board.
1454 # Select the host bridge type
1455 config PCI_HOST_VIA82C505
1457 depends on PCI && ARCH_SHARK
1460 config PCI_HOST_ITE8152
1462 depends on PCI && MACH_ARMCORE
1466 source "drivers/pci/Kconfig"
1468 source "drivers/pcmcia/Kconfig"
1472 menu "Kernel Features"
1474 source "kernel/time/Kconfig"
1477 bool "Symmetric Multi-Processing"
1478 depends on CPU_V6K || CPU_V7
1479 depends on GENERIC_CLOCKEVENTS
1480 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1481 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1482 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1483 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
1485 select USE_GENERIC_SMP_HELPERS
1486 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1488 This enables support for systems with more than one CPU. If you have
1489 a system with only one CPU, like most personal computers, say N. If
1490 you have a system with more than one CPU, say Y.
1492 If you say N here, the kernel will run on single and multiprocessor
1493 machines, but will use only one CPU of a multiprocessor machine. If
1494 you say Y here, the kernel will run on many, but not all, single
1495 processor machines. On a single processor machine, the kernel will
1496 run faster if you say N here.
1498 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1499 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1500 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1502 If you don't know what to do here, say N.
1505 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1506 depends on EXPERIMENTAL
1507 depends on SMP && !XIP_KERNEL
1510 SMP kernels contain instructions which fail on non-SMP processors.
1511 Enabling this option allows the kernel to modify itself to make
1512 these instructions safe. Disabling it allows about 1K of space
1515 If you don't know what to do here, say Y.
1517 config ARM_CPU_TOPOLOGY
1518 bool "Support cpu topology definition"
1519 depends on SMP && CPU_V7
1522 Support ARM cpu topology definition. The MPIDR register defines
1523 affinity between processors which is then used to describe the cpu
1524 topology of an ARM System.
1527 bool "Multi-core scheduler support"
1528 depends on ARM_CPU_TOPOLOGY
1530 Multi-core scheduler support improves the CPU scheduler's decision
1531 making when dealing with multi-core CPU chips at a cost of slightly
1532 increased overhead in some places. If unsure say N here.
1535 bool "SMT scheduler support"
1536 depends on ARM_CPU_TOPOLOGY
1538 Improves the CPU scheduler's decision making when dealing with
1539 MultiThreading at a cost of slightly increased overhead in some
1540 places. If unsure say N here.
1545 This option enables support for the ARM system coherency unit
1552 This options enables support for the ARM timer and watchdog unit
1555 prompt "Memory split"
1558 Select the desired split between kernel and user memory.
1560 If you are not absolutely sure what you are doing, leave this
1564 bool "3G/1G user/kernel split"
1566 bool "2G/2G user/kernel split"
1568 bool "1G/3G user/kernel split"
1573 default 0x40000000 if VMSPLIT_1G
1574 default 0x80000000 if VMSPLIT_2G
1578 int "Maximum number of CPUs (2-32)"
1584 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1585 depends on SMP && HOTPLUG && EXPERIMENTAL
1587 Say Y here to experiment with turning CPUs off and on. CPUs
1588 can be controlled through /sys/devices/system/cpu.
1591 bool "Use local timer interrupts"
1594 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1596 Enable support for local timers on SMP platforms, rather then the
1597 legacy IPI broadcast method. Local timers allows the system
1598 accounting to be spread across the timer interval, preventing a
1599 "thundering herd" at every timer tick.
1601 source kernel/Kconfig.preempt
1605 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1606 ARCH_S5PV210 || ARCH_EXYNOS4
1607 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1608 default AT91_TIMER_HZ if ARCH_AT91
1609 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1612 config THUMB2_KERNEL
1613 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1614 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1616 select ARM_ASM_UNIFIED
1619 By enabling this option, the kernel will be compiled in
1620 Thumb-2 mode. A compiler/assembler that understand the unified
1621 ARM-Thumb syntax is needed.
1625 config THUMB2_AVOID_R_ARM_THM_JUMP11
1626 bool "Work around buggy Thumb-2 short branch relocations in gas"
1627 depends on THUMB2_KERNEL && MODULES
1630 Various binutils versions can resolve Thumb-2 branches to
1631 locally-defined, preemptible global symbols as short-range "b.n"
1632 branch instructions.
1634 This is a problem, because there's no guarantee the final
1635 destination of the symbol, or any candidate locations for a
1636 trampoline, are within range of the branch. For this reason, the
1637 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1638 relocation in modules at all, and it makes little sense to add
1641 The symptom is that the kernel fails with an "unsupported
1642 relocation" error when loading some modules.
1644 Until fixed tools are available, passing
1645 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1646 code which hits this problem, at the cost of a bit of extra runtime
1647 stack usage in some cases.
1649 The problem is described in more detail at:
1650 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1652 Only Thumb-2 kernels are affected.
1654 Unless you are sure your tools don't have this problem, say Y.
1656 config ARM_ASM_UNIFIED
1660 bool "Use the ARM EABI to compile the kernel"
1662 This option allows for the kernel to be compiled using the latest
1663 ARM ABI (aka EABI). This is only useful if you are using a user
1664 space environment that is also compiled with EABI.
1666 Since there are major incompatibilities between the legacy ABI and
1667 EABI, especially with regard to structure member alignment, this
1668 option also changes the kernel syscall calling convention to
1669 disambiguate both ABIs and allow for backward compatibility support
1670 (selected with CONFIG_OABI_COMPAT).
1672 To use this you need GCC version 4.0.0 or later.
1675 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1676 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1679 This option preserves the old syscall interface along with the
1680 new (ARM EABI) one. It also provides a compatibility layer to
1681 intercept syscalls that have structure arguments which layout
1682 in memory differs between the legacy ABI and the new ARM EABI
1683 (only for non "thumb" binaries). This option adds a tiny
1684 overhead to all syscalls and produces a slightly larger kernel.
1685 If you know you'll be using only pure EABI user space then you
1686 can say N here. If this option is not selected and you attempt
1687 to execute a legacy ABI binary then the result will be
1688 UNPREDICTABLE (in fact it can be predicted that it won't work
1689 at all). If in doubt say Y.
1691 config ARCH_HAS_HOLES_MEMORYMODEL
1694 config ARCH_SPARSEMEM_ENABLE
1697 config ARCH_SPARSEMEM_DEFAULT
1698 def_bool ARCH_SPARSEMEM_ENABLE
1700 config ARCH_SELECT_MEMORY_MODEL
1701 def_bool ARCH_SPARSEMEM_ENABLE
1703 config HAVE_ARCH_PFN_VALID
1704 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1707 bool "High Memory Support"
1710 The address space of ARM processors is only 4 Gigabytes large
1711 and it has to accommodate user address space, kernel address
1712 space as well as some memory mapped IO. That means that, if you
1713 have a large amount of physical memory and/or IO, not all of the
1714 memory can be "permanently mapped" by the kernel. The physical
1715 memory that is not permanently mapped is called "high memory".
1717 Depending on the selected kernel/user memory split, minimum
1718 vmalloc space and actual amount of RAM, you may not need this
1719 option which should result in a slightly faster kernel.
1724 bool "Allocate 2nd-level pagetables from highmem"
1727 config HW_PERF_EVENTS
1728 bool "Enable hardware performance counter support for perf events"
1729 depends on PERF_EVENTS && CPU_HAS_PMU
1732 Enable hardware performance counter support for perf events. If
1733 disabled, perf events will use software events only.
1737 config FORCE_MAX_ZONEORDER
1738 int "Maximum zone order" if ARCH_SHMOBILE
1739 range 11 64 if ARCH_SHMOBILE
1740 default "9" if SA1111
1743 The kernel memory allocator divides physically contiguous memory
1744 blocks into "zones", where each zone is a power of two number of
1745 pages. This option selects the largest power of two that the kernel
1746 keeps in the memory allocator. If you need to allocate very large
1747 blocks of physically contiguous memory, then you may need to
1748 increase this value.
1750 This config option is actually maximum order plus one. For example,
1751 a value of 11 means that the largest free memory block is 2^10 pages.
1754 bool "Timer and CPU usage LEDs"
1755 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1756 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1757 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1758 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1759 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1760 ARCH_AT91 || ARCH_DAVINCI || \
1761 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1763 If you say Y here, the LEDs on your machine will be used
1764 to provide useful information about your current system status.
1766 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1767 be able to select which LEDs are active using the options below. If
1768 you are compiling a kernel for the EBSA-110 or the LART however, the
1769 red LED will simply flash regularly to indicate that the system is
1770 still functional. It is safe to say Y here if you have a CATS
1771 system, but the driver will do nothing.
1774 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1775 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1776 || MACH_OMAP_PERSEUS2
1778 depends on !GENERIC_CLOCKEVENTS
1779 default y if ARCH_EBSA110
1781 If you say Y here, one of the system LEDs (the green one on the
1782 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1783 will flash regularly to indicate that the system is still
1784 operational. This is mainly useful to kernel hackers who are
1785 debugging unstable kernels.
1787 The LART uses the same LED for both Timer LED and CPU usage LED
1788 functions. You may choose to use both, but the Timer LED function
1789 will overrule the CPU usage LED.
1792 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1794 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1795 || MACH_OMAP_PERSEUS2
1798 If you say Y here, the red LED will be used to give a good real
1799 time indication of CPU usage, by lighting whenever the idle task
1800 is not currently executing.
1802 The LART uses the same LED for both Timer LED and CPU usage LED
1803 functions. You may choose to use both, but the Timer LED function
1804 will overrule the CPU usage LED.
1806 config ALIGNMENT_TRAP
1807 bool "Enable alignment trap"
1808 depends on CPU_CP15_MMU
1809 default y if !ARCH_EBSA110
1810 select HAVE_PROC_CPU if PROC_FS
1812 ARM processors cannot fetch/store information which is not
1813 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1814 address divisible by 4. On 32-bit ARM processors, these non-aligned
1815 fetch/store instructions will be emulated in software if you say
1816 here, which has a severe performance impact. This is necessary for
1817 correct operation of some network protocols. With an IP-only
1818 configuration it is safe to say N, otherwise say Y.
1820 config UACCESS_WITH_MEMCPY
1821 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1822 depends on MMU && EXPERIMENTAL
1823 default y if CPU_FEROCEON
1825 Implement faster copy_to_user and clear_user methods for CPU
1826 cores where a 8-word STM instruction give significantly higher
1827 memory write throughput than a sequence of individual 32bit stores.
1829 A possible side effect is a slight increase in scheduling latency
1830 between threads sharing the same address space if they invoke
1831 such copy operations with large buffers.
1833 However, if the CPU data cache is using a write-allocate mode,
1834 this option is unlikely to provide any performance gain.
1838 prompt "Enable seccomp to safely compute untrusted bytecode"
1840 This kernel feature is useful for number crunching applications
1841 that may need to compute untrusted bytecode during their
1842 execution. By using pipes or other transports made available to
1843 the process as file descriptors supporting the read/write
1844 syscalls, it's possible to isolate those applications in
1845 their own address space using seccomp. Once seccomp is
1846 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1847 and the task is only allowed to execute a few safe syscalls
1848 defined by each seccomp mode.
1850 config CC_STACKPROTECTOR
1851 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1852 depends on EXPERIMENTAL
1854 This option turns on the -fstack-protector GCC feature. This
1855 feature puts, at the beginning of functions, a canary value on
1856 the stack just before the return address, and validates
1857 the value just before actually returning. Stack based buffer
1858 overflows (that need to overwrite this return address) now also
1859 overwrite the canary, which gets detected and the attack is then
1860 neutralized via a kernel panic.
1861 This feature requires gcc version 4.2 or above.
1863 config DEPRECATED_PARAM_STRUCT
1864 bool "Provide old way to pass kernel parameters"
1866 This was deprecated in 2001 and announced to live on for 5 years.
1867 Some old boot loaders still use this way.
1871 depends on CPU_V7 && SYSFS
1879 bool "Flattened Device Tree support"
1881 select OF_EARLY_FLATTREE
1884 Include support for flattened device tree machine descriptions.
1886 # Compressed boot loader in ROM. Yes, we really want to ask about
1887 # TEXT and BSS so we preserve their values in the config files.
1888 config ZBOOT_ROM_TEXT
1889 hex "Compressed ROM boot loader base address"
1892 The physical address at which the ROM-able zImage is to be
1893 placed in the target. Platforms which normally make use of
1894 ROM-able zImage formats normally set this to a suitable
1895 value in their defconfig file.
1897 If ZBOOT_ROM is not enabled, this has no effect.
1899 config ZBOOT_ROM_BSS
1900 hex "Compressed ROM boot loader BSS address"
1903 The base address of an area of read/write memory in the target
1904 for the ROM-able zImage which must be available while the
1905 decompressor is running. It must be large enough to hold the
1906 entire decompressed kernel plus an additional 128 KiB.
1907 Platforms which normally make use of ROM-able zImage formats
1908 normally set this to a suitable value in their defconfig file.
1910 If ZBOOT_ROM is not enabled, this has no effect.
1913 bool "Compressed boot loader in ROM/flash"
1914 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1916 Say Y here if you intend to execute your compressed kernel image
1917 (zImage) directly from ROM or flash. If unsure, say N.
1920 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1921 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1922 default ZBOOT_ROM_NONE
1924 Include experimental SD/MMC loading code in the ROM-able zImage.
1925 With this enabled it is possible to write the the ROM-able zImage
1926 kernel image to an MMC or SD card and boot the kernel straight
1927 from the reset vector. At reset the processor Mask ROM will load
1928 the first part of the the ROM-able zImage which in turn loads the
1929 rest the kernel image to RAM.
1931 config ZBOOT_ROM_NONE
1932 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1934 Do not load image from SD or MMC
1936 config ZBOOT_ROM_MMCIF
1937 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1939 Load image from MMCIF hardware block.
1941 config ZBOOT_ROM_SH_MOBILE_SDHI
1942 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1944 Load image from SDHI hardware block
1948 config ARM_APPENDED_DTB
1949 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1950 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1952 With this option, the boot code will look for a device tree binary
1953 (DTB) appended to zImage
1954 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1956 This is meant as a backward compatibility convenience for those
1957 systems with a bootloader that can't be upgraded to accommodate
1958 the documented boot protocol using a device tree.
1960 Beware that there is very little in terms of protection against
1961 this option being confused by leftover garbage in memory that might
1962 look like a DTB header after a reboot if no actual DTB is appended
1963 to zImage. Do not leave this option active in a production kernel
1964 if you don't intend to always append a DTB. Proper passing of the
1965 location into r2 of a bootloader provided DTB is always preferable
1968 config ARM_ATAG_DTB_COMPAT
1969 bool "Supplement the appended DTB with traditional ATAG information"
1970 depends on ARM_APPENDED_DTB
1972 Some old bootloaders can't be updated to a DTB capable one, yet
1973 they provide ATAGs with memory configuration, the ramdisk address,
1974 the kernel cmdline string, etc. Such information is dynamically
1975 provided by the bootloader and can't always be stored in a static
1976 DTB. To allow a device tree enabled kernel to be used with such
1977 bootloaders, this option allows zImage to extract the information
1978 from the ATAG list and store it at run time into the appended DTB.
1981 string "Default kernel command string"
1984 On some architectures (EBSA110 and CATS), there is currently no way
1985 for the boot loader to pass arguments to the kernel. For these
1986 architectures, you should supply some command-line options at build
1987 time by entering them here. As a minimum, you should specify the
1988 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1991 prompt "Kernel command line type" if CMDLINE != ""
1992 default CMDLINE_FROM_BOOTLOADER
1994 config CMDLINE_FROM_BOOTLOADER
1995 bool "Use bootloader kernel arguments if available"
1997 Uses the command-line options passed by the boot loader. If
1998 the boot loader doesn't provide any, the default kernel command
1999 string provided in CMDLINE will be used.
2001 config CMDLINE_EXTEND
2002 bool "Extend bootloader kernel arguments"
2004 The command-line arguments provided by the boot loader will be
2005 appended to the default kernel command string.
2007 config CMDLINE_FORCE
2008 bool "Always use the default kernel command string"
2010 Always use the default kernel command string, even if the boot
2011 loader passes other arguments to the kernel.
2012 This is useful if you cannot or don't want to change the
2013 command-line options your boot loader passes to the kernel.
2017 bool "Kernel Execute-In-Place from ROM"
2018 depends on !ZBOOT_ROM
2020 Execute-In-Place allows the kernel to run from non-volatile storage
2021 directly addressable by the CPU, such as NOR flash. This saves RAM
2022 space since the text section of the kernel is not loaded from flash
2023 to RAM. Read-write sections, such as the data section and stack,
2024 are still copied to RAM. The XIP kernel is not compressed since
2025 it has to run directly from flash, so it will take more space to
2026 store it. The flash address used to link the kernel object files,
2027 and for storing it, is configuration dependent. Therefore, if you
2028 say Y here, you must know the proper physical address where to
2029 store the kernel image depending on your own flash memory usage.
2031 Also note that the make target becomes "make xipImage" rather than
2032 "make zImage" or "make Image". The final kernel binary to put in
2033 ROM memory will be arch/arm/boot/xipImage.
2037 config XIP_PHYS_ADDR
2038 hex "XIP Kernel Physical Location"
2039 depends on XIP_KERNEL
2040 default "0x00080000"
2042 This is the physical address in your flash memory the kernel will
2043 be linked for and stored to. This address is dependent on your
2047 bool "Kexec system call (EXPERIMENTAL)"
2048 depends on EXPERIMENTAL
2050 kexec is a system call that implements the ability to shutdown your
2051 current kernel, and to start another kernel. It is like a reboot
2052 but it is independent of the system firmware. And like a reboot
2053 you can start any kernel with it, not just Linux.
2055 It is an ongoing process to be certain the hardware in a machine
2056 is properly shutdown, so do not be surprised if this code does not
2057 initially work for you. It may help to enable device hotplugging
2061 bool "Export atags in procfs"
2065 Should the atags used to boot the kernel be exported in an "atags"
2066 file in procfs. Useful with kexec.
2069 bool "Build kdump crash kernel (EXPERIMENTAL)"
2070 depends on EXPERIMENTAL
2072 Generate crash dump after being started by kexec. This should
2073 be normally only set in special crash dump kernels which are
2074 loaded in the main kernel with kexec-tools into a specially
2075 reserved region and then later executed after a crash by
2076 kdump/kexec. The crash dump kernel must be compiled to a
2077 memory address not used by the main kernel
2079 For more details see Documentation/kdump/kdump.txt
2081 config AUTO_ZRELADDR
2082 bool "Auto calculation of the decompressed kernel image address"
2083 depends on !ZBOOT_ROM && !ARCH_U300
2085 ZRELADDR is the physical address where the decompressed kernel
2086 image will be placed. If AUTO_ZRELADDR is selected, the address
2087 will be determined at run-time by masking the current IP with
2088 0xf8000000. This assumes the zImage being placed in the first 128MB
2089 from start of memory.
2093 menu "CPU Power Management"
2097 source "drivers/cpufreq/Kconfig"
2100 tristate "CPUfreq driver for i.MX CPUs"
2101 depends on ARCH_MXC && CPU_FREQ
2102 select CPU_FREQ_TABLE
2104 This enables the CPUfreq driver for i.MX CPUs.
2106 config CPU_FREQ_SA1100
2109 config CPU_FREQ_SA1110
2112 config CPU_FREQ_INTEGRATOR
2113 tristate "CPUfreq driver for ARM Integrator CPUs"
2114 depends on ARCH_INTEGRATOR && CPU_FREQ
2117 This enables the CPUfreq driver for ARM Integrator CPUs.
2119 For details, take a look at <file:Documentation/cpu-freq>.
2125 depends on CPU_FREQ && ARCH_PXA && PXA25x
2127 select CPU_FREQ_TABLE
2128 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2133 Internal configuration node for common cpufreq on Samsung SoC
2135 config CPU_FREQ_S3C24XX
2136 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2137 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2140 This enables the CPUfreq driver for the Samsung S3C24XX family
2143 For details, take a look at <file:Documentation/cpu-freq>.
2147 config CPU_FREQ_S3C24XX_PLL
2148 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2149 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2151 Compile in support for changing the PLL frequency from the
2152 S3C24XX series CPUfreq driver. The PLL takes time to settle
2153 after a frequency change, so by default it is not enabled.
2155 This also means that the PLL tables for the selected CPU(s) will
2156 be built which may increase the size of the kernel image.
2158 config CPU_FREQ_S3C24XX_DEBUG
2159 bool "Debug CPUfreq Samsung driver core"
2160 depends on CPU_FREQ_S3C24XX
2162 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2164 config CPU_FREQ_S3C24XX_IODEBUG
2165 bool "Debug CPUfreq Samsung driver IO timing"
2166 depends on CPU_FREQ_S3C24XX
2168 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2170 config CPU_FREQ_S3C24XX_DEBUGFS
2171 bool "Export debugfs for CPUFreq"
2172 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2174 Export status information via debugfs.
2178 source "drivers/cpuidle/Kconfig"
2182 menu "Floating point emulation"
2184 comment "At least one emulation must be selected"
2187 bool "NWFPE math emulation"
2188 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2190 Say Y to include the NWFPE floating point emulator in the kernel.
2191 This is necessary to run most binaries. Linux does not currently
2192 support floating point hardware so you need to say Y here even if
2193 your machine has an FPA or floating point co-processor podule.
2195 You may say N here if you are going to load the Acorn FPEmulator
2196 early in the bootup.
2199 bool "Support extended precision"
2200 depends on FPE_NWFPE
2202 Say Y to include 80-bit support in the kernel floating-point
2203 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2204 Note that gcc does not generate 80-bit operations by default,
2205 so in most cases this option only enlarges the size of the
2206 floating point emulator without any good reason.
2208 You almost surely want to say N here.
2211 bool "FastFPE math emulation (EXPERIMENTAL)"
2212 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2214 Say Y here to include the FAST floating point emulator in the kernel.
2215 This is an experimental much faster emulator which now also has full
2216 precision for the mantissa. It does not support any exceptions.
2217 It is very simple, and approximately 3-6 times faster than NWFPE.
2219 It should be sufficient for most programs. It may be not suitable
2220 for scientific calculations, but you have to check this for yourself.
2221 If you do not feel you need a faster FP emulation you should better
2225 bool "VFP-format floating point maths"
2226 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2228 Say Y to include VFP support code in the kernel. This is needed
2229 if your hardware includes a VFP unit.
2231 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2232 release notes and additional status information.
2234 Say N if your target does not have VFP hardware.
2242 bool "Advanced SIMD (NEON) Extension support"
2243 depends on VFPv3 && CPU_V7
2245 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2250 menu "Userspace binary formats"
2252 source "fs/Kconfig.binfmt"
2255 tristate "RISC OS personality"
2258 Say Y here to include the kernel code necessary if you want to run
2259 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2260 experimental; if this sounds frightening, say N and sleep in peace.
2261 You can also say M here to compile this support as a module (which
2262 will be called arthur).
2266 menu "Power management options"
2268 source "kernel/power/Kconfig"
2270 config ARCH_SUSPEND_POSSIBLE
2271 depends on !ARCH_S5PC100
2272 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2273 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2276 config ARM_CPU_SUSPEND
2281 source "net/Kconfig"
2283 source "drivers/Kconfig"
2287 source "arch/arm/Kconfig.debug"
2289 source "security/Kconfig"
2291 source "crypto/Kconfig"
2293 source "lib/Kconfig"