5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
199 depends on EXPERIMENTAL
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary, or theoretically 64K
209 for the MSM machine class.
211 config ARM_PATCH_PHYS_VIRT_16BIT
213 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
215 This option extends the physical to virtual translation patching
216 to allow physical memory down to a theoretical minimum of 64K
219 source "init/Kconfig"
221 source "kernel/Kconfig.freezer"
226 bool "MMU-based Paged Memory Management Support"
229 Select if you want MMU-based virtualised addressing space
230 support by paged memory management. If unsure, say 'Y'.
233 # The "ARM system type" choice list is ordered alphabetically by option
234 # text. Please add new entries in the option alphabetic order.
237 prompt "ARM system type"
238 default ARCH_VERSATILE
240 config ARCH_INTEGRATOR
241 bool "ARM Ltd. Integrator family"
243 select ARCH_HAS_CPUFREQ
246 select GENERIC_CLOCKEVENTS
247 select PLAT_VERSATILE
248 select PLAT_VERSATILE_FPGA_IRQ
250 Support for ARM's Integrator platform.
253 bool "ARM Ltd. RealView family"
257 select GENERIC_CLOCKEVENTS
258 select ARCH_WANT_OPTIONAL_GPIOLIB
259 select PLAT_VERSATILE
260 select PLAT_VERSATILE_CLCD
261 select ARM_TIMER_SP804
262 select GPIO_PL061 if GPIOLIB
264 This enables support for ARM Ltd RealView boards.
266 config ARCH_VERSATILE
267 bool "ARM Ltd. Versatile family"
272 select GENERIC_CLOCKEVENTS
273 select ARCH_WANT_OPTIONAL_GPIOLIB
274 select PLAT_VERSATILE
275 select PLAT_VERSATILE_CLCD
276 select PLAT_VERSATILE_FPGA_IRQ
277 select ARM_TIMER_SP804
279 This enables support for ARM Ltd Versatile board.
282 bool "ARM Ltd. Versatile Express family"
283 select ARCH_WANT_OPTIONAL_GPIOLIB
285 select ARM_TIMER_SP804
287 select GENERIC_CLOCKEVENTS
289 select HAVE_PATA_PLATFORM
291 select PLAT_VERSATILE
292 select PLAT_VERSATILE_CLCD
294 This enables support for the ARM Ltd Versatile Express boards.
298 select ARCH_REQUIRE_GPIOLIB
301 select ARM_PATCH_PHYS_VIRT if MMU
303 This enables support for systems based on the Atmel AT91RM9200,
304 AT91SAM9 and AT91CAP9 processors.
307 bool "Broadcom BCMRING"
311 select ARM_TIMER_SP804
313 select GENERIC_CLOCKEVENTS
314 select ARCH_WANT_OPTIONAL_GPIOLIB
316 Support for Broadcom's BCMRing platform.
319 bool "Cirrus Logic CLPS711x/EP721x-based"
321 select ARCH_USES_GETTIMEOFFSET
323 Support for Cirrus Logic 711x/721x based boards.
326 bool "Cavium Networks CNS3XXX family"
328 select GENERIC_CLOCKEVENTS
330 select MIGHT_HAVE_PCI
331 select PCI_DOMAINS if PCI
333 Support for Cavium Networks CNS3XXX platform.
336 bool "Cortina Systems Gemini"
338 select ARCH_REQUIRE_GPIOLIB
339 select ARCH_USES_GETTIMEOFFSET
341 Support for the Cortina Systems Gemini family SoCs
348 select ARCH_USES_GETTIMEOFFSET
350 This is an evaluation board for the StrongARM processor available
351 from Digital. It has limited hardware on-board, including an
352 Ethernet interface, two PCMCIA sockets, two serial ports and a
361 select ARCH_REQUIRE_GPIOLIB
362 select ARCH_HAS_HOLES_MEMORYMODEL
363 select ARCH_USES_GETTIMEOFFSET
365 This enables support for the Cirrus EP93xx series of CPUs.
367 config ARCH_FOOTBRIDGE
371 select GENERIC_CLOCKEVENTS
373 Support for systems based on the DC21285 companion chip
374 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
377 bool "Freescale MXC/iMX-based"
378 select GENERIC_CLOCKEVENTS
379 select ARCH_REQUIRE_GPIOLIB
382 select HAVE_SCHED_CLOCK
384 Support for Freescale MXC/iMX-based family of processors
387 bool "Freescale MXS-based"
388 select GENERIC_CLOCKEVENTS
389 select ARCH_REQUIRE_GPIOLIB
393 Support for Freescale MXS-based family of processors
396 bool "Hilscher NetX based"
400 select GENERIC_CLOCKEVENTS
402 This enables support for systems based on the Hilscher NetX Soc
405 bool "Hynix HMS720x-based"
408 select ARCH_USES_GETTIMEOFFSET
410 This enables support for systems based on the Hynix HMS720x
418 select ARCH_SUPPORTS_MSI
421 Support for Intel's IOP13XX (XScale) family of processors.
429 select ARCH_REQUIRE_GPIOLIB
431 Support for Intel's 80219 and IOP32X (XScale) family of
440 select ARCH_REQUIRE_GPIOLIB
442 Support for Intel's IOP33X (XScale) family of processors.
449 select ARCH_USES_GETTIMEOFFSET
451 Support for Intel's IXP23xx (XScale) family of processors.
454 bool "IXP2400/2800-based"
458 select ARCH_USES_GETTIMEOFFSET
460 Support for Intel's IXP2400/2800 (XScale) family of processors.
468 select GENERIC_CLOCKEVENTS
469 select HAVE_SCHED_CLOCK
470 select MIGHT_HAVE_PCI
471 select DMABOUNCE if PCI
473 Support for Intel's IXP4XX (XScale) family of processors.
479 select ARCH_REQUIRE_GPIOLIB
480 select GENERIC_CLOCKEVENTS
483 Support for the Marvell Dove SoC 88AP510
486 bool "Marvell Kirkwood"
489 select ARCH_REQUIRE_GPIOLIB
490 select GENERIC_CLOCKEVENTS
493 Support for the following Marvell Kirkwood series SoCs:
494 88F6180, 88F6192 and 88F6281.
500 select ARCH_REQUIRE_GPIOLIB
503 select USB_ARCH_HAS_OHCI
506 select GENERIC_CLOCKEVENTS
508 Support for the NXP LPC32XX family of processors
511 bool "Marvell MV78xx0"
514 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
518 Support for the following Marvell MV78xx0 series SoCs:
526 select ARCH_REQUIRE_GPIOLIB
527 select GENERIC_CLOCKEVENTS
530 Support for the following Marvell Orion 5x series SoCs:
531 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
532 Orion-2 (5281), Orion-1-90 (6183).
535 bool "Marvell PXA168/910/MMP2"
537 select ARCH_REQUIRE_GPIOLIB
539 select GENERIC_CLOCKEVENTS
540 select HAVE_SCHED_CLOCK
545 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
548 bool "Micrel/Kendin KS8695"
550 select ARCH_REQUIRE_GPIOLIB
551 select ARCH_USES_GETTIMEOFFSET
553 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
554 System-on-Chip devices.
557 bool "Nuvoton W90X900 CPU"
559 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
564 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
565 At present, the w90x900 has been renamed nuc900, regarding
566 the ARM series product line, you can login the following
567 link address to know more.
569 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
570 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
573 bool "Nuvoton NUC93X CPU"
577 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
578 low-power and high performance MPEG-4/JPEG multimedia controller chip.
585 select GENERIC_CLOCKEVENTS
588 select HAVE_SCHED_CLOCK
589 select ARCH_HAS_BARRIERS if CACHE_L2X0
590 select ARCH_HAS_CPUFREQ
592 This enables support for NVIDIA Tegra based systems (Tegra APX,
593 Tegra 6xx and Tegra 2 series).
596 bool "Philips Nexperia PNX4008 Mobile"
599 select ARCH_USES_GETTIMEOFFSET
601 This enables support for Philips PNX4008 mobile platform.
604 bool "PXA2xx/PXA3xx-based"
607 select ARCH_HAS_CPUFREQ
610 select ARCH_REQUIRE_GPIOLIB
611 select GENERIC_CLOCKEVENTS
612 select HAVE_SCHED_CLOCK
617 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
622 select GENERIC_CLOCKEVENTS
623 select ARCH_REQUIRE_GPIOLIB
626 Support for Qualcomm MSM/QSD based systems. This runs on the
627 apps processor of the MSM/QSD and depends on a shared memory
628 interface to the modem processor which runs the baseband
629 stack and controls some vital subsystems
630 (clock and power control, etc).
633 bool "Renesas SH-Mobile / R-Mobile"
636 select GENERIC_CLOCKEVENTS
639 select MULTI_IRQ_HANDLER
640 select PM_GENERIC_DOMAINS if PM
642 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
649 select ARCH_MAY_HAVE_PC_FDC
650 select HAVE_PATA_PLATFORM
653 select ARCH_SPARSEMEM_ENABLE
654 select ARCH_USES_GETTIMEOFFSET
656 On the Acorn Risc-PC, Linux can support the internal IDE disk and
657 CD-ROM interface, serial and parallel port, and the floppy drive.
664 select ARCH_SPARSEMEM_ENABLE
666 select ARCH_HAS_CPUFREQ
668 select GENERIC_CLOCKEVENTS
670 select HAVE_SCHED_CLOCK
672 select ARCH_REQUIRE_GPIOLIB
674 Support for StrongARM 11x0 based boards.
677 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
679 select ARCH_HAS_CPUFREQ
682 select ARCH_USES_GETTIMEOFFSET
683 select HAVE_S3C2410_I2C if I2C
685 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
686 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
687 the Samsung SMDK2410 development board (and derivatives).
689 Note, the S3C2416 and the S3C2450 are so close that they even share
690 the same SoC ID code. This means that there is no separate machine
691 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
694 bool "Samsung S3C64XX"
701 select ARCH_USES_GETTIMEOFFSET
702 select ARCH_HAS_CPUFREQ
703 select ARCH_REQUIRE_GPIOLIB
704 select SAMSUNG_CLKSRC
705 select SAMSUNG_IRQ_VIC_TIMER
706 select SAMSUNG_IRQ_UART
707 select S3C_GPIO_TRACK
708 select S3C_GPIO_PULL_UPDOWN
709 select S3C_GPIO_CFG_S3C24XX
710 select S3C_GPIO_CFG_S3C64XX
712 select USB_ARCH_HAS_OHCI
713 select SAMSUNG_GPIOLIB_4BIT
714 select HAVE_S3C2410_I2C if I2C
715 select HAVE_S3C2410_WATCHDOG if WATCHDOG
717 Samsung S3C64XX series based systems
720 bool "Samsung S5P6440 S5P6450"
726 select HAVE_S3C2410_WATCHDOG if WATCHDOG
727 select GENERIC_CLOCKEVENTS
728 select HAVE_SCHED_CLOCK
729 select HAVE_S3C2410_I2C if I2C
730 select HAVE_S3C_RTC if RTC_CLASS
732 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
736 bool "Samsung S5PC100"
741 select ARM_L1_CACHE_SHIFT_6
742 select ARCH_USES_GETTIMEOFFSET
743 select HAVE_S3C2410_I2C if I2C
744 select HAVE_S3C_RTC if RTC_CLASS
745 select HAVE_S3C2410_WATCHDOG if WATCHDOG
747 Samsung S5PC100 series based systems
750 bool "Samsung S5PV210/S5PC110"
752 select ARCH_SPARSEMEM_ENABLE
757 select ARM_L1_CACHE_SHIFT_6
758 select ARCH_HAS_CPUFREQ
759 select GENERIC_CLOCKEVENTS
760 select HAVE_SCHED_CLOCK
761 select HAVE_S3C2410_I2C if I2C
762 select HAVE_S3C_RTC if RTC_CLASS
763 select HAVE_S3C2410_WATCHDOG if WATCHDOG
765 Samsung S5PV210/S5PC110 series based systems
768 bool "Samsung EXYNOS4"
770 select ARCH_SPARSEMEM_ENABLE
774 select ARCH_HAS_CPUFREQ
775 select GENERIC_CLOCKEVENTS
776 select HAVE_S3C_RTC if RTC_CLASS
777 select HAVE_S3C2410_I2C if I2C
778 select HAVE_S3C2410_WATCHDOG if WATCHDOG
780 Samsung EXYNOS4 series based systems
789 select ARCH_USES_GETTIMEOFFSET
791 Support for the StrongARM based Digital DNARD machine, also known
792 as "Shark" (<http://www.shark-linux.de/shark.html>).
795 bool "Telechips TCC ARM926-based systems"
800 select GENERIC_CLOCKEVENTS
802 Support for Telechips TCC ARM926-based systems.
805 bool "ST-Ericsson U300 Series"
809 select HAVE_SCHED_CLOCK
813 select GENERIC_CLOCKEVENTS
817 Support for ST-Ericsson U300 series mobile platforms.
820 bool "ST-Ericsson U8500 Series"
823 select GENERIC_CLOCKEVENTS
825 select ARCH_REQUIRE_GPIOLIB
826 select ARCH_HAS_CPUFREQ
828 Support for ST-Ericsson's Ux500 architecture
831 bool "STMicroelectronics Nomadik"
836 select GENERIC_CLOCKEVENTS
837 select ARCH_REQUIRE_GPIOLIB
839 Support for the Nomadik platform by ST-Ericsson
843 select GENERIC_CLOCKEVENTS
844 select ARCH_REQUIRE_GPIOLIB
848 select GENERIC_ALLOCATOR
849 select GENERIC_IRQ_CHIP
850 select ARCH_HAS_HOLES_MEMORYMODEL
852 Support for TI's DaVinci platform.
857 select ARCH_REQUIRE_GPIOLIB
858 select ARCH_HAS_CPUFREQ
860 select GENERIC_CLOCKEVENTS
861 select HAVE_SCHED_CLOCK
862 select ARCH_HAS_HOLES_MEMORYMODEL
864 Support for TI's OMAP platform (OMAP1/2/3/4).
869 select ARCH_REQUIRE_GPIOLIB
872 select GENERIC_CLOCKEVENTS
875 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
878 bool "VIA/WonderMedia 85xx"
881 select ARCH_HAS_CPUFREQ
882 select GENERIC_CLOCKEVENTS
883 select ARCH_REQUIRE_GPIOLIB
886 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
890 # This is sorted alphabetically by mach-* pathname. However, plat-*
891 # Kconfigs may be included either alphabetically (according to the
892 # plat- suffix) or along side the corresponding mach-* source.
894 source "arch/arm/mach-at91/Kconfig"
896 source "arch/arm/mach-bcmring/Kconfig"
898 source "arch/arm/mach-clps711x/Kconfig"
900 source "arch/arm/mach-cns3xxx/Kconfig"
902 source "arch/arm/mach-davinci/Kconfig"
904 source "arch/arm/mach-dove/Kconfig"
906 source "arch/arm/mach-ep93xx/Kconfig"
908 source "arch/arm/mach-footbridge/Kconfig"
910 source "arch/arm/mach-gemini/Kconfig"
912 source "arch/arm/mach-h720x/Kconfig"
914 source "arch/arm/mach-integrator/Kconfig"
916 source "arch/arm/mach-iop32x/Kconfig"
918 source "arch/arm/mach-iop33x/Kconfig"
920 source "arch/arm/mach-iop13xx/Kconfig"
922 source "arch/arm/mach-ixp4xx/Kconfig"
924 source "arch/arm/mach-ixp2000/Kconfig"
926 source "arch/arm/mach-ixp23xx/Kconfig"
928 source "arch/arm/mach-kirkwood/Kconfig"
930 source "arch/arm/mach-ks8695/Kconfig"
932 source "arch/arm/mach-lpc32xx/Kconfig"
934 source "arch/arm/mach-msm/Kconfig"
936 source "arch/arm/mach-mv78xx0/Kconfig"
938 source "arch/arm/plat-mxc/Kconfig"
940 source "arch/arm/mach-mxs/Kconfig"
942 source "arch/arm/mach-netx/Kconfig"
944 source "arch/arm/mach-nomadik/Kconfig"
945 source "arch/arm/plat-nomadik/Kconfig"
947 source "arch/arm/mach-nuc93x/Kconfig"
949 source "arch/arm/plat-omap/Kconfig"
951 source "arch/arm/mach-omap1/Kconfig"
953 source "arch/arm/mach-omap2/Kconfig"
955 source "arch/arm/mach-orion5x/Kconfig"
957 source "arch/arm/mach-pxa/Kconfig"
958 source "arch/arm/plat-pxa/Kconfig"
960 source "arch/arm/mach-mmp/Kconfig"
962 source "arch/arm/mach-realview/Kconfig"
964 source "arch/arm/mach-sa1100/Kconfig"
966 source "arch/arm/plat-samsung/Kconfig"
967 source "arch/arm/plat-s3c24xx/Kconfig"
968 source "arch/arm/plat-s5p/Kconfig"
970 source "arch/arm/plat-spear/Kconfig"
972 source "arch/arm/plat-tcc/Kconfig"
975 source "arch/arm/mach-s3c2410/Kconfig"
976 source "arch/arm/mach-s3c2412/Kconfig"
977 source "arch/arm/mach-s3c2416/Kconfig"
978 source "arch/arm/mach-s3c2440/Kconfig"
979 source "arch/arm/mach-s3c2443/Kconfig"
983 source "arch/arm/mach-s3c64xx/Kconfig"
986 source "arch/arm/mach-s5p64x0/Kconfig"
988 source "arch/arm/mach-s5pc100/Kconfig"
990 source "arch/arm/mach-s5pv210/Kconfig"
992 source "arch/arm/mach-exynos4/Kconfig"
994 source "arch/arm/mach-shmobile/Kconfig"
996 source "arch/arm/mach-tegra/Kconfig"
998 source "arch/arm/mach-u300/Kconfig"
1000 source "arch/arm/mach-ux500/Kconfig"
1002 source "arch/arm/mach-versatile/Kconfig"
1004 source "arch/arm/mach-vexpress/Kconfig"
1005 source "arch/arm/plat-versatile/Kconfig"
1007 source "arch/arm/mach-vt8500/Kconfig"
1009 source "arch/arm/mach-w90x900/Kconfig"
1011 # Definitions to make life easier
1017 select GENERIC_CLOCKEVENTS
1018 select HAVE_SCHED_CLOCK
1023 select GENERIC_IRQ_CHIP
1024 select HAVE_SCHED_CLOCK
1029 config PLAT_VERSATILE
1032 config ARM_TIMER_SP804
1036 source arch/arm/mm/Kconfig
1039 bool "Enable iWMMXt support"
1040 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1041 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1043 Enable support for iWMMXt context switching at run time if
1044 running on a CPU that supports it.
1046 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1049 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1053 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1054 (!ARCH_OMAP3 || OMAP3_EMU)
1058 config MULTI_IRQ_HANDLER
1061 Allow each machine to specify it's own IRQ handler at run time.
1064 source "arch/arm/Kconfig-nommu"
1067 config ARM_ERRATA_411920
1068 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1069 depends on CPU_V6 || CPU_V6K
1071 Invalidation of the Instruction Cache operation can
1072 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1073 It does not affect the MPCore. This option enables the ARM Ltd.
1074 recommended workaround.
1076 config ARM_ERRATA_430973
1077 bool "ARM errata: Stale prediction on replaced interworking branch"
1080 This option enables the workaround for the 430973 Cortex-A8
1081 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1082 interworking branch is replaced with another code sequence at the
1083 same virtual address, whether due to self-modifying code or virtual
1084 to physical address re-mapping, Cortex-A8 does not recover from the
1085 stale interworking branch prediction. This results in Cortex-A8
1086 executing the new code sequence in the incorrect ARM or Thumb state.
1087 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1088 and also flushes the branch target cache at every context switch.
1089 Note that setting specific bits in the ACTLR register may not be
1090 available in non-secure mode.
1092 config ARM_ERRATA_458693
1093 bool "ARM errata: Processor deadlock when a false hazard is created"
1096 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1097 erratum. For very specific sequences of memory operations, it is
1098 possible for a hazard condition intended for a cache line to instead
1099 be incorrectly associated with a different cache line. This false
1100 hazard might then cause a processor deadlock. The workaround enables
1101 the L1 caching of the NEON accesses and disables the PLD instruction
1102 in the ACTLR register. Note that setting specific bits in the ACTLR
1103 register may not be available in non-secure mode.
1105 config ARM_ERRATA_460075
1106 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1109 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1110 erratum. Any asynchronous access to the L2 cache may encounter a
1111 situation in which recent store transactions to the L2 cache are lost
1112 and overwritten with stale memory contents from external memory. The
1113 workaround disables the write-allocate mode for the L2 cache via the
1114 ACTLR register. Note that setting specific bits in the ACTLR register
1115 may not be available in non-secure mode.
1117 config ARM_ERRATA_742230
1118 bool "ARM errata: DMB operation may be faulty"
1119 depends on CPU_V7 && SMP
1121 This option enables the workaround for the 742230 Cortex-A9
1122 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1123 between two write operations may not ensure the correct visibility
1124 ordering of the two writes. This workaround sets a specific bit in
1125 the diagnostic register of the Cortex-A9 which causes the DMB
1126 instruction to behave as a DSB, ensuring the correct behaviour of
1129 config ARM_ERRATA_742231
1130 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1131 depends on CPU_V7 && SMP
1133 This option enables the workaround for the 742231 Cortex-A9
1134 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1135 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1136 accessing some data located in the same cache line, may get corrupted
1137 data due to bad handling of the address hazard when the line gets
1138 replaced from one of the CPUs at the same time as another CPU is
1139 accessing it. This workaround sets specific bits in the diagnostic
1140 register of the Cortex-A9 which reduces the linefill issuing
1141 capabilities of the processor.
1143 config PL310_ERRATA_588369
1144 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1145 depends on CACHE_L2X0
1147 The PL310 L2 cache controller implements three types of Clean &
1148 Invalidate maintenance operations: by Physical Address
1149 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1150 They are architecturally defined to behave as the execution of a
1151 clean operation followed immediately by an invalidate operation,
1152 both performing to the same memory location. This functionality
1153 is not correctly implemented in PL310 as clean lines are not
1154 invalidated as a result of these operations.
1156 config ARM_ERRATA_720789
1157 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1158 depends on CPU_V7 && SMP
1160 This option enables the workaround for the 720789 Cortex-A9 (prior to
1161 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1162 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1163 As a consequence of this erratum, some TLB entries which should be
1164 invalidated are not, resulting in an incoherency in the system page
1165 tables. The workaround changes the TLB flushing routines to invalidate
1166 entries regardless of the ASID.
1168 config PL310_ERRATA_727915
1169 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1170 depends on CACHE_L2X0
1172 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1173 operation (offset 0x7FC). This operation runs in background so that
1174 PL310 can handle normal accesses while it is in progress. Under very
1175 rare circumstances, due to this erratum, write data can be lost when
1176 PL310 treats a cacheable write transaction during a Clean &
1177 Invalidate by Way operation.
1179 config ARM_ERRATA_743622
1180 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1183 This option enables the workaround for the 743622 Cortex-A9
1184 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1185 optimisation in the Cortex-A9 Store Buffer may lead to data
1186 corruption. This workaround sets a specific bit in the diagnostic
1187 register of the Cortex-A9 which disables the Store Buffer
1188 optimisation, preventing the defect from occurring. This has no
1189 visible impact on the overall performance or power consumption of the
1192 config ARM_ERRATA_751472
1193 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1194 depends on CPU_V7 && SMP
1196 This option enables the workaround for the 751472 Cortex-A9 (prior
1197 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1198 completion of a following broadcasted operation if the second
1199 operation is received by a CPU before the ICIALLUIS has completed,
1200 potentially leading to corrupted entries in the cache or TLB.
1202 config ARM_ERRATA_753970
1203 bool "ARM errata: cache sync operation may be faulty"
1204 depends on CACHE_PL310
1206 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1208 Under some condition the effect of cache sync operation on
1209 the store buffer still remains when the operation completes.
1210 This means that the store buffer is always asked to drain and
1211 this prevents it from merging any further writes. The workaround
1212 is to replace the normal offset of cache sync operation (0x730)
1213 by another offset targeting an unmapped PL310 register 0x740.
1214 This has the same effect as the cache sync operation: store buffer
1215 drain and waiting for all buffers empty.
1217 config ARM_ERRATA_754322
1218 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1221 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1222 r3p*) erratum. A speculative memory access may cause a page table walk
1223 which starts prior to an ASID switch but completes afterwards. This
1224 can populate the micro-TLB with a stale entry which may be hit with
1225 the new ASID. This workaround places two dsb instructions in the mm
1226 switching code so that no page table walks can cross the ASID switch.
1228 config ARM_ERRATA_754327
1229 bool "ARM errata: no automatic Store Buffer drain"
1230 depends on CPU_V7 && SMP
1232 This option enables the workaround for the 754327 Cortex-A9 (prior to
1233 r2p0) erratum. The Store Buffer does not have any automatic draining
1234 mechanism and therefore a livelock may occur if an external agent
1235 continuously polls a memory location waiting to observe an update.
1236 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1237 written polling loops from denying visibility of updates to memory.
1241 source "arch/arm/common/Kconfig"
1251 Find out whether you have ISA slots on your motherboard. ISA is the
1252 name of a bus system, i.e. the way the CPU talks to the other stuff
1253 inside your box. Other bus systems are PCI, EISA, MicroChannel
1254 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1255 newer boards don't support it. If you have ISA, say Y, otherwise N.
1257 # Select ISA DMA controller support
1262 # Select ISA DMA interface
1267 bool "PCI support" if MIGHT_HAVE_PCI
1269 Find out whether you have a PCI motherboard. PCI is the name of a
1270 bus system, i.e. the way the CPU talks to the other stuff inside
1271 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1272 VESA. If you have PCI, say Y, otherwise N.
1278 config PCI_NANOENGINE
1279 bool "BSE nanoEngine PCI support"
1280 depends on SA1100_NANOENGINE
1282 Enable PCI on the BSE nanoEngine board.
1287 # Select the host bridge type
1288 config PCI_HOST_VIA82C505
1290 depends on PCI && ARCH_SHARK
1293 config PCI_HOST_ITE8152
1295 depends on PCI && MACH_ARMCORE
1299 source "drivers/pci/Kconfig"
1301 source "drivers/pcmcia/Kconfig"
1305 menu "Kernel Features"
1307 source "kernel/time/Kconfig"
1310 bool "Symmetric Multi-Processing"
1311 depends on CPU_V6K || CPU_V7
1312 depends on GENERIC_CLOCKEVENTS
1313 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1314 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1315 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1316 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1317 select USE_GENERIC_SMP_HELPERS
1318 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1320 This enables support for systems with more than one CPU. If you have
1321 a system with only one CPU, like most personal computers, say N. If
1322 you have a system with more than one CPU, say Y.
1324 If you say N here, the kernel will run on single and multiprocessor
1325 machines, but will use only one CPU of a multiprocessor machine. If
1326 you say Y here, the kernel will run on many, but not all, single
1327 processor machines. On a single processor machine, the kernel will
1328 run faster if you say N here.
1330 See also <file:Documentation/i386/IO-APIC.txt>,
1331 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1332 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1334 If you don't know what to do here, say N.
1337 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1338 depends on EXPERIMENTAL
1339 depends on SMP && !XIP_KERNEL
1342 SMP kernels contain instructions which fail on non-SMP processors.
1343 Enabling this option allows the kernel to modify itself to make
1344 these instructions safe. Disabling it allows about 1K of space
1347 If you don't know what to do here, say Y.
1352 This option enables support for the ARM system coherency unit
1359 This options enables support for the ARM timer and watchdog unit
1362 prompt "Memory split"
1365 Select the desired split between kernel and user memory.
1367 If you are not absolutely sure what you are doing, leave this
1371 bool "3G/1G user/kernel split"
1373 bool "2G/2G user/kernel split"
1375 bool "1G/3G user/kernel split"
1380 default 0x40000000 if VMSPLIT_1G
1381 default 0x80000000 if VMSPLIT_2G
1385 int "Maximum number of CPUs (2-32)"
1391 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1392 depends on SMP && HOTPLUG && EXPERIMENTAL
1394 Say Y here to experiment with turning CPUs off and on. CPUs
1395 can be controlled through /sys/devices/system/cpu.
1398 bool "Use local timer interrupts"
1401 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1403 Enable support for local timers on SMP platforms, rather then the
1404 legacy IPI broadcast method. Local timers allows the system
1405 accounting to be spread across the timer interval, preventing a
1406 "thundering herd" at every timer tick.
1408 source kernel/Kconfig.preempt
1412 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1413 ARCH_S5PV210 || ARCH_EXYNOS4
1414 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1415 default AT91_TIMER_HZ if ARCH_AT91
1416 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1419 config THUMB2_KERNEL
1420 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1421 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1423 select ARM_ASM_UNIFIED
1425 By enabling this option, the kernel will be compiled in
1426 Thumb-2 mode. A compiler/assembler that understand the unified
1427 ARM-Thumb syntax is needed.
1431 config THUMB2_AVOID_R_ARM_THM_JUMP11
1432 bool "Work around buggy Thumb-2 short branch relocations in gas"
1433 depends on THUMB2_KERNEL && MODULES
1436 Various binutils versions can resolve Thumb-2 branches to
1437 locally-defined, preemptible global symbols as short-range "b.n"
1438 branch instructions.
1440 This is a problem, because there's no guarantee the final
1441 destination of the symbol, or any candidate locations for a
1442 trampoline, are within range of the branch. For this reason, the
1443 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1444 relocation in modules at all, and it makes little sense to add
1447 The symptom is that the kernel fails with an "unsupported
1448 relocation" error when loading some modules.
1450 Until fixed tools are available, passing
1451 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1452 code which hits this problem, at the cost of a bit of extra runtime
1453 stack usage in some cases.
1455 The problem is described in more detail at:
1456 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1458 Only Thumb-2 kernels are affected.
1460 Unless you are sure your tools don't have this problem, say Y.
1462 config ARM_ASM_UNIFIED
1466 bool "Use the ARM EABI to compile the kernel"
1468 This option allows for the kernel to be compiled using the latest
1469 ARM ABI (aka EABI). This is only useful if you are using a user
1470 space environment that is also compiled with EABI.
1472 Since there are major incompatibilities between the legacy ABI and
1473 EABI, especially with regard to structure member alignment, this
1474 option also changes the kernel syscall calling convention to
1475 disambiguate both ABIs and allow for backward compatibility support
1476 (selected with CONFIG_OABI_COMPAT).
1478 To use this you need GCC version 4.0.0 or later.
1481 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1482 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1485 This option preserves the old syscall interface along with the
1486 new (ARM EABI) one. It also provides a compatibility layer to
1487 intercept syscalls that have structure arguments which layout
1488 in memory differs between the legacy ABI and the new ARM EABI
1489 (only for non "thumb" binaries). This option adds a tiny
1490 overhead to all syscalls and produces a slightly larger kernel.
1491 If you know you'll be using only pure EABI user space then you
1492 can say N here. If this option is not selected and you attempt
1493 to execute a legacy ABI binary then the result will be
1494 UNPREDICTABLE (in fact it can be predicted that it won't work
1495 at all). If in doubt say Y.
1497 config ARCH_HAS_HOLES_MEMORYMODEL
1500 config ARCH_SPARSEMEM_ENABLE
1503 config ARCH_SPARSEMEM_DEFAULT
1504 def_bool ARCH_SPARSEMEM_ENABLE
1506 config ARCH_SELECT_MEMORY_MODEL
1507 def_bool ARCH_SPARSEMEM_ENABLE
1509 config HAVE_ARCH_PFN_VALID
1510 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1513 bool "High Memory Support"
1516 The address space of ARM processors is only 4 Gigabytes large
1517 and it has to accommodate user address space, kernel address
1518 space as well as some memory mapped IO. That means that, if you
1519 have a large amount of physical memory and/or IO, not all of the
1520 memory can be "permanently mapped" by the kernel. The physical
1521 memory that is not permanently mapped is called "high memory".
1523 Depending on the selected kernel/user memory split, minimum
1524 vmalloc space and actual amount of RAM, you may not need this
1525 option which should result in a slightly faster kernel.
1530 bool "Allocate 2nd-level pagetables from highmem"
1533 config HW_PERF_EVENTS
1534 bool "Enable hardware performance counter support for perf events"
1535 depends on PERF_EVENTS && CPU_HAS_PMU
1538 Enable hardware performance counter support for perf events. If
1539 disabled, perf events will use software events only.
1543 config FORCE_MAX_ZONEORDER
1544 int "Maximum zone order" if ARCH_SHMOBILE
1545 range 11 64 if ARCH_SHMOBILE
1546 default "9" if SA1111
1549 The kernel memory allocator divides physically contiguous memory
1550 blocks into "zones", where each zone is a power of two number of
1551 pages. This option selects the largest power of two that the kernel
1552 keeps in the memory allocator. If you need to allocate very large
1553 blocks of physically contiguous memory, then you may need to
1554 increase this value.
1556 This config option is actually maximum order plus one. For example,
1557 a value of 11 means that the largest free memory block is 2^10 pages.
1560 bool "Timer and CPU usage LEDs"
1561 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1562 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1563 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1564 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1565 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1566 ARCH_AT91 || ARCH_DAVINCI || \
1567 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1569 If you say Y here, the LEDs on your machine will be used
1570 to provide useful information about your current system status.
1572 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1573 be able to select which LEDs are active using the options below. If
1574 you are compiling a kernel for the EBSA-110 or the LART however, the
1575 red LED will simply flash regularly to indicate that the system is
1576 still functional. It is safe to say Y here if you have a CATS
1577 system, but the driver will do nothing.
1580 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1581 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1582 || MACH_OMAP_PERSEUS2
1584 depends on !GENERIC_CLOCKEVENTS
1585 default y if ARCH_EBSA110
1587 If you say Y here, one of the system LEDs (the green one on the
1588 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1589 will flash regularly to indicate that the system is still
1590 operational. This is mainly useful to kernel hackers who are
1591 debugging unstable kernels.
1593 The LART uses the same LED for both Timer LED and CPU usage LED
1594 functions. You may choose to use both, but the Timer LED function
1595 will overrule the CPU usage LED.
1598 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1600 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1601 || MACH_OMAP_PERSEUS2
1604 If you say Y here, the red LED will be used to give a good real
1605 time indication of CPU usage, by lighting whenever the idle task
1606 is not currently executing.
1608 The LART uses the same LED for both Timer LED and CPU usage LED
1609 functions. You may choose to use both, but the Timer LED function
1610 will overrule the CPU usage LED.
1612 config ALIGNMENT_TRAP
1614 depends on CPU_CP15_MMU
1615 default y if !ARCH_EBSA110
1616 select HAVE_PROC_CPU if PROC_FS
1618 ARM processors cannot fetch/store information which is not
1619 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1620 address divisible by 4. On 32-bit ARM processors, these non-aligned
1621 fetch/store instructions will be emulated in software if you say
1622 here, which has a severe performance impact. This is necessary for
1623 correct operation of some network protocols. With an IP-only
1624 configuration it is safe to say N, otherwise say Y.
1626 config UACCESS_WITH_MEMCPY
1627 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1628 depends on MMU && EXPERIMENTAL
1629 default y if CPU_FEROCEON
1631 Implement faster copy_to_user and clear_user methods for CPU
1632 cores where a 8-word STM instruction give significantly higher
1633 memory write throughput than a sequence of individual 32bit stores.
1635 A possible side effect is a slight increase in scheduling latency
1636 between threads sharing the same address space if they invoke
1637 such copy operations with large buffers.
1639 However, if the CPU data cache is using a write-allocate mode,
1640 this option is unlikely to provide any performance gain.
1644 prompt "Enable seccomp to safely compute untrusted bytecode"
1646 This kernel feature is useful for number crunching applications
1647 that may need to compute untrusted bytecode during their
1648 execution. By using pipes or other transports made available to
1649 the process as file descriptors supporting the read/write
1650 syscalls, it's possible to isolate those applications in
1651 their own address space using seccomp. Once seccomp is
1652 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1653 and the task is only allowed to execute a few safe syscalls
1654 defined by each seccomp mode.
1656 config CC_STACKPROTECTOR
1657 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1658 depends on EXPERIMENTAL
1660 This option turns on the -fstack-protector GCC feature. This
1661 feature puts, at the beginning of functions, a canary value on
1662 the stack just before the return address, and validates
1663 the value just before actually returning. Stack based buffer
1664 overflows (that need to overwrite this return address) now also
1665 overwrite the canary, which gets detected and the attack is then
1666 neutralized via a kernel panic.
1667 This feature requires gcc version 4.2 or above.
1669 config DEPRECATED_PARAM_STRUCT
1670 bool "Provide old way to pass kernel parameters"
1672 This was deprecated in 2001 and announced to live on for 5 years.
1673 Some old boot loaders still use this way.
1680 bool "Flattened Device Tree support"
1682 select OF_EARLY_FLATTREE
1684 Include support for flattened device tree machine descriptions.
1686 # Compressed boot loader in ROM. Yes, we really want to ask about
1687 # TEXT and BSS so we preserve their values in the config files.
1688 config ZBOOT_ROM_TEXT
1689 hex "Compressed ROM boot loader base address"
1692 The physical address at which the ROM-able zImage is to be
1693 placed in the target. Platforms which normally make use of
1694 ROM-able zImage formats normally set this to a suitable
1695 value in their defconfig file.
1697 If ZBOOT_ROM is not enabled, this has no effect.
1699 config ZBOOT_ROM_BSS
1700 hex "Compressed ROM boot loader BSS address"
1703 The base address of an area of read/write memory in the target
1704 for the ROM-able zImage which must be available while the
1705 decompressor is running. It must be large enough to hold the
1706 entire decompressed kernel plus an additional 128 KiB.
1707 Platforms which normally make use of ROM-able zImage formats
1708 normally set this to a suitable value in their defconfig file.
1710 If ZBOOT_ROM is not enabled, this has no effect.
1713 bool "Compressed boot loader in ROM/flash"
1714 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1716 Say Y here if you intend to execute your compressed kernel image
1717 (zImage) directly from ROM or flash. If unsure, say N.
1720 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1721 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1722 default ZBOOT_ROM_NONE
1724 Include experimental SD/MMC loading code in the ROM-able zImage.
1725 With this enabled it is possible to write the the ROM-able zImage
1726 kernel image to an MMC or SD card and boot the kernel straight
1727 from the reset vector. At reset the processor Mask ROM will load
1728 the first part of the the ROM-able zImage which in turn loads the
1729 rest the kernel image to RAM.
1731 config ZBOOT_ROM_NONE
1732 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1734 Do not load image from SD or MMC
1736 config ZBOOT_ROM_MMCIF
1737 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1739 Load image from MMCIF hardware block.
1741 config ZBOOT_ROM_SH_MOBILE_SDHI
1742 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1744 Load image from SDHI hardware block
1749 string "Default kernel command string"
1752 On some architectures (EBSA110 and CATS), there is currently no way
1753 for the boot loader to pass arguments to the kernel. For these
1754 architectures, you should supply some command-line options at build
1755 time by entering them here. As a minimum, you should specify the
1756 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1759 prompt "Kernel command line type" if CMDLINE != ""
1760 default CMDLINE_FROM_BOOTLOADER
1762 config CMDLINE_FROM_BOOTLOADER
1763 bool "Use bootloader kernel arguments if available"
1765 Uses the command-line options passed by the boot loader. If
1766 the boot loader doesn't provide any, the default kernel command
1767 string provided in CMDLINE will be used.
1769 config CMDLINE_EXTEND
1770 bool "Extend bootloader kernel arguments"
1772 The command-line arguments provided by the boot loader will be
1773 appended to the default kernel command string.
1775 config CMDLINE_FORCE
1776 bool "Always use the default kernel command string"
1778 Always use the default kernel command string, even if the boot
1779 loader passes other arguments to the kernel.
1780 This is useful if you cannot or don't want to change the
1781 command-line options your boot loader passes to the kernel.
1785 bool "Kernel Execute-In-Place from ROM"
1786 depends on !ZBOOT_ROM
1788 Execute-In-Place allows the kernel to run from non-volatile storage
1789 directly addressable by the CPU, such as NOR flash. This saves RAM
1790 space since the text section of the kernel is not loaded from flash
1791 to RAM. Read-write sections, such as the data section and stack,
1792 are still copied to RAM. The XIP kernel is not compressed since
1793 it has to run directly from flash, so it will take more space to
1794 store it. The flash address used to link the kernel object files,
1795 and for storing it, is configuration dependent. Therefore, if you
1796 say Y here, you must know the proper physical address where to
1797 store the kernel image depending on your own flash memory usage.
1799 Also note that the make target becomes "make xipImage" rather than
1800 "make zImage" or "make Image". The final kernel binary to put in
1801 ROM memory will be arch/arm/boot/xipImage.
1805 config XIP_PHYS_ADDR
1806 hex "XIP Kernel Physical Location"
1807 depends on XIP_KERNEL
1808 default "0x00080000"
1810 This is the physical address in your flash memory the kernel will
1811 be linked for and stored to. This address is dependent on your
1815 bool "Kexec system call (EXPERIMENTAL)"
1816 depends on EXPERIMENTAL
1818 kexec is a system call that implements the ability to shutdown your
1819 current kernel, and to start another kernel. It is like a reboot
1820 but it is independent of the system firmware. And like a reboot
1821 you can start any kernel with it, not just Linux.
1823 It is an ongoing process to be certain the hardware in a machine
1824 is properly shutdown, so do not be surprised if this code does not
1825 initially work for you. It may help to enable device hotplugging
1829 bool "Export atags in procfs"
1833 Should the atags used to boot the kernel be exported in an "atags"
1834 file in procfs. Useful with kexec.
1837 bool "Build kdump crash kernel (EXPERIMENTAL)"
1838 depends on EXPERIMENTAL
1840 Generate crash dump after being started by kexec. This should
1841 be normally only set in special crash dump kernels which are
1842 loaded in the main kernel with kexec-tools into a specially
1843 reserved region and then later executed after a crash by
1844 kdump/kexec. The crash dump kernel must be compiled to a
1845 memory address not used by the main kernel
1847 For more details see Documentation/kdump/kdump.txt
1849 config AUTO_ZRELADDR
1850 bool "Auto calculation of the decompressed kernel image address"
1851 depends on !ZBOOT_ROM && !ARCH_U300
1853 ZRELADDR is the physical address where the decompressed kernel
1854 image will be placed. If AUTO_ZRELADDR is selected, the address
1855 will be determined at run-time by masking the current IP with
1856 0xf8000000. This assumes the zImage being placed in the first 128MB
1857 from start of memory.
1861 menu "CPU Power Management"
1865 source "drivers/cpufreq/Kconfig"
1868 tristate "CPUfreq driver for i.MX CPUs"
1869 depends on ARCH_MXC && CPU_FREQ
1871 This enables the CPUfreq driver for i.MX CPUs.
1873 config CPU_FREQ_SA1100
1876 config CPU_FREQ_SA1110
1879 config CPU_FREQ_INTEGRATOR
1880 tristate "CPUfreq driver for ARM Integrator CPUs"
1881 depends on ARCH_INTEGRATOR && CPU_FREQ
1884 This enables the CPUfreq driver for ARM Integrator CPUs.
1886 For details, take a look at <file:Documentation/cpu-freq>.
1892 depends on CPU_FREQ && ARCH_PXA && PXA25x
1894 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1899 Internal configuration node for common cpufreq on Samsung SoC
1901 config CPU_FREQ_S3C24XX
1902 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1903 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1906 This enables the CPUfreq driver for the Samsung S3C24XX family
1909 For details, take a look at <file:Documentation/cpu-freq>.
1913 config CPU_FREQ_S3C24XX_PLL
1914 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1915 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1917 Compile in support for changing the PLL frequency from the
1918 S3C24XX series CPUfreq driver. The PLL takes time to settle
1919 after a frequency change, so by default it is not enabled.
1921 This also means that the PLL tables for the selected CPU(s) will
1922 be built which may increase the size of the kernel image.
1924 config CPU_FREQ_S3C24XX_DEBUG
1925 bool "Debug CPUfreq Samsung driver core"
1926 depends on CPU_FREQ_S3C24XX
1928 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1930 config CPU_FREQ_S3C24XX_IODEBUG
1931 bool "Debug CPUfreq Samsung driver IO timing"
1932 depends on CPU_FREQ_S3C24XX
1934 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1936 config CPU_FREQ_S3C24XX_DEBUGFS
1937 bool "Export debugfs for CPUFreq"
1938 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1940 Export status information via debugfs.
1944 source "drivers/cpuidle/Kconfig"
1948 menu "Floating point emulation"
1950 comment "At least one emulation must be selected"
1953 bool "NWFPE math emulation"
1954 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1956 Say Y to include the NWFPE floating point emulator in the kernel.
1957 This is necessary to run most binaries. Linux does not currently
1958 support floating point hardware so you need to say Y here even if
1959 your machine has an FPA or floating point co-processor podule.
1961 You may say N here if you are going to load the Acorn FPEmulator
1962 early in the bootup.
1965 bool "Support extended precision"
1966 depends on FPE_NWFPE
1968 Say Y to include 80-bit support in the kernel floating-point
1969 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1970 Note that gcc does not generate 80-bit operations by default,
1971 so in most cases this option only enlarges the size of the
1972 floating point emulator without any good reason.
1974 You almost surely want to say N here.
1977 bool "FastFPE math emulation (EXPERIMENTAL)"
1978 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1980 Say Y here to include the FAST floating point emulator in the kernel.
1981 This is an experimental much faster emulator which now also has full
1982 precision for the mantissa. It does not support any exceptions.
1983 It is very simple, and approximately 3-6 times faster than NWFPE.
1985 It should be sufficient for most programs. It may be not suitable
1986 for scientific calculations, but you have to check this for yourself.
1987 If you do not feel you need a faster FP emulation you should better
1991 bool "VFP-format floating point maths"
1992 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1994 Say Y to include VFP support code in the kernel. This is needed
1995 if your hardware includes a VFP unit.
1997 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1998 release notes and additional status information.
2000 Say N if your target does not have VFP hardware.
2008 bool "Advanced SIMD (NEON) Extension support"
2009 depends on VFPv3 && CPU_V7
2011 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2016 menu "Userspace binary formats"
2018 source "fs/Kconfig.binfmt"
2021 tristate "RISC OS personality"
2024 Say Y here to include the kernel code necessary if you want to run
2025 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2026 experimental; if this sounds frightening, say N and sleep in peace.
2027 You can also say M here to compile this support as a module (which
2028 will be called arthur).
2032 menu "Power management options"
2034 source "kernel/power/Kconfig"
2036 config ARCH_SUSPEND_POSSIBLE
2037 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2038 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2039 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2044 source "net/Kconfig"
2046 source "drivers/Kconfig"
2050 source "arch/arm/Kconfig.debug"
2052 source "security/Kconfig"
2054 source "crypto/Kconfig"
2056 source "lib/Kconfig"