Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt

   1 * Renesas R-Car DMA Controller Device Tree bindings
   2
   3 Renesas R-Car Generation 2 SoCs have multiple multi-channel DMA
   4 controller instances named DMAC capable of serving multiple clients. Channels
   5 can be dedicated to specific clients or shared between a large number of
   6 clients.
   7
   8 Each DMA client is connected to one dedicated port of the DMAC, identified by
   9 an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
  10 256 clients in total. When the number of hardware channels is lower than the
  11 number of clients to be served, channels must be shared between multiple DMA
  12 clients. The association of DMA clients to DMAC channels is fully dynamic and
  13 not described in these device tree bindings.
  14
  15 Required Properties:
  16
  17 - compatible: must contain "renesas,rcar-dmac"
  18
  19 - reg: base address and length of the registers block for the DMAC
  20
  21 - interrupts: interrupt specifiers for the DMAC, one for each entry in
  22   interrupt-names.
  23 - interrupt-names: one entry per channel, named "ch%u", where %u is the
  24   channel number ranging from zero to the number of channels minus one.
  25
  26 - clock-names: "fck" for the functional clock
  27 - clocks: a list of phandle + clock-specifier pairs, one for each entry
  28   in clock-names.
  29 - clock-names: must contain "fck" for the functional clock.
  30
  31 - #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port
  32   connected to the DMA client
  33 - dma-channels: number of DMA channels
  34
  35 Example: R8A7790 (R-Car H2) SYS-DMACs
  36
  37         dmac0: dma-controller@e6700000 {
  38                 compatible = "renesas,rcar-dmac";
  39                 reg = <0 0xe6700000 0 0x20000>;
  40                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
  41                               0 200 IRQ_TYPE_LEVEL_HIGH
  42                               0 201 IRQ_TYPE_LEVEL_HIGH
  43                               0 202 IRQ_TYPE_LEVEL_HIGH
  44                               0 203 IRQ_TYPE_LEVEL_HIGH
  45                               0 204 IRQ_TYPE_LEVEL_HIGH
  46                               0 205 IRQ_TYPE_LEVEL_HIGH
  47                               0 206 IRQ_TYPE_LEVEL_HIGH
  48                               0 207 IRQ_TYPE_LEVEL_HIGH
  49                               0 208 IRQ_TYPE_LEVEL_HIGH
  50                               0 209 IRQ_TYPE_LEVEL_HIGH
  51                               0 210 IRQ_TYPE_LEVEL_HIGH
  52                               0 211 IRQ_TYPE_LEVEL_HIGH
  53                               0 212 IRQ_TYPE_LEVEL_HIGH
  54                               0 213 IRQ_TYPE_LEVEL_HIGH
  55                               0 214 IRQ_TYPE_LEVEL_HIGH>;
  56                 interrupt-names = "error",
  57                                 "ch0", "ch1", "ch2", "ch3",
  58                                 "ch4", "ch5", "ch6", "ch7",
  59                                 "ch8", "ch9", "ch10", "ch11",
  60                                 "ch12", "ch13", "ch14";
  61                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
  62                 clock-names = "fck";
  63                 #dma-cells = <1>;
  64                 dma-channels = <15>;
  65         };
  66
  67         dmac1: dma-controller@e6720000 {
  68                 compatible = "renesas,rcar-dmac";
  69                 reg = <0 0xe6720000 0 0x20000>;
  70                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
  71                               0 216 IRQ_TYPE_LEVEL_HIGH
  72                               0 217 IRQ_TYPE_LEVEL_HIGH
  73                               0 218 IRQ_TYPE_LEVEL_HIGH
  74                               0 219 IRQ_TYPE_LEVEL_HIGH
  75                               0 308 IRQ_TYPE_LEVEL_HIGH
  76                               0 309 IRQ_TYPE_LEVEL_HIGH
  77                               0 310 IRQ_TYPE_LEVEL_HIGH
  78                               0 311 IRQ_TYPE_LEVEL_HIGH
  79                               0 312 IRQ_TYPE_LEVEL_HIGH
  80                               0 313 IRQ_TYPE_LEVEL_HIGH
  81                               0 314 IRQ_TYPE_LEVEL_HIGH
  82                               0 315 IRQ_TYPE_LEVEL_HIGH
  83                               0 316 IRQ_TYPE_LEVEL_HIGH
  84                               0 317 IRQ_TYPE_LEVEL_HIGH
  85                               0 318 IRQ_TYPE_LEVEL_HIGH>;
  86                 interrupt-names = "error",
  87                                 "ch0", "ch1", "ch2", "ch3",
  88                                 "ch4", "ch5", "ch6", "ch7",
  89                                 "ch8", "ch9", "ch10", "ch11",
  90                                 "ch12", "ch13", "ch14";
  91                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
  92                 clock-names = "fck";
  93                 #dma-cells = <1>;
  94                 dma-channels = <15>;
  95         };