From fef85fc466ec1f4400a902049a519948f6b40979 Mon Sep 17 00:00:00 2001
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Fri, 21 Nov 2014 14:09:57 +0000
Subject: [PATCH] defxx: Correct DEFEA's ESIC MMIO decoding

Use ESIC's memory area 1 (MEMCS1) and its Memory Address High Compare
and Memory Address Low Compare registers to set up the MMIO range for
decoding accesses to PDQ ASIC registers.  Previously the PDQ ASIC was
thought to be addressable with the memory area 0 (MEMCS0) and its Memory
Address Compare and Memory Address Mask registers.

The MMIO range allocated for the option card is preset via ECU (EISA
Configuration Utility) and can be disabled, so handle such a case
gracefully too.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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