From fa0406a8d8c3a4a302085ccd031d999161405f70 Mon Sep 17 00:00:00 2001
From: Paul Walmsley <paul@pwsan.com>
Date: Tue, 12 May 2009 17:27:09 -0600
Subject: [PATCH] OMAP3 SRAM: clear the SDRC PWRENA bit during SDRC frequency
 change

Clear the SDRC_POWER.PWRENA bit before putting the SDRAM into self-refresh
mode.  This prevents the SDRC from attempting to power off the SDRAM,
which can cause the system to hang.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
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