From ef33bc3217c7aa9868f497c4f797cc50ad3ce357 Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Fri, 4 Apr 2014 15:09:47 +0800 Subject: [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations The BCP bit in TCR4/RCR4 register rules as followings: 0 Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 1 Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. For all formats currently supported in the fsl_sai driver, they're exactly sending data on the falling edge and sampling on the rising edge. However, the driver clears this BCP bit for all of them which results click noise when working with SGTL5000 and big noise with WM8962. Thus this patch corrects the BCP settings for all the formats here to fix the nosie issue. Signed-off-by: Nicolin Chen Acked-by: Xiubo Li Signed-off-by: Mark Brown --- Reading git-format-patch failed