From d838ff33ec3a6262f44476d8edc0303acdc16580 Mon Sep 17 00:00:00 2001
From: =?utf8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
Date: Mon, 23 Dec 2013 00:32:34 -0300
Subject: [PATCH] clk: sunxi: add gating support to PLL1
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This commit adds gating support to PLL1 on the clock driver. This makes
the PLL1 implementation fully compatible with PLL4 as well.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
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