From d33f473dcd8e69321f001ba330d648f475b504c9 Mon Sep 17 00:00:00 2001
From: Illia Smyrnov <illia.smyrnov@ti.com>
Date: Mon, 17 Jun 2013 16:31:06 +0300
Subject: [PATCH] spi: omap2-mcspi: Add FIFO buffer support

The MCSPI controller has a built-in FIFO buffer to unload the DMA or interrupt
handler and improve data throughput. This patch adds FIFO buffer support for SPI
transfers in DMA mode.

For SPI transfers in DMA mode, the largest possible FIFO buffer size will be
calculated and set up. The FIFO won't be used for the SPI transfers in DMA mode
if: calculated FIFO buffer size is less then 2 bytes or the FIFO buffer size
isn't multiple of the SPI word length.

Signed-off-by: Illia Smyrnov <illia.smyrnov@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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