From be585d4916864387c53c82b4bde7f04093aac440 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:18 +0000 Subject: [PATCH] rockchip: rk3576: Disable USB3OTG0 U3 port early The RK3576 SoC comes with USB OTG support using a DWC3 controller with a USB2 PHY and a USB3 PHY (USBDP PHY). Some board designs may not use the USBDP PHY for USB3 purpose. For these board to use USB OTG the input clock source must change to use UTMI clk instead of PIPE clk. Change to always disable the USB3OTG0 U3 port early and leave it to the USBDP PHY driver to re-enable the U3 port when a usb3-phy is described in the board device tree. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3576/rk3576.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index 2b1318f9532..a6c2fbdc484 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -33,6 +33,9 @@ #define SGRF_DOMAIN_CON4 0x10 #define SGRF_DOMAIN_CON5 0x14 +#define USB_GRF_BASE 0x2601E000 +#define USB3OTG0_CON1 0x0030 + const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000", [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000", @@ -155,6 +158,9 @@ int arch_cpu_init(void) */ writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20); + /* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */ + writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1); + return 0; } -- 2.47.3