From bb947665f57629404549cb2f6955ab82e0d557b2 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Fri, 8 Aug 2025 16:03:56 +0200 Subject: [PATCH] ARM: stm32mp: fix RIFSC semaphores acquisition Fix RIFSC semaphores acquisition by not returning an error when the current CID already possess the semaphore. Also fix an incorrect mask for the CID value in the SEMCR register. Signed-off-by: Gatien Chevallier Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/mach-stm32mp/stm32mp2/rifsc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-stm32mp/stm32mp2/rifsc.c b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c index 50dececf77b..136ed68bba1 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/rifsc.c +++ b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c @@ -73,7 +73,8 @@ static int stm32_rif_acquire_semaphore(void *base, u32 id) void *addr = base + RIFSC_RISC_PER0_SEMCR(id); /* Check that the semaphore is available */ - if (!stm32_rif_is_semaphore_available(base, id)) + if (!stm32_rif_is_semaphore_available(base, id) && + FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) != RIF_CID1)) return -EACCES; setbits_le32(addr, SEMCR_MUTEX); @@ -171,7 +172,7 @@ static int rifsc_check_access(void *base, u32 id) return -EACCES; } if (!stm32_rif_is_semaphore_available(base, id) && - !(FIELD_GET(RIFSC_RISC_SCID_MASK, sem_reg_value) & BIT(RIF_CID1))) { + !(FIELD_GET(RIFSC_RISC_SCID_MASK, sem_reg_value) & RIF_CID1)) { log_debug("Semaphore unavailable for peripheral %d\n", id); return -EACCES; } -- 2.47.3