From 9c909ac90902a9c0ecca2bc9ac36289cb84990f5 Mon Sep 17 00:00:00 2001
From: Paul Walmsley <paul@pwsan.com>
Date: Thu, 18 Sep 2008 10:30:31 -0600
Subject: [PATCH] OMAP3 clock: DPLLs should enter bypass if new rate is sys_ck

This patch causes a DPLL to enter bypass when it is instructed to set
its rate to that of its bypass clock.  Previously this was only possible
after setting the DPLL rate, then disabling and re-enabling it.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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