From 8b8a7634315be747959b0165e38138879f93cf6c Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Thu, 19 Sep 2013 11:15:49 +0200
Subject: [PATCH] MIPS: Disable usermode switching of the FR bit for MIPS R5
 CPUs.

Currently the kernel will always use the FR=0 register model for O32.  If
an O32 application did enable FR=1 mode, some data from another application
might be leaked in the extra registers becoming visible.

Iow, this patch is meant to make the kernel MIPS R5 tolerant but leaves
proper MIPS R5 support to a future patchset.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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