From 85922e54a3a14a6aee6c0b1fc67d81ef0c60fc9c Mon Sep 17 00:00:00 2001
From: Oskar Schirmer <oskar@linutronix.de>
Date: Thu, 17 Feb 2011 16:42:58 +0100
Subject: [PATCH] arm: tcc8k: Choose PLL settings conforming to board layout

The evaluation board is driven with 1.2V core voltage, so system clock
must not exceed 192 MHz, bus clock must not exceed 110 MHz. Choose
appropriate values and set DTCMWAIT accordingly. Adapt UART setting to
avoid console log interruption and wait for the specified locking time
of 300us to pass.

Signed-off-by: Oskar Schirmer <oskar@linutronix.de>
Cc: bigeasy@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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