From 82ba1c3c9988a8055f4a4d7ca2168e9efe7e7874 Mon Sep 17 00:00:00 2001
From: Mark Zhang <markz@nvidia.com>
Date: Thu, 26 Dec 2013 16:44:24 -0800
Subject: [PATCH] clk: tegra: fix host1x clock on Tegra124

The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents.
Change thte id to tegra_clk_host1x_8 so that the correct clock gets
registered.

Signed-off-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
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