From 81fbf101f2858e63bbb380447a76870924b84653 Mon Sep 17 00:00:00 2001
From: Ruchika Kharwar <ruchika@ti.com>
Date: Thu, 30 May 2013 14:54:09 -0500
Subject: [PATCH] usb: phy: omap-usb3: updated dpll M,N values to support
 DRA7xx devices

Addition of the M and N recommended values for the USB3 PHY DPLL.
Sysclk for DRA7xx is 20MHz.

This yields:
Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz

Signed-off-by: Ruchika Kharwar <ruchika@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
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