From 73acc7df534ff458a81435178dab3ea037ed6d78 Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Thu, 20 Jun 2013 14:56:17 +0200
Subject: [PATCH] MIPS: Fix TLBR-use hazards for R2 cores in the TLB reload
 handlers

MIPS R2 documents state that an execution hazard barrier is needed
after a TLBR before reading EntryLo.

Original patch by Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/5526/
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