From 4e68f5a79da5b595fc40ceff5ebcfa3e6637bf37 Mon Sep 17 00:00:00 2001
From: Rajendra Nayak <rnayak@ti.com>
Date: Mon, 7 May 2012 23:55:21 -0600
Subject: [PATCH] ARM: OMAP3: Fix CM register bit masks

The register bits for MPU_CLK_SRC and IVA2_CLK_SRC in CM_CLKSEL1_PLL
register are 3 bits wide.  Fix the MASK definition accordingly.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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