From 28fe2076004da062e9affac1cec98c697de53eb1 Mon Sep 17 00:00:00 2001
From: Thierry Reding <treding@nvidia.com>
Date: Mon, 26 Jan 2015 16:02:48 +0100
Subject: [PATCH] drm/tegra: sor: Registers are 32-bit

Use a sized unsigned 32-bit data type (u32) to store register contents.
The SOR registers are 32 bits wide irrespective of the architecture's
data width.

Signed-off-by: Thierry Reding <treding@nvidia.com>
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