From: Jacob Pan Date: Tue, 11 Nov 2014 19:30:09 +0000 (-0800) Subject: mfd/axp20x: avoid irq numbering collision X-Git-Tag: omap-for-v3.19/fixes-for-merge-window~27^2~37^3~1 X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ff3bbc5c637ab0843b3a9df717b6cca4e8243f0c;p=pandora-kernel.git mfd/axp20x: avoid irq numbering collision IRQ numbers in axp20x devices are defined with high-order bit first in each IRQ enable/status registers. On Intel platforms it is more common to number IRQs with least significant bit first. Therefore, sharing IRQ# between the two is very difficult. Since AXP288 is a customized PMIC for Intel platform and the amount of shared IRQs are very small, we use separate IRQ numbering. This also fixes collision and a duplicate in WBTO interrupt. e.g. For the 16 interrupts controlled in IRQ enabled registers 1 & 2, on axp20x for ARM, the PMIC local IRQ numbers and register bits are mapped as: IRQ#: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 --------------------------------------------------------- ARM: 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Intel: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Signed-off-by: Todd Brandt Signed-off-by: Jacob Pan Acked-by: Jonathan Cameron Signed-off-by: Lee Jones --- Reading git-diff-tree failed