From: Jisheng Zhang <jszhang@marvell.com>
Date: Wed, 12 Nov 2014 06:22:53 +0000 (+0800)
Subject: irqchip: dw-apb-ictl: Enable IRQ_GC_MASK_CACHE_PER_TYPE
X-Git-Tag: omap-for-v3.20/drop-legacy-3517~160^2~1
X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a9d5fcc00e715354d3fec1e8009c5895b5ba65ba;p=pandora-kernel.git

irqchip: dw-apb-ictl: Enable IRQ_GC_MASK_CACHE_PER_TYPE

The irq_chip_type instances have separate mask registers, so we need to
enable IRQ_GC_MASK_CACHE_PER_TYPE to actually handle separate mask registers.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1415773374-4629-3-git-send-email-jszhang@marvell.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
---

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