From: Tom Rini Date: Tue, 24 Dec 2024 18:07:22 +0000 (-0600) Subject: Subtree merge tag 'v6.12-dts' of dts repo [1] into dts/upstream X-Git-Tag: v2025.04-rc1~17^2~31 X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6a042f830f5d98f6ba3127a5d34b7acfd319690e;p=pandora-u-boot.git Subtree merge tag 'v6.12-dts' of dts repo [1] into dts/upstream [1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git Based on what "git diff" suggests, rename a device tree for imx8mm_venice_defconfig and imx8mp_venice_defconfig Signed-off-by: Tom Rini --- Cc: Tim Harvey --- 6a042f830f5d98f6ba3127a5d34b7acfd319690e diff --cc configs/imx8mm_venice_defconfig index 5f3c5be90ec,00000000000..339dbc32517 mode 100644,000000..100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@@ -1,175 -1,0 +1,175 @@@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x8000 +CONFIG_ENV_OFFSET=0x3f0000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-venice-gw71xx-0x" +CONFIG_TARGET_IMX8MM_VENICE=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_BOOTM_LEN=0x10000000 +CONFIG_SYS_LOAD_ADDR=0x48200000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x3f8000 +CONFIG_PCI=y +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="gsc wd-disable" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y +CONFIG_SYS_DISABLE_AUTOLOAD=y +CONFIG_CMD_WGET=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_UUID=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_TPM=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y - CONFIG_OF_LIST="freescale/imx8mm-venice-gw71xx-0x freescale/imx8mm-venice-gw72xx-0x freescale/imx8mm-venice-gw73xx-0x freescale/imx8mm-venice-gw7901 freescale/imx8mm-venice-gw7902 freescale/imx8mm-venice-gw7903 freescale/imx8mm-venice-gw7904 freescale/imx8mm-venice-gw7905-0x" ++CONFIG_OF_LIST="freescale/imx8mm-venice-gw71xx-0x freescale/imx8mm-venice-gw72xx-0x freescale/imx8mm-venice-gw73xx-0x freescale/imx8mm-venice-gw7901 freescale/imx8mm-venice-gw7902 freescale/imx8mm-venice-gw7903 freescale/imx8mm-venice-gw7904 freescale/imx8mm-venice-gw75xx-0x" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth0" +CONFIG_IP_DEFRAG=y +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MM=y +CONFIG_CLK_IMX8MM=y +CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_XWAY=y +CONFIG_PHY_FIXED=y +CONFIG_DM_MDIO=y +CONFIG_DM_DSA=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_KSZ9477=y +CONFIG_MII=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_IMX=y +CONFIG_PHY_IMX8M_PCIE=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_DM_PMIC_MP5416=y +CONFIG_SPL_DM_PMIC_MP5416=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +# CONFIG_TPM_V1 is not set +CONFIG_TPM2_TIS_SPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Gateworks" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_IMX_WATCHDOG=y +CONFIG_TPM=y +# CONFIG_SPL_SHA512 is not set +# CONFIG_SPL_SHA384 is not set +CONFIG_HEXDUMP=y diff --cc configs/imx8mp_venice_defconfig index faf696fdbd1,00000000000..d058585b2a9 mode 100644,000000..100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@@ -1,175 -1,0 +1,175 @@@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x8000 +CONFIG_ENV_OFFSET=0x3f0000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-venice-gw71xx-2x" +CONFIG_TARGET_IMX8MP_VENICE=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x960000 +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SYS_BOOTM_LEN=0x10000000 +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x3f8000 +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_PCI=y +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="gsc wd-disable" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y +CONFIG_SYS_DISABLE_AUTOLOAD=y +CONFIG_CMD_WGET=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_UUID=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_TPM=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y - CONFIG_OF_LIST="freescale/imx8mp-venice-gw71xx-2x freescale/imx8mp-venice-gw72xx-2x freescale/imx8mp-venice-gw73xx-2x freescale/imx8mp-venice-gw74xx freescale/imx8mp-venice-gw7905-2x" ++CONFIG_OF_LIST="freescale/imx8mp-venice-gw71xx-2x freescale/imx8mp-venice-gw72xx-2x freescale/imx8mp-venice-gw73xx-2x freescale/imx8mp-venice-gw74xx freescale/imx8mp-venice-gw75xx-2x" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_IP_DEFRAG=y +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_SPL_DM=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MP=y +CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_XWAY=y +CONFIG_PHY_FIXED=y +CONFIG_DM_MDIO=y +CONFIG_DM_DSA=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_KSZ9477=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_IMX=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PHY_IMX8M_PCIE=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_DM_PMIC_MP5416=y +CONFIG_SPL_DM_PMIC_MP5416=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +# CONFIG_TPM_V1 is not set +CONFIG_TPM2_TIS_SPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_IMX_WATCHDOG=y +CONFIG_TPM=y +# CONFIG_SPL_SHA512 is not set +# CONFIG_SPL_SHA384 is not set +CONFIG_HEXDUMP=y diff --cc dts/upstream/Bindings/arc/snps,archs-pct.yaml index 00000000000,532f7584f59..532f7584f59 mode 000000,100644..100644 --- a/dts/upstream/Bindings/arc/snps,archs-pct.yaml +++ b/dts/upstream/Bindings/arc/snps,archs-pct.yaml diff --cc dts/upstream/Bindings/arm/cirrus/cirrus,ep9301.yaml index 00000000000,170aad5dd7e..170aad5dd7e mode 000000,100644..100644 --- a/dts/upstream/Bindings/arm/cirrus/cirrus,ep9301.yaml +++ b/dts/upstream/Bindings/arm/cirrus/cirrus,ep9301.yaml diff --cc dts/upstream/Bindings/ata/cirrus,ep9312-pata.yaml index 00000000000,8130923fdc7..8130923fdc7 mode 000000,100644..100644 --- a/dts/upstream/Bindings/ata/cirrus,ep9312-pata.yaml +++ b/dts/upstream/Bindings/ata/cirrus,ep9312-pata.yaml diff --cc dts/upstream/Bindings/board/fsl,bcsr.yaml index 00000000000,df3dd839967..df3dd839967 mode 000000,100644..100644 --- a/dts/upstream/Bindings/board/fsl,bcsr.yaml +++ b/dts/upstream/Bindings/board/fsl,bcsr.yaml diff --cc dts/upstream/Bindings/board/fsl,fpga-qixis-i2c.yaml index 00000000000,28b37772fb6..28b37772fb6 mode 000000,100644..100644 --- a/dts/upstream/Bindings/board/fsl,fpga-qixis-i2c.yaml +++ b/dts/upstream/Bindings/board/fsl,fpga-qixis-i2c.yaml diff --cc dts/upstream/Bindings/board/fsl,fpga-qixis.yaml index 00000000000,5a3cd431ef6..5a3cd431ef6 mode 000000,100644..100644 --- a/dts/upstream/Bindings/board/fsl,fpga-qixis.yaml +++ b/dts/upstream/Bindings/board/fsl,fpga-qixis.yaml diff --cc dts/upstream/Bindings/bus/qcom,ebi2.yaml index 00000000000,1b1fb3538e6..1b1fb3538e6 mode 000000,100644..100644 --- a/dts/upstream/Bindings/bus/qcom,ebi2.yaml +++ b/dts/upstream/Bindings/bus/qcom,ebi2.yaml diff --cc dts/upstream/Bindings/clock/mediatek,syscon.yaml index 00000000000,10483e26878..10483e26878 mode 000000,100644..100644 --- a/dts/upstream/Bindings/clock/mediatek,syscon.yaml +++ b/dts/upstream/Bindings/clock/mediatek,syscon.yaml diff --cc dts/upstream/Bindings/clock/nxp,lpc3220-clk.yaml index 00000000000,16f79616d18..16f79616d18 mode 000000,100644..100644 --- a/dts/upstream/Bindings/clock/nxp,lpc3220-clk.yaml +++ b/dts/upstream/Bindings/clock/nxp,lpc3220-clk.yaml diff --cc dts/upstream/Bindings/clock/nxp,lpc3220-usb-clk.yaml index 00000000000,10361d2292f..10361d2292f mode 000000,100644..100644 --- a/dts/upstream/Bindings/clock/nxp,lpc3220-usb-clk.yaml +++ b/dts/upstream/Bindings/clock/nxp,lpc3220-usb-clk.yaml diff --cc dts/upstream/Bindings/clock/qcom,qcs404-turingcc.yaml index 00000000000,033e010754a..033e010754a mode 000000,100644..100644 --- a/dts/upstream/Bindings/clock/qcom,qcs404-turingcc.yaml +++ b/dts/upstream/Bindings/clock/qcom,qcs404-turingcc.yaml diff --cc dts/upstream/Bindings/clock/qcom,sm4450-camcc.yaml index 00000000000,f54ce865880..f54ce865880 mode 000000,100644..100644 --- a/dts/upstream/Bindings/clock/qcom,sm4450-camcc.yaml +++ b/dts/upstream/Bindings/clock/qcom,sm4450-camcc.yaml diff --cc dts/upstream/Bindings/clock/qcom,sm4450-dispcc.yaml index 00000000000,2aa05353eff..2aa05353eff mode 000000,100644..100644 --- a/dts/upstream/Bindings/clock/qcom,sm4450-dispcc.yaml +++ b/dts/upstream/Bindings/clock/qcom,sm4450-dispcc.yaml diff --cc dts/upstream/Bindings/clock/qcom,sm8150-camcc.yaml index 00000000000,5e9f62d7866..5e9f62d7866 mode 000000,100644..100644 --- a/dts/upstream/Bindings/clock/qcom,sm8150-camcc.yaml +++ b/dts/upstream/Bindings/clock/qcom,sm8150-camcc.yaml diff --cc dts/upstream/Bindings/clock/renesas,rzv2h-cpg.yaml index 00000000000,926c503bed1..926c503bed1 mode 000000,100644..100644 --- a/dts/upstream/Bindings/clock/renesas,rzv2h-cpg.yaml +++ b/dts/upstream/Bindings/clock/renesas,rzv2h-cpg.yaml diff --cc dts/upstream/Bindings/clock/rockchip,rk3576-cru.yaml index 00000000000,9c9b36049c7..9c9b36049c7 mode 000000,100644..100644 --- a/dts/upstream/Bindings/clock/rockchip,rk3576-cru.yaml +++ b/dts/upstream/Bindings/clock/rockchip,rk3576-cru.yaml diff --cc dts/upstream/Bindings/clock/samsung,exynosautov920-clock.yaml index 00000000000,3330b272747..3330b272747 mode 000000,100644..100644 --- a/dts/upstream/Bindings/clock/samsung,exynosautov920-clock.yaml +++ b/dts/upstream/Bindings/clock/samsung,exynosautov920-clock.yaml diff --cc dts/upstream/Bindings/display/elgin,jg10309-01.yaml index 00000000000,faca0cb3f15..faca0cb3f15 mode 000000,100644..100644 --- a/dts/upstream/Bindings/display/elgin,jg10309-01.yaml +++ b/dts/upstream/Bindings/display/elgin,jg10309-01.yaml diff --cc dts/upstream/Bindings/display/panel/boe,tv101wum-ll2.yaml index 00000000000,dced98e1c69..dced98e1c69 mode 000000,100644..100644 --- a/dts/upstream/Bindings/display/panel/boe,tv101wum-ll2.yaml +++ b/dts/upstream/Bindings/display/panel/boe,tv101wum-ll2.yaml diff --cc dts/upstream/Bindings/dma/cirrus,ep9301-dma-m2m.yaml index 00000000000,871b76ddf90..871b76ddf90 mode 000000,100644..100644 --- a/dts/upstream/Bindings/dma/cirrus,ep9301-dma-m2m.yaml +++ b/dts/upstream/Bindings/dma/cirrus,ep9301-dma-m2m.yaml diff --cc dts/upstream/Bindings/dma/cirrus,ep9301-dma-m2p.yaml index 00000000000,d14c3155354..d14c3155354 mode 000000,100644..100644 --- a/dts/upstream/Bindings/dma/cirrus,ep9301-dma-m2p.yaml +++ b/dts/upstream/Bindings/dma/cirrus,ep9301-dma-m2p.yaml diff --cc dts/upstream/Bindings/dma/loongson,ls1b-apbdma.yaml index 00000000000,4c7d2fb7b29..4c7d2fb7b29 mode 000000,100644..100644 --- a/dts/upstream/Bindings/dma/loongson,ls1b-apbdma.yaml +++ b/dts/upstream/Bindings/dma/loongson,ls1b-apbdma.yaml diff --cc dts/upstream/Bindings/dma/marvell,xor-v2.yaml index 00000000000,646b4e779d8..646b4e779d8 mode 000000,100644..100644 --- a/dts/upstream/Bindings/dma/marvell,xor-v2.yaml +++ b/dts/upstream/Bindings/dma/marvell,xor-v2.yaml diff --cc dts/upstream/Bindings/dma/nxp,lpc3220-dmamux.yaml index 00000000000,32f20874415..32f20874415 mode 000000,100644..100644 --- a/dts/upstream/Bindings/dma/nxp,lpc3220-dmamux.yaml +++ b/dts/upstream/Bindings/dma/nxp,lpc3220-dmamux.yaml diff --cc dts/upstream/Bindings/extcon/linux,extcon-usb-gpio.yaml index 00000000000,8856107bdd3..8856107bdd3 mode 000000,100644..100644 --- a/dts/upstream/Bindings/extcon/linux,extcon-usb-gpio.yaml +++ b/dts/upstream/Bindings/extcon/linux,extcon-usb-gpio.yaml diff --cc dts/upstream/Bindings/firmware/nxp,imx95-scmi.yaml index 00000000000,1a95010a546..1a95010a546 mode 000000,100644..100644 --- a/dts/upstream/Bindings/firmware/nxp,imx95-scmi.yaml +++ b/dts/upstream/Bindings/firmware/nxp,imx95-scmi.yaml diff --cc dts/upstream/Bindings/gpio/nxp,lpc3220-gpio.yaml index 00000000000,25b5494393c..25b5494393c mode 000000,100644..100644 --- a/dts/upstream/Bindings/gpio/nxp,lpc3220-gpio.yaml +++ b/dts/upstream/Bindings/gpio/nxp,lpc3220-gpio.yaml diff --cc dts/upstream/Bindings/hwlock/sprd,hwspinlock-r3p0.yaml index 00000000000,abe11df2576..abe11df2576 mode 000000,100644..100644 --- a/dts/upstream/Bindings/hwlock/sprd,hwspinlock-r3p0.yaml +++ b/dts/upstream/Bindings/hwlock/sprd,hwspinlock-r3p0.yaml diff --cc dts/upstream/Bindings/hwmon/lltc,ltc2978.yaml index 00000000000,1f98da32f3f..1f98da32f3f mode 000000,100644..100644 --- a/dts/upstream/Bindings/hwmon/lltc,ltc2978.yaml +++ b/dts/upstream/Bindings/hwmon/lltc,ltc2978.yaml diff --cc dts/upstream/Bindings/hwmon/maxim,max31790.yaml index 00000000000,b1ff496f87f..b1ff496f87f mode 000000,100644..100644 --- a/dts/upstream/Bindings/hwmon/maxim,max31790.yaml +++ b/dts/upstream/Bindings/hwmon/maxim,max31790.yaml diff --cc dts/upstream/Bindings/hwmon/sophgo,sg2042-hwmon-mcu.yaml index 00000000000,f0667ac41d7..f0667ac41d7 mode 000000,100644..100644 --- a/dts/upstream/Bindings/hwmon/sophgo,sg2042-hwmon-mcu.yaml +++ b/dts/upstream/Bindings/hwmon/sophgo,sg2042-hwmon-mcu.yaml diff --cc dts/upstream/Bindings/i2c/sprd,sc9860-i2c.yaml index 00000000000,ec0d39e73d2..ec0d39e73d2 mode 000000,100644..100644 --- a/dts/upstream/Bindings/i2c/sprd,sc9860-i2c.yaml +++ b/dts/upstream/Bindings/i2c/sprd,sc9860-i2c.yaml diff --cc dts/upstream/Bindings/i2c/tsd,mule-i2c-mux.yaml index 00000000000,28139b67666..28139b67666 mode 000000,100644..100644 --- a/dts/upstream/Bindings/i2c/tsd,mule-i2c-mux.yaml +++ b/dts/upstream/Bindings/i2c/tsd,mule-i2c-mux.yaml diff --cc dts/upstream/Bindings/iio/accel/adi,adxl380.yaml index 00000000000,f1ff5ff4f47..f1ff5ff4f47 mode 000000,100644..100644 --- a/dts/upstream/Bindings/iio/accel/adi,adxl380.yaml +++ b/dts/upstream/Bindings/iio/accel/adi,adxl380.yaml diff --cc dts/upstream/Bindings/iio/adc/adi,ad4000.yaml index 00000000000,e413a9d8d2a..e413a9d8d2a mode 000000,100644..100644 --- a/dts/upstream/Bindings/iio/adc/adi,ad4000.yaml +++ b/dts/upstream/Bindings/iio/adc/adi,ad4000.yaml diff --cc dts/upstream/Bindings/iio/adc/adi,ad4695.yaml index 00000000000,310f046e139..310f046e139 mode 000000,100644..100644 --- a/dts/upstream/Bindings/iio/adc/adi,ad4695.yaml +++ b/dts/upstream/Bindings/iio/adc/adi,ad4695.yaml diff --cc dts/upstream/Bindings/iio/adc/microchip,pac1921.yaml index 00000000000,12e56b1b3d3..12e56b1b3d3 mode 000000,100644..100644 --- a/dts/upstream/Bindings/iio/adc/microchip,pac1921.yaml +++ b/dts/upstream/Bindings/iio/adc/microchip,pac1921.yaml diff --cc dts/upstream/Bindings/iio/adc/sophgo,cv1800b-saradc.yaml index 00000000000,f652b98615f..f652b98615f mode 000000,100644..100644 --- a/dts/upstream/Bindings/iio/adc/sophgo,cv1800b-saradc.yaml +++ b/dts/upstream/Bindings/iio/adc/sophgo,cv1800b-saradc.yaml diff --cc dts/upstream/Bindings/iio/dac/adi,ltc2664.yaml index 00000000000,33490853497..33490853497 mode 000000,100644..100644 --- a/dts/upstream/Bindings/iio/dac/adi,ltc2664.yaml +++ b/dts/upstream/Bindings/iio/dac/adi,ltc2664.yaml diff --cc dts/upstream/Bindings/iio/dac/adi,ltc2672.yaml index 00000000000,c8c434c1064..c8c434c1064 mode 000000,100644..100644 --- a/dts/upstream/Bindings/iio/dac/adi,ltc2672.yaml +++ b/dts/upstream/Bindings/iio/dac/adi,ltc2672.yaml diff --cc dts/upstream/Bindings/iio/dac/dac.yaml index 00000000000,daa40724e1c..daa40724e1c mode 000000,100644..100644 --- a/dts/upstream/Bindings/iio/dac/dac.yaml +++ b/dts/upstream/Bindings/iio/dac/dac.yaml diff --cc dts/upstream/Bindings/iio/humidity/sciosense,ens210.yaml index 00000000000,ed0ea938f7f..ed0ea938f7f mode 000000,100644..100644 --- a/dts/upstream/Bindings/iio/humidity/sciosense,ens210.yaml +++ b/dts/upstream/Bindings/iio/humidity/sciosense,ens210.yaml diff --cc dts/upstream/Bindings/iio/light/rohm,bh1745.yaml index 00000000000,44896795c67..44896795c67 mode 000000,100644..100644 --- a/dts/upstream/Bindings/iio/light/rohm,bh1745.yaml +++ b/dts/upstream/Bindings/iio/light/rohm,bh1745.yaml diff --cc dts/upstream/Bindings/iio/pressure/sensirion,sdp500.yaml index 00000000000,813239f6879..813239f6879 mode 000000,100644..100644 --- a/dts/upstream/Bindings/iio/pressure/sensirion,sdp500.yaml +++ b/dts/upstream/Bindings/iio/pressure/sensirion,sdp500.yaml diff --cc dts/upstream/Bindings/iio/proximity/awinic,aw96103.yaml index 00000000000,7a83ceced11..7a83ceced11 mode 000000,100644..100644 --- a/dts/upstream/Bindings/iio/proximity/awinic,aw96103.yaml +++ b/dts/upstream/Bindings/iio/proximity/awinic,aw96103.yaml diff --cc dts/upstream/Bindings/iio/proximity/tyhx,hx9023s.yaml index 00000000000,64ce8bc8bd3..64ce8bc8bd3 mode 000000,100644..100644 --- a/dts/upstream/Bindings/iio/proximity/tyhx,hx9023s.yaml +++ b/dts/upstream/Bindings/iio/proximity/tyhx,hx9023s.yaml diff --cc dts/upstream/Bindings/input/cirrus,ep9307-keypad.yaml index 00000000000,a0d2460c55a..a0d2460c55a mode 000000,100644..100644 --- a/dts/upstream/Bindings/input/cirrus,ep9307-keypad.yaml +++ b/dts/upstream/Bindings/input/cirrus,ep9307-keypad.yaml diff --cc dts/upstream/Bindings/input/rotary-encoder.yaml index 00000000000,e315aab7f58..e315aab7f58 mode 000000,100644..100644 --- a/dts/upstream/Bindings/input/rotary-encoder.yaml +++ b/dts/upstream/Bindings/input/rotary-encoder.yaml diff --cc dts/upstream/Bindings/input/touchscreen/adi,ad7879.yaml index 00000000000,caa5fa3cc3f..caa5fa3cc3f mode 000000,100644..100644 --- a/dts/upstream/Bindings/input/touchscreen/adi,ad7879.yaml +++ b/dts/upstream/Bindings/input/touchscreen/adi,ad7879.yaml diff --cc dts/upstream/Bindings/input/touchscreen/ti,ads7843.yaml index 00000000000,604921733d2..604921733d2 mode 000000,100644..100644 --- a/dts/upstream/Bindings/input/touchscreen/ti,ads7843.yaml +++ b/dts/upstream/Bindings/input/touchscreen/ti,ads7843.yaml diff --cc dts/upstream/Bindings/input/touchscreen/toradex,vf50-touchscreen.yaml index 00000000000,5094c5183c7..5094c5183c7 mode 000000,100644..100644 --- a/dts/upstream/Bindings/input/touchscreen/toradex,vf50-touchscreen.yaml +++ b/dts/upstream/Bindings/input/touchscreen/toradex,vf50-touchscreen.yaml diff --cc dts/upstream/Bindings/interrupt-controller/aspeed,ast2400-vic.yaml index 00000000000,73e8b9a39bd..73e8b9a39bd mode 000000,100644..100644 --- a/dts/upstream/Bindings/interrupt-controller/aspeed,ast2400-vic.yaml +++ b/dts/upstream/Bindings/interrupt-controller/aspeed,ast2400-vic.yaml diff --cc dts/upstream/Bindings/interrupt-controller/brcm,bcm2836-l1-intc.yaml index 00000000000,5fda626c80c..5fda626c80c mode 000000,100644..100644 --- a/dts/upstream/Bindings/interrupt-controller/brcm,bcm2836-l1-intc.yaml +++ b/dts/upstream/Bindings/interrupt-controller/brcm,bcm2836-l1-intc.yaml diff --cc dts/upstream/Bindings/leds/sprd,sc2731-bltc.yaml index 00000000000,5853410c7a4..5853410c7a4 mode 000000,100644..100644 --- a/dts/upstream/Bindings/leds/sprd,sc2731-bltc.yaml +++ b/dts/upstream/Bindings/leds/sprd,sc2731-bltc.yaml diff --cc dts/upstream/Bindings/leds/ti.lm36922.yaml index 00000000000,8ffbc6b785a..8ffbc6b785a mode 000000,100644..100644 --- a/dts/upstream/Bindings/leds/ti.lm36922.yaml +++ b/dts/upstream/Bindings/leds/ti.lm36922.yaml diff --cc dts/upstream/Bindings/media/i2c/ovti,og01a1b.yaml index 00000000000,ca57c01739d..ca57c01739d mode 000000,100644..100644 --- a/dts/upstream/Bindings/media/i2c/ovti,og01a1b.yaml +++ b/dts/upstream/Bindings/media/i2c/ovti,og01a1b.yaml diff --cc dts/upstream/Bindings/mfd/adi,adp5585.yaml index 00000000000,ee2272f754a..ee2272f754a mode 000000,100644..100644 --- a/dts/upstream/Bindings/mfd/adi,adp5585.yaml +++ b/dts/upstream/Bindings/mfd/adi,adp5585.yaml diff --cc dts/upstream/Bindings/misc/aspeed,ast2400-cvic.yaml index 00000000000,accf1a7ecf1..accf1a7ecf1 mode 000000,100644..100644 --- a/dts/upstream/Bindings/misc/aspeed,ast2400-cvic.yaml +++ b/dts/upstream/Bindings/misc/aspeed,ast2400-cvic.yaml diff --cc dts/upstream/Bindings/mmc/atmel,sama5d2-sdhci.yaml index 00000000000,8c8ade88e8f..8c8ade88e8f mode 000000,100644..100644 --- a/dts/upstream/Bindings/mmc/atmel,sama5d2-sdhci.yaml +++ b/dts/upstream/Bindings/mmc/atmel,sama5d2-sdhci.yaml diff --cc dts/upstream/Bindings/mmc/nuvoton,ma35d1-sdhci.yaml index 00000000000,4d787147c30..4d787147c30 mode 000000,100644..100644 --- a/dts/upstream/Bindings/mmc/nuvoton,ma35d1-sdhci.yaml +++ b/dts/upstream/Bindings/mmc/nuvoton,ma35d1-sdhci.yaml diff --cc dts/upstream/Bindings/mtd/technologic,nand.yaml index 00000000000,f9d87c46094..f9d87c46094 mode 000000,100644..100644 --- a/dts/upstream/Bindings/mtd/technologic,nand.yaml +++ b/dts/upstream/Bindings/mtd/technologic,nand.yaml diff --cc dts/upstream/Bindings/net/bluetooth/amlogic,w155s2-bt.yaml index 00000000000,6fd7557039d..6fd7557039d mode 000000,100644..100644 --- a/dts/upstream/Bindings/net/bluetooth/amlogic,w155s2-bt.yaml +++ b/dts/upstream/Bindings/net/bluetooth/amlogic,w155s2-bt.yaml diff --cc dts/upstream/Bindings/net/can/microchip,mcp2510.yaml index 00000000000,db446dde684..db446dde684 mode 000000,100644..100644 --- a/dts/upstream/Bindings/net/can/microchip,mcp2510.yaml +++ b/dts/upstream/Bindings/net/can/microchip,mcp2510.yaml diff --cc dts/upstream/Bindings/net/can/rockchip,rk3568v2-canfd.yaml index 00000000000,a077c033001..a077c033001 mode 000000,100644..100644 --- a/dts/upstream/Bindings/net/can/rockchip,rk3568v2-canfd.yaml +++ b/dts/upstream/Bindings/net/can/rockchip,rk3568v2-canfd.yaml diff --cc dts/upstream/Bindings/net/cirrus,ep9301-eth.yaml index 00000000000,ad091530709..ad091530709 mode 000000,100644..100644 --- a/dts/upstream/Bindings/net/cirrus,ep9301-eth.yaml +++ b/dts/upstream/Bindings/net/cirrus,ep9301-eth.yaml diff --cc dts/upstream/Bindings/net/fsl,cpm-enet.yaml index 00000000000,da836477e8b..da836477e8b mode 000000,100644..100644 --- a/dts/upstream/Bindings/net/fsl,cpm-enet.yaml +++ b/dts/upstream/Bindings/net/fsl,cpm-enet.yaml diff --cc dts/upstream/Bindings/net/fsl,cpm-mdio.yaml index 00000000000,b1791a3c490..b1791a3c490 mode 000000,100644..100644 --- a/dts/upstream/Bindings/net/fsl,cpm-mdio.yaml +++ b/dts/upstream/Bindings/net/fsl,cpm-mdio.yaml diff --cc dts/upstream/Bindings/net/maxim,ds26522.yaml index 00000000000,6c97eda217e..6c97eda217e mode 000000,100644..100644 --- a/dts/upstream/Bindings/net/maxim,ds26522.yaml +++ b/dts/upstream/Bindings/net/maxim,ds26522.yaml diff --cc dts/upstream/Bindings/net/microchip,lan8650.yaml index 00000000000,61e11d4a07c..61e11d4a07c mode 000000,100644..100644 --- a/dts/upstream/Bindings/net/microchip,lan8650.yaml +++ b/dts/upstream/Bindings/net/microchip,lan8650.yaml diff --cc dts/upstream/Bindings/net/wireless/marvell,sd8787.yaml index 00000000000,1715b22e0dc..1715b22e0dc mode 000000,100644..100644 --- a/dts/upstream/Bindings/net/wireless/marvell,sd8787.yaml +++ b/dts/upstream/Bindings/net/wireless/marvell,sd8787.yaml diff --cc dts/upstream/Bindings/pci/altr,msi-controller.yaml index 00000000000,98814862d00..98814862d00 mode 000000,100644..100644 --- a/dts/upstream/Bindings/pci/altr,msi-controller.yaml +++ b/dts/upstream/Bindings/pci/altr,msi-controller.yaml diff --cc dts/upstream/Bindings/pci/altr,pcie-root-port.yaml index 00000000000,52533fccc13..52533fccc13 mode 000000,100644..100644 --- a/dts/upstream/Bindings/pci/altr,pcie-root-port.yaml +++ b/dts/upstream/Bindings/pci/altr,pcie-root-port.yaml diff --cc dts/upstream/Bindings/perf/arm,ni.yaml index 00000000000,d66fffa256d..d66fffa256d mode 000000,100644..100644 --- a/dts/upstream/Bindings/perf/arm,ni.yaml +++ b/dts/upstream/Bindings/perf/arm,ni.yaml diff --cc dts/upstream/Bindings/phy/hisilicon,hi3798cv200-combphy.yaml index 00000000000,81001966f65..81001966f65 mode 000000,100644..100644 --- a/dts/upstream/Bindings/phy/hisilicon,hi3798cv200-combphy.yaml +++ b/dts/upstream/Bindings/phy/hisilicon,hi3798cv200-combphy.yaml diff --cc dts/upstream/Bindings/phy/nuvoton,ma35d1-usb2-phy.yaml index 00000000000,fff858c909a..fff858c909a mode 000000,100644..100644 --- a/dts/upstream/Bindings/phy/nuvoton,ma35d1-usb2-phy.yaml +++ b/dts/upstream/Bindings/phy/nuvoton,ma35d1-usb2-phy.yaml diff --cc dts/upstream/Bindings/phy/qcom,sata-phy.yaml index 00000000000,0bf18d32c13..0bf18d32c13 mode 000000,100644..100644 --- a/dts/upstream/Bindings/phy/qcom,sata-phy.yaml +++ b/dts/upstream/Bindings/phy/qcom,sata-phy.yaml diff --cc dts/upstream/Bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml index 00000000000,1bb386b4203..1bb386b4203 mode 000000,100644..100644 --- a/dts/upstream/Bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml diff --cc dts/upstream/Bindings/pinctrl/qcom,apq8064-pinctrl.yaml index 00000000000,f251dcd4bb7..f251dcd4bb7 mode 000000,100644..100644 --- a/dts/upstream/Bindings/pinctrl/qcom,apq8064-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,apq8064-pinctrl.yaml diff --cc dts/upstream/Bindings/pinctrl/qcom,apq8084-pinctrl.yaml index 00000000000,38877d8b97f..38877d8b97f mode 000000,100644..100644 --- a/dts/upstream/Bindings/pinctrl/qcom,apq8084-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,apq8084-pinctrl.yaml diff --cc dts/upstream/Bindings/pinctrl/qcom,ipq4019-pinctrl.yaml index 00000000000,cc5de9f7768..cc5de9f7768 mode 000000,100644..100644 --- a/dts/upstream/Bindings/pinctrl/qcom,ipq4019-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,ipq4019-pinctrl.yaml diff --cc dts/upstream/Bindings/pinctrl/qcom,ipq8064-pinctrl.yaml index 00000000000,58f11e1bdd4..58f11e1bdd4 mode 000000,100644..100644 --- a/dts/upstream/Bindings/pinctrl/qcom,ipq8064-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,ipq8064-pinctrl.yaml diff --cc dts/upstream/Bindings/pinctrl/sophgo,cv1800-pinctrl.yaml index 00000000000,1e6a55afe26..1e6a55afe26 mode 000000,100644..100644 --- a/dts/upstream/Bindings/pinctrl/sophgo,cv1800-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/sophgo,cv1800-pinctrl.yaml diff --cc dts/upstream/Bindings/platform/microsoft,surface-sam.yaml index 00000000000,b33d26f15b2..b33d26f15b2 mode 000000,100644..100644 --- a/dts/upstream/Bindings/platform/microsoft,surface-sam.yaml +++ b/dts/upstream/Bindings/platform/microsoft,surface-sam.yaml diff --cc dts/upstream/Bindings/pwm/cirrus,ep9301-pwm.yaml index 00000000000,903210ef9c3..903210ef9c3 mode 000000,100644..100644 --- a/dts/upstream/Bindings/pwm/cirrus,ep9301-pwm.yaml +++ b/dts/upstream/Bindings/pwm/cirrus,ep9301-pwm.yaml diff --cc dts/upstream/Bindings/regulator/mediatek,mt6397-regulator.yaml index 00000000000,50db6782a09..50db6782a09 mode 000000,100644..100644 --- a/dts/upstream/Bindings/regulator/mediatek,mt6397-regulator.yaml +++ b/dts/upstream/Bindings/regulator/mediatek,mt6397-regulator.yaml diff --cc dts/upstream/Bindings/remoteproc/ti,k3-m4f-rproc.yaml index 00000000000,2bd0752b6ba..2bd0752b6ba mode 000000,100644..100644 --- a/dts/upstream/Bindings/remoteproc/ti,k3-m4f-rproc.yaml +++ b/dts/upstream/Bindings/remoteproc/ti,k3-m4f-rproc.yaml diff --cc dts/upstream/Bindings/rng/rockchip,rk3568-rng.yaml index 00000000000,e0595814a6d..e0595814a6d mode 000000,100644..100644 --- a/dts/upstream/Bindings/rng/rockchip,rk3568-rng.yaml +++ b/dts/upstream/Bindings/rng/rockchip,rk3568-rng.yaml diff --cc dts/upstream/Bindings/rtc/sprd,sc2731-rtc.yaml index 00000000000,f3d20e97696..f3d20e97696 mode 000000,100644..100644 --- a/dts/upstream/Bindings/rtc/sprd,sc2731-rtc.yaml +++ b/dts/upstream/Bindings/rtc/sprd,sc2731-rtc.yaml diff --cc dts/upstream/Bindings/serial/serial-peripheral-props.yaml index 00000000000,b4a73214d20..b4a73214d20 mode 000000,100644..100644 --- a/dts/upstream/Bindings/serial/serial-peripheral-props.yaml +++ b/dts/upstream/Bindings/serial/serial-peripheral-props.yaml diff --cc dts/upstream/Bindings/soc/bcm/brcm,bcm2711-avs-monitor.yaml index 00000000000,e02d9d7e7d9..e02d9d7e7d9 mode 000000,100644..100644 --- a/dts/upstream/Bindings/soc/bcm/brcm,bcm2711-avs-monitor.yaml +++ b/dts/upstream/Bindings/soc/bcm/brcm,bcm2711-avs-monitor.yaml diff --cc dts/upstream/Bindings/soc/cirrus/cirrus,ep9301-syscon.yaml index 00000000000,7cb1b411498..7cb1b411498 mode 000000,100644..100644 --- a/dts/upstream/Bindings/soc/cirrus/cirrus,ep9301-syscon.yaml +++ b/dts/upstream/Bindings/soc/cirrus/cirrus,ep9301-syscon.yaml diff --cc dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml index 00000000000,3b50e0a003c..3b50e0a003c mode 000000,100644..100644 --- a/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml +++ b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml diff --cc dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml index 00000000000,71ae64cb8a4..71ae64cb8a4 mode 000000,100644..100644 --- a/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml +++ b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml diff --cc dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml index 00000000000,64ffbf75dd9..64ffbf75dd9 mode 000000,100644..100644 --- a/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml +++ b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml diff --cc dts/upstream/Bindings/soc/fsl/fsl,rcpm.yaml index 00000000000,03d71ab930d..03d71ab930d mode 000000,100644..100644 --- a/dts/upstream/Bindings/soc/fsl/fsl,rcpm.yaml +++ b/dts/upstream/Bindings/soc/fsl/fsl,rcpm.yaml diff --cc dts/upstream/Bindings/sound/cirrus,cs4271.yaml index 00000000000,68fbf5cc208..68fbf5cc208 mode 000000,100644..100644 --- a/dts/upstream/Bindings/sound/cirrus,cs4271.yaml +++ b/dts/upstream/Bindings/sound/cirrus,cs4271.yaml diff --cc dts/upstream/Bindings/sound/dlg,da7213.yaml index 00000000000,c2dede1e82f..c2dede1e82f mode 000000,100644..100644 --- a/dts/upstream/Bindings/sound/dlg,da7213.yaml +++ b/dts/upstream/Bindings/sound/dlg,da7213.yaml diff --cc dts/upstream/Bindings/sound/fsl,imx-audio-es8328.yaml index 00000000000,5eb6f5812cf..5eb6f5812cf mode 000000,100644..100644 --- a/dts/upstream/Bindings/sound/fsl,imx-audio-es8328.yaml +++ b/dts/upstream/Bindings/sound/fsl,imx-audio-es8328.yaml diff --cc dts/upstream/Bindings/sound/fsl,saif.yaml index 00000000000,0b5db6bb1b7..0b5db6bb1b7 mode 000000,100644..100644 --- a/dts/upstream/Bindings/sound/fsl,saif.yaml +++ b/dts/upstream/Bindings/sound/fsl,saif.yaml diff --cc dts/upstream/Bindings/sound/mediatek,mt8365-afe.yaml index 00000000000,45ad56d3723..45ad56d3723 mode 000000,100644..100644 --- a/dts/upstream/Bindings/sound/mediatek,mt8365-afe.yaml +++ b/dts/upstream/Bindings/sound/mediatek,mt8365-afe.yaml diff --cc dts/upstream/Bindings/sound/mediatek,mt8365-mt6357.yaml index 00000000000,ff9ebb63a05..ff9ebb63a05 mode 000000,100644..100644 --- a/dts/upstream/Bindings/sound/mediatek,mt8365-mt6357.yaml +++ b/dts/upstream/Bindings/sound/mediatek,mt8365-mt6357.yaml diff --cc dts/upstream/Bindings/sound/qcom,apq8016-sbc-sndcard.yaml index 00000000000,6ad45154903..6ad45154903 mode 000000,100644..100644 --- a/dts/upstream/Bindings/sound/qcom,apq8016-sbc-sndcard.yaml +++ b/dts/upstream/Bindings/sound/qcom,apq8016-sbc-sndcard.yaml diff --cc dts/upstream/Bindings/sound/ti,pcm512x.yaml index 00000000000,21ea9ff5a2b..21ea9ff5a2b mode 000000,100644..100644 --- a/dts/upstream/Bindings/sound/ti,pcm512x.yaml +++ b/dts/upstream/Bindings/sound/ti,pcm512x.yaml diff --cc dts/upstream/Bindings/sound/ti,tlv320dac3100.yaml index 00000000000,85e937e3496..85e937e3496 mode 000000,100644..100644 --- a/dts/upstream/Bindings/sound/ti,tlv320dac3100.yaml +++ b/dts/upstream/Bindings/sound/ti,tlv320dac3100.yaml diff --cc dts/upstream/Bindings/sound/ti,tpa6130a2.yaml index 00000000000,a42bf9bde69..a42bf9bde69 mode 000000,100644..100644 --- a/dts/upstream/Bindings/sound/ti,tpa6130a2.yaml +++ b/dts/upstream/Bindings/sound/ti,tpa6130a2.yaml diff --cc dts/upstream/Bindings/spi/cirrus,ep9301-spi.yaml index 00000000000,73980a27dc0..73980a27dc0 mode 000000,100644..100644 --- a/dts/upstream/Bindings/spi/cirrus,ep9301-spi.yaml +++ b/dts/upstream/Bindings/spi/cirrus,ep9301-spi.yaml diff --cc dts/upstream/Bindings/spi/nxp,sc18is.yaml index 00000000000,43753a94837..43753a94837 mode 000000,100644..100644 --- a/dts/upstream/Bindings/spi/nxp,sc18is.yaml +++ b/dts/upstream/Bindings/spi/nxp,sc18is.yaml diff --cc dts/upstream/Bindings/timer/brcm,bcm2835-system-timer.yaml index 00000000000,f5804b5b0e6..f5804b5b0e6 mode 000000,100644..100644 --- a/dts/upstream/Bindings/timer/brcm,bcm2835-system-timer.yaml +++ b/dts/upstream/Bindings/timer/brcm,bcm2835-system-timer.yaml diff --cc dts/upstream/Bindings/timer/fsl,ftm-timer.yaml index 00000000000,0e4a8ddc3de..0e4a8ddc3de mode 000000,100644..100644 --- a/dts/upstream/Bindings/timer/fsl,ftm-timer.yaml +++ b/dts/upstream/Bindings/timer/fsl,ftm-timer.yaml diff --cc dts/upstream/Bindings/timer/nxp,lpc3220-timer.yaml index 00000000000,3ae2eb0625d..3ae2eb0625d mode 000000,100644..100644 --- a/dts/upstream/Bindings/timer/nxp,lpc3220-timer.yaml +++ b/dts/upstream/Bindings/timer/nxp,lpc3220-timer.yaml diff --cc dts/upstream/Bindings/timer/ti,da830-timer.yaml index 00000000000,e9646f4e86c..e9646f4e86c mode 000000,100644..100644 --- a/dts/upstream/Bindings/timer/ti,da830-timer.yaml +++ b/dts/upstream/Bindings/timer/ti,da830-timer.yaml diff --cc dts/upstream/Bindings/usb/fsl,ls1028a.yaml index 00000000000,a44bdf39188..a44bdf39188 mode 000000,100644..100644 --- a/dts/upstream/Bindings/usb/fsl,ls1028a.yaml +++ b/dts/upstream/Bindings/usb/fsl,ls1028a.yaml diff --cc dts/upstream/Bindings/watchdog/cirrus,ep9301-wdt.yaml index 00000000000,5dbe891c70c..5dbe891c70c mode 000000,100644..100644 --- a/dts/upstream/Bindings/watchdog/cirrus,ep9301-wdt.yaml +++ b/dts/upstream/Bindings/watchdog/cirrus,ep9301-wdt.yaml diff --cc dts/upstream/Bindings/watchdog/nxp,lpc1850-wwdt.yaml index 00000000000,52878fdbe3a..52878fdbe3a mode 000000,100644..100644 --- a/dts/upstream/Bindings/watchdog/nxp,lpc1850-wwdt.yaml +++ b/dts/upstream/Bindings/watchdog/nxp,lpc1850-wwdt.yaml diff --cc dts/upstream/Bindings/watchdog/ti,davinci-wdt.yaml index 00000000000,3c78f60f5f4..3c78f60f5f4 mode 000000,100644..100644 --- a/dts/upstream/Bindings/watchdog/ti,davinci-wdt.yaml +++ b/dts/upstream/Bindings/watchdog/ti,davinci-wdt.yaml diff --cc dts/upstream/Bindings/watchdog/zii,rave-wdt.yaml index 00000000000,9dbaa941538..9dbaa941538 mode 000000,100644..100644 --- a/dts/upstream/Bindings/watchdog/zii,rave-wdt.yaml +++ b/dts/upstream/Bindings/watchdog/zii,rave-wdt.yaml diff --cc dts/upstream/Makefile index fb51acef7c6,00000000000..210830c688c mode 100644,000000..100644 --- a/dts/upstream/Makefile +++ b/dts/upstream/Makefile @@@ -1,180 -1,0 +1,194 @@@ + +DTC ?= dtc +CPP ?= cpp + +# Disable noisy checks by default +ifeq ($(findstring 1,$(DTC_VERBOSE)),) +DTC_FLAGS += -Wno-unit_address_vs_reg \ + -Wno-unit_address_format \ + -Wno-avoid_unnecessary_addr_size \ + -Wno-alias_paths \ + -Wno-graph_child_address \ + -Wno-simple_bus_reg \ + -Wno-unique_unit_address \ + -Wno-pci_device_reg +endif + +ifneq ($(findstring 2,$(DTC_VERBOSE)),) +DTC_FLAGS += -Wnode_name_chars_strict \ + -Wproperty_name_chars_strict +endif + +MAKEFLAGS += -rR --no-print-directory + +ALL_ARCHES := $(patsubst src/%,%,$(wildcard src/*)) + +PHONY += all +all: $(foreach i,$(ALL_ARCHES),all_$(i)) + +PHONY += clean +clean: $(foreach i,$(ALL_ARCHES),clean_$(i)) + +# Do not: +# o use make's built-in rules and variables +# (this increases performance and avoids hard-to-debug behaviour); +# o print "Entering directory ..."; +MAKEFLAGS += -rR --no-print-directory + +# To put more focus on warnings, be less verbose as default +# Use 'make V=1' to see the full commands + +ifeq ("$(origin V)", "command line") + KBUILD_VERBOSE = $(V) +endif +ifndef KBUILD_VERBOSE + KBUILD_VERBOSE = 0 +endif + +# Beautify output +# --------------------------------------------------------------------------- +# +# Normally, we echo the whole command before executing it. By making +# that echo $($(quiet)$(cmd)), we now have the possibility to set +# $(quiet) to choose other forms of output instead, e.g. +# +# quiet_cmd_cc_o_c = Compiling $(RELDIR)/$@ +# cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $< +# +# If $(quiet) is empty, the whole command will be printed. +# If it is set to "quiet_", only the short version will be printed. +# If it is set to "silent_", nothing will be printed at all, since +# the variable $(silent_cmd_cc_o_c) doesn't exist. +# +# A simple variant is to prefix commands with $(Q) - that's useful +# for commands that shall be hidden in non-verbose mode. +# +# $(Q)ln $@ :< +# +# If KBUILD_VERBOSE equals 0 then the above command will be hidden. +# If KBUILD_VERBOSE equals 1 then the above command is displayed. + +ifeq ($(KBUILD_VERBOSE),1) + quiet = + Q = +else + quiet=quiet_ + Q = @ +endif + +# If the user is running make -s (silent mode), suppress echoing of +# commands + +ifneq ($(filter 4.%,$(MAKE_VERSION)),) # make-4 +ifneq ($(filter %s ,$(firstword x$(MAKEFLAGS))),) + quiet=silent_ +endif +else # make-3.8x +ifneq ($(filter s% -s%,$(MAKEFLAGS)),) + quiet=silent_ +endif +endif + +export quiet Q KBUILD_VERBOSE + +all_%: + $(Q)$(MAKE) ARCH=$* all_arch + +clean_%: + $(Q)$(MAKE) ARCH=$* clean_arch + +ifeq ($(ARCH),) + +ALL_DTS := $(shell find src/* -name \*.dts) ++ALL_DTSO := $(shell find src/* -name \*.dtso) + +ALL_DTB := $(patsubst %.dts,%.dtb,$(ALL_DTS)) ++ALL_DTBO := $(patsubst %.dtso,%.dtbo,$(ALL_DTSO)) + - $(ALL_DTB): ARCH=$(word 2,$(subst /, ,$@)) - $(ALL_DTB): FORCE ++$(ALL_DTB) $(ALL_DTBO): ARCH=$(word 2,$(subst /, ,$@)) ++$(ALL_DTB) $(ALL_DTBO): FORCE + $(Q)$(MAKE) ARCH=$(ARCH) $@ + +else + +ARCH_DTS := $(shell find src/$(ARCH) -name \*.dts) ++ARCH_DTSO := $(shell find src/$(ARCH) -name \*.dtso) + +ARCH_DTB := $(patsubst %.dts,%.dtb,$(ARCH_DTS)) ++ARCH_DTBO := $(patsubst %.dtso,%.dtbo,$(ARCH_DTSO)) + +src := src/$(ARCH) +obj := src/$(ARCH) + +include scripts/Kbuild.include + - cmd_files := $(wildcard $(foreach f,$(ARCH_DTB),$(dir $(f)).$(notdir $(f)).cmd)) ++cmd_files := $(wildcard $(foreach f,$(ARCH_DTB) $(ARCH_DTBO),$(dir $(f)).$(notdir $(f)).cmd)) + +ifneq ($(cmd_files),) + include $(cmd_files) +endif + +quiet_cmd_clean = CLEAN $(obj) + cmd_clean = rm -f $(__clean-files) + +dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) + +dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \ + -Iinclude -I$(src) -Isrc -Itestcase-data \ + -undef -D__DTS__ + +quiet_cmd_dtc = DTC $@ +cmd_dtc = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ + $(DTC) -O dtb -o $@ -b 0 \ + -i $(src) $(DTC_FLAGS) \ + -d $(depfile).dtc.tmp $(dtc-tmp) ; \ + cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) + +$(obj)/%.dtb: $(src)/%.dts FORCE + $(call if_changed_dep,dtc) + ++quiet_cmd_dtco = DTCO $@ ++cmd_dtco = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ ++ $(DTC) -@ -O dtb -o $@ -b 0 \ ++ -i $(src) $(DTC_FLAGS) \ ++ -d $(depfile).dtc.tmp $(dtc-tmp) ; \ ++ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) ++ ++$(obj)/%.dtbo: $(src)/%.dtso FORCE ++ $(call if_changed_dep,dtco) ++ +PHONY += all_arch - all_arch: $(ARCH_DTB) ++all_arch: $(ARCH_DTB) $(ARCH_DTBO) + @: + +RCS_FIND_IGNORE := \( -name SCCS -o -name BitKeeper -o -name .svn -o -name CVS \ + -o -name .pc -o -name .hg -o -name .git \) -prune -o + +PHONY += clean_arch - clean_arch: __clean-files = $(ARCH_DTB) ++clean_arch: __clean-files = $(ARCH_DTB) $(ARCH_DTBO) +clean_arch: FORCE + $(call cmd,clean) + @find . $(RCS_FIND_IGNORE) \ + \( -name '.*.cmd' \ + -o -name '.*.d' \ + -o -name '.*.tmp' \ + \) -type f -print | xargs rm -f + +endif + +help: + @echo "Targets:" + @echo " all: Build all device tree binaries for all architectures" + @echo " clean: Clean all generated files" + @echo "" + @echo " all_: Build all device tree binaries for " + @echo " clean_: Clean all generated files for " + @echo "" + @echo " src//.dtb Build a single device tree binary" + @echo "" + @echo "Architectures: $(ALL_ARCHES)" + +PHONY += FORCE +FORCE: + +.PHONY: $(PHONY) diff --cc dts/upstream/include/dt-bindings/clock/at91.h index 3e3972a814c,00000000000..6ede88c3992 mode 100644,000000..100644 --- a/dts/upstream/include/dt-bindings/clock/at91.h +++ b/dts/upstream/include/dt-bindings/clock/at91.h @@@ -1,54 -1,0 +1,58 @@@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * This header provides constants for AT91 pmc status. + * + * The constants defined in this header are being used in dts. + */ + +#ifndef _DT_BINDINGS_CLK_AT91_H +#define _DT_BINDINGS_CLK_AT91_H + +#define PMC_TYPE_CORE 0 +#define PMC_TYPE_SYSTEM 1 +#define PMC_TYPE_PERIPHERAL 2 +#define PMC_TYPE_GCK 3 +#define PMC_TYPE_PROGRAMMABLE 4 + +#define PMC_SLOW 0 +#define PMC_MCK 1 +#define PMC_UTMI 2 +#define PMC_MAIN 3 +#define PMC_MCK2 4 +#define PMC_I2S0_MUX 5 +#define PMC_I2S1_MUX 6 +#define PMC_PLLACK 7 +#define PMC_PLLBCK 8 +#define PMC_AUDIOPLLCK 9 +#define PMC_AUDIOPINCK 10 + +/* SAMA7G5 */ +#define PMC_CPUPLL (PMC_MAIN + 1) +#define PMC_SYSPLL (PMC_MAIN + 2) +#define PMC_DDRPLL (PMC_MAIN + 3) +#define PMC_IMGPLL (PMC_MAIN + 4) +#define PMC_BAUDPLL (PMC_MAIN + 5) +#define PMC_AUDIOPMCPLL (PMC_MAIN + 6) +#define PMC_AUDIOIOPLL (PMC_MAIN + 7) +#define PMC_ETHPLL (PMC_MAIN + 8) +#define PMC_CPU (PMC_MAIN + 9) +#define PMC_MCK1 (PMC_MAIN + 10) + ++/* SAM9X7 */ ++#define PMC_PLLADIV2 (PMC_MAIN + 11) ++#define PMC_LVDSPLL (PMC_MAIN + 12) ++ +#ifndef AT91_PMC_MOSCS +#define AT91_PMC_MOSCS 0 /* MOSCS Flag */ +#define AT91_PMC_LOCKA 1 /* PLLA Lock */ +#define AT91_PMC_LOCKB 2 /* PLLB Lock */ +#define AT91_PMC_MCKRDY 3 /* Master Clock */ +#define AT91_PMC_LOCKU 6 /* UPLL Lock */ +#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */ +#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */ +#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */ +#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */ +#define AT91_PMC_GCKRDY 24 /* Generated Clocks */ +#endif + +#endif diff --cc dts/upstream/include/dt-bindings/clock/cirrus,ep9301-syscon.h index 00000000000,6bb8f532e7d..6bb8f532e7d mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/clock/cirrus,ep9301-syscon.h +++ b/dts/upstream/include/dt-bindings/clock/cirrus,ep9301-syscon.h diff --cc dts/upstream/include/dt-bindings/clock/qcom,sm4450-camcc.h index 00000000000,bf077951bf1..bf077951bf1 mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/clock/qcom,sm4450-camcc.h +++ b/dts/upstream/include/dt-bindings/clock/qcom,sm4450-camcc.h diff --cc dts/upstream/include/dt-bindings/clock/qcom,sm4450-dispcc.h index 00000000000,ca6f2ef9015..ca6f2ef9015 mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/clock/qcom,sm4450-dispcc.h +++ b/dts/upstream/include/dt-bindings/clock/qcom,sm4450-dispcc.h diff --cc dts/upstream/include/dt-bindings/clock/qcom,sm4450-gpucc.h index 00000000000,304f83e5f64..304f83e5f64 mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/clock/qcom,sm4450-gpucc.h +++ b/dts/upstream/include/dt-bindings/clock/qcom,sm4450-gpucc.h diff --cc dts/upstream/include/dt-bindings/clock/qcom,sm8150-camcc.h index 00000000000,5444035efa9..5444035efa9 mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/clock/qcom,sm8150-camcc.h +++ b/dts/upstream/include/dt-bindings/clock/qcom,sm8150-camcc.h diff --cc dts/upstream/include/dt-bindings/clock/renesas,r9a09g057-cpg.h index 00000000000,541e6d719bd..541e6d719bd mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/clock/renesas,r9a09g057-cpg.h +++ b/dts/upstream/include/dt-bindings/clock/renesas,r9a09g057-cpg.h diff --cc dts/upstream/include/dt-bindings/clock/rk3036-cru.h index a96a9870ad5,00000000000..99cc617e1e5 mode 100644,000000..100644 --- a/dts/upstream/include/dt-bindings/clock/rk3036-cru.h +++ b/dts/upstream/include/dt-bindings/clock/rk3036-cru.h @@@ -1,187 -1,0 +1,185 @@@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_GPLL 3 +#define ARMCLK 4 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI 65 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_NANDC 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_OTGPHY0 93 +#define SCLK_LCDC 100 +#define SCLK_HDMI 109 +#define SCLK_HEVC 111 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_VIDEO 125 +#define SCLK_MAC 151 +#define SCLK_MACREF 152 +#define SCLK_MACPLL 153 +#define SCLK_SFC 160 + +/* aclk gates */ +#define ACLK_DMAC2 194 +#define ACLK_LCDC 197 +#define ACLK_VIO 203 +#define ACLK_VCODEC 208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_SPI 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_HDMI 360 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_WDT 368 +#define PCLK_ACODEC 369 + +/* hclk gates */ +#define HCLK_OTG0 449 +#define HCLK_OTG1 450 +#define HCLK_NANDC 453 +#define HCLK_SFC 454 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_MAC 460 +#define HCLK_I2S 462 +#define HCLK_LCDC 465 +#define HCLK_ROM 467 +#define HCLK_VIO_BUS 472 +#define HCLK_VCODEC 476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + - #define CLK_NR_CLKS (HCLK_PERI + 1) - +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE0_DBG 4 +#define SRST_CORE1_DBG 5 +#define SRST_CORE0_POR 8 +#define SRST_CORE1_POR 9 +#define SRST_L2C 12 +#define SRST_TOPDBG 13 +#define SRST_STRC_SYS_A 14 +#define SRST_PD_CORE_NIU 15 + +#define SRST_TIMER2 16 +#define SRST_CPUSYS_H 17 +#define SRST_AHB2APB_H 19 +#define SRST_TIMER3 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_PERI_NIU 23 +#define SRST_I2S 24 +#define SRST_DDR_PLL 25 +#define SRST_GPU_DLL 26 +#define SRST_TIMER0 27 +#define SRST_TIMER1 28 +#define SRST_CORE_DLL 29 +#define SRST_EFUSE_P 30 +#define SRST_ACODEC_P 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_SFC 47 + +#define SRST_PWM0 48 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_GRF 55 +#define SRST_PERIPHSYS_A 57 +#define SRST_PERIPHSYS_H 58 +#define SRST_PERIPHSYS_P 59 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA2 64 +#define SRST_MAC 66 +#define SRST_NANDC 68 +#define SRST_USBOTG0 69 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_OTGC1 74 +#define SRST_DDRMSCH 79 + +#define SRST_MMC0 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI0 84 +#define SRST_WDT 86 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 + +#define SRST_HDMI_P 96 +#define SRST_VIO_BUS_H 99 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_USBPOR 105 + +#define SRST_VCODEC_A 112 +#define SRST_VCODEC_H 113 +#define SRST_VIO1_A 114 +#define SRST_HEVC 115 +#define SRST_VCODEC_NIU_A 116 +#define SRST_LCDC1_A 117 +#define SRST_LCDC1_H 118 +#define SRST_LCDC1_D 119 +#define SRST_GPU 120 +#define SRST_GPU_NIU_A 122 + +#define SRST_DBG_P 131 + +#endif diff --cc dts/upstream/include/dt-bindings/clock/rk3228-cru.h index de550ea56ee,00000000000..138b6ce514d mode 100644,000000..100644 --- a/dts/upstream/include/dt-bindings/clock/rk3228-cru.h +++ b/dts/upstream/include/dt-bindings/clock/rk3228-cru.h @@@ -1,287 -1,0 +1,285 @@@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Jeffy Chen + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define ARMCLK 5 + +/* sclk gates (special clocks) */ +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_TSADC 72 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S0 80 +#define SCLK_I2S1 81 +#define SCLK_I2S2 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_SDIO_SRC 120 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_VOP 122 +#define SCLK_HDMI_HDCP 123 +#define SCLK_MAC_SRC 124 +#define SCLK_MAC_EXTCLK 125 +#define SCLK_MAC 126 +#define SCLK_MAC_REFOUT 127 +#define SCLK_MAC_REF 128 +#define SCLK_MAC_RX 129 +#define SCLK_MAC_TX 130 +#define SCLK_MAC_PHY 131 +#define SCLK_MAC_OUT 132 +#define SCLK_VDEC_CABAC 133 +#define SCLK_VDEC_CORE 134 +#define SCLK_RGA 135 +#define SCLK_HDCP 136 +#define SCLK_HDMI_CEC 137 +#define SCLK_CRYPTO 138 +#define SCLK_TSP 139 +#define SCLK_HSADC 140 +#define SCLK_WIFI 141 +#define SCLK_OTGPHY0 142 +#define SCLK_OTGPHY1 143 +#define SCLK_HDMI_PHY 144 + +/* dclk gates */ +#define DCLK_VOP 190 +#define DCLK_HDMI_PHY 191 + +/* aclk gates */ +#define ACLK_DMAC 194 +#define ACLK_CPU 195 +#define ACLK_VPU_PRE 196 +#define ACLK_RKVDEC_PRE 197 +#define ACLK_RGA_PRE 198 +#define ACLK_IEP_PRE 199 +#define ACLK_HDCP_PRE 200 +#define ACLK_VOP_PRE 201 +#define ACLK_VPU 202 +#define ACLK_RKVDEC 203 +#define ACLK_IEP 204 +#define ACLK_RGA 205 +#define ACLK_HDCP 206 +#define ACLK_PERI 210 +#define ACLK_VOP 211 +#define ACLK_GMAC 212 +#define ACLK_GPU 213 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_VIO_H2P 324 +#define PCLK_HDCP 325 +#define PCLK_EFUSE_1024 326 +#define PCLK_EFUSE_256 327 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_SPI0 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_TSADC 344 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_CPU 354 +#define PCLK_PERI 363 +#define PCLK_HDMI_CTRL 364 +#define PCLK_HDMI_PHY 365 +#define PCLK_GMAC 367 + +/* hclk gates */ +#define HCLK_I2S0_8CH 442 +#define HCLK_I2S1_8CH 443 +#define HCLK_I2S2_2CH 444 +#define HCLK_SPDIF_8CH 445 +#define HCLK_VOP 452 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_CPU 460 +#define HCLK_VPU_PRE 461 +#define HCLK_RKVDEC_PRE 462 +#define HCLK_VIO_PRE 463 +#define HCLK_VPU 464 +#define HCLK_RKVDEC 465 +#define HCLK_VIO 466 +#define HCLK_RGA 467 +#define HCLK_IEP 468 +#define HCLK_VIO_H2P 469 +#define HCLK_HDCP_MMU 470 +#define HCLK_HOST0 471 +#define HCLK_HOST1 472 +#define HCLK_HOST2 473 +#define HCLK_OTG 474 +#define HCLK_TSP 475 +#define HCLK_M_CRYPTO 476 +#define HCLK_S_CRYPTO 477 +#define HCLK_PERI 478 + - #define CLK_NR_CLKS (HCLK_PERI + 1) - +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_ACLK_CORE 13 +#define SRST_NOC 14 +#define SRST_L2C 15 + +#define SRST_CPUSYS_H 18 +#define SRST_BUSSYS_H 19 +#define SRST_SPDIF 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_OTG_ADP 23 +#define SRST_I2S0 24 +#define SRST_I2S1 25 +#define SRST_I2S2 26 +#define SRST_ACODEC_P 27 +#define SRST_DFIMON 28 +#define SRST_MSCH 29 +#define SRST_EFUSE1024 30 +#define SRST_EFUSE256 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_PERIPH_NOC_A 36 +#define SRST_PERIPH_NOC_BUS_H 37 +#define SRST_PERIPH_NOC_P 38 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_PHYNOC 42 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_I2C3 46 + +#define SRST_PWM 48 +#define SRST_A53_GIC 49 +#define SRST_DAP 51 +#define SRST_DAP_NOC 52 +#define SRST_CRYPTO 53 +#define SRST_SGRF 54 +#define SRST_GRF 55 +#define SRST_GMAC 56 +#define SRST_PERIPH_NOC_H 58 +#define SRST_MACPHY 63 + +#define SRST_DMA 64 +#define SRST_NANDC 68 +#define SRST_USBOTG 69 +#define SRST_OTGC 70 +#define SRST_USBHOST0 71 +#define SRST_HOST_CTRL0 72 +#define SRST_USBHOST1 73 +#define SRST_HOST_CTRL1 74 +#define SRST_USBHOST2 75 +#define SRST_HOST_CTRL2 76 +#define SRST_USBPOR0 77 +#define SRST_USBPOR1 78 +#define SRST_DDRMSCH 79 + +#define SRST_SMART_CARD 80 +#define SRST_SDMMC 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI 84 +#define SRST_TSP_H 85 +#define SRST_TSP 86 +#define SRST_TSADC 87 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 +#define SRST_HOST0_ECHI 92 +#define SRST_HOST1_ECHI 93 +#define SRST_HOST2_ECHI 94 +#define SRST_VOP_NOC_A 95 + +#define SRST_HDMI_P 96 +#define SRST_VIO_ARBI_H 97 +#define SRST_IEP_NOC_A 98 +#define SRST_VIO_NOC_H 99 +#define SRST_VOP_A 100 +#define SRST_VOP_H 101 +#define SRST_VOP_D 102 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_UTMI2 105 +#define SRST_UTMI3 106 +#define SRST_RGA 107 +#define SRST_RGA_NOC_A 108 +#define SRST_RGA_A 109 +#define SRST_RGA_H 110 +#define SRST_HDCP_A 111 + +#define SRST_VPU_A 112 +#define SRST_VPU_H 113 +#define SRST_VPU_NOC_A 116 +#define SRST_VPU_NOC_H 117 +#define SRST_RKVDEC_A 118 +#define SRST_RKVDEC_NOC_A 119 +#define SRST_RKVDEC_H 120 +#define SRST_RKVDEC_NOC_H 121 +#define SRST_RKVDEC_CORE 122 +#define SRST_RKVDEC_CABAC 123 +#define SRST_IEP_A 124 +#define SRST_IEP_H 125 +#define SRST_GPU_A 126 +#define SRST_GPU_NOC_A 127 + +#define SRST_CORE_DBG 128 +#define SRST_DBG_P 129 +#define SRST_TIMER0 130 +#define SRST_TIMER1 131 +#define SRST_TIMER2 132 +#define SRST_TIMER3 133 +#define SRST_TIMER4 134 +#define SRST_TIMER5 135 +#define SRST_VIO_H2P 136 +#define SRST_HDMIPHY 139 +#define SRST_VDAC 140 +#define SRST_TIMER_6CH_P 141 + +#endif diff --cc dts/upstream/include/dt-bindings/clock/rk3288-cru.h index 33819acbfc5,00000000000..c6034b01b05 mode 100644,000000..100644 --- a/dts/upstream/include/dt-bindings/clock/rk3288-cru.h +++ b/dts/upstream/include/dt-bindings/clock/rk3288-cru.h @@@ -1,380 -1,0 +1,378 @@@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_NPLL 5 +#define ARMCLK 6 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI0 65 +#define SCLK_SPI1 66 +#define SCLK_SPI2 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO0 69 +#define SCLK_SDIO1 70 +#define SCLK_EMMC 71 +#define SCLK_TSADC 72 +#define SCLK_SARADC 73 +#define SCLK_PS2C 74 +#define SCLK_NANDC0 75 +#define SCLK_NANDC1 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_UART3 80 +#define SCLK_UART4 81 +#define SCLK_I2S0 82 +#define SCLK_SPDIF 83 +#define SCLK_SPDIF8CH 84 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 +#define SCLK_TIMER6 91 +#define SCLK_HSADC 92 +#define SCLK_OTGPHY0 93 +#define SCLK_OTGPHY1 94 +#define SCLK_OTGPHY2 95 +#define SCLK_OTG_ADP 96 +#define SCLK_HSICPHY480M 97 +#define SCLK_HSICPHY12M 98 +#define SCLK_MACREF 99 +#define SCLK_LCDC_PWM0 100 +#define SCLK_LCDC_PWM1 101 +#define SCLK_MAC_RX 102 +#define SCLK_MAC_TX 103 +#define SCLK_EDP_24M 104 +#define SCLK_EDP 105 +#define SCLK_RGA 106 +#define SCLK_ISP 107 +#define SCLK_ISP_JPE 108 +#define SCLK_HDMI_HDCP 109 +#define SCLK_HDMI_CEC 110 +#define SCLK_HEVC_CABAC 111 +#define SCLK_HEVC_CORE 112 +#define SCLK_I2S0_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO0_DRV 115 +#define SCLK_SDIO1_DRV 116 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO0_SAMPLE 119 +#define SCLK_SDIO1_SAMPLE 120 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_USBPHY480M_SRC 122 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_CRYPTO 125 +#define SCLK_MIPIDSI_24M 126 +#define SCLK_VIP_OUT 127 + +#define SCLK_MAC 151 +#define SCLK_MACREF_OUT 152 + +#define DCLK_VOP0 190 +#define DCLK_VOP1 191 + +/* aclk gates */ +#define ACLK_GPU 192 +#define ACLK_DMAC1 193 +#define ACLK_DMAC2 194 +#define ACLK_MMU 195 +#define ACLK_GMAC 196 +#define ACLK_VOP0 197 +#define ACLK_VOP1 198 +#define ACLK_CRYPTO 199 +#define ACLK_RGA 200 +#define ACLK_RGA_NIU 201 +#define ACLK_IEP 202 +#define ACLK_VIO0_NIU 203 +#define ACLK_VIP 204 +#define ACLK_ISP 205 +#define ACLK_VIO1_NIU 206 +#define ACLK_HEVC 207 +#define ACLK_VCODEC 208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_GPIO4 324 +#define PCLK_GPIO5 325 +#define PCLK_GPIO6 326 +#define PCLK_GPIO7 327 +#define PCLK_GPIO8 328 +#define PCLK_GRF 329 +#define PCLK_SGRF 330 +#define PCLK_PMU 331 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_I2C4 336 +#define PCLK_I2C5 337 +#define PCLK_SPI0 338 +#define PCLK_SPI1 339 +#define PCLK_SPI2 340 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_UART3 344 +#define PCLK_UART4 345 +#define PCLK_TSADC 346 +#define PCLK_SARADC 347 +#define PCLK_SIM 348 +#define PCLK_GMAC 349 +#define PCLK_PWM 350 +#define PCLK_RKPWM 351 +#define PCLK_PS2C 352 +#define PCLK_TIMER 353 +#define PCLK_TZPC 354 +#define PCLK_EDP_CTRL 355 +#define PCLK_MIPI_DSI0 356 +#define PCLK_MIPI_DSI1 357 +#define PCLK_MIPI_CSI 358 +#define PCLK_LVDS_PHY 359 +#define PCLK_HDMI_CTRL 360 +#define PCLK_VIO2_H2P 361 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL0 364 +#define PCLK_PUBL0 365 +#define PCLK_DDRUPCTL1 366 +#define PCLK_PUBL1 367 +#define PCLK_WDT 368 +#define PCLK_EFUSE256 369 +#define PCLK_EFUSE1024 370 +#define PCLK_ISP_IN 371 + +/* hclk gates */ +#define HCLK_GPS 448 +#define HCLK_OTG0 449 +#define HCLK_USBHOST0 450 +#define HCLK_USBHOST1 451 +#define HCLK_HSIC 452 +#define HCLK_NANDC0 453 +#define HCLK_NANDC1 454 +#define HCLK_TSP 455 +#define HCLK_SDMMC 456 +#define HCLK_SDIO0 457 +#define HCLK_SDIO1 458 +#define HCLK_EMMC 459 +#define HCLK_HSADC 460 +#define HCLK_CRYPTO 461 +#define HCLK_I2S0 462 +#define HCLK_SPDIF 463 +#define HCLK_SPDIF8CH 464 +#define HCLK_VOP0 465 +#define HCLK_VOP1 466 +#define HCLK_ROM 467 +#define HCLK_IEP 468 +#define HCLK_ISP 469 +#define HCLK_RGA 470 +#define HCLK_VIO_AHB_ARBI 471 +#define HCLK_VIO_NIU 472 +#define HCLK_VIP 473 +#define HCLK_VIO2_H2P 474 +#define HCLK_HEVC 475 +#define HCLK_VCODEC 476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + - #define CLK_NR_CLKS (HCLK_PERI + 1) - +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE2 2 +#define SRST_CORE3 3 +#define SRST_CORE0_PO 4 +#define SRST_CORE1_PO 5 +#define SRST_CORE2_PO 6 +#define SRST_CORE3_PO 7 +#define SRST_PDCORE_STRSYS 8 +#define SRST_PDBUS_STRSYS 9 +#define SRST_L2C 10 +#define SRST_TOPDBG 11 +#define SRST_CORE0_DBG 12 +#define SRST_CORE1_DBG 13 +#define SRST_CORE2_DBG 14 +#define SRST_CORE3_DBG 15 + +#define SRST_PDBUG_AHB_ARBITOR 16 +#define SRST_EFUSE256 17 +#define SRST_DMAC1 18 +#define SRST_INTMEM 19 +#define SRST_ROM 20 +#define SRST_SPDIF8CH 21 +#define SRST_TIMER 22 +#define SRST_I2S0 23 +#define SRST_SPDIF 24 +#define SRST_TIMER0 25 +#define SRST_TIMER1 26 +#define SRST_TIMER2 27 +#define SRST_TIMER3 28 +#define SRST_TIMER4 29 +#define SRST_TIMER5 30 +#define SRST_EFUSE 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_GPIO4 36 +#define SRST_GPIO5 37 +#define SRST_GPIO6 38 +#define SRST_GPIO7 39 +#define SRST_GPIO8 40 +#define SRST_I2C0 42 +#define SRST_I2C1 43 +#define SRST_I2C2 44 +#define SRST_I2C3 45 +#define SRST_I2C4 46 +#define SRST_I2C5 47 + +#define SRST_DWPWM 48 +#define SRST_MMC_PERI 49 +#define SRST_PERIPH_MMU 50 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_TPIU 53 +#define SRST_PMU_APB 54 +#define SRST_GRF 55 +#define SRST_PMU 56 +#define SRST_PERIPH_AXI 57 +#define SRST_PERIPH_AHB 58 +#define SRST_PERIPH_APB 59 +#define SRST_PERIPH_NIU 60 +#define SRST_PDPERI_AHB_ARBI 61 +#define SRST_EMEM 62 +#define SRST_USB_PERI 63 + +#define SRST_DMAC2 64 +#define SRST_MAC 66 +#define SRST_GPS 67 +#define SRST_RKPWM 69 +#define SRST_CCP 71 +#define SRST_USBHOST0 72 +#define SRST_HSIC 73 +#define SRST_HSIC_AUX 74 +#define SRST_HSIC_PHY 75 +#define SRST_HSADC 76 +#define SRST_NANDC0 77 +#define SRST_NANDC1 78 + +#define SRST_TZPC 80 +#define SRST_SPI0 83 +#define SRST_SPI1 84 +#define SRST_SPI2 85 +#define SRST_SARADC 87 +#define SRST_PDALIVE_NIU 88 +#define SRST_PDPMU_INTMEM 89 +#define SRST_PDPMU_NIU 90 +#define SRST_SGRF 91 + +#define SRST_VIO_ARBI 96 +#define SRST_RGA_NIU 97 +#define SRST_VIO0_NIU_AXI 98 +#define SRST_VIO_NIU_AHB 99 +#define SRST_LCDC0_AXI 100 +#define SRST_LCDC0_AHB 101 +#define SRST_LCDC0_DCLK 102 +#define SRST_VIO1_NIU_AXI 103 +#define SRST_VIP 104 +#define SRST_RGA_CORE 105 +#define SRST_IEP_AXI 106 +#define SRST_IEP_AHB 107 +#define SRST_RGA_AXI 108 +#define SRST_RGA_AHB 109 +#define SRST_ISP 110 +#define SRST_EDP 111 + +#define SRST_VCODEC_AXI 112 +#define SRST_VCODEC_AHB 113 +#define SRST_VIO_H2P 114 +#define SRST_MIPIDSI0 115 +#define SRST_MIPIDSI1 116 +#define SRST_MIPICSI 117 +#define SRST_LVDS_PHY 118 +#define SRST_LVDS_CON 119 +#define SRST_GPU 120 +#define SRST_HDMI 121 +#define SRST_CORE_PVTM 124 +#define SRST_GPU_PVTM 125 + +#define SRST_MMC0 128 +#define SRST_SDIO0 129 +#define SRST_SDIO1 130 +#define SRST_EMMC 131 +#define SRST_USBOTG_AHB 132 +#define SRST_USBOTG_PHY 133 +#define SRST_USBOTG_CON 134 +#define SRST_USBHOST0_AHB 135 +#define SRST_USBHOST0_PHY 136 +#define SRST_USBHOST0_CON 137 +#define SRST_USBHOST1_AHB 138 +#define SRST_USBHOST1_PHY 139 +#define SRST_USBHOST1_CON 140 +#define SRST_USB_ADP 141 +#define SRST_ACC_EFUSE 142 + +#define SRST_CORESIGHT 144 +#define SRST_PD_CORE_AHB_NOC 145 +#define SRST_PD_CORE_APB_NOC 146 +#define SRST_PD_CORE_MP_AXI 147 +#define SRST_GIC 148 +#define SRST_LCDC_PWM0 149 +#define SRST_LCDC_PWM1 150 +#define SRST_VIO0_H2P_BRG 151 +#define SRST_VIO1_H2P_BRG 152 +#define SRST_RGA_H2P_BRG 153 +#define SRST_HEVC 154 +#define SRST_TSADC 159 + +#define SRST_DDRPHY0 160 +#define SRST_DDRPHY0_APB 161 +#define SRST_DDRCTRL0 162 +#define SRST_DDRCTRL0_APB 163 +#define SRST_DDRPHY0_CTRL 164 +#define SRST_DDRPHY1 165 +#define SRST_DDRPHY1_APB 166 +#define SRST_DDRCTRL1 167 +#define SRST_DDRCTRL1_APB 168 +#define SRST_DDRPHY1_CTRL 169 +#define SRST_DDRMSCH0 170 +#define SRST_DDRMSCH1 171 +#define SRST_CRYPTO 174 +#define SRST_C2C_HOST 175 + +#define SRST_LCDC1_AXI 176 +#define SRST_LCDC1_AHB 177 +#define SRST_LCDC1_DCLK 178 +#define SRST_UART0 179 +#define SRST_UART1 180 +#define SRST_UART2 181 +#define SRST_UART3 182 +#define SRST_UART4 183 +#define SRST_SIMC 186 +#define SRST_PS2C 187 +#define SRST_TSP 188 +#define SRST_TSP_CLKIN0 189 +#define SRST_TSP_CLKIN1 190 +#define SRST_TSP_27M 191 + +#endif diff --cc dts/upstream/include/dt-bindings/clock/rk3368-cru.h index 83c72a163fd,00000000000..ebae3cbf819 mode 100644,000000..100644 --- a/dts/upstream/include/dt-bindings/clock/rk3368-cru.h +++ b/dts/upstream/include/dt-bindings/clock/rk3368-cru.h @@@ -1,384 -1,0 +1,382 @@@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2015 Heiko Stuebner + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H + +/* core clocks */ +#define PLL_APLLB 1 +#define PLL_APLLL 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define ARMCLKB 7 +#define ARMCLKL 8 + +/* sclk gates (special clocks) */ +#define SCLK_GPU_CORE 64 +#define SCLK_SPI0 65 +#define SCLK_SPI1 66 +#define SCLK_SPI2 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO0 69 +#define SCLK_EMMC 71 +#define SCLK_TSADC 72 +#define SCLK_SARADC 73 +#define SCLK_NANDC0 75 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_UART3 80 +#define SCLK_UART4 81 +#define SCLK_I2S_8CH 82 +#define SCLK_SPDIF_8CH 83 +#define SCLK_I2S_2CH 84 +#define SCLK_TIMER00 85 +#define SCLK_TIMER01 86 +#define SCLK_TIMER02 87 +#define SCLK_TIMER03 88 +#define SCLK_TIMER04 89 +#define SCLK_TIMER05 90 +#define SCLK_OTGPHY0 93 +#define SCLK_OTG_ADP 96 +#define SCLK_HSICPHY480M 97 +#define SCLK_HSICPHY12M 98 +#define SCLK_MACREF 99 +#define SCLK_VOP0_PWM 100 +#define SCLK_MAC_RX 102 +#define SCLK_MAC_TX 103 +#define SCLK_EDP_24M 104 +#define SCLK_EDP 105 +#define SCLK_RGA 106 +#define SCLK_ISP 107 +#define SCLK_HDCP 108 +#define SCLK_HDMI_HDCP 109 +#define SCLK_HDMI_CEC 110 +#define SCLK_HEVC_CABAC 111 +#define SCLK_HEVC_CORE 112 +#define SCLK_I2S_8CH_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO0_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO0_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_USBPHY480M 122 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_PMU 125 +#define SCLK_SFC 126 +#define SCLK_MAC 127 +#define SCLK_MACREF_OUT 128 +#define SCLK_TIMER10 133 +#define SCLK_TIMER11 134 +#define SCLK_TIMER12 135 +#define SCLK_TIMER13 136 +#define SCLK_TIMER14 137 +#define SCLK_TIMER15 138 +#define SCLK_VIP_OUT 139 + +#define DCLK_VOP 190 +#define MCLK_CRYPTO 191 + +/* aclk gates */ +#define ACLK_GPU_MEM 192 +#define ACLK_GPU_CFG 193 +#define ACLK_DMAC_BUS 194 +#define ACLK_DMAC_PERI 195 +#define ACLK_PERI_MMU 196 +#define ACLK_GMAC 197 +#define ACLK_VOP 198 +#define ACLK_VOP_IEP 199 +#define ACLK_RGA 200 +#define ACLK_HDCP 201 +#define ACLK_IEP 202 +#define ACLK_VIO0_NOC 203 +#define ACLK_VIP 204 +#define ACLK_ISP 205 +#define ACLK_VIO1_NOC 206 +#define ACLK_VIDEO 208 +#define ACLK_BUS 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_PMUGRF 324 +#define PCLK_MAILBOX 325 +#define PCLK_GRF 329 +#define PCLK_SGRF 330 +#define PCLK_PMU 331 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_I2C4 336 +#define PCLK_I2C5 337 +#define PCLK_SPI0 338 +#define PCLK_SPI1 339 +#define PCLK_SPI2 340 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_UART3 344 +#define PCLK_UART4 345 +#define PCLK_TSADC 346 +#define PCLK_SARADC 347 +#define PCLK_SIM 348 +#define PCLK_GMAC 349 +#define PCLK_PWM0 350 +#define PCLK_PWM1 351 +#define PCLK_TIMER0 353 +#define PCLK_TIMER1 354 +#define PCLK_EDP_CTRL 355 +#define PCLK_MIPI_DSI0 356 +#define PCLK_MIPI_CSI 358 +#define PCLK_HDCP 359 +#define PCLK_HDMI_CTRL 360 +#define PCLK_VIO_H2P 361 +#define PCLK_BUS 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_DDRPHY 365 +#define PCLK_ISP 366 +#define PCLK_VIP 367 +#define PCLK_WDT 368 +#define PCLK_EFUSE256 369 +#define PCLK_DPHYRX 370 +#define PCLK_DPHYTX0 371 + +/* hclk gates */ +#define HCLK_SFC 448 +#define HCLK_OTG0 449 +#define HCLK_HOST0 450 +#define HCLK_HOST1 451 +#define HCLK_HSIC 452 +#define HCLK_NANDC0 453 +#define HCLK_TSP 455 +#define HCLK_SDMMC 456 +#define HCLK_SDIO0 457 +#define HCLK_EMMC 459 +#define HCLK_HSADC 460 +#define HCLK_CRYPTO 461 +#define HCLK_I2S_2CH 462 +#define HCLK_I2S_8CH 463 +#define HCLK_SPDIF 464 +#define HCLK_VOP 465 +#define HCLK_ROM 467 +#define HCLK_IEP 468 +#define HCLK_ISP 469 +#define HCLK_RGA 470 +#define HCLK_VIO_AHB_ARBI 471 +#define HCLK_VIO_NOC 472 +#define HCLK_VIP 473 +#define HCLK_VIO_H2P 474 +#define HCLK_VIO_HDCPMMU 475 +#define HCLK_VIDEO 476 +#define HCLK_BUS 477 +#define HCLK_PERI 478 + - #define CLK_NR_CLKS (HCLK_PERI + 1) - +/* soft-reset indices */ +#define SRST_CORE_B0 0 +#define SRST_CORE_B1 1 +#define SRST_CORE_B2 2 +#define SRST_CORE_B3 3 +#define SRST_CORE_B0_PO 4 +#define SRST_CORE_B1_PO 5 +#define SRST_CORE_B2_PO 6 +#define SRST_CORE_B3_PO 7 +#define SRST_L2_B 8 +#define SRST_ADB_B 9 +#define SRST_PD_CORE_B_NIU 10 +#define SRST_PDBUS_STRSYS 11 +#define SRST_SOCDBG_B 14 +#define SRST_CORE_B_DBG 15 + +#define SRST_DMAC1 18 +#define SRST_INTMEM 19 +#define SRST_ROM 20 +#define SRST_SPDIF8CH 21 +#define SRST_I2S8CH 23 +#define SRST_MAILBOX 24 +#define SRST_I2S2CH 25 +#define SRST_EFUSE_256 26 +#define SRST_MCU_SYS 28 +#define SRST_MCU_PO 29 +#define SRST_MCU_NOC 30 +#define SRST_EFUSE 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_GPIO4 36 +#define SRST_PMUGRF 41 +#define SRST_I2C0 42 +#define SRST_I2C1 43 +#define SRST_I2C2 44 +#define SRST_I2C3 45 +#define SRST_I2C4 46 +#define SRST_I2C5 47 + +#define SRST_DWPWM 48 +#define SRST_MMC_PERI 49 +#define SRST_PERIPH_MMU 50 +#define SRST_GRF 55 +#define SRST_PMU 56 +#define SRST_PERIPH_AXI 57 +#define SRST_PERIPH_AHB 58 +#define SRST_PERIPH_APB 59 +#define SRST_PERIPH_NIU 60 +#define SRST_PDPERI_AHB_ARBI 61 +#define SRST_EMEM 62 +#define SRST_USB_PERI 63 + +#define SRST_DMAC2 64 +#define SRST_MAC 66 +#define SRST_GPS 67 +#define SRST_RKPWM 69 +#define SRST_USBHOST0 72 +#define SRST_HSIC 73 +#define SRST_HSIC_AUX 74 +#define SRST_HSIC_PHY 75 +#define SRST_HSADC 76 +#define SRST_NANDC0 77 +#define SRST_SFC 79 + +#define SRST_SPI0 83 +#define SRST_SPI1 84 +#define SRST_SPI2 85 +#define SRST_SARADC 87 +#define SRST_PDALIVE_NIU 88 +#define SRST_PDPMU_INTMEM 89 +#define SRST_PDPMU_NIU 90 +#define SRST_SGRF 91 + +#define SRST_VIO_ARBI 96 +#define SRST_RGA_NIU 97 +#define SRST_VIO0_NIU_AXI 98 +#define SRST_VIO_NIU_AHB 99 +#define SRST_LCDC0_AXI 100 +#define SRST_LCDC0_AHB 101 +#define SRST_LCDC0_DCLK 102 +#define SRST_VIP 104 +#define SRST_RGA_CORE 105 +#define SRST_IEP_AXI 106 +#define SRST_IEP_AHB 107 +#define SRST_RGA_AXI 108 +#define SRST_RGA_AHB 109 +#define SRST_ISP 110 +#define SRST_EDP_24M 111 + +#define SRST_VIDEO_AXI 112 +#define SRST_VIDEO_AHB 113 +#define SRST_MIPIDPHYTX 114 +#define SRST_MIPIDSI0 115 +#define SRST_MIPIDPHYRX 116 +#define SRST_MIPICSI 117 +#define SRST_GPU 120 +#define SRST_HDMI 121 +#define SRST_EDP 122 +#define SRST_PMU_PVTM 123 +#define SRST_CORE_PVTM 124 +#define SRST_GPU_PVTM 125 +#define SRST_GPU_SYS 126 +#define SRST_GPU_MEM_NIU 127 + +#define SRST_MMC0 128 +#define SRST_SDIO0 129 +#define SRST_EMMC 131 +#define SRST_USBOTG_AHB 132 +#define SRST_USBOTG_PHY 133 +#define SRST_USBOTG_CON 134 +#define SRST_USBHOST0_AHB 135 +#define SRST_USBHOST0_PHY 136 +#define SRST_USBHOST0_CON 137 +#define SRST_USBOTG_UTMI 138 +#define SRST_USBHOST1_UTMI 139 +#define SRST_USB_ADP 141 + +#define SRST_CORESIGHT 144 +#define SRST_PD_CORE_AHB_NOC 145 +#define SRST_PD_CORE_APB_NOC 146 +#define SRST_GIC 148 +#define SRST_LCDC_PWM0 149 +#define SRST_RGA_H2P_BRG 153 +#define SRST_VIDEO 154 +#define SRST_GPU_CFG_NIU 157 +#define SRST_TSADC 159 + +#define SRST_DDRPHY0 160 +#define SRST_DDRPHY0_APB 161 +#define SRST_DDRCTRL0 162 +#define SRST_DDRCTRL0_APB 163 +#define SRST_VIDEO_NIU 165 +#define SRST_VIDEO_NIU_AHB 167 +#define SRST_DDRMSCH0 170 +#define SRST_PDBUS_AHB 173 +#define SRST_CRYPTO 174 + +#define SRST_UART0 179 +#define SRST_UART1 180 +#define SRST_UART2 181 +#define SRST_UART3 182 +#define SRST_UART4 183 +#define SRST_SIMC 186 +#define SRST_TSP 188 +#define SRST_TSP_CLKIN0 189 + +#define SRST_CORE_L0 192 +#define SRST_CORE_L1 193 +#define SRST_CORE_L2 194 +#define SRST_CORE_L3 195 +#define SRST_CORE_L0_PO 195 +#define SRST_CORE_L1_PO 197 +#define SRST_CORE_L2_PO 198 +#define SRST_CORE_L3_PO 199 +#define SRST_L2_L 200 +#define SRST_ADB_L 201 +#define SRST_PD_CORE_L_NIU 202 +#define SRST_CCI_SYS 203 +#define SRST_CCI_DDR 204 +#define SRST_CCI 205 +#define SRST_SOCDBG_L 206 +#define SRST_CORE_L_DBG 207 + +#define SRST_CORE_B0_NC 208 +#define SRST_CORE_B0_PO_NC 209 +#define SRST_L2_B_NC 210 +#define SRST_ADB_B_NC 211 +#define SRST_PD_CORE_B_NIU_NC 212 +#define SRST_PDBUS_STRSYS_NC 213 +#define SRST_CORE_L0_NC 214 +#define SRST_CORE_L0_PO_NC 215 +#define SRST_L2_L_NC 216 +#define SRST_ADB_L_NC 217 +#define SRST_PD_CORE_L_NIU_NC 218 +#define SRST_CCI_SYS_NC 219 +#define SRST_CCI_DDR_NC 220 +#define SRST_CCI_NC 221 +#define SRST_TRACE_NC 222 + +#define SRST_TIMER00 224 +#define SRST_TIMER01 225 +#define SRST_TIMER02 226 +#define SRST_TIMER03 227 +#define SRST_TIMER04 228 +#define SRST_TIMER05 229 +#define SRST_TIMER10 230 +#define SRST_TIMER11 231 +#define SRST_TIMER12 232 +#define SRST_TIMER13 233 +#define SRST_TIMER14 234 +#define SRST_TIMER15 235 +#define SRST_TIMER0_APB 236 +#define SRST_TIMER1_APB 237 + +#endif diff --cc dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h index 00000000000,25aed298ac2..25aed298ac2 mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h +++ b/dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h diff --cc dts/upstream/include/dt-bindings/clock/samsung,exynosautov920.h index 00000000000,c720f344b6b..c720f344b6b mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/clock/samsung,exynosautov920.h +++ b/dts/upstream/include/dt-bindings/clock/samsung,exynosautov920.h diff --cc dts/upstream/include/dt-bindings/iio/adi,ad4695.h index 00000000000,9fbef542bf6..9fbef542bf6 mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/iio/adi,ad4695.h +++ b/dts/upstream/include/dt-bindings/iio/adi,ad4695.h diff --cc dts/upstream/include/dt-bindings/interconnect/qcom,ipq5332.h index 00000000000,16475bb07a4..16475bb07a4 mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/interconnect/qcom,ipq5332.h +++ b/dts/upstream/include/dt-bindings/interconnect/qcom,ipq5332.h diff --cc dts/upstream/include/dt-bindings/interconnect/qcom,msm8937.h index 00000000000,98b8a4637aa..98b8a4637aa mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/interconnect/qcom,msm8937.h +++ b/dts/upstream/include/dt-bindings/interconnect/qcom,msm8937.h diff --cc dts/upstream/include/dt-bindings/interconnect/qcom,msm8976.h index 00000000000,4ea90f22320..4ea90f22320 mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/interconnect/qcom,msm8976.h +++ b/dts/upstream/include/dt-bindings/interconnect/qcom,msm8976.h diff --cc dts/upstream/include/dt-bindings/pinctrl/pinctrl-cv1800b.h index 00000000000,0593fc33d47..0593fc33d47 mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/pinctrl/pinctrl-cv1800b.h +++ b/dts/upstream/include/dt-bindings/pinctrl/pinctrl-cv1800b.h diff --cc dts/upstream/include/dt-bindings/pinctrl/pinctrl-cv1812h.h index 00000000000,2908de34791..2908de34791 mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/pinctrl/pinctrl-cv1812h.h +++ b/dts/upstream/include/dt-bindings/pinctrl/pinctrl-cv1812h.h diff --cc dts/upstream/include/dt-bindings/pinctrl/pinctrl-cv18xx.h index 00000000000,bc92ad1067e..bc92ad1067e mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/pinctrl/pinctrl-cv18xx.h +++ b/dts/upstream/include/dt-bindings/pinctrl/pinctrl-cv18xx.h diff --cc dts/upstream/include/dt-bindings/pinctrl/pinctrl-sg2000.h index 00000000000,4871f9a7c6c..4871f9a7c6c mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/pinctrl/pinctrl-sg2000.h +++ b/dts/upstream/include/dt-bindings/pinctrl/pinctrl-sg2000.h diff --cc dts/upstream/include/dt-bindings/pinctrl/pinctrl-sg2002.h index 00000000000,3c36cfa0a55..3c36cfa0a55 mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/pinctrl/pinctrl-sg2002.h +++ b/dts/upstream/include/dt-bindings/pinctrl/pinctrl-sg2002.h diff --cc dts/upstream/include/dt-bindings/power/rockchip,rk3576-power.h index 00000000000,324a056aa85..324a056aa85 mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/power/rockchip,rk3576-power.h +++ b/dts/upstream/include/dt-bindings/power/rockchip,rk3576-power.h diff --cc dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h index 00000000000,ae856906f3a..ae856906f3a mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h +++ b/dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h diff --cc dts/upstream/include/dt-bindings/soc/qe-fsl,tsa.h index 00000000000,3cf3df9c096..3cf3df9c096 mode 000000,100644..100644 --- a/dts/upstream/include/dt-bindings/soc/qe-fsl,tsa.h +++ b/dts/upstream/include/dt-bindings/soc/qe-fsl,tsa.h diff --cc dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-catalina.dts index 00000000000,82835e96317..82835e96317 mode 000000,100644..100644 --- a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-catalina.dts +++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-catalina.dts diff --cc dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-blueridge-4u.dts index 00000000000,839aad4ddd9..839aad4ddd9 mode 000000,100644..100644 --- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-blueridge-4u.dts +++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-blueridge-4u.dts diff --cc dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-blueridge.dts index 00000000000,dfe5cc3edb5..dfe5cc3edb5 mode 000000,100644..100644 --- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-blueridge.dts +++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-blueridge.dts diff --cc dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-fuji.dts index 00000000000,c24e464e5fa..c24e464e5fa mode 000000,100644..100644 --- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-fuji.dts +++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-fuji.dts diff --cc dts/upstream/src/arm/aspeed/ibm-power11-quad.dtsi index 00000000000,68c941a194b..68c941a194b mode 000000,100644..100644 --- a/dts/upstream/src/arm/aspeed/ibm-power11-quad.dtsi +++ b/dts/upstream/src/arm/aspeed/ibm-power11-quad.dtsi diff --cc dts/upstream/src/arm/broadcom/bcm2166x-common.dtsi index 00000000000,87180b7fd69..87180b7fd69 mode 000000,100644..100644 --- a/dts/upstream/src/arm/broadcom/bcm2166x-common.dtsi +++ b/dts/upstream/src/arm/broadcom/bcm2166x-common.dtsi diff --cc dts/upstream/src/arm/cirrus/ep93xx-bk3.dts index 00000000000,40bc9b2a6ba..40bc9b2a6ba mode 000000,100644..100644 --- a/dts/upstream/src/arm/cirrus/ep93xx-bk3.dts +++ b/dts/upstream/src/arm/cirrus/ep93xx-bk3.dts diff --cc dts/upstream/src/arm/cirrus/ep93xx-edb9302.dts index 00000000000,312b2be1c63..312b2be1c63 mode 000000,100644..100644 --- a/dts/upstream/src/arm/cirrus/ep93xx-edb9302.dts +++ b/dts/upstream/src/arm/cirrus/ep93xx-edb9302.dts diff --cc dts/upstream/src/arm/cirrus/ep93xx-ts7250.dts index 00000000000,9e03f93d9fc..9e03f93d9fc mode 000000,100644..100644 --- a/dts/upstream/src/arm/cirrus/ep93xx-ts7250.dts +++ b/dts/upstream/src/arm/cirrus/ep93xx-ts7250.dts diff --cc dts/upstream/src/arm/cirrus/ep93xx.dtsi index 00000000000,0dd1eee346c..0dd1eee346c mode 000000,100644..100644 --- a/dts/upstream/src/arm/cirrus/ep93xx.dtsi +++ b/dts/upstream/src/arm/cirrus/ep93xx.dtsi diff --cc dts/upstream/src/arm/st/stm32mp151c-mecio1r0.dts index 00000000000,a5ea1431c39..a5ea1431c39 mode 000000,100644..100644 --- a/dts/upstream/src/arm/st/stm32mp151c-mecio1r0.dts +++ b/dts/upstream/src/arm/st/stm32mp151c-mecio1r0.dts diff --cc dts/upstream/src/arm/st/stm32mp151c-mect1s.dts index 00000000000,a1b8c3646e9..a1b8c3646e9 mode 000000,100644..100644 --- a/dts/upstream/src/arm/st/stm32mp151c-mect1s.dts +++ b/dts/upstream/src/arm/st/stm32mp151c-mect1s.dts diff --cc dts/upstream/src/arm/st/stm32mp153c-mecio1r1.dts index 00000000000,16b814c1935..16b814c1935 mode 000000,100644..100644 --- a/dts/upstream/src/arm/st/stm32mp153c-mecio1r1.dts +++ b/dts/upstream/src/arm/st/stm32mp153c-mecio1r1.dts diff --cc dts/upstream/src/arm/st/stm32mp15x-mecio1-io.dtsi index 00000000000,915ba2526f4..915ba2526f4 mode 000000,100644..100644 --- a/dts/upstream/src/arm/st/stm32mp15x-mecio1-io.dtsi +++ b/dts/upstream/src/arm/st/stm32mp15x-mecio1-io.dtsi diff --cc dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-sp.dts index 00000000000,0cf16dc903c..0cf16dc903c mode 000000,100644..100644 --- a/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-sp.dts +++ b/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-sp.dts diff --cc dts/upstream/src/arm64/amlogic/amlogic-c3-c308l-aw419.dts index 00000000000,45f8631f9fe..45f8631f9fe mode 000000,100644..100644 --- a/dts/upstream/src/arm64/amlogic/amlogic-c3-c308l-aw419.dts +++ b/dts/upstream/src/arm64/amlogic/amlogic-c3-c308l-aw419.dts diff --cc dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b.dts index 00000000000,2bdbb678024..2bdbb678024 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b.dts +++ b/dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b.dts diff --cc dts/upstream/src/arm64/broadcom/bcm2712.dtsi index 00000000000,6e5a984c1d4..6e5a984c1d4 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/broadcom/bcm2712.dtsi +++ b/dts/upstream/src/arm64/broadcom/bcm2712.dtsi diff --cc dts/upstream/src/arm64/freescale/imx8-ss-lvds0.dtsi index 00000000000,dad0dc8fb43..dad0dc8fb43 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/freescale/imx8-ss-lvds0.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8-ss-lvds0.dtsi diff --cc dts/upstream/src/arm64/freescale/imx8-ss-lvds1.dtsi index 00000000000,12ae4f48e1e..12ae4f48e1e mode 000000,100644..100644 --- a/dts/upstream/src/arm64/freescale/imx8-ss-lvds1.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8-ss-lvds1.dtsi diff --cc dts/upstream/src/arm64/freescale/imx8-ss-mipi0.dtsi index 00000000000,9c5b0cbdfcb..9c5b0cbdfcb mode 000000,100644..100644 --- a/dts/upstream/src/arm64/freescale/imx8-ss-mipi0.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8-ss-mipi0.dtsi diff --cc dts/upstream/src/arm64/freescale/imx8-ss-mipi1.dtsi index 00000000000,5b1f08e412b..5b1f08e412b mode 000000,100644..100644 --- a/dts/upstream/src/arm64/freescale/imx8-ss-mipi1.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8-ss-mipi1.dtsi diff --cc dts/upstream/src/arm64/freescale/imx8mp-phycore-no-eth.dtso index 00000000000,5f0278bf61e..5f0278bf61e mode 000000,100644..100644 --- a/dts/upstream/src/arm64/freescale/imx8mp-phycore-no-eth.dtso +++ b/dts/upstream/src/arm64/freescale/imx8mp-phycore-no-eth.dtso diff --cc dts/upstream/src/arm64/freescale/imx8mp-var-som-symphony.dts index 00000000000,36d3eb86520..36d3eb86520 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/freescale/imx8mp-var-som-symphony.dts +++ b/dts/upstream/src/arm64/freescale/imx8mp-var-som-symphony.dts diff --cc dts/upstream/src/arm64/freescale/imx8mp-var-som.dtsi index 00000000000,b2ac2583a59..b2ac2583a59 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/freescale/imx8mp-var-som.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8mp-var-som.dtsi diff --cc dts/upstream/src/arm64/freescale/imx8qm-ss-lvds.dtsi index 00000000000,0514d8b2af7..0514d8b2af7 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/freescale/imx8qm-ss-lvds.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8qm-ss-lvds.dtsi diff --cc dts/upstream/src/arm64/freescale/imx8qm-ss-mipi.dtsi index 00000000000,f4c393fe720..f4c393fe720 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/freescale/imx8qm-ss-mipi.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8qm-ss-mipi.dtsi diff --cc dts/upstream/src/arm64/freescale/imx93-14x14-evk.dts index 00000000000,236a44c1782..236a44c1782 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/freescale/imx93-14x14-evk.dts +++ b/dts/upstream/src/arm64/freescale/imx93-14x14-evk.dts diff --cc dts/upstream/src/arm64/freescale/imx93-kontron-bl-osm-s.dts index 00000000000,89e97c604bd..89e97c604bd mode 000000,100644..100644 --- a/dts/upstream/src/arm64/freescale/imx93-kontron-bl-osm-s.dts +++ b/dts/upstream/src/arm64/freescale/imx93-kontron-bl-osm-s.dts diff --cc dts/upstream/src/arm64/freescale/imx93-kontron-osm-s.dtsi index 00000000000,47c1363a2f9..47c1363a2f9 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/freescale/imx93-kontron-osm-s.dtsi +++ b/dts/upstream/src/arm64/freescale/imx93-kontron-osm-s.dtsi diff --cc dts/upstream/src/arm64/qcom/msm8916-samsung-j3-common.dtsi index 00000000000,1d74cccc438..1d74cccc438 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/qcom/msm8916-samsung-j3-common.dtsi +++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-j3-common.dtsi diff --cc dts/upstream/src/arm64/qcom/msm8916-samsung-j3ltetw.dts index 00000000000,a26d2fd13c9..a26d2fd13c9 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/qcom/msm8916-samsung-j3ltetw.dts +++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-j3ltetw.dts diff --cc dts/upstream/src/arm64/qcom/msm8916-wingtech-wt86518.dts index 00000000000,3cfa80e38a9..3cfa80e38a9 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/qcom/msm8916-wingtech-wt86518.dts +++ b/dts/upstream/src/arm64/qcom/msm8916-wingtech-wt86518.dts diff --cc dts/upstream/src/arm64/qcom/msm8916-wingtech-wt86528.dts index 00000000000,ec2c4dcd3ea..ec2c4dcd3ea mode 000000,100644..100644 --- a/dts/upstream/src/arm64/qcom/msm8916-wingtech-wt86528.dts +++ b/dts/upstream/src/arm64/qcom/msm8916-wingtech-wt86528.dts diff --cc dts/upstream/src/arm64/qcom/msm8916-wingtech-wt865x8.dtsi index 00000000000,1a7c347dc3f..1a7c347dc3f mode 000000,100644..100644 --- a/dts/upstream/src/arm64/qcom/msm8916-wingtech-wt865x8.dtsi +++ b/dts/upstream/src/arm64/qcom/msm8916-wingtech-wt865x8.dtsi diff --cc dts/upstream/src/arm64/qcom/msm8929-pm8916.dtsi index 00000000000,c2bf25997e9..c2bf25997e9 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/qcom/msm8929-pm8916.dtsi +++ b/dts/upstream/src/arm64/qcom/msm8929-pm8916.dtsi diff --cc dts/upstream/src/arm64/qcom/msm8929-wingtech-wt82918hd.dts index 00000000000,8feecffb16b..8feecffb16b mode 000000,100644..100644 --- a/dts/upstream/src/arm64/qcom/msm8929-wingtech-wt82918hd.dts +++ b/dts/upstream/src/arm64/qcom/msm8929-wingtech-wt82918hd.dts diff --cc dts/upstream/src/arm64/qcom/msm8929.dtsi index 00000000000,ef7bb1ced95..ef7bb1ced95 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/qcom/msm8929.dtsi +++ b/dts/upstream/src/arm64/qcom/msm8929.dtsi diff --cc dts/upstream/src/arm64/qcom/msm8939-wingtech-wt82918.dts index 00000000000,aa6b699aa2a..aa6b699aa2a mode 000000,100644..100644 --- a/dts/upstream/src/arm64/qcom/msm8939-wingtech-wt82918.dts +++ b/dts/upstream/src/arm64/qcom/msm8939-wingtech-wt82918.dts diff --cc dts/upstream/src/arm64/qcom/msm8939-wingtech-wt82918.dtsi index 00000000000,800e0747a2f..800e0747a2f mode 000000,100644..100644 --- a/dts/upstream/src/arm64/qcom/msm8939-wingtech-wt82918.dtsi +++ b/dts/upstream/src/arm64/qcom/msm8939-wingtech-wt82918.dtsi diff --cc dts/upstream/src/arm64/qcom/msm8939-wingtech-wt82918hd.dts index 00000000000,59414db4250..59414db4250 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/qcom/msm8939-wingtech-wt82918hd.dts +++ b/dts/upstream/src/arm64/qcom/msm8939-wingtech-wt82918hd.dts diff --cc dts/upstream/src/arm64/qcom/msm8992-lg-h815.dts index 00000000000,38b305816d2..38b305816d2 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/qcom/msm8992-lg-h815.dts +++ b/dts/upstream/src/arm64/qcom/msm8992-lg-h815.dts diff --cc dts/upstream/src/arm64/qcom/x1e78100-lenovo-thinkpad-t14s.dts index 00000000000,fdde988ae01..fdde988ae01 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/qcom/x1e78100-lenovo-thinkpad-t14s.dts +++ b/dts/upstream/src/arm64/qcom/x1e78100-lenovo-thinkpad-t14s.dts diff --cc dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus.dtsi index 00000000000,cdb401767c4..cdb401767c4 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus.dtsi +++ b/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus.dtsi diff --cc dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus13.dts index 00000000000,eb7580dd968..eb7580dd968 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus13.dts +++ b/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus13.dts diff --cc dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus15.dts index 00000000000,4751ad9b510..4751ad9b510 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus15.dts +++ b/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus15.dts diff --cc dts/upstream/src/arm64/renesas/r9a07g043u11-smarc-du-adv7513.dtso index 00000000000,ecd43a67100..ecd43a67100 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/renesas/r9a07g043u11-smarc-du-adv7513.dtso +++ b/dts/upstream/src/arm64/renesas/r9a07g043u11-smarc-du-adv7513.dtso diff --cc dts/upstream/src/arm64/renesas/r9a09g057.dtsi index 00000000000,1ad5a1b6917..1ad5a1b6917 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/renesas/r9a09g057.dtsi +++ b/dts/upstream/src/arm64/renesas/r9a09g057.dtsi diff --cc dts/upstream/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts index 00000000000,4703da8e9cf..4703da8e9cf mode 000000,100644..100644 --- a/dts/upstream/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/dts/upstream/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts diff --cc dts/upstream/src/arm64/renesas/rz-smarc-du-adv7513.dtsi index 00000000000,36707576030..36707576030 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/renesas/rz-smarc-du-adv7513.dtsi +++ b/dts/upstream/src/arm64/renesas/rz-smarc-du-adv7513.dtsi diff --cc dts/upstream/src/arm64/rockchip/px30-firefly-jd4-core-mb.dts index 00000000000,d03e6aef54d..d03e6aef54d mode 000000,100644..100644 --- a/dts/upstream/src/arm64/rockchip/px30-firefly-jd4-core-mb.dts +++ b/dts/upstream/src/arm64/rockchip/px30-firefly-jd4-core-mb.dts diff --cc dts/upstream/src/arm64/rockchip/px30-firefly-jd4-core.dtsi index 00000000000,f18d7eb9a9c..f18d7eb9a9c mode 000000,100644..100644 --- a/dts/upstream/src/arm64/rockchip/px30-firefly-jd4-core.dtsi +++ b/dts/upstream/src/arm64/rockchip/px30-firefly-jd4-core.dtsi diff --cc dts/upstream/src/arm64/rockchip/rk3399-base.dtsi index 00000000000,9d5f5b083e3..9d5f5b083e3 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/rockchip/rk3399-base.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3399-base.dtsi diff --cc dts/upstream/src/arm64/rockchip/rk3566-lckfb-tspi.dts index 00000000000,7cd91f8000c..7cd91f8000c mode 000000,100644..100644 --- a/dts/upstream/src/arm64/rockchip/rk3566-lckfb-tspi.dts +++ b/dts/upstream/src/arm64/rockchip/rk3566-lckfb-tspi.dts diff --cc dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5-display-vz.dtso index 00000000000,70c23e1bf14..70c23e1bf14 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5-display-vz.dtso +++ b/dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5-display-vz.dtso diff --cc dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5-display.dtsi index 00000000000,b22bb543ecb..b22bb543ecb mode 000000,100644..100644 --- a/dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5-display.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5-display.dtsi diff --cc dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts index 00000000000,467f6959408..467f6959408 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts diff --cc dts/upstream/src/arm64/ti/k3-am67a-beagley-ai.dts index 00000000000,44dfbdf8927..44dfbdf8927 mode 000000,100644..100644 --- a/dts/upstream/src/arm64/ti/k3-am67a-beagley-ai.dts +++ b/dts/upstream/src/arm64/ti/k3-am67a-beagley-ai.dts