From: Gabor Juhos <juhosg@openwrt.org>
Date: Wed, 14 Mar 2012 09:45:24 +0000 (+0100)
Subject: MIPS: ath79: rework IP2/IP3 interrupt handling
X-Git-Tag: v3.5-rc1~47^2^5~7
X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4dbcbdf8135def8f704b130305721bdd42a8078b;p=pandora-kernel.git

MIPS: ath79: rework IP2/IP3 interrupt handling

The current implementation assumes that flushing the
DDR writeback buffer is required for IP2/IP3 interrupts,
however this is not true for all SoCs.

Use SoC specific IP2/IP3 handlers instead of flushing
the buffers in the dispatcher code.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Cc: linux-mips@linux-mips.org
Cc: mcgrof@infradead.org
Patchwork: https://patchwork.linux-mips.org/patch/3509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

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