From: Linus Torvalds Date: Mon, 21 Sep 2009 16:15:07 +0000 (-0700) Subject: Merge branch 'perfcounters-rename-for-linus' of git://git.kernel.org/pub/scm/linux... X-Git-Tag: v2.6.32-rc1~611 X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=43c1266ce4dc06bfd236cec31e11e9ecd69c0bef;hp=57c0c15b5244320065374ad2c54f4fbec77a6428;p=pandora-kernel.git Merge branch 'perfcounters-rename-for-linus' of git://git./linux/kernel/git/tip/linux-2.6-tip * 'perfcounters-rename-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: perf: Tidy up after the big rename perf: Do the big rename: Performance Counters -> Performance Events perf_counter: Rename 'event' to event_id/hw_event perf_counter: Rename list_entry -> group_entry, counter_list -> group_list Manually resolved some fairly trivial conflicts with the tracing tree in include/trace/ftrace.h and kernel/trace/trace_syscalls.c. --- diff --git a/Documentation/DocBook/Makefile b/Documentation/DocBook/Makefile index 9632444f6c62..ab8300f67182 100644 --- a/Documentation/DocBook/Makefile +++ b/Documentation/DocBook/Makefile @@ -14,7 +14,7 @@ DOCBOOKS := z8530book.xml mcabook.xml device-drivers.xml \ genericirq.xml s390-drivers.xml uio-howto.xml scsi.xml \ mac80211.xml debugobjects.xml sh.xml regulator.xml \ alsa-driver-api.xml writing-an-alsa-driver.xml \ - tracepoint.xml + tracepoint.xml media.xml ### # The build process is as follows (targets): @@ -32,7 +32,7 @@ PS_METHOD = $(prefer-db2x) ### # The targets that may be used. -PHONY += xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs +PHONY += xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs media BOOKS := $(addprefix $(obj)/,$(DOCBOOKS)) xmldocs: $(BOOKS) @@ -45,12 +45,16 @@ PDF := $(patsubst %.xml, %.pdf, $(BOOKS)) pdfdocs: $(PDF) HTML := $(sort $(patsubst %.xml, %.html, $(BOOKS))) -htmldocs: $(HTML) +htmldocs: media $(HTML) $(call build_main_index) MAN := $(patsubst %.xml, %.9, $(BOOKS)) mandocs: $(MAN) +media: + mkdir -p $(srctree)/Documentation/DocBook/media/ + cp $(srctree)/Documentation/DocBook/dvb/*.png $(srctree)/Documentation/DocBook/v4l/*.gif $(srctree)/Documentation/DocBook/media/ + installmandocs: mandocs mkdir -p /usr/local/man/man9/ install Documentation/DocBook/man/*.9.gz /usr/local/man/man9/ diff --git a/Documentation/DocBook/dvb/.gitignore b/Documentation/DocBook/dvb/.gitignore new file mode 100644 index 000000000000..d7ec32eafac9 --- /dev/null +++ b/Documentation/DocBook/dvb/.gitignore @@ -0,0 +1 @@ +!*.xml diff --git a/Documentation/DocBook/dvb/audio.xml b/Documentation/DocBook/dvb/audio.xml new file mode 100644 index 000000000000..eeb96b8a0864 --- /dev/null +++ b/Documentation/DocBook/dvb/audio.xml @@ -0,0 +1,1473 @@ +DVB Audio Device +The DVB audio device controls the MPEG2 audio decoder of the DVB hardware. It +can be accessed through /dev/dvb/adapter0/audio0. Data types and and +ioctl definitions can be accessed by including linux/dvb/video.h in your +application. + +Please note that some DVB cards don’t have their own MPEG decoder, which results in +the omission of the audio and video device. + + +
+Audio Data Types +This section describes the structures, data types and defines used when talking to the +audio device. + + +
+audio_stream_source_t +The audio stream source is set through the AUDIO_SELECT_SOURCE call and can take +the following values, depending on whether we are replaying from an internal (demux) or +external (user write) source. + + + typedef enum { + AUDIO_SOURCE_DEMUX, + AUDIO_SOURCE_MEMORY + } audio_stream_source_t; + +AUDIO_SOURCE_DEMUX selects the demultiplexer (fed either by the frontend or the +DVR device) as the source of the video stream. If AUDIO_SOURCE_MEMORY +is selected the stream comes from the application through the write() system +call. + + +
+
+audio_play_state_t +The following values can be returned by the AUDIO_GET_STATUS call representing the +state of audio playback. + + + typedef enum { + AUDIO_STOPPED, + AUDIO_PLAYING, + AUDIO_PAUSED + } audio_play_state_t; + + +
+
+audio_channel_select_t +The audio channel selected via AUDIO_CHANNEL_SELECT is determined by the +following values. + + + typedef enum { + AUDIO_STEREO, + AUDIO_MONO_LEFT, + AUDIO_MONO_RIGHT, + } audio_channel_select_t; + + +
+
+struct audio_status +The AUDIO_GET_STATUS call returns the following structure informing about various +states of the playback operation. + + + typedef struct audio_status { + boolean AV_sync_state; + boolean mute_state; + audio_play_state_t play_state; + audio_stream_source_t stream_source; + audio_channel_select_t channel_select; + boolean bypass_mode; + } audio_status_t; + + +
+
+struct audio_mixer +The following structure is used by the AUDIO_SET_MIXER call to set the audio +volume. + + + typedef struct audio_mixer { + unsigned int volume_left; + unsigned int volume_right; + } audio_mixer_t; + + +
+
+audio encodings +A call to AUDIO_GET_CAPABILITIES returns an unsigned integer with the following +bits set according to the hardwares capabilities. + + + #define AUDIO_CAP_DTS 1 + #define AUDIO_CAP_LPCM 2 + #define AUDIO_CAP_MP1 4 + #define AUDIO_CAP_MP2 8 + #define AUDIO_CAP_MP3 16 + #define AUDIO_CAP_AAC 32 + #define AUDIO_CAP_OGG 64 + #define AUDIO_CAP_SDDS 128 + #define AUDIO_CAP_AC3 256 + + +
+
+struct audio_karaoke +The ioctl AUDIO_SET_KARAOKE uses the following format: + + + typedef + struct audio_karaoke{ + int vocal1; + int vocal2; + int melody; + } audio_karaoke_t; + +If Vocal1 or Vocal2 are non-zero, they get mixed into left and right t at 70% each. If both, +Vocal1 and Vocal2 are non-zero, Vocal1 gets mixed into the left channel and Vocal2 into the +right channel at 100% each. Ff Melody is non-zero, the melody channel gets mixed into left +and right. + + +
+
+audio attributes +The following attributes can be set by a call to AUDIO_SET_ATTRIBUTES: + + + typedef uint16_t audio_attributes_t; + /⋆ bits: descr. ⋆/ + /⋆ 15-13 audio coding mode (0=ac3, 2=mpeg1, 3=mpeg2ext, 4=LPCM, 6=DTS, ⋆/ + /⋆ 12 multichannel extension ⋆/ + /⋆ 11-10 audio type (0=not spec, 1=language included) ⋆/ + /⋆ 9- 8 audio application mode (0=not spec, 1=karaoke, 2=surround) ⋆/ + /⋆ 7- 6 Quantization / DRC (mpeg audio: 1=DRC exists)(lpcm: 0=16bit, ⋆/ + /⋆ 5- 4 Sample frequency fs (0=48kHz, 1=96kHz) ⋆/ + /⋆ 2- 0 number of audio channels (n+1 channels) ⋆/ + +
+
+Audio Function Calls + + +
+open() +DESCRIPTION + + +This system call opens a named audio device (e.g. /dev/dvb/adapter0/audio0) + for subsequent use. When an open() call has succeeded, the device will be ready + for use. The significance of blocking or non-blocking mode is described in the + documentation for functions where there is a difference. It does not affect the + semantics of the open() call itself. A device opened in blocking mode can later + be put into non-blocking mode (and vice versa) using the F_SETFL command + of the fcntl system call. This is a standard system call, documented in the Linux + manual page for fcntl. Only one user can open the Audio Device in O_RDWR + mode. All other attempts to open the device in this mode will fail, and an error + code will be returned. If the Audio Device is opened in O_RDONLY mode, the + only ioctl call that can be used is AUDIO_GET_STATUS. All other call will + return with an error code. + + +SYNOPSIS + + +int open(const char ⋆deviceName, int flags); + + +PARAMETERS + + +const char + *deviceName + +Name of specific audio device. + + +int flags + +A bit-wise OR of the following flags: + + + +O_RDONLY read-only access + + + +O_RDWR read/write access + + + +O_NONBLOCK open in non-blocking mode + + + +(blocking mode is the default) + + +ERRORS + + +ENODEV + +Device driver not loaded/available. + + +EINTERNAL + +Internal error. + + +EBUSY + +Device or resource busy. + + +EINVAL + +Invalid argument. + + + +
+
+close() +DESCRIPTION + + +This system call closes a previously opened audio device. + + +SYNOPSIS + + +int close(int fd); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + + +
+
+write() +DESCRIPTION + + +This system call can only be used if AUDIO_SOURCE_MEMORY is selected + in the ioctl call AUDIO_SELECT_SOURCE. The data provided shall be in + PES format. If O_NONBLOCK is not specified the function will block until + buffer space is available. The amount of data to be transferred is implied by + count. + + +SYNOPSIS + + +size_t write(int fd, const void ⋆buf, size_t count); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +void *buf + +Pointer to the buffer containing the PES data. + + +size_t count + +Size of buf. + + +ERRORS + + +EPERM + +Mode AUDIO_SOURCE_MEMORY not selected. + + +ENOMEM + +Attempted to write more data than the internal buffer can + hold. + + +EBADF + +fd is not a valid open file descriptor. + + + +
AUDIO_STOP +DESCRIPTION + + +This ioctl call asks the Audio Device to stop playing the current stream. + + +SYNOPSIS + + +int ioctl(int fd, int request = AUDIO_STOP); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_STOP for this command. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINTERNAL + +Internal error. + + + +
AUDIO_PLAY +DESCRIPTION + + +This ioctl call asks the Audio Device to start playing an audio stream from the + selected source. + + +SYNOPSIS + + +int ioctl(int fd, int request = AUDIO_PLAY); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_PLAY for this command. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINTERNAL + +Internal error. + + + +
AUDIO_PAUSE +DESCRIPTION + + +This ioctl call suspends the audio stream being played. Decoding and playing + are paused. It is then possible to restart again decoding and playing process of + the audio stream using AUDIO_CONTINUE command. + + +If AUDIO_SOURCE_MEMORY is selected in the ioctl call + AUDIO_SELECT_SOURCE, the DVB-subsystem will not decode (consume) + any more data until the ioctl call AUDIO_CONTINUE or AUDIO_PLAY is + performed. + + +SYNOPSIS + + +int ioctl(int fd, int request = AUDIO_PAUSE); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_PAUSE for this command. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EINTERNAL + +Internal error. + + + +
AUDIO_SELECT_SOURCE +DESCRIPTION + + +This ioctl call informs the audio device which source shall be used + for the input data. The possible sources are demux or memory. If + AUDIO_SOURCE_MEMORY is selected, the data is fed to the Audio Device + through the write command. + + +SYNOPSIS + + +int ioctl(int fd, int request = AUDIO_SELECT_SOURCE, + audio_stream_source_t source); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_SELECT_SOURCE for this command. + + +audio_stream_source_t + source + +Indicates the source that shall be used for the Audio + stream. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EINTERNAL + +Internal error. + + +EINVAL + +Illegal input parameter. + + + +
AUDIO_SET_MUTE +DESCRIPTION + + +This ioctl call asks the audio device to mute the stream that is currently being + played. + + +SYNOPSIS + + +int ioctl(int fd, int request = AUDIO_SET_MUTE, + boolean state); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_SET_MUTE for this command. + + +boolean state + +Indicates if audio device shall mute or not. + + + +TRUE Audio Mute + + + +FALSE Audio Un-mute + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EINTERNAL + +Internal error. + + +EINVAL + +Illegal input parameter. + + + +
AUDIO_SET_AV_SYNC +DESCRIPTION + + +This ioctl call asks the Audio Device to turn ON or OFF A/V synchronization. + + +SYNOPSIS + + +int ioctl(int fd, int request = AUDIO_SET_AV_SYNC, + boolean state); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_AV_SYNC for this command. + + +boolean state + +Tells the DVB subsystem if A/V synchronization shall be + ON or OFF. + + + +TRUE AV-sync ON + + + +FALSE AV-sync OFF + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EINTERNAL + +Internal error. + + +EINVAL + +Illegal input parameter. + + + +
AUDIO_SET_BYPASS_MODE +DESCRIPTION + + +This ioctl call asks the Audio Device to bypass the Audio decoder and forward + the stream without decoding. This mode shall be used if streams that can’t be + handled by the DVB system shall be decoded. Dolby DigitalTM streams are + automatically forwarded by the DVB subsystem if the hardware can handle it. + + +SYNOPSIS + + +int ioctl(int fd, int request = + AUDIO_SET_BYPASS_MODE, boolean mode); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_SET_BYPASS_MODE for this + command. + + +boolean mode + +Enables or disables the decoding of the current Audio + stream in the DVB subsystem. + + + +TRUE Bypass is disabled + + + +FALSE Bypass is enabled + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EINTERNAL + +Internal error. + + +EINVAL + +Illegal input parameter. + + + +
AUDIO_CHANNEL_SELECT +DESCRIPTION + + +This ioctl call asks the Audio Device to select the requested channel if possible. + + +SYNOPSIS + + +int ioctl(int fd, int request = + AUDIO_CHANNEL_SELECT, audio_channel_select_t); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_CHANNEL_SELECT for this + command. + + +audio_channel_select_t + ch + +Select the output format of the audio (mono left/right, + stereo). + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EINTERNAL + +Internal error. + + +EINVAL + +Illegal input parameter ch. + + + +
AUDIO_GET_STATUS +DESCRIPTION + + +This ioctl call asks the Audio Device to return the current state of the Audio + Device. + + +SYNOPSIS + + +int ioctl(int fd, int request = AUDIO_GET_STATUS, + struct audio_status ⋆status); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_GET_STATUS for this command. + + +struct audio_status + *status + +Returns the current state of Audio Device. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EINTERNAL + +Internal error. + + +EFAULT + +status points to invalid address. + + + +
AUDIO_GET_CAPABILITIES +DESCRIPTION + + +This ioctl call asks the Audio Device to tell us about the decoding capabilities + of the audio hardware. + + +SYNOPSIS + + +int ioctl(int fd, int request = + AUDIO_GET_CAPABILITIES, unsigned int ⋆cap); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_GET_CAPABILITIES for this + command. + + +unsigned int *cap + +Returns a bit array of supported sound formats. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EINTERNAL + +Internal error. + + +EFAULT + +cap points to an invalid address. + + + +
AUDIO_CLEAR_BUFFER +DESCRIPTION + + +This ioctl call asks the Audio Device to clear all software and hardware buffers + of the audio decoder device. + + +SYNOPSIS + + +int ioctl(int fd, int request = AUDIO_CLEAR_BUFFER); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_CLEAR_BUFFER for this command. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EINTERNAL + +Internal error. + + + +
AUDIO_SET_ID +DESCRIPTION + + +This ioctl selects which sub-stream is to be decoded if a program or system + stream is sent to the video device. If no audio stream type is set the id has to be + in [0xC0,0xDF] for MPEG sound, in [0x80,0x87] for AC3 and in [0xA0,0xA7] + for LPCM. More specifications may follow for other stream types. If the stream + type is set the id just specifies the substream id of the audio stream and only + the first 5 bits are recognized. + + +SYNOPSIS + + +int ioctl(int fd, int request = AUDIO_SET_ID, int + id); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_SET_ID for this command. + + +int id + +audio sub-stream id + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EINTERNAL + +Internal error. + + +EINVAL + +Invalid sub-stream id. + + + +
AUDIO_SET_MIXER +DESCRIPTION + + +This ioctl lets you adjust the mixer settings of the audio decoder. + + +SYNOPSIS + + +int ioctl(int fd, int request = AUDIO_SET_MIXER, + audio_mixer_t ⋆mix); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_SET_ID for this command. + + +audio_mixer_t *mix + +mixer settings. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EINTERNAL + +Internal error. + + +EFAULT + +mix points to an invalid address. + + + +
AUDIO_SET_STREAMTYPE +DESCRIPTION + + +This ioctl tells the driver which kind of audio stream to expect. This is useful + if the stream offers several audio sub-streams like LPCM and AC3. + + +SYNOPSIS + + +int ioctl(fd, int request = AUDIO_SET_STREAMTYPE, + int type); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_SET_STREAMTYPE for this + command. + + +int type + +stream type + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINVAL + +type is not a valid or supported stream type. + + + +
AUDIO_SET_EXT_ID +DESCRIPTION + + +This ioctl can be used to set the extension id for MPEG streams in DVD + playback. Only the first 3 bits are recognized. + + +SYNOPSIS + + +int ioctl(fd, int request = AUDIO_SET_EXT_ID, int + id); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_SET_EXT_ID for this command. + + +int id + +audio sub_stream_id + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINVAL + +id is not a valid id. + + + +
AUDIO_SET_ATTRIBUTES +DESCRIPTION + + +This ioctl is intended for DVD playback and allows you to set certain + information about the audio stream. + + +SYNOPSIS + + +int ioctl(fd, int request = AUDIO_SET_ATTRIBUTES, + audio_attributes_t attr ); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_SET_ATTRIBUTES for this command. + + +audio_attributes_t + attr + +audio attributes according to section ?? + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINVAL + +attr is not a valid or supported attribute setting. + + + +
AUDIO_SET_KARAOKE +DESCRIPTION + + +This ioctl allows one to set the mixer settings for a karaoke DVD. + + +SYNOPSIS + + +int ioctl(fd, int request = AUDIO_SET_STREAMTYPE, + audio_karaoke_t ⋆karaoke); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals AUDIO_SET_STREAMTYPE for this + command. + + +audio_karaoke_t + *karaoke + +karaoke settings according to section ??. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINVAL + +karaoke is not a valid or supported karaoke setting. + + +
+
diff --git a/Documentation/DocBook/dvb/ca.xml b/Documentation/DocBook/dvb/ca.xml new file mode 100644 index 000000000000..b1f1d2fad654 --- /dev/null +++ b/Documentation/DocBook/dvb/ca.xml @@ -0,0 +1,221 @@ +DVB CA Device +The DVB CA device controls the conditional access hardware. It can be accessed through +/dev/dvb/adapter0/ca0. Data types and and ioctl definitions can be accessed by +including linux/dvb/ca.h in your application. + + +
+CA Data Types + + +
+ca_slot_info_t + + /⋆ slot interface types and info ⋆/ + + typedef struct ca_slot_info_s { + int num; /⋆ slot number ⋆/ + + int type; /⋆ CA interface this slot supports ⋆/ + #define CA_CI 1 /⋆ CI high level interface ⋆/ + #define CA_CI_LINK 2 /⋆ CI link layer level interface ⋆/ + #define CA_CI_PHYS 4 /⋆ CI physical layer level interface ⋆/ + #define CA_SC 128 /⋆ simple smart card interface ⋆/ + + unsigned int flags; + #define CA_CI_MODULE_PRESENT 1 /⋆ module (or card) inserted ⋆/ + #define CA_CI_MODULE_READY 2 + } ca_slot_info_t; + + +
+
+ca_descr_info_t + + typedef struct ca_descr_info_s { + unsigned int num; /⋆ number of available descramblers (keys) ⋆/ + unsigned int type; /⋆ type of supported scrambling system ⋆/ + #define CA_ECD 1 + #define CA_NDS 2 + #define CA_DSS 4 + } ca_descr_info_t; + + +
+
+ca_cap_t + + typedef struct ca_cap_s { + unsigned int slot_num; /⋆ total number of CA card and module slots ⋆/ + unsigned int slot_type; /⋆ OR of all supported types ⋆/ + unsigned int descr_num; /⋆ total number of descrambler slots (keys) ⋆/ + unsigned int descr_type;/⋆ OR of all supported types ⋆/ + } ca_cap_t; + + +
+
+ca_msg_t + + /⋆ a message to/from a CI-CAM ⋆/ + typedef struct ca_msg_s { + unsigned int index; + unsigned int type; + unsigned int length; + unsigned char msg[256]; + } ca_msg_t; + + +
+
+ca_descr_t + + typedef struct ca_descr_s { + unsigned int index; + unsigned int parity; + unsigned char cw[8]; + } ca_descr_t; + +
+
+CA Function Calls + + +
+open() +DESCRIPTION + + +This system call opens a named ca device (e.g. /dev/ost/ca) for subsequent use. +When an open() call has succeeded, the device will be ready for use. + The significance of blocking or non-blocking mode is described in the + documentation for functions where there is a difference. It does not affect the + semantics of the open() call itself. A device opened in blocking mode can later + be put into non-blocking mode (and vice versa) using the F_SETFL command + of the fcntl system call. This is a standard system call, documented in the Linux + manual page for fcntl. Only one user can open the CA Device in O_RDWR + mode. All other attempts to open the device in this mode will fail, and an error + code will be returned. + + +SYNOPSIS + + +int open(const char ⋆deviceName, int flags); + + +PARAMETERS + + +const char + *deviceName + +Name of specific video device. + + +int flags + +A bit-wise OR of the following flags: + + + +O_RDONLY read-only access + + + +O_RDWR read/write access + + + +O_NONBLOCK open in non-blocking mode + + + +(blocking mode is the default) + + +ERRORS + + +ENODEV + +Device driver not loaded/available. + + +EINTERNAL + +Internal error. + + +EBUSY + +Device or resource busy. + + +EINVAL + +Invalid argument. + + + +
+
+close() +DESCRIPTION + + +This system call closes a previously opened audio device. + + +SYNOPSIS + + +int close(int fd); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +
+
diff --git a/Documentation/DocBook/dvb/demux.xml b/Documentation/DocBook/dvb/demux.xml new file mode 100644 index 000000000000..1b8c4e9835b9 --- /dev/null +++ b/Documentation/DocBook/dvb/demux.xml @@ -0,0 +1,973 @@ +DVB Demux Device + +The DVB demux device controls the filters of the DVB hardware/software. It can be +accessed through /dev/adapter0/demux0. Data types and and ioctl definitions can be +accessed by including linux/dvb/dmx.h in your application. + +
+Demux Data Types + +
+dmx_output_t + + typedef enum + { + DMX_OUT_DECODER, + DMX_OUT_TAP, + DMX_OUT_TS_TAP + } dmx_output_t; + +DMX_OUT_TAP delivers the stream output to the demux device on which the ioctl is +called. + +DMX_OUT_TS_TAP routes output to the logical DVR device /dev/dvb/adapter0/dvr0, +which delivers a TS multiplexed from all filters for which DMX_OUT_TS_TAP was +specified. + +
+ +
+dmx_input_t + + typedef enum + { + DMX_IN_FRONTEND, + DMX_IN_DVR + } dmx_input_t; + +
+ +
+dmx_pes_type_t + + typedef enum + { + DMX_PES_AUDIO, + DMX_PES_VIDEO, + DMX_PES_TELETEXT, + DMX_PES_SUBTITLE, + DMX_PES_PCR, + DMX_PES_OTHER + } dmx_pes_type_t; + +
+ +
+dmx_event_t + + typedef enum + { + DMX_SCRAMBLING_EV, + DMX_FRONTEND_EV + } dmx_event_t; + +
+ +
+dmx_scrambling_status_t + + typedef enum + { + DMX_SCRAMBLING_OFF, + DMX_SCRAMBLING_ON + } dmx_scrambling_status_t; + +
+ +
+struct dmx_filter + + typedef struct dmx_filter + { + uint8_t filter[DMX_FILTER_SIZE]; + uint8_t mask[DMX_FILTER_SIZE]; + } dmx_filter_t; + +
+ +
+struct dmx_sct_filter_params + + struct dmx_sct_filter_params + { + uint16_t pid; + dmx_filter_t filter; + uint32_t timeout; + uint32_t flags; + #define DMX_CHECK_CRC 1 + #define DMX_ONESHOT 2 + #define DMX_IMMEDIATE_START 4 + }; + +
+ +
+struct dmx_pes_filter_params + + struct dmx_pes_filter_params + { + uint16_t pid; + dmx_input_t input; + dmx_output_t output; + dmx_pes_type_t pes_type; + uint32_t flags; + }; + +
+ +
+struct dmx_event + + struct dmx_event + { + dmx_event_t event; + time_t timeStamp; + union + { + dmx_scrambling_status_t scrambling; + } u; + }; + +
+ +
+struct dmx_stc + + struct dmx_stc { + unsigned int num; /⋆ input : which STC? 0..N ⋆/ + unsigned int base; /⋆ output: divisor for stc to get 90 kHz clock ⋆/ + uint64_t stc; /⋆ output: stc in 'base'⋆90 kHz units ⋆/ + }; + +
+ +
+ +
+Demux Function Calls + +
+open() +DESCRIPTION + + +This system call, used with a device name of /dev/dvb/adapter0/demux0, + allocates a new filter and returns a handle which can be used for subsequent + control of that filter. This call has to be made for each filter to be used, i.e. every + returned file descriptor is a reference to a single filter. /dev/dvb/adapter0/dvr0 + is a logical device to be used for retrieving Transport Streams for digital + video recording. When reading from this device a transport stream containing + the packets from all PES filters set in the corresponding demux device + (/dev/dvb/adapter0/demux0) having the output set to DMX_OUT_TS_TAP. A + recorded Transport Stream is replayed by writing to this device. +The significance of blocking or non-blocking mode is described in the + documentation for functions where there is a difference. It does not affect the + semantics of the open() call itself. A device opened in blocking mode can later + be put into non-blocking mode (and vice versa) using the F_SETFL command + of the fcntl system call. + + +SYNOPSIS + + +int open(const char ⋆deviceName, int flags); + + +PARAMETERS + + +const char + *deviceName + +Name of demux device. + + +int flags + +A bit-wise OR of the following flags: + + + +O_RDWR read/write access + + + +O_NONBLOCK open in non-blocking mode + + + +(blocking mode is the default) + + +ERRORS + + +ENODEV + +Device driver not loaded/available. + + +EINVAL + +Invalid argument. + + +EMFILE + +“Too many open files”, i.e. no more filters available. + + +ENOMEM + +The driver failed to allocate enough memory. + + +
+ +
+close() +DESCRIPTION + + +This system call deactivates and deallocates a filter that was previously + allocated via the open() call. + + +SYNOPSIS + + +int close(int fd); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +
+ +
+read() +DESCRIPTION + + +This system call returns filtered data, which might be section or PES data. The + filtered data is transferred from the driver’s internal circular buffer to buf. The + maximum amount of data to be transferred is implied by count. + + +When returning section data the driver always tries to return a complete single + section (even though buf would provide buffer space for more data). If the size + of the buffer is smaller than the section as much as possible will be returned, + and the remaining data will be provided in subsequent calls. + + +The size of the internal buffer is 2 * 4096 bytes (the size of two maximum + sized sections) by default. The size of this buffer may be changed by using the + DMX_SET_BUFFER_SIZE function. If the buffer is not large enough, or if + the read operations are not performed fast enough, this may result in a buffer + overflow error. In this case EOVERFLOW will be returned, and the circular + buffer will be emptied. This call is blocking if there is no data to return, i.e. the + process will be put to sleep waiting for data, unless the O_NONBLOCK flag + is specified. + + +Note that in order to be able to read, the filtering process has to be started + by defining either a section or a PES filter by means of the ioctl functions, + and then starting the filtering process via the DMX_START ioctl function + or by setting the DMX_IMMEDIATE_START flag. If the reading is done + from a logical DVR demux device, the data will constitute a Transport Stream + including the packets from all PES filters in the corresponding demux device + /dev/dvb/adapter0/demux0 having the output set to DMX_OUT_TS_TAP. + + +SYNOPSIS + + +size_t read(int fd, void ⋆buf, size_t count); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +void *buf + +Pointer to the buffer to be used for returned filtered data. + + +size_t count + +Size of buf. + + +ERRORS + + +EWOULDBLOCK + +No data to return and O_NONBLOCK was specified. + + +EBADF + +fd is not a valid open file descriptor. + + +ECRC + +Last section had a CRC error - no data returned. The + buffer is flushed. + + +EOVERFLOW + + + + +The filtered data was not read from the buffer in due + time, resulting in non-read data being lost. The buffer is + flushed. + + +ETIMEDOUT + +The section was not loaded within the stated timeout + period. See ioctl DMX_SET_FILTER for how to set a + timeout. + + +EFAULT + +The driver failed to write to the callers buffer due to an + invalid *buf pointer. + + +
+ +
+write() +DESCRIPTION + + +This system call is only provided by the logical device /dev/dvb/adapter0/dvr0, + associated with the physical demux device that provides the actual DVR + functionality. It is used for replay of a digitally recorded Transport Stream. + Matching filters have to be defined in the corresponding physical demux + device, /dev/dvb/adapter0/demux0. The amount of data to be transferred is + implied by count. + + +SYNOPSIS + + +ssize_t write(int fd, const void ⋆buf, size_t + count); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +void *buf + +Pointer to the buffer containing the Transport Stream. + + +size_t count + +Size of buf. + + +ERRORS + + +EWOULDBLOCK + +No data was written. This + might happen if O_NONBLOCK was specified and there + is no more buffer space available (if O_NONBLOCK is + not specified the function will block until buffer space is + available). + + +EBUSY + +This error code indicates that there are conflicting + requests. The corresponding demux device is setup to + receive data from the front- end. Make sure that these + filters are stopped and that the filters with input set to + DMX_IN_DVR are started. + + +EBADF + +fd is not a valid open file descriptor. + + +
+ +
+DMX_START +DESCRIPTION + + +This ioctl call is used to start the actual filtering operation defined via the ioctl + calls DMX_SET_FILTER or DMX_SET_PES_FILTER. + + +SYNOPSIS + + +int ioctl( int fd, int request = DMX_START); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals DMX_START for this command. + + +ERRORS + + +EBADF + +fd is not a valid file descriptor. + + +EINVAL + +Invalid argument, i.e. no filtering parameters provided via + the DMX_SET_FILTER or DMX_SET_PES_FILTER + functions. + + +EBUSY + +This error code indicates that there are conflicting + requests. There are active filters filtering data from + another input source. Make sure that these filters are + stopped before starting this filter. + + +
+ +
+DMX_STOP +DESCRIPTION + + +This ioctl call is used to stop the actual filtering operation defined via the + ioctl calls DMX_SET_FILTER or DMX_SET_PES_FILTER and started via + the DMX_START command. + + +SYNOPSIS + + +int ioctl( int fd, int request = DMX_STOP); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals DMX_STOP for this command. + + +ERRORS + + +EBADF + +fd is not a valid file descriptor. + + +
+ +
+DMX_SET_FILTER +DESCRIPTION + + +This ioctl call sets up a filter according to the filter and mask parameters + provided. A timeout may be defined stating number of seconds to wait for a + section to be loaded. A value of 0 means that no timeout should be applied. + Finally there is a flag field where it is possible to state whether a section should + be CRC-checked, whether the filter should be a ”one-shot” filter, i.e. if the + filtering operation should be stopped after the first section is received, and + whether the filtering operation should be started immediately (without waiting + for a DMX_START ioctl call). If a filter was previously set-up, this filter will + be canceled, and the receive buffer will be flushed. + + +SYNOPSIS + + +int ioctl( int fd, int request = DMX_SET_FILTER, + struct dmx_sct_filter_params ⋆params); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals DMX_SET_FILTER for this command. + + +struct + dmx_sct_filter_params + *params + +Pointer to structure containing filter parameters. + + +ERRORS + + +EBADF + +fd is not a valid file descriptor. + + +EINVAL + +Invalid argument. + + +
+ +
+DMX_SET_PES_FILTER +DESCRIPTION + + +This ioctl call sets up a PES filter according to the parameters provided. By a + PES filter is meant a filter that is based just on the packet identifier (PID), i.e. + no PES header or payload filtering capability is supported. + + +The transport stream destination for the filtered output may be set. Also the + PES type may be stated in order to be able to e.g. direct a video stream directly + to the video decoder. Finally there is a flag field where it is possible to state + whether the filtering operation should be started immediately (without waiting + for a DMX_START ioctl call). If a filter was previously set-up, this filter will + be cancelled, and the receive buffer will be flushed. + + +SYNOPSIS + + +int ioctl( int fd, int request = DMX_SET_PES_FILTER, + struct dmx_pes_filter_params ⋆params); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals DMX_SET_PES_FILTER for this command. + + +struct + dmx_pes_filter_params + *params + +Pointer to structure containing filter parameters. + + +ERRORS + + +EBADF + +fd is not a valid file descriptor. + + +EINVAL + +Invalid argument. + + +EBUSY + +This error code indicates that there are conflicting + requests. There are active filters filtering data from + another input source. Make sure that these filters are + stopped before starting this filter. + + +
+ +
+DMX_SET_BUFFER_SIZE +DESCRIPTION + + +This ioctl call is used to set the size of the circular buffer used for filtered data. + The default size is two maximum sized sections, i.e. if this function is not called + a buffer size of 2 * 4096 bytes will be used. + + +SYNOPSIS + + +int ioctl( int fd, int request = + DMX_SET_BUFFER_SIZE, unsigned long size); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals DMX_SET_BUFFER_SIZE for this command. + + +unsigned long size + +Size of circular buffer. + + +ERRORS + + +EBADF + +fd is not a valid file descriptor. + + +ENOMEM + +The driver was not able to allocate a buffer of the + requested size. + + +
+ +
+DMX_GET_EVENT +DESCRIPTION + + +This ioctl call returns an event if available. If an event is not available, + the behavior depends on whether the device is in blocking or non-blocking + mode. In the latter case, the call fails immediately with errno set to + EWOULDBLOCK. In the former case, the call blocks until an event becomes + available. + + +The standard Linux poll() and/or select() system calls can be used with the + device file descriptor to watch for new events. For select(), the file descriptor + should be included in the exceptfds argument, and for poll(), POLLPRI should + be specified as the wake-up condition. Only the latest event for each filter is + saved. + + +SYNOPSIS + + +int ioctl( int fd, int request = DMX_GET_EVENT, + struct dmx_event ⋆ev); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals DMX_GET_EVENT for this command. + + +struct dmx_event *ev + +Pointer to the location where the event is to be stored. + + +ERRORS + + +EBADF + +fd is not a valid file descriptor. + + +EFAULT + +ev points to an invalid address. + + +EWOULDBLOCK + +There is no event pending, and the device is in + non-blocking mode. + + +
+ +
+DMX_GET_STC +DESCRIPTION + + +This ioctl call returns the current value of the system time counter (which is driven + by a PES filter of type DMX_PES_PCR). Some hardware supports more than one + STC, so you must specify which one by setting the num field of stc before the ioctl + (range 0...n). The result is returned in form of a ratio with a 64 bit numerator + and a 32 bit denominator, so the real 90kHz STC value is stc->stc / + stc->base + . + + +SYNOPSIS + + +int ioctl( int fd, int request = DMX_GET_STC, struct + dmx_stc ⋆stc); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals DMX_GET_STC for this command. + + +struct dmx_stc *stc + +Pointer to the location where the stc is to be stored. + + +ERRORS + + +EBADF + +fd is not a valid file descriptor. + + +EFAULT + +stc points to an invalid address. + + +EINVAL + +Invalid stc number. + + +
diff --git a/Documentation/DocBook/dvb/dvbapi.xml b/Documentation/DocBook/dvb/dvbapi.xml new file mode 100644 index 000000000000..4fc5b23470a3 --- /dev/null +++ b/Documentation/DocBook/dvb/dvbapi.xml @@ -0,0 +1,87 @@ + + + +Ralph +Metzler +J. K. +
rjkm@metzlerbros.de
 + + +Marcus +Metzler +O. C. +
rjkm@metzlerbros.de
 + + +Mauro +Chehab +Carvalho +
mchehab@redhat.com
 +Ported document to Docbook XML. + + + + 2002 + 2003 + 2009 + Convergence GmbH + + + + + +2.0.1 +2009-09-16 +mcc + +Added ISDB-T test originally written by Patrick Boettcher + + + +2.0.0 +2009-09-06 +mcc +Conversion from LaTex to DocBook XML. The + contents is the same as the original LaTex version. + + +1.0.0 +2003-07-24 +rjkm +Initial revision on LaTEX. + + + + + +LINUX DVB API +Version 3 + + + &sub-intro; + + + &sub-frontend; + + + &sub-demux; + + + &sub-video; + + + &sub-audio; + + + &sub-ca; + + + &sub-net; + + + &sub-kdapi; + + + &sub-examples; + + diff --git a/Documentation/DocBook/dvb/dvbstb.pdf b/Documentation/DocBook/dvb/dvbstb.pdf new file mode 100644 index 000000000000..0fa75d90c3eb Binary files /dev/null and b/Documentation/DocBook/dvb/dvbstb.pdf differ diff --git a/Documentation/DocBook/dvb/dvbstb.png b/Documentation/DocBook/dvb/dvbstb.png new file mode 100644 index 000000000000..9b8f372e7afd Binary files /dev/null and b/Documentation/DocBook/dvb/dvbstb.png differ diff --git a/Documentation/DocBook/dvb/examples.xml b/Documentation/DocBook/dvb/examples.xml new file mode 100644 index 000000000000..f037e568eb6e --- /dev/null +++ b/Documentation/DocBook/dvb/examples.xml @@ -0,0 +1,365 @@ +Examples +In this section we would like to present some examples for using the DVB API. + +Maintainer note: This section is out of date. Please refer to the sample programs packaged +with the driver distribution from . + + +
+Tuning +We will start with a generic tuning subroutine that uses the frontend and SEC, as well as +the demux devices. The example is given for QPSK tuners, but can easily be adjusted for +QAM. + + + #include <sys/ioctl.h> + #include <stdio.h> + #include <stdint.h> + #include <sys/types.h> + #include <sys/stat.h> + #include <fcntl.h> + #include <time.h> + #include <unistd.h> + + #include <linux/dvb/dmx.h> + #include <linux/dvb/frontend.h> + #include <linux/dvb/sec.h> + #include <sys/poll.h> + + #define DMX "/dev/dvb/adapter0/demux1" + #define FRONT "/dev/dvb/adapter0/frontend1" + #define SEC "/dev/dvb/adapter0/sec1" + + /⋆ routine for checking if we have a signal and other status information⋆/ + int FEReadStatus(int fd, fe_status_t ⋆stat) + { + int ans; + + if ( (ans = ioctl(fd,FE_READ_STATUS,stat) < 0)){ + perror("FE READ STATUS: "); + return -1; + } + + if (⋆stat & FE_HAS_POWER) + printf("FE HAS POWER\n"); + + if (⋆stat & FE_HAS_SIGNAL) + printf("FE HAS SIGNAL\n"); + + if (⋆stat & FE_SPECTRUM_INV) + printf("SPEKTRUM INV\n"); + + return 0; + } + + + /⋆ tune qpsk ⋆/ + /⋆ freq: frequency of transponder ⋆/ + /⋆ vpid, apid, tpid: PIDs of video, audio and teletext TS packets ⋆/ + /⋆ diseqc: DiSEqC address of the used LNB ⋆/ + /⋆ pol: Polarisation ⋆/ + /⋆ srate: Symbol Rate ⋆/ + /⋆ fec. FEC ⋆/ + /⋆ lnb_lof1: local frequency of lower LNB band ⋆/ + /⋆ lnb_lof2: local frequency of upper LNB band ⋆/ + /⋆ lnb_slof: switch frequency of LNB ⋆/ + + int set_qpsk_channel(int freq, int vpid, int apid, int tpid, + int diseqc, int pol, int srate, int fec, int lnb_lof1, + int lnb_lof2, int lnb_slof) + { + struct secCommand scmd; + struct secCmdSequence scmds; + struct dmx_pes_filter_params pesFilterParams; + FrontendParameters frp; + struct pollfd pfd[1]; + FrontendEvent event; + int demux1, demux2, demux3, front; + + frequency = (uint32_t) freq; + symbolrate = (uint32_t) srate; + + if((front = open(FRONT,O_RDWR)) < 0){ + perror("FRONTEND DEVICE: "); + return -1; + } + + if((sec = open(SEC,O_RDWR)) < 0){ + perror("SEC DEVICE: "); + return -1; + } + + if (demux1 < 0){ + if ((demux1=open(DMX, O_RDWR|O_NONBLOCK)) + < 0){ + perror("DEMUX DEVICE: "); + return -1; + } + } + + if (demux2 < 0){ + if ((demux2=open(DMX, O_RDWR|O_NONBLOCK)) + < 0){ + perror("DEMUX DEVICE: "); + return -1; + } + } + + if (demux3 < 0){ + if ((demux3=open(DMX, O_RDWR|O_NONBLOCK)) + < 0){ + perror("DEMUX DEVICE: "); + return -1; + } + } + + if (freq < lnb_slof) { + frp.Frequency = (freq - lnb_lof1); + scmds.continuousTone = SEC_TONE_OFF; + } else { + frp.Frequency = (freq - lnb_lof2); + scmds.continuousTone = SEC_TONE_ON; + } + frp.Inversion = INVERSION_AUTO; + if (pol) scmds.voltage = SEC_VOLTAGE_18; + else scmds.voltage = SEC_VOLTAGE_13; + + scmd.type=0; + scmd.u.diseqc.addr=0x10; + scmd.u.diseqc.cmd=0x38; + scmd.u.diseqc.numParams=1; + scmd.u.diseqc.params[0] = 0xF0 | ((diseqc ⋆ 4) & 0x0F) | + (scmds.continuousTone == SEC_TONE_ON ? 1 : 0) | + (scmds.voltage==SEC_VOLTAGE_18 ? 2 : 0); + + scmds.miniCommand=SEC_MINI_NONE; + scmds.numCommands=1; + scmds.commands=&scmd; + if (ioctl(sec, SEC_SEND_SEQUENCE, &scmds) < 0){ + perror("SEC SEND: "); + return -1; + } + + if (ioctl(sec, SEC_SEND_SEQUENCE, &scmds) < 0){ + perror("SEC SEND: "); + return -1; + } + + frp.u.qpsk.SymbolRate = srate; + frp.u.qpsk.FEC_inner = fec; + + if (ioctl(front, FE_SET_FRONTEND, &frp) < 0){ + perror("QPSK TUNE: "); + return -1; + } + + pfd[0].fd = front; + pfd[0].events = POLLIN; + + if (poll(pfd,1,3000)){ + if (pfd[0].revents & POLLIN){ + printf("Getting QPSK event\n"); + if ( ioctl(front, FE_GET_EVENT, &event) + + == -EOVERFLOW){ + perror("qpsk get event"); + return -1; + } + printf("Received "); + switch(event.type){ + case FE_UNEXPECTED_EV: + printf("unexpected event\n"); + return -1; + case FE_FAILURE_EV: + printf("failure event\n"); + return -1; + + case FE_COMPLETION_EV: + printf("completion event\n"); + } + } + } + + + pesFilterParams.pid = vpid; + pesFilterParams.input = DMX_IN_FRONTEND; + pesFilterParams.output = DMX_OUT_DECODER; + pesFilterParams.pes_type = DMX_PES_VIDEO; + pesFilterParams.flags = DMX_IMMEDIATE_START; + if (ioctl(demux1, DMX_SET_PES_FILTER, &pesFilterParams) < 0){ + perror("set_vpid"); + return -1; + } + + pesFilterParams.pid = apid; + pesFilterParams.input = DMX_IN_FRONTEND; + pesFilterParams.output = DMX_OUT_DECODER; + pesFilterParams.pes_type = DMX_PES_AUDIO; + pesFilterParams.flags = DMX_IMMEDIATE_START; + if (ioctl(demux2, DMX_SET_PES_FILTER, &pesFilterParams) < 0){ + perror("set_apid"); + return -1; + } + + pesFilterParams.pid = tpid; + pesFilterParams.input = DMX_IN_FRONTEND; + pesFilterParams.output = DMX_OUT_DECODER; + pesFilterParams.pes_type = DMX_PES_TELETEXT; + pesFilterParams.flags = DMX_IMMEDIATE_START; + if (ioctl(demux3, DMX_SET_PES_FILTER, &pesFilterParams) < 0){ + perror("set_tpid"); + return -1; + } + + return has_signal(fds); + } + + +The program assumes that you are using a universal LNB and a standard DiSEqC +switch with up to 4 addresses. Of course, you could build in some more checking if +tuning was successful and maybe try to repeat the tuning process. Depending on the +external hardware, i.e. LNB and DiSEqC switch, and weather conditions this may be +necessary. + +
+ +
+The DVR device +The following program code shows how to use the DVR device for recording. + + + #include <sys/ioctl.h> + #include <stdio.h> + #include <stdint.h> + #include <sys/types.h> + #include <sys/stat.h> + #include <fcntl.h> + #include <time.h> + #include <unistd.h> + + #include <linux/dvb/dmx.h> + #include <linux/dvb/video.h> + #include <sys/poll.h> + #define DVR "/dev/dvb/adapter0/dvr1" + #define AUDIO "/dev/dvb/adapter0/audio1" + #define VIDEO "/dev/dvb/adapter0/video1" + + #define BUFFY (188⋆20) + #define MAX_LENGTH (1024⋆1024⋆5) /⋆ record 5MB ⋆/ + + + /⋆ switch the demuxes to recording, assuming the transponder is tuned ⋆/ + + /⋆ demux1, demux2: file descriptor of video and audio filters ⋆/ + /⋆ vpid, apid: PIDs of video and audio channels ⋆/ + + int switch_to_record(int demux1, int demux2, uint16_t vpid, uint16_t apid) + { + struct dmx_pes_filter_params pesFilterParams; + + if (demux1 < 0){ + if ((demux1=open(DMX, O_RDWR|O_NONBLOCK)) + < 0){ + perror("DEMUX DEVICE: "); + return -1; + } + } + + if (demux2 < 0){ + if ((demux2=open(DMX, O_RDWR|O_NONBLOCK)) + < 0){ + perror("DEMUX DEVICE: "); + return -1; + } + } + + pesFilterParams.pid = vpid; + pesFilterParams.input = DMX_IN_FRONTEND; + pesFilterParams.output = DMX_OUT_TS_TAP; + pesFilterParams.pes_type = DMX_PES_VIDEO; + pesFilterParams.flags = DMX_IMMEDIATE_START; + if (ioctl(demux1, DMX_SET_PES_FILTER, &pesFilterParams) < 0){ + perror("DEMUX DEVICE"); + return -1; + } + pesFilterParams.pid = apid; + pesFilterParams.input = DMX_IN_FRONTEND; + pesFilterParams.output = DMX_OUT_TS_TAP; + pesFilterParams.pes_type = DMX_PES_AUDIO; + pesFilterParams.flags = DMX_IMMEDIATE_START; + if (ioctl(demux2, DMX_SET_PES_FILTER, &pesFilterParams) < 0){ + perror("DEMUX DEVICE"); + return -1; + } + return 0; + } + + /⋆ start recording MAX_LENGTH , assuming the transponder is tuned ⋆/ + + /⋆ demux1, demux2: file descriptor of video and audio filters ⋆/ + /⋆ vpid, apid: PIDs of video and audio channels ⋆/ + int record_dvr(int demux1, int demux2, uint16_t vpid, uint16_t apid) + { + int i; + int len; + int written; + uint8_t buf[BUFFY]; + uint64_t length; + struct pollfd pfd[1]; + int dvr, dvr_out; + + /⋆ open dvr device ⋆/ + if ((dvr = open(DVR, O_RDONLY|O_NONBLOCK)) < 0){ + perror("DVR DEVICE"); + return -1; + } + + /⋆ switch video and audio demuxes to dvr ⋆/ + printf ("Switching dvr on\n"); + i = switch_to_record(demux1, demux2, vpid, apid); + printf("finished: "); + + printf("Recording %2.0f MB of test file in TS format\n", + MAX_LENGTH/(1024.0⋆1024.0)); + length = 0; + + /⋆ open output file ⋆/ + if ((dvr_out = open(DVR_FILE,O_WRONLY|O_CREAT + |O_TRUNC, S_IRUSR|S_IWUSR + |S_IRGRP|S_IWGRP|S_IROTH| + S_IWOTH)) < 0){ + perror("Can't open file for dvr test"); + return -1; + } + + pfd[0].fd = dvr; + pfd[0].events = POLLIN; + + /⋆ poll for dvr data and write to file ⋆/ + while (length < MAX_LENGTH ) { + if (poll(pfd,1,1)){ + if (pfd[0].revents & POLLIN){ + len = read(dvr, buf, BUFFY); + if (len < 0){ + perror("recording"); + return -1; + } + if (len > 0){ + written = 0; + while (written < len) + written += + write (dvr_out, + buf, len); + length += len; + printf("written %2.0f MB\r", + length/1024./1024.); + } + } + } + } + return 0; + } + + + +
diff --git a/Documentation/DocBook/dvb/frontend.xml b/Documentation/DocBook/dvb/frontend.xml new file mode 100644 index 000000000000..9d89a7b94fd5 --- /dev/null +++ b/Documentation/DocBook/dvb/frontend.xml @@ -0,0 +1,1766 @@ +DVB Frontend API + +The DVB frontend device controls the tuner and DVB demodulator +hardware. It can be accessed through /dev/dvb/adapter0/frontend0. Data types and and +ioctl definitions can be accessed by including linux/dvb/frontend.h in your application. + +DVB frontends come in three varieties: DVB-S (satellite), DVB-C +(cable) and DVB-T (terrestrial). Transmission via the internet (DVB-IP) +is not yet handled by this API but a future extension is possible. For +DVB-S the frontend device also supports satellite equipment control +(SEC) via DiSEqC and V-SEC protocols. The DiSEqC (digital SEC) +specification is available from +Eutelsat. + +Note that the DVB API may also be used for MPEG decoder-only PCI +cards, in which case there exists no frontend device. + +
+Frontend Data Types + +
+frontend type + +For historical reasons frontend types are named after the type of modulation used in +transmission. + + typedef enum fe_type { + FE_QPSK, /⋆ DVB-S ⋆/ + FE_QAM, /⋆ DVB-C ⋆/ + FE_OFDM /⋆ DVB-T ⋆/ + } fe_type_t; + + +
+ +
+frontend capabilities + +Capabilities describe what a frontend can do. Some capabilities can only be supported for +a specific frontend type. + + typedef enum fe_caps { + FE_IS_STUPID = 0, + FE_CAN_INVERSION_AUTO = 0x1, + FE_CAN_FEC_1_2 = 0x2, + FE_CAN_FEC_2_3 = 0x4, + FE_CAN_FEC_3_4 = 0x8, + FE_CAN_FEC_4_5 = 0x10, + FE_CAN_FEC_5_6 = 0x20, + FE_CAN_FEC_6_7 = 0x40, + FE_CAN_FEC_7_8 = 0x80, + FE_CAN_FEC_8_9 = 0x100, + FE_CAN_FEC_AUTO = 0x200, + FE_CAN_QPSK = 0x400, + FE_CAN_QAM_16 = 0x800, + FE_CAN_QAM_32 = 0x1000, + FE_CAN_QAM_64 = 0x2000, + FE_CAN_QAM_128 = 0x4000, + FE_CAN_QAM_256 = 0x8000, + FE_CAN_QAM_AUTO = 0x10000, + FE_CAN_TRANSMISSION_MODE_AUTO = 0x20000, + FE_CAN_BANDWIDTH_AUTO = 0x40000, + FE_CAN_GUARD_INTERVAL_AUTO = 0x80000, + FE_CAN_HIERARCHY_AUTO = 0x100000, + FE_CAN_MUTE_TS = 0x80000000, + FE_CAN_CLEAN_SETUP = 0x40000000 + } fe_caps_t; + +
+ +
+frontend information + +Information about the frontend ca be queried with FE_GET_INFO. + + + struct dvb_frontend_info { + char name[128]; + fe_type_t type; + uint32_t frequency_min; + uint32_t frequency_max; + uint32_t frequency_stepsize; + uint32_t frequency_tolerance; + uint32_t symbol_rate_min; + uint32_t symbol_rate_max; + uint32_t symbol_rate_tolerance; /⋆ ppm ⋆/ + uint32_t notifier_delay; /⋆ ms ⋆/ + fe_caps_t caps; + }; + +
+ +
+diseqc master command + +A message sent from the frontend to DiSEqC capable equipment. + + struct dvb_diseqc_master_cmd { + uint8_t msg [6]; /⋆ { framing, address, command, data[3] } ⋆/ + uint8_t msg_len; /⋆ valid values are 3...6 ⋆/ + }; + +
+
+diseqc slave reply + +A reply to the frontend from DiSEqC 2.0 capable equipment. + + struct dvb_diseqc_slave_reply { + uint8_t msg [4]; /⋆ { framing, data [3] } ⋆/ + uint8_t msg_len; /⋆ valid values are 0...4, 0 means no msg ⋆/ + int timeout; /⋆ return from ioctl after timeout ms with ⋆/ + }; /⋆ errorcode when no message was received ⋆/ + +
+ +
+diseqc slave reply +The voltage is usually used with non-DiSEqC capable LNBs to switch the polarzation +(horizontal/vertical). When using DiSEqC epuipment this voltage has to be switched +consistently to the DiSEqC commands as described in the DiSEqC spec. + + typedef enum fe_sec_voltage { + SEC_VOLTAGE_13, + SEC_VOLTAGE_18 + } fe_sec_voltage_t; + +
+ +
+SEC continuous tone + +The continous 22KHz tone is usually used with non-DiSEqC capable LNBs to switch the +high/low band of a dual-band LNB. When using DiSEqC epuipment this voltage has to +be switched consistently to the DiSEqC commands as described in the DiSEqC +spec. + + typedef enum fe_sec_tone_mode { + SEC_TONE_ON, + SEC_TONE_OFF + } fe_sec_tone_mode_t; + +
+ +
+SEC tone burst + +The 22KHz tone burst is usually used with non-DiSEqC capable switches to select +between two connected LNBs/satellites. When using DiSEqC epuipment this voltage has to +be switched consistently to the DiSEqC commands as described in the DiSEqC +spec. + + typedef enum fe_sec_mini_cmd { + SEC_MINI_A, + SEC_MINI_B + } fe_sec_mini_cmd_t; + + + +
+ +
+frontend status +Several functions of the frontend device use the fe_status data type defined +by + + typedef enum fe_status { + FE_HAS_SIGNAL = 0x01, /⋆ found something above the noise level ⋆/ + FE_HAS_CARRIER = 0x02, /⋆ found a DVB signal ⋆/ + FE_HAS_VITERBI = 0x04, /⋆ FEC is stable ⋆/ + FE_HAS_SYNC = 0x08, /⋆ found sync bytes ⋆/ + FE_HAS_LOCK = 0x10, /⋆ everything's working... ⋆/ + FE_TIMEDOUT = 0x20, /⋆ no lock within the last ~2 seconds ⋆/ + FE_REINIT = 0x40 /⋆ frontend was reinitialized, ⋆/ + } fe_status_t; /⋆ application is recommned to reset ⋆/ + +to indicate the current state and/or state changes of the frontend hardware. + + +
+ +
+frontend parameters +The kind of parameters passed to the frontend device for tuning depend on +the kind of hardware you are using. All kinds of parameters are combined as an +union in the FrontendParameters structure: + + struct dvb_frontend_parameters { + uint32_t frequency; /⋆ (absolute) frequency in Hz for QAM/OFDM ⋆/ + /⋆ intermediate frequency in kHz for QPSK ⋆/ + fe_spectral_inversion_t inversion; + union { + struct dvb_qpsk_parameters qpsk; + struct dvb_qam_parameters qam; + struct dvb_ofdm_parameters ofdm; + } u; + }; + +For satellite QPSK frontends you have to use the QPSKParameters member defined by + + struct dvb_qpsk_parameters { + uint32_t symbol_rate; /⋆ symbol rate in Symbols per second ⋆/ + fe_code_rate_t fec_inner; /⋆ forward error correction (see above) ⋆/ + }; + +for cable QAM frontend you use the QAMParameters structure + + struct dvb_qam_parameters { + uint32_t symbol_rate; /⋆ symbol rate in Symbols per second ⋆/ + fe_code_rate_t fec_inner; /⋆ forward error correction (see above) ⋆/ + fe_modulation_t modulation; /⋆ modulation type (see above) ⋆/ + }; + +DVB-T frontends are supported by the OFDMParamters structure + + + struct dvb_ofdm_parameters { + fe_bandwidth_t bandwidth; + fe_code_rate_t code_rate_HP; /⋆ high priority stream code rate ⋆/ + fe_code_rate_t code_rate_LP; /⋆ low priority stream code rate ⋆/ + fe_modulation_t constellation; /⋆ modulation type (see above) ⋆/ + fe_transmit_mode_t transmission_mode; + fe_guard_interval_t guard_interval; + fe_hierarchy_t hierarchy_information; + }; + +In the case of QPSK frontends the Frequency field specifies the intermediate +frequency, i.e. the offset which is effectively added to the local oscillator frequency (LOF) of +the LNB. The intermediate frequency has to be specified in units of kHz. For QAM and +OFDM frontends the Frequency specifies the absolute frequency and is given in +Hz. + +The Inversion field can take one of these values: + + + typedef enum fe_spectral_inversion { + INVERSION_OFF, + INVERSION_ON, + INVERSION_AUTO + } fe_spectral_inversion_t; + +It indicates if spectral inversion should be presumed or not. In the automatic setting +(INVERSION_AUTO) the hardware will try to figure out the correct setting by +itself. + +The possible values for the FEC_inner field are + + + typedef enum fe_code_rate { + FEC_NONE = 0, + FEC_1_2, + FEC_2_3, + FEC_3_4, + FEC_4_5, + FEC_5_6, + FEC_6_7, + FEC_7_8, + FEC_8_9, + FEC_AUTO + } fe_code_rate_t; + +which correspond to error correction rates of 1/2, 2/3, etc., no error correction or auto +detection. + +For cable and terrestrial frontends (QAM and OFDM) one also has to specify the quadrature +modulation mode which can be one of the following: + + + typedef enum fe_modulation { + QPSK, + QAM_16, + QAM_32, + QAM_64, + QAM_128, + QAM_256, + QAM_AUTO + } fe_modulation_t; + +Finally, there are several more parameters for OFDM: + + + typedef enum fe_transmit_mode { + TRANSMISSION_MODE_2K, + TRANSMISSION_MODE_8K, + TRANSMISSION_MODE_AUTO + } fe_transmit_mode_t; + + + typedef enum fe_bandwidth { + BANDWIDTH_8_MHZ, + BANDWIDTH_7_MHZ, + BANDWIDTH_6_MHZ, + BANDWIDTH_AUTO + } fe_bandwidth_t; + + + typedef enum fe_guard_interval { + GUARD_INTERVAL_1_32, + GUARD_INTERVAL_1_16, + GUARD_INTERVAL_1_8, + GUARD_INTERVAL_1_4, + GUARD_INTERVAL_AUTO + } fe_guard_interval_t; + + + typedef enum fe_hierarchy { + HIERARCHY_NONE, + HIERARCHY_1, + HIERARCHY_2, + HIERARCHY_4, + HIERARCHY_AUTO + } fe_hierarchy_t; + + +
+ +
+frontend events + + struct dvb_frontend_event { + fe_status_t status; + struct dvb_frontend_parameters parameters; + }; + +
+
+ + +
+Frontend Function Calls + +
+open() +DESCRIPTION + + +This system call opens a named frontend device (/dev/dvb/adapter0/frontend0) + for subsequent use. Usually the first thing to do after a successful open is to + find out the frontend type with FE_GET_INFO. +The device can be opened in read-only mode, which only allows monitoring of + device status and statistics, or read/write mode, which allows any kind of use + (e.g. performing tuning operations.) + +In a system with multiple front-ends, it is usually the case that multiple devices + cannot be open in read/write mode simultaneously. As long as a front-end + device is opened in read/write mode, other open() calls in read/write mode will + either fail or block, depending on whether non-blocking or blocking mode was + specified. A front-end device opened in blocking mode can later be put into + non-blocking mode (and vice versa) using the F_SETFL command of the fcntl + system call. This is a standard system call, documented in the Linux manual + page for fcntl. When an open() call has succeeded, the device will be ready + for use in the specified mode. This implies that the corresponding hardware is + powered up, and that other front-ends may have been powered down to make + that possible. + + + +SYNOPSIS + +int open(const char ⋆deviceName, int flags); + + +PARAMETERS + + +const char + *deviceName + +Name of specific video device. + + +int flags + +A bit-wise OR of the following flags: + + + +O_RDONLY read-only access + + + +O_RDWR read/write access + + + +O_NONBLOCK open in non-blocking mode + + + +(blocking mode is the default) + + +ERRORS + + +ENODEV + +Device driver not loaded/available. + + +EINTERNAL + +Internal error. + + +EBUSY + +Device or resource busy. + + +EINVAL + +Invalid argument. + + +
+ +
+close() +DESCRIPTION + + +This system call closes a previously opened front-end device. After closing + a front-end device, its corresponding hardware might be powered down + automatically. + + +SYNOPSIS + + +int close(int fd); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +
+ +
+FE_READ_STATUS +DESCRIPTION + + +This ioctl call returns status information about the front-end. This call only + requires read-only access to the device. + + +SYNOPSIS + + +int ioctl(int fd, int request = FE_READ_STATUS, + fe_status_t ⋆status); + + +PARAMETERS + + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_READ_STATUS for this command. + + +struct fe_status_t + *status + +Points to the location where the front-end status word is + to be stored. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EFAULT + +status points to invalid address. + + +
+ +
+FE_READ_BER +DESCRIPTION + + +This ioctl call returns the bit error rate for the signal currently + received/demodulated by the front-end. For this command, read-only access to + the device is sufficient. + + +SYNOPSIS + + +int ioctl(int fd, int request = FE_READ_BER, + uint32_t ⋆ber); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_READ_BER for this command. + + +uint32_t *ber + +The bit error rate is stored into *ber. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EFAULT + +ber points to invalid address. + + +ENOSIGNAL + +There is no signal, thus no meaningful bit error rate. Also + returned if the front-end is not turned on. + + +ENOSYS + +Function not available for this device. + + +
+ +
+FE_READ_SNR + +DESCRIPTION + + +This ioctl call returns the signal-to-noise ratio for the signal currently received + by the front-end. For this command, read-only access to the device is sufficient. + + +SYNOPSIS + + +int ioctl(int fd, int request = FE_READ_SNR, int16_t + ⋆snr); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_READ_SNR for this command. + + +int16_t *snr + +The signal-to-noise ratio is stored into *snr. + + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EFAULT + +snr points to invalid address. + + +ENOSIGNAL + +There is no signal, thus no meaningful signal strength + value. Also returned if front-end is not turned on. + + +ENOSYS + +Function not available for this device. + + +
+ +
+FE_READ_SIGNAL_STRENGTH +DESCRIPTION + + +This ioctl call returns the signal strength value for the signal currently received + by the front-end. For this command, read-only access to the device is sufficient. + + +SYNOPSIS + + +int ioctl( int fd, int request = + FE_READ_SIGNAL_STRENGTH, int16_t ⋆strength); + + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_READ_SIGNAL_STRENGTH for this + command. + + +int16_t *strength + +The signal strength value is stored into *strength. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EFAULT + +status points to invalid address. + + +ENOSIGNAL + +There is no signal, thus no meaningful signal strength + value. Also returned if front-end is not turned on. + + +ENOSYS + +Function not available for this device. + + +
+ +
+FE_READ_UNCORRECTED_BLOCKS +DESCRIPTION + + +This ioctl call returns the number of uncorrected blocks detected by the device + driver during its lifetime. For meaningful measurements, the increment in block + count during a specific time interval should be calculated. For this command, + read-only access to the device is sufficient. + + +Note that the counter will wrap to zero after its maximum count has been + reached. + + +SYNOPSIS + + +int ioctl( int fd, int request = + FE_READ_UNCORRECTED_BLOCKS, uint32_t ⋆ublocks); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_READ_UNCORRECTED_BLOCKS for this + command. + + +uint32_t *ublocks + +The total number of uncorrected blocks seen by the driver + so far. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EFAULT + +ublocks points to invalid address. + + +ENOSYS + +Function not available for this device. + + +
+ +
+FE_SET_FRONTEND +DESCRIPTION + + +This ioctl call starts a tuning operation using specified parameters. The result + of this call will be successful if the parameters were valid and the tuning could + be initiated. The result of the tuning operation in itself, however, will arrive + asynchronously as an event (see documentation for FE_GET_EVENT and + FrontendEvent.) If a new FE_SET_FRONTEND operation is initiated before + the previous one was completed, the previous operation will be aborted in favor + of the new one. This command requires read/write access to the device. + + + +SYNOPSIS + + +int ioctl(int fd, int request = FE_SET_FRONTEND, + struct dvb_frontend_parameters ⋆p); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_SET_FRONTEND for this command. + + +struct + dvb_frontend_parameters + *p + +Points to parameters for tuning operation. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EFAULT + +p points to invalid address. + + +EINVAL + +Maximum supported symbol rate reached. + + +
+ +
+FE_GET_FRONTEND +DESCRIPTION + + +This ioctl call queries the currently effective frontend parameters. For this + command, read-only access to the device is sufficient. + + + +SYNOPSIS + + +int ioctl(int fd, int request = FE_GET_FRONTEND, + struct dvb_frontend_parameters ⋆p); + + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_SET_FRONTEND for this command. + + +struct + dvb_frontend_parameters + *p + +Points to parameters for tuning operation. + + + +ERRORS + + + +EBADF + +fd is not a valid open file descriptor. + + +EFAULT + +p points to invalid address. + + +EINVAL + +Maximum supported symbol rate reached. + + + +
+ +
+FE_GET_EVENT +DESCRIPTION + + +This ioctl call returns a frontend event if available. If an event is not + available, the behavior depends on whether the device is in blocking or + non-blocking mode. In the latter case, the call fails immediately with errno + set to EWOULDBLOCK. In the former case, the call blocks until an event + becomes available. + + +The standard Linux poll() and/or select() system calls can be used with the + device file descriptor to watch for new events. For select(), the file descriptor + should be included in the exceptfds argument, and for poll(), POLLPRI should + be specified as the wake-up condition. Since the event queue allocated is + rather small (room for 8 events), the queue must be serviced regularly to avoid + overflow. If an overflow happens, the oldest event is discarded from the queue, + and an error (EOVERFLOW) occurs the next time the queue is read. After + reporting the error condition in this fashion, subsequent FE_GET_EVENT + calls will return events from the queue as usual. + + +For the sake of implementation simplicity, this command requires read/write + access to the device. + + + +SYNOPSIS + + +int ioctl(int fd, int request = QPSK_GET_EVENT, + struct dvb_frontend_event ⋆ev); + + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_GET_EVENT for this command. + + +struct + dvb_frontend_event + *ev + +Points to the location where the event, + + + +if any, is to be stored. + + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EFAULT + +ev points to invalid address. + + +EWOULDBLOCK + +There is no event pending, and the device is in + non-blocking mode. + + +EOVERFLOW + + + + +Overflow in event queue - one or more events were lost. + + +
+ +
+FE_GET_INFO +DESCRIPTION + + +This ioctl call returns information about the front-end. This call only requires + read-only access to the device. + + +SYNOPSIS + + + + int ioctl(int fd, int request = FE_GET_INFO, struct + dvb_frontend_info ⋆info); + + +PARAMETERS + + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_GET_INFO for this command. + + +struct + dvb_frontend_info + *info + +Points to the location where the front-end information is + to be stored. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EFAULT + +info points to invalid address. + + +
+ +
+FE_DISEQC_RESET_OVERLOAD +DESCRIPTION + + +If the bus has been automatically powered off due to power overload, this ioctl + call restores the power to the bus. The call requires read/write access to the + device. This call has no effect if the device is manually powered off. Not all + DVB adapters support this ioctl. + + + +SYNOPSIS + + +int ioctl(int fd, int request = + FE_DISEQC_RESET_OVERLOAD); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_DISEQC_RESET_OVERLOAD for this + command. + + + +ERRORS + + +EBADF + +fd is not a valid file descriptor. + + +EPERM + +Permission denied (needs read/write access). + + +EINTERNAL + +Internal error in the device driver. + + +
+ +
+FE_DISEQC_SEND_MASTER_CMD +DESCRIPTION + + +This ioctl call is used to send a a DiSEqC command. + + +SYNOPSIS + + +int ioctl(int fd, int request = + FE_DISEQC_SEND_MASTER_CMD, struct + dvb_diseqc_master_cmd ⋆cmd); + + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_DISEQC_SEND_MASTER_CMD for this + command. + + +struct + dvb_diseqc_master_cmd + *cmd + +Pointer to the command to be transmitted. + + + +ERRORS + + +EBADF + +fd is not a valid file descriptor. + + +EFAULT + +Seq points to an invalid address. + + +EINVAL + +The data structure referred to by seq is invalid in some + way. + + +EPERM + +Permission denied (needs read/write access). + + +EINTERNAL + +Internal error in the device driver. + + +
+ +
+FE_DISEQC_RECV_SLAVE_REPLY +DESCRIPTION + + +This ioctl call is used to receive reply to a DiSEqC 2.0 command. + + + +SYNOPSIS + + +int ioctl(int fd, int request = + FE_DISEQC_RECV_SLAVE_REPLY, struct + dvb_diseqc_slave_reply ⋆reply); + + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_DISEQC_RECV_SLAVE_REPLY for this + command. + + +struct + dvb_diseqc_slave_reply + *reply + +Pointer to the command to be received. + + +ERRORS + + +EBADF + +fd is not a valid file descriptor. + + +EFAULT + +Seq points to an invalid address. + + +EINVAL + +The data structure referred to by seq is invalid in some + way. + + +EPERM + +Permission denied (needs read/write access). + + +EINTERNAL + +Internal error in the device driver. + + +
+ +
+FE_DISEQC_SEND_BURST +DESCRIPTION + + +This ioctl call is used to send a 22KHz tone burst. + + + +SYNOPSIS + + +int ioctl(int fd, int request = + FE_DISEQC_SEND_BURST, fe_sec_mini_cmd_t burst); + + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_DISEQC_SEND_BURST for this command. + + +fe_sec_mini_cmd_t + burst + +burst A or B. + + + +ERRORS + + +EBADF + +fd is not a valid file descriptor. + + +EFAULT + +Seq points to an invalid address. + + +EINVAL + +The data structure referred to by seq is invalid in some + way. + + +EPERM + +Permission denied (needs read/write access). + + +EINTERNAL + +Internal error in the device driver. + + +
+ +
+FE_SET_TONE +DESCRIPTION + + +This call is used to set the generation of the continuous 22kHz tone. This call + requires read/write permissions. + + +SYNOPSIS + + +int ioctl(int fd, int request = FE_SET_TONE, + fe_sec_tone_mode_t tone); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_SET_TONE for this command. + + +fe_sec_tone_mode_t + tone + +The requested tone generation mode (on/off). + + +ERRORS + + +ENODEV + +Device driver not loaded/available. + + +EBUSY + +Device or resource busy. + + +EINVAL + +Invalid argument. + + +EPERM + +File not opened with read permissions. + + +EINTERNAL + +Internal error in the device driver. + + +
+ +
+FE_SET_VOLTAGE +DESCRIPTION + + +This call is used to set the bus voltage. This call requires read/write + permissions. + + +SYNOPSIS + + +int ioctl(int fd, int request = FE_SET_VOLTAGE, + fe_sec_voltage_t voltage); + + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_SET_VOLTAGE for this command. + + +fe_sec_voltage_t + voltage + +The requested bus voltage. + + + +ERRORS + + +ENODEV + +Device driver not loaded/available. + + +EBUSY + +Device or resource busy. + + +EINVAL + +Invalid argument. + + +EPERM + +File not opened with read permissions. + + +EINTERNAL + +Internal error in the device driver. + + +
+ +
+FE_ENABLE_HIGH_LNB_VOLTAGE +DESCRIPTION + + +If high != 0 enables slightly higher voltages instead of 13/18V (to compensate + for long cables). This call requires read/write permissions. Not all DVB + adapters support this ioctl. + + + +SYNOPSIS + + +int ioctl(int fd, int request = + FE_ENABLE_HIGH_LNB_VOLTAGE, int high); + + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_SET_VOLTAGE for this command. + + +int high + +The requested bus voltage. + + + +ERRORS + + +ENODEV + +Device driver not loaded/available. + + +EBUSY + +Device or resource busy. + + +EINVAL + +Invalid argument. + + +EPERM + +File not opened with read permissions. + + +EINTERNAL + +Internal error in the device driver. + + +
+
+&sub-isdbt; diff --git a/Documentation/DocBook/dvb/intro.xml b/Documentation/DocBook/dvb/intro.xml new file mode 100644 index 000000000000..0dc83f672ea2 --- /dev/null +++ b/Documentation/DocBook/dvb/intro.xml @@ -0,0 +1,191 @@ +Introduction + +
+What you need to know + +The reader of this document is required to have some knowledge in +the area of digital video broadcasting (DVB) and should be familiar with +part I of the MPEG2 specification ISO/IEC 13818 (aka ITU-T H.222), i.e +you should know what a program/transport stream (PS/TS) is and what is +meant by a packetized elementary stream (PES) or an I-frame. + +Various DVB standards documents are available from + and/or +. + +It is also necessary to know how to access unix/linux devices and +how to use ioctl calls. This also includes the knowledge of C or C++. + +
+ +
+History + +The first API for DVB cards we used at Convergence in late 1999 +was an extension of the Video4Linux API which was primarily developed +for frame grabber cards. As such it was not really well suited to be +used for DVB cards and their new features like recording MPEG streams +and filtering several section and PES data streams at the same time. + + +In early 2000, we were approached by Nokia with a proposal for a +new standard Linux DVB API. As a commitment to the development of +terminals based on open standards, Nokia and Convergence made it +available to all Linux developers and published it on + in September 2000. +Convergence is the maintainer of the Linux DVB API. Together with the +LinuxTV community (i.e. you, the reader of this document), the Linux DVB +API will be constantly reviewed and improved. With the Linux driver for +the Siemens/Hauppauge DVB PCI card Convergence provides a first +implementation of the Linux DVB API. +
+ +
+Overview + +
+Components of a DVB card/STB + + + + + + + + +
+ +A DVB PCI card or DVB set-top-box (STB) usually consists of the +following main hardware components: + + + + +Frontend consisting of tuner and DVB demodulator + +Here the raw signal reaches the DVB hardware from a satellite dish +or antenna or directly from cable. The frontend down-converts and +demodulates this signal into an MPEG transport stream (TS). In case of a +satellite frontend, this includes a facility for satellite equipment +control (SEC), which allows control of LNB polarization, multi feed +switches or dish rotors. + + + + +Conditional Access (CA) hardware like CI adapters and smartcard slots + + +The complete TS is passed through the CA hardware. Programs to +which the user has access (controlled by the smart card) are decoded in +real time and re-inserted into the TS. + + + + Demultiplexer which filters the incoming DVB stream + +The demultiplexer splits the TS into its components like audio and +video streams. Besides usually several of such audio and video streams +it also contains data streams with information about the programs +offered in this or other streams of the same provider. + + + + +MPEG2 audio and video decoder + +The main targets of the demultiplexer are the MPEG2 audio and +video decoders. After decoding they pass on the uncompressed audio and +video to the computer screen or (through a PAL/NTSC encoder) to a TV +set. + + + + + + shows a crude schematic of the control and data flow +between those components. + +On a DVB PCI card not all of these have to be present since some +functionality can be provided by the main CPU of the PC (e.g. MPEG +picture and sound decoding) or is not needed (e.g. for data-only uses +like “internet over satellite”). Also not every card or STB +provides conditional access hardware. + +
+ +
+Linux DVB Devices + +The Linux DVB API lets you control these hardware components +through currently six Unix-style character devices for video, audio, +frontend, demux, CA and IP-over-DVB networking. The video and audio +devices control the MPEG2 decoder hardware, the frontend device the +tuner and the DVB demodulator. The demux device gives you control over +the PES and section filters of the hardware. If the hardware does not +support filtering these filters can be implemented in software. Finally, +the CA device controls all the conditional access capabilities of the +hardware. It can depend on the individual security requirements of the +platform, if and how many of the CA functions are made available to the +application through this device. + +All devices can be found in the /dev +tree under /dev/dvb. The individual devices +are called: + + + + +/dev/dvb/adapterN/audioM, + + +/dev/dvb/adapterN/videoM, + + +/dev/dvb/adapterN/frontendM, + + + +/dev/dvb/adapterN/netM, + + + +/dev/dvb/adapterN/demuxM, + + + +/dev/dvb/adapterN/caM, + +where N enumerates the DVB PCI cards in a system starting +from 0, and M enumerates the devices of each type within each +adapter, starting from 0, too. We will omit the “/dev/dvb/adapterN/” in the further dicussion +of these devices. The naming scheme for the devices is the same wheter +devfs is used or not. + +More details about the data structures and function calls of all +the devices are described in the following chapters. + +
+ +
+API include files + +For each of the DVB devices a corresponding include file exists. +The DVB API include files should be included in application sources with +a partial path like: + + + + #include <linux/dvb/frontend.h> + + +To enable applications to support different API version, an +additional include file linux/dvb/version.h exists, which defines the +constant DVB_API_VERSION. This document +describes DVB_API_VERSION 3. + + +
+ diff --git a/Documentation/DocBook/dvb/isdbt.xml b/Documentation/DocBook/dvb/isdbt.xml new file mode 100644 index 000000000000..92855222fccb --- /dev/null +++ b/Documentation/DocBook/dvb/isdbt.xml @@ -0,0 +1,314 @@ +
+ ISDB-T frontend + This section describes shortly what are the possible parameters in the Linux + DVB-API called "S2API" and now DVB API 5 in order to tune an ISDB-T/ISDB-Tsb + demodulator: + + This ISDB-T/ISDB-Tsb API extension should reflect all information + needed to tune any ISDB-T/ISDB-Tsb hardware. Of course it is possible + that some very sophisticated devices won't need certain parameters to + tune. + + The information given here should help application writers to know how + to handle ISDB-T and ISDB-Tsb hardware using the Linux DVB-API. + + The details given here about ISDB-T and ISDB-Tsb are just enough to + basically show the dependencies between the needed parameter values, + but surely some information is left out. For more detailed information + see the following documents: + + ARIB STD-B31 - "Transmission System for Digital Terrestrial + Television Broadcasting" and + ARIB TR-B14 - "Operational Guidelines for Digital Terrestrial + Television Broadcasting". + + In order to read this document one has to have some knowledge the + channel structure in ISDB-T and ISDB-Tsb. I.e. it has to be known to + the reader that an ISDB-T channel consists of 13 segments, that it can + have up to 3 layer sharing those segments, and things like that. + + Parameters used by ISDB-T and ISDB-Tsb. + +
+ Parameters that are common with DVB-T and ATSC + +
+ <constant>DTV_FREQUENCY</constant> + + Central frequency of the channel. + + For ISDB-T the channels are usally transmitted with an offset of 143kHz. E.g. a + valid frequncy could be 474143 kHz. The stepping is bound to the bandwidth of + the channel which is 6MHz. + + As in ISDB-Tsb the channel consists of only one or three segments the + frequency step is 429kHz, 3*429 respectively. As for ISDB-T the + central frequency of the channel is expected. +
+ +
+ <constant>DTV_BANDWIDTH_HZ</constant> (optional) + + Possible values: + + For ISDB-T it should be always 6000000Hz (6MHz) + For ISDB-Tsb it can vary depending on the number of connected segments + + Note: Hardware specific values might be given here, but standard + applications should not bother to set a value to this field as + standard demods are ignoring it anyway. + + Bandwidth in ISDB-T is fixed (6MHz) or can be easily derived from + other parameters (DTV_ISDBT_SB_SEGMENT_IDX, + DTV_ISDBT_SB_SEGMENT_COUNT). +
+ +
+ <constant>DTV_DELIVERY_SYSTEM</constant> + + Possible values: SYS_ISDBT +
+ +
+ <constant>DTV_TRANSMISSION_MODE</constant> + + ISDB-T supports three carrier/symbol-size: 8K, 4K, 2K. It is called + 'mode' in the standard: Mode 1 is 2K, mode 2 is 4K, mode 3 is 8K + + Possible values: TRANSMISSION_MODE_2K, TRANSMISSION_MODE_8K, + TRANSMISSION_MODE_AUTO, TRANSMISSION_MODE_4K + + If DTV_TRANSMISSION_MODE is set the TRANSMISSION_MODE_AUTO the + hardware will try to find the correct FFT-size (if capable) and will + use TMCC to fill in the missing parameters. + + TRANSMISSION_MODE_4K is added at the same time as the other new parameters. +
+ +
+ <constant>DTV_GUARD_INTERVAL</constant> + + Possible values: GUARD_INTERVAL_1_32, GUARD_INTERVAL_1_16, GUARD_INTERVAL_1_8, + GUARD_INTERVAL_1_4, GUARD_INTERVAL_AUTO + + If DTV_GUARD_INTERVAL is set the GUARD_INTERVAL_AUTO the hardware will + try to find the correct guard interval (if capable) and will use TMCC to fill + in the missing parameters. +
+
+
+ ISDB-T only parameters + +
+ <constant>DTV_ISDBT_PARTIAL_RECEPTION</constant> + + If DTV_ISDBT_SOUND_BROADCASTING is '0' this bit-field represents whether + the channel is in partial reception mode or not. + + If '1' DTV_ISDBT_LAYERA_* values are assigned to the center segment and + DTV_ISDBT_LAYERA_SEGMENT_COUNT has to be '1'. + + If in addition DTV_ISDBT_SOUND_BROADCASTING is '1' + DTV_ISDBT_PARTIAL_RECEPTION represents whether this ISDB-Tsb channel + is consisting of one segment and layer or three segments and two layers. + + Possible values: 0, 1, -1 (AUTO) +
+ +
+ <constant>DTV_ISDBT_SOUND_BROADCASTING</constant> + + This field represents whether the other DTV_ISDBT_*-parameters are + referring to an ISDB-T and an ISDB-Tsb channel. (See also + DTV_ISDBT_PARTIAL_RECEPTION). + + Possible values: 0, 1, -1 (AUTO) +
+ +
+ <constant>DTV_ISDBT_SB_SUBCHANNEL_ID</constant> + + This field only applies if DTV_ISDBT_SOUND_BROADCASTING is '1'. + + (Note of the author: This might not be the correct description of the + SUBCHANNEL-ID in all details, but it is my understanding of the technical + background needed to program a device) + + An ISDB-Tsb channel (1 or 3 segments) can be broadcasted alone or in a + set of connected ISDB-Tsb channels. In this set of channels every + channel can be received independently. The number of connected + ISDB-Tsb segment can vary, e.g. depending on the frequency spectrum + bandwidth available. + + Example: Assume 8 ISDB-Tsb connected segments are broadcasted. The + broadcaster has several possibilities to put those channels in the + air: Assuming a normal 13-segment ISDB-T spectrum he can align the 8 + segments from position 1-8 to 5-13 or anything in between. + + The underlying layer of segments are subchannels: each segment is + consisting of several subchannels with a predefined IDs. A sub-channel + is used to help the demodulator to synchronize on the channel. + + An ISDB-T channel is always centered over all sub-channels. As for + the example above, in ISDB-Tsb it is no longer as simple as that. + + The DTV_ISDBT_SB_SUBCHANNEL_ID parameter is used to give the + sub-channel ID of the segment to be demodulated. + + Possible values: 0 .. 41, -1 (AUTO) +
+ +
+ + <constant>DTV_ISDBT_SB_SEGMENT_IDX</constant> + + This field only applies if DTV_ISDBT_SOUND_BROADCASTING is '1'. + + DTV_ISDBT_SB_SEGMENT_IDX gives the index of the segment to be + demodulated for an ISDB-Tsb channel where several of them are + transmitted in the connected manner. + + Possible values: 0 .. DTV_ISDBT_SB_SEGMENT_COUNT - 1 + + Note: This value cannot be determined by an automatic channel search. +
+ +
+ <constant>DTV_ISDBT_SB_SEGMENT_COUNT</constant> + + This field only applies if DTV_ISDBT_SOUND_BROADCASTING is '1'. + + DTV_ISDBT_SB_SEGMENT_COUNT gives the total count of connected ISDB-Tsb + channels. + + Possible values: 1 .. 13 + + Note: This value cannot be determined by an automatic channel search. +
+ +
+ Hierarchical layers + + ISDB-T channels can be coded hierarchically. As opposed to DVB-T in + ISDB-T hierarchical layers can be decoded simultaneously. For that + reason a ISDB-T demodulator has 3 viterbi and 3 reed-solomon-decoders. + + ISDB-T has 3 hierarchical layers which each can use a part of the + available segments. The total number of segments over all layers has + to 13 in ISDB-T. + +
+ <constant>DTV_ISDBT_LAYER_ENABLED</constant> + + Hierarchical reception in ISDB-T is achieved by enabling or disabling + layers in the decoding process. Setting all bits of + DTV_ISDBT_LAYER_ENABLED to '1' forces all layers (if applicable) to be + demodulated. This is the default. + + If the channel is in the partial reception mode + (DTV_ISDBT_PARTIAL_RECEPTION = 1) the central segment can be decoded + independently of the other 12 segments. In that mode layer A has to + have a SEGMENT_COUNT of 1. + + In ISDB-Tsb only layer A is used, it can be 1 or 3 in ISDB-Tsb + according to DTV_ISDBT_PARTIAL_RECEPTION. SEGMENT_COUNT must be filled + accordingly. + + Possible values: 0x1, 0x2, 0x4 (|-able) + + DTV_ISDBT_LAYER_ENABLED[0:0] - layer A + DTV_ISDBT_LAYER_ENABLED[1:1] - layer B + DTV_ISDBT_LAYER_ENABLED[2:2] - layer C + DTV_ISDBT_LAYER_ENABLED[31:3] unused +
+ +
+ <constant>DTV_ISDBT_LAYER*_FEC</constant> + + Possible values: FEC_AUTO, FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8 +
+ +
+ <constant>DTV_ISDBT_LAYER*_MODULATION</constant> + + Possible values: QAM_AUTO, QPSK, QAM_16, QAM_64, DQPSK + + Note: If layer C is DQPSK layer B has to be DQPSK. If layer B is DQPSK + and DTV_ISDBT_PARTIAL_RECEPTION=0 layer has to be DQPSK. +
+ +
+ <constant>DTV_ISDBT_LAYER*_SEGMENT_COUNT</constant> + + Possible values: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, -1 (AUTO) + + Note: Truth table for DTV_ISDBT_SOUND_BROADCASTING and + DTV_ISDBT_PARTIAL_RECEPTION and LAYER*_SEGMENT_COUNT + + + + + + + PR + SB + Layer A width + Layer B width + Layer C width + total width + + + + 0 + 0 + 1 .. 13 + 1 .. 13 + 1 .. 13 + 13 + + + + 1 + 0 + 1 + 1 .. 13 + 1 .. 13 + 13 + + + + 0 + 1 + 1 + 0 + 0 + 1 + + + + 1 + 1 + 1 + 2 + 0 + 13 + + + + + + +
+ +
+ <constant>DTV_ISDBT_LAYER*_TIME_INTERLEAVING</constant> + + Possible values: 0, 1, 2, 3, -1 (AUTO) + + Note: The real inter-leaver depth-names depend on the mode (fft-size); the values + here are referring to what can be found in the TMCC-structure - + independent of the mode. +
+
+
+
diff --git a/Documentation/DocBook/dvb/kdapi.xml b/Documentation/DocBook/dvb/kdapi.xml new file mode 100644 index 000000000000..6c67481eaa4b --- /dev/null +++ b/Documentation/DocBook/dvb/kdapi.xml @@ -0,0 +1,2309 @@ +Kernel Demux API +The kernel demux API defines a driver-internal interface for registering low-level, +hardware specific driver to a hardware independent demux layer. It is only of interest for +DVB device driver writers. The header file for this API is named demux.h and located in +drivers/media/dvb/dvb-core. + +Maintainer note: This section must be reviewed. It is probably out of date. + + +
+Kernel Demux Data Types + + +
+dmx_success_t + + typedef enum { + DMX_OK = 0, /⋆ Received Ok ⋆/ + DMX_LENGTH_ERROR, /⋆ Incorrect length ⋆/ + DMX_OVERRUN_ERROR, /⋆ Receiver ring buffer overrun ⋆/ + DMX_CRC_ERROR, /⋆ Incorrect CRC ⋆/ + DMX_FRAME_ERROR, /⋆ Frame alignment error ⋆/ + DMX_FIFO_ERROR, /⋆ Receiver FIFO overrun ⋆/ + DMX_MISSED_ERROR /⋆ Receiver missed packet ⋆/ + } dmx_success_t; + + +
+
+TS filter types + + /⋆--------------------------------------------------------------------------⋆/ + /⋆ TS packet reception ⋆/ + /⋆--------------------------------------------------------------------------⋆/ + + /⋆ TS filter type for set_type() ⋆/ + + #define TS_PACKET 1 /⋆ send TS packets (188 bytes) to callback (default) ⋆/ + #define TS_PAYLOAD_ONLY 2 /⋆ in case TS_PACKET is set, only send the TS + payload (<=184 bytes per packet) to callback ⋆/ + #define TS_DECODER 4 /⋆ send stream to built-in decoder (if present) ⋆/ + + +
+
+dmx_ts_pes_t +The structure + + + typedef enum + { + DMX_TS_PES_AUDIO, /⋆ also send packets to audio decoder (if it exists) ⋆/ + DMX_TS_PES_VIDEO, /⋆ ... ⋆/ + DMX_TS_PES_TELETEXT, + DMX_TS_PES_SUBTITLE, + DMX_TS_PES_PCR, + DMX_TS_PES_OTHER, + } dmx_ts_pes_t; + +describes the PES type for filters which write to a built-in decoder. The correspond (and +should be kept identical) to the types in the demux device. + + + struct dmx_ts_feed_s { + int is_filtering; /⋆ Set to non-zero when filtering in progress ⋆/ + struct dmx_demux_s⋆ parent; /⋆ Back-pointer ⋆/ + void⋆ priv; /⋆ Pointer to private data of the API client ⋆/ + int (⋆set) (struct dmx_ts_feed_s⋆ feed, + __u16 pid, + size_t callback_length, + size_t circular_buffer_size, + int descramble, + struct timespec timeout); + int (⋆start_filtering) (struct dmx_ts_feed_s⋆ feed); + int (⋆stop_filtering) (struct dmx_ts_feed_s⋆ feed); + int (⋆set_type) (struct dmx_ts_feed_s⋆ feed, + int type, + dmx_ts_pes_t pes_type); + }; + + typedef struct dmx_ts_feed_s dmx_ts_feed_t; + + + /⋆--------------------------------------------------------------------------⋆/ + /⋆ PES packet reception (not supported yet) ⋆/ + /⋆--------------------------------------------------------------------------⋆/ + + typedef struct dmx_pes_filter_s { + struct dmx_pes_s⋆ parent; /⋆ Back-pointer ⋆/ + void⋆ priv; /⋆ Pointer to private data of the API client ⋆/ + } dmx_pes_filter_t; + + + typedef struct dmx_pes_feed_s { + int is_filtering; /⋆ Set to non-zero when filtering in progress ⋆/ + struct dmx_demux_s⋆ parent; /⋆ Back-pointer ⋆/ + void⋆ priv; /⋆ Pointer to private data of the API client ⋆/ + int (⋆set) (struct dmx_pes_feed_s⋆ feed, + __u16 pid, + size_t circular_buffer_size, + int descramble, + struct timespec timeout); + int (⋆start_filtering) (struct dmx_pes_feed_s⋆ feed); + int (⋆stop_filtering) (struct dmx_pes_feed_s⋆ feed); + int (⋆allocate_filter) (struct dmx_pes_feed_s⋆ feed, + dmx_pes_filter_t⋆⋆ filter); + int (⋆release_filter) (struct dmx_pes_feed_s⋆ feed, + dmx_pes_filter_t⋆ filter); + } dmx_pes_feed_t; + + + typedef struct { + __u8 filter_value [DMX_MAX_FILTER_SIZE]; + __u8 filter_mask [DMX_MAX_FILTER_SIZE]; + struct dmx_section_feed_s⋆ parent; /⋆ Back-pointer ⋆/ + void⋆ priv; /⋆ Pointer to private data of the API client ⋆/ + } dmx_section_filter_t; + + + struct dmx_section_feed_s { + int is_filtering; /⋆ Set to non-zero when filtering in progress ⋆/ + struct dmx_demux_s⋆ parent; /⋆ Back-pointer ⋆/ + void⋆ priv; /⋆ Pointer to private data of the API client ⋆/ + int (⋆set) (struct dmx_section_feed_s⋆ feed, + __u16 pid, + size_t circular_buffer_size, + int descramble, + int check_crc); + int (⋆allocate_filter) (struct dmx_section_feed_s⋆ feed, + dmx_section_filter_t⋆⋆ filter); + int (⋆release_filter) (struct dmx_section_feed_s⋆ feed, + dmx_section_filter_t⋆ filter); + int (⋆start_filtering) (struct dmx_section_feed_s⋆ feed); + int (⋆stop_filtering) (struct dmx_section_feed_s⋆ feed); + }; + typedef struct dmx_section_feed_s dmx_section_feed_t; + + /⋆--------------------------------------------------------------------------⋆/ + /⋆ Callback functions ⋆/ + /⋆--------------------------------------------------------------------------⋆/ + + typedef int (⋆dmx_ts_cb) ( __u8 ⋆ buffer1, + size_t buffer1_length, + __u8 ⋆ buffer2, + size_t buffer2_length, + dmx_ts_feed_t⋆ source, + dmx_success_t success); + + typedef int (⋆dmx_section_cb) ( __u8 ⋆ buffer1, + size_t buffer1_len, + __u8 ⋆ buffer2, + size_t buffer2_len, + dmx_section_filter_t ⋆ source, + dmx_success_t success); + + typedef int (⋆dmx_pes_cb) ( __u8 ⋆ buffer1, + size_t buffer1_len, + __u8 ⋆ buffer2, + size_t buffer2_len, + dmx_pes_filter_t⋆ source, + dmx_success_t success); + + /⋆--------------------------------------------------------------------------⋆/ + /⋆ DVB Front-End ⋆/ + /⋆--------------------------------------------------------------------------⋆/ + + typedef enum { + DMX_OTHER_FE = 0, + DMX_SATELLITE_FE, + DMX_CABLE_FE, + DMX_TERRESTRIAL_FE, + DMX_LVDS_FE, + DMX_ASI_FE, /⋆ DVB-ASI interface ⋆/ + DMX_MEMORY_FE + } dmx_frontend_source_t; + + typedef struct { + /⋆ The following char⋆ fields point to NULL terminated strings ⋆/ + char⋆ id; /⋆ Unique front-end identifier ⋆/ + char⋆ vendor; /⋆ Name of the front-end vendor ⋆/ + char⋆ model; /⋆ Name of the front-end model ⋆/ + struct list_head connectivity_list; /⋆ List of front-ends that can + be connected to a particular + demux ⋆/ + void⋆ priv; /⋆ Pointer to private data of the API client ⋆/ + dmx_frontend_source_t source; + } dmx_frontend_t; + + /⋆--------------------------------------------------------------------------⋆/ + /⋆ MPEG-2 TS Demux ⋆/ + /⋆--------------------------------------------------------------------------⋆/ + + /⋆ + ⋆ Flags OR'ed in the capabilites field of struct dmx_demux_s. + ⋆/ + + #define DMX_TS_FILTERING 1 + #define DMX_PES_FILTERING 2 + #define DMX_SECTION_FILTERING 4 + #define DMX_MEMORY_BASED_FILTERING 8 /⋆ write() available ⋆/ + #define DMX_CRC_CHECKING 16 + #define DMX_TS_DESCRAMBLING 32 + #define DMX_SECTION_PAYLOAD_DESCRAMBLING 64 + #define DMX_MAC_ADDRESS_DESCRAMBLING 128 + + +
+
+demux_demux_t + + /⋆ + ⋆ DMX_FE_ENTRY(): Casts elements in the list of registered + ⋆ front-ends from the generic type struct list_head + ⋆ to the type ⋆ dmx_frontend_t + ⋆. + ⋆/ + + #define DMX_FE_ENTRY(list) list_entry(list, dmx_frontend_t, connectivity_list) + + struct dmx_demux_s { + /⋆ The following char⋆ fields point to NULL terminated strings ⋆/ + char⋆ id; /⋆ Unique demux identifier ⋆/ + char⋆ vendor; /⋆ Name of the demux vendor ⋆/ + char⋆ model; /⋆ Name of the demux model ⋆/ + __u32 capabilities; /⋆ Bitfield of capability flags ⋆/ + dmx_frontend_t⋆ frontend; /⋆ Front-end connected to the demux ⋆/ + struct list_head reg_list; /⋆ List of registered demuxes ⋆/ + void⋆ priv; /⋆ Pointer to private data of the API client ⋆/ + int users; /⋆ Number of users ⋆/ + int (⋆open) (struct dmx_demux_s⋆ demux); + int (⋆close) (struct dmx_demux_s⋆ demux); + int (⋆write) (struct dmx_demux_s⋆ demux, const char⋆ buf, size_t count); + int (⋆allocate_ts_feed) (struct dmx_demux_s⋆ demux, + dmx_ts_feed_t⋆⋆ feed, + dmx_ts_cb callback); + int (⋆release_ts_feed) (struct dmx_demux_s⋆ demux, + dmx_ts_feed_t⋆ feed); + int (⋆allocate_pes_feed) (struct dmx_demux_s⋆ demux, + dmx_pes_feed_t⋆⋆ feed, + dmx_pes_cb callback); + int (⋆release_pes_feed) (struct dmx_demux_s⋆ demux, + dmx_pes_feed_t⋆ feed); + int (⋆allocate_section_feed) (struct dmx_demux_s⋆ demux, + dmx_section_feed_t⋆⋆ feed, + dmx_section_cb callback); + int (⋆release_section_feed) (struct dmx_demux_s⋆ demux, + dmx_section_feed_t⋆ feed); + int (⋆descramble_mac_address) (struct dmx_demux_s⋆ demux, + __u8⋆ buffer1, + size_t buffer1_length, + __u8⋆ buffer2, + size_t buffer2_length, + __u16 pid); + int (⋆descramble_section_payload) (struct dmx_demux_s⋆ demux, + __u8⋆ buffer1, + size_t buffer1_length, + __u8⋆ buffer2, size_t buffer2_length, + __u16 pid); + int (⋆add_frontend) (struct dmx_demux_s⋆ demux, + dmx_frontend_t⋆ frontend); + int (⋆remove_frontend) (struct dmx_demux_s⋆ demux, + dmx_frontend_t⋆ frontend); + struct list_head⋆ (⋆get_frontends) (struct dmx_demux_s⋆ demux); + int (⋆connect_frontend) (struct dmx_demux_s⋆ demux, + dmx_frontend_t⋆ frontend); + int (⋆disconnect_frontend) (struct dmx_demux_s⋆ demux); + + + /⋆ added because js cannot keep track of these himself ⋆/ + int (⋆get_pes_pids) (struct dmx_demux_s⋆ demux, __u16 ⋆pids); + }; + typedef struct dmx_demux_s dmx_demux_t; + + +
+
+Demux directory + + /⋆ + ⋆ DMX_DIR_ENTRY(): Casts elements in the list of registered + ⋆ demuxes from the generic type struct list_head⋆ to the type dmx_demux_t + ⋆. + ⋆/ + + #define DMX_DIR_ENTRY(list) list_entry(list, dmx_demux_t, reg_list) + + int dmx_register_demux (dmx_demux_t⋆ demux); + int dmx_unregister_demux (dmx_demux_t⋆ demux); + struct list_head⋆ dmx_get_demuxes (void); + +
+
+Demux Directory API +The demux directory is a Linux kernel-wide facility for registering and accessing the +MPEG-2 TS demuxes in the system. Run-time registering and unregistering of demux drivers +is possible using this API. + +All demux drivers in the directory implement the abstract interface dmx_demux_t. + + +
dmx_register_demux() +DESCRIPTION + + +This function makes a demux driver interface available to the Linux kernel. It is + usually called by the init_module() function of the kernel module that contains + the demux driver. The caller of this function is responsible for allocating + dynamic or static memory for the demux structure and for initializing its fields + before calling this function. The memory allocated for the demux structure + must not be freed before calling dmx_unregister_demux(), + + +SYNOPSIS + + +int dmx_register_demux ( dmx_demux_t ⋆demux ) + + +PARAMETERS + + +dmx_demux_t* + demux + +Pointer to the demux structure. + + +RETURNS + + +0 + +The function was completed without errors. + + +-EEXIST + +A demux with the same value of the id field already stored + in the directory. + + +-ENOSPC + +No space left in the directory. + + + +
dmx_unregister_demux() +DESCRIPTION + + +This function is called to indicate that the given demux interface is no + longer available. The caller of this function is responsible for freeing the + memory of the demux structure, if it was dynamically allocated before calling + dmx_register_demux(). The cleanup_module() function of the kernel module + that contains the demux driver should call this function. Note that this function + fails if the demux is currently in use, i.e., release_demux() has not been called + for the interface. + + +SYNOPSIS + + +int dmx_unregister_demux ( dmx_demux_t ⋆demux ) + + +PARAMETERS + + +dmx_demux_t* + demux + +Pointer to the demux structure which is to be + unregistered. + + +RETURNS + + +0 + +The function was completed without errors. + + +ENODEV + +The specified demux is not registered in the demux + directory. + + +EBUSY + +The specified demux is currently in use. + + + +
dmx_get_demuxes() +DESCRIPTION + + +Provides the caller with the list of registered demux interfaces, using the + standard list structure defined in the include file linux/list.h. The include file + demux.h defines the macro DMX_DIR_ENTRY() for converting an element of + the generic type struct list_head* to the type dmx_demux_t*. The caller must + not free the memory of any of the elements obtained via this function call. + + +SYNOPSIS + + +struct list_head ⋆dmx_get_demuxes () + + +PARAMETERS + + +none + + +RETURNS + + +struct list_head * + +A list of demux interfaces, or NULL in the case of an + empty list. + + +
+
+Demux API +The demux API should be implemented for each demux in the system. It is used to select +the TS source of a demux and to manage the demux resources. When the demux +client allocates a resource via the demux API, it receives a pointer to the API of that +resource. + +Each demux receives its TS input from a DVB front-end or from memory, as set via the +demux API. In a system with more than one front-end, the API can be used to select one of +the DVB front-ends as a TS source for a demux, unless this is fixed in the HW platform. The +demux API only controls front-ends regarding their connections with demuxes; the APIs +used to set the other front-end parameters, such as tuning, are not defined in this +document. + +The functions that implement the abstract interface demux should be defined static or +module private and registered to the Demux Directory for external access. It is not necessary +to implement every function in the demux_t struct, however (for example, a demux interface +might support Section filtering, but not TS or PES filtering). The API client is expected to +check the value of any function pointer before calling the function: the value of NULL means +“function not available”. + +Whenever the functions of the demux API modify shared data, the possibilities of lost +update and race condition problems should be addressed, e.g. by protecting parts of code with +mutexes. This is especially important on multi-processor hosts. + +Note that functions called from a bottom half context must not sleep, at least in the 2.2.x +kernels. Even a simple memory allocation can result in a kernel thread being put to sleep if +swapping is needed. For example, the Linux kernel calls the functions of a network device +interface from a bottom half context. Thus, if a demux API function is called from network +device code, the function must not sleep. + + + +
+open() +DESCRIPTION + + +This function reserves the demux for use by the caller and, if necessary, + initializes the demux. When the demux is no longer needed, the function close() + should be called. It should be possible for multiple clients to access the demux + at the same time. Thus, the function implementation should increment the + demux usage count when open() is called and decrement it when close() is + called. + + +SYNOPSIS + + +int open ( demux_t⋆ demux ); + + +PARAMETERS + + +demux_t* demux + +Pointer to the demux API and instance data. + + +RETURNS + + +0 + +The function was completed without errors. + + +-EUSERS + +Maximum usage count reached. + + +-EINVAL + +Bad parameter. + + + +
+
+close() +DESCRIPTION + + +This function reserves the demux for use by the caller and, if necessary, + initializes the demux. When the demux is no longer needed, the function close() + should be called. It should be possible for multiple clients to access the demux + at the same time. Thus, the function implementation should increment the + demux usage count when open() is called and decrement it when close() is + called. + + +SYNOPSIS + + +int close(demux_t⋆ demux); + + +PARAMETERS + + +demux_t* demux + +Pointer to the demux API and instance data. + + +RETURNS + + +0 + +The function was completed without errors. + + +-ENODEV + +The demux was not in use. + + +-EINVAL + +Bad parameter. + + + +
+
+write() +DESCRIPTION + + +This function provides the demux driver with a memory buffer containing TS + packets. Instead of receiving TS packets from the DVB front-end, the demux + driver software will read packets from memory. Any clients of this demux + with active TS, PES or Section filters will receive filtered data via the Demux + callback API (see 0). The function returns when all the data in the buffer has + been consumed by the demux. Demux hardware typically cannot read TS from + memory. If this is the case, memory-based filtering has to be implemented + entirely in software. + + +SYNOPSIS + + +int write(demux_t⋆ demux, const char⋆ buf, size_t + count); + + +PARAMETERS + + +demux_t* demux + +Pointer to the demux API and instance data. + + +const char* buf + +Pointer to the TS data in kernel-space memory. + + +size_t length + +Length of the TS data. + + +RETURNS + + +0 + +The function was completed without errors. + + +-ENOSYS + +The command is not implemented. + + +-EINVAL + +Bad parameter. + + + +
allocate_ts_feed() +DESCRIPTION + + +Allocates a new TS feed, which is used to filter the TS packets carrying a + certain PID. The TS feed normally corresponds to a hardware PID filter on the + demux chip. + + +SYNOPSIS + + +int allocate_ts_feed(dmx_demux_t⋆ demux, + dmx_ts_feed_t⋆⋆ feed, dmx_ts_cb callback); + + +PARAMETERS + + +demux_t* demux + +Pointer to the demux API and instance data. + + +dmx_ts_feed_t** + feed + +Pointer to the TS feed API and instance data. + + +dmx_ts_cb callback + +Pointer to the callback function for passing received TS + packet + + +RETURNS + + +0 + +The function was completed without errors. + + +-EBUSY + +No more TS feeds available. + + +-ENOSYS + +The command is not implemented. + + +-EINVAL + +Bad parameter. + + + +
release_ts_feed() +DESCRIPTION + + +Releases the resources allocated with allocate_ts_feed(). Any filtering in + progress on the TS feed should be stopped before calling this function. + + +SYNOPSIS + + +int release_ts_feed(dmx_demux_t⋆ demux, + dmx_ts_feed_t⋆ feed); + + +PARAMETERS + + +demux_t* demux + +Pointer to the demux API and instance data. + + +dmx_ts_feed_t* feed + +Pointer to the TS feed API and instance data. + + +RETURNS + + +0 + +The function was completed without errors. + + +-EINVAL + +Bad parameter. + + + +
allocate_section_feed() +DESCRIPTION + + +Allocates a new section feed, i.e. a demux resource for filtering and receiving + sections. On platforms with hardware support for section filtering, a section + feed is directly mapped to the demux HW. On other platforms, TS packets are + first PID filtered in hardware and a hardware section filter then emulated in + software. The caller obtains an API pointer of type dmx_section_feed_t as an + out parameter. Using this API the caller can set filtering parameters and start + receiving sections. + + +SYNOPSIS + + +int allocate_section_feed(dmx_demux_t⋆ demux, + dmx_section_feed_t ⋆⋆feed, dmx_section_cb callback); + + +PARAMETERS + + +demux_t *demux + +Pointer to the demux API and instance data. + + +dmx_section_feed_t + **feed + +Pointer to the section feed API and instance data. + + +dmx_section_cb + callback + +Pointer to the callback function for passing received + sections. + + +RETURNS + + +0 + +The function was completed without errors. + + +-EBUSY + +No more section feeds available. + + +-ENOSYS + +The command is not implemented. + + +-EINVAL + +Bad parameter. + + + +
release_section_feed() +DESCRIPTION + + +Releases the resources allocated with allocate_section_feed(), including + allocated filters. Any filtering in progress on the section feed should be stopped + before calling this function. + + +SYNOPSIS + + +int release_section_feed(dmx_demux_t⋆ demux, + dmx_section_feed_t ⋆feed); + + +PARAMETERS + + +demux_t *demux + +Pointer to the demux API and instance data. + + +dmx_section_feed_t + *feed + +Pointer to the section feed API and instance data. + + +RETURNS + + +0 + +The function was completed without errors. + + +-EINVAL + +Bad parameter. + + + +
descramble_mac_address() +DESCRIPTION + + +This function runs a descrambling algorithm on the destination MAC + address field of a DVB Datagram Section, replacing the original address + with its un-encrypted version. Otherwise, the description on the function + descramble_section_payload() applies also to this function. + + +SYNOPSIS + + +int descramble_mac_address(dmx_demux_t⋆ demux, __u8 + ⋆buffer1, size_t buffer1_length, __u8 ⋆buffer2, + size_t buffer2_length, __u16 pid); + + +PARAMETERS + + +dmx_demux_t + *demux + +Pointer to the demux API and instance data. + + +__u8 *buffer1 + +Pointer to the first byte of the section. + + +size_t buffer1_length + +Length of the section data, including headers and CRC, + in buffer1. + + +__u8* buffer2 + +Pointer to the tail of the section data, or NULL. The + pointer has a non-NULL value if the section wraps past + the end of a circular buffer. + + +size_t buffer2_length + +Length of the section data, including headers and CRC, + in buffer2. + + +__u16 pid + +The PID on which the section was received. Useful + for obtaining the descrambling key, e.g. from a DVB + Common Access facility. + + +RETURNS + + +0 + +The function was completed without errors. + + +-ENOSYS + +No descrambling facility available. + + +-EINVAL + +Bad parameter. + + + +
descramble_section_payload() +DESCRIPTION + + +This function runs a descrambling algorithm on the payload of a DVB + Datagram Section, replacing the original payload with its un-encrypted + version. The function will be called from the demux API implementation; + the API client need not call this function directly. Section-level scrambling + algorithms are currently standardized only for DVB-RCC (return channel + over 2-directional cable TV network) systems. For all other DVB networks, + encryption schemes are likely to be proprietary to each data broadcaster. Thus, + it is expected that this function pointer will have the value of NULL (i.e., + function not available) in most demux API implementations. Nevertheless, it + should be possible to use the function pointer as a hook for dynamically adding + a “plug-in” descrambling facility to a demux driver. + + +While this function is not needed with hardware-based section descrambling, + the descramble_section_payload function pointer can be used to override the + default hardware-based descrambling algorithm: if the function pointer has a + non-NULL value, the corresponding function should be used instead of any + descrambling hardware. + + +SYNOPSIS + + +int descramble_section_payload(dmx_demux_t⋆ demux, + __u8 ⋆buffer1, size_t buffer1_length, __u8 ⋆buffer2, + size_t buffer2_length, __u16 pid); + + +PARAMETERS + + +dmx_demux_t + *demux + +Pointer to the demux API and instance data. + + +__u8 *buffer1 + +Pointer to the first byte of the section. + + +size_t buffer1_length + +Length of the section data, including headers and CRC, + in buffer1. + + +__u8 *buffer2 + +Pointer to the tail of the section data, or NULL. The + pointer has a non-NULL value if the section wraps past + the end of a circular buffer. + + +size_t buffer2_length + +Length of the section data, including headers and CRC, + in buffer2. + + +__u16 pid + +The PID on which the section was received. Useful + for obtaining the descrambling key, e.g. from a DVB + Common Access facility. + + +RETURNS + + +0 + +The function was completed without errors. + + +-ENOSYS + +No descrambling facility available. + + +-EINVAL + +Bad parameter. + + + +
add_frontend() +DESCRIPTION + + +Registers a connectivity between a demux and a front-end, i.e., indicates that + the demux can be connected via a call to connect_frontend() to use the given + front-end as a TS source. The client of this function has to allocate dynamic or + static memory for the frontend structure and initialize its fields before calling + this function. This function is normally called during the driver initialization. + The caller must not free the memory of the frontend struct before successfully + calling remove_frontend(). + + +SYNOPSIS + + +int add_frontend(dmx_demux_t ⋆demux, dmx_frontend_t + ⋆frontend); + + +PARAMETERS + + +dmx_demux_t* + demux + +Pointer to the demux API and instance data. + + +dmx_frontend_t* + frontend + +Pointer to the front-end instance data. + + +RETURNS + + +0 + +The function was completed without errors. + + +-EEXIST + +A front-end with the same value of the id field already + registered. + + +-EINUSE + +The demux is in use. + + +-ENOMEM + +No more front-ends can be added. + + +-EINVAL + +Bad parameter. + + + +
remove_frontend() +DESCRIPTION + + +Indicates that the given front-end, registered by a call to add_frontend(), can + no longer be connected as a TS source by this demux. The function should be + called when a front-end driver or a demux driver is removed from the system. + If the front-end is in use, the function fails with the return value of -EBUSY. + After successfully calling this function, the caller can free the memory of + the frontend struct if it was dynamically allocated before the add_frontend() + operation. + + +SYNOPSIS + + +int remove_frontend(dmx_demux_t⋆ demux, + dmx_frontend_t⋆ frontend); + + +PARAMETERS + + +dmx_demux_t* + demux + +Pointer to the demux API and instance data. + + +dmx_frontend_t* + frontend + +Pointer to the front-end instance data. + + +RETURNS + + +0 + +The function was completed without errors. + + +-EINVAL + +Bad parameter. + + +-EBUSY + +The front-end is in use, i.e. a call to connect_frontend() + has not been followed by a call to disconnect_frontend(). + + + +
get_frontends() +DESCRIPTION + + +Provides the APIs of the front-ends that have been registered for this demux. + Any of the front-ends obtained with this call can be used as a parameter for + connect_frontend(). + + +The include file demux.h contains the macro DMX_FE_ENTRY() for + converting an element of the generic type struct list_head* to the type + dmx_frontend_t*. The caller must not free the memory of any of the elements + obtained via this function call. + + +SYNOPSIS + + +struct list_head⋆ get_frontends(dmx_demux_t⋆ demux); + + +PARAMETERS + + +dmx_demux_t* + demux + +Pointer to the demux API and instance data. + + +RETURNS + + +dmx_demux_t* + +A list of front-end interfaces, or NULL in the case of an + empty list. + + + +
connect_frontend() +DESCRIPTION + + +Connects the TS output of the front-end to the input of the demux. A demux + can only be connected to a front-end registered to the demux with the function + add_frontend(). + + +It may or may not be possible to connect multiple demuxes to the same + front-end, depending on the capabilities of the HW platform. When not used, + the front-end should be released by calling disconnect_frontend(). + + +SYNOPSIS + + +int connect_frontend(dmx_demux_t⋆ demux, + dmx_frontend_t⋆ frontend); + + +PARAMETERS + + +dmx_demux_t* + demux + +Pointer to the demux API and instance data. + + +dmx_frontend_t* + frontend + +Pointer to the front-end instance data. + + +RETURNS + + +0 + +The function was completed without errors. + + +-EINVAL + +Bad parameter. + + +-EBUSY + +The front-end is in use. + + + +
disconnect_frontend() +DESCRIPTION + + +Disconnects the demux and a front-end previously connected by a + connect_frontend() call. + + +SYNOPSIS + + +int disconnect_frontend(dmx_demux_t⋆ demux); + + +PARAMETERS + + +dmx_demux_t* + demux + +Pointer to the demux API and instance data. + + +RETURNS + + +0 + +The function was completed without errors. + + +-EINVAL + +Bad parameter. + + +
+
+Demux Callback API +This kernel-space API comprises the callback functions that deliver filtered data to the +demux client. Unlike the other APIs, these API functions are provided by the client and called +from the demux code. + +The function pointers of this abstract interface are not packed into a structure as in the +other demux APIs, because the callback functions are registered and used independent +of each other. As an example, it is possible for the API client to provide several +callback functions for receiving TS packets and no callbacks for PES packets or +sections. + +The functions that implement the callback API need not be re-entrant: when a demux +driver calls one of these functions, the driver is not allowed to call the function again before +the original call returns. If a callback is triggered by a hardware interrupt, it is recommended +to use the Linux “bottom half” mechanism or start a tasklet instead of making the callback +function call directly from a hardware interrupt. + + +
dmx_ts_cb() +DESCRIPTION + + +This function, provided by the client of the demux API, is called from the + demux code. The function is only called when filtering on this TS feed has + been enabled using the start_filtering() function. + + +Any TS packets that match the filter settings are copied to a circular buffer. The + filtered TS packets are delivered to the client using this callback function. The + size of the circular buffer is controlled by the circular_buffer_size parameter + of the set() function in the TS Feed API. It is expected that the buffer1 and + buffer2 callback parameters point to addresses within the circular buffer, but + other implementations are also possible. Note that the called party should not + try to free the memory the buffer1 and buffer2 parameters point to. + + +When this function is called, the buffer1 parameter typically points to the + start of the first undelivered TS packet within a circular buffer. The buffer2 + buffer parameter is normally NULL, except when the received TS packets have + crossed the last address of the circular buffer and ”wrapped” to the beginning + of the buffer. In the latter case the buffer1 parameter would contain an address + within the circular buffer, while the buffer2 parameter would contain the first + address of the circular buffer. + + +The number of bytes delivered with this function (i.e. buffer1_length + + buffer2_length) is usually equal to the value of callback_length parameter + given in the set() function, with one exception: if a timeout occurs before + receiving callback_length bytes of TS data, any undelivered packets are + immediately delivered to the client by calling this function. The timeout + duration is controlled by the set() function in the TS Feed API. + + +If a TS packet is received with errors that could not be fixed by the TS-level + forward error correction (FEC), the Transport_error_indicator flag of the TS + packet header should be set. The TS packet should not be discarded, as + the error can possibly be corrected by a higher layer protocol. If the called + party is slow in processing the callback, it is possible that the circular buffer + eventually fills up. If this happens, the demux driver should discard any TS + packets received while the buffer is full. The error should be indicated to the + client on the next callback by setting the success parameter to the value of + DMX_OVERRUN_ERROR. + + +The type of data returned to the callback can be selected by the new + function int (*set_type) (struct dmx_ts_feed_s* feed, int type, dmx_ts_pes_t + pes_type) which is part of the dmx_ts_feed_s struct (also cf. to the + include file ost/demux.h) The type parameter decides if the raw TS packet + (TS_PACKET) or just the payload (TS_PACKET—TS_PAYLOAD_ONLY) + should be returned. If additionally the TS_DECODER bit is set the stream + will also be sent to the hardware MPEG decoder. In this case, the second + flag decides as what kind of data the stream should be interpreted. The + possible choices are one of DMX_TS_PES_AUDIO, DMX_TS_PES_VIDEO, + DMX_TS_PES_TELETEXT, DMX_TS_PES_SUBTITLE, + DMX_TS_PES_PCR, or DMX_TS_PES_OTHER. + + +SYNOPSIS + + +int dmx_ts_cb(__u8⋆ buffer1, size_t buffer1_length, + __u8⋆ buffer2, size_t buffer2_length, dmx_ts_feed_t⋆ + source, dmx_success_t success); + + +PARAMETERS + + +__u8* buffer1 + +Pointer to the start of the filtered TS packets. + + +size_t buffer1_length + +Length of the TS data in buffer1. + + +__u8* buffer2 + +Pointer to the tail of the filtered TS packets, or NULL. + + +size_t buffer2_length + +Length of the TS data in buffer2. + + +dmx_ts_feed_t* + source + +Indicates which TS feed is the source of the callback. + + +dmx_success_t + success + +Indicates if there was an error in TS reception. + + +RETURNS + + +0 + +Continue filtering. + + +-1 + +Stop filtering - has the same effect as a call to + stop_filtering() on the TS Feed API. + + + +
dmx_section_cb() +DESCRIPTION + + +This function, provided by the client of the demux API, is called from the + demux code. The function is only called when filtering of sections has been + enabled using the function start_filtering() of the section feed API. When the + demux driver has received a complete section that matches at least one section + filter, the client is notified via this callback function. Normally this function is + called for each received section; however, it is also possible to deliver multiple + sections with one callback, for example when the system load is high. If an + error occurs while receiving a section, this function should be called with + the corresponding error type set in the success field, whether or not there is + data to deliver. The Section Feed implementation should maintain a circular + buffer for received sections. However, this is not necessary if the Section Feed + API is implemented as a client of the TS Feed API, because the TS Feed + implementation then buffers the received data. The size of the circular buffer + can be configured using the set() function in the Section Feed API. If there + is no room in the circular buffer when a new section is received, the section + must be discarded. If this happens, the value of the success parameter should + be DMX_OVERRUN_ERROR on the next callback. + + +SYNOPSIS + + +int dmx_section_cb(__u8⋆ buffer1, size_t + buffer1_length, __u8⋆ buffer2, size_t + buffer2_length, dmx_section_filter_t⋆ source, + dmx_success_t success); + + +PARAMETERS + + +__u8* buffer1 + +Pointer to the start of the filtered section, e.g. within the + circular buffer of the demux driver. + + +size_t buffer1_length + +Length of the filtered section data in buffer1, including + headers and CRC. + + +__u8* buffer2 + +Pointer to the tail of the filtered section data, or NULL. + Useful to handle the wrapping of a circular buffer. + + +size_t buffer2_length + +Length of the filtered section data in buffer2, including + headers and CRC. + + +dmx_section_filter_t* + filter + +Indicates the filter that triggered the callback. + + +dmx_success_t + success + +Indicates if there was an error in section reception. + + +RETURNS + + +0 + +Continue filtering. + + +-1 + +Stop filtering - has the same effect as a call to + stop_filtering() on the Section Feed API. + + +
+
+TS Feed API +A TS feed is typically mapped to a hardware PID filter on the demux chip. +Using this API, the client can set the filtering properties to start/stop filtering TS +packets on a particular TS feed. The API is defined as an abstract interface of the type +dmx_ts_feed_t. + +The functions that implement the interface should be defined static or module private. The +client can get the handle of a TS feed API by calling the function allocate_ts_feed() in the +demux API. + + +
set() +DESCRIPTION + + +This function sets the parameters of a TS feed. Any filtering in progress on the + TS feed must be stopped before calling this function. + + +SYNOPSIS + + +int set ( dmx_ts_feed_t⋆ feed, __u16 pid, size_t + callback_length, size_t circular_buffer_size, int + descramble, struct timespec timeout); + + +PARAMETERS + + +dmx_ts_feed_t* feed + +Pointer to the TS feed API and instance data. + + +__u16 pid + +PID value to filter. Only the TS packets carrying the + specified PID will be passed to the API client. + + +size_t + callback_length + +Number of bytes to deliver with each call to the + dmx_ts_cb() callback function. The value of this + parameter should be a multiple of 188. + + +size_t + circular_buffer_size + +Size of the circular buffer for the filtered TS packets. + + +int descramble + +If non-zero, descramble the filtered TS packets. + + +struct timespec + timeout + +Maximum time to wait before delivering received TS + packets to the client. + + +RETURNS + + +0 + +The function was completed without errors. + + +-ENOMEM + +Not enough memory for the requested buffer size. + + +-ENOSYS + +No descrambling facility available for TS. + + +-EINVAL + +Bad parameter. + + + +
start_filtering() +DESCRIPTION + + +Starts filtering TS packets on this TS feed, according to its settings. The PID + value to filter can be set by the API client. All matching TS packets are + delivered asynchronously to the client, using the callback function registered + with allocate_ts_feed(). + + +SYNOPSIS + + +int start_filtering(dmx_ts_feed_t⋆ feed); + + +PARAMETERS + + +dmx_ts_feed_t* feed + +Pointer to the TS feed API and instance data. + + +RETURNS + + +0 + +The function was completed without errors. + + +-EINVAL + +Bad parameter. + + + +
stop_filtering() +DESCRIPTION + + +Stops filtering TS packets on this TS feed. + + +SYNOPSIS + + +int stop_filtering(dmx_ts_feed_t⋆ feed); + + +PARAMETERS + + +dmx_ts_feed_t* feed + +Pointer to the TS feed API and instance data. + + +RETURNS + + +0 + +The function was completed without errors. + + +-EINVAL + +Bad parameter. + + +
+
+Section Feed API +A section feed is a resource consisting of a PID filter and a set of section filters. Using this +API, the client can set the properties of a section feed and to start/stop filtering. The API is +defined as an abstract interface of the type dmx_section_feed_t. The functions that implement +the interface should be defined static or module private. The client can get the handle of +a section feed API by calling the function allocate_section_feed() in the demux +API. + +On demux platforms that provide section filtering in hardware, the Section Feed API +implementation provides a software wrapper for the demux hardware. Other platforms may +support only PID filtering in hardware, requiring that TS packets are converted to sections in +software. In the latter case the Section Feed API implementation can be a client of the TS +Feed API. + + +
+
+set() +DESCRIPTION + + +This function sets the parameters of a section feed. Any filtering in progress on + the section feed must be stopped before calling this function. If descrambling + is enabled, the payload_scrambling_control and address_scrambling_control + fields of received DVB datagram sections should be observed. If either one is + non-zero, the section should be descrambled either in hardware or using the + functions descramble_mac_address() and descramble_section_payload() of the + demux API. Note that according to the MPEG-2 Systems specification, only + the payloads of private sections can be scrambled while the rest of the section + data must be sent in the clear. + + +SYNOPSIS + + +int set(dmx_section_feed_t⋆ feed, __u16 pid, size_t + circular_buffer_size, int descramble, int + check_crc); + + +PARAMETERS + + +dmx_section_feed_t* + feed + +Pointer to the section feed API and instance data. + + +__u16 pid + +PID value to filter; only the TS packets carrying the + specified PID will be accepted. + + +size_t + circular_buffer_size + +Size of the circular buffer for filtered sections. + + +int descramble + +If non-zero, descramble any sections that are scrambled. + + +int check_crc + +If non-zero, check the CRC values of filtered sections. + + +RETURNS + + +0 + +The function was completed without errors. + + +-ENOMEM + +Not enough memory for the requested buffer size. + + +-ENOSYS + +No descrambling facility available for sections. + + +-EINVAL + +Bad parameters. + + + +
allocate_filter() +DESCRIPTION + + +This function is used to allocate a section filter on the demux. It should only be + called when no filtering is in progress on this section feed. If a filter cannot be + allocated, the function fails with -ENOSPC. See in section ?? for the format of + the section filter. + + +The bitfields filter_mask and filter_value should only be modified when no + filtering is in progress on this section feed. filter_mask controls which bits of + filter_value are compared with the section headers/payload. On a binary value + of 1 in filter_mask, the corresponding bits are compared. The filter only accepts + sections that are equal to filter_value in all the tested bit positions. Any changes + to the values of filter_mask and filter_value are guaranteed to take effect only + when the start_filtering() function is called next time. The parent pointer in + the struct is initialized by the API implementation to the value of the feed + parameter. The priv pointer is not used by the API implementation, and can + thus be freely utilized by the caller of this function. Any data pointed to by the + priv pointer is available to the recipient of the dmx_section_cb() function call. + + +While the maximum section filter length (DMX_MAX_FILTER_SIZE) is + currently set at 16 bytes, hardware filters of that size are not available on all + platforms. Therefore, section filtering will often take place first in hardware, + followed by filtering in software for the header bytes that were not covered + by a hardware filter. The filter_mask field can be checked to determine how + many bytes of the section filter are actually used, and if the hardware filter will + suffice. Additionally, software-only section filters can optionally be allocated + to clients when all hardware section filters are in use. Note that on most demux + hardware it is not possible to filter on the section_length field of the section + header – thus this field is ignored, even though it is included in filter_value and + filter_mask fields. + + +SYNOPSIS + + +int allocate_filter(dmx_section_feed_t⋆ feed, + dmx_section_filter_t⋆⋆ filter); + + +PARAMETERS + + +dmx_section_feed_t* + feed + +Pointer to the section feed API and instance data. + + +dmx_section_filter_t** + filter + +Pointer to the allocated filter. + + +RETURNS + + +0 + +The function was completed without errors. + + +-ENOSPC + +No filters of given type and length available. + + +-EINVAL + +Bad parameters. + + + +
release_filter() +DESCRIPTION + + +This function releases all the resources of a previously allocated section filter. + The function should not be called while filtering is in progress on this section + feed. After calling this function, the caller should not try to dereference the + filter pointer. + + +SYNOPSIS + + +int release_filter ( dmx_section_feed_t⋆ feed, + dmx_section_filter_t⋆ filter); + + +PARAMETERS + + +dmx_section_feed_t* + feed + +Pointer to the section feed API and instance data. + + +dmx_section_filter_t* + filter + +I/O Pointer to the instance data of a section filter. + + +RETURNS + + +0 + +The function was completed without errors. + + +-ENODEV + +No such filter allocated. + + +-EINVAL + +Bad parameter. + + + +
start_filtering() +DESCRIPTION + + +Starts filtering sections on this section feed, according to its settings. Sections + are first filtered based on their PID and then matched with the section + filters allocated for this feed. If the section matches the PID filter and + at least one section filter, it is delivered to the API client. The section + is delivered asynchronously using the callback function registered with + allocate_section_feed(). + + +SYNOPSIS + + +int start_filtering ( dmx_section_feed_t⋆ feed ); + + +PARAMETERS + + +dmx_section_feed_t* + feed + +Pointer to the section feed API and instance data. + + +RETURNS + + +0 + +The function was completed without errors. + + +-EINVAL + +Bad parameter. + + + +
stop_filtering() +DESCRIPTION + + +Stops filtering sections on this section feed. Note that any changes to the + filtering parameters (filter_value, filter_mask, etc.) should only be made when + filtering is stopped. + + +SYNOPSIS + + +int stop_filtering ( dmx_section_feed_t⋆ feed ); + + +PARAMETERS + + +dmx_section_feed_t* + feed + +Pointer to the section feed API and instance data. + + +RETURNS + + +0 + +The function was completed without errors. + + +-EINVAL + +Bad parameter. + + + +
diff --git a/Documentation/DocBook/dvb/net.xml b/Documentation/DocBook/dvb/net.xml new file mode 100644 index 000000000000..94e388d94c0d --- /dev/null +++ b/Documentation/DocBook/dvb/net.xml @@ -0,0 +1,12 @@ +DVB Network API +The DVB net device enables feeding of MPE (multi protocol encapsulation) packets +received via DVB into the Linux network protocol stack, e.g. for internet via satellite +applications. It can be accessed through /dev/dvb/adapter0/net0. Data types and +and ioctl definitions can be accessed by including linux/dvb/net.h in your +application. + +
+DVB Net Data Types +To be written… + +
diff --git a/Documentation/DocBook/dvb/video.xml b/Documentation/DocBook/dvb/video.xml new file mode 100644 index 000000000000..7bb287e67c8e --- /dev/null +++ b/Documentation/DocBook/dvb/video.xml @@ -0,0 +1,1971 @@ +DVB Video Device +The DVB video device controls the MPEG2 video decoder of the DVB hardware. It +can be accessed through /dev/dvb/adapter0/video0. Data types and and +ioctl definitions can be accessed by including linux/dvb/video.h in your +application. + +Note that the DVB video device only controls decoding of the MPEG video stream, not +its presentation on the TV or computer screen. On PCs this is typically handled by an +associated video4linux device, e.g. /dev/video, which allows scaling and defining output +windows. + +Some DVB cards don’t have their own MPEG decoder, which results in the omission of +the audio and video device as well as the video4linux device. + +The ioctls that deal with SPUs (sub picture units) and navigation packets are only +supported on some MPEG decoders made for DVD playback. + +
+Video Data Types + +
+video_format_t +The video_format_t data type defined by + + + typedef enum { + VIDEO_FORMAT_4_3, + VIDEO_FORMAT_16_9 + } video_format_t; + +is used in the VIDEO_SET_FORMAT function (??) to tell the driver which aspect ratio +the output hardware (e.g. TV) has. It is also used in the data structures video_status +(??) returned by VIDEO_GET_STATUS (??) and video_event (??) returned by +VIDEO_GET_EVENT (??) which report about the display format of the current video +stream. + +
+ +
+video_display_format_t +In case the display format of the video stream and of the display hardware differ the +application has to specify how to handle the cropping of the picture. This can be done using +the VIDEO_SET_DISPLAY_FORMAT call (??) which accepts + + + typedef enum { + VIDEO_PAN_SCAN, + VIDEO_LETTER_BOX, + VIDEO_CENTER_CUT_OUT + } video_display_format_t; + +as argument. + +
+ +
+video stream source +The video stream source is set through the VIDEO_SELECT_SOURCE call and can take +the following values, depending on whether we are replaying from an internal (demuxer) or +external (user write) source. + + + typedef enum { + VIDEO_SOURCE_DEMUX, + VIDEO_SOURCE_MEMORY + } video_stream_source_t; + +VIDEO_SOURCE_DEMUX selects the demultiplexer (fed either by the frontend or the +DVR device) as the source of the video stream. If VIDEO_SOURCE_MEMORY +is selected the stream comes from the application through the write() system +call. + +
+ +
+video play state +The following values can be returned by the VIDEO_GET_STATUS call representing the +state of video playback. + + + typedef enum { + VIDEO_STOPPED, + VIDEO_PLAYING, + VIDEO_FREEZED + } video_play_state_t; + +
+ +
+struct video_event +The following is the structure of a video event as it is returned by the VIDEO_GET_EVENT +call. + + + struct video_event { + int32_t type; + time_t timestamp; + union { + video_format_t video_format; + } u; + }; + +
+ +
+struct video_status +The VIDEO_GET_STATUS call returns the following structure informing about various +states of the playback operation. + + + struct video_status { + boolean video_blank; + video_play_state_t play_state; + video_stream_source_t stream_source; + video_format_t video_format; + video_displayformat_t display_format; + }; + +If video_blank is set video will be blanked out if the channel is changed or if playback is +stopped. Otherwise, the last picture will be displayed. play_state indicates if the video is +currently frozen, stopped, or being played back. The stream_source corresponds to the seleted +source for the video stream. It can come either from the demultiplexer or from memory. +The video_format indicates the aspect ratio (one of 4:3 or 16:9) of the currently +played video stream. Finally, display_format corresponds to the selected cropping +mode in case the source video format is not the same as the format of the output +device. + +
+ +
+struct video_still_picture +An I-frame displayed via the VIDEO_STILLPICTURE call is passed on within the +following structure. + + + /⋆ pointer to and size of a single iframe in memory ⋆/ + struct video_still_picture { + char ⋆iFrame; + int32_t size; + }; + +
+ +
+video capabilities +A call to VIDEO_GET_CAPABILITIES returns an unsigned integer with the following +bits set according to the hardwares capabilities. + + + /⋆ bit definitions for capabilities: ⋆/ + /⋆ can the hardware decode MPEG1 and/or MPEG2? ⋆/ + #define VIDEO_CAP_MPEG1 1 + #define VIDEO_CAP_MPEG2 2 + /⋆ can you send a system and/or program stream to video device? + (you still have to open the video and the audio device but only + send the stream to the video device) ⋆/ + #define VIDEO_CAP_SYS 4 + #define VIDEO_CAP_PROG 8 + /⋆ can the driver also handle SPU, NAVI and CSS encoded data? + (CSS API is not present yet) ⋆/ + #define VIDEO_CAP_SPU 16 + #define VIDEO_CAP_NAVI 32 + #define VIDEO_CAP_CSS 64 + +
+ +
+video system +A call to VIDEO_SET_SYSTEM sets the desired video system for TV output. The +following system types can be set: + + + typedef enum { + VIDEO_SYSTEM_PAL, + VIDEO_SYSTEM_NTSC, + VIDEO_SYSTEM_PALN, + VIDEO_SYSTEM_PALNc, + VIDEO_SYSTEM_PALM, + VIDEO_SYSTEM_NTSC60, + VIDEO_SYSTEM_PAL60, + VIDEO_SYSTEM_PALM60 + } video_system_t; + +
+ +
+struct video_highlight +Calling the ioctl VIDEO_SET_HIGHLIGHTS posts the SPU highlight information. The +call expects the following format for that information: + + + typedef + struct video_highlight { + boolean active; /⋆ 1=show highlight, 0=hide highlight ⋆/ + uint8_t contrast1; /⋆ 7- 4 Pattern pixel contrast ⋆/ + /⋆ 3- 0 Background pixel contrast ⋆/ + uint8_t contrast2; /⋆ 7- 4 Emphasis pixel-2 contrast ⋆/ + /⋆ 3- 0 Emphasis pixel-1 contrast ⋆/ + uint8_t color1; /⋆ 7- 4 Pattern pixel color ⋆/ + /⋆ 3- 0 Background pixel color ⋆/ + uint8_t color2; /⋆ 7- 4 Emphasis pixel-2 color ⋆/ + /⋆ 3- 0 Emphasis pixel-1 color ⋆/ + uint32_t ypos; /⋆ 23-22 auto action mode ⋆/ + /⋆ 21-12 start y ⋆/ + /⋆ 9- 0 end y ⋆/ + uint32_t xpos; /⋆ 23-22 button color number ⋆/ + /⋆ 21-12 start x ⋆/ + /⋆ 9- 0 end x ⋆/ + } video_highlight_t; + + +
+
+video SPU +Calling VIDEO_SET_SPU deactivates or activates SPU decoding, according to the +following format: + + + typedef + struct video_spu { + boolean active; + int stream_id; + } video_spu_t; + + +
+
+video SPU palette +The following structure is used to set the SPU palette by calling VIDEO_SPU_PALETTE: + + + typedef + struct video_spu_palette{ + int length; + uint8_t ⋆palette; + } video_spu_palette_t; + + +
+
+video NAVI pack +In order to get the navigational data the following structure has to be passed to the ioctl +VIDEO_GET_NAVI: + + + typedef + struct video_navi_pack{ + int length; /⋆ 0 ... 1024 ⋆/ + uint8_t data[1024]; + } video_navi_pack_t; + +
+ + +
+video attributes +The following attributes can be set by a call to VIDEO_SET_ATTRIBUTES: + + + typedef uint16_t video_attributes_t; + /⋆ bits: descr. ⋆/ + /⋆ 15-14 Video compression mode (0=MPEG-1, 1=MPEG-2) ⋆/ + /⋆ 13-12 TV system (0=525/60, 1=625/50) ⋆/ + /⋆ 11-10 Aspect ratio (0=4:3, 3=16:9) ⋆/ + /⋆ 9- 8 permitted display mode on 4:3 monitor (0=both, 1=only pan-sca ⋆/ + /⋆ 7 line 21-1 data present in GOP (1=yes, 0=no) ⋆/ + /⋆ 6 line 21-2 data present in GOP (1=yes, 0=no) ⋆/ + /⋆ 5- 3 source resolution (0=720x480/576, 1=704x480/576, 2=352x480/57 ⋆/ + /⋆ 2 source letterboxed (1=yes, 0=no) ⋆/ + /⋆ 0 film/camera mode (0=camera, 1=film (625/50 only)) ⋆/ + +
+ + +
+Video Function Calls + + +
+open() +DESCRIPTION + + +This system call opens a named video device (e.g. /dev/dvb/adapter0/video0) + for subsequent use. +When an open() call has succeeded, the device will be ready for use. + The significance of blocking or non-blocking mode is described in the + documentation for functions where there is a difference. It does not affect the + semantics of the open() call itself. A device opened in blocking mode can later + be put into non-blocking mode (and vice versa) using the F_SETFL command + of the fcntl system call. This is a standard system call, documented in the Linux + manual page for fcntl. Only one user can open the Video Device in O_RDWR + mode. All other attempts to open the device in this mode will fail, and an + error-code will be returned. If the Video Device is opened in O_RDONLY + mode, the only ioctl call that can be used is VIDEO_GET_STATUS. All other + call will return an error code. + + + +SYNOPSIS + + +int open(const char ⋆deviceName, int flags); + + +PARAMETERS + + +const char + *deviceName + +Name of specific video device. + + +int flags + +A bit-wise OR of the following flags: + + + +O_RDONLY read-only access + + + +O_RDWR read/write access + + + +O_NONBLOCK open in non-blocking mode + + + +(blocking mode is the default) + + +ERRORS + + +ENODEV + +Device driver not loaded/available. + + +EINTERNAL + +Internal error. + + +EBUSY + +Device or resource busy. + + +EINVAL + +Invalid argument. + + + +
+
+close() +DESCRIPTION + + +This system call closes a previously opened video device. + + +SYNOPSIS + + +int close(int fd); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + + +
+
+write() +DESCRIPTION + + +This system call can only be used if VIDEO_SOURCE_MEMORY is selected + in the ioctl call VIDEO_SELECT_SOURCE. The data provided shall be in + PES format, unless the capability allows other formats. If O_NONBLOCK is + not specified the function will block until buffer space is available. The amount + of data to be transferred is implied by count. + + +SYNOPSIS + + +size_t write(int fd, const void ⋆buf, size_t count); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +void *buf + +Pointer to the buffer containing the PES data. + + +size_t count + +Size of buf. + + +ERRORS + + +EPERM + +Mode VIDEO_SOURCE_MEMORY not selected. + + +ENOMEM + +Attempted to write more data than the internal buffer can + hold. + + +EBADF + +fd is not a valid open file descriptor. + + + +
VIDEO_STOP +DESCRIPTION + + +This ioctl call asks the Video Device to stop playing the current stream. + Depending on the input parameter, the screen can be blanked out or displaying + the last decoded frame. + + +SYNOPSIS + + +int ioctl(fd, int request = VIDEO_STOP, boolean + mode); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_STOP for this command. + + +Boolean mode + +Indicates how the screen shall be handled. + + + +TRUE: Blank screen when stop. + + + +FALSE: Show last decoded frame. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINTERNAL + +Internal error, possibly in the communication with the + DVB subsystem. + + + +
VIDEO_PLAY +DESCRIPTION + + +This ioctl call asks the Video Device to start playing a video stream from the + selected source. + + +SYNOPSIS + + +int ioctl(fd, int request = VIDEO_PLAY); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_PLAY for this command. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINTERNAL + +Internal error, possibly in the communication with the + DVB subsystem. + + + +
VIDEO_FREEZE +DESCRIPTION + + +This ioctl call suspends the live video stream being played. Decoding + and playing are frozen. It is then possible to restart the decoding + and playing process of the video stream using the VIDEO_CONTINUE + command. If VIDEO_SOURCE_MEMORY is selected in the ioctl call + VIDEO_SELECT_SOURCE, the DVB subsystem will not decode any more + data until the ioctl call VIDEO_CONTINUE or VIDEO_PLAY is performed. + + +SYNOPSIS + + +int ioctl(fd, int request = VIDEO_FREEZE); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_FREEZE for this command. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINTERNAL + +Internal error, possibly in the communication with the + DVB subsystem. + + + +
VIDEO_CONTINUE +DESCRIPTION + + +This ioctl call restarts decoding and playing processes of the video stream + which was played before a call to VIDEO_FREEZE was made. + + +SYNOPSIS + + +int ioctl(fd, int request = VIDEO_CONTINUE); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_CONTINUE for this command. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINTERNAL + +Internal error, possibly in the communication with the + DVB subsystem. + + + +
VIDEO_SELECT_SOURCE +DESCRIPTION + + +This ioctl call informs the video device which source shall be used for the input + data. The possible sources are demux or memory. If memory is selected, the + data is fed to the video device through the write command. + + +SYNOPSIS + + +int ioctl(fd, int request = VIDEO_SELECT_SOURCE, + video_stream_source_t source); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_SELECT_SOURCE for this command. + + +video_stream_source_t + source + +Indicates which source shall be used for the Video stream. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINTERNAL + +Internal error, possibly in the communication with the + DVB subsystem. + + + +
VIDEO_SET_BLANK +DESCRIPTION + + +This ioctl call asks the Video Device to blank out the picture. + + +SYNOPSIS + + +int ioctl(fd, int request = VIDEO_SET_BLANK, boolean + mode); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_SET_BLANK for this command. + + +boolean mode + +TRUE: Blank screen when stop. + + + +FALSE: Show last decoded frame. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINTERNAL + +Internal error, possibly in the communication with the + DVB subsystem. + + +EINVAL + +Illegal input parameter + + + +
VIDEO_GET_STATUS +DESCRIPTION + + +This ioctl call asks the Video Device to return the current status of the device. + + +SYNOPSIS + + + int ioctl(fd, int request = VIDEO_GET_STATUS, struct + video_status ⋆status); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_GET_STATUS for this command. + + +struct video_status + *status + +Returns the current status of the Video Device. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINTERNAL + +Internal error, possibly in the communication with the + DVB subsystem. + + +EFAULT + +status points to invalid address + + + +
VIDEO_GET_EVENT +DESCRIPTION + + +This ioctl call returns an event of type video_event if available. If an event is + not available, the behavior depends on whether the device is in blocking or + non-blocking mode. In the latter case, the call fails immediately with errno + set to EWOULDBLOCK. In the former case, the call blocks until an event + becomes available. The standard Linux poll() and/or select() system calls can + be used with the device file descriptor to watch for new events. For select(), + the file descriptor should be included in the exceptfds argument, and for + poll(), POLLPRI should be specified as the wake-up condition. Read-only + permissions are sufficient for this ioctl call. + + +SYNOPSIS + + + int ioctl(fd, int request = VIDEO_GET_EVENT, struct + video_event ⋆ev); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_GET_EVENT for this command. + + +struct video_event + *ev + +Points to the location where the event, if any, is to be + stored. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EFAULT + +ev points to invalid address + + +EWOULDBLOCK + +There is no event pending, and the device is in + non-blocking mode. + + +EOVERFLOW + + + + +Overflow in event queue - one or more events were lost. + + + +
VIDEO_SET_DISPLAY_FORMAT +DESCRIPTION + + +This ioctl call asks the Video Device to select the video format to be applied + by the MPEG chip on the video. + + +SYNOPSIS + + + int ioctl(fd, int request = + VIDEO_SET_DISPLAY_FORMAT, video_display_format_t + format); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_SET_DISPLAY_FORMAT for this + command. + + +video_display_format_t + format + +Selects the video format to be used. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINTERNAL + +Internal error. + + +EINVAL + +Illegal parameter format. + + + +
VIDEO_STILLPICTURE +DESCRIPTION + + +This ioctl call asks the Video Device to display a still picture (I-frame). The + input data shall contain an I-frame. If the pointer is NULL, then the current + displayed still picture is blanked. + + +SYNOPSIS + + +int ioctl(fd, int request = VIDEO_STILLPICTURE, + struct video_still_picture ⋆sp); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_STILLPICTURE for this command. + + +struct + video_still_picture + *sp + +Pointer to a location where an I-frame and size is stored. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINTERNAL + +Internal error. + + +EFAULT + +sp points to an invalid iframe. + + + +
VIDEO_FAST_FORWARD +DESCRIPTION + + +This ioctl call asks the Video Device to skip decoding of N number of I-frames. + This call can only be used if VIDEO_SOURCE_MEMORY is selected. + + +SYNOPSIS + + +int ioctl(fd, int request = VIDEO_FAST_FORWARD, int + nFrames); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_FAST_FORWARD for this command. + + +int nFrames + +The number of frames to skip. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINTERNAL + +Internal error. + + +EPERM + +Mode VIDEO_SOURCE_MEMORY not selected. + + +EINVAL + +Illegal parameter format. + + + +
VIDEO_SLOWMOTION +DESCRIPTION + + +This ioctl call asks the video device to repeat decoding frames N number of + times. This call can only be used if VIDEO_SOURCE_MEMORY is selected. + + +SYNOPSIS + + +int ioctl(fd, int request = VIDEO_SLOWMOTION, int + nFrames); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_SLOWMOTION for this command. + + +int nFrames + +The number of times to repeat each frame. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINTERNAL + +Internal error. + + +EPERM + +Mode VIDEO_SOURCE_MEMORY not selected. + + +EINVAL + +Illegal parameter format. + + + +
VIDEO_GET_CAPABILITIES +DESCRIPTION + + +This ioctl call asks the video device about its decoding capabilities. On success + it returns and integer which has bits set according to the defines in section ??. + + +SYNOPSIS + + +int ioctl(fd, int request = VIDEO_GET_CAPABILITIES, + unsigned int ⋆cap); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_GET_CAPABILITIES for this + command. + + +unsigned int *cap + +Pointer to a location where to store the capability + information. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EFAULT + +cap points to an invalid iframe. + + + +
VIDEO_SET_ID +DESCRIPTION + + +This ioctl selects which sub-stream is to be decoded if a program or system + stream is sent to the video device. + + +SYNOPSIS + + +int ioctl(int fd, int request = VIDEO_SET_ID, int + id); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_SET_ID for this command. + + +int id + +video sub-stream id + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EINTERNAL + +Internal error. + + +EINVAL + +Invalid sub-stream id. + + + +
VIDEO_CLEAR_BUFFER +DESCRIPTION + + +This ioctl call clears all video buffers in the driver and in the decoder hardware. + + +SYNOPSIS + + +int ioctl(fd, int request = VIDEO_CLEAR_BUFFER); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_CLEAR_BUFFER for this command. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + + +
VIDEO_SET_STREAMTYPE +DESCRIPTION + + +This ioctl tells the driver which kind of stream to expect being written to it. If + this call is not used the default of video PES is used. Some drivers might not + support this call and always expect PES. + + +SYNOPSIS + + +int ioctl(fd, int request = VIDEO_SET_STREAMTYPE, + int type); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_SET_STREAMTYPE for this command. + + +int type + +stream type + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINVAL + +type is not a valid or supported stream type. + + + +
VIDEO_SET_FORMAT +DESCRIPTION + + +This ioctl sets the screen format (aspect ratio) of the connected output device + (TV) so that the output of the decoder can be adjusted accordingly. + + +SYNOPSIS + + + int ioctl(fd, int request = VIDEO_SET_FORMAT, + video_format_t format); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_SET_FORMAT for this command. + + +video_format_t + format + +video format of TV as defined in section ??. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINVAL + +format is not a valid video format. + + + +
VIDEO_SET_SYSTEM +DESCRIPTION + + +This ioctl sets the television output format. The format (see section ??) may + vary from the color format of the displayed MPEG stream. If the hardware is + not able to display the requested format the call will return an error. + + +SYNOPSIS + + + int ioctl(fd, int request = VIDEO_SET_SYSTEM , + video_system_t system); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_SET_FORMAT for this command. + + +video_system_t + system + +video system of TV output. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINVAL + +system is not a valid or supported video system. + + + +
VIDEO_SET_HIGHLIGHT +DESCRIPTION + + +This ioctl sets the SPU highlight information for the menu access of a DVD. + + +SYNOPSIS + + + int ioctl(fd, int request = VIDEO_SET_HIGHLIGHT + ,video_highlight_t ⋆vhilite) + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_SET_HIGHLIGHT for this command. + + +video_highlight_t + *vhilite + +SPU Highlight information according to section ??. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor. + + +EINVAL + +input is not a valid highlight setting. + + + +
VIDEO_SET_SPU +DESCRIPTION + + +This ioctl activates or deactivates SPU decoding in a DVD input stream. It can + only be used, if the driver is able to handle a DVD stream. + + +SYNOPSIS + + + int ioctl(fd, int request = VIDEO_SET_SPU , + video_spu_t ⋆spu) + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_SET_SPU for this command. + + +video_spu_t *spu + +SPU decoding (de)activation and subid setting according + to section ??. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINVAL + +input is not a valid spu setting or driver cannot handle + SPU. + + + +
VIDEO_SET_SPU_PALETTE +DESCRIPTION + + +This ioctl sets the SPU color palette. + + +SYNOPSIS + + + int ioctl(fd, int request = VIDEO_SET_SPU_PALETTE + ,video_spu_palette_t ⋆palette ) + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_SET_SPU_PALETTE for this command. + + +video_spu_palette_t + *palette + +SPU palette according to section ??. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINVAL + +input is not a valid palette or driver doesn’t handle SPU. + + + +
VIDEO_GET_NAVI +DESCRIPTION + + +This ioctl returns navigational information from the DVD stream. This is + especially needed if an encoded stream has to be decoded by the hardware. + + +SYNOPSIS + + + int ioctl(fd, int request = VIDEO_GET_NAVI , + video_navi_pack_t ⋆navipack) + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_GET_NAVI for this command. + + +video_navi_pack_t + *navipack + +PCI or DSI pack (private stream 2) according to section + ??. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EFAULT + +driver is not able to return navigational information + + + +
VIDEO_SET_ATTRIBUTES +DESCRIPTION + + +This ioctl is intended for DVD playback and allows you to set certain + information about the stream. Some hardware may not need this information, + but the call also tells the hardware to prepare for DVD playback. + + +SYNOPSIS + + + int ioctl(fd, int request = VIDEO_SET_ATTRIBUTE + ,video_attributes_t vattr) + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals VIDEO_SET_ATTRIBUTE for this command. + + +video_attributes_t + vattr + +video attributes according to section ??. + + +ERRORS + + +EBADF + +fd is not a valid open file descriptor + + +EINVAL + +input is not a valid attribute setting. + + +
diff --git a/Documentation/DocBook/media-entities.tmpl b/Documentation/DocBook/media-entities.tmpl new file mode 100644 index 000000000000..0eb43c1970bb --- /dev/null +++ b/Documentation/DocBook/media-entities.tmpl @@ -0,0 +1,364 @@ + + + +close()"> +ioctl()"> +mmap()"> +munmap()"> +open()"> +poll()"> +read()"> +select()"> +write()"> + + +VIDIOC_CROPCAP"> +VIDIOC_DBG_G_CHIP_IDENT"> +VIDIOC_DBG_G_REGISTER"> +VIDIOC_DBG_S_REGISTER"> +VIDIOC_DQBUF"> +VIDIOC_ENCODER_CMD"> +VIDIOC_ENUMAUDIO"> +VIDIOC_ENUMAUDOUT"> +VIDIOC_ENUMINPUT"> +VIDIOC_ENUMOUTPUT"> +VIDIOC_ENUMSTD"> +VIDIOC_ENUM_FMT"> +VIDIOC_ENUM_FRAMEINTERVALS"> +VIDIOC_ENUM_FRAMESIZES"> +VIDIOC_G_AUDIO"> +VIDIOC_G_AUDOUT"> +VIDIOC_G_CROP"> +VIDIOC_G_CTRL"> +VIDIOC_G_ENC_INDEX"> +VIDIOC_G_EXT_CTRLS"> +VIDIOC_G_FBUF"> +VIDIOC_G_FMT"> +VIDIOC_G_FREQUENCY"> +VIDIOC_G_INPUT"> +VIDIOC_G_JPEGCOMP"> +VIDIOC_G_MPEGCOMP"> +VIDIOC_G_MODULATOR"> +VIDIOC_G_OUTPUT"> +VIDIOC_G_PARM"> +VIDIOC_G_PRIORITY"> +VIDIOC_G_SLICED_VBI_CAP"> +VIDIOC_G_STD"> +VIDIOC_G_TUNER"> +VIDIOC_LOG_STATUS"> +VIDIOC_OVERLAY"> +VIDIOC_QBUF"> +VIDIOC_QUERYBUF"> +VIDIOC_QUERYCAP"> +VIDIOC_QUERYCTRL"> +VIDIOC_QUERYMENU"> +VIDIOC_QUERYSTD"> +VIDIOC_REQBUFS"> +VIDIOC_STREAMOFF"> +VIDIOC_STREAMON"> +VIDIOC_S_AUDIO"> +VIDIOC_S_AUDOUT"> +VIDIOC_S_CROP"> +VIDIOC_S_CTRL"> +VIDIOC_S_EXT_CTRLS"> +VIDIOC_S_FBUF"> +VIDIOC_S_FMT"> +VIDIOC_S_FREQUENCY"> +VIDIOC_S_HW_FREQ_SEEK"> +VIDIOC_S_INPUT"> +VIDIOC_S_JPEGCOMP"> +VIDIOC_S_MPEGCOMP"> +VIDIOC_S_MODULATOR"> +VIDIOC_S_OUTPUT"> +VIDIOC_S_PARM"> +VIDIOC_S_PRIORITY"> +VIDIOC_S_STD"> +VIDIOC_S_TUNER"> +VIDIOC_TRY_ENCODER_CMD"> +VIDIOC_TRY_EXT_CTRLS"> +VIDIOC_TRY_FMT"> + + +v4l2_std_id"> + + +v4l2_buf_type"> +v4l2_colorspace"> +v4l2_ctrl_type"> +v4l2_exposure_auto_type"> +v4l2_field"> +v4l2_frmivaltypes"> +v4l2_frmsizetypes"> +v4l2_memory"> +v4l2_mpeg_audio_ac3_bitrate"> +v4l2_mpeg_audio_crc"> +v4l2_mpeg_audio_emphasis"> +v4l2_mpeg_audio_encoding"> +v4l2_mpeg_audio_l1_bitrate"> +v4l2_mpeg_audio_l2_bitrate"> +v4l2_mpeg_audio_l3_bitrate"> +v4l2_mpeg_audio_mode"> +v4l2_mpeg_audio_mode_extension"> +v4l2_mpeg_audio_sampling_freq"> +v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type"> +v4l2_mpeg_cx2341x_video_luma_spatial_filter_type"> +v4l2_mpeg_cx2341x_video_median_filter_type"> +v4l2_mpeg_cx2341x_video_spatial_filter_mode"> +v4l2_mpeg_cx2341x_video_temporal_filter_mode"> +v4l2_mpeg_stream_type"> +v4l2_mpeg_stream_vbi_fmt"> +v4l2_mpeg_video_aspect"> +v4l2_mpeg_video_bitrate_mode"> +v4l2_mpeg_video_encoding"> +v4l2_power_line_frequency"> +v4l2_priority"> +v4l2_tuner_type"> +v4l2_preemphasis"> + + +v4l2_audio"> +v4l2_audioout"> +v4l2_buffer"> +v4l2_capability"> +v4l2_captureparm"> +v4l2_clip"> +v4l2_control"> +v4l2_crop"> +v4l2_cropcap"> +v4l2_dbg_chip_ident"> +v4l2_dbg_match"> +v4l2_dbg_register"> +v4l2_enc_idx"> +v4l2_enc_idx_entry"> +v4l2_encoder_cmd"> +v4l2_ext_control"> +v4l2_ext_controls"> +v4l2_fmtdesc"> +v4l2_format"> +v4l2_fract"> +v4l2_framebuffer"> +v4l2_frequency"> +v4l2_frmival_stepwise"> +v4l2_frmivalenum"> +v4l2_frmsize_discrete"> +v4l2_frmsize_stepwise"> +v4l2_frmsizeenum"> +v4l2_hw_freq_seek"> +v4l2_input"> +v4l2_jpegcompression"> +v4l2_modulator"> +v4l2_mpeg_vbi_fmt_ivtv"> +v4l2_output"> +v4l2_outputparm"> +v4l2_pix_format"> +v4l2_queryctrl"> +v4l2_querymenu"> +v4l2_rect"> +v4l2_requestbuffers"> +v4l2_sliced_vbi_cap"> +v4l2_sliced_vbi_data"> +v4l2_sliced_vbi_format"> +v4l2_standard"> +v4l2_streamparm"> +v4l2_timecode"> +v4l2_tuner"> +v4l2_vbi_format"> +v4l2_window"> + + +EACCES error code"> +EAGAIN error code"> +EBADF error code"> +EBUSY error code"> +EFAULT error code"> +EIO error code"> +EINTR error code"> +EINVAL error code"> +ENFILE error code"> +ENOMEM error code"> +ENOSPC error code"> +ENOTTY error code"> +ENXIO error code"> +EMFILE error code"> +EPERM error code"> +ERANGE error code"> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Documentation/DocBook/media-indices.tmpl b/Documentation/DocBook/media-indices.tmpl new file mode 100644 index 000000000000..9e30a236d74f --- /dev/null +++ b/Documentation/DocBook/media-indices.tmpl @@ -0,0 +1,85 @@ + + +List of Types +v4l2_std_id +enum v4l2_buf_type +enum v4l2_colorspace +enum v4l2_ctrl_type +enum v4l2_exposure_auto_type +enum v4l2_field +enum v4l2_frmivaltypes +enum v4l2_frmsizetypes +enum v4l2_memory +enum v4l2_mpeg_audio_ac3_bitrate +enum v4l2_mpeg_audio_crc +enum v4l2_mpeg_audio_emphasis +enum v4l2_mpeg_audio_encoding +enum v4l2_mpeg_audio_l1_bitrate +enum v4l2_mpeg_audio_l2_bitrate +enum v4l2_mpeg_audio_l3_bitrate +enum v4l2_mpeg_audio_mode +enum v4l2_mpeg_audio_mode_extension +enum v4l2_mpeg_audio_sampling_freq +enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type +enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type +enum v4l2_mpeg_cx2341x_video_median_filter_type +enum v4l2_mpeg_cx2341x_video_spatial_filter_mode +enum v4l2_mpeg_cx2341x_video_temporal_filter_mode +enum v4l2_mpeg_stream_type +enum v4l2_mpeg_stream_vbi_fmt +enum v4l2_mpeg_video_aspect +enum v4l2_mpeg_video_bitrate_mode +enum v4l2_mpeg_video_encoding +enum v4l2_power_line_frequency +enum v4l2_priority +enum v4l2_tuner_type +enum v4l2_preemphasis +struct v4l2_audio +struct v4l2_audioout +struct v4l2_buffer +struct v4l2_capability +struct v4l2_captureparm +struct v4l2_clip +struct v4l2_control +struct v4l2_crop +struct v4l2_cropcap +struct v4l2_dbg_chip_ident +struct v4l2_dbg_match +struct v4l2_dbg_register +struct v4l2_enc_idx +struct v4l2_enc_idx_entry +struct v4l2_encoder_cmd +struct v4l2_ext_control +struct v4l2_ext_controls +struct v4l2_fmtdesc +struct v4l2_format +struct v4l2_fract +struct v4l2_framebuffer +struct v4l2_frequency +struct v4l2_frmival_stepwise +struct v4l2_frmivalenum +struct v4l2_frmsize_discrete +struct v4l2_frmsize_stepwise +struct v4l2_frmsizeenum +struct v4l2_hw_freq_seek +struct v4l2_input +struct v4l2_jpegcompression +struct v4l2_modulator +struct v4l2_mpeg_vbi_fmt_ivtv +struct v4l2_output +struct v4l2_outputparm +struct v4l2_pix_format +struct v4l2_queryctrl +struct v4l2_querymenu +struct v4l2_rect +struct v4l2_requestbuffers +struct v4l2_sliced_vbi_cap +struct v4l2_sliced_vbi_data +struct v4l2_sliced_vbi_format +struct v4l2_standard +struct v4l2_streamparm +struct v4l2_timecode +struct v4l2_tuner +struct v4l2_vbi_format +struct v4l2_window + diff --git a/Documentation/DocBook/media.tmpl b/Documentation/DocBook/media.tmpl new file mode 100644 index 000000000000..eea564bb12cb --- /dev/null +++ b/Documentation/DocBook/media.tmpl @@ -0,0 +1,112 @@ + + %media-entities; + + + + +open()."> +2C"> +Return ValueOn success 0 is returned, on error -1 and the errno variable is set appropriately:"> +2"> + + +"> +"> +"> + + +http://www.linuxtv.org/lists.php"> + + +http://linuxtv.org/repo/"> +]> + + + +LINUX MEDIA INFRASTRUCTURE API + + + 2009 + LinuxTV Developers + + + + +Permission is granted to copy, distribute and/or modify +this document under the terms of the GNU Free Documentation License, +Version 1.1 or any later version published by the Free Software +Foundation. A copy of the license is included in the chapter entitled +"GNU Free Documentation License" + + + + + + + + Introduction + + This document covers the Linux Kernel to Userspace API's used by + video and radio straming devices, including video cameras, + analog and digital TV receiver cards, AM/FM receiver cards, + streaming capture devices. + It is divided into three parts. + The first part covers radio, capture, + cameras and analog TV devices. + The second part covers the + API used for digital TV and Internet reception via one of the + several digital tv standards. While it is called as DVB API, + in fact it covers several different video standards including + DVB-T, DVB-S, DVB-C and ATSC. The API is currently being updated + to documment support also for DVB-S2, ISDB-T and ISDB-S. + The third part covers other API's used by all media infrastructure devices + For additional information and for the latest development code, + see: http://linuxtv.org. + For discussing improvements, reporting troubles, sending new drivers, etc, please mail to: Linux Media Mailing List (LMML).. + + + + +&sub-v4l2; + + +&sub-dvbapi; + + + + + +Mauro +Chehab +Carvalho +
mchehab@redhat.com
 +Initial version. + + + + 2009 + Mauro Carvalho Chehab + + + + + +1.0.0 +2009-09-06 +mcc +Initial revision + + + + +Other API's used by media infrastructure drivers + +&sub-remote_controllers; + + + +&sub-fdl-appendix; + + diff --git a/Documentation/DocBook/stylesheet.xsl b/Documentation/DocBook/stylesheet.xsl index 974e17ccf106..254c1d5d2e50 100644 --- a/Documentation/DocBook/stylesheet.xsl +++ b/Documentation/DocBook/stylesheet.xsl @@ -3,6 +3,7 @@ 1 ansi 80 +0 2 diff --git a/Documentation/DocBook/v4l/.gitignore b/Documentation/DocBook/v4l/.gitignore new file mode 100644 index 000000000000..d7ec32eafac9 --- /dev/null +++ b/Documentation/DocBook/v4l/.gitignore @@ -0,0 +1 @@ +!*.xml diff --git a/Documentation/DocBook/v4l/biblio.xml b/Documentation/DocBook/v4l/biblio.xml new file mode 100644 index 000000000000..afc8a0dd2601 --- /dev/null +++ b/Documentation/DocBook/v4l/biblio.xml @@ -0,0 +1,188 @@ + + References + + + EIA 608-B + + Electronic Industries Alliance (http://www.eia.org) + + EIA 608-B "Recommended Practice for Line 21 Data +Service" + + + + EN 300 294 + + European Telecommunication Standards Institute +(http://www.etsi.org) + + EN 300 294 "625-line television Wide Screen Signalling +(WSS)" + + + + ETS 300 231 + + European Telecommunication Standards Institute +(http://www.etsi.org) + + ETS 300 231 "Specification of the domestic video +Programme Delivery Control system (PDC)" + + + + ETS 300 706 + + European Telecommunication Standards Institute +(http://www.etsi.org) + + ETS 300 706 "Enhanced Teletext specification" + + + + ISO 13818-1 + + International Telecommunication Union (http://www.itu.ch), International +Organisation for Standardisation (http://www.iso.ch) + + ITU-T Rec. H.222.0 | ISO/IEC 13818-1 "Information +technology — Generic coding of moving pictures and associated +audio information: Systems" + + + + ISO 13818-2 + + International Telecommunication Union (http://www.itu.ch), International +Organisation for Standardisation (http://www.iso.ch) + + ITU-T Rec. H.262 | ISO/IEC 13818-2 "Information +technology — Generic coding of moving pictures and associated +audio information: Video" + + + + ITU BT.470 + + International Telecommunication Union (http://www.itu.ch) + + ITU-R Recommendation BT.470-6 "Conventional Television +Systems" + + + + ITU BT.601 + + International Telecommunication Union (http://www.itu.ch) + + ITU-R Recommendation BT.601-5 "Studio Encoding Parameters +of Digital Television for Standard 4:3 and Wide-Screen 16:9 Aspect +Ratios" + + + + ITU BT.653 + + International Telecommunication Union (http://www.itu.ch) + + ITU-R Recommendation BT.653-3 "Teletext systems" + + + + ITU BT.709 + + International Telecommunication Union (http://www.itu.ch) + + ITU-R Recommendation BT.709-5 "Parameter values for the +HDTV standards for production and international programme +exchange" + + + + ITU BT.1119 + + International Telecommunication Union (http://www.itu.ch) + + ITU-R Recommendation BT.1119 "625-line +television Wide Screen Signalling (WSS)" + + + + JFIF + + Independent JPEG Group (http://www.ijg.org) + + JPEG File Interchange Format + Version 1.02 + + + + SMPTE 12M + + Society of Motion Picture and Television Engineers +(http://www.smpte.org) + + SMPTE 12M-1999 "Television, Audio and Film - Time and +Control Code" + + + + SMPTE 170M + + Society of Motion Picture and Television Engineers +(http://www.smpte.org) + + SMPTE 170M-1999 "Television - Composite Analog Video +Signal - NTSC for Studio Applications" + + + + SMPTE 240M + + Society of Motion Picture and Television Engineers +(http://www.smpte.org) + + SMPTE 240M-1999 "Television - Signal Parameters - +1125-Line High-Definition Production" + + + + EN 50067 + + European Committee for Electrotechnical Standardization +(http://www.cenelec.eu) + + Specification of the radio data system (RDS) for VHF/FM sound broadcasting +in the frequency range from 87,5 to 108,0 MHz + + + + NRSC-4 + + National Radio Systems Committee +(http://www.nrscstandards.org) + + NTSC-4: United States RBDS Standard + + + + + diff --git a/Documentation/DocBook/v4l/capture.c.xml b/Documentation/DocBook/v4l/capture.c.xml new file mode 100644 index 000000000000..1c5c49a2de59 --- /dev/null +++ b/Documentation/DocBook/v4l/capture.c.xml @@ -0,0 +1,659 @@ + +/* + * V4L2 video capture example + * + * This program can be used and distributed without restrictions. + * + * This program is provided with the V4L2 API + * see http://linuxtv.org/docs.php for more information + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <assert.h> + +#include <getopt.h> /* getopt_long() */ + +#include <fcntl.h> /* low-level i/o */ +#include <unistd.h> +#include <errno.h> +#include <sys/stat.h> +#include <sys/types.h> +#include <sys/time.h> +#include <sys/mman.h> +#include <sys/ioctl.h> + +#include <linux/videodev2.h> + +#define CLEAR(x) memset(&(x), 0, sizeof(x)) + +enum io_method { + IO_METHOD_READ, + IO_METHOD_MMAP, + IO_METHOD_USERPTR, +}; + +struct buffer { + void *start; + size_t length; +}; + +static char *dev_name; +static enum io_method io = IO_METHOD_MMAP; +static int fd = -1; +struct buffer *buffers; +static unsigned int n_buffers; +static int out_buf; +static int force_format; +static int frame_count = 70; + +static void errno_exit(const char *s) +{ + fprintf(stderr, "%s error %d, %s\n", s, errno, strerror(errno)); + exit(EXIT_FAILURE); +} + +static int xioctl(int fh, int request, void *arg) +{ + int r; + + do { + r = ioctl(fh, request, arg); + } while (-1 == r && EINTR == errno); + + return r; +} + +static void process_image(const void *p, int size) +{ + if (out_buf) + fwrite(p, size, 1, stdout); + + fflush(stderr); + fprintf(stderr, "."); + fflush(stdout); +} + +static int read_frame(void) +{ + struct v4l2_buffer buf; + unsigned int i; + + switch (io) { + case IO_METHOD_READ: + if (-1 == read(fd, buffers[0].start, buffers[0].length)) { + switch (errno) { + case EAGAIN: + return 0; + + case EIO: + /* Could ignore EIO, see spec. */ + + /* fall through */ + + default: + errno_exit("read"); + } + } + + process_image(buffers[0].start, buffers[0].length); + break; + + case IO_METHOD_MMAP: + CLEAR(buf); + + buf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + buf.memory = V4L2_MEMORY_MMAP; + + if (-1 == xioctl(fd, VIDIOC_DQBUF, &buf)) { + switch (errno) { + case EAGAIN: + return 0; + + case EIO: + /* Could ignore EIO, see spec. */ + + /* fall through */ + + default: + errno_exit("VIDIOC_DQBUF"); + } + } + + assert(buf.index < n_buffers); + + process_image(buffers[buf.index].start, buf.bytesused); + + if (-1 == xioctl(fd, VIDIOC_QBUF, &buf)) + errno_exit("VIDIOC_QBUF"); + break; + + case IO_METHOD_USERPTR: + CLEAR(buf); + + buf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + buf.memory = V4L2_MEMORY_USERPTR; + + if (-1 == xioctl(fd, VIDIOC_DQBUF, &buf)) { + switch (errno) { + case EAGAIN: + return 0; + + case EIO: + /* Could ignore EIO, see spec. */ + + /* fall through */ + + default: + errno_exit("VIDIOC_DQBUF"); + } + } + + for (i = 0; i < n_buffers; ++i) + if (buf.m.userptr == (unsigned long)buffers[i].start + && buf.length == buffers[i].length) + break; + + assert(i < n_buffers); + + process_image((void *)buf.m.userptr, buf.bytesused); + + if (-1 == xioctl(fd, VIDIOC_QBUF, &buf)) + errno_exit("VIDIOC_QBUF"); + break; + } + + return 1; +} + +static void mainloop(void) +{ + unsigned int count; + + count = frame_count; + + while (count-- > 0) { + for (;;) { + fd_set fds; + struct timeval tv; + int r; + + FD_ZERO(&fds); + FD_SET(fd, &fds); + + /* Timeout. */ + tv.tv_sec = 2; + tv.tv_usec = 0; + + r = select(fd + 1, &fds, NULL, NULL, &tv); + + if (-1 == r) { + if (EINTR == errno) + continue; + errno_exit("select"); + } + + if (0 == r) { + fprintf(stderr, "select timeout\n"); + exit(EXIT_FAILURE); + } + + if (read_frame()) + break; + /* EAGAIN - continue select loop. */ + } + } +} + +static void stop_capturing(void) +{ + enum v4l2_buf_type type; + + switch (io) { + case IO_METHOD_READ: + /* Nothing to do. */ + break; + + case IO_METHOD_MMAP: + case IO_METHOD_USERPTR: + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + if (-1 == xioctl(fd, VIDIOC_STREAMOFF, &type)) + errno_exit("VIDIOC_STREAMOFF"); + break; + } +} + +static void start_capturing(void) +{ + unsigned int i; + enum v4l2_buf_type type; + + switch (io) { + case IO_METHOD_READ: + /* Nothing to do. */ + break; + + case IO_METHOD_MMAP: + for (i = 0; i < n_buffers; ++i) { + struct v4l2_buffer buf; + + CLEAR(buf); + buf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + buf.memory = V4L2_MEMORY_MMAP; + buf.index = i; + + if (-1 == xioctl(fd, VIDIOC_QBUF, &buf)) + errno_exit("VIDIOC_QBUF"); + } + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + if (-1 == xioctl(fd, VIDIOC_STREAMON, &type)) + errno_exit("VIDIOC_STREAMON"); + break; + + case IO_METHOD_USERPTR: + for (i = 0; i < n_buffers; ++i) { + struct v4l2_buffer buf; + + CLEAR(buf); + buf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + buf.memory = V4L2_MEMORY_USERPTR; + buf.index = i; + buf.m.userptr = (unsigned long)buffers[i].start; + buf.length = buffers[i].length; + + if (-1 == xioctl(fd, VIDIOC_QBUF, &buf)) + errno_exit("VIDIOC_QBUF"); + } + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + if (-1 == xioctl(fd, VIDIOC_STREAMON, &type)) + errno_exit("VIDIOC_STREAMON"); + break; + } +} + +static void uninit_device(void) +{ + unsigned int i; + + switch (io) { + case IO_METHOD_READ: + free(buffers[0].start); + break; + + case IO_METHOD_MMAP: + for (i = 0; i < n_buffers; ++i) + if (-1 == munmap(buffers[i].start, buffers[i].length)) + errno_exit("munmap"); + break; + + case IO_METHOD_USERPTR: + for (i = 0; i < n_buffers; ++i) + free(buffers[i].start); + break; + } + + free(buffers); +} + +static void init_read(unsigned int buffer_size) +{ + buffers = calloc(1, sizeof(*buffers)); + + if (!buffers) { + fprintf(stderr, "Out of memory\n"); + exit(EXIT_FAILURE); + } + + buffers[0].length = buffer_size; + buffers[0].start = malloc(buffer_size); + + if (!buffers[0].start) { + fprintf(stderr, "Out of memory\n"); + exit(EXIT_FAILURE); + } +} + +static void init_mmap(void) +{ + struct v4l2_requestbuffers req; + + CLEAR(req); + + req.count = 4; + req.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + req.memory = V4L2_MEMORY_MMAP; + + if (-1 == xioctl(fd, VIDIOC_REQBUFS, &req)) { + if (EINVAL == errno) { + fprintf(stderr, "%s does not support " + "memory mapping\n", dev_name); + exit(EXIT_FAILURE); + } else { + errno_exit("VIDIOC_REQBUFS"); + } + } + + if (req.count < 2) { + fprintf(stderr, "Insufficient buffer memory on %s\n", + dev_name); + exit(EXIT_FAILURE); + } + + buffers = calloc(req.count, sizeof(*buffers)); + + if (!buffers) { + fprintf(stderr, "Out of memory\n"); + exit(EXIT_FAILURE); + } + + for (n_buffers = 0; n_buffers < req.count; ++n_buffers) { + struct v4l2_buffer buf; + + CLEAR(buf); + + buf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + buf.memory = V4L2_MEMORY_MMAP; + buf.index = n_buffers; + + if (-1 == xioctl(fd, VIDIOC_QUERYBUF, &buf)) + errno_exit("VIDIOC_QUERYBUF"); + + buffers[n_buffers].length = buf.length; + buffers[n_buffers].start = + mmap(NULL /* start anywhere */, + buf.length, + PROT_READ | PROT_WRITE /* required */, + MAP_SHARED /* recommended */, + fd, buf.m.offset); + + if (MAP_FAILED == buffers[n_buffers].start) + errno_exit("mmap"); + } +} + +static void init_userp(unsigned int buffer_size) +{ + struct v4l2_requestbuffers req; + + CLEAR(req); + + req.count = 4; + req.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + req.memory = V4L2_MEMORY_USERPTR; + + if (-1 == xioctl(fd, VIDIOC_REQBUFS, &req)) { + if (EINVAL == errno) { + fprintf(stderr, "%s does not support " + "user pointer i/o\n", dev_name); + exit(EXIT_FAILURE); + } else { + errno_exit("VIDIOC_REQBUFS"); + } + } + + buffers = calloc(4, sizeof(*buffers)); + + if (!buffers) { + fprintf(stderr, "Out of memory\n"); + exit(EXIT_FAILURE); + } + + for (n_buffers = 0; n_buffers < 4; ++n_buffers) { + buffers[n_buffers].length = buffer_size; + buffers[n_buffers].start = malloc(buffer_size); + + if (!buffers[n_buffers].start) { + fprintf(stderr, "Out of memory\n"); + exit(EXIT_FAILURE); + } + } +} + +static void init_device(void) +{ + struct v4l2_capability cap; + struct v4l2_cropcap cropcap; + struct v4l2_crop crop; + struct v4l2_format fmt; + unsigned int min; + + if (-1 == xioctl(fd, VIDIOC_QUERYCAP, &cap)) { + if (EINVAL == errno) { + fprintf(stderr, "%s is no V4L2 device\n", + dev_name); + exit(EXIT_FAILURE); + } else { + errno_exit("VIDIOC_QUERYCAP"); + } + } + + if (!(cap.capabilities & V4L2_CAP_VIDEO_CAPTURE)) { + fprintf(stderr, "%s is no video capture device\n", + dev_name); + exit(EXIT_FAILURE); + } + + switch (io) { + case IO_METHOD_READ: + if (!(cap.capabilities & V4L2_CAP_READWRITE)) { + fprintf(stderr, "%s does not support read i/o\n", + dev_name); + exit(EXIT_FAILURE); + } + break; + + case IO_METHOD_MMAP: + case IO_METHOD_USERPTR: + if (!(cap.capabilities & V4L2_CAP_STREAMING)) { + fprintf(stderr, "%s does not support streaming i/o\n", + dev_name); + exit(EXIT_FAILURE); + } + break; + } + + + /* Select video input, video standard and tune here. */ + + + CLEAR(cropcap); + + cropcap.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + if (0 == xioctl(fd, VIDIOC_CROPCAP, &cropcap)) { + crop.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + crop.c = cropcap.defrect; /* reset to default */ + + if (-1 == xioctl(fd, VIDIOC_S_CROP, &crop)) { + switch (errno) { + case EINVAL: + /* Cropping not supported. */ + break; + default: + /* Errors ignored. */ + break; + } + } + } else { + /* Errors ignored. */ + } + + + CLEAR(fmt); + + fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + if (force_format) { + fmt.fmt.pix.width = 640; + fmt.fmt.pix.height = 480; + fmt.fmt.pix.pixelformat = V4L2_PIX_FMT_YUYV; + fmt.fmt.pix.field = V4L2_FIELD_INTERLACED; + + if (-1 == xioctl(fd, VIDIOC_S_FMT, &fmt)) + errno_exit("VIDIOC_S_FMT"); + + /* Note VIDIOC_S_FMT may change width and height. */ + } else { + /* Preserve original settings as set by v4l2-ctl for example */ + if (-1 == xioctl(fd, VIDIOC_G_FMT, &fmt)) + errno_exit("VIDIOC_G_FMT"); + } + + /* Buggy driver paranoia. */ + min = fmt.fmt.pix.width * 2; + if (fmt.fmt.pix.bytesperline < min) + fmt.fmt.pix.bytesperline = min; + min = fmt.fmt.pix.bytesperline * fmt.fmt.pix.height; + if (fmt.fmt.pix.sizeimage < min) + fmt.fmt.pix.sizeimage = min; + + switch (io) { + case IO_METHOD_READ: + init_read(fmt.fmt.pix.sizeimage); + break; + + case IO_METHOD_MMAP: + init_mmap(); + break; + + case IO_METHOD_USERPTR: + init_userp(fmt.fmt.pix.sizeimage); + break; + } +} + +static void close_device(void) +{ + if (-1 == close(fd)) + errno_exit("close"); + + fd = -1; +} + +static void open_device(void) +{ + struct stat st; + + if (-1 == stat(dev_name, &st)) { + fprintf(stderr, "Cannot identify '%s': %d, %s\n", + dev_name, errno, strerror(errno)); + exit(EXIT_FAILURE); + } + + if (!S_ISCHR(st.st_mode)) { + fprintf(stderr, "%s is no device\n", dev_name); + exit(EXIT_FAILURE); + } + + fd = open(dev_name, O_RDWR /* required */ | O_NONBLOCK, 0); + + if (-1 == fd) { + fprintf(stderr, "Cannot open '%s': %d, %s\n", + dev_name, errno, strerror(errno)); + exit(EXIT_FAILURE); + } +} + +static void usage(FILE *fp, int argc, char **argv) +{ + fprintf(fp, + "Usage: %s [options]\n\n" + "Version 1.3\n" + "Options:\n" + "-d | --device name Video device name [%s]\n" + "-h | --help Print this message\n" + "-m | --mmap Use memory mapped buffers [default]\n" + "-r | --read Use read() calls\n" + "-u | --userp Use application allocated buffers\n" + "-o | --output Outputs stream to stdout\n" + "-f | --format Force format to 640x480 YUYV\n" + "-c | --count Number of frames to grab [%i]\n" + "", + argv[0], dev_name, frame_count); +} + +static const char short_options[] = "d:hmruofc:"; + +static const struct option +long_options[] = { + { "device", required_argument, NULL, 'd' }, + { "help", no_argument, NULL, 'h' }, + { "mmap", no_argument, NULL, 'm' }, + { "read", no_argument, NULL, 'r' }, + { "userp", no_argument, NULL, 'u' }, + { "output", no_argument, NULL, 'o' }, + { "format", no_argument, NULL, 'f' }, + { "count", required_argument, NULL, 'c' }, + { 0, 0, 0, 0 } +}; + +int main(int argc, char **argv) +{ + dev_name = "/dev/video0"; + + for (;;) { + int idx; + int c; + + c = getopt_long(argc, argv, + short_options, long_options, &idx); + + if (-1 == c) + break; + + switch (c) { + case 0: /* getopt_long() flag */ + break; + + case 'd': + dev_name = optarg; + break; + + case 'h': + usage(stdout, argc, argv); + exit(EXIT_SUCCESS); + + case 'm': + io = IO_METHOD_MMAP; + break; + + case 'r': + io = IO_METHOD_READ; + break; + + case 'u': + io = IO_METHOD_USERPTR; + break; + + case 'o': + out_buf++; + break; + + case 'f': + force_format++; + break; + + case 'c': + errno = 0; + frame_count = strtol(optarg, NULL, 0); + if (errno) + errno_exit(optarg); + break; + + default: + usage(stderr, argc, argv); + exit(EXIT_FAILURE); + } + } + + open_device(); + init_device(); + start_capturing(); + mainloop(); + stop_capturing(); + uninit_device(); + close_device(); + fprintf(stderr, "\n"); + return 0; +} + diff --git a/Documentation/DocBook/v4l/common.xml b/Documentation/DocBook/v4l/common.xml new file mode 100644 index 000000000000..b1a81d246d58 --- /dev/null +++ b/Documentation/DocBook/v4l/common.xml @@ -0,0 +1,1160 @@ + Common API Elements + + Programming a V4L2 device consists of these +steps: + + + + Opening the device + + + Changing device properties, selecting a video and audio +input, video standard, picture brightness a. o. + + + Negotiating a data format + + + Negotiating an input/output method + + + The actual input/output loop + + + Closing the device + + + + In practice most steps are optional and can be executed out of +order. It depends on the V4L2 device type, you can read about the +details in . In this chapter we will discuss +the basic concepts applicable to all devices. + +
+ Opening and Closing Devices + +
+ Device Naming + + V4L2 drivers are implemented as kernel modules, loaded +manually by the system administrator or automatically when a device is +first opened. The driver modules plug into the "videodev" kernel +module. It provides helper functions and a common application +interface specified in this document. + + Each driver thus loaded registers one or more device nodes +with major number 81 and a minor number between 0 and 255. Assigning +minor numbers to V4L2 devices is entirely up to the system administrator, +this is primarily intended to solve conflicts between devices. + Access permissions are associated with character +device special files, hence we must ensure device numbers cannot +change with the module load order. To this end minor numbers are no +longer automatically assigned by the "videodev" module as in V4L but +requested by the driver. The defaults will suffice for most people +unless two drivers compete for the same minor numbers. + The module options to select minor numbers are named +after the device special file with a "_nr" suffix. For example "video_nr" +for /dev/video video capture devices. The number is +an offset to the base minor number associated with the device type. + + In earlier versions of the V4L2 API the module options +where named after the device special file with a "unit_" prefix, expressing +the minor number itself, not an offset. Rationale for this change is unknown. +Lastly the naming and semantics are just a convention among driver writers, +the point to note is that minor numbers are not supposed to be hardcoded +into drivers. + When the driver supports multiple devices of the same +type more than one minor number can be assigned, separated by commas: + + +> insmod mydriver.o video_nr=0,1 radio_nr=0,1 + + + In /etc/modules.conf this may be +written as: + +alias char-major-81-0 mydriver +alias char-major-81-1 mydriver +alias char-major-81-64 mydriver +options mydriver video_nr=0,1 radio_nr=0,1 + + + + When an application attempts to open a device +special file with major number 81 and minor number 0, 1, or 64, load +"mydriver" (and the "videodev" module it depends upon). + + + Register the first two video capture devices with +minor number 0 and 1 (base number is 0), the first two radio device +with minor number 64 and 65 (base 64). + + + When no minor number is given as module +option the driver supplies a default. +recommends the base minor numbers to be used for the various device +types. Obviously minor numbers must be unique. When the number is +already in use the offending device will not be +registered. + + By convention system administrators create various +character device special files with these major and minor numbers in +the /dev directory. The names recomended for the +different V4L2 device types are listed in . + + + The creation of character special files (with +mknod) is a privileged operation and +devices cannot be opened by major and minor number. That means +applications cannot reliable scan for loaded or +installed drivers. The user must enter a device name, or the +application can try the conventional device names. + + Under the device filesystem (devfs) the minor number +options are ignored. V4L2 drivers (or by proxy the "videodev" module) +automatically create the required device files in the +/dev/v4l directory using the conventional device +names above. +
+ + + +
+ Multiple Opens + + In general, V4L2 devices can be opened more than once. +When this is supported by the driver, users can for example start a +"panel" application to change controls like brightness or audio +volume, while another application captures video and audio. In other words, panel +applications are comparable to an OSS or ALSA audio mixer application. +When a device supports multiple functions like capturing and overlay +simultaneously, multiple opens allow concurrent +use of the device by forked processes or specialized applications. + + Multiple opens are optional, although drivers should +permit at least concurrent accesses without data exchange, &ie; panel +applications. This implies &func-open; can return an &EBUSY; when the +device is already in use, as well as &func-ioctl; functions initiating +data exchange (namely the &VIDIOC-S-FMT; ioctl), and the &func-read; +and &func-write; functions. + + Mere opening a V4L2 device does not grant exclusive +access. + Drivers could recognize the +O_EXCL open flag. Presently this is not required, +so applications cannot know if it really works. + Initiating data exchange however assigns the right +to read or write the requested type of data, and to change related +properties, to this file descriptor. Applications can request +additional access privileges using the priority mechanism described in +. +
+ +
+ Shared Data Streams + + V4L2 drivers should not support multiple applications +reading or writing the same data stream on a device by copying +buffers, time multiplexing or similar means. This is better handled by +a proxy application in user space. When the driver supports stream +sharing anyway it must be implemented transparently. The V4L2 API does +not specify how conflicts are solved. +
+ +
+ Functions + + To open and close V4L2 devices applications use the +&func-open; and &func-close; function, respectively. Devices are +programmed using the &func-ioctl; function as explained in the +following sections. +
+
+ +
+ Querying Capabilities + + Because V4L2 covers a wide variety of devices not all +aspects of the API are equally applicable to all types of devices. +Furthermore devices of the same type have different capabilities and +this specification permits the omission of a few complicated and less +important parts of the API. + + The &VIDIOC-QUERYCAP; ioctl is available to check if the kernel +device is compatible with this specification, and to query the functions and I/O +methods supported by the device. Other features can be queried +by calling the respective ioctl, for example &VIDIOC-ENUMINPUT; +to learn about the number, types and names of video connectors on the +device. Although abstraction is a major objective of this API, the +ioctl also allows driver specific applications to reliable identify +the driver. + + All V4L2 drivers must support +VIDIOC_QUERYCAP. Applications should always call +this ioctl after opening the device. +
+ +
+ Application Priority + + When multiple applications share a device it may be +desirable to assign them different priorities. Contrary to the +traditional "rm -rf /" school of thought a video recording application +could for example block other applications from changing video +controls or switching the current TV channel. Another objective is to +permit low priority applications working in background, which can be +preempted by user controlled applications and automatically regain +control of the device at a later time. + + Since these features cannot be implemented entirely in user +space V4L2 defines the &VIDIOC-G-PRIORITY; and &VIDIOC-S-PRIORITY; +ioctls to request and query the access priority associate with a file +descriptor. Opening a device assigns a medium priority, compatible +with earlier versions of V4L2 and drivers not supporting these ioctls. +Applications requiring a different priority will usually call +VIDIOC_S_PRIORITY after verifying the device with +the &VIDIOC-QUERYCAP; ioctl. + + Ioctls changing driver properties, such as &VIDIOC-S-INPUT;, +return an &EBUSY; after another application obtained higher priority. +An event mechanism to notify applications about asynchronous property +changes has been proposed but not added yet. +
+ +
+ Video Inputs and Outputs + + Video inputs and outputs are physical connectors of a +device. These can be for example RF connectors (antenna/cable), CVBS +a.k.a. Composite Video, S-Video or RGB connectors. Only video and VBI +capture devices have inputs, output devices have outputs, at least one +each. Radio devices have no video inputs or outputs. + + To learn about the number and attributes of the +available inputs and outputs applications can enumerate them with the +&VIDIOC-ENUMINPUT; and &VIDIOC-ENUMOUTPUT; ioctl, respectively. The +&v4l2-input; returned by the VIDIOC_ENUMINPUT +ioctl also contains signal status information applicable when the +current video input is queried. + + The &VIDIOC-G-INPUT; and &VIDIOC-G-OUTPUT; ioctl return the +index of the current video input or output. To select a different +input or output applications call the &VIDIOC-S-INPUT; and +&VIDIOC-S-OUTPUT; ioctl. Drivers must implement all the input ioctls +when the device has one or more inputs, all the output ioctls when the +device has one or more outputs. + + + + + Information about the current video input + + +&v4l2-input; input; +int index; + +if (-1 == ioctl (fd, &VIDIOC-G-INPUT;, &index)) { + perror ("VIDIOC_G_INPUT"); + exit (EXIT_FAILURE); +} + +memset (&input, 0, sizeof (input)); +input.index = index; + +if (-1 == ioctl (fd, &VIDIOC-ENUMINPUT;, &input)) { + perror ("VIDIOC_ENUMINPUT"); + exit (EXIT_FAILURE); +} + +printf ("Current input: %s\n", input.name); + + + + + Switching to the first video input + + +int index; + +index = 0; + +if (-1 == ioctl (fd, &VIDIOC-S-INPUT;, &index)) { + perror ("VIDIOC_S_INPUT"); + exit (EXIT_FAILURE); +} + + +
+ +
+ Audio Inputs and Outputs + + Audio inputs and outputs are physical connectors of a +device. Video capture devices have inputs, output devices have +outputs, zero or more each. Radio devices have no audio inputs or +outputs. They have exactly one tuner which in fact +is an audio source, but this API associates +tuners with video inputs or outputs only, and radio devices have +none of these. + Actually &v4l2-audio; ought to have a +tuner field like &v4l2-input;, not only +making the API more consistent but also permitting radio devices with +multiple tuners. + A connector on a TV card to loop back the received +audio signal to a sound card is not considered an audio output. + + Audio and video inputs and outputs are associated. Selecting +a video source also selects an audio source. This is most evident when +the video and audio source is a tuner. Further audio connectors can +combine with more than one video input or output. Assumed two +composite video inputs and two audio inputs exist, there may be up to +four valid combinations. The relation of video and audio connectors +is defined in the audioset field of the +respective &v4l2-input; or &v4l2-output;, where each bit represents +the index number, starting at zero, of one audio input or output. + + To learn about the number and attributes of the +available inputs and outputs applications can enumerate them with the +&VIDIOC-ENUMAUDIO; and &VIDIOC-ENUMAUDOUT; ioctl, respectively. The +&v4l2-audio; returned by the VIDIOC_ENUMAUDIO ioctl +also contains signal status information applicable when the current +audio input is queried. + + The &VIDIOC-G-AUDIO; and &VIDIOC-G-AUDOUT; ioctl report +the current audio input and output, respectively. Note that, unlike +&VIDIOC-G-INPUT; and &VIDIOC-G-OUTPUT; these ioctls return a structure +as VIDIOC_ENUMAUDIO and +VIDIOC_ENUMAUDOUT do, not just an index. + + To select an audio input and change its properties +applications call the &VIDIOC-S-AUDIO; ioctl. To select an audio +output (which presently has no changeable properties) applications +call the &VIDIOC-S-AUDOUT; ioctl. + + Drivers must implement all input ioctls when the device +has one or more inputs, all output ioctls when the device has one +or more outputs. When the device has any audio inputs or outputs the +driver must set the V4L2_CAP_AUDIO flag in the +&v4l2-capability; returned by the &VIDIOC-QUERYCAP; ioctl. + + + Information about the current audio input + + +&v4l2-audio; audio; + +memset (&audio, 0, sizeof (audio)); + +if (-1 == ioctl (fd, &VIDIOC-G-AUDIO;, &audio)) { + perror ("VIDIOC_G_AUDIO"); + exit (EXIT_FAILURE); +} + +printf ("Current input: %s\n", audio.name); + + + + + Switching to the first audio input + + +&v4l2-audio; audio; + +memset (&audio, 0, sizeof (audio)); /* clear audio.mode, audio.reserved */ + +audio.index = 0; + +if (-1 == ioctl (fd, &VIDIOC-S-AUDIO;, &audio)) { + perror ("VIDIOC_S_AUDIO"); + exit (EXIT_FAILURE); +} + + +
+ +
+ Tuners and Modulators + +
+ Tuners + + Video input devices can have one or more tuners +demodulating a RF signal. Each tuner is associated with one or more +video inputs, depending on the number of RF connectors on the tuner. +The type field of the respective +&v4l2-input; returned by the &VIDIOC-ENUMINPUT; ioctl is set to +V4L2_INPUT_TYPE_TUNER and its +tuner field contains the index number of +the tuner. + + Radio devices have exactly one tuner with index zero, no +video inputs. + + To query and change tuner properties applications use the +&VIDIOC-G-TUNER; and &VIDIOC-S-TUNER; ioctl, respectively. The +&v4l2-tuner; returned by VIDIOC_G_TUNER also +contains signal status information applicable when the tuner of the +current video input, or a radio tuner is queried. Note that +VIDIOC_S_TUNER does not switch the current tuner, +when there is more than one at all. The tuner is solely determined by +the current video input. Drivers must support both ioctls and set the +V4L2_CAP_TUNER flag in the &v4l2-capability; +returned by the &VIDIOC-QUERYCAP; ioctl when the device has one or +more tuners. +
+ +
+ Modulators + + Video output devices can have one or more modulators, uh, +modulating a video signal for radiation or connection to the antenna +input of a TV set or video recorder. Each modulator is associated with +one or more video outputs, depending on the number of RF connectors on +the modulator. The type field of the +respective &v4l2-output; returned by the &VIDIOC-ENUMOUTPUT; ioctl is +set to V4L2_OUTPUT_TYPE_MODULATOR and its +modulator field contains the index number +of the modulator. This specification does not define radio output +devices. + + To query and change modulator properties applications use +the &VIDIOC-G-MODULATOR; and &VIDIOC-S-MODULATOR; ioctl. Note that +VIDIOC_S_MODULATOR does not switch the current +modulator, when there is more than one at all. The modulator is solely +determined by the current video output. Drivers must support both +ioctls and set the V4L2_CAP_MODULATOR flag in +the &v4l2-capability; returned by the &VIDIOC-QUERYCAP; ioctl when the +device has one or more modulators. +
+ +
+ Radio Frequency + + To get and set the tuner or modulator radio frequency +applications use the &VIDIOC-G-FREQUENCY; and &VIDIOC-S-FREQUENCY; +ioctl which both take a pointer to a &v4l2-frequency;. These ioctls +are used for TV and radio devices alike. Drivers must support both +ioctls when the tuner or modulator ioctls are supported, or +when the device is a radio device. +
+
+ +
+ Video Standards + + Video devices typically support one or more different video +standards or variations of standards. Each video input and output may +support another set of standards. This set is reported by the +std field of &v4l2-input; and +&v4l2-output; returned by the &VIDIOC-ENUMINPUT; and +&VIDIOC-ENUMOUTPUT; ioctl, respectively. + + V4L2 defines one bit for each analog video standard +currently in use worldwide, and sets aside bits for driver defined +standards, ⪚ hybrid standards to watch NTSC video tapes on PAL TVs +and vice versa. Applications can use the predefined bits to select a +particular standard, although presenting the user a menu of supported +standards is preferred. To enumerate and query the attributes of the +supported standards applications use the &VIDIOC-ENUMSTD; ioctl. + + Many of the defined standards are actually just variations +of a few major standards. The hardware may in fact not distinguish +between them, or do so internal and switch automatically. Therefore +enumerated standards also contain sets of one or more standard +bits. + + Assume a hypothetic tuner capable of demodulating B/PAL, +G/PAL and I/PAL signals. The first enumerated standard is a set of B +and G/PAL, switched automatically depending on the selected radio +frequency in UHF or VHF band. Enumeration gives a "PAL-B/G" or "PAL-I" +choice. Similar a Composite input may collapse standards, enumerating +"PAL-B/G/H/I", "NTSC-M" and "SECAM-D/K". + Some users are already confused by technical terms PAL, +NTSC and SECAM. There is no point asking them to distinguish between +B, G, D, or K when the software or hardware can do that +automatically. + + + To query and select the standard used by the current video +input or output applications call the &VIDIOC-G-STD; and +&VIDIOC-S-STD; ioctl, respectively. The received +standard can be sensed with the &VIDIOC-QUERYSTD; ioctl. Note parameter of all these ioctls is a pointer to a &v4l2-std-id; type (a standard set), not an index into the standard enumeration. + An alternative to the current scheme is to use pointers +to indices as arguments of VIDIOC_G_STD and +VIDIOC_S_STD, the &v4l2-input; and +&v4l2-output; std field would be a set of +indices like audioset. + Indices are consistent with the rest of the API +and identify the standard unambiguously. In the present scheme of +things an enumerated standard is looked up by &v4l2-std-id;. Now the +standards supported by the inputs of a device can overlap. Just +assume the tuner and composite input in the example above both +exist on a device. An enumeration of "PAL-B/G", "PAL-H/I" suggests +a choice which does not exist. We cannot merge or omit sets, because +applications would be unable to find the standards reported by +VIDIOC_G_STD. That leaves separate enumerations +for each input. Also selecting a standard by &v4l2-std-id; can be +ambiguous. Advantage of this method is that applications need not +identify the standard indirectly, after enumerating.So in +summary, the lookup itself is unavoidable. The difference is only +whether the lookup is necessary to find an enumerated standard or to +switch to a standard by &v4l2-std-id;. + Drivers must implement all video standard ioctls +when the device has one or more video inputs or outputs. + + Special rules apply to USB cameras where the notion of video +standards makes little sense. More generally any capture device, +output devices accordingly, which is + + incapable of capturing fields or frames at the nominal +rate of the video standard, or + + + where timestamps refer +to the instant the field or frame was received by the driver, not the +capture time, or + + + where sequence numbers +refer to the frames received by the driver, not the captured +frames. + + Here the driver shall set the +std field of &v4l2-input; and &v4l2-output; +to zero, the VIDIOC_G_STD, +VIDIOC_S_STD, +VIDIOC_QUERYSTD and +VIDIOC_ENUMSTD ioctls shall return the +&EINVAL;. + See for a rationale. Probably +even USB cameras follow some well known video standard. It might have +been better to explicitly indicate elsewhere if a device cannot live +up to normal expectations, instead of this exception. + + + + Information about the current video standard + + +&v4l2-std-id; std_id; +&v4l2-standard; standard; + +if (-1 == ioctl (fd, &VIDIOC-G-STD;, &std_id)) { + /* Note when VIDIOC_ENUMSTD always returns EINVAL this + is no video device or it falls under the USB exception, + and VIDIOC_G_STD returning EINVAL is no error. */ + + perror ("VIDIOC_G_STD"); + exit (EXIT_FAILURE); +} + +memset (&standard, 0, sizeof (standard)); +standard.index = 0; + +while (0 == ioctl (fd, &VIDIOC-ENUMSTD;, &standard)) { + if (standard.id & std_id) { + printf ("Current video standard: %s\n", standard.name); + exit (EXIT_SUCCESS); + } + + standard.index++; +} + +/* EINVAL indicates the end of the enumeration, which cannot be + empty unless this device falls under the USB exception. */ + +if (errno == EINVAL || standard.index == 0) { + perror ("VIDIOC_ENUMSTD"); + exit (EXIT_FAILURE); +} + + + + + Listing the video standards supported by the current +input + + +&v4l2-input; input; +&v4l2-standard; standard; + +memset (&input, 0, sizeof (input)); + +if (-1 == ioctl (fd, &VIDIOC-G-INPUT;, &input.index)) { + perror ("VIDIOC_G_INPUT"); + exit (EXIT_FAILURE); +} + +if (-1 == ioctl (fd, &VIDIOC-ENUMINPUT;, &input)) { + perror ("VIDIOC_ENUM_INPUT"); + exit (EXIT_FAILURE); +} + +printf ("Current input %s supports:\n", input.name); + +memset (&standard, 0, sizeof (standard)); +standard.index = 0; + +while (0 == ioctl (fd, &VIDIOC-ENUMSTD;, &standard)) { + if (standard.id & input.std) + printf ("%s\n", standard.name); + + standard.index++; +} + +/* EINVAL indicates the end of the enumeration, which cannot be + empty unless this device falls under the USB exception. */ + +if (errno != EINVAL || standard.index == 0) { + perror ("VIDIOC_ENUMSTD"); + exit (EXIT_FAILURE); +} + + + + + Selecting a new video standard + + +&v4l2-input; input; +&v4l2-std-id; std_id; + +memset (&input, 0, sizeof (input)); + +if (-1 == ioctl (fd, &VIDIOC-G-INPUT;, &input.index)) { + perror ("VIDIOC_G_INPUT"); + exit (EXIT_FAILURE); +} + +if (-1 == ioctl (fd, &VIDIOC-ENUMINPUT;, &input)) { + perror ("VIDIOC_ENUM_INPUT"); + exit (EXIT_FAILURE); +} + +if (0 == (input.std & V4L2_STD_PAL_BG)) { + fprintf (stderr, "Oops. B/G PAL is not supported.\n"); + exit (EXIT_FAILURE); +} + +/* Note this is also supposed to work when only B + or G/PAL is supported. */ + +std_id = V4L2_STD_PAL_BG; + +if (-1 == ioctl (fd, &VIDIOC-S-STD;, &std_id)) { + perror ("VIDIOC_S_STD"); + exit (EXIT_FAILURE); +} + + +
+ + &sub-controls; + +
+ Data Formats + +
+ Data Format Negotiation + + Different devices exchange different kinds of data with +applications, for example video images, raw or sliced VBI data, RDS +datagrams. Even within one kind many different formats are possible, +in particular an abundance of image formats. Although drivers must +provide a default and the selection persists across closing and +reopening a device, applications should always negotiate a data format +before engaging in data exchange. Negotiation means the application +asks for a particular format and the driver selects and reports the +best the hardware can do to satisfy the request. Of course +applications can also just query the current selection. + + A single mechanism exists to negotiate all data formats +using the aggregate &v4l2-format; and the &VIDIOC-G-FMT; and +&VIDIOC-S-FMT; ioctls. Additionally the &VIDIOC-TRY-FMT; ioctl can be +used to examine what the hardware could do, +without actually selecting a new data format. The data formats +supported by the V4L2 API are covered in the respective device section +in . For a closer look at image formats see +. + + The VIDIOC_S_FMT ioctl is a major +turning-point in the initialization sequence. Prior to this point +multiple panel applications can access the same device concurrently to +select the current input, change controls or modify other properties. +The first VIDIOC_S_FMT assigns a logical stream +(video data, VBI data etc.) exclusively to one file descriptor. + + Exclusive means no other application, more precisely no +other file descriptor, can grab this stream or change device +properties inconsistent with the negotiated parameters. A video +standard change for example, when the new standard uses a different +number of scan lines, can invalidate the selected image format. +Therefore only the file descriptor owning the stream can make +invalidating changes. Accordingly multiple file descriptors which +grabbed different logical streams prevent each other from interfering +with their settings. When for example video overlay is about to start +or already in progress, simultaneous video capturing may be restricted +to the same cropping and image size. + + When applications omit the +VIDIOC_S_FMT ioctl its locking side effects are +implied by the next step, the selection of an I/O method with the +&VIDIOC-REQBUFS; ioctl or implicit with the first &func-read; or +&func-write; call. + + Generally only one logical stream can be assigned to a +file descriptor, the exception being drivers permitting simultaneous +video capturing and overlay using the same file descriptor for +compatibility with V4L and earlier versions of V4L2. Switching the +logical stream or returning into "panel mode" is possible by closing +and reopening the device. Drivers may support a +switch using VIDIOC_S_FMT. + + All drivers exchanging data with +applications must support the VIDIOC_G_FMT and +VIDIOC_S_FMT ioctl. Implementation of the +VIDIOC_TRY_FMT is highly recommended but +optional. +
+ +
+ Image Format Enumeration + + Apart of the generic format negotiation functions +a special ioctl to enumerate all image formats supported by video +capture, overlay or output devices is available. + Enumerating formats an application has no a-priori +knowledge of (otherwise it could explicitly ask for them and need not +enumerate) seems useless, but there are applications serving as proxy +between drivers and the actual video applications for which this is +useful. + + + The &VIDIOC-ENUM-FMT; ioctl must be supported +by all drivers exchanging image data with applications. + + + Drivers are not supposed to convert image formats in +kernel space. They must enumerate only formats directly supported by +the hardware. If necessary driver writers should publish an example +conversion routine or library for integration into applications. + +
+
+ +
+ Image Cropping, Insertion and Scaling + + Some video capture devices can sample a subsection of the +picture and shrink or enlarge it to an image of arbitrary size. We +call these abilities cropping and scaling. Some video output devices +can scale an image up or down and insert it at an arbitrary scan line +and horizontal offset into a video signal. + + Applications can use the following API to select an area in +the video signal, query the default area and the hardware limits. +Despite their name, the &VIDIOC-CROPCAP;, &VIDIOC-G-CROP; +and &VIDIOC-S-CROP; ioctls apply to input as well as output +devices. + + Scaling requires a source and a target. On a video capture +or overlay device the source is the video signal, and the cropping +ioctls determine the area actually sampled. The target are images +read by the application or overlaid onto the graphics screen. Their +size (and position for an overlay) is negotiated with the +&VIDIOC-G-FMT; and &VIDIOC-S-FMT; ioctls. + + On a video output device the source are the images passed in +by the application, and their size is again negotiated with the +VIDIOC_G/S_FMT ioctls, or may be encoded in a +compressed video stream. The target is the video signal, and the +cropping ioctls determine the area where the images are +inserted. + + Source and target rectangles are defined even if the device +does not support scaling or the VIDIOC_G/S_CROP +ioctls. Their size (and position where applicable) will be fixed in +this case. All capture and output device must support the +VIDIOC_CROPCAP ioctl such that applications can +determine if scaling takes place. + +
+ Cropping Structures + +
+ Image Cropping, Insertion and Scaling + + + + + + + + + The cropping, insertion and scaling process + + +
+ + For capture devices the coordinates of the top left +corner, width and height of the area which can be sampled is given by +the bounds substructure of the +&v4l2-cropcap; returned by the VIDIOC_CROPCAP +ioctl. To support a wide range of hardware this specification does not +define an origin or units. However by convention drivers should +horizontally count unscaled samples relative to 0H (the leading edge +of the horizontal sync pulse, see ). +Vertically ITU-R line +numbers of the first field (, ), multiplied by two if the driver can capture both +fields. + + The top left corner, width and height of the source +rectangle, that is the area actually sampled, is given by &v4l2-crop; +using the same coordinate system as &v4l2-cropcap;. Applications can +use the VIDIOC_G_CROP and +VIDIOC_S_CROP ioctls to get and set this +rectangle. It must lie completely within the capture boundaries and +the driver may further adjust the requested size and/or position +according to hardware limitations. + + Each capture device has a default source rectangle, given +by the defrect substructure of +&v4l2-cropcap;. The center of this rectangle shall align with the +center of the active picture area of the video signal, and cover what +the driver writer considers the complete picture. Drivers shall reset +the source rectangle to the default when the driver is first loaded, +but not later. + + For output devices these structures and ioctls are used +accordingly, defining the target rectangle where +the images will be inserted into the video signal. + +
+ +
+ Scaling Adjustments + + Video hardware can have various cropping, insertion and +scaling limitations. It may only scale up or down, support only +discrete scaling factors, or have different scaling abilities in +horizontal and vertical direction. Also it may not support scaling at +all. At the same time the &v4l2-crop; rectangle may have to be +aligned, and both the source and target rectangles may have arbitrary +upper and lower size limits. In particular the maximum +width and height +in &v4l2-crop; may be smaller than the +&v4l2-cropcap;.bounds area. Therefore, as +usual, drivers are expected to adjust the requested parameters and +return the actual values selected. + + Applications can change the source or the target rectangle +first, as they may prefer a particular image size or a certain area in +the video signal. If the driver has to adjust both to satisfy hardware +limitations, the last requested rectangle shall take priority, and the +driver should preferably adjust the opposite one. The &VIDIOC-TRY-FMT; +ioctl however shall not change the driver state and therefore only +adjust the requested rectangle. + + Suppose scaling on a video capture device is restricted to +a factor 1:1 or 2:1 in either direction and the target image size must +be a multiple of 16 × 16 pixels. The source cropping +rectangle is set to defaults, which are also the upper limit in this +example, of 640 × 400 pixels at offset 0, 0. An +application requests an image size of 300 × 225 +pixels, assuming video will be scaled down from the "full picture" +accordingly. The driver sets the image size to the closest possible +values 304 × 224, then chooses the cropping rectangle +closest to the requested size, that is 608 × 224 +(224 × 2:1 would exceed the limit 400). The offset +0, 0 is still valid, thus unmodified. Given the default cropping +rectangle reported by VIDIOC_CROPCAP the +application can easily propose another offset to center the cropping +rectangle. + + Now the application may insist on covering an area using a +picture aspect ratio closer to the original request, so it asks for a +cropping rectangle of 608 × 456 pixels. The present +scaling factors limit cropping to 640 × 384, so the +driver returns the cropping size 608 × 384 and adjusts +the image size to closest possible 304 × 192. + +
+ +
+ Examples + + Source and target rectangles shall remain unchanged across +closing and reopening a device, such that piping data into or out of a +device will work without special preparations. More advanced +applications should ensure the parameters are suitable before starting +I/O. + + + Resetting the cropping parameters + + (A video capture device is assumed; change +V4L2_BUF_TYPE_VIDEO_CAPTURE for other +devices.) + + +&v4l2-cropcap; cropcap; +&v4l2-crop; crop; + +memset (&cropcap, 0, sizeof (cropcap)); +cropcap.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + +if (-1 == ioctl (fd, &VIDIOC-CROPCAP;, &cropcap)) { + perror ("VIDIOC_CROPCAP"); + exit (EXIT_FAILURE); +} + +memset (&crop, 0, sizeof (crop)); +crop.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; +crop.c = cropcap.defrect; + +/* Ignore if cropping is not supported (EINVAL). */ + +if (-1 == ioctl (fd, &VIDIOC-S-CROP;, &crop) + && errno != EINVAL) { + perror ("VIDIOC_S_CROP"); + exit (EXIT_FAILURE); +} + + + + + Simple downscaling + + (A video capture device is assumed.) + + +&v4l2-cropcap; cropcap; +&v4l2-format; format; + +reset_cropping_parameters (); + +/* Scale down to 1/4 size of full picture. */ + +memset (&format, 0, sizeof (format)); /* defaults */ + +format.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + +format.fmt.pix.width = cropcap.defrect.width >> 1; +format.fmt.pix.height = cropcap.defrect.height >> 1; +format.fmt.pix.pixelformat = V4L2_PIX_FMT_YUYV; + +if (-1 == ioctl (fd, &VIDIOC-S-FMT;, &format)) { + perror ("VIDIOC_S_FORMAT"); + exit (EXIT_FAILURE); +} + +/* We could check the actual image size now, the actual scaling factor + or if the driver can scale at all. */ + + + + + Selecting an output area + + +&v4l2-cropcap; cropcap; +&v4l2-crop; crop; + +memset (&cropcap, 0, sizeof (cropcap)); +cropcap.type = V4L2_BUF_TYPE_VIDEO_OUTPUT; + +if (-1 == ioctl (fd, VIDIOC_CROPCAP;, &cropcap)) { + perror ("VIDIOC_CROPCAP"); + exit (EXIT_FAILURE); +} + +memset (&crop, 0, sizeof (crop)); + +crop.type = V4L2_BUF_TYPE_VIDEO_OUTPUT; +crop.c = cropcap.defrect; + +/* Scale the width and height to 50 % of their original size + and center the output. */ + +crop.c.width /= 2; +crop.c.height /= 2; +crop.c.left += crop.c.width / 2; +crop.c.top += crop.c.height / 2; + +/* Ignore if cropping is not supported (EINVAL). */ + +if (-1 == ioctl (fd, VIDIOC_S_CROP, &crop) + && errno != EINVAL) { + perror ("VIDIOC_S_CROP"); + exit (EXIT_FAILURE); +} + + + + + Current scaling factor and pixel aspect + + (A video capture device is assumed.) + + +&v4l2-cropcap; cropcap; +&v4l2-crop; crop; +&v4l2-format; format; +double hscale, vscale; +double aspect; +int dwidth, dheight; + +memset (&cropcap, 0, sizeof (cropcap)); +cropcap.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + +if (-1 == ioctl (fd, &VIDIOC-CROPCAP;, &cropcap)) { + perror ("VIDIOC_CROPCAP"); + exit (EXIT_FAILURE); +} + +memset (&crop, 0, sizeof (crop)); +crop.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + +if (-1 == ioctl (fd, &VIDIOC-G-CROP;, &crop)) { + if (errno != EINVAL) { + perror ("VIDIOC_G_CROP"); + exit (EXIT_FAILURE); + } + + /* Cropping not supported. */ + crop.c = cropcap.defrect; +} + +memset (&format, 0, sizeof (format)); +format.fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + +if (-1 == ioctl (fd, &VIDIOC-G-FMT;, &format)) { + perror ("VIDIOC_G_FMT"); + exit (EXIT_FAILURE); +} + +/* The scaling applied by the driver. */ + +hscale = format.fmt.pix.width / (double) crop.c.width; +vscale = format.fmt.pix.height / (double) crop.c.height; + +aspect = cropcap.pixelaspect.numerator / + (double) cropcap.pixelaspect.denominator; +aspect = aspect * hscale / vscale; + +/* Devices following ITU-R BT.601 do not capture + square pixels. For playback on a computer monitor + we should scale the images to this size. */ + +dwidth = format.fmt.pix.width / aspect; +dheight = format.fmt.pix.height; + + +
+
+ +
+ Streaming Parameters + + Streaming parameters are intended to optimize the video +capture process as well as I/O. Presently applications can request a +high quality capture mode with the &VIDIOC-S-PARM; ioctl. + + The current video standard determines a nominal number of +frames per second. If less than this number of frames is to be +captured or output, applications can request frame skipping or +duplicating on the driver side. This is especially useful when using +the &func-read; or &func-write;, which are not augmented by timestamps +or sequence counters, and to avoid unneccessary data copying. + + Finally these ioctls can be used to determine the number of +buffers used internally by a driver in read/write mode. For +implications see the section discussing the &func-read; +function. + + To get and set the streaming parameters applications call +the &VIDIOC-G-PARM; and &VIDIOC-S-PARM; ioctl, respectively. They take +a pointer to a &v4l2-streamparm;, which contains a union holding +separate parameters for input and output devices. + + These ioctls are optional, drivers need not implement +them. If so, they return the &EINVAL;. +
+ + diff --git a/Documentation/DocBook/v4l/compat.xml b/Documentation/DocBook/v4l/compat.xml new file mode 100644 index 000000000000..4d1902a54d61 --- /dev/null +++ b/Documentation/DocBook/v4l/compat.xml @@ -0,0 +1,2457 @@ + Changes + + The following chapters document the evolution of the V4L2 API, +errata or extensions. They are also intended to help application and +driver writers to port or update their code. + +
+ Differences between V4L and V4L2 + + The Video For Linux API was first introduced in Linux 2.1 to +unify and replace various TV and radio device related interfaces, +developed independently by driver writers in prior years. Starting +with Linux 2.5 the much improved V4L2 API replaces the V4L API, +although existing drivers will continue to support V4L applications in +the future, either directly or through the V4L2 compatibility layer in +the videodev kernel module translating ioctls on +the fly. For a transition period not all drivers will support the V4L2 +API. + +
+ Opening and Closing Devices + + For compatibility reasons the character device file names +recommended for V4L2 video capture, overlay, radio, teletext and raw +vbi capture devices did not change from those used by V4L. They are +listed in and below in . + + The V4L videodev module automatically +assigns minor numbers to drivers in load order, depending on the +registered device type. We recommend that V4L2 drivers by default +register devices with the same numbers, but the system administrator +can assign arbitrary minor numbers using driver module options. The +major device number remains 81. + + + V4L Device Types, Names and Numbers + + + + Device Type + File Name + Minor Numbers + + + + + Video capture and overlay + /dev/video and +/dev/bttv0 According to +Documentation/devices.txt these should be symbolic links to +/dev/video0. Note the original bttv interface is +not compatible with V4L or V4L2. , +/dev/video0 to +/dev/video63 + 0-63 + + + Radio receiver + /dev/radio + According to +Documentation/devices.txt a symbolic link to +/dev/radio0. + , /dev/radio0 to +/dev/radio63 + 64-127 + + + Teletext decoder + /dev/vtx, +/dev/vtx0 to +/dev/vtx31 + 192-223 + + + Raw VBI capture + /dev/vbi, +/dev/vbi0 to +/dev/vbi31 + 224-255 + + + +
+ + V4L prohibits (or used to prohibit) multiple opens of a +device file. V4L2 drivers may support multiple +opens, see for details and consequences. + + V4L drivers respond to V4L2 ioctls with an &EINVAL;. The +compatibility layer in the V4L2 videodev module +can translate V4L ioctl requests to their V4L2 counterpart, however a +V4L2 driver usually needs more preparation to become fully V4L +compatible. This is covered in more detail in . +
+ +
+ Querying Capabilities + + The V4L VIDIOCGCAP ioctl is +equivalent to V4L2's &VIDIOC-QUERYCAP;. + + The name field in struct +video_capability became +card in &v4l2-capability;, +type was replaced by +capabilities. Note V4L2 does not +distinguish between device types like this, better think of basic +video input, video output and radio devices supporting a set of +related functions like video capturing, video overlay and VBI +capturing. See for an +introduction. + + + + struct +video_capability +type + &v4l2-capability; +capabilities flags + Purpose + + + + + VID_TYPE_CAPTURE + V4L2_CAP_VIDEO_CAPTURE + The video +capture interface is supported. + + + VID_TYPE_TUNER + V4L2_CAP_TUNER + The device has a tuner or +modulator. + + + VID_TYPE_TELETEXT + V4L2_CAP_VBI_CAPTURE + The raw VBI +capture interface is supported. + + + VID_TYPE_OVERLAY + V4L2_CAP_VIDEO_OVERLAY + The video +overlay interface is supported. + + + VID_TYPE_CHROMAKEY + V4L2_FBUF_CAP_CHROMAKEY in +field capability of +&v4l2-framebuffer; + Whether chromakey overlay is supported. For +more information on overlay see +. + + + VID_TYPE_CLIPPING + V4L2_FBUF_CAP_LIST_CLIPPING +and V4L2_FBUF_CAP_BITMAP_CLIPPING in field +capability of &v4l2-framebuffer; + Whether clipping the overlaid image is +supported, see . + + + VID_TYPE_FRAMERAM + V4L2_FBUF_CAP_EXTERNOVERLAY +not set in field +capability of &v4l2-framebuffer; + Whether overlay overwrites frame buffer memory, +see . + + + VID_TYPE_SCALES + - + This flag indicates if the hardware can scale +images. The V4L2 API implies the scale factor by setting the cropping +dimensions and image size with the &VIDIOC-S-CROP; and &VIDIOC-S-FMT; +ioctl, respectively. The driver returns the closest sizes possible. +For more information on cropping and scaling see . + + + VID_TYPE_MONOCHROME + - + Applications can enumerate the supported image +formats with the &VIDIOC-ENUM-FMT; ioctl to determine if the device +supports grey scale capturing only. For more information on image +formats see . + + + VID_TYPE_SUBCAPTURE + - + Applications can call the &VIDIOC-G-CROP; ioctl +to determine if the device supports capturing a subsection of the full +picture ("cropping" in V4L2). If not, the ioctl returns the &EINVAL;. +For more information on cropping and scaling see . + + + VID_TYPE_MPEG_DECODER + - + Applications can enumerate the supported image +formats with the &VIDIOC-ENUM-FMT; ioctl to determine if the device +supports MPEG streams. + + + VID_TYPE_MPEG_ENCODER + - + See above. + + + VID_TYPE_MJPEG_DECODER + - + See above. + + + VID_TYPE_MJPEG_ENCODER + - + See above. + + + + + + The audios field was replaced +by capabilities flag +V4L2_CAP_AUDIO, indicating +if the device has any audio inputs or outputs. To +determine their number applications can enumerate audio inputs with +the &VIDIOC-G-AUDIO; ioctl. The audio ioctls are described in . + + The maxwidth, +maxheight, +minwidth and +minheight fields were removed. Calling the +&VIDIOC-S-FMT; or &VIDIOC-TRY-FMT; ioctl with the desired dimensions +returns the closest size possible, taking into account the current +video standard, cropping and scaling limitations. +
+ +
+ Video Sources + + V4L provides the VIDIOCGCHAN and +VIDIOCSCHAN ioctl using struct +video_channel to enumerate +the video inputs of a V4L device. The equivalent V4L2 ioctls +are &VIDIOC-ENUMINPUT;, &VIDIOC-G-INPUT; and &VIDIOC-S-INPUT; +using &v4l2-input; as discussed in . + + The channel field counting +inputs was renamed to index, the video +input types were renamed as follows: + + + + struct video_channel +type + &v4l2-input; +type + + + + + VIDEO_TYPE_TV + V4L2_INPUT_TYPE_TUNER + + + VIDEO_TYPE_CAMERA + V4L2_INPUT_TYPE_CAMERA + + + + + + Unlike the tuners field +expressing the number of tuners of this input, V4L2 assumes each video +input is connected to at most one tuner. However a tuner can have more +than one input, &ie; RF connectors, and a device can have multiple +tuners. The index number of the tuner associated with the input, if +any, is stored in field tuner of +&v4l2-input;. Enumeration of tuners is discussed in . + + The redundant VIDEO_VC_TUNER flag was +dropped. Video inputs associated with a tuner are of type +V4L2_INPUT_TYPE_TUNER. The +VIDEO_VC_AUDIO flag was replaced by the +audioset field. V4L2 considers devices with +up to 32 audio inputs. Each set bit in the +audioset field represents one audio input +this video input combines with. For information about audio inputs and +how to switch between them see . + + The norm field describing the +supported video standards was replaced by +std. The V4L specification mentions a flag +VIDEO_VC_NORM indicating whether the standard can +be changed. This flag was a later addition together with the +norm field and has been removed in the +meantime. V4L2 has a similar, albeit more comprehensive approach +to video standards, see for more +information. +
+ +
+ Tuning + + The V4L VIDIOCGTUNER and +VIDIOCSTUNER ioctl and struct +video_tuner can be used to enumerate the +tuners of a V4L TV or radio device. The equivalent V4L2 ioctls are +&VIDIOC-G-TUNER; and &VIDIOC-S-TUNER; using &v4l2-tuner;. Tuners are +covered in . + + The tuner field counting tuners +was renamed to index. The fields +name, rangelow +and rangehigh remained unchanged. + + The VIDEO_TUNER_PAL, +VIDEO_TUNER_NTSC and +VIDEO_TUNER_SECAM flags indicating the supported +video standards were dropped. This information is now contained in the +associated &v4l2-input;. No replacement exists for the +VIDEO_TUNER_NORM flag indicating whether the +video standard can be switched. The mode +field to select a different video standard was replaced by a whole new +set of ioctls and structures described in . +Due to its ubiquity it should be mentioned the BTTV driver supports +several standards in addition to the regular +VIDEO_MODE_PAL (0), +VIDEO_MODE_NTSC, +VIDEO_MODE_SECAM and +VIDEO_MODE_AUTO (3). Namely N/PAL Argentina, +M/PAL, N/PAL, and NTSC Japan with numbers 3-6 (sic). + + The VIDEO_TUNER_STEREO_ON flag +indicating stereo reception became +V4L2_TUNER_SUB_STEREO in field +rxsubchans. This field also permits the +detection of monaural and bilingual audio, see the definition of +&v4l2-tuner; for details. Presently no replacement exists for the +VIDEO_TUNER_RDS_ON and +VIDEO_TUNER_MBS_ON flags. + + The VIDEO_TUNER_LOW flag was renamed +to V4L2_TUNER_CAP_LOW in the &v4l2-tuner; +capability field. + + The VIDIOCGFREQ and +VIDIOCSFREQ ioctl to change the tuner frequency +where renamed to &VIDIOC-G-FREQUENCY; and &VIDIOC-S-FREQUENCY;. They +take a pointer to a &v4l2-frequency; instead of an unsigned long +integer. +
+ +
+ Image Properties + + V4L2 has no equivalent of the +VIDIOCGPICT and VIDIOCSPICT +ioctl and struct video_picture. The following +fields where replaced by V4L2 controls accessible with the +&VIDIOC-QUERYCTRL;, &VIDIOC-G-CTRL; and &VIDIOC-S-CTRL; ioctls: + + + + struct video_picture + V4L2 Control ID + + + + + brightness + V4L2_CID_BRIGHTNESS + + + hue + V4L2_CID_HUE + + + colour + V4L2_CID_SATURATION + + + contrast + V4L2_CID_CONTRAST + + + whiteness + V4L2_CID_WHITENESS + + + + + + The V4L picture controls are assumed to range from 0 to +65535 with no particular reset value. The V4L2 API permits arbitrary +limits and defaults which can be queried with the &VIDIOC-QUERYCTRL; +ioctl. For general information about controls see . + + The depth (average number of +bits per pixel) of a video image is implied by the selected image +format. V4L2 does not explicitely provide such information assuming +applications recognizing the format are aware of the image depth and +others need not know. The palette field +moved into the &v4l2-pix-format;: + + + + struct video_picture +palette + &v4l2-pix-format; +pixfmt + + + + + VIDEO_PALETTE_GREY + V4L2_PIX_FMT_GREY + + + VIDEO_PALETTE_HI240 + V4L2_PIX_FMT_HI240 + This is a custom format used by the BTTV +driver, not one of the V4L2 standard formats. + + + + VIDEO_PALETTE_RGB565 + V4L2_PIX_FMT_RGB565 + + + VIDEO_PALETTE_RGB555 + V4L2_PIX_FMT_RGB555 + + + VIDEO_PALETTE_RGB24 + V4L2_PIX_FMT_BGR24 + + + VIDEO_PALETTE_RGB32 + V4L2_PIX_FMT_BGR32 + Presumably all V4L RGB formats are +little-endian, although some drivers might interpret them according to machine endianess. V4L2 defines little-endian, big-endian and red/blue +swapped variants. For details see . + + + + VIDEO_PALETTE_YUV422 + V4L2_PIX_FMT_YUYV + + + VIDEO_PALETTE_YUYV + VIDEO_PALETTE_YUV422 +and VIDEO_PALETTE_YUYV are the same formats. Some +V4L drivers respond to one, some to the other. + + V4L2_PIX_FMT_YUYV + + + VIDEO_PALETTE_UYVY + V4L2_PIX_FMT_UYVY + + + VIDEO_PALETTE_YUV420 + None + + + VIDEO_PALETTE_YUV411 + V4L2_PIX_FMT_Y41P + Not to be confused with +V4L2_PIX_FMT_YUV411P, which is a planar +format. + + + VIDEO_PALETTE_RAW + None V4L explains this +as: "RAW capture (BT848)" + + + VIDEO_PALETTE_YUV422P + V4L2_PIX_FMT_YUV422P + + + VIDEO_PALETTE_YUV411P + V4L2_PIX_FMT_YUV411P + Not to be confused with +V4L2_PIX_FMT_Y41P, which is a packed +format. + + + VIDEO_PALETTE_YUV420P + V4L2_PIX_FMT_YVU420 + + + VIDEO_PALETTE_YUV410P + V4L2_PIX_FMT_YVU410 + + + + + + V4L2 image formats are defined in . The image format can be selected with the +&VIDIOC-S-FMT; ioctl. +
+ +
+ Audio + + The VIDIOCGAUDIO and +VIDIOCSAUDIO ioctl and struct +video_audio are used to enumerate the +audio inputs of a V4L device. The equivalent V4L2 ioctls are +&VIDIOC-G-AUDIO; and &VIDIOC-S-AUDIO; using &v4l2-audio; as +discussed in . + + The audio "channel number" +field counting audio inputs was renamed to +index. + + On VIDIOCSAUDIO the +mode field selects one +of the VIDEO_SOUND_MONO, +VIDEO_SOUND_STEREO, +VIDEO_SOUND_LANG1 or +VIDEO_SOUND_LANG2 audio demodulation modes. When +the current audio standard is BTSC +VIDEO_SOUND_LANG2 refers to SAP and +VIDEO_SOUND_LANG1 is meaningless. Also +undocumented in the V4L specification, there is no way to query the +selected mode. On VIDIOCGAUDIO the driver returns +the actually received audio programmes in this +field. In the V4L2 API this information is stored in the &v4l2-tuner; +rxsubchans and +audmode fields, respectively. See for more information on tuners. Related to audio +modes &v4l2-audio; also reports if this is a mono or stereo +input, regardless if the source is a tuner. + + The following fields where replaced by V4L2 controls +accessible with the &VIDIOC-QUERYCTRL;, &VIDIOC-G-CTRL; and +&VIDIOC-S-CTRL; ioctls: + + + + struct +video_audio + V4L2 Control ID + + + + + volume + V4L2_CID_AUDIO_VOLUME + + + bass + V4L2_CID_AUDIO_BASS + + + treble + V4L2_CID_AUDIO_TREBLE + + + balance + V4L2_CID_AUDIO_BALANCE + + + + + + To determine which of these controls are supported by a +driver V4L provides the flags +VIDEO_AUDIO_VOLUME, +VIDEO_AUDIO_BASS, +VIDEO_AUDIO_TREBLE and +VIDEO_AUDIO_BALANCE. In the V4L2 API the +&VIDIOC-QUERYCTRL; ioctl reports if the respective control is +supported. Accordingly the VIDEO_AUDIO_MUTABLE +and VIDEO_AUDIO_MUTE flags where replaced by the +boolean V4L2_CID_AUDIO_MUTE control. + + All V4L2 controls have a step +attribute replacing the struct video_audio +step field. The V4L audio controls are +assumed to range from 0 to 65535 with no particular reset value. The +V4L2 API permits arbitrary limits and defaults which can be queried +with the &VIDIOC-QUERYCTRL; ioctl. For general information about +controls see . +
+ +
+ Frame Buffer Overlay + + The V4L2 ioctls equivalent to +VIDIOCGFBUF and VIDIOCSFBUF +are &VIDIOC-G-FBUF; and &VIDIOC-S-FBUF;. The +base field of struct +video_buffer remained unchanged, except V4L2 +defines a flag to indicate non-destructive overlays instead of a +NULL pointer. All other fields moved into the +&v4l2-pix-format; fmt substructure of +&v4l2-framebuffer;. The depth field was +replaced by pixelformat. See for a list of RGB formats and their +respective color depths. + + Instead of the special ioctls +VIDIOCGWIN and VIDIOCSWIN +V4L2 uses the general-purpose data format negotiation ioctls +&VIDIOC-G-FMT; and &VIDIOC-S-FMT;. They take a pointer to a +&v4l2-format; as argument. Here the win +member of the fmt union is used, a +&v4l2-window;. + + The x, +y, width and +height fields of struct +video_window moved into &v4l2-rect; +substructure w of struct +v4l2_window. The +chromakey, +clips, and +clipcount fields remained unchanged. Struct +video_clip was renamed to &v4l2-clip;, also +containing a struct v4l2_rect, but the +semantics are still the same. + + The VIDEO_WINDOW_INTERLACE flag was +dropped. Instead applications must set the +field field to +V4L2_FIELD_ANY or +V4L2_FIELD_INTERLACED. The +VIDEO_WINDOW_CHROMAKEY flag moved into +&v4l2-framebuffer;, under the new name +V4L2_FBUF_FLAG_CHROMAKEY. + + In V4L, storing a bitmap pointer in +clips and setting +clipcount to +VIDEO_CLIP_BITMAP (-1) requests bitmap +clipping, using a fixed size bitmap of 1024 × 625 bits. Struct +v4l2_window has a separate +bitmap pointer field for this purpose and +the bitmap size is determined by w.width and +w.height. + + The VIDIOCCAPTURE ioctl to enable or +disable overlay was renamed to &VIDIOC-OVERLAY;. +
+ +
+ Cropping + + To capture only a subsection of the full picture V4L +defines the VIDIOCGCAPTURE and +VIDIOCSCAPTURE ioctls using struct +video_capture. The equivalent V4L2 ioctls are +&VIDIOC-G-CROP; and &VIDIOC-S-CROP; using &v4l2-crop;, and the related +&VIDIOC-CROPCAP; ioctl. This is a rather complex matter, see + for details. + + The x, +y, width and +height fields moved into &v4l2-rect; +substructure c of struct +v4l2_crop. The +decimation field was dropped. In the V4L2 +API the scaling factor is implied by the size of the cropping +rectangle and the size of the captured or overlaid image. + + The VIDEO_CAPTURE_ODD +and VIDEO_CAPTURE_EVEN flags to capture only the +odd or even field, respectively, were replaced by +V4L2_FIELD_TOP and +V4L2_FIELD_BOTTOM in the field named +field of &v4l2-pix-format; and +&v4l2-window;. These structures are used to select a capture or +overlay format with the &VIDIOC-S-FMT; ioctl. +
+ +
+ Reading Images, Memory Mapping + +
+ Capturing using the read method + + There is no essential difference between reading images +from a V4L or V4L2 device using the &func-read; function, however V4L2 +drivers are not required to support this I/O method. Applications can +determine if the function is available with the &VIDIOC-QUERYCAP; +ioctl. All V4L2 devices exchanging data with applications must support +the &func-select; and &func-poll; functions. + + To select an image format and size, V4L provides the +VIDIOCSPICT and VIDIOCSWIN +ioctls. V4L2 uses the general-purpose data format negotiation ioctls +&VIDIOC-G-FMT; and &VIDIOC-S-FMT;. They take a pointer to a +&v4l2-format; as argument, here the &v4l2-pix-format; named +pix of its fmt +union is used. + + For more information about the V4L2 read interface see +. +
+
+ Capturing using memory mapping + + Applications can read from V4L devices by mapping +buffers in device memory, or more often just buffers allocated in +DMA-able system memory, into their address space. This avoids the data +copying overhead of the read method. V4L2 supports memory mapping as +well, with a few differences. + + + + + + V4L + V4L2 + + + + + + The image format must be selected before +buffers are allocated, with the &VIDIOC-S-FMT; ioctl. When no format +is selected the driver may use the last, possibly by another +application requested format. + + + Applications cannot change the number of +buffers. The it is built into the driver, unless it has a module +option to change the number when the driver module is +loaded. + The &VIDIOC-REQBUFS; ioctl allocates the +desired number of buffers, this is a required step in the initialization +sequence. + + + Drivers map all buffers as one contiguous +range of memory. The VIDIOCGMBUF ioctl is +available to query the number of buffers, the offset of each buffer +from the start of the virtual file, and the overall amount of memory +used, which can be used as arguments for the &func-mmap; +function. + Buffers are individually mapped. The +offset and size of each buffer can be determined with the +&VIDIOC-QUERYBUF; ioctl. + + + The VIDIOCMCAPTURE +ioctl prepares a buffer for capturing. It also determines the image +format for this buffer. The ioctl returns immediately, eventually with +an &EAGAIN; if no video signal had been detected. When the driver +supports more than one buffer applications can call the ioctl multiple +times and thus have multiple outstanding capture +requests.The VIDIOCSYNC ioctl +suspends execution until a particular buffer has been +filled. + Drivers maintain an incoming and outgoing +queue. &VIDIOC-QBUF; enqueues any empty buffer into the incoming +queue. Filled buffers are dequeued from the outgoing queue with the +&VIDIOC-DQBUF; ioctl. To wait until filled buffers become available this +function, &func-select; or &func-poll; can be used. The +&VIDIOC-STREAMON; ioctl must be called once after enqueuing one or +more buffers to start capturing. Its counterpart +&VIDIOC-STREAMOFF; stops capturing and dequeues all buffers from both +queues. Applications can query the signal status, if known, with the +&VIDIOC-ENUMINPUT; ioctl. + + + + + + For a more in-depth discussion of memory mapping and +examples, see . +
+
+ +
+ Reading Raw VBI Data + + Originally the V4L API did not specify a raw VBI capture +interface, only the device file /dev/vbi was +reserved for this purpose. The only driver supporting this interface +was the BTTV driver, de-facto defining the V4L VBI interface. Reading +from the device yields a raw VBI image with the following +parameters: + + + + &v4l2-vbi-format; + V4L, BTTV driver + + + + + sampling_rate + 28636363 Hz NTSC (or any other 525-line +standard); 35468950 Hz PAL and SECAM (625-line standards) + + + offset + ? + + + samples_per_line + 2048 + + + sample_format + V4L2_PIX_FMT_GREY. The last four bytes (a +machine endianess integer) contain a frame counter. + + + start[] + 10, 273 NTSC; 22, 335 PAL and SECAM + + + count[] + 16, 16Old driver +versions used different values, eventually the custom +BTTV_VBISIZE ioctl was added to query the +correct values. + + + flags + 0 + + + + + + Undocumented in the V4L specification, in Linux 2.3 the +VIDIOCGVBIFMT and +VIDIOCSVBIFMT ioctls using struct +vbi_format were added to determine the VBI +image parameters. These ioctls are only partially compatible with the +V4L2 VBI interface specified in . + + An offset field does not +exist, sample_format is supposed to be +VIDEO_PALETTE_RAW, equivalent to +V4L2_PIX_FMT_GREY. The remaining fields are +probably equivalent to &v4l2-vbi-format;. + + Apparently only the Zoran (ZR 36120) driver implements +these ioctls. The semantics differ from those specified for V4L2 in two +ways. The parameters are reset on &func-open; and +VIDIOCSVBIFMT always returns an &EINVAL; if the +parameters are invalid. +
+ +
+ Miscellaneous + + V4L2 has no equivalent of the +VIDIOCGUNIT ioctl. Applications can find the VBI +device associated with a video capture device (or vice versa) by +reopening the device and requesting VBI data. For details see +. + + No replacement exists for VIDIOCKEY, +and the V4L functions for microcode programming. A new interface for +MPEG compression and playback devices is documented in . +
+ +
+ +
+ Changes of the V4L2 API + + Soon after the V4L API was added to the kernel it was +criticised as too inflexible. In August 1998 Bill Dirks proposed a +number of improvements and began to work on documentation, example +drivers and applications. With the help of other volunteers this +eventually became the V4L2 API, not just an extension but a +replacement for the V4L API. However it took another four years and +two stable kernel releases until the new API was finally accepted for +inclusion into the kernel in its present form. + +
+ Early Versions + 1998-08-20: First version. + + 1998-08-27: The &func-select; function was introduced. + + 1998-09-10: New video standard interface. + + 1998-09-18: The VIDIOC_NONCAP ioctl +was replaced by the otherwise meaningless O_TRUNC +&func-open; flag, and the aliases O_NONCAP and +O_NOIO were defined. Applications can set this +flag if they intend to access controls only, as opposed to capture +applications which need exclusive access. The +VIDEO_STD_XXX identifiers are now ordinals +instead of flags, and the video_std_construct() +helper function takes id and transmission arguments. + + 1998-09-28: Revamped video standard. Made video controls +individually enumerable. + + 1998-10-02: The id field was +removed from struct video_standard and the +color subcarrier fields were renamed. The &VIDIOC-QUERYSTD; ioctl was +renamed to &VIDIOC-ENUMSTD;, &VIDIOC-G-INPUT; to &VIDIOC-ENUMINPUT;. A +first draft of the Codec API was released. + + 1998-11-08: Many minor changes. Most symbols have been +renamed. Some material changes to &v4l2-capability;. + + 1998-11-12: The read/write directon of some ioctls was misdefined. + + 1998-11-14: V4L2_PIX_FMT_RGB24 +changed to V4L2_PIX_FMT_BGR24, and +V4L2_PIX_FMT_RGB32 changed to +V4L2_PIX_FMT_BGR32. Audio controls are now +accessible with the &VIDIOC-G-CTRL; and &VIDIOC-S-CTRL; ioctls under +names starting with V4L2_CID_AUDIO. The +V4L2_MAJOR define was removed from +videodev.h since it was only used once in the +videodev kernel module. The +YUV422 and YUV411 planar +image formats were added. + + 1998-11-28: A few ioctl symbols changed. Interfaces for codecs and +video output devices were added. + + 1999-01-14: A raw VBI capture interface was added. + + 1999-01-19: The VIDIOC_NEXTBUF ioctl + was removed. +
+ +
+ V4L2 Version 0.16 1999-01-31 + 1999-01-27: There is now one QBUF ioctl, VIDIOC_QWBUF and VIDIOC_QRBUF +are gone. VIDIOC_QBUF takes a v4l2_buffer as a parameter. Added +digital zoom (cropping) controls. +
+ + + +
+ V4L2 Version 0.18 1999-03-16 + Added a v4l to V4L2 ioctl compatibility layer to +videodev.c. Driver writers, this changes how you implement your ioctl +handler. See the Driver Writer's Guide. Added some more control id +codes. +
+ +
+ V4L2 Version 0.19 1999-06-05 + 1999-03-18: Fill in the category and catname fields of +v4l2_queryctrl objects before passing them to the driver. Required a +minor change to the VIDIOC_QUERYCTRL handlers in the sample +drivers. + 1999-03-31: Better compatibility for v4l memory capture +ioctls. Requires changes to drivers to fully support new compatibility +features, see Driver Writer's Guide and v4l2cap.c. Added new control +IDs: V4L2_CID_HFLIP, _VFLIP. Changed V4L2_PIX_FMT_YUV422P to _YUV422P, +and _YUV411P to _YUV411P. + 1999-04-04: Added a few more control IDs. + 1999-04-07: Added the button control type. + 1999-05-02: Fixed a typo in videodev.h, and added the +V4L2_CTRL_FLAG_GRAYED (later V4L2_CTRL_FLAG_GRABBED) flag. + 1999-05-20: Definition of VIDIOC_G_CTRL was wrong causing +a malfunction of this ioctl. + 1999-06-05: Changed the value of +V4L2_CID_WHITENESS. +
+ +
+ V4L2 Version 0.20 (1999-09-10) + + Version 0.20 introduced a number of changes which were +not backward compatible with 0.19 and earlier +versions. Purpose of these changes was to simplify the API, while +making it more extensible and following common Linux driver API +conventions. + + + + Some typos in V4L2_FMT_FLAG +symbols were fixed. &v4l2-clip; was changed for compatibility with +v4l. (1999-08-30) + + + + V4L2_TUNER_SUB_LANG1 was added. +(1999-09-05) + + + + All ioctl() commands that used an integer argument now +take a pointer to an integer. Where it makes sense, ioctls will return +the actual new value in the integer pointed to by the argument, a +common convention in the V4L2 API. The affected ioctls are: +VIDIOC_PREVIEW, VIDIOC_STREAMON, VIDIOC_STREAMOFF, VIDIOC_S_FREQ, +VIDIOC_S_INPUT, VIDIOC_S_OUTPUT, VIDIOC_S_EFFECT. For example + +err = ioctl (fd, VIDIOC_XXX, V4L2_XXX); + becomes +int a = V4L2_XXX; err = ioctl(fd, VIDIOC_XXX, &a); + + + + + + All the different get- and set-format commands were +swept into one &VIDIOC-G-FMT; and &VIDIOC-S-FMT; ioctl taking a union +and a type field selecting the union member as parameter. Purpose is to +simplify the API by eliminating several ioctls and to allow new and +driver private data streams without adding new ioctls. + + This change obsoletes the following ioctls: +VIDIOC_S_INFMT, +VIDIOC_G_INFMT, +VIDIOC_S_OUTFMT, +VIDIOC_G_OUTFMT, +VIDIOC_S_VBIFMT and +VIDIOC_G_VBIFMT. The image format structure +v4l2_format was renamed to &v4l2-pix-format;, +while &v4l2-format; is now the envelopping structure for all format +negotiations. + + + + Similar to the changes above, the +VIDIOC_G_PARM and +VIDIOC_S_PARM ioctls were merged with +VIDIOC_G_OUTPARM and +VIDIOC_S_OUTPARM. A +type field in the new &v4l2-streamparm; +selects the respective union member. + + This change obsoletes the +VIDIOC_G_OUTPARM and +VIDIOC_S_OUTPARM ioctls. + + + + Control enumeration was simplified, and two new +control flags were introduced and one dropped. The +catname field was replaced by a +group field. + + Drivers can now flag unsupported and temporarily +unavailable controls with V4L2_CTRL_FLAG_DISABLED +and V4L2_CTRL_FLAG_GRABBED respectively. The +group name indicates a possibly narrower +classification than the category. In other +words, there may be multiple groups within a category. Controls within +a group would typically be drawn within a group box. Controls in +different categories might have a greater separation, or may even +appear in separate windows. + + + + The &v4l2-buffer; timestamp +was changed to a 64 bit integer, containing the sampling or output +time of the frame in nanoseconds. Additionally timestamps will be in +absolute system time, not starting from zero at the beginning of a +stream. The data type name for timestamps is stamp_t, defined as a +signed 64-bit integer. Output devices should not send a buffer out +until the time in the timestamp field has arrived. I would like to +follow SGI's lead, and adopt a multimedia timestamping system like +their UST (Unadjusted System Time). See +http://reality.sgi.com/cpirazzi_engr/lg/time/intro.html. [This link is +no longer valid.] UST uses timestamps that are 64-bit signed integers +(not struct timeval's) and given in nanosecond units. The UST clock +starts at zero when the system is booted and runs continuously and +uniformly. It takes a little over 292 years for UST to overflow. There +is no way to set the UST clock. The regular Linux time-of-day clock +can be changed periodically, which would cause errors if it were being +used for timestamping a multimedia stream. A real UST style clock will +require some support in the kernel that is not there yet. But in +anticipation, I will change the timestamp field to a 64-bit integer, +and I will change the v4l2_masterclock_gettime() function (used only +by drivers) to return a 64-bit integer. + + + + A sequence field was added +to &v4l2-buffer;. The sequence field counts +captured frames, it is ignored by output devices. When a capture +driver drops a frame, the sequence number of that frame is +skipped. + + +
+ +
+ V4L2 Version 0.20 incremental changes + + + 1999-12-23: In &v4l2-vbi-format; the +reserved1 field became +offset. Previously drivers were required to +clear the reserved1 field. + + 2000-01-13: The + V4L2_FMT_FLAG_NOT_INTERLACED flag was added. + + 2000-07-31: The linux/poll.h header +is now included by videodev.h for compatibility +with the original videodev.h file. + + 2000-11-20: V4L2_TYPE_VBI_OUTPUT and +V4L2_PIX_FMT_Y41P were added. + + 2000-11-25: V4L2_TYPE_VBI_INPUT was +added. + + 2000-12-04: A couple typos in symbol names were fixed. + + 2001-01-18: To avoid namespace conflicts the +fourcc macro defined in the +videodev.h header file was renamed to +v4l2_fourcc. + + 2001-01-25: A possible driver-level compatibility problem +between the videodev.h file in Linux 2.4.0 and +the videodev.h file included in the +videodevX patch was fixed. Users of an earlier +version of videodevX on Linux 2.4.0 should +recompile their V4L and V4L2 drivers. + + 2001-01-26: A possible kernel-level incompatibility +between the videodev.h file in the +videodevX patch and the +videodev.h file in Linux 2.2.x with devfs patches +applied was fixed. + + 2001-03-02: Certain V4L ioctls which pass data in both +direction although they are defined with read-only parameter, did not +work correctly through the backward compatibility layer. +[Solution?] + + 2001-04-13: Big endian 16-bit RGB formats were added. + + 2001-09-17: New YUV formats and the &VIDIOC-G-FREQUENCY; and +&VIDIOC-S-FREQUENCY; ioctls were added. (The old +VIDIOC_G_FREQ and +VIDIOC_S_FREQ ioctls did not take multiple tuners +into account.) + + 2000-09-18: V4L2_BUF_TYPE_VBI was +added. This may break compatibility as the +&VIDIOC-G-FMT; and &VIDIOC-S-FMT; ioctls may fail now if the struct +v4l2_fmt type +field does not contain V4L2_BUF_TYPE_VBI. In the +documentation of the &v4l2-vbi-format; +offset field the ambiguous phrase "rising +edge" was changed to "leading edge". +
+ +
+ V4L2 Version 0.20 2000-11-23 + + A number of changes were made to the raw VBI +interface. + + + + Figures clarifying the line numbering scheme were +added to the V4L2 API specification. The +start[0] and +start[1] fields no longer count line +numbers beginning at zero. Rationale: a) The previous definition was +unclear. b) The start[] values are ordinal +numbers. c) There is no point in inventing a new line numbering +scheme. We now use line number as defined by ITU-R, period. +Compatibility: Add one to the start values. Applications depending on +the previous semantics may not function correctly. + + + + The restriction "count[0] > 0 and count[1] > 0" +has been relaxed to "(count[0] + count[1]) > 0". Rationale: +Drivers may allocate resources at scan line granularity and some data +services are transmitted only on the first field. The comment that +both count values will usually be equal is +misleading and pointless and has been removed. This change +breaks compatibility with earlier versions: +Drivers may return EINVAL, applications may not function +correctly. + + + + Drivers are again permitted to return negative +(unknown) start values as proposed earlier. Why this feature was +dropped is unclear. This change may break +compatibility with applications depending on the start +values being positive. The use of EBUSY and +EINVAL error codes with the &VIDIOC-S-FMT; ioctl +was clarified. The &EBUSY; was finally documented, and the +reserved2 field which was previously +mentioned only in the videodev.h header +file. + + + + New buffer types +V4L2_TYPE_VBI_INPUT and +V4L2_TYPE_VBI_OUTPUT were added. The former is an +alias for the old V4L2_TYPE_VBI, the latter was +missing in the videodev.h file. + + +
+ +
+ V4L2 Version 0.20 2002-07-25 + Added sliced VBI interface proposal. +
+ +
+ V4L2 in Linux 2.5.46, 2002-10 + + Around October-November 2002, prior to an announced +feature freeze of Linux 2.5, the API was revised, drawing from +experience with V4L2 0.20. This unnamed version was finally merged +into Linux 2.5.46. + + + + As specified in , drivers +must make related device functions available under all minor device +numbers. + + + + The &func-open; function requires access mode +O_RDWR regardless of the device type. All V4L2 +drivers exchanging data with applications must support the +O_NONBLOCK flag. The O_NOIO +flag, a V4L2 symbol which aliased the meaningless +O_TRUNC to indicate accesses without data +exchange (panel applications) was dropped. Drivers must stay in "panel +mode" until the application attempts to initiate a data exchange, see +. + + + + The &v4l2-capability; changed dramatically. Note that +also the size of the structure changed, which is encoded in the ioctl +request code, thus older V4L2 devices will respond with an &EINVAL; to +the new &VIDIOC-QUERYCAP; ioctl. + + There are new fields to identify the driver, a new RDS +device function V4L2_CAP_RDS_CAPTURE, the +V4L2_CAP_AUDIO flag indicates if the device has +any audio connectors, another I/O capability +V4L2_CAP_ASYNCIO can be flagged. In response to +these changes the type field became a bit +set and was merged into the flags field. +V4L2_FLAG_TUNER was renamed to +V4L2_CAP_TUNER, +V4L2_CAP_VIDEO_OVERLAY replaced +V4L2_FLAG_PREVIEW and +V4L2_CAP_VBI_CAPTURE and +V4L2_CAP_VBI_OUTPUT replaced +V4L2_FLAG_DATA_SERVICE. +V4L2_FLAG_READ and +V4L2_FLAG_WRITE were merged into +V4L2_CAP_READWRITE. + + The redundant fields +inputs, outputs +and audios were removed. These properties +can be determined as described in and . + + The somewhat volatile and therefore barely useful +fields maxwidth, +maxheight, +minwidth, +minheight, +maxframerate were removed. This information +is available as described in and +. + + V4L2_FLAG_SELECT was removed. We +believe the select() function is important enough to require support +of it in all V4L2 drivers exchanging data with applications. The +redundant V4L2_FLAG_MONOCHROME flag was removed, +this information is available as described in . + + + + In &v4l2-input; the +assoc_audio field and the +capability field and its only flag +V4L2_INPUT_CAP_AUDIO was replaced by the new +audioset field. Instead of linking one +video input to one audio input this field reports all audio inputs +this video input combines with. + + New fields are tuner +(reversing the former link from tuners to video inputs), +std and +status. + + Accordingly &v4l2-output; lost its +capability and +assoc_audio fields. +audioset, +modulator and +std where added instead. + + + + The &v4l2-audio; field +audio was renamed to +index, for consistency with other +structures. A new capability flag +V4L2_AUDCAP_STEREO was added to indicated if the +audio input in question supports stereo sound. +V4L2_AUDCAP_EFFECTS and the corresponding +V4L2_AUDMODE flags where removed. This can be +easily implemented using controls. (However the same applies to AVL +which is still there.) + + Again for consistency the &v4l2-audioout; field +audio was renamed to +index. + + + + The &v4l2-tuner; +input field was replaced by an +index field, permitting devices with +multiple tuners. The link between video inputs and tuners is now +reversed, inputs point to their tuner. The +std substructure became a +simple set (more about this below) and moved into &v4l2-input;. A +type field was added. + + Accordingly in &v4l2-modulator; the +output was replaced by an +index field. + + In &v4l2-frequency; the +port field was replaced by a +tuner field containing the respective tuner +or modulator index number. A tuner type +field was added and the reserved field +became larger for future extensions (satellite tuners in +particular). + + + + The idea of completely transparent video standards was +dropped. Experience showed that applications must be able to work with +video standards beyond presenting the user a menu. Instead of +enumerating supported standards with an ioctl applications can now +refer to standards by &v4l2-std-id; and symbols defined in the +videodev2.h header file. For details see . The &VIDIOC-G-STD; and +&VIDIOC-S-STD; now take a pointer to this type as argument. +&VIDIOC-QUERYSTD; was added to autodetect the received standard, if +the hardware has this capability. In &v4l2-standard; an +index field was added for &VIDIOC-ENUMSTD;. +A &v4l2-std-id; field named id was added as +machine readable identifier, also replacing the +transmission field. The misleading +framerate field was renamed +to frameperiod. The now obsolete +colorstandard information, originally +needed to distguish between variations of standards, were +removed. + + Struct v4l2_enumstd ceased to +be. &VIDIOC-ENUMSTD; now takes a pointer to a &v4l2-standard; +directly. The information which standards are supported by a +particular video input or output moved into &v4l2-input; and +&v4l2-output; fields named std, +respectively. + + + + The &v4l2-queryctrl; fields +category and +group did not catch on and/or were not +implemented as expected and therefore removed. + + + + The &VIDIOC-TRY-FMT; ioctl was added to negotiate data +formats as with &VIDIOC-S-FMT;, but without the overhead of +programming the hardware and regardless of I/O in progress. + + In &v4l2-format; the fmt +union was extended to contain &v4l2-window;. All image format +negotiations are now possible with VIDIOC_G_FMT, +VIDIOC_S_FMT and +VIDIOC_TRY_FMT; ioctl. The +VIDIOC_G_WIN and +VIDIOC_S_WIN ioctls to prepare for a video +overlay were removed. The type field +changed to type &v4l2-buf-type; and the buffer type names changed as +follows. + + + + Old defines + &v4l2-buf-type; + + + + + V4L2_BUF_TYPE_CAPTURE + V4L2_BUF_TYPE_VIDEO_CAPTURE + + + V4L2_BUF_TYPE_CODECIN + Omitted for now + + + V4L2_BUF_TYPE_CODECOUT + Omitted for now + + + V4L2_BUF_TYPE_EFFECTSIN + Omitted for now + + + V4L2_BUF_TYPE_EFFECTSIN2 + Omitted for now + + + V4L2_BUF_TYPE_EFFECTSOUT + Omitted for now + + + V4L2_BUF_TYPE_VIDEOOUT + V4L2_BUF_TYPE_VIDEO_OUTPUT + + + - + V4L2_BUF_TYPE_VIDEO_OVERLAY + + + - + V4L2_BUF_TYPE_VBI_CAPTURE + + + - + V4L2_BUF_TYPE_VBI_OUTPUT + + + - + V4L2_BUF_TYPE_SLICED_VBI_CAPTURE + + + - + V4L2_BUF_TYPE_SLICED_VBI_OUTPUT + + + V4L2_BUF_TYPE_PRIVATE_BASE + V4L2_BUF_TYPE_PRIVATE + + + + + + + + In &v4l2-fmtdesc; a &v4l2-buf-type; field named +type was added as in &v4l2-format;. The +VIDIOC_ENUM_FBUFFMT ioctl is no longer needed and +was removed. These calls can be replaced by &VIDIOC-ENUM-FMT; with +type V4L2_BUF_TYPE_VIDEO_OVERLAY. + + + + In &v4l2-pix-format; the +depth field was removed, assuming +applications which recognize the format by its four-character-code +already know the color depth, and others do not care about it. The +same rationale lead to the removal of the +V4L2_FMT_FLAG_COMPRESSED flag. The +V4L2_FMT_FLAG_SWCONVECOMPRESSED flag was removed +because drivers are not supposed to convert images in kernel space. A +user library of conversion functions should be provided instead. The +V4L2_FMT_FLAG_BYTESPERLINE flag was redundant. +Applications can set the bytesperline field +to zero to get a reasonable default. Since the remaining flags were +replaced as well, the flags field itself +was removed. + The interlace flags were replaced by a &v4l2-field; +value in a newly added field +field. + + + + Old flag + &v4l2-field; + + + + + V4L2_FMT_FLAG_NOT_INTERLACED + ? + + + V4L2_FMT_FLAG_INTERLACED += V4L2_FMT_FLAG_COMBINED + V4L2_FIELD_INTERLACED + + + V4L2_FMT_FLAG_TOPFIELD += V4L2_FMT_FLAG_ODDFIELD + V4L2_FIELD_TOP + + + V4L2_FMT_FLAG_BOTFIELD += V4L2_FMT_FLAG_EVENFIELD + V4L2_FIELD_BOTTOM + + + - + V4L2_FIELD_SEQ_TB + + + - + V4L2_FIELD_SEQ_BT + + + - + V4L2_FIELD_ALTERNATE + + + + + + The color space flags were replaced by a +&v4l2-colorspace; value in a newly added +colorspace field, where one of +V4L2_COLORSPACE_SMPTE170M, +V4L2_COLORSPACE_BT878, +V4L2_COLORSPACE_470_SYSTEM_M or +V4L2_COLORSPACE_470_SYSTEM_BG replaces +V4L2_FMT_CS_601YUV. + + + + In &v4l2-requestbuffers; the +type field was properly defined as +&v4l2-buf-type;. Buffer types changed as mentioned above. A new +memory field of type &v4l2-memory; was +added to distinguish between I/O methods using buffers allocated +by the driver or the application. See for +details. + + + + In &v4l2-buffer; the type +field was properly defined as &v4l2-buf-type;. Buffer types changed as +mentioned above. A field field of type +&v4l2-field; was added to indicate if a buffer contains a top or +bottom field. The old field flags were removed. Since no unadjusted +system time clock was added to the kernel as planned, the +timestamp field changed back from type +stamp_t, an unsigned 64 bit integer expressing the sample time in +nanoseconds, to struct timeval. With the +addition of a second memory mapping method the +offset field moved into union +m, and a new +memory field of type &v4l2-memory; was +added to distinguish between I/O methods. See +for details. + + The V4L2_BUF_REQ_CONTIG +flag was used by the V4L compatibility layer, after changes to this +code it was no longer needed. The +V4L2_BUF_ATTR_DEVICEMEM flag would indicate if +the buffer was indeed allocated in device memory rather than DMA-able +system memory. It was barely useful and so was removed. + + + + In &v4l2-framebuffer; the +base[3] array anticipating double- and +triple-buffering in off-screen video memory, however without defining +a synchronization mechanism, was replaced by a single pointer. The +V4L2_FBUF_CAP_SCALEUP and +V4L2_FBUF_CAP_SCALEDOWN flags were removed. +Applications can determine this capability more accurately using the +new cropping and scaling interface. The +V4L2_FBUF_CAP_CLIPPING flag was replaced by +V4L2_FBUF_CAP_LIST_CLIPPING and +V4L2_FBUF_CAP_BITMAP_CLIPPING. + + + + In &v4l2-clip; the x, +y, width and +height field moved into a +c substructure of type &v4l2-rect;. The +x and y fields +were renamed to left and +top, &ie; offsets to a context dependent +origin. + + + + In &v4l2-window; the x, +y, width and +height field moved into a +w substructure as above. A +field field of type %v4l2-field; was added +to distinguish between field and frame (interlaced) overlay. + + + + The digital zoom interface, including struct +v4l2_zoomcap, struct +v4l2_zoom, +V4L2_ZOOM_NONCAP and +V4L2_ZOOM_WHILESTREAMING was replaced by a new +cropping and scaling interface. The previously unused struct +v4l2_cropcap and +v4l2_crop where redefined for this purpose. +See for details. + + + + In &v4l2-vbi-format; the +SAMPLE_FORMAT field now contains a +four-character-code as used to identify video image formats and +V4L2_PIX_FMT_GREY replaces the +V4L2_VBI_SF_UBYTE define. The +reserved field was extended. + + + + In &v4l2-captureparm; the type of the +timeperframe field changed from unsigned +long to &v4l2-fract;. This allows the accurate expression of multiples +of the NTSC-M frame rate 30000 / 1001. A new field +readbuffers was added to control the driver +behaviour in read I/O mode. + + Similar changes were made to &v4l2-outputparm;. + + + + The struct v4l2_performance +and VIDIOC_G_PERF ioctl were dropped. Except when +using the read/write I/O method, which is +limited anyway, this information is already available to +applications. + + + + The example transformation from RGB to YCbCr color +space in the old V4L2 documentation was inaccurate, this has been +corrected in . + + +
+ +
+ V4L2 2003-06-19 + + + + A new capability flag +V4L2_CAP_RADIO was added for radio devices. Prior +to this change radio devices would identify solely by having exactly one +tuner whose type field reads V4L2_TUNER_RADIO. + + + + An optional driver access priority mechanism was +added, see for details. + + + + The audio input and output interface was found to be +incomplete. + Previously the &VIDIOC-G-AUDIO; +ioctl would enumerate the available audio inputs. An ioctl to +determine the current audio input, if more than one combines with the +current video input, did not exist. So +VIDIOC_G_AUDIO was renamed to +VIDIOC_G_AUDIO_OLD, this ioctl will be removed in +the future. The &VIDIOC-ENUMAUDIO; ioctl was added to enumerate +audio inputs, while &VIDIOC-G-AUDIO; now reports the current audio +input. + The same changes were made to &VIDIOC-G-AUDOUT; and +&VIDIOC-ENUMAUDOUT;. + Until further the "videodev" module will automatically +translate between the old and new ioctls, but drivers and applications +must be updated to successfully compile again. + + + + The &VIDIOC-OVERLAY; ioctl was incorrectly defined with +write-read parameter. It was changed to write-only, while the write-read +version was renamed to VIDIOC_OVERLAY_OLD. The old +ioctl will be removed in the future. Until further the "videodev" +kernel module will automatically translate to the new version, so drivers +must be recompiled, but not applications. + + + + incorrectly stated that +clipping rectangles define regions where the video can be seen. +Correct is that clipping rectangles define regions where +no video shall be displayed and so the graphics +surface can be seen. + + + + The &VIDIOC-S-PARM; and &VIDIOC-S-CTRL; ioctls were +defined with write-only parameter, inconsistent with other ioctls +modifying their argument. They were changed to write-read, while a +_OLD suffix was added to the write-only versions. +The old ioctls will be removed in the future. Drivers and +applications assuming a constant parameter need an update. + + +
+ +
+ V4L2 2003-11-05 + + + In the following pixel +formats were incorrectly transferred from Bill Dirks' V4L2 +specification. Descriptions below refer to bytes in memory, in +ascending address order. + + + + Symbol + In this document prior to revision +0.5 + Corrected + + + + + V4L2_PIX_FMT_RGB24 + B, G, R + R, G, B + + + V4L2_PIX_FMT_BGR24 + R, G, B + B, G, R + + + V4L2_PIX_FMT_RGB32 + B, G, R, X + R, G, B, X + + + V4L2_PIX_FMT_BGR32 + R, G, B, X + B, G, R, X + + + + The +V4L2_PIX_FMT_BGR24 example was always +correct. + In the mapping +of the V4L VIDEO_PALETTE_RGB24 and +VIDEO_PALETTE_RGB32 formats to V4L2 pixel formats +was accordingly corrected. + + + + Unrelated to the fixes above, drivers may still +interpret some V4L2 RGB pixel formats differently. These issues have +yet to be addressed, for details see . + + +
+ +
+ V4L2 in Linux 2.6.6, 2004-05-09 + + + The &VIDIOC-CROPCAP; ioctl was incorrectly defined +with read-only parameter. It is now defined as write-read ioctl, while +the read-only version was renamed to +VIDIOC_CROPCAP_OLD. The old ioctl will be removed +in the future. + + +
+ +
+ V4L2 in Linux 2.6.8 + + + A new field input (former +reserved[0]) was added to the &v4l2-buffer; +structure. Purpose of this field is to alternate between video inputs +(⪚ cameras) in step with the video capturing process. This function +must be enabled with the new V4L2_BUF_FLAG_INPUT +flag. The flags field is no longer +read-only. + + +
+ +
+ V4L2 spec erratum 2004-08-01 + + + + The return value of the + function was incorrectly documented. + + + + Audio output ioctls end in -AUDOUT, not -AUDIOOUT. + + + + In the Current Audio Input example the +VIDIOC_G_AUDIO ioctl took the wrong +argument. + + + + The documentation of the &VIDIOC-QBUF; and +&VIDIOC-DQBUF; ioctls did not mention the &v4l2-buffer; +memory field. It was also missing from +examples. Also on the VIDIOC_DQBUF page the &EIO; +was not documented. + + +
+ +
+ V4L2 in Linux 2.6.14 + + + A new sliced VBI interface was added. It is documented +in and replaces the interface first +proposed in V4L2 specification 0.8. + + +
+ +
+ V4L2 in Linux 2.6.15 + + + The &VIDIOC-LOG-STATUS; ioctl was added. + + + + New video standards +V4L2_STD_NTSC_443, +V4L2_STD_SECAM_LC, +V4L2_STD_SECAM_DK (a set of SECAM D, K and K1), +and V4L2_STD_ATSC (a set of +V4L2_STD_ATSC_8_VSB and +V4L2_STD_ATSC_16_VSB) were defined. Note the +V4L2_STD_525_60 set now includes +V4L2_STD_NTSC_443. See also . + + + + The VIDIOC_G_COMP and +VIDIOC_S_COMP ioctl were renamed to +VIDIOC_G_MPEGCOMP and +VIDIOC_S_MPEGCOMP respectively. Their argument +was replaced by a struct +v4l2_mpeg_compression pointer. (The +VIDIOC_G_MPEGCOMP and +VIDIOC_S_MPEGCOMP ioctls where removed in Linux +2.6.25.) + + +
+ +
+ V4L2 spec erratum 2005-11-27 + The capture example in +called the &VIDIOC-S-CROP; ioctl without checking if cropping is +supported. In the video standard selection example in + the &VIDIOC-S-STD; call used the wrong +argument type. +
+ +
+ V4L2 spec erratum 2006-01-10 + + + The V4L2_IN_ST_COLOR_KILL flag in +&v4l2-input; not only indicates if the color killer is enabled, but +also if it is active. (The color killer disables color decoding when +it detects no color in the video signal to improve the image +quality.) + + + + &VIDIOC-S-PARM; is a write-read ioctl, not write-only as +stated on its reference page. The ioctl changed in 2003 as noted above. + + +
+ +
+ V4L2 spec erratum 2006-02-03 + + + In &v4l2-captureparm; and &v4l2-outputparm; the +timeperframe field gives the time in +seconds, not microseconds. + + +
+ +
+ V4L2 spec erratum 2006-02-04 + + + The clips field in +&v4l2-window; must point to an array of &v4l2-clip;, not a linked +list, because drivers ignore the struct +v4l2_clip.next +pointer. + + +
+ +
+ V4L2 in Linux 2.6.17 + + + New video standard macros were added: +V4L2_STD_NTSC_M_KR (NTSC M South Korea), and the +sets V4L2_STD_MN, +V4L2_STD_B, V4L2_STD_GH and +V4L2_STD_DK. The +V4L2_STD_NTSC and +V4L2_STD_SECAM sets now include +V4L2_STD_NTSC_M_KR and +V4L2_STD_SECAM_LC respectively. + + + + A new V4L2_TUNER_MODE_LANG1_LANG2 +was defined to record both languages of a bilingual program. The +use of V4L2_TUNER_MODE_STEREO for this purpose +is deprecated now. See the &VIDIOC-G-TUNER; section for +details. + + +
+ +
+ V4L2 spec erratum 2006-09-23 (Draft 0.15) + + + In various places +V4L2_BUF_TYPE_SLICED_VBI_CAPTURE and +V4L2_BUF_TYPE_SLICED_VBI_OUTPUT of the sliced VBI +interface were not mentioned along with other buffer types. + + + + In it was clarified +that the &v4l2-audio; mode field is a flags +field. + + + + did not mention the +sliced VBI and radio capability flags. + + + + In it was +clarified that applications must initialize the tuner +type field of &v4l2-frequency; before +calling &VIDIOC-S-FREQUENCY;. + + + + The reserved array +in &v4l2-requestbuffers; has 2 elements, not 32. + + + + In and the device file names +/dev/vout which never caught on were replaced +by /dev/video. + + + + With Linux 2.6.15 the possible range for VBI device minor +numbers was extended from 224-239 to 224-255. Accordingly device file names +/dev/vbi0 to /dev/vbi31 are +possible now. + + +
+ +
+ V4L2 in Linux 2.6.18 + + + New ioctls &VIDIOC-G-EXT-CTRLS;, &VIDIOC-S-EXT-CTRLS; +and &VIDIOC-TRY-EXT-CTRLS; were added, a flag to skip unsupported +controls with &VIDIOC-QUERYCTRL;, new control types +V4L2_CTRL_TYPE_INTEGER64 and +V4L2_CTRL_TYPE_CTRL_CLASS (), and new control flags +V4L2_CTRL_FLAG_READ_ONLY, +V4L2_CTRL_FLAG_UPDATE, +V4L2_CTRL_FLAG_INACTIVE and +V4L2_CTRL_FLAG_SLIDER (). See for details. + + +
+ +
+ V4L2 in Linux 2.6.19 + + + In &v4l2-sliced-vbi-cap; a buffer type field was added +replacing a reserved field. Note on architectures where the size of +enum types differs from int types the size of the structure changed. +The &VIDIOC-G-SLICED-VBI-CAP; ioctl was redefined from being read-only +to write-read. Applications must initialize the type field and clear +the reserved fields now. These changes may break the +compatibility with older drivers and applications. + + + + The ioctls &VIDIOC-ENUM-FRAMESIZES; and +&VIDIOC-ENUM-FRAMEINTERVALS; were added. + + + + A new pixel format V4L2_PIX_FMT_RGB444 () was added. + + +
+ +
+ V4L2 spec erratum 2006-10-12 (Draft 0.17) + + + V4L2_PIX_FMT_HM12 () is a YUV 4:2:0, not 4:2:2 format. + + +
+ +
+ V4L2 in Linux 2.6.21 + + + The videodev2.h header file is +now dual licensed under GNU General Public License version two or +later, and under a 3-clause BSD-style license. + + +
+ +
+ V4L2 in Linux 2.6.22 + + + Two new field orders + V4L2_FIELD_INTERLACED_TB and + V4L2_FIELD_INTERLACED_BT were + added. See for details. + + + + Three new clipping/blending methods with a global or +straight or inverted local alpha value were added to the video overlay +interface. See the description of the &VIDIOC-G-FBUF; and +&VIDIOC-S-FBUF; ioctls for details. + A new global_alpha field +was added to v4l2_window, +extending the structure. This may break +compatibility with applications using a struct +v4l2_window directly. However the VIDIOC_G/S/TRY_FMT ioctls, which take a +pointer to a v4l2_format parent +structure with padding bytes at the end, are not affected. + + + + The format of the chromakey +field in &v4l2-window; changed from "host order RGB32" to a pixel +value in the same format as the framebuffer. This may break +compatibility with existing applications. Drivers +supporting the "host order RGB32" format are not known. + + + +
+ +
+ V4L2 in Linux 2.6.24 + + + The pixel formats +V4L2_PIX_FMT_PAL8, +V4L2_PIX_FMT_YUV444, +V4L2_PIX_FMT_YUV555, +V4L2_PIX_FMT_YUV565 and +V4L2_PIX_FMT_YUV32 were added. + + +
+ +
+ V4L2 in Linux 2.6.25 + + + The pixel formats +V4L2_PIX_FMT_Y16 and +V4L2_PIX_FMT_SBGGR16 were added. + + + New controls +V4L2_CID_POWER_LINE_FREQUENCY, +V4L2_CID_HUE_AUTO, +V4L2_CID_WHITE_BALANCE_TEMPERATURE, +V4L2_CID_SHARPNESS and +V4L2_CID_BACKLIGHT_COMPENSATION were added. The +controls V4L2_CID_BLACK_LEVEL, +V4L2_CID_WHITENESS, +V4L2_CID_HCENTER and +V4L2_CID_VCENTER were deprecated. + + + + A Camera controls +class was added, with the new controls +V4L2_CID_EXPOSURE_AUTO, +V4L2_CID_EXPOSURE_ABSOLUTE, +V4L2_CID_EXPOSURE_AUTO_PRIORITY, +V4L2_CID_PAN_RELATIVE, +V4L2_CID_TILT_RELATIVE, +V4L2_CID_PAN_RESET, +V4L2_CID_TILT_RESET, +V4L2_CID_PAN_ABSOLUTE, +V4L2_CID_TILT_ABSOLUTE, +V4L2_CID_FOCUS_ABSOLUTE, +V4L2_CID_FOCUS_RELATIVE and +V4L2_CID_FOCUS_AUTO. + + + The VIDIOC_G_MPEGCOMP and +VIDIOC_S_MPEGCOMP ioctls, which were superseded +by the extended controls +interface in Linux 2.6.18, where finally removed from the +videodev2.h header file. + + +
+ +
+ V4L2 in Linux 2.6.26 + + + The pixel formats +V4L2_PIX_FMT_Y16 and +V4L2_PIX_FMT_SBGGR16 were added. + + + Added user controls +V4L2_CID_CHROMA_AGC and +V4L2_CID_COLOR_KILLER. + + +
+ +
+ V4L2 in Linux 2.6.27 + + + The &VIDIOC-S-HW-FREQ-SEEK; ioctl and the +V4L2_CAP_HW_FREQ_SEEK capability were added. + + + The pixel formats +V4L2_PIX_FMT_YVYU, +V4L2_PIX_FMT_PCA501, +V4L2_PIX_FMT_PCA505, +V4L2_PIX_FMT_PCA508, +V4L2_PIX_FMT_PCA561, +V4L2_PIX_FMT_SGBRG8, +V4L2_PIX_FMT_PAC207 and +V4L2_PIX_FMT_PJPG were added. + + +
+ +
+ V4L2 in Linux 2.6.28 + + + Added V4L2_MPEG_AUDIO_ENCODING_AAC and +V4L2_MPEG_AUDIO_ENCODING_AC3 MPEG audio encodings. + + + Added V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC MPEG +video encoding. + + + The pixel formats +V4L2_PIX_FMT_SGRBG10 and +V4L2_PIX_FMT_SGRBG10DPCM8 were added. + + +
+ +
+ V4L2 in Linux 2.6.29 + + + The VIDIOC_G_CHIP_IDENT ioctl was renamed +to VIDIOC_G_CHIP_IDENT_OLD and &VIDIOC-DBG-G-CHIP-IDENT; +was introduced in its place. The old struct v4l2_chip_ident +was renamed to v4l2_chip_ident_old. + + + The pixel formats +V4L2_PIX_FMT_VYUY, +V4L2_PIX_FMT_NV16 and +V4L2_PIX_FMT_NV61 were added. + + + Added camera controls +V4L2_CID_ZOOM_ABSOLUTE, +V4L2_CID_ZOOM_RELATIVE, +V4L2_CID_ZOOM_CONTINUOUS and +V4L2_CID_PRIVACY. + + +
+
+ V4L2 in Linux 2.6.30 + + + New control flag V4L2_CTRL_FLAG_WRITE_ONLY was added. + + + New control V4L2_CID_COLORFX was added. + + +
+
+ V4L2 in Linux 2.6.32 + + + In order to be easier to compare a V4L2 API and a kernel +version, now V4L2 API is numbered using the Linux Kernel version numeration. + + + Finalized the RDS capture API. See for +more information. + + + Added new capabilities for modulators and RDS encoders. + + + Add description for libv4l API. + + + Added support for string controls via new type V4L2_CTRL_TYPE_STRING. + + + Added V4L2_CID_BAND_STOP_FILTER documentation. + + + Added FM Modulator (FM TX) Extended Control Class: V4L2_CTRL_CLASS_FM_TX and their Control IDs. + + + Added Remote Controller chapter, describing the default Remote Controller mapping for media devices. + + +
+
+ +
+ Relation of V4L2 to other Linux multimedia APIs + +
+ X Video Extension + + The X Video Extension (abbreviated XVideo or just Xv) is +an extension of the X Window system, implemented for example by the +XFree86 project. Its scope is similar to V4L2, an API to video capture +and output devices for X clients. Xv allows applications to display +live video in a window, send window contents to a TV output, and +capture or output still images in XPixmaps + This is not implemented in XFree86. + . With their implementation XFree86 makes the +extension available across many operating systems and +architectures. + + Because the driver is embedded into the X server Xv has a +number of advantages over the V4L2 video +overlay interface. The driver can easily determine the overlay +target, &ie; visible graphics memory or off-screen buffers for a +destructive overlay. It can program the RAMDAC for a non-destructive +overlay, scaling or color-keying, or the clipping functions of the +video capture hardware, always in sync with drawing operations or +windows moving or changing their stacking order. + + To combine the advantages of Xv and V4L a special Xv +driver exists in XFree86 and XOrg, just programming any overlay capable +Video4Linux device it finds. To enable it +/etc/X11/XF86Config must contain these lines: + +Section "Module" + Load "v4l" +EndSection + + As of XFree86 4.2 this driver still supports only V4L +ioctls, however it should work just fine with all V4L2 devices through +the V4L2 backward-compatibility layer. Since V4L2 permits multiple +opens it is possible (if supported by the V4L2 driver) to capture +video while an X client requested video overlay. Restrictions of +simultaneous capturing and overlay are discussed in apply. + + Only marginally related to V4L2, XFree86 extended Xv to +support hardware YUV to RGB conversion and scaling for faster video +playback, and added an interface to MPEG-2 decoding hardware. This API +is useful to display images captured with V4L2 devices. +
+ +
+ Digital Video + + V4L2 does not support digital terrestrial, cable or +satellite broadcast. A separate project aiming at digital receivers +exists. You can find its homepage at http://linuxtv.org. The Linux DVB API +has no connection to the V4L2 API except that drivers for hybrid +hardware may support both. +
+ +
+ Audio Interfaces + + [to do - OSS/ALSA] +
+
+ +
+ Experimental API Elements + + The following V4L2 API elements are currently experimental +and may change in the future. + + + + Video Output Overlay (OSD) Interface, . + + + V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY, + &v4l2-buf-type;, . + + + V4L2_CAP_VIDEO_OUTPUT_OVERLAY, +&VIDIOC-QUERYCAP; ioctl, . + + + &VIDIOC-ENUM-FRAMESIZES; and +&VIDIOC-ENUM-FRAMEINTERVALS; ioctls. + + + &VIDIOC-G-ENC-INDEX; ioctl. + + + &VIDIOC-ENCODER-CMD; and &VIDIOC-TRY-ENCODER-CMD; +ioctls. + + + &VIDIOC-DBG-G-REGISTER; and &VIDIOC-DBG-S-REGISTER; +ioctls. + + + &VIDIOC-DBG-G-CHIP-IDENT; ioctl. + + +
+ +
+ Obsolete API Elements + + The following V4L2 API elements were superseded by new +interfaces and should not be implemented in new drivers. + + + + VIDIOC_G_MPEGCOMP and +VIDIOC_S_MPEGCOMP ioctls. Use Extended Controls, +. + + +
+ + diff --git a/Documentation/DocBook/v4l/controls.xml b/Documentation/DocBook/v4l/controls.xml new file mode 100644 index 000000000000..f492accb691d --- /dev/null +++ b/Documentation/DocBook/v4l/controls.xml @@ -0,0 +1,2049 @@ +
+ User Controls + + Devices typically have a number of user-settable controls +such as brightness, saturation and so on, which would be presented to +the user on a graphical user interface. But, different devices +will have different controls available, and furthermore, the range of +possible values, and the default value will vary from device to +device. The control ioctls provide the information and a mechanism to +create a nice user interface for these controls that will work +correctly with any device. + + All controls are accessed using an ID value. V4L2 defines +several IDs for specific purposes. Drivers can also implement their +own custom controls using V4L2_CID_PRIVATE_BASE +and higher values. The pre-defined control IDs have the prefix +V4L2_CID_, and are listed in . The ID is used when querying the attributes of +a control, and when getting or setting the current value. + + Generally applications should present controls to the user +without assumptions about their purpose. Each control comes with a +name string the user is supposed to understand. When the purpose is +non-intuitive the driver writer should provide a user manual, a user +interface plug-in or a driver specific panel application. Predefined +IDs were introduced to change a few controls programmatically, for +example to mute a device during a channel switch. + + Drivers may enumerate different controls after switching +the current video input or output, tuner or modulator, or audio input +or output. Different in the sense of other bounds, another default and +current value, step size or other menu items. A control with a certain +custom ID can also change name and +type. + It will be more convenient for applications if drivers +make use of the V4L2_CTRL_FLAG_DISABLED flag, but +that was never required. + Control values are stored globally, they do not +change when switching except to stay within the reported bounds. They +also do not change ⪚ when the device is opened or closed, when the +tuner radio frequency is changed or generally never without +application request. Since V4L2 specifies no event mechanism, panel +applications intended to cooperate with other panel applications (be +they built into a larger application, as a TV viewer) may need to +regularly poll control values to update their user +interface. + Applications could call an ioctl to request events. +After another process called &VIDIOC-S-CTRL; or another ioctl changing +shared properties the &func-select; function would indicate +readability until any ioctl (querying the properties) is +called. + + + + Control IDs + + &cs-def; + + + ID + Type + Description + + + + + V4L2_CID_BASE + + First predefined ID, equal to +V4L2_CID_BRIGHTNESS. + + + V4L2_CID_USER_BASE + + Synonym of V4L2_CID_BASE. + + + V4L2_CID_BRIGHTNESS + integer + Picture brightness, or more precisely, the black +level. + + + V4L2_CID_CONTRAST + integer + Picture contrast or luma gain. + + + V4L2_CID_SATURATION + integer + Picture color saturation or chroma gain. + + + V4L2_CID_HUE + integer + Hue or color balance. + + + V4L2_CID_AUDIO_VOLUME + integer + Overall audio volume. Note some drivers also +provide an OSS or ALSA mixer interface. + + + V4L2_CID_AUDIO_BALANCE + integer + Audio stereo balance. Minimum corresponds to all +the way left, maximum to right. + + + V4L2_CID_AUDIO_BASS + integer + Audio bass adjustment. + + + V4L2_CID_AUDIO_TREBLE + integer + Audio treble adjustment. + + + V4L2_CID_AUDIO_MUTE + boolean + Mute audio, &ie; set the volume to zero, however +without affecting V4L2_CID_AUDIO_VOLUME. Like +ALSA drivers, V4L2 drivers must mute at load time to avoid excessive +noise. Actually the entire device should be reset to a low power +consumption state. + + + V4L2_CID_AUDIO_LOUDNESS + boolean + Loudness mode (bass boost). + + + V4L2_CID_BLACK_LEVEL + integer + Another name for brightness (not a synonym of +V4L2_CID_BRIGHTNESS). This control is deprecated +and should not be used in new drivers and applications. + + + V4L2_CID_AUTO_WHITE_BALANCE + boolean + Automatic white balance (cameras). + + + V4L2_CID_DO_WHITE_BALANCE + button + This is an action control. When set (the value is +ignored), the device will do a white balance and then hold the current +setting. Contrast this with the boolean +V4L2_CID_AUTO_WHITE_BALANCE, which, when +activated, keeps adjusting the white balance. + + + V4L2_CID_RED_BALANCE + integer + Red chroma balance. + + + V4L2_CID_BLUE_BALANCE + integer + Blue chroma balance. + + + V4L2_CID_GAMMA + integer + Gamma adjust. + + + V4L2_CID_WHITENESS + integer + Whiteness for grey-scale devices. This is a synonym +for V4L2_CID_GAMMA. This control is deprecated +and should not be used in new drivers and applications. + + + V4L2_CID_EXPOSURE + integer + Exposure (cameras). [Unit?] + + + V4L2_CID_AUTOGAIN + boolean + Automatic gain/exposure control. + + + V4L2_CID_GAIN + integer + Gain control. + + + V4L2_CID_HFLIP + boolean + Mirror the picture horizontally. + + + V4L2_CID_VFLIP + boolean + Mirror the picture vertically. + + + V4L2_CID_HCENTER_DEPRECATED (formerly V4L2_CID_HCENTER) + integer + Horizontal image centering. This control is +deprecated. New drivers and applications should use the Camera class controls +V4L2_CID_PAN_ABSOLUTE, +V4L2_CID_PAN_RELATIVE and +V4L2_CID_PAN_RESET instead. + + + V4L2_CID_VCENTER_DEPRECATED + (formerly V4L2_CID_VCENTER) + integer + Vertical image centering. Centering is intended to +physically adjust cameras. For image cropping see +, for clipping . This +control is deprecated. New drivers and applications should use the +Camera class controls +V4L2_CID_TILT_ABSOLUTE, +V4L2_CID_TILT_RELATIVE and +V4L2_CID_TILT_RESET instead. + + + V4L2_CID_POWER_LINE_FREQUENCY + enum + Enables a power line frequency filter to avoid +flicker. Possible values for enum v4l2_power_line_frequency are: +V4L2_CID_POWER_LINE_FREQUENCY_DISABLED (0), +V4L2_CID_POWER_LINE_FREQUENCY_50HZ (1) and +V4L2_CID_POWER_LINE_FREQUENCY_60HZ (2). + + + V4L2_CID_HUE_AUTO + boolean + Enables automatic hue control by the device. The +effect of setting V4L2_CID_HUE while automatic +hue control is enabled is undefined, drivers should ignore such +request. + + + V4L2_CID_WHITE_BALANCE_TEMPERATURE + integer + This control specifies the white balance settings +as a color temperature in Kelvin. A driver should have a minimum of +2800 (incandescent) to 6500 (daylight). For more information about +color temperature see Wikipedia. + + + V4L2_CID_SHARPNESS + integer + Adjusts the sharpness filters in a camera. The +minimum value disables the filters, higher values give a sharper +picture. + + + V4L2_CID_BACKLIGHT_COMPENSATION + integer + Adjusts the backlight compensation in a camera. The +minimum value disables backlight compensation. + + + V4L2_CID_CHROMA_AGC + boolean + Chroma automatic gain control. + + + V4L2_CID_COLOR_KILLER + boolean + Enable the color killer (&ie; force a black & white image in case of a weak video signal). + + + V4L2_CID_COLORFX + enum + Selects a color effect. Possible values for +enum v4l2_colorfx are: +V4L2_COLORFX_NONE (0), +V4L2_COLORFX_BW (1) and +V4L2_COLORFX_SEPIA (2). + + + V4L2_CID_LASTP1 + + End of the predefined control IDs (currently +V4L2_CID_COLORFX + 1). + + + V4L2_CID_PRIVATE_BASE + + ID of the first custom (driver specific) control. +Applications depending on particular custom controls should check the +driver name and version, see . + + + +
+ + Applications can enumerate the available controls with the +&VIDIOC-QUERYCTRL; and &VIDIOC-QUERYMENU; ioctls, get and set a +control value with the &VIDIOC-G-CTRL; and &VIDIOC-S-CTRL; ioctls. +Drivers must implement VIDIOC_QUERYCTRL, +VIDIOC_G_CTRL and +VIDIOC_S_CTRL when the device has one or more +controls, VIDIOC_QUERYMENU when it has one or +more menu type controls. + + + Enumerating all controls + + +&v4l2-queryctrl; queryctrl; +&v4l2-querymenu; querymenu; + +static void +enumerate_menu (void) +{ + printf (" Menu items:\n"); + + memset (&querymenu, 0, sizeof (querymenu)); + querymenu.id = queryctrl.id; + + for (querymenu.index = queryctrl.minimum; + querymenu.index <= queryctrl.maximum; + querymenu.index++) { + if (0 == ioctl (fd, &VIDIOC-QUERYMENU;, &querymenu)) { + printf (" %s\n", querymenu.name); + } else { + perror ("VIDIOC_QUERYMENU"); + exit (EXIT_FAILURE); + } + } +} + +memset (&queryctrl, 0, sizeof (queryctrl)); + +for (queryctrl.id = V4L2_CID_BASE; + queryctrl.id < V4L2_CID_LASTP1; + queryctrl.id++) { + if (0 == ioctl (fd, &VIDIOC-QUERYCTRL;, &queryctrl)) { + if (queryctrl.flags & V4L2_CTRL_FLAG_DISABLED) + continue; + + printf ("Control %s\n", queryctrl.name); + + if (queryctrl.type == V4L2_CTRL_TYPE_MENU) + enumerate_menu (); + } else { + if (errno == EINVAL) + continue; + + perror ("VIDIOC_QUERYCTRL"); + exit (EXIT_FAILURE); + } +} + +for (queryctrl.id = V4L2_CID_PRIVATE_BASE;; + queryctrl.id++) { + if (0 == ioctl (fd, &VIDIOC-QUERYCTRL;, &queryctrl)) { + if (queryctrl.flags & V4L2_CTRL_FLAG_DISABLED) + continue; + + printf ("Control %s\n", queryctrl.name); + + if (queryctrl.type == V4L2_CTRL_TYPE_MENU) + enumerate_menu (); + } else { + if (errno == EINVAL) + break; + + perror ("VIDIOC_QUERYCTRL"); + exit (EXIT_FAILURE); + } +} + + + + + Changing controls + + +&v4l2-queryctrl; queryctrl; +&v4l2-control; control; + +memset (&queryctrl, 0, sizeof (queryctrl)); +queryctrl.id = V4L2_CID_BRIGHTNESS; + +if (-1 == ioctl (fd, &VIDIOC-QUERYCTRL;, &queryctrl)) { + if (errno != EINVAL) { + perror ("VIDIOC_QUERYCTRL"); + exit (EXIT_FAILURE); + } else { + printf ("V4L2_CID_BRIGHTNESS is not supported\n"); + } +} else if (queryctrl.flags & V4L2_CTRL_FLAG_DISABLED) { + printf ("V4L2_CID_BRIGHTNESS is not supported\n"); +} else { + memset (&control, 0, sizeof (control)); + control.id = V4L2_CID_BRIGHTNESS; + control.value = queryctrl.default_value; + + if (-1 == ioctl (fd, &VIDIOC-S-CTRL;, &control)) { + perror ("VIDIOC_S_CTRL"); + exit (EXIT_FAILURE); + } +} + +memset (&control, 0, sizeof (control)); +control.id = V4L2_CID_CONTRAST; + +if (0 == ioctl (fd, &VIDIOC-G-CTRL;, &control)) { + control.value += 1; + + /* The driver may clamp the value or return ERANGE, ignored here */ + + if (-1 == ioctl (fd, &VIDIOC-S-CTRL;, &control) + && errno != ERANGE) { + perror ("VIDIOC_S_CTRL"); + exit (EXIT_FAILURE); + } +/* Ignore if V4L2_CID_CONTRAST is unsupported */ +} else if (errno != EINVAL) { + perror ("VIDIOC_G_CTRL"); + exit (EXIT_FAILURE); +} + +control.id = V4L2_CID_AUDIO_MUTE; +control.value = TRUE; /* silence */ + +/* Errors ignored */ +ioctl (fd, VIDIOC_S_CTRL, &control); + + +
+ +
+ Extended Controls + +
+ Introduction + + The control mechanism as originally designed was meant +to be used for user settings (brightness, saturation, etc). However, +it turned out to be a very useful model for implementing more +complicated driver APIs where each driver implements only a subset of +a larger API. + + The MPEG encoding API was the driving force behind +designing and implementing this extended control mechanism: the MPEG +standard is quite large and the currently supported hardware MPEG +encoders each only implement a subset of this standard. Further more, +many parameters relating to how the video is encoded into an MPEG +stream are specific to the MPEG encoding chip since the MPEG standard +only defines the format of the resulting MPEG stream, not how the +video is actually encoded into that format. + + Unfortunately, the original control API lacked some +features needed for these new uses and so it was extended into the +(not terribly originally named) extended control API. + + Even though the MPEG encoding API was the first effort +to use the Extended Control API, nowadays there are also other classes +of Extended Controls, such as Camera Controls and FM Transmitter Controls. +The Extended Controls API as well as all Extended Controls classes are +described in the following text. +
+ +
+ The Extended Control API + + Three new ioctls are available: &VIDIOC-G-EXT-CTRLS;, +&VIDIOC-S-EXT-CTRLS; and &VIDIOC-TRY-EXT-CTRLS;. These ioctls act on +arrays of controls (as opposed to the &VIDIOC-G-CTRL; and +&VIDIOC-S-CTRL; ioctls that act on a single control). This is needed +since it is often required to atomically change several controls at +once. + + Each of the new ioctls expects a pointer to a +&v4l2-ext-controls;. This structure contains a pointer to the control +array, a count of the number of controls in that array and a control +class. Control classes are used to group similar controls into a +single class. For example, control class +V4L2_CTRL_CLASS_USER contains all user controls +(&ie; all controls that can also be set using the old +VIDIOC_S_CTRL ioctl). Control class +V4L2_CTRL_CLASS_MPEG contains all controls +relating to MPEG encoding, etc. + + All controls in the control array must belong to the +specified control class. An error is returned if this is not the +case. + + It is also possible to use an empty control array (count +== 0) to check whether the specified control class is +supported. + + The control array is a &v4l2-ext-control; array. The +v4l2_ext_control structure is very similar to +&v4l2-control;, except for the fact that it also allows for 64-bit +values and pointers to be passed. + + It is important to realize that due to the flexibility of +controls it is necessary to check whether the control you want to set +actually is supported in the driver and what the valid range of values +is. So use the &VIDIOC-QUERYCTRL; and &VIDIOC-QUERYMENU; ioctls to +check this. Also note that it is possible that some of the menu +indices in a control of type V4L2_CTRL_TYPE_MENU +may not be supported (VIDIOC_QUERYMENU will +return an error). A good example is the list of supported MPEG audio +bitrates. Some drivers only support one or two bitrates, others +support a wider range. +
+ +
+ Enumerating Extended Controls + + The recommended way to enumerate over the extended +controls is by using &VIDIOC-QUERYCTRL; in combination with the +V4L2_CTRL_FLAG_NEXT_CTRL flag: + + + +&v4l2-queryctrl; qctrl; + +qctrl.id = V4L2_CTRL_FLAG_NEXT_CTRL; +while (0 == ioctl (fd, &VIDIOC-QUERYCTRL;, &qctrl)) { + /* ... */ + qctrl.id |= V4L2_CTRL_FLAG_NEXT_CTRL; +} + + + + The initial control ID is set to 0 ORed with the +V4L2_CTRL_FLAG_NEXT_CTRL flag. The +VIDIOC_QUERYCTRL ioctl will return the first +control with a higher ID than the specified one. When no such controls +are found an error is returned. + + If you want to get all controls within a specific control +class, then you can set the initial +qctrl.id value to the control class and add +an extra check to break out of the loop when a control of another +control class is found: + + + +qctrl.id = V4L2_CTRL_CLASS_MPEG | V4L2_CTRL_FLAG_NEXT_CTRL; +while (0 == ioctl (fd, &VIDIOC-QUERYCTRL;, &qctrl)) { + if (V4L2_CTRL_ID2CLASS (qctrl.id) != V4L2_CTRL_CLASS_MPEG) + break; + /* ... */ + qctrl.id |= V4L2_CTRL_FLAG_NEXT_CTRL; + } + + + + The 32-bit qctrl.id value is +subdivided into three bit ranges: the top 4 bits are reserved for +flags (⪚ V4L2_CTRL_FLAG_NEXT_CTRL) and are not +actually part of the ID. The remaining 28 bits form the control ID, of +which the most significant 12 bits define the control class and the +least significant 16 bits identify the control within the control +class. It is guaranteed that these last 16 bits are always non-zero +for controls. The range of 0x1000 and up are reserved for +driver-specific controls. The macro +V4L2_CTRL_ID2CLASS(id) returns the control class +ID based on a control ID. + + If the driver does not support extended controls, then +VIDIOC_QUERYCTRL will fail when used in +combination with V4L2_CTRL_FLAG_NEXT_CTRL. In +that case the old method of enumerating control should be used (see +1.8). But if it is supported, then it is guaranteed to enumerate over +all controls, including driver-private controls. +
+ +
+ Creating Control Panels + + It is possible to create control panels for a graphical +user interface where the user can select the various controls. +Basically you will have to iterate over all controls using the method +described above. Each control class starts with a control of type +V4L2_CTRL_TYPE_CTRL_CLASS. +VIDIOC_QUERYCTRL will return the name of this +control class which can be used as the title of a tab page within a +control panel. + + The flags field of &v4l2-queryctrl; also contains hints on +the behavior of the control. See the &VIDIOC-QUERYCTRL; documentation +for more details. +
+ +
+ MPEG Control Reference + + Below all controls within the MPEG control class are +described. First the generic controls, then controls specific for +certain hardware. + +
+ Generic MPEG Controls + + + MPEG Control IDs + + + + + + + + + + ID + Type + Description + + + + + + V4L2_CID_MPEG_CLASS  + class + The MPEG class +descriptor. Calling &VIDIOC-QUERYCTRL; for this control will return a +description of this control class. This description can be used as the +caption of a Tab page in a GUI, for example. + + + + V4L2_CID_MPEG_STREAM_TYPE  + enum v4l2_mpeg_stream_type + The MPEG-1, -2 or -4 +output stream type. One cannot assume anything here. Each hardware +MPEG encoder tends to support different subsets of the available MPEG +stream types. The currently defined stream types are: + + + + + + V4L2_MPEG_STREAM_TYPE_MPEG2_PS  + MPEG-2 program stream + + + V4L2_MPEG_STREAM_TYPE_MPEG2_TS  + MPEG-2 transport stream + + + V4L2_MPEG_STREAM_TYPE_MPEG1_SS  + MPEG-1 system stream + + + V4L2_MPEG_STREAM_TYPE_MPEG2_DVD  + MPEG-2 DVD-compatible stream + + + V4L2_MPEG_STREAM_TYPE_MPEG1_VCD  + MPEG-1 VCD-compatible stream + + + V4L2_MPEG_STREAM_TYPE_MPEG2_SVCD  + MPEG-2 SVCD-compatible stream + + + + + + + V4L2_CID_MPEG_STREAM_PID_PMT  + integer + Program Map Table +Packet ID for the MPEG transport stream (default 16) + + + + V4L2_CID_MPEG_STREAM_PID_AUDIO  + integer + Audio Packet ID for +the MPEG transport stream (default 256) + + + + V4L2_CID_MPEG_STREAM_PID_VIDEO  + integer + Video Packet ID for +the MPEG transport stream (default 260) + + + + V4L2_CID_MPEG_STREAM_PID_PCR  + integer + Packet ID for the +MPEG transport stream carrying PCR fields (default 259) + + + + V4L2_CID_MPEG_STREAM_PES_ID_AUDIO  + integer + Audio ID for MPEG +PES + + + + V4L2_CID_MPEG_STREAM_PES_ID_VIDEO  + integer + Video ID for MPEG +PES + + + + V4L2_CID_MPEG_STREAM_VBI_FMT  + enum v4l2_mpeg_stream_vbi_fmt + Some cards can embed +VBI data (⪚ Closed Caption, Teletext) into the MPEG stream. This +control selects whether VBI data should be embedded, and if so, what +embedding method should be used. The list of possible VBI formats +depends on the driver. The currently defined VBI format types +are: + + + + + + V4L2_MPEG_STREAM_VBI_FMT_NONE  + No VBI in the MPEG stream + + + V4L2_MPEG_STREAM_VBI_FMT_IVTV  + VBI in private packets, IVTV format (documented +in the kernel sources in the file Documentation/video4linux/cx2341x/README.vbi) + + + + + + + V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ  + enum v4l2_mpeg_audio_sampling_freq + MPEG Audio sampling +frequency. Possible values are: + + + + + + V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100  + 44.1 kHz + + + V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000  + 48 kHz + + + V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000  + 32 kHz + + + + + + + V4L2_CID_MPEG_AUDIO_ENCODING  + enum v4l2_mpeg_audio_encoding + MPEG Audio encoding. +Possible values are: + + + + + + V4L2_MPEG_AUDIO_ENCODING_LAYER_1  + MPEG-1/2 Layer I encoding + + + V4L2_MPEG_AUDIO_ENCODING_LAYER_2  + MPEG-1/2 Layer II encoding + + + V4L2_MPEG_AUDIO_ENCODING_LAYER_3  + MPEG-1/2 Layer III encoding + + + V4L2_MPEG_AUDIO_ENCODING_AAC  + MPEG-2/4 AAC (Advanced Audio Coding) + + + V4L2_MPEG_AUDIO_ENCODING_AC3  + AC-3 aka ATSC A/52 encoding + + + + + + + V4L2_CID_MPEG_AUDIO_L1_BITRATE  + enum v4l2_mpeg_audio_l1_bitrate + MPEG-1/2 Layer I bitrate. +Possible values are: + + + + + + V4L2_MPEG_AUDIO_L1_BITRATE_32K  + 32 kbit/s + + V4L2_MPEG_AUDIO_L1_BITRATE_64K  + 64 kbit/s + + + V4L2_MPEG_AUDIO_L1_BITRATE_96K  + 96 kbit/s + + + V4L2_MPEG_AUDIO_L1_BITRATE_128K  + 128 kbit/s + + + V4L2_MPEG_AUDIO_L1_BITRATE_160K  + 160 kbit/s + + + V4L2_MPEG_AUDIO_L1_BITRATE_192K  + 192 kbit/s + + + V4L2_MPEG_AUDIO_L1_BITRATE_224K  + 224 kbit/s + + + V4L2_MPEG_AUDIO_L1_BITRATE_256K  + 256 kbit/s + + + V4L2_MPEG_AUDIO_L1_BITRATE_288K  + 288 kbit/s + + + V4L2_MPEG_AUDIO_L1_BITRATE_320K  + 320 kbit/s + + + V4L2_MPEG_AUDIO_L1_BITRATE_352K  + 352 kbit/s + + + V4L2_MPEG_AUDIO_L1_BITRATE_384K  + 384 kbit/s + + + V4L2_MPEG_AUDIO_L1_BITRATE_416K  + 416 kbit/s + + + V4L2_MPEG_AUDIO_L1_BITRATE_448K  + 448 kbit/s + + + + + + + V4L2_CID_MPEG_AUDIO_L2_BITRATE  + enum v4l2_mpeg_audio_l2_bitrate + MPEG-1/2 Layer II bitrate. +Possible values are: + + + + + + V4L2_MPEG_AUDIO_L2_BITRATE_32K  + 32 kbit/s + + + V4L2_MPEG_AUDIO_L2_BITRATE_48K  + 48 kbit/s + + + V4L2_MPEG_AUDIO_L2_BITRATE_56K  + 56 kbit/s + + + V4L2_MPEG_AUDIO_L2_BITRATE_64K  + 64 kbit/s + + + V4L2_MPEG_AUDIO_L2_BITRATE_80K  + 80 kbit/s + + + V4L2_MPEG_AUDIO_L2_BITRATE_96K  + 96 kbit/s + + + V4L2_MPEG_AUDIO_L2_BITRATE_112K  + 112 kbit/s + + + V4L2_MPEG_AUDIO_L2_BITRATE_128K  + 128 kbit/s + + + V4L2_MPEG_AUDIO_L2_BITRATE_160K  + 160 kbit/s + + + V4L2_MPEG_AUDIO_L2_BITRATE_192K  + 192 kbit/s + + + V4L2_MPEG_AUDIO_L2_BITRATE_224K  + 224 kbit/s + + + V4L2_MPEG_AUDIO_L2_BITRATE_256K  + 256 kbit/s + + + V4L2_MPEG_AUDIO_L2_BITRATE_320K  + 320 kbit/s + + + V4L2_MPEG_AUDIO_L2_BITRATE_384K  + 384 kbit/s + + + + + + + V4L2_CID_MPEG_AUDIO_L3_BITRATE  + enum v4l2_mpeg_audio_l3_bitrate + MPEG-1/2 Layer III bitrate. +Possible values are: + + + + + + V4L2_MPEG_AUDIO_L3_BITRATE_32K  + 32 kbit/s + + + V4L2_MPEG_AUDIO_L3_BITRATE_40K  + 40 kbit/s + + + V4L2_MPEG_AUDIO_L3_BITRATE_48K  + 48 kbit/s + + + V4L2_MPEG_AUDIO_L3_BITRATE_56K  + 56 kbit/s + + + V4L2_MPEG_AUDIO_L3_BITRATE_64K  + 64 kbit/s + + + V4L2_MPEG_AUDIO_L3_BITRATE_80K  + 80 kbit/s + + + V4L2_MPEG_AUDIO_L3_BITRATE_96K  + 96 kbit/s + + + V4L2_MPEG_AUDIO_L3_BITRATE_112K  + 112 kbit/s + + + V4L2_MPEG_AUDIO_L3_BITRATE_128K  + 128 kbit/s + + + V4L2_MPEG_AUDIO_L3_BITRATE_160K  + 160 kbit/s + + + V4L2_MPEG_AUDIO_L3_BITRATE_192K  + 192 kbit/s + + + V4L2_MPEG_AUDIO_L3_BITRATE_224K  + 224 kbit/s + + + V4L2_MPEG_AUDIO_L3_BITRATE_256K  + 256 kbit/s + + + V4L2_MPEG_AUDIO_L3_BITRATE_320K  + 320 kbit/s + + + + + + + V4L2_CID_MPEG_AUDIO_AAC_BITRATE  + integer + AAC bitrate in bits per second. + + + + V4L2_CID_MPEG_AUDIO_AC3_BITRATE  + enum v4l2_mpeg_audio_ac3_bitrate + AC-3 bitrate. +Possible values are: + + + + + + V4L2_MPEG_AUDIO_AC3_BITRATE_32K  + 32 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_40K  + 40 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_48K  + 48 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_56K  + 56 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_64K  + 64 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_80K  + 80 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_96K  + 96 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_112K  + 112 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_128K  + 128 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_160K  + 160 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_192K  + 192 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_224K  + 224 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_256K  + 256 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_320K  + 320 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_384K  + 384 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_448K  + 448 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_512K  + 512 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_576K  + 576 kbit/s + + + V4L2_MPEG_AUDIO_AC3_BITRATE_640K  + 640 kbit/s + + + + + + + V4L2_CID_MPEG_AUDIO_MODE  + enum v4l2_mpeg_audio_mode + MPEG Audio mode. +Possible values are: + + + + + + V4L2_MPEG_AUDIO_MODE_STEREO  + Stereo + + + V4L2_MPEG_AUDIO_MODE_JOINT_STEREO  + Joint Stereo + + + V4L2_MPEG_AUDIO_MODE_DUAL  + Bilingual + + + V4L2_MPEG_AUDIO_MODE_MONO  + Mono + + + + + + + V4L2_CID_MPEG_AUDIO_MODE_EXTENSION  + enum v4l2_mpeg_audio_mode_extension + Joint Stereo +audio mode extension. In Layer I and II they indicate which subbands +are in intensity stereo. All other subbands are coded in stereo. Layer +III is not (yet) supported. Possible values +are: + + + + + + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_4  + Subbands 4-31 in intensity stereo + + + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_8  + Subbands 8-31 in intensity stereo + + + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_12  + Subbands 12-31 in intensity stereo + + + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_16  + Subbands 16-31 in intensity stereo + + + + + + + V4L2_CID_MPEG_AUDIO_EMPHASIS  + enum v4l2_mpeg_audio_emphasis + Audio Emphasis. +Possible values are: + + + + + + V4L2_MPEG_AUDIO_EMPHASIS_NONE  + None + + + V4L2_MPEG_AUDIO_EMPHASIS_50_DIV_15_uS  + 50/15 microsecond emphasis + + + V4L2_MPEG_AUDIO_EMPHASIS_CCITT_J17  + CCITT J.17 + + + + + + + V4L2_CID_MPEG_AUDIO_CRC  + enum v4l2_mpeg_audio_crc + CRC method. Possible +values are: + + + + + + V4L2_MPEG_AUDIO_CRC_NONE  + None + + + V4L2_MPEG_AUDIO_CRC_CRC16  + 16 bit parity check + + + + + + + V4L2_CID_MPEG_AUDIO_MUTE  + boolean + Mutes the audio when +capturing. This is not done by muting audio hardware, which can still +produce a slight hiss, but in the encoder itself, guaranteeing a fixed +and reproducable audio bitstream. 0 = unmuted, 1 = muted. + + + + V4L2_CID_MPEG_VIDEO_ENCODING  + enum v4l2_mpeg_video_encoding + MPEG Video encoding +method. Possible values are: + + + + + + V4L2_MPEG_VIDEO_ENCODING_MPEG_1  + MPEG-1 Video encoding + + + V4L2_MPEG_VIDEO_ENCODING_MPEG_2  + MPEG-2 Video encoding + + + V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC  + MPEG-4 AVC (H.264) Video encoding + + + + + + + V4L2_CID_MPEG_VIDEO_ASPECT  + enum v4l2_mpeg_video_aspect + Video aspect. +Possible values are: + + + + + + V4L2_MPEG_VIDEO_ASPECT_1x1  + + + V4L2_MPEG_VIDEO_ASPECT_4x3  + + + V4L2_MPEG_VIDEO_ASPECT_16x9  + + + V4L2_MPEG_VIDEO_ASPECT_221x100  + + + + + + + V4L2_CID_MPEG_VIDEO_B_FRAMES  + integer + Number of B-Frames +(default 2) + + + + V4L2_CID_MPEG_VIDEO_GOP_SIZE  + integer + GOP size (default +12) + + + + V4L2_CID_MPEG_VIDEO_GOP_CLOSURE  + boolean + GOP closure (default +1) + + + + V4L2_CID_MPEG_VIDEO_PULLDOWN  + boolean + Enable 3:2 pulldown +(default 0) + + + + V4L2_CID_MPEG_VIDEO_BITRATE_MODE  + enum v4l2_mpeg_video_bitrate_mode + Video bitrate mode. +Possible values are: + + + + + + V4L2_MPEG_VIDEO_BITRATE_MODE_VBR  + Variable bitrate + + + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR  + Constant bitrate + + + + + + + V4L2_CID_MPEG_VIDEO_BITRATE  + integer + Video bitrate in bits +per second. + + + + V4L2_CID_MPEG_VIDEO_BITRATE_PEAK  + integer + Peak video bitrate in +bits per second. Must be larger or equal to the average video bitrate. +It is ignored if the video bitrate mode is set to constant +bitrate. + + + + V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION  + integer + For every captured +frame, skip this many subsequent frames (default 0). + + + + V4L2_CID_MPEG_VIDEO_MUTE  + boolean + + "Mutes" the video to a +fixed color when capturing. This is useful for testing, to produce a +fixed video bitstream. 0 = unmuted, 1 = muted. + + + + V4L2_CID_MPEG_VIDEO_MUTE_YUV  + integer + Sets the "mute" color +of the video. The supplied 32-bit integer is interpreted as follows (bit +0 = least significant bit): + + + + + + Bit 0:7 + V chrominance information + + + Bit 8:15 + U chrominance information + + + Bit 16:23 + Y luminance information + + + Bit 24:31 + Must be zero. + + + + + + +
+
+ +
+ CX2341x MPEG Controls + + The following MPEG class controls deal with MPEG +encoding settings that are specific to the Conexant CX23415 and +CX23416 MPEG encoding chips. + + + CX2341x Control IDs + + + + + + + + + + ID + Type + Description + + + + + + V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE  + enum v4l2_mpeg_cx2341x_video_spatial_filter_mode + Sets the Spatial +Filter mode (default MANUAL). Possible values +are: + + + + + + V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_MANUAL  + Choose the filter manually + + + V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_AUTO  + Choose the filter automatically + + + + + + + V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER  + integer (0-15) + The setting for the +Spatial Filter. 0 = off, 15 = maximum. (Default is 0.) + + + + V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE  + enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type + Select the algorithm +to use for the Luma Spatial Filter (default +1D_HOR). Possible values: + + + + + + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_OFF  + No filter + + + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_HOR  + One-dimensional horizontal + + + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_VERT  + One-dimensional vertical + + + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_HV_SEPARABLE  + Two-dimensional separable + + + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_SYM_NON_SEPARABLE  + Two-dimensional symmetrical +non-separable + + + + + + + V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE  + enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type + Select the algorithm +for the Chroma Spatial Filter (default 1D_HOR). +Possible values are: + + + + + + V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_OFF  + No filter + + + V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_1D_HOR  + One-dimensional horizontal + + + + + + + V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE  + enum v4l2_mpeg_cx2341x_video_temporal_filter_mode + Sets the Temporal +Filter mode (default MANUAL). Possible values +are: + + + + + + V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_MANUAL  + Choose the filter manually + + + V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_AUTO  + Choose the filter automatically + + + + + + + V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER  + integer (0-31) + The setting for the +Temporal Filter. 0 = off, 31 = maximum. (Default is 8 for full-scale +capturing and 0 for scaled capturing.) + + + + V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE  + enum v4l2_mpeg_cx2341x_video_median_filter_type + Median Filter Type +(default OFF). Possible values are: + + + + + + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_OFF  + No filter + + + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR  + Horizontal filter + + + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_VERT  + Vertical filter + + + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR_VERT  + Horizontal and vertical filter + + + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_DIAG  + Diagonal filter + + + + + + + V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM  + integer (0-255) + Threshold above which +the luminance median filter is enabled (default 0) + + + + V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP  + integer (0-255) + Threshold below which +the luminance median filter is enabled (default 255) + + + + V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM  + integer (0-255) + Threshold above which +the chroma median filter is enabled (default 0) + + + + V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP  + integer (0-255) + Threshold below which +the chroma median filter is enabled (default 255) + + + + V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS  + boolean + + The CX2341X MPEG encoder +can insert one empty MPEG-2 PES packet into the stream between every +four video frames. The packet size is 2048 bytes, including the +packet_start_code_prefix and stream_id fields. The stream_id is 0xBF +(private stream 2). The payload consists of 0x00 bytes, to be filled +in by the application. 0 = do not insert, 1 = insert packets. + + + +
+
+
+ +
+ Camera Control Reference + + The Camera class includes controls for mechanical (or +equivalent digital) features of a device such as controllable lenses +or sensors. + + + Camera Control IDs + + + + + + + + + + ID + Type + Description + + + + + + V4L2_CID_CAMERA_CLASS  + class + The Camera class +descriptor. Calling &VIDIOC-QUERYCTRL; for this control will return a +description of this control class. + + + + + V4L2_CID_EXPOSURE_AUTO  + enum v4l2_exposure_auto_type + Enables automatic +adjustments of the exposure time and/or iris aperture. The effect of +manual changes of the exposure time or iris aperture while these +features are enabled is undefined, drivers should ignore such +requests. Possible values are: + + + + + + V4L2_EXPOSURE_AUTO  + Automatic exposure time, automatic iris +aperture. + + + V4L2_EXPOSURE_MANUAL  + Manual exposure time, manual iris. + + + V4L2_EXPOSURE_SHUTTER_PRIORITY  + Manual exposure time, auto iris. + + + V4L2_EXPOSURE_APERTURE_PRIORITY  + Auto exposure time, manual iris. + + + + + + + + V4L2_CID_EXPOSURE_ABSOLUTE  + integer + Determines the exposure +time of the camera sensor. The exposure time is limited by the frame +interval. Drivers should interpret the values as 100 µs units, +where the value 1 stands for 1/10000th of a second, 10000 for 1 second +and 100000 for 10 seconds. + + + + + V4L2_CID_EXPOSURE_AUTO_PRIORITY  + boolean + When +V4L2_CID_EXPOSURE_AUTO is set to +AUTO or APERTURE_PRIORITY, +this control determines if the device may dynamically vary the frame +rate. By default this feature is disabled (0) and the frame rate must +remain constant. + + + + + V4L2_CID_PAN_RELATIVE  + integer + This control turns the +camera horizontally by the specified amount. The unit is undefined. A +positive value moves the camera to the right (clockwise when viewed +from above), a negative value to the left. A value of zero does not +cause motion. This is a write-only control. + + + + + V4L2_CID_TILT_RELATIVE  + integer + This control turns the +camera vertically by the specified amount. The unit is undefined. A +positive value moves the camera up, a negative value down. A value of +zero does not cause motion. This is a write-only control. + + + + + V4L2_CID_PAN_RESET  + button + When this control is set, +the camera moves horizontally to the default position. + + + + + V4L2_CID_TILT_RESET  + button + When this control is set, +the camera moves vertically to the default position. + + + + + V4L2_CID_PAN_ABSOLUTE  + integer + This control +turns the camera horizontally to the specified position. Positive +values move the camera to the right (clockwise when viewed from above), +negative values to the left. Drivers should interpret the values as arc +seconds, with valid values between -180 * 3600 and +180 * 3600 +inclusive. + + + + + V4L2_CID_TILT_ABSOLUTE  + integer + This control +turns the camera vertically to the specified position. Positive values +move the camera up, negative values down. Drivers should interpret the +values as arc seconds, with valid values between -180 * 3600 and +180 +* 3600 inclusive. + + + + + V4L2_CID_FOCUS_ABSOLUTE  + integer + This control sets the +focal point of the camera to the specified position. The unit is +undefined. Positive values set the focus closer to the camera, +negative values towards infinity. + + + + + V4L2_CID_FOCUS_RELATIVE  + integer + This control moves the +focal point of the camera by the specified amount. The unit is +undefined. Positive values move the focus closer to the camera, +negative values towards infinity. This is a write-only control. + + + + + V4L2_CID_FOCUS_AUTO  + boolean + Enables automatic focus +adjustments. The effect of manual focus adjustments while this feature +is enabled is undefined, drivers should ignore such requests. + + + + + V4L2_CID_ZOOM_ABSOLUTE  + integer + Specify the objective lens +focal length as an absolute value. The zoom unit is driver-specific and its +value should be a positive integer. + + + + + V4L2_CID_ZOOM_RELATIVE  + integer + Specify the objective lens +focal length relatively to the current value. Positive values move the zoom +lens group towards the telephoto direction, negative values towards the +wide-angle direction. The zoom unit is driver-specific. This is a write-only control. + + + + + V4L2_CID_ZOOM_CONTINUOUS  + integer + Move the objective lens group +at the specified speed until it reaches physical device limits or until an +explicit request to stop the movement. A positive value moves the zoom lens +group towards the telephoto direction. A value of zero stops the zoom lens +group movement. A negative value moves the zoom lens group towards the +wide-angle direction. The zoom speed unit is driver-specific. + + + + + V4L2_CID_PRIVACY  + boolean + Prevent video from being acquired +by the camera. When this control is set to TRUE (1), no +image can be captured by the camera. Common means to enforce privacy are +mechanical obturation of the sensor and firmware image processing, but the +device is not restricted to these methods. Devices that implement the privacy +control must support read access and may support write access. + + + + V4L2_CID_BAND_STOP_FILTER  + integer + Switch the band-stop filter of a +camera sensor on or off, or specify its strength. Such band-stop filters can +be used, for example, to filter out the fluorescent light component. + + + + +
+
+ +
+ FM Transmitter Control Reference + + The FM Transmitter (FM_TX) class includes controls for common features of +FM transmissions capable devices. Currently this class includes parameters for audio +compression, pilot tone generation, audio deviation limiter, RDS transmission and +tuning power features. + + + FM_TX Control IDs + + + + + + + + + + + ID + Type + Description + + + + + + V4L2_CID_FM_TX_CLASS  + class + The FM_TX class +descriptor. Calling &VIDIOC-QUERYCTRL; for this control will return a +description of this control class. + + + V4L2_CID_RDS_TX_DEVIATION  + integer + + Configures RDS signal frequency deviation level in Hz. +The range and step are driver-specific. + + + V4L2_CID_RDS_TX_PI  + integer + + Sets the RDS Programme Identification field +for transmission. + + + V4L2_CID_RDS_TX_PTY  + integer + + Sets the RDS Programme Type field for transmission. +This encodes up to 31 pre-defined programme types. + + + V4L2_CID_RDS_TX_PS_NAME  + string + + Sets the Programme Service name (PS_NAME) for transmission. +It is intended for static display on a receiver. It is the primary aid to listeners in programme service +identification and selection. In Annex E of , the RDS specification, +there is a full description of the correct character encoding for Programme Service name strings. +Also from RDS specification, PS is usually a single eight character text. However, it is also possible +to find receivers which can scroll strings sized as 8 x N characters. So, this control must be configured +with steps of 8 characters. The result is it must always contain a string with size multiple of 8. + + + V4L2_CID_RDS_TX_RADIO_TEXT  + string + + Sets the Radio Text info for transmission. It is a textual description of +what is being broadcasted. RDS Radio Text can be applied when broadcaster wishes to transmit longer PS names, +programme-related information or any other text. In these cases, RadioText should be used in addition to +V4L2_CID_RDS_TX_PS_NAME. The encoding for Radio Text strings is also fully described +in Annex E of . The length of Radio Text strings depends on which RDS Block is being +used to transmit it, either 32 (2A block) or 64 (2B block). However, it is also possible +to find receivers which can scroll strings sized as 32 x N or 64 x N characters. So, this control must be configured +with steps of 32 or 64 characters. The result is it must always contain a string with size multiple of 32 or 64. + + + V4L2_CID_AUDIO_LIMITER_ENABLED  + boolean + + Enables or disables the audio deviation limiter feature. +The limiter is useful when trying to maximize the audio volume, minimize receiver-generated +distortion and prevent overmodulation. + + + + V4L2_CID_AUDIO_LIMITER_RELEASE_TIME  + integer + + Sets the audio deviation limiter feature release time. +Unit is in useconds. Step and range are driver-specific. + + + V4L2_CID_AUDIO_LIMITER_DEVIATION  + integer + + Configures audio frequency deviation level in Hz. +The range and step are driver-specific. + + + V4L2_CID_AUDIO_COMPRESSION_ENABLED  + boolean + + Enables or disables the audio compression feature. +This feature amplifies signals below the threshold by a fixed gain and compresses audio +signals above the threshold by the ratio of Threshold/(Gain + Threshold). + + + V4L2_CID_AUDIO_COMPRESSION_GAIN  + integer + + Sets the gain for audio compression feature. It is +a dB value. The range and step are driver-specific. + + + V4L2_CID_AUDIO_COMPRESSION_THRESHOLD  + integer + + Sets the threshold level for audio compression freature. +It is a dB value. The range and step are driver-specific. + + + V4L2_CID_AUDIO_COMPRESSION_ATTACK_TIME  + integer + + Sets the attack time for audio compression feature. +It is a useconds value. The range and step are driver-specific. + + + V4L2_CID_AUDIO_COMPRESSION_RELEASE_TIME  + integer + + Sets the release time for audio compression feature. +It is a useconds value. The range and step are driver-specific. + + + V4L2_CID_PILOT_TONE_ENABLED  + boolean + + Enables or disables the pilot tone generation feature. + + + V4L2_CID_PILOT_TONE_DEVIATION  + integer + + Configures pilot tone frequency deviation level. Unit is +in Hz. The range and step are driver-specific. + + + V4L2_CID_PILOT_TONE_FREQUENCY  + integer + + Configures pilot tone frequency value. Unit is +in Hz. The range and step are driver-specific. + + + V4L2_CID_TUNE_PREEMPHASIS  + integer + + Configures the pre-emphasis value for broadcasting. +A pre-emphasis filter is applied to the broadcast to accentuate the high audio frequencies. +Depending on the region, a time constant of either 50 or 75 useconds is used. The enum v4l2_preemphasis +defines possible values for pre-emphasis. Here they are: + + + + + V4L2_PREEMPHASIS_DISABLED  + No pre-emphasis is applied. + + + V4L2_PREEMPHASIS_50_uS  + A pre-emphasis of 50 uS is used. + + + V4L2_PREEMPHASIS_75_uS  + A pre-emphasis of 75 uS is used. + + + + + + + V4L2_CID_TUNE_POWER_LEVEL  + integer + + Sets the output power level for signal transmission. +Unit is in dBuV. Range and step are driver-specific. + + + V4L2_CID_TUNE_ANTENNA_CAPACITOR  + integer + + This selects the value of antenna tuning capacitor +manually or automatically if set to zero. Unit, range and step are driver-specific. + + + + +
+ +For more details about RDS specification, refer to + document, from CENELEC. +
+
+ + diff --git a/Documentation/DocBook/v4l/crop.gif b/Documentation/DocBook/v4l/crop.gif new file mode 100644 index 000000000000..3b9e7d836d4b Binary files /dev/null and b/Documentation/DocBook/v4l/crop.gif differ diff --git a/Documentation/DocBook/v4l/crop.pdf b/Documentation/DocBook/v4l/crop.pdf new file mode 100644 index 000000000000..c9fb81cd32f3 Binary files /dev/null and b/Documentation/DocBook/v4l/crop.pdf differ diff --git a/Documentation/DocBook/v4l/dev-capture.xml b/Documentation/DocBook/v4l/dev-capture.xml new file mode 100644 index 000000000000..32807e43f170 --- /dev/null +++ b/Documentation/DocBook/v4l/dev-capture.xml @@ -0,0 +1,115 @@ + Video Capture Interface + + Video capture devices sample an analog video signal and store +the digitized images in memory. Today nearly all devices can capture +at full 25 or 30 frames/second. With this interface applications can +control the capture process and move images from the driver into user +space. + + Conventionally V4L2 video capture devices are accessed through +character device special files named /dev/video +and /dev/video0 to +/dev/video63 with major number 81 and minor +numbers 0 to 63. /dev/video is typically a +symbolic link to the preferred video device. Note the same device +files are used for video output devices. + +
+ Querying Capabilities + + Devices supporting the video capture interface set the +V4L2_CAP_VIDEO_CAPTURE flag in the +capabilities field of &v4l2-capability; +returned by the &VIDIOC-QUERYCAP; ioctl. As secondary device functions +they may also support the video overlay +(V4L2_CAP_VIDEO_OVERLAY) and the raw VBI capture +(V4L2_CAP_VBI_CAPTURE) interface. At least one of +the read/write or streaming I/O methods must be supported. Tuners and +audio inputs are optional. +
+ +
+ Supplemental Functions + + Video capture devices shall support audio input, tuner, controls, +cropping and scaling and streaming parameter ioctls as needed. +The video input and video standard ioctls must be supported by +all video capture devices. +
+ +
+ Image Format Negotiation + + The result of a capture operation is determined by +cropping and image format parameters. The former select an area of the +video picture to capture, the latter how images are stored in memory, +&ie; in RGB or YUV format, the number of bits per pixel or width and +height. Together they also define how images are scaled in the +process. + + As usual these parameters are not reset +at &func-open; time to permit Unix tool chains, programming a device +and then reading from it as if it was a plain file. Well written V4L2 +applications ensure they really get what they want, including cropping +and scaling. + + Cropping initialization at minimum requires to reset the +parameters to defaults. An example is given in . + + To query the current image format applications set the +type field of a &v4l2-format; to +V4L2_BUF_TYPE_VIDEO_CAPTURE and call the +&VIDIOC-G-FMT; ioctl with a pointer to this structure. Drivers fill +the &v4l2-pix-format; pix member of the +fmt union. + + To request different parameters applications set the +type field of a &v4l2-format; as above and +initialize all fields of the &v4l2-pix-format; +vbi member of the +fmt union, or better just modify the +results of VIDIOC_G_FMT, and call the +&VIDIOC-S-FMT; ioctl with a pointer to this structure. Drivers may +adjust the parameters and finally return the actual parameters as +VIDIOC_G_FMT does. + + Like VIDIOC_S_FMT the +&VIDIOC-TRY-FMT; ioctl can be used to learn about hardware limitations +without disabling I/O or possibly time consuming hardware +preparations. + + The contents of &v4l2-pix-format; are discussed in . See also the specification of the +VIDIOC_G_FMT, VIDIOC_S_FMT +and VIDIOC_TRY_FMT ioctls for details. Video +capture devices must implement both the +VIDIOC_G_FMT and +VIDIOC_S_FMT ioctl, even if +VIDIOC_S_FMT ignores all requests and always +returns default parameters as VIDIOC_G_FMT does. +VIDIOC_TRY_FMT is optional. +
+ +
+ Reading Images + + A video capture device may support the read() function and/or streaming (memory mapping or user pointer) I/O. See for details. +
+ + diff --git a/Documentation/DocBook/v4l/dev-codec.xml b/Documentation/DocBook/v4l/dev-codec.xml new file mode 100644 index 000000000000..6e156dc45b94 --- /dev/null +++ b/Documentation/DocBook/v4l/dev-codec.xml @@ -0,0 +1,26 @@ + Codec Interface + + + Suspended + + This interface has been be suspended from the V4L2 API +implemented in Linux 2.6 until we have more experience with codec +device interfaces. + + + A V4L2 codec can compress, decompress, transform, or otherwise +convert video data from one format into another format, in memory. +Applications send data to be converted to the driver through a +&func-write; call, and receive the converted data through a +&func-read; call. For efficiency a driver may also support streaming +I/O. + + [to do] + + diff --git a/Documentation/DocBook/v4l/dev-effect.xml b/Documentation/DocBook/v4l/dev-effect.xml new file mode 100644 index 000000000000..9c243beba0e6 --- /dev/null +++ b/Documentation/DocBook/v4l/dev-effect.xml @@ -0,0 +1,25 @@ + Effect Devices Interface + + + Suspended + + This interface has been be suspended from the V4L2 API +implemented in Linux 2.6 until we have more experience with effect +device interfaces. + + + A V4L2 video effect device can do image effects, filtering, or +combine two or more images or image streams. For example video +transitions or wipes. Applications send data to be processed and +receive the result data either with &func-read; and &func-write; +functions, or through the streaming I/O mechanism. + + [to do] + + diff --git a/Documentation/DocBook/v4l/dev-osd.xml b/Documentation/DocBook/v4l/dev-osd.xml new file mode 100644 index 000000000000..c9a68a2ccd33 --- /dev/null +++ b/Documentation/DocBook/v4l/dev-osd.xml @@ -0,0 +1,164 @@ + Video Output Overlay Interface + Also known as On-Screen Display (OSD) + + + Experimental + + This is an experimental +interface and may change in the future. + + + Some video output devices can overlay a framebuffer image onto +the outgoing video signal. Applications can set up such an overlay +using this interface, which borrows structures and ioctls of the Video Overlay interface. + + The OSD function is accessible through the same character +special file as the Video Output function. +Note the default function of such a /dev/video device +is video capturing or output. The OSD function is only available after +calling the &VIDIOC-S-FMT; ioctl. + +
+ Querying Capabilities + + Devices supporting the Video Output +Overlay interface set the +V4L2_CAP_VIDEO_OUTPUT_OVERLAY flag in the +capabilities field of &v4l2-capability; +returned by the &VIDIOC-QUERYCAP; ioctl. +
+ +
+ Framebuffer + + Contrary to the Video Overlay +interface the framebuffer is normally implemented on the TV card and +not the graphics card. On Linux it is accessible as a framebuffer +device (/dev/fbN). Given a V4L2 device, +applications can find the corresponding framebuffer device by calling +the &VIDIOC-G-FBUF; ioctl. It returns, amongst other information, the +physical address of the framebuffer in the +base field of &v4l2-framebuffer;. The +framebuffer device ioctl FBIOGET_FSCREENINFO +returns the same address in the smem_start +field of struct fb_fix_screeninfo. The +FBIOGET_FSCREENINFO ioctl and struct +fb_fix_screeninfo are defined in the +linux/fb.h header file. + + The width and height of the framebuffer depends on the +current video standard. A V4L2 driver may reject attempts to change +the video standard (or any other ioctl which would imply a framebuffer +size change) with an &EBUSY; until all applications closed the +framebuffer device. + + + Finding a framebuffer device for OSD + + +#include <linux/fb.h> + +&v4l2-framebuffer; fbuf; +unsigned int i; +int fb_fd; + +if (-1 == ioctl (fd, VIDIOC_G_FBUF, &fbuf)) { + perror ("VIDIOC_G_FBUF"); + exit (EXIT_FAILURE); +} + +for (i = 0; i > 30; ++i) { + char dev_name[16]; + struct fb_fix_screeninfo si; + + snprintf (dev_name, sizeof (dev_name), "/dev/fb%u", i); + + fb_fd = open (dev_name, O_RDWR); + if (-1 == fb_fd) { + switch (errno) { + case ENOENT: /* no such file */ + case ENXIO: /* no driver */ + continue; + + default: + perror ("open"); + exit (EXIT_FAILURE); + } + } + + if (0 == ioctl (fb_fd, FBIOGET_FSCREENINFO, &si)) { + if (si.smem_start == (unsigned long) fbuf.base) + break; + } else { + /* Apparently not a framebuffer device. */ + } + + close (fb_fd); + fb_fd = -1; +} + +/* fb_fd is the file descriptor of the framebuffer device + for the video output overlay, or -1 if no device was found. */ + + +
+ +
+ Overlay Window and Scaling + + The overlay is controlled by source and target rectangles. +The source rectangle selects a subsection of the framebuffer image to +be overlaid, the target rectangle an area in the outgoing video signal +where the image will appear. Drivers may or may not support scaling, +and arbitrary sizes and positions of these rectangles. Further drivers +may support any (or none) of the clipping/blending methods defined for +the Video Overlay interface. + + A &v4l2-window; defines the size of the source rectangle, +its position in the framebuffer and the clipping/blending method to be +used for the overlay. To get the current parameters applications set +the type field of a &v4l2-format; to +V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY and call the +&VIDIOC-G-FMT; ioctl. The driver fills the +v4l2_window substructure named +win. It is not possible to retrieve a +previously programmed clipping list or bitmap. + + To program the source rectangle applications set the +type field of a &v4l2-format; to +V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY, initialize +the win substructure and call the +&VIDIOC-S-FMT; ioctl. The driver adjusts the parameters against +hardware limits and returns the actual parameters as +VIDIOC_G_FMT does. Like +VIDIOC_S_FMT, the &VIDIOC-TRY-FMT; ioctl can be +used to learn about driver capabilities without actually changing +driver state. Unlike VIDIOC_S_FMT this also works +after the overlay has been enabled. + + A &v4l2-crop; defines the size and position of the target +rectangle. The scaling factor of the overlay is implied by the width +and height given in &v4l2-window; and &v4l2-crop;. The cropping API +applies to Video Output and Video +Output Overlay devices in the same way as to +Video Capture and Video +Overlay devices, merely reversing the direction of the +data flow. For more information see . +
+ +
+ Enabling Overlay + + There is no V4L2 ioctl to enable or disable the overlay, +however the framebuffer interface of the driver may support the +FBIOBLANK ioctl. +
+ + diff --git a/Documentation/DocBook/v4l/dev-output.xml b/Documentation/DocBook/v4l/dev-output.xml new file mode 100644 index 000000000000..63c3c20e5a72 --- /dev/null +++ b/Documentation/DocBook/v4l/dev-output.xml @@ -0,0 +1,111 @@ + Video Output Interface + + Video output devices encode stills or image sequences as +analog video signal. With this interface applications can +control the encoding process and move images from user space to +the driver. + + Conventionally V4L2 video output devices are accessed through +character device special files named /dev/video +and /dev/video0 to +/dev/video63 with major number 81 and minor +numbers 0 to 63. /dev/video is typically a +symbolic link to the preferred video device. Note the same device +files are used for video capture devices. + +
+ Querying Capabilities + + Devices supporting the video output interface set the +V4L2_CAP_VIDEO_OUTPUT flag in the +capabilities field of &v4l2-capability; +returned by the &VIDIOC-QUERYCAP; ioctl. As secondary device functions +they may also support the raw VBI +output (V4L2_CAP_VBI_OUTPUT) interface. At +least one of the read/write or streaming I/O methods must be +supported. Modulators and audio outputs are optional. +
+ +
+ Supplemental Functions + + Video output devices shall support audio output, modulator, controls, +cropping and scaling and streaming parameter ioctls as needed. +The video output and video standard ioctls must be supported by +all video output devices. +
+ +
+ Image Format Negotiation + + The output is determined by cropping and image format +parameters. The former select an area of the video picture where the +image will appear, the latter how images are stored in memory, &ie; in +RGB or YUV format, the number of bits per pixel or width and height. +Together they also define how images are scaled in the process. + + As usual these parameters are not reset +at &func-open; time to permit Unix tool chains, programming a device +and then writing to it as if it was a plain file. Well written V4L2 +applications ensure they really get what they want, including cropping +and scaling. + + Cropping initialization at minimum requires to reset the +parameters to defaults. An example is given in . + + To query the current image format applications set the +type field of a &v4l2-format; to +V4L2_BUF_TYPE_VIDEO_OUTPUT and call the +&VIDIOC-G-FMT; ioctl with a pointer to this structure. Drivers fill +the &v4l2-pix-format; pix member of the +fmt union. + + To request different parameters applications set the +type field of a &v4l2-format; as above and +initialize all fields of the &v4l2-pix-format; +vbi member of the +fmt union, or better just modify the +results of VIDIOC_G_FMT, and call the +&VIDIOC-S-FMT; ioctl with a pointer to this structure. Drivers may +adjust the parameters and finally return the actual parameters as +VIDIOC_G_FMT does. + + Like VIDIOC_S_FMT the +&VIDIOC-TRY-FMT; ioctl can be used to learn about hardware limitations +without disabling I/O or possibly time consuming hardware +preparations. + + The contents of &v4l2-pix-format; are discussed in . See also the specification of the +VIDIOC_G_FMT, VIDIOC_S_FMT +and VIDIOC_TRY_FMT ioctls for details. Video +output devices must implement both the +VIDIOC_G_FMT and +VIDIOC_S_FMT ioctl, even if +VIDIOC_S_FMT ignores all requests and always +returns default parameters as VIDIOC_G_FMT does. +VIDIOC_TRY_FMT is optional. +
+ +
+ Writing Images + + A video output device may support the write() function and/or streaming (memory mapping or user pointer) I/O. See for details. +
+ + diff --git a/Documentation/DocBook/v4l/dev-overlay.xml b/Documentation/DocBook/v4l/dev-overlay.xml new file mode 100644 index 000000000000..92513cf79150 --- /dev/null +++ b/Documentation/DocBook/v4l/dev-overlay.xml @@ -0,0 +1,379 @@ + Video Overlay Interface + Also known as Framebuffer Overlay or Previewing + + Video overlay devices have the ability to genlock (TV-)video +into the (VGA-)video signal of a graphics card, or to store captured +images directly in video memory of a graphics card, typically with +clipping. This can be considerable more efficient than capturing +images and displaying them by other means. In the old days when only +nuclear power plants needed cooling towers this used to be the only +way to put live video into a window. + + Video overlay devices are accessed through the same character +special files as video capture devices. +Note the default function of a /dev/video device +is video capturing. The overlay function is only available after +calling the &VIDIOC-S-FMT; ioctl. + + The driver may support simultaneous overlay and capturing +using the read/write and streaming I/O methods. If so, operation at +the nominal frame rate of the video standard is not guaranteed. Frames +may be directed away from overlay to capture, or one field may be used +for overlay and the other for capture if the capture parameters permit +this. + + Applications should use different file descriptors for +capturing and overlay. This must be supported by all drivers capable +of simultaneous capturing and overlay. Optionally these drivers may +also permit capturing and overlay with a single file descriptor for +compatibility with V4L and earlier versions of V4L2. + A common application of two file descriptors is the +XFree86 Xv/V4L interface driver and +a V4L2 application. While the X server controls video overlay, the +application can take advantage of memory mapping and DMA. + In the opinion of the designers of this API, no driver +writer taking the efforts to support simultaneous capturing and +overlay will restrict this ability by requiring a single file +descriptor, as in V4L and earlier versions of V4L2. Making this +optional means applications depending on two file descriptors need +backup routines to be compatible with all drivers, which is +considerable more work than using two fds in applications which do +not. Also two fd's fit the general concept of one file descriptor for +each logical stream. Hence as a complexity trade-off drivers +must support two file descriptors and +may support single fd operation. + + +
+ Querying Capabilities + + Devices supporting the video overlay interface set the +V4L2_CAP_VIDEO_OVERLAY flag in the +capabilities field of &v4l2-capability; +returned by the &VIDIOC-QUERYCAP; ioctl. The overlay I/O method specified +below must be supported. Tuners and audio inputs are optional. +
+ +
+ Supplemental Functions + + Video overlay devices shall support audio input, tuner, controls, +cropping and scaling and streaming parameter ioctls as needed. +The video input and video standard ioctls must be supported by +all video overlay devices. +
+ +
+ Setup + + Before overlay can commence applications must program the +driver with frame buffer parameters, namely the address and size of +the frame buffer and the image format, for example RGB 5:6:5. The +&VIDIOC-G-FBUF; and &VIDIOC-S-FBUF; ioctls are available to get +and set these parameters, respectively. The +VIDIOC_S_FBUF ioctl is privileged because it +allows to set up DMA into physical memory, bypassing the memory +protection mechanisms of the kernel. Only the superuser can change the +frame buffer address and size. Users are not supposed to run TV +applications as root or with SUID bit set. A small helper application +with suitable privileges should query the graphics system and program +the V4L2 driver at the appropriate time. + + Some devices add the video overlay to the output signal +of the graphics card. In this case the frame buffer is not modified by +the video device, and the frame buffer address and pixel format are +not needed by the driver. The VIDIOC_S_FBUF ioctl +is not privileged. An application can check for this type of device by +calling the VIDIOC_G_FBUF ioctl. + + A driver may support any (or none) of five clipping/blending +methods: + + Chroma-keying displays the overlaid image only where +pixels in the primary graphics surface assume a certain color. + + + A bitmap can be specified where each bit corresponds +to a pixel in the overlaid image. When the bit is set, the +corresponding video pixel is displayed, otherwise a pixel of the +graphics surface. + + + A list of clipping rectangles can be specified. In +these regions no video is displayed, so the +graphics surface can be seen here. + + + The framebuffer has an alpha channel that can be used +to clip or blend the framebuffer with the video. + + + A global alpha value can be specified to blend the +framebuffer contents with video images. + + + + When simultaneous capturing and overlay is supported and +the hardware prohibits different image and frame buffer formats, the +format requested first takes precedence. The attempt to capture +(&VIDIOC-S-FMT;) or overlay (&VIDIOC-S-FBUF;) may fail with an +&EBUSY; or return accordingly modified parameters.. +
+ +
+ Overlay Window + + The overlaid image is determined by cropping and overlay +window parameters. The former select an area of the video picture to +capture, the latter how images are overlaid and clipped. Cropping +initialization at minimum requires to reset the parameters to +defaults. An example is given in . + + The overlay window is described by a &v4l2-window;. It +defines the size of the image, its position over the graphics surface +and the clipping to be applied. To get the current parameters +applications set the type field of a +&v4l2-format; to V4L2_BUF_TYPE_VIDEO_OVERLAY and +call the &VIDIOC-G-FMT; ioctl. The driver fills the +v4l2_window substructure named +win. It is not possible to retrieve a +previously programmed clipping list or bitmap. + + To program the overlay window applications set the +type field of a &v4l2-format; to +V4L2_BUF_TYPE_VIDEO_OVERLAY, initialize the +win substructure and call the +&VIDIOC-S-FMT; ioctl. The driver adjusts the parameters against +hardware limits and returns the actual parameters as +VIDIOC_G_FMT does. Like +VIDIOC_S_FMT, the &VIDIOC-TRY-FMT; ioctl can be +used to learn about driver capabilities without actually changing +driver state. Unlike VIDIOC_S_FMT this also works +after the overlay has been enabled. + + The scaling factor of the overlaid image is implied by the +width and height given in &v4l2-window; and the size of the cropping +rectangle. For more information see . + + When simultaneous capturing and overlay is supported and +the hardware prohibits different image and window sizes, the size +requested first takes precedence. The attempt to capture or overlay as +well (&VIDIOC-S-FMT;) may fail with an &EBUSY; or return accordingly +modified parameters. + + + struct <structname>v4l2_window</structname> + + &cs-str; + + + &v4l2-rect; + w + Size and position of the window relative to the +top, left corner of the frame buffer defined with &VIDIOC-S-FBUF;. The +window can extend the frame buffer width and height, the +x and y +coordinates can be negative, and it can lie completely outside the +frame buffer. The driver clips the window accordingly, or if that is +not possible, modifies its size and/or position. + + + &v4l2-field; + field + Applications set this field to determine which +video field shall be overlaid, typically one of +V4L2_FIELD_ANY (0), +V4L2_FIELD_TOP, +V4L2_FIELD_BOTTOM or +V4L2_FIELD_INTERLACED. Drivers may have to choose +a different field order and return the actual setting here. + + + __u32 + chromakey + When chroma-keying has been negotiated with +&VIDIOC-S-FBUF; applications set this field to the desired pixel value +for the chroma key. The format is the same as the pixel format of the +framebuffer (&v4l2-framebuffer; +fmt.pixelformat field), with bytes in host +order. E. g. for V4L2_PIX_FMT_BGR24 +the value should be 0xRRGGBB on a little endian, 0xBBGGRR on a big +endian host. + + + &v4l2-clip; * + clips + When chroma-keying has not +been negotiated and &VIDIOC-G-FBUF; indicated this capability, +applications can set this field to point to an array of +clipping rectangles. + + + + + Like the window coordinates +w, clipping rectangles are defined relative +to the top, left corner of the frame buffer. However clipping +rectangles must not extend the frame buffer width and height, and they +must not overlap. If possible applications should merge adjacent +rectangles. Whether this must create x-y or y-x bands, or the order of +rectangles, is not defined. When clip lists are not supported the +driver ignores this field. Its contents after calling &VIDIOC-S-FMT; +are undefined. + + + __u32 + clipcount + When the application set the +clips field, this field must contain the +number of clipping rectangles in the list. When clip lists are not +supported the driver ignores this field, its contents after calling +VIDIOC_S_FMT are undefined. When clip lists are +supported but no clipping is desired this field must be set to +zero. + + + void * + bitmap + When chroma-keying has +not been negotiated and &VIDIOC-G-FBUF; indicated +this capability, applications can set this field to point to a +clipping bit mask. + + + It must be of the same size +as the window, w.width and +w.height. Each bit corresponds to a pixel +in the overlaid image, which is displayed only when the bit is +set. Pixel coordinates translate to bits like: + +((__u8 *) bitmap)[w.width * y + x / 8] & (1 << (x & 7))where 0 ≤ x < +w.width and 0 ≤ +y <w.height. + Should we require + w.width to be a multiple of + eight? + When a clipping +bit mask is not supported the driver ignores this field, its contents +after calling &VIDIOC-S-FMT; are undefined. When a bit mask is supported +but no clipping is desired this field must be set to +NULL.Applications need not create a +clip list or bit mask. When they pass both, or despite negotiating +chroma-keying, the results are undefined. Regardless of the chosen +method, the clipping abilities of the hardware may be limited in +quantity or quality. The results when these limits are exceeded are +undefined. + When the image is written into frame buffer +memory it will be undesirable if the driver clips out less pixels +than expected, because the application and graphics system are not +aware these regions need to be refreshed. The driver should clip out +more pixels or not write the image at all. + + + + __u8 + global_alpha + The global alpha value used to blend the +framebuffer with video images, if global alpha blending has been +negotiated (V4L2_FBUF_FLAG_GLOBAL_ALPHA, see +&VIDIOC-S-FBUF;, ). + + + + + Note this field was added in Linux 2.6.23, extending the structure. However +the VIDIOC_G/S/TRY_FMT ioctls, +which take a pointer to a v4l2_format parent structure with padding +bytes at the end, are not affected. + + + +
+ + + struct <structname>v4l2_clip</structname><footnote> + <para>The X Window system defines "regions" which are +vectors of struct BoxRec { short x1, y1, x2, y2; } with width = x2 - +x1 and height = y2 - y1, so one cannot pass X11 clip lists +directly.</para> + </footnote> + + &cs-str; + + + &v4l2-rect; + c + Coordinates of the clipping rectangle, relative to +the top, left corner of the frame buffer. Only window pixels +outside all clipping rectangles are +displayed. + + + &v4l2-clip; * + next + Pointer to the next clipping rectangle, NULL when +this is the last rectangle. Drivers ignore this field, it cannot be +used to pass a linked list of clipping rectangles. + + + +
+ + + + + struct <structname>v4l2_rect</structname> + + &cs-str; + + + __s32 + left + Horizontal offset of the top, left corner of the +rectangle, in pixels. + + + __s32 + top + Vertical offset of the top, left corner of the +rectangle, in pixels. Offsets increase to the right and down. + + + __s32 + width + Width of the rectangle, in pixels. + + + __s32 + height + Height of the rectangle, in pixels. Width and +height cannot be negative, the fields are signed for hysterical +reasons. + + + +
+
+ +
+ Enabling Overlay + + To start or stop the frame buffer overlay applications call +the &VIDIOC-OVERLAY; ioctl. +
+ + diff --git a/Documentation/DocBook/v4l/dev-radio.xml b/Documentation/DocBook/v4l/dev-radio.xml new file mode 100644 index 000000000000..73aa90b45b34 --- /dev/null +++ b/Documentation/DocBook/v4l/dev-radio.xml @@ -0,0 +1,57 @@ + Radio Interface + + This interface is intended for AM and FM (analog) radio +receivers and transmitters. + + Conventionally V4L2 radio devices are accessed through +character device special files named /dev/radio +and /dev/radio0 to +/dev/radio63 with major number 81 and minor +numbers 64 to 127. + +
+ Querying Capabilities + + Devices supporting the radio interface set the +V4L2_CAP_RADIO and +V4L2_CAP_TUNER or +V4L2_CAP_MODULATOR flag in the +capabilities field of &v4l2-capability; +returned by the &VIDIOC-QUERYCAP; ioctl. Other combinations of +capability flags are reserved for future extensions. +
+ +
+ Supplemental Functions + + Radio devices can support controls, and must support the tuner or modulator ioctls. + + They do not support the video input or output, audio input +or output, video standard, cropping and scaling, compression and +streaming parameter, or overlay ioctls. All other ioctls and I/O +methods are reserved for future extensions. +
+ +
+ Programming + + Radio devices may have a couple audio controls (as discussed +in ) such as a volume control, possibly custom +controls. Further all radio devices have one tuner or modulator (these are +discussed in ) with index number zero to select +the radio frequency and to determine if a monaural or FM stereo +program is received/emitted. Drivers switch automatically between AM and FM +depending on the selected frequency. The &VIDIOC-G-TUNER; or +&VIDIOC-G-MODULATOR; ioctl +reports the supported frequency range. +
+ + diff --git a/Documentation/DocBook/v4l/dev-raw-vbi.xml b/Documentation/DocBook/v4l/dev-raw-vbi.xml new file mode 100644 index 000000000000..c5a70bdfaf27 --- /dev/null +++ b/Documentation/DocBook/v4l/dev-raw-vbi.xml @@ -0,0 +1,347 @@ + Raw VBI Data Interface + + VBI is an abbreviation of Vertical Blanking Interval, a gap +in the sequence of lines of an analog video signal. During VBI +no picture information is transmitted, allowing some time while the +electron beam of a cathode ray tube TV returns to the top of the +screen. Using an oscilloscope you will find here the vertical +synchronization pulses and short data packages ASK +modulatedASK: Amplitude-Shift Keying. A high signal +level represents a '1' bit, a low level a '0' bit. +onto the video signal. These are transmissions of services such as +Teletext or Closed Caption. + + Subject of this interface type is raw VBI data, as sampled off +a video signal, or to be added to a signal for output. +The data format is similar to uncompressed video images, a number of +lines times a number of samples per line, we call this a VBI image. + + Conventionally V4L2 VBI devices are accessed through character +device special files named /dev/vbi and +/dev/vbi0 to /dev/vbi31 with +major number 81 and minor numbers 224 to 255. +/dev/vbi is typically a symbolic link to the +preferred VBI device. This convention applies to both input and output +devices. + + To address the problems of finding related video and VBI +devices VBI capturing and output is also available as device function +under /dev/video. To capture or output raw VBI +data with these devices applications must call the &VIDIOC-S-FMT; +ioctl. Accessed as /dev/vbi, raw VBI capturing +or output is the default device function. + +
+ Querying Capabilities + + Devices supporting the raw VBI capturing or output API set +the V4L2_CAP_VBI_CAPTURE or +V4L2_CAP_VBI_OUTPUT flags, respectively, in the +capabilities field of &v4l2-capability; +returned by the &VIDIOC-QUERYCAP; ioctl. At least one of the +read/write, streaming or asynchronous I/O methods must be +supported. VBI devices may or may not have a tuner or modulator. +
+ +
+ Supplemental Functions + + VBI devices shall support video +input or output, tuner or +modulator, and controls ioctls +as needed. The video standard ioctls provide +information vital to program a VBI device, therefore must be +supported. +
+ +
+ Raw VBI Format Negotiation + + Raw VBI sampling abilities can vary, in particular the +sampling frequency. To properly interpret the data V4L2 specifies an +ioctl to query the sampling parameters. Moreover, to allow for some +flexibility applications can also suggest different parameters. + + As usual these parameters are not +reset at &func-open; time to permit Unix tool chains, programming a +device and then reading from it as if it was a plain file. Well +written V4L2 applications should always ensure they really get what +they want, requesting reasonable parameters and then checking if the +actual parameters are suitable. + + To query the current raw VBI capture parameters +applications set the type field of a +&v4l2-format; to V4L2_BUF_TYPE_VBI_CAPTURE or +V4L2_BUF_TYPE_VBI_OUTPUT, and call the +&VIDIOC-G-FMT; ioctl with a pointer to this structure. Drivers fill +the &v4l2-vbi-format; vbi member of the +fmt union. + + To request different parameters applications set the +type field of a &v4l2-format; as above and +initialize all fields of the &v4l2-vbi-format; +vbi member of the +fmt union, or better just modify the +results of VIDIOC_G_FMT, and call the +&VIDIOC-S-FMT; ioctl with a pointer to this structure. Drivers return +an &EINVAL; only when the given parameters are ambiguous, otherwise +they modify the parameters according to the hardware capabilites and +return the actual parameters. When the driver allocates resources at +this point, it may return an &EBUSY; to indicate the returned +parameters are valid but the required resources are currently not +available. That may happen for instance when the video and VBI areas +to capture would overlap, or when the driver supports multiple opens +and another process already requested VBI capturing or output. Anyway, +applications must expect other resource allocation points which may +return EBUSY, at the &VIDIOC-STREAMON; ioctl +and the first read(), write() and select() call. + + VBI devices must implement both the +VIDIOC_G_FMT and +VIDIOC_S_FMT ioctl, even if +VIDIOC_S_FMT ignores all requests and always +returns default parameters as VIDIOC_G_FMT does. +VIDIOC_TRY_FMT is optional. + + + struct <structname>v4l2_vbi_format</structname> + + &cs-str; + + + __u32 + sampling_rate + Samples per second, i. e. unit 1 Hz. + + + __u32 + offset + Horizontal offset of the VBI image, +relative to the leading edge of the line synchronization pulse and +counted in samples: The first sample in the VBI image will be located +offset / +sampling_rate seconds following the leading +edge. See also . + + + __u32 + samples_per_line + + + + __u32 + sample_format + Defines the sample format as in , a four-character-code. + A few devices may be unable to +sample VBI data at all but can extend the video capture window to the +VBI region. + Usually this is +V4L2_PIX_FMT_GREY, i. e. each sample +consists of 8 bits with lower values oriented towards the black level. +Do not assume any other correlation of values with the signal level. +For example, the MSB does not necessarily indicate if the signal is +'high' or 'low' because 128 may not be the mean value of the +signal. Drivers shall not convert the sample format by software. + + + __u32 + start[2] + This is the scanning system line number +associated with the first line of the VBI image, of the first and the +second field respectively. See and + for valid values. VBI input drivers can +return start values 0 if the hardware cannot reliable identify +scanning lines, VBI acquisition may not require this +information. + + + __u32 + count[2] + The number of lines in the first and second +field image, respectively. + + + Drivers should be as +flexibility as possible. For example, it may be possible to extend or +move the VBI capture window down to the picture area, implementing a +'full field mode' to capture data service transmissions embedded in +the picture.An application can set the first or second +count value to zero if no data is required +from the respective field; count[1] if the +scanning system is progressive, &ie; not interlaced. The +corresponding start value shall be ignored by the application and +driver. Anyway, drivers may not support single field capturing and +return both count values non-zero.Both +count values set to zero, or line numbers +outside the bounds depicted in and , or a field image covering +lines of two fields, are invalid and shall not be returned by the +driver.To initialize the start +and count fields, applications must first +determine the current video standard selection. The &v4l2-std-id; or +the framelines field of &v4l2-standard; can +be evaluated for this purpose. + + + __u32 + flags + See below. Currently +only drivers set flags, applications must set this field to +zero. + + + __u32 + reserved[2] + This array is reserved for future extensions. +Drivers and applications must set it to zero. + + + +
+ + + Raw VBI Format Flags + + &cs-def; + + + V4L2_VBI_UNSYNC + 0x0001 + This flag indicates hardware which does not +properly distinguish between fields. Normally the VBI image stores the +first field (lower scanning line numbers) first in memory. This may be +a top or bottom field depending on the video standard. When this flag +is set the first or second field may be stored first, however the +fields are still in correct temporal order with the older field first +in memory. + Most VBI services transmit on both fields, but +some have different semantics depending on the field number. These +cannot be reliable decoded or encoded when +V4L2_VBI_UNSYNC is set. + + + + V4L2_VBI_INTERLACED + 0x0002 + By default the two field images will be passed +sequentially; all lines of the first field followed by all lines of +the second field (compare +V4L2_FIELD_SEQ_TB and +V4L2_FIELD_SEQ_BT, whether the top or bottom +field is first in memory depends on the video standard). When this +flag is set, the two fields are interlaced (cf. +V4L2_FIELD_INTERLACED). The first line of the +first field followed by the first line of the second field, then the +two second lines, and so on. Such a layout may be necessary when the +hardware has been programmed to capture or output interlaced video +images and is unable to separate the fields for VBI capturing at +the same time. For simplicity setting this flag implies that both +count values are equal and non-zero. + + + +
+ +
+ Line synchronization + + + + + + + + + Line synchronization diagram + + +
+ +
+ ITU-R 525 line numbering (M/NTSC and M/PAL) + + + + + + + + + NTSC field synchronization diagram + + + (1) For the purpose of this specification field 2 +starts in line 264 and not 263.5 because half line capturing is not +supported. + + +
+ +
+ ITU-R 625 line numbering + + + + + + + + + PAL/SECAM field synchronization diagram + + + (1) For the purpose of this specification field 2 +starts in line 314 and not 313.5 because half line capturing is not +supported. + + +
+ + Remember the VBI image format depends on the selected +video standard, therefore the application must choose a new standard or +query the current standard first. Attempts to read or write data ahead +of format negotiation, or after switching the video standard which may +invalidate the negotiated VBI parameters, should be refused by the +driver. A format change during active I/O is not permitted. +
+ +
+ Reading and writing VBI images + + To assure synchronization with the field number and easier +implementation, the smallest unit of data passed at a time is one +frame, consisting of two fields of VBI images immediately following in +memory. + + The total size of a frame computes as follows: + + +(count[0] + count[1]) * +samples_per_line * sample size in bytes + + The sample size is most likely always one byte, +applications must check the sample_format +field though, to function properly with other drivers. + + A VBI device may support read/write and/or streaming (memory mapping or user pointer) I/O. The latter bears the +possibility of synchronizing video and +VBI data by using buffer timestamps. + + Remember the &VIDIOC-STREAMON; ioctl and the first read(), +write() and select() call can be resource allocation points returning +an &EBUSY; if the required hardware resources are temporarily +unavailable, for example the device is already in use by another +process. +
+ + diff --git a/Documentation/DocBook/v4l/dev-rds.xml b/Documentation/DocBook/v4l/dev-rds.xml new file mode 100644 index 000000000000..0869d701b1e5 --- /dev/null +++ b/Documentation/DocBook/v4l/dev-rds.xml @@ -0,0 +1,168 @@ + RDS Interface + + The Radio Data System transmits supplementary +information in binary format, for example the station name or travel +information, on an inaudible audio subcarrier of a radio program. This +interface is aimed at devices capable of receiving and decoding RDS +information. + + For more information see the core RDS standard +and the RBDS standard . + + Note that the RBDS standard as is used in the USA is almost identical +to the RDS standard. Any RDS decoder can also handle RBDS. Only some of the fields +have slightly different meanings. See the RBDS standard for more information. + + The RBDS standard also specifies support for MMBS (Modified Mobile Search). +This is a proprietary format which seems to be discontinued. The RDS interface does not +support this format. Should support for MMBS (or the so-called 'E blocks' in general) +be needed, then please contact the linux-media mailing list: &v4l-ml;. + +
+ Querying Capabilities + + Devices supporting the RDS capturing API +set the V4L2_CAP_RDS_CAPTURE flag in +the capabilities field of &v4l2-capability; +returned by the &VIDIOC-QUERYCAP; ioctl. +Any tuner that supports RDS will set the +V4L2_TUNER_CAP_RDS flag in the capability +field of &v4l2-tuner;. +Whether an RDS signal is present can be detected by looking at +the rxsubchans field of &v4l2-tuner;: the +V4L2_TUNER_SUB_RDS will be set if RDS data was detected. + + Devices supporting the RDS output API +set the V4L2_CAP_RDS_OUTPUT flag in +the capabilities field of &v4l2-capability; +returned by the &VIDIOC-QUERYCAP; ioctl. +Any modulator that supports RDS will set the +V4L2_TUNER_CAP_RDS flag in the capability +field of &v4l2-modulator;. +In order to enable the RDS transmission one must set the V4L2_TUNER_SUB_RDS +bit in the txsubchans field of &v4l2-modulator;. + +
+ +
+ Reading RDS data + + RDS data can be read from the radio device +with the &func-read; function. The data is packed in groups of three bytes, +as follows: + + struct +<structname>v4l2_rds_data</structname> + + + + + + + __u8 + lsb + Least Significant Byte of RDS Block + + + __u8 + msb + Most Significant Byte of RDS Block + + + __u8 + block + Block description + + + +
+ + Block description + + + + + + Bits 0-2 + Block (aka offset) of the received data. + + + Bits 3-5 + Deprecated. Currently identical to bits 0-2. Do not use these bits. + + + Bit 6 + Corrected bit. Indicates that an error was corrected for this data block. + + + Bit 7 + Error bit. Indicates that an uncorrectable error occurred during reception of this block. + + + +
+ + + Block defines + + + + + + + V4L2_RDS_BLOCK_MSK + 7 + Mask for bits 0-2 to get the block ID. + + + V4L2_RDS_BLOCK_A + 0 + Block A. + + + V4L2_RDS_BLOCK_B + 1 + Block B. + + + V4L2_RDS_BLOCK_C + 2 + Block C. + + + V4L2_RDS_BLOCK_D + 3 + Block D. + + + V4L2_RDS_BLOCK_C_ALT + 4 + Block C'. + + + V4L2_RDS_BLOCK_INVALID + 7 + An invalid block. + + + V4L2_RDS_BLOCK_CORRECTED + 0x40 + A bit error was detected but corrected. + + + V4L2_RDS_BLOCK_ERROR + 0x80 + An incorrectable error occurred. + + + +
+
+ + diff --git a/Documentation/DocBook/v4l/dev-sliced-vbi.xml b/Documentation/DocBook/v4l/dev-sliced-vbi.xml new file mode 100644 index 000000000000..69e789fa7f7b --- /dev/null +++ b/Documentation/DocBook/v4l/dev-sliced-vbi.xml @@ -0,0 +1,708 @@ + Sliced VBI Data Interface + + VBI stands for Vertical Blanking Interval, a gap in the +sequence of lines of an analog video signal. During VBI no picture +information is transmitted, allowing some time while the electron beam +of a cathode ray tube TV returns to the top of the screen. + + Sliced VBI devices use hardware to demodulate data transmitted +in the VBI. V4L2 drivers shall not do this by +software, see also the raw VBI +interface. The data is passed as short packets of fixed size, +covering one scan line each. The number of packets per video frame is +variable. + + Sliced VBI capture and output devices are accessed through the +same character special files as raw VBI devices. When a driver +supports both interfaces, the default function of a +/dev/vbi device is raw VBI +capturing or output, and the sliced VBI function is only available +after calling the &VIDIOC-S-FMT; ioctl as defined below. Likewise a +/dev/video device may support the sliced VBI API, +however the default function here is video capturing or output. +Different file descriptors must be used to pass raw and sliced VBI +data simultaneously, if this is supported by the driver. + +
+ Querying Capabilities + + Devices supporting the sliced VBI capturing or output API +set the V4L2_CAP_SLICED_VBI_CAPTURE or +V4L2_CAP_SLICED_VBI_OUTPUT flag respectively, in +the capabilities field of &v4l2-capability; +returned by the &VIDIOC-QUERYCAP; ioctl. At least one of the +read/write, streaming or asynchronous I/O +methods must be supported. Sliced VBI devices may have a tuner +or modulator. +
+ +
+ Supplemental Functions + + Sliced VBI devices shall support video +input or output and tuner or +modulator ioctls if they have these capabilities, and they may +support control ioctls. The video standard ioctls provide information +vital to program a sliced VBI device, therefore must be +supported. +
+ +
+ Sliced VBI Format Negotiation + + To find out which data services are supported by the +hardware applications can call the &VIDIOC-G-SLICED-VBI-CAP; ioctl. +All drivers implementing the sliced VBI interface must support this +ioctl. The results may differ from those of the &VIDIOC-S-FMT; ioctl +when the number of VBI lines the hardware can capture or output per +frame, or the number of services it can identify on a given line are +limited. For example on PAL line 16 the hardware may be able to look +for a VPS or Teletext signal, but not both at the same time. + + To determine the currently selected services applications +set the type field of &v4l2-format; to + V4L2_BUF_TYPE_SLICED_VBI_CAPTURE or +V4L2_BUF_TYPE_SLICED_VBI_OUTPUT, and the &VIDIOC-G-FMT; +ioctl fills the fmt.sliced member, a +&v4l2-sliced-vbi-format;. + + Applications can request different parameters by +initializing or modifying the fmt.sliced +member and calling the &VIDIOC-S-FMT; ioctl with a pointer to the +v4l2_format structure. + + The sliced VBI API is more complicated than the raw VBI API +because the hardware must be told which VBI service to expect on each +scan line. Not all services may be supported by the hardware on all +lines (this is especially true for VBI output where Teletext is often +unsupported and other services can only be inserted in one specific +line). In many cases, however, it is sufficient to just set the +service_set field to the required services +and let the driver fill the service_lines +array according to hardware capabilities. Only if more precise control +is needed should the programmer set the +service_lines array explicitly. + + The &VIDIOC-S-FMT; ioctl modifies the parameters +according to hardware capabilities. When the driver allocates +resources at this point, it may return an &EBUSY; if the required +resources are temporarily unavailable. Other resource allocation +points which may return EBUSY can be the +&VIDIOC-STREAMON; ioctl and the first &func-read;, &func-write; and +&func-select; call. + + + struct +<structname>v4l2_sliced_vbi_format</structname> + + + + + + + + + + __u32 + service_set + If +service_set is non-zero when passed with +&VIDIOC-S-FMT; or &VIDIOC-TRY-FMT;, the +service_lines array will be filled by the +driver according to the services specified in this field. For example, +if service_set is initialized with +V4L2_SLICED_TELETEXT_B | V4L2_SLICED_WSS_625, a +driver for the cx25840 video decoder sets lines 7-22 of both +fieldsAccording to ETS 300 706 lines 6-22 of the +first field and lines 5-22 of the second field may carry Teletext +data. to V4L2_SLICED_TELETEXT_B +and line 23 of the first field to +V4L2_SLICED_WSS_625. If +service_set is set to zero, then the values +of service_lines will be used instead. +On return the driver sets this field to the union of all +elements of the returned service_lines +array. It may contain less services than requested, perhaps just one, +if the hardware cannot handle more services simultaneously. It may be +empty (zero) if none of the requested services are supported by the +hardware. + + + __u16 + service_lines[2][24] + Applications initialize this +array with sets of data services the driver shall look for or insert +on the respective scan line. Subject to hardware capabilities drivers +return the requested set, a subset, which may be just a single +service, or an empty set. When the hardware cannot handle multiple +services on the same line the driver shall choose one. No assumptions +can be made on which service the driver chooses.Data +services are defined in . Array indices +map to ITU-R line numbers (see also and ) as follows: + + + + + Element + 525 line systems + 625 line systems + + + + + service_lines[0][1] + 1 + 1 + + + + + service_lines[0][23] + 23 + 23 + + + + + service_lines[1][1] + 264 + 314 + + + + + service_lines[1][23] + 286 + 336 + + + + + + Drivers must set +service_lines[0][0] and +service_lines[1][0] to zero. + + + __u32 + io_size + Maximum number of bytes passed by +one &func-read; or &func-write; call, and the buffer size in bytes for +the &VIDIOC-QBUF; and &VIDIOC-DQBUF; ioctl. Drivers set this field to +the size of &v4l2-sliced-vbi-data; times the number of non-zero +elements in the returned service_lines +array (that is the number of lines potentially carrying data). + + + __u32 + reserved[2] + This array is reserved for future +extensions. Applications and drivers must set it to zero. + + + +
+ + + + Sliced VBI services + + + + + + + + + + Symbol + Value + Reference + Lines, usually + Payload + + + + + V4L2_SLICED_TELETEXT_B +(Teletext System B) + 0x0001 + , + PAL/SECAM line 7-22, 320-335 (second field 7-22) + Last 42 of the 45 byte Teletext packet, that is +without clock run-in and framing code, lsb first transmitted. + + + V4L2_SLICED_VPS + 0x0400 + + PAL line 16 + Byte number 3 to 15 according to Figure 9 of +ETS 300 231, lsb first transmitted. + + + V4L2_SLICED_CAPTION_525 + 0x1000 + + NTSC line 21, 284 (second field 21) + Two bytes in transmission order, including parity +bit, lsb first transmitted. + + + V4L2_SLICED_WSS_625 + 0x4000 + , + PAL/SECAM line 23 + +Byte 0 1 + msb lsb msb lsb + Bit 7 6 5 4 3 2 1 0 x x 13 12 11 10 9 + + + + V4L2_SLICED_VBI_525 + 0x1000 + Set of services applicable to 525 +line systems. + + + V4L2_SLICED_VBI_625 + 0x4401 + Set of services applicable to 625 +line systems. + + + +
+ + Drivers may return an &EINVAL; when applications attempt to +read or write data without prior format negotiation, after switching +the video standard (which may invalidate the negotiated VBI +parameters) and after switching the video input (which may change the +video standard as a side effect). The &VIDIOC-S-FMT; ioctl may return +an &EBUSY; when applications attempt to change the format while i/o is +in progress (between a &VIDIOC-STREAMON; and &VIDIOC-STREAMOFF; call, +and after the first &func-read; or &func-write; call). +
+ +
+ Reading and writing sliced VBI data + + A single &func-read; or &func-write; call must pass all data +belonging to one video frame. That is an array of +v4l2_sliced_vbi_data structures with one or +more elements and a total size not exceeding +io_size bytes. Likewise in streaming I/O +mode one buffer of io_size bytes must +contain data of one video frame. The id of +unused v4l2_sliced_vbi_data elements must be +zero. + + + struct +<structname>v4l2_sliced_vbi_data</structname> + + &cs-def; + + + __u32 + id + A flag from +identifying the type of data in this packet. Only a single bit must be +set. When the id of a captured packet is +zero, the packet is empty and the contents of other fields are +undefined. Applications shall ignore empty packets. When the +id of a packet for output is zero the +contents of the data field are undefined +and the driver must no longer insert data on the requested +field and +line. + + + __u32 + field + The video field number this data has been captured +from, or shall be inserted at. 0 for the first +field, 1 for the second field. + + + __u32 + line + The field (as opposed to frame) line number this +data has been captured from, or shall be inserted at. See and for valid +values. Sliced VBI capture devices can set the line number of all +packets to 0 if the hardware cannot reliably +identify scan lines. The field number must always be valid. + + + __u32 + reserved + This field is reserved for future extensions. +Applications and drivers must set it to zero. + + + __u8 + data[48] + The packet payload. See for the contents and number of +bytes passed for each data type. The contents of padding bytes at the +end of this array are undefined, drivers and applications shall ignore +them. + + + +
+ + Packets are always passed in ascending line number order, +without duplicate line numbers. The &func-write; function and the +&VIDIOC-QBUF; ioctl must return an &EINVAL; when applications violate +this rule. They must also return an &EINVAL; when applications pass an +incorrect field or line number, or a combination of +field, line and +id which has not been negotiated with the +&VIDIOC-G-FMT; or &VIDIOC-S-FMT; ioctl. When the line numbers are +unknown the driver must pass the packets in transmitted order. The +driver can insert empty packets with id set +to zero anywhere in the packet array. + + To assure synchronization and to distinguish from frame +dropping, when a captured frame does not carry any of the requested +data services drivers must pass one or more empty packets. When an +application fails to pass VBI data in time for output, the driver +must output the last VPS and WSS packet again, and disable the output +of Closed Caption and Teletext data, or output data which is ignored +by Closed Caption and Teletext decoders. + + A sliced VBI device may support read/write and/or streaming (memory mapping and/or user +pointer) I/O. The latter bears the possibility of synchronizing +video and VBI data by using buffer timestamps. + +
+ +
+ Sliced VBI Data in MPEG Streams + + If a device can produce an MPEG output stream, it may be +capable of providing negotiated sliced VBI +services as data embedded in the MPEG stream. Users or +applications control this sliced VBI data insertion with the V4L2_CID_MPEG_STREAM_VBI_FMT +control. + + If the driver does not provide the V4L2_CID_MPEG_STREAM_VBI_FMT +control, or only allows that control to be set to +V4L2_MPEG_STREAM_VBI_FMT_NONE, then the device +cannot embed sliced VBI data in the MPEG stream. + + The +V4L2_CID_MPEG_STREAM_VBI_FMT control does not implicitly set +the device driver to capture nor cease capturing sliced VBI data. The +control only indicates to embed sliced VBI data in the MPEG stream, if +an application has negotiated sliced VBI service be captured. + + It may also be the case that a device can embed sliced VBI +data in only certain types of MPEG streams: for example in an MPEG-2 +PS but not an MPEG-2 TS. In this situation, if sliced VBI data +insertion is requested, the sliced VBI data will be embedded in MPEG +stream types when supported, and silently omitted from MPEG stream +types where sliced VBI data insertion is not supported by the device. + + + The following subsections specify the format of the +embedded sliced VBI data. + +
+ MPEG Stream Embedded, Sliced VBI Data Format: NONE + The +V4L2_MPEG_STREAM_VBI_FMT_NONE embedded sliced VBI +format shall be interpreted by drivers as a control to cease +embedding sliced VBI data in MPEG streams. Neither the device nor +driver shall insert "empty" embedded sliced VBI data packets in the +MPEG stream when this format is set. No MPEG stream data structures +are specified for this format. +
+ +
+ MPEG Stream Embedded, Sliced VBI Data Format: IVTV + The +V4L2_MPEG_STREAM_VBI_FMT_IVTV embedded sliced VBI +format, when supported, indicates to the driver to embed up to 36 +lines of sliced VBI data per frame in an MPEG-2 Private +Stream 1 PES packet encapsulated in an MPEG-2 +Program Pack in the MPEG stream. + + Historical context: This format +specification originates from a custom, embedded, sliced VBI data +format used by the ivtv driver. This format +has already been informally specified in the kernel sources in the +file Documentation/video4linux/cx2341x/README.vbi +. The maximum size of the payload and other aspects of this format +are driven by the CX23415 MPEG decoder's capabilities and limitations +with respect to extracting, decoding, and displaying sliced VBI data +embedded within an MPEG stream. + + This format's use is not exclusive to +the ivtv driver nor +exclusive to CX2341x devices, as the sliced VBI data packet insertion +into the MPEG stream is implemented in driver software. At least the +cx18 driver provides sliced VBI data insertion +into an MPEG-2 PS in this format as well. + + The following definitions specify the payload of the +MPEG-2 Private Stream 1 PES packets that contain +sliced VBI data when +V4L2_MPEG_STREAM_VBI_FMT_IVTV is set. +(The MPEG-2 Private Stream 1 PES packet header +and encapsulating MPEG-2 Program Pack header are +not detailed here. Please refer to the MPEG-2 specifications for +details on those packet headers.) + + The payload of the MPEG-2 Private Stream 1 PES + packets that contain sliced VBI data is specified by +&v4l2-mpeg-vbi-fmt-ivtv;. The payload is variable +length, depending on the actual number of lines of sliced VBI data +present in a video frame. The payload may be padded at the end with +unspecified fill bytes to align the end of the payload to a 4-byte +boundary. The payload shall never exceed 1552 bytes (2 fields with +18 lines/field with 43 bytes of data/line and a 4 byte magic number). + + + + struct <structname>v4l2_mpeg_vbi_fmt_ivtv</structname> + + + &cs-ustr; + + + __u8 + magic[4] + + A "magic" constant from that indicates +this is a valid sliced VBI data payload and also indicates which +member of the anonymous union, itv0 or +ITV0, to use for the payload data. + + + union + (anonymous) + + + + struct + v4l2_mpeg_vbi_itv0 + + itv0 + The primary form of the sliced VBI data payload +that contains anywhere from 1 to 35 lines of sliced VBI data. +Line masks are provided in this form of the payload indicating +which VBI lines are provided. + + + + struct + v4l2_mpeg_vbi_ITV0 + + ITV0 + An alternate form of the sliced VBI data payload +used when 36 lines of sliced VBI data are present. No line masks are +provided in this form of the payload; all valid line mask bits are +implcitly set. + + + +
+ + + Magic Constants for &v4l2-mpeg-vbi-fmt-ivtv; + <structfield>magic</structfield> field + + &cs-def; + + + Defined Symbol + Value + Description + + + + + V4L2_MPEG_VBI_IVTV_MAGIC0 + + "itv0" + Indicates the itv0 +member of the union in &v4l2-mpeg-vbi-fmt-ivtv; is valid. + + + V4L2_MPEG_VBI_IVTV_MAGIC1 + + "ITV0" + Indicates the ITV0 +member of the union in &v4l2-mpeg-vbi-fmt-ivtv; is valid and +that 36 lines of sliced VBI data are present. + + + +
+ + + struct <structname>v4l2_mpeg_vbi_itv0</structname> + + + &cs-str; + + + __le32 + linemask[2] + Bitmasks indicating the VBI service lines +present. These linemask values are stored +in little endian byte order in the MPEG stream. Some reference +linemask bit positions with their +corresponding VBI line number and video field are given below. +b0 indicates the least significant bit of a +linemask value: +linemask[0] b0: line 6 first field +linemask[0] b17: line 23 first field +linemask[0] b18: line 6 second field +linemask[0] b31: line 19 second field +linemask[1] b0: line 20 second field +linemask[1] b3: line 23 second field +linemask[1] b4-b31: unused and set to 0 + + + struct + v4l2_mpeg_vbi_itv0_line + + line[35] + This is a variable length array that holds from 1 +to 35 lines of sliced VBI data. The sliced VBI data lines present +correspond to the bits set in the linemask +array, starting from b0 of +linemask[0] up through b31 of +linemask[0], and from b0 + of linemask[1] up through b +3 of linemask[1]. +line[0] corresponds to the first bit +found set in the linemask array, +line[1] corresponds to the second bit +found set in the linemask array, etc. +If no linemask array bits are set, then +line[0] may contain one line of +unspecified data that should be ignored by applications. + + + +
+ + + struct <structname>v4l2_mpeg_vbi_ITV0</structname> + + + &cs-str; + + + struct + v4l2_mpeg_vbi_itv0_line + + line[36] + A fixed length array of 36 lines of sliced VBI +data. line[0] through line +[17] correspond to lines 6 through 23 of the +first field. line[18] through +line[35] corresponds to lines 6 +through 23 of the second field. + + + +
+ + + struct <structname>v4l2_mpeg_vbi_itv0_line</structname> + + + &cs-str; + + + __u8 + id + A line identifier value from + that indicates +the type of sliced VBI data stored on this line. + + + __u8 + data[42] + The sliced VBI data for the line. + + + +
+ + + Line Identifiers for struct <link + linkend="v4l2-mpeg-vbi-itv0-line"><structname> +v4l2_mpeg_vbi_itv0_line</structname></link> <structfield>id +</structfield> field + + &cs-def; + + + Defined Symbol + Value + Description + + + + + V4L2_MPEG_VBI_IVTV_TELETEXT_B + + 1 + Refer to +Sliced VBI services for a description of the line payload. + + + V4L2_MPEG_VBI_IVTV_CAPTION_525 + + 4 + Refer to +Sliced VBI services for a description of the line payload. + + + V4L2_MPEG_VBI_IVTV_WSS_625 + + 5 + Refer to +Sliced VBI services for a description of the line payload. + + + V4L2_MPEG_VBI_IVTV_VPS + + 7 + Refer to +Sliced VBI services for a description of the line payload. + + + +
+ +
+
+ + + diff --git a/Documentation/DocBook/v4l/dev-teletext.xml b/Documentation/DocBook/v4l/dev-teletext.xml new file mode 100644 index 000000000000..76184e8ed618 --- /dev/null +++ b/Documentation/DocBook/v4l/dev-teletext.xml @@ -0,0 +1,40 @@ + Teletext Interface + + This interface aims at devices receiving and demodulating +Teletext data [, ], evaluating the +Teletext packages and storing formatted pages in cache memory. Such +devices are usually implemented as microcontrollers with serial +interface (I2C) and can be found on older +TV cards, dedicated Teletext decoding cards and home-brew devices +connected to the PC parallel port. + + The Teletext API was designed by Martin Buck. It is defined in +the kernel header file linux/videotext.h, the +specification is available from +ftp://ftp.gwdg.de/pub/linux/misc/videotext/. (Videotext is the name of +the German public television Teletext service.) Conventional character +device file names are /dev/vtx and +/dev/vttuner, with device number 83, 0 and 83, 16 +respectively. A similar interface exists for the Philips SAA5249 +Teletext decoder [specification?] with character device file names +/dev/tlkN, device number 102, N. + + Eventually the Teletext API was integrated into the V4L API +with character device file names /dev/vtx0 to +/dev/vtx31, device major number 81, minor numbers +192 to 223. For reference the V4L Teletext API specification is +reproduced here in full: "Teletext interfaces talk the existing VTX +API." Teletext devices with major number 83 and 102 will be removed in +Linux 2.6. + + There are no plans to replace the Teletext API or to integrate +it into V4L2. Please write to the linux-media mailing list: &v4l-ml; +when the need arises. + + diff --git a/Documentation/DocBook/v4l/driver.xml b/Documentation/DocBook/v4l/driver.xml new file mode 100644 index 000000000000..1f7eea5c4ec3 --- /dev/null +++ b/Documentation/DocBook/v4l/driver.xml @@ -0,0 +1,208 @@ + V4L2 Driver Programming + + + + to do + + + diff --git a/Documentation/DocBook/v4l/fdl-appendix.xml b/Documentation/DocBook/v4l/fdl-appendix.xml new file mode 100644 index 000000000000..b6ce50dbe492 --- /dev/null +++ b/Documentation/DocBook/v4l/fdl-appendix.xml @@ -0,0 +1,671 @@ + + + + + + Version 1.1, March 2000 + + + 2000Free Software Foundation, Inc. + + + +
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If you have no + Front-Cover Texts, write + no Front-Cover Texts instead of + Front-Cover Texts being LIST; likewise for Back-Cover Texts. + + + + If your document contains nontrivial examples of program code, + we recommend releasing these examples in parallel under your + choice of free software license, such as the GNU General Public + License, to permit their use in free software. + + + + + + + + + diff --git a/Documentation/DocBook/v4l/fieldseq_bt.gif b/Documentation/DocBook/v4l/fieldseq_bt.gif new file mode 100644 index 000000000000..60e8569a76c9 Binary files /dev/null and b/Documentation/DocBook/v4l/fieldseq_bt.gif differ diff --git a/Documentation/DocBook/v4l/fieldseq_bt.pdf b/Documentation/DocBook/v4l/fieldseq_bt.pdf new file mode 100644 index 000000000000..26598b23f80d Binary files /dev/null and b/Documentation/DocBook/v4l/fieldseq_bt.pdf differ diff --git a/Documentation/DocBook/v4l/fieldseq_tb.gif b/Documentation/DocBook/v4l/fieldseq_tb.gif new file mode 100644 index 000000000000..718492f1cfc7 Binary files /dev/null and b/Documentation/DocBook/v4l/fieldseq_tb.gif differ diff --git a/Documentation/DocBook/v4l/fieldseq_tb.pdf b/Documentation/DocBook/v4l/fieldseq_tb.pdf new file mode 100644 index 000000000000..4965b22ddb3a Binary files /dev/null and b/Documentation/DocBook/v4l/fieldseq_tb.pdf differ diff --git a/Documentation/DocBook/v4l/func-close.xml b/Documentation/DocBook/v4l/func-close.xml new file mode 100644 index 000000000000..dfb41cbbbec3 --- /dev/null +++ b/Documentation/DocBook/v4l/func-close.xml @@ -0,0 +1,70 @@ + + + V4L2 close() + &manvol; + + + + v4l2-close + Close a V4L2 device + + + + + #include <unistd.h> + + int close + int fd + + + + + + Arguments + + + + fd + + &fd; + + + + + + + Description + + Closes the device. Any I/O in progress is terminated and +resources associated with the file descriptor are freed. However data +format parameters, current input or output, control values or other +properties remain unchanged. + + + + Return Value + + The function returns 0 on +success, -1 on failure and the +errno is set appropriately. Possible error +codes: + + + + EBADF + + fd is not a valid open file +descriptor. + + + + + + + diff --git a/Documentation/DocBook/v4l/func-ioctl.xml b/Documentation/DocBook/v4l/func-ioctl.xml new file mode 100644 index 000000000000..00f9690e1c28 --- /dev/null +++ b/Documentation/DocBook/v4l/func-ioctl.xml @@ -0,0 +1,146 @@ + + + V4L2 ioctl() + &manvol; + + + + v4l2-ioctl + Program a V4L2 device + + + + + #include <sys/ioctl.h> + + int ioctl + int fd + int request + void *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + V4L2 ioctl request code as defined in the videodev.h header file, for example +VIDIOC_QUERYCAP. + + + + argp + + Pointer to a function parameter, usually a structure. + + + + + + + Description + + The ioctl() function is used to program +V4L2 devices. The argument fd must be an open +file descriptor. An ioctl request has encoded +in it whether the argument is an input, output or read/write +parameter, and the size of the argument argp in +bytes. Macros and defines specifying V4L2 ioctl requests are located +in the videodev.h header file. +Applications should use their own copy, not include the version in the +kernel sources on the system they compile on. All V4L2 ioctl requests, +their respective function and parameters are specified in . + + + + Return Value + + On success the ioctl() function returns +0 and does not reset the +errno variable. On failure +-1 is returned, when the ioctl takes an +output or read/write parameter it remains unmodified, and the +errno variable is set appropriately. See below for +possible error codes. Generic errors like EBADF +or EFAULT are not listed in the sections +discussing individual ioctl requests. + Note ioctls may return undefined error codes. Since errors +may have side effects such as a driver reset applications should +abort on unexpected errors. + + + + EBADF + + fd is not a valid open file +descriptor. + + + + EBUSY + + The property cannot be changed right now. Typically +this error code is returned when I/O is in progress or the driver +supports multiple opens and another process locked the property. + + + + EFAULT + + argp references an inaccessible +memory area. + + + + ENOTTY + + fd is not associated with a +character special device. + + + + EINVAL + + The request or the data pointed +to by argp is not valid. This is a very common +error code, see the individual ioctl requests listed in for actual causes. + + + + ENOMEM + + Not enough physical or virtual memory was available to +complete the request. + + + + ERANGE + + The application attempted to set a control with the +&VIDIOC-S-CTRL; ioctl to a value which is out of bounds. + + + + + + + diff --git a/Documentation/DocBook/v4l/func-mmap.xml b/Documentation/DocBook/v4l/func-mmap.xml new file mode 100644 index 000000000000..2e2fc3933aea --- /dev/null +++ b/Documentation/DocBook/v4l/func-mmap.xml @@ -0,0 +1,185 @@ + + + V4L2 mmap() + &manvol; + + + + v4l2-mmap + Map device memory into application address space + + + + + +#include <unistd.h> +#include <sys/mman.h> + + void *mmap + void *start + size_t length + int prot + int flags + int fd + off_t offset + + + + + + Arguments + + + start + + Map the buffer to this address in the +application's address space. When the MAP_FIXED +flag is specified, start must be a multiple of the +pagesize and mmap will fail when the specified address +cannot be used. Use of this option is discouraged; applications should +just specify a NULL pointer here. + + + + length + + Length of the memory area to map. This must be the +same value as returned by the driver in the &v4l2-buffer; +length field. + + + + prot + + The prot argument describes the +desired memory protection. Regardless of the device type and the +direction of data exchange it should be set to +PROT_READ | PROT_WRITE, +permitting read and write access to image buffers. Drivers should +support at least this combination of flags. Note the Linux +video-buf kernel module, which is used by the +bttv, saa7134, saa7146, cx88 and vivi driver supports only +PROT_READ | PROT_WRITE. When +the driver does not support the desired protection the +mmap() function fails. + Note device memory accesses (⪚ the memory on a +graphics card with video capturing hardware) may incur a performance +penalty compared to main memory accesses, or reads may be +significantly slower than writes or vice versa. Other I/O methods may +be more efficient in this case. + + + + flags + + The flags parameter +specifies the type of the mapped object, mapping options and whether +modifications made to the mapped copy of the page are private to the +process or are to be shared with other references. + MAP_FIXED requests that the +driver selects no other address than the one specified. If the +specified address cannot be used, mmap() will fail. If +MAP_FIXED is specified, +start must be a multiple of the pagesize. Use +of this option is discouraged. + One of the MAP_SHARED or +MAP_PRIVATE flags must be set. +MAP_SHARED allows applications to share the +mapped memory with other (⪚ child-) processes. Note the Linux +video-buf module which is used by the bttv, +saa7134, saa7146, cx88 and vivi driver supports only +MAP_SHARED. MAP_PRIVATE +requests copy-on-write semantics. V4L2 applications should not set the +MAP_PRIVATE, MAP_DENYWRITE, +MAP_EXECUTABLE or MAP_ANON +flag. + + + + fd + + &fd; + + + + offset + + Offset of the buffer in device memory. This must be the +same value as returned by the driver in the &v4l2-buffer; +m union offset field. + + + + + + + Description + + The mmap() function asks to map +length bytes starting at +offset in the memory of the device specified by +fd into the application address space, +preferably at address start. This latter +address is a hint only, and is usually specified as 0. + + Suitable length and offset parameters are queried with the +&VIDIOC-QUERYBUF; ioctl. Buffers must be allocated with the +&VIDIOC-REQBUFS; ioctl before they can be queried. + + To unmap buffers the &func-munmap; function is used. + + + + Return Value + + On success mmap() returns a pointer to +the mapped buffer. On error MAP_FAILED (-1) is +returned, and the errno variable is set +appropriately. Possible error codes are: + + + + EBADF + + fd is not a valid file +descriptor. + + + + EACCES + + fd is +not open for reading and writing. + + + + EINVAL + + The start or +length or offset are not +suitable. (E. g. they are too large, or not aligned on a +PAGESIZE boundary.) + The flags or +prot value is not supported. + No buffers have been allocated with the +&VIDIOC-REQBUFS; ioctl. + + + + ENOMEM + + Not enough physical or virtual memory was available to +complete the request. + + + + + + + diff --git a/Documentation/DocBook/v4l/func-munmap.xml b/Documentation/DocBook/v4l/func-munmap.xml new file mode 100644 index 000000000000..502ed49323b0 --- /dev/null +++ b/Documentation/DocBook/v4l/func-munmap.xml @@ -0,0 +1,83 @@ + + + V4L2 munmap() + &manvol; + + + + v4l2-munmap + Unmap device memory + + + + + +#include <unistd.h> +#include <sys/mman.h> + + int munmap + void *start + size_t length + + + + + Arguments + + + start + + Address of the mapped buffer as returned by the +&func-mmap; function. + + + + length + + Length of the mapped buffer. This must be the same +value as given to mmap() and returned by the +driver in the &v4l2-buffer; length +field. + + + + + + + Description + + Unmaps a previously with the &func-mmap; function mapped +buffer and frees it, if possible. + + + + Return Value + + On success munmap() returns 0, on +failure -1 and the errno variable is set +appropriately: + + + + EINVAL + + The start or +length is incorrect, or no buffers have been +mapped yet. + + + + + + + diff --git a/Documentation/DocBook/v4l/func-open.xml b/Documentation/DocBook/v4l/func-open.xml new file mode 100644 index 000000000000..7595d07a8c72 --- /dev/null +++ b/Documentation/DocBook/v4l/func-open.xml @@ -0,0 +1,121 @@ + + + V4L2 open() + &manvol; + + + + v4l2-open + Open a V4L2 device + + + + + #include <fcntl.h> + + int open + const char *device_name + int flags + + + + + + Arguments + + + + device_name + + Device to be opened. + + + + flags + + Open flags. Access mode must be +O_RDWR. This is just a technicality, input devices +still support only reading and output devices only writing. + When the O_NONBLOCK flag is +given, the read() function and the &VIDIOC-DQBUF; ioctl will return +the &EAGAIN; when no data is available or no buffer is in the driver +outgoing queue, otherwise these functions block until data becomes +available. All V4L2 drivers exchanging data with applications must +support the O_NONBLOCK flag. + Other flags have no effect. + + + + + + Description + + To open a V4L2 device applications call +open() with the desired device name. This +function has no side effects; all data format parameters, current +input or output, control values or other properties remain unchanged. +At the first open() call after loading the driver +they will be reset to default values, drivers are never in an +undefined state. + + + Return Value + + On success open returns the new file +descriptor. On error -1 is returned, and the errno +variable is set appropriately. Possible error codes are: + + + + EACCES + + The caller has no permission to access the +device. + + + + EBUSY + + The driver does not support multiple opens and the +device is already in use. + + + + ENXIO + + No device corresponding to this device special file +exists. + + + + ENOMEM + + Not enough kernel memory was available to complete the +request. + + + + EMFILE + + The process already has the maximum number of +files open. + + + + ENFILE + + The limit on the total number of files open on the +system has been reached. + + + + + + + diff --git a/Documentation/DocBook/v4l/func-poll.xml b/Documentation/DocBook/v4l/func-poll.xml new file mode 100644 index 000000000000..ec3c718f5963 --- /dev/null +++ b/Documentation/DocBook/v4l/func-poll.xml @@ -0,0 +1,127 @@ + + + V4L2 poll() + &manvol; + + + + v4l2-poll + Wait for some event on a file descriptor + + + + + #include <sys/poll.h> + + int poll + struct pollfd *ufds + unsigned int nfds + int timeout + + + + + + Description + + With the poll() function applications +can suspend execution until the driver has captured data or is ready +to accept data for output. + + When streaming I/O has been negotiated this function waits +until a buffer has been filled or displayed and can be dequeued with +the &VIDIOC-DQBUF; ioctl. When buffers are already in the outgoing +queue of the driver the function returns immediately. + + On success poll() returns the number of +file descriptors that have been selected (that is, file descriptors +for which the revents field of the +respective pollfd structure is non-zero). +Capture devices set the POLLIN and +POLLRDNORM flags in the +revents field, output devices the +POLLOUT and POLLWRNORM +flags. When the function timed out it returns a value of zero, on +failure it returns -1 and the +errno variable is set appropriately. When the +application did not call &VIDIOC-QBUF; or &VIDIOC-STREAMON; yet the +poll() function succeeds, but sets the +POLLERR flag in the +revents field. + + When use of the read() function has +been negotiated and the driver does not capture yet, the +poll function starts capturing. When that fails +it returns a POLLERR as above. Otherwise it waits +until data has been captured and can be read. When the driver captures +continuously (as opposed to, for example, still images) the function +may return immediately. + + When use of the write() function has +been negotiated the poll function just waits +until the driver is ready for a non-blocking +write() call. + + All drivers implementing the read() or +write() function or streaming I/O must also +support the poll() function. + + For more details see the +poll() manual page. + + + + Return Value + + On success, poll() returns the number +structures which have non-zero revents +fields, or zero if the call timed out. On error +-1 is returned, and the +errno variable is set appropriately: + + + + EBADF + + One or more of the ufds members +specify an invalid file descriptor. + + + + EBUSY + + The driver does not support multiple read or write +streams and the device is already in use. + + + + EFAULT + + ufds references an inaccessible +memory area. + + + + EINTR + + The call was interrupted by a signal. + + + + EINVAL + + The nfds argument is greater +than OPEN_MAX. + + + + + + + diff --git a/Documentation/DocBook/v4l/func-read.xml b/Documentation/DocBook/v4l/func-read.xml new file mode 100644 index 000000000000..a5089bf8873d --- /dev/null +++ b/Documentation/DocBook/v4l/func-read.xml @@ -0,0 +1,189 @@ + + + V4L2 read() + &manvol; + + + + v4l2-read + Read from a V4L2 device + + + + + #include <unistd.h> + + ssize_t read + int fd + void *buf + size_t count + + + + + + Arguments + + + + fd + + &fd; + + + + buf + + + + + + count + + + + + + + + + Description + + read() attempts to read up to +count bytes from file descriptor +fd into the buffer starting at +buf. The layout of the data in the buffer is +discussed in the respective device interface section, see ##. If count is zero, +read() returns zero and has no other results. If +count is greater than +SSIZE_MAX, the result is unspecified. Regardless +of the count value each +read() call will provide at most one frame (two +fields) worth of data. + + By default read() blocks until data +becomes available. When the O_NONBLOCK flag was +given to the &func-open; function it +returns immediately with an &EAGAIN; when no data is available. The +&func-select; or &func-poll; functions +can always be used to suspend execution until data becomes available. All +drivers supporting the read() function must also +support select() and +poll(). + + Drivers can implement read functionality in different +ways, using a single or multiple buffers and discarding the oldest or +newest frames once the internal buffers are filled. + + read() never returns a "snapshot" of a +buffer being filled. Using a single buffer the driver will stop +capturing when the application starts reading the buffer until the +read is finished. Thus only the period of the vertical blanking +interval is available for reading, or the capture rate must fall below +the nominal frame rate of the video standard. + +The behavior of +read() when called during the active picture +period or the vertical blanking separating the top and bottom field +depends on the discarding policy. A driver discarding the oldest +frames keeps capturing into an internal buffer, continuously +overwriting the previously, not read frame, and returns the frame +being received at the time of the read() call as +soon as it is complete. + + A driver discarding the newest frames stops capturing until +the next read() call. The frame being received at +read() time is discarded, returning the following +frame instead. Again this implies a reduction of the capture rate to +one half or less of the nominal frame rate. An example of this model +is the video read mode of the bttv driver, initiating a DMA to user +memory when read() is called and returning when +the DMA finished. + + In the multiple buffer model drivers maintain a ring of +internal buffers, automatically advancing to the next free buffer. +This allows continuous capturing when the application can empty the +buffers fast enough. Again, the behavior when the driver runs out of +free buffers depends on the discarding policy. + + Applications can get and set the number of buffers used +internally by the driver with the &VIDIOC-G-PARM; and &VIDIOC-S-PARM; +ioctls. They are optional, however. The discarding policy is not +reported and cannot be changed. For minimum requirements see . + + + + Return Value + + On success, the number of bytes read is returned. It is not +an error if this number is smaller than the number of bytes requested, +or the amount of data required for one frame. This may happen for +example because read() was interrupted by a +signal. On error, -1 is returned, and the errno +variable is set appropriately. In this case the next read will start +at the beginning of a new frame. Possible error codes are: + + + + EAGAIN + + Non-blocking I/O has been selected using +O_NONBLOCK and no data was immediately available for reading. + + + + EBADF + + fd is not a valid file +descriptor or is not open for reading, or the process already has the +maximum number of files open. + + + + EBUSY + + The driver does not support multiple read streams and the +device is already in use. + + + + EFAULT + + buf references an inaccessible +memory area. + + + + EINTR + + The call was interrupted by a signal before any +data was read. + + + + EIO + + I/O error. This indicates some hardware problem or a +failure to communicate with a remote device (USB camera etc.). + + + + EINVAL + + The read() function is not +supported by this driver, not on this device, or generally not on this +type of device. + + + + + + + diff --git a/Documentation/DocBook/v4l/func-select.xml b/Documentation/DocBook/v4l/func-select.xml new file mode 100644 index 000000000000..b6713623181f --- /dev/null +++ b/Documentation/DocBook/v4l/func-select.xml @@ -0,0 +1,138 @@ + + + V4L2 select() + &manvol; + + + + v4l2-select + Synchronous I/O multiplexing + + + + + +#include <sys/time.h> +#include <sys/types.h> +#include <unistd.h> + + int select + int nfds + fd_set *readfds + fd_set *writefds + fd_set *exceptfds + struct timeval *timeout + + + + + + Description + + With the select() function applications +can suspend execution until the driver has captured data or is ready +to accept data for output. + + When streaming I/O has been negotiated this function waits +until a buffer has been filled or displayed and can be dequeued with +the &VIDIOC-DQBUF; ioctl. When buffers are already in the outgoing +queue of the driver the function returns immediately. + + On success select() returns the total +number of bits set in the fd_sets. When the +function timed out it returns a value of zero. On failure it returns +-1 and the errno +variable is set appropriately. When the application did not call +&VIDIOC-QBUF; or &VIDIOC-STREAMON; yet the +select() function succeeds, setting the bit of +the file descriptor in readfds or +writefds, but subsequent &VIDIOC-DQBUF; calls +will fail.The Linux kernel implements +select() like the &func-poll; function, but +select() cannot return a +POLLERR. + + + When use of the read() function has +been negotiated and the driver does not capture yet, the +select() function starts capturing. When that +fails, select() returns successful and a +subsequent read() call, which also attempts to +start capturing, will return an appropriate error code. When the +driver captures continuously (as opposed to, for example, still +images) and data is already available the +select() function returns immediately. + + When use of the write() function has +been negotiated the select() function just waits +until the driver is ready for a non-blocking +write() call. + + All drivers implementing the read() or +write() function or streaming I/O must also +support the select() function. + + For more details see the select() +manual page. + + + + + Return Value + + On success, select() returns the number +of descriptors contained in the three returned descriptor sets, which +will be zero if the timeout expired. On error +-1 is returned, and the +errno variable is set appropriately; the sets and +timeout are undefined. Possible error codes +are: + + + + EBADF + + One or more of the file descriptor sets specified a +file descriptor that is not open. + + + + EBUSY + + The driver does not support multiple read or write +streams and the device is already in use. + + + + EFAULT + + The readfds, +writefds, exceptfds or +timeout pointer references an inaccessible memory +area. + + + + EINTR + + The call was interrupted by a signal. + + + + EINVAL + + The nfds argument is less than +zero or greater than FD_SETSIZE. + + + + + + + diff --git a/Documentation/DocBook/v4l/func-write.xml b/Documentation/DocBook/v4l/func-write.xml new file mode 100644 index 000000000000..2c09c09371c3 --- /dev/null +++ b/Documentation/DocBook/v4l/func-write.xml @@ -0,0 +1,136 @@ + + + V4L2 write() + &manvol; + + + + v4l2-write + Write to a V4L2 device + + + + + #include <unistd.h> + + ssize_t write + int fd + void *buf + size_t count + + + + + + Arguments + + + + fd + + &fd; + + + + buf + + + + + + count + + + + + + + + + Description + + write() writes up to +count bytes to the device referenced by the +file descriptor fd from the buffer starting at +buf. When the hardware outputs are not active +yet, this function enables them. When count is +zero, write() returns +0 without any other effect. + + When the application does not provide more data in time, the +previous video frame, raw VBI image, sliced VPS or WSS data is +displayed again. Sliced Teletext or Closed Caption data is not +repeated, the driver inserts a blank line instead. + + + + Return Value + + On success, the number of bytes written are returned. Zero +indicates nothing was written. On error, -1 +is returned, and the errno variable is set +appropriately. In this case the next write will start at the beginning +of a new frame. Possible error codes are: + + + + EAGAIN + + Non-blocking I/O has been selected using the O_NONBLOCK flag and no +buffer space was available to write the data immediately. + + + + EBADF + + fd is not a valid file +descriptor or is not open for writing. + + + + EBUSY + + The driver does not support multiple write streams and the +device is already in use. + + + + EFAULT + + buf references an inaccessible +memory area. + + + + EINTR + + The call was interrupted by a signal before any +data was written. + + + + EIO + + I/O error. This indicates some hardware problem. + + + + EINVAL + + The write() function is not +supported by this driver, not on this device, or generally not on this +type of device. + + + + + + + diff --git a/Documentation/DocBook/v4l/io.xml b/Documentation/DocBook/v4l/io.xml new file mode 100644 index 000000000000..f92f24323b2a --- /dev/null +++ b/Documentation/DocBook/v4l/io.xml @@ -0,0 +1,1073 @@ + Input/Output + + The V4L2 API defines several different methods to read from or +write to a device. All drivers exchanging data with applications must +support at least one of them. + + The classic I/O method using the read() +and write() function is automatically selected +after opening a V4L2 device. When the driver does not support this +method attempts to read or write will fail at any time. + + Other methods must be negotiated. To select the streaming I/O +method with memory mapped or user buffers applications call the +&VIDIOC-REQBUFS; ioctl. The asynchronous I/O method is not defined +yet. + + Video overlay can be considered another I/O method, although +the application does not directly receive the image data. It is +selected by initiating video overlay with the &VIDIOC-S-FMT; ioctl. +For more information see . + + Generally exactly one I/O method, including overlay, is +associated with each file descriptor. The only exceptions are +applications not exchanging data with a driver ("panel applications", +see ) and drivers permitting simultaneous video capturing +and overlay using the same file descriptor, for compatibility with V4L +and earlier versions of V4L2. + + VIDIOC_S_FMT and +VIDIOC_REQBUFS would permit this to some degree, +but for simplicity drivers need not support switching the I/O method +(after first switching away from read/write) other than by closing +and reopening the device. + + The following sections describe the various I/O methods in +more detail. + +
+ Read/Write + + Input and output devices support the +read() and write() function, +respectively, when the V4L2_CAP_READWRITE flag in +the capabilities field of &v4l2-capability; +returned by the &VIDIOC-QUERYCAP; ioctl is set. + + Drivers may need the CPU to copy the data, but they may also +support DMA to or from user memory, so this I/O method is not +necessarily less efficient than other methods merely exchanging buffer +pointers. It is considered inferior though because no meta-information +like frame counters or timestamps are passed. This information is +necessary to recognize frame dropping and to synchronize with other +data streams. However this is also the simplest I/O method, requiring +little or no setup to exchange data. It permits command line stunts +like this (the vidctrl tool is +fictitious): + + + +> vidctrl /dev/video --input=0 --format=YUYV --size=352x288 +> dd if=/dev/video of=myimage.422 bs=202752 count=1 + + + + To read from the device applications use the +&func-read; function, to write the &func-write; function. +Drivers must implement one I/O method if they +exchange data with applications, but it need not be this. + It would be desirable if applications could depend on +drivers supporting all I/O interfaces, but as much as the complex +memory mapping I/O can be inadequate for some devices we have no +reason to require this interface, which is most useful for simple +applications capturing still images. + When reading or writing is supported, the driver +must also support the &func-select; and &func-poll; +function. + At the driver level select() and +poll() are the same, and +select() is too important to be optional. + +
+ +
+ Streaming I/O (Memory Mapping) + + Input and output devices support this I/O method when the +V4L2_CAP_STREAMING flag in the +capabilities field of &v4l2-capability; +returned by the &VIDIOC-QUERYCAP; ioctl is set. There are two +streaming methods, to determine if the memory mapping flavor is +supported applications must call the &VIDIOC-REQBUFS; ioctl. + + Streaming is an I/O method where only pointers to buffers +are exchanged between application and driver, the data itself is not +copied. Memory mapping is primarily intended to map buffers in device +memory into the application's address space. Device memory can be for +example the video memory on a graphics card with a video capture +add-on. However, being the most efficient I/O method available for a +long time, many other drivers support streaming as well, allocating +buffers in DMA-able main memory. + + A driver can support many sets of buffers. Each set is +identified by a unique buffer type value. The sets are independent and +each set can hold a different type of data. To access different sets +at the same time different file descriptors must be used. + One could use one file descriptor and set the buffer +type field accordingly when calling &VIDIOC-QBUF; etc., but it makes +the select() function ambiguous. We also like the +clean approach of one file descriptor per logical stream. Video +overlay for example is also a logical stream, although the CPU is not +needed for continuous operation. + + + To allocate device buffers applications call the +&VIDIOC-REQBUFS; ioctl with the desired number of buffers and buffer +type, for example V4L2_BUF_TYPE_VIDEO_CAPTURE. +This ioctl can also be used to change the number of buffers or to free +the allocated memory, provided none of the buffers are still +mapped. + + Before applications can access the buffers they must map +them into their address space with the &func-mmap; function. The +location of the buffers in device memory can be determined with the +&VIDIOC-QUERYBUF; ioctl. The m.offset and +length returned in a &v4l2-buffer; are +passed as sixth and second parameter to the +mmap() function. The offset and length values +must not be modified. Remember the buffers are allocated in physical +memory, as opposed to virtual memory which can be swapped out to disk. +Applications should free the buffers as soon as possible with the +&func-munmap; function. + + + Mapping buffers + + +&v4l2-requestbuffers; reqbuf; +struct { + void *start; + size_t length; +} *buffers; +unsigned int i; + +memset (&reqbuf, 0, sizeof (reqbuf)); +reqbuf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; +reqbuf.memory = V4L2_MEMORY_MMAP; +reqbuf.count = 20; + +if (-1 == ioctl (fd, &VIDIOC-REQBUFS;, &reqbuf)) { + if (errno == EINVAL) + printf ("Video capturing or mmap-streaming is not supported\n"); + else + perror ("VIDIOC_REQBUFS"); + + exit (EXIT_FAILURE); +} + +/* We want at least five buffers. */ + +if (reqbuf.count < 5) { + /* You may need to free the buffers here. */ + printf ("Not enough buffer memory\n"); + exit (EXIT_FAILURE); +} + +buffers = calloc (reqbuf.count, sizeof (*buffers)); +assert (buffers != NULL); + +for (i = 0; i < reqbuf.count; i++) { + &v4l2-buffer; buffer; + + memset (&buffer, 0, sizeof (buffer)); + buffer.type = reqbuf.type; + buffer.memory = V4L2_MEMORY_MMAP; + buffer.index = i; + + if (-1 == ioctl (fd, &VIDIOC-QUERYBUF;, &buffer)) { + perror ("VIDIOC_QUERYBUF"); + exit (EXIT_FAILURE); + } + + buffers[i].length = buffer.length; /* remember for munmap() */ + + buffers[i].start = mmap (NULL, buffer.length, + PROT_READ | PROT_WRITE, /* recommended */ + MAP_SHARED, /* recommended */ + fd, buffer.m.offset); + + if (MAP_FAILED == buffers[i].start) { + /* If you do not exit here you should unmap() and free() + the buffers mapped so far. */ + perror ("mmap"); + exit (EXIT_FAILURE); + } +} + +/* Cleanup. */ + +for (i = 0; i < reqbuf.count; i++) + munmap (buffers[i].start, buffers[i].length); + + + + Conceptually streaming drivers maintain two buffer queues, an incoming +and an outgoing queue. They separate the synchronous capture or output +operation locked to a video clock from the application which is +subject to random disk or network delays and preemption by +other processes, thereby reducing the probability of data loss. +The queues are organized as FIFOs, buffers will be +output in the order enqueued in the incoming FIFO, and were +captured in the order dequeued from the outgoing FIFO. + + The driver may require a minimum number of buffers enqueued +at all times to function, apart of this no limit exists on the number +of buffers applications can enqueue in advance, or dequeue and +process. They can also enqueue in a different order than buffers have +been dequeued, and the driver can fill enqueued +empty buffers in any order. + Random enqueue order permits applications processing +images out of order (such as video codecs) to return buffers earlier, +reducing the probability of data loss. Random fill order allows +drivers to reuse buffers on a LIFO-basis, taking advantage of caches +holding scatter-gather lists and the like. + The index number of a buffer (&v4l2-buffer; +index) plays no role here, it only +identifies the buffer. + + Initially all mapped buffers are in dequeued state, +inaccessible by the driver. For capturing applications it is customary +to first enqueue all mapped buffers, then to start capturing and enter +the read loop. Here the application waits until a filled buffer can be +dequeued, and re-enqueues the buffer when the data is no longer +needed. Output applications fill and enqueue buffers, when enough +buffers are stacked up the output is started with +VIDIOC_STREAMON. In the write loop, when +the application runs out of free buffers, it must wait until an empty +buffer can be dequeued and reused. + + To enqueue and dequeue a buffer applications use the +&VIDIOC-QBUF; and &VIDIOC-DQBUF; ioctl. The status of a buffer being +mapped, enqueued, full or empty can be determined at any time using the +&VIDIOC-QUERYBUF; ioctl. Two methods exist to suspend execution of the +application until one or more buffers can be dequeued. By default +VIDIOC_DQBUF blocks when no buffer is in the +outgoing queue. When the O_NONBLOCK flag was +given to the &func-open; function, VIDIOC_DQBUF +returns immediately with an &EAGAIN; when no buffer is available. The +&func-select; or &func-poll; function are always available. + + To start and stop capturing or output applications call the +&VIDIOC-STREAMON; and &VIDIOC-STREAMOFF; ioctl. Note +VIDIOC_STREAMOFF removes all buffers from both +queues as a side effect. Since there is no notion of doing anything +"now" on a multitasking system, if an application needs to synchronize +with another event it should examine the &v4l2-buffer; +timestamp of captured buffers, or set the +field before enqueuing buffers for output. + + Drivers implementing memory mapping I/O must +support the VIDIOC_REQBUFS, +VIDIOC_QUERYBUF, +VIDIOC_QBUF, VIDIOC_DQBUF, +VIDIOC_STREAMON and +VIDIOC_STREAMOFF ioctl, the +mmap(), munmap(), +select() and poll() +function. + At the driver level select() and +poll() are the same, and +select() is too important to be optional. The +rest should be evident. + + + [capture example] + +
+ +
+ Streaming I/O (User Pointers) + + Input and output devices support this I/O method when the +V4L2_CAP_STREAMING flag in the +capabilities field of &v4l2-capability; +returned by the &VIDIOC-QUERYCAP; ioctl is set. If the particular user +pointer method (not only memory mapping) is supported must be +determined by calling the &VIDIOC-REQBUFS; ioctl. + + This I/O method combines advantages of the read/write and +memory mapping methods. Buffers are allocated by the application +itself, and can reside for example in virtual or shared memory. Only +pointers to data are exchanged, these pointers and meta-information +are passed in &v4l2-buffer;. The driver must be switched +into user pointer I/O mode by calling the &VIDIOC-REQBUFS; with the +desired buffer type. No buffers are allocated beforehands, +consequently they are not indexed and cannot be queried like mapped +buffers with the VIDIOC_QUERYBUF ioctl. + + + Initiating streaming I/O with user pointers + + +&v4l2-requestbuffers; reqbuf; + +memset (&reqbuf, 0, sizeof (reqbuf)); +reqbuf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; +reqbuf.memory = V4L2_MEMORY_USERPTR; + +if (ioctl (fd, &VIDIOC-REQBUFS;, &reqbuf) == -1) { + if (errno == EINVAL) + printf ("Video capturing or user pointer streaming is not supported\n"); + else + perror ("VIDIOC_REQBUFS"); + + exit (EXIT_FAILURE); +} + + + + Buffer addresses and sizes are passed on the fly with the +&VIDIOC-QBUF; ioctl. Although buffers are commonly cycled, +applications can pass different addresses and sizes at each +VIDIOC_QBUF call. If required by the hardware the +driver swaps memory pages within physical memory to create a +continuous area of memory. This happens transparently to the +application in the virtual memory subsystem of the kernel. When buffer +pages have been swapped out to disk they are brought back and finally +locked in physical memory for DMA. + We expect that frequently used buffers are typically not +swapped out. Anyway, the process of swapping, locking or generating +scatter-gather lists may be time consuming. The delay can be masked by +the depth of the incoming buffer queue, and perhaps by maintaining +caches assuming a buffer will be soon enqueued again. On the other +hand, to optimize memory usage drivers can limit the number of buffers +locked in advance and recycle the most recently used buffers first. Of +course, the pages of empty buffers in the incoming queue need not be +saved to disk. Output buffers must be saved on the incoming and +outgoing queue because an application may share them with other +processes. + + + Filled or displayed buffers are dequeued with the +&VIDIOC-DQBUF; ioctl. The driver can unlock the memory pages at any +time between the completion of the DMA and this ioctl. The memory is +also unlocked when &VIDIOC-STREAMOFF; is called, &VIDIOC-REQBUFS;, or +when the device is closed. Applications must take care not to free +buffers without dequeuing. For once, the buffers remain locked until +further, wasting physical memory. Second the driver will not be +notified when the memory is returned to the application's free list +and subsequently reused for other purposes, possibly completing the +requested DMA and overwriting valuable data. + + For capturing applications it is customary to enqueue a +number of empty buffers, to start capturing and enter the read loop. +Here the application waits until a filled buffer can be dequeued, and +re-enqueues the buffer when the data is no longer needed. Output +applications fill and enqueue buffers, when enough buffers are stacked +up output is started. In the write loop, when the application +runs out of free buffers it must wait until an empty buffer can be +dequeued and reused. Two methods exist to suspend execution of the +application until one or more buffers can be dequeued. By default +VIDIOC_DQBUF blocks when no buffer is in the +outgoing queue. When the O_NONBLOCK flag was +given to the &func-open; function, VIDIOC_DQBUF +returns immediately with an &EAGAIN; when no buffer is available. The +&func-select; or &func-poll; function are always available. + + To start and stop capturing or output applications call the +&VIDIOC-STREAMON; and &VIDIOC-STREAMOFF; ioctl. Note +VIDIOC_STREAMOFF removes all buffers from both +queues and unlocks all buffers as a side effect. Since there is no +notion of doing anything "now" on a multitasking system, if an +application needs to synchronize with another event it should examine +the &v4l2-buffer; timestamp of captured +buffers, or set the field before enqueuing buffers for output. + + Drivers implementing user pointer I/O must +support the VIDIOC_REQBUFS, +VIDIOC_QBUF, VIDIOC_DQBUF, +VIDIOC_STREAMON and +VIDIOC_STREAMOFF ioctl, the +select() and poll() function. + At the driver level select() and +poll() are the same, and +select() is too important to be optional. The +rest should be evident. + +
+ +
+ Asynchronous I/O + + This method is not defined yet. +
+ +
+ Buffers + + A buffer contains data exchanged by application and +driver using one of the Streaming I/O methods. Only pointers to +buffers are exchanged, the data itself is not copied. These pointers, +together with meta-information like timestamps or field parity, are +stored in a struct v4l2_buffer, argument to +the &VIDIOC-QUERYBUF;, &VIDIOC-QBUF; and &VIDIOC-DQBUF; ioctl. + + Nominally timestamps refer to the first data byte transmitted. +In practice however the wide range of hardware covered by the V4L2 API +limits timestamp accuracy. Often an interrupt routine will +sample the system clock shortly after the field or frame was stored +completely in memory. So applications must expect a constant +difference up to one field or frame period plus a small (few scan +lines) random error. The delay and error can be much +larger due to compression or transmission over an external bus when +the frames are not properly stamped by the sender. This is frequently +the case with USB cameras. Here timestamps refer to the instant the +field or frame was received by the driver, not the capture time. These +devices identify by not enumerating any video standards, see . + + Similar limitations apply to output timestamps. Typically +the video hardware locks to a clock controlling the video timing, the +horizontal and vertical synchronization pulses. At some point in the +line sequence, possibly the vertical blanking, an interrupt routine +samples the system clock, compares against the timestamp and programs +the hardware to repeat the previous field or frame, or to display the +buffer contents. + + Apart of limitations of the video device and natural +inaccuracies of all clocks, it should be noted system time itself is +not perfectly stable. It can be affected by power saving cycles, +warped to insert leap seconds, or even turned back or forth by the +system administrator affecting long term measurements. + Since no other Linux multimedia +API supports unadjusted time it would be foolish to introduce here. We +must use a universally supported clock to synchronize different media, +hence time of day. + + + + struct <structname>v4l2_buffer</structname> + + &cs-ustr; + + + __u32 + index + + Number of the buffer, set by the application. This +field is only used for memory mapping I/O +and can range from zero to the number of buffers allocated +with the &VIDIOC-REQBUFS; ioctl (&v4l2-requestbuffers; count) minus one. + + + &v4l2-buf-type; + type + + Type of the buffer, same as &v4l2-format; +type or &v4l2-requestbuffers; +type, set by the application. + + + __u32 + bytesused + + The number of bytes occupied by the data in the +buffer. It depends on the negotiated data format and may change with +each buffer for compressed variable size data like JPEG images. +Drivers must set this field when type +refers to an input stream, applications when an output stream. + + + __u32 + flags + + Flags set by the application or driver, see . + + + &v4l2-field; + field + + Indicates the field order of the image in the +buffer, see . This field is not used when +the buffer contains VBI data. Drivers must set it when +type refers to an input stream, +applications when an output stream. + + + struct timeval + timestamp + + For input streams this is the +system time (as returned by the gettimeofday() +function) when the first data byte was captured. For output streams +the data will not be displayed before this time, secondary to the +nominal frame rate determined by the current video standard in +enqueued order. Applications can for example zero this field to +display frames as soon as possible. The driver stores the time at +which the first data byte was actually sent out in the +timestamp field. This permits +applications to monitor the drift between the video and system +clock. + + + &v4l2-timecode; + timecode + + When type is +V4L2_BUF_TYPE_VIDEO_CAPTURE and the +V4L2_BUF_FLAG_TIMECODE flag is set in +flags, this structure contains a frame +timecode. In V4L2_FIELD_ALTERNATE +mode the top and bottom field contain the same timecode. +Timecodes are intended to help video editing and are typically recorded on +video tapes, but also embedded in compressed formats like MPEG. This +field is independent of the timestamp and +sequence fields. + + + __u32 + sequence + + Set by the driver, counting the frames in the +sequence. + + + In V4L2_FIELD_ALTERNATE mode the top and +bottom field have the same sequence number. The count starts at zero +and includes dropped or repeated frames. A dropped frame was received +by an input device but could not be stored due to lack of free buffer +space. A repeated frame was displayed again by an output device +because the application did not pass new data in +time.Note this may count the frames received +e.g. over USB, without taking into account the frames dropped by the +remote hardware due to limited compression throughput or bus +bandwidth. These devices identify by not enumerating any video +standards, see . + + + &v4l2-memory; + memory + + This field must be set by applications and/or drivers +in accordance with the selected I/O method. + + + union + m + + + + __u32 + offset + When memory is +V4L2_MEMORY_MMAP this is the offset of the buffer +from the start of the device memory. The value is returned by the +driver and apart of serving as parameter to the &func-mmap; function +not useful for applications. See for details. + + + + unsigned long + userptr + When memory is +V4L2_MEMORY_USERPTR this is a pointer to the +buffer (casted to unsigned long type) in virtual memory, set by the +application. See for details. + + + __u32 + length + + Size of the buffer (not the payload) in bytes. + + + __u32 + input + + Some video capture drivers support rapid and +synchronous video input changes, a function useful for example in +video surveillance applications. For this purpose applications set the +V4L2_BUF_FLAG_INPUT flag, and this field to the +number of a video input as in &v4l2-input; field +index. + + + __u32 + reserved + + A place holder for future extensions and custom +(driver defined) buffer types +V4L2_BUF_TYPE_PRIVATE and higher. + + + +
+ + + enum v4l2_buf_type + + &cs-def; + + + V4L2_BUF_TYPE_VIDEO_CAPTURE + 1 + Buffer of a video capture stream, see . + + + V4L2_BUF_TYPE_VIDEO_OUTPUT + 2 + Buffer of a video output stream, see . + + + V4L2_BUF_TYPE_VIDEO_OVERLAY + 3 + Buffer for video overlay, see . + + + V4L2_BUF_TYPE_VBI_CAPTURE + 4 + Buffer of a raw VBI capture stream, see . + + + V4L2_BUF_TYPE_VBI_OUTPUT + 5 + Buffer of a raw VBI output stream, see . + + + V4L2_BUF_TYPE_SLICED_VBI_CAPTURE + 6 + Buffer of a sliced VBI capture stream, see . + + + V4L2_BUF_TYPE_SLICED_VBI_OUTPUT + 7 + Buffer of a sliced VBI output stream, see . + + + V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY + 8 + Buffer for video output overlay (OSD), see . Status: Experimental. + + + V4L2_BUF_TYPE_PRIVATE + 0x80 + This and higher values are reserved for custom +(driver defined) buffer types. + + + +
+ + + Buffer Flags + + &cs-def; + + + V4L2_BUF_FLAG_MAPPED + 0x0001 + The buffer resides in device memory and has been mapped +into the application's address space, see for details. +Drivers set or clear this flag when the +VIDIOC_QUERYBUF, VIDIOC_QBUF or VIDIOC_DQBUF ioctl is called. Set by the driver. + + + V4L2_BUF_FLAG_QUEUED + 0x0002 + Internally drivers maintain two buffer queues, an +incoming and outgoing queue. When this flag is set, the buffer is +currently on the incoming queue. It automatically moves to the +outgoing queue after the buffer has been filled (capture devices) or +displayed (output devices). Drivers set or clear this flag when the +VIDIOC_QUERYBUF ioctl is called. After +(successful) calling the VIDIOC_QBUF ioctl it is +always set and after VIDIOC_DQBUF always +cleared. + + + V4L2_BUF_FLAG_DONE + 0x0004 + When this flag is set, the buffer is currently on +the outgoing queue, ready to be dequeued from the driver. Drivers set +or clear this flag when the VIDIOC_QUERYBUF ioctl +is called. After calling the VIDIOC_QBUF or +VIDIOC_DQBUF it is always cleared. Of course a +buffer cannot be on both queues at the same time, the +V4L2_BUF_FLAG_QUEUED and +V4L2_BUF_FLAG_DONE flag are mutually exclusive. +They can be both cleared however, then the buffer is in "dequeued" +state, in the application domain to say so. + + + V4L2_BUF_FLAG_KEYFRAME + 0x0008 + Drivers set or clear this flag when calling the +VIDIOC_DQBUF ioctl. It may be set by video +capture devices when the buffer contains a compressed image which is a +key frame (or field), &ie; can be decompressed on its own. + + + V4L2_BUF_FLAG_PFRAME + 0x0010 + Similar to V4L2_BUF_FLAG_KEYFRAME +this flags predicted frames or fields which contain only differences to a +previous key frame. + + + V4L2_BUF_FLAG_BFRAME + 0x0020 + Similar to V4L2_BUF_FLAG_PFRAME + this is a bidirectional predicted frame or field. [ooc tbd] + + + V4L2_BUF_FLAG_TIMECODE + 0x0100 + The timecode field is valid. +Drivers set or clear this flag when the VIDIOC_DQBUF +ioctl is called. + + + V4L2_BUF_FLAG_INPUT + 0x0200 + The input field is valid. +Applications set or clear this flag before calling the +VIDIOC_QBUF ioctl. + + + +
+ + + enum v4l2_memory + + &cs-def; + + + V4L2_MEMORY_MMAP + 1 + The buffer is used for memory +mapping I/O. + + + V4L2_MEMORY_USERPTR + 2 + The buffer is used for user +pointer I/O. + + + V4L2_MEMORY_OVERLAY + 3 + [to do] + + + +
+ +
+ Timecodes + + The v4l2_timecode structure is +designed to hold a or similar timecode. +(struct timeval timestamps are stored in +&v4l2-buffer; field timestamp.) + + + struct <structname>v4l2_timecode</structname> + + &cs-str; + + + __u32 + type + Frame rate the timecodes are based on, see . + + + __u32 + flags + Timecode flags, see . + + + __u8 + frames + Frame count, 0 ... 23/24/29/49/59, depending on the + type of timecode. + + + __u8 + seconds + Seconds count, 0 ... 59. This is a binary, not BCD number. + + + __u8 + minutes + Minutes count, 0 ... 59. This is a binary, not BCD number. + + + __u8 + hours + Hours count, 0 ... 29. This is a binary, not BCD number. + + + __u8 + userbits[4] + The "user group" bits from the timecode. + + + +
+ + + Timecode Types + + &cs-def; + + + V4L2_TC_TYPE_24FPS + 1 + 24 frames per second, i. e. film. + + + V4L2_TC_TYPE_25FPS + 2 + 25 frames per second, &ie; PAL or SECAM video. + + + V4L2_TC_TYPE_30FPS + 3 + 30 frames per second, &ie; NTSC video. + + + V4L2_TC_TYPE_50FPS + 4 + + + + V4L2_TC_TYPE_60FPS + 5 + + + + +
+ + + Timecode Flags + + &cs-def; + + + V4L2_TC_FLAG_DROPFRAME + 0x0001 + Indicates "drop frame" semantics for counting frames +in 29.97 fps material. When set, frame numbers 0 and 1 at the start of +each minute, except minutes 0, 10, 20, 30, 40, 50 are omitted from the +count. + + + V4L2_TC_FLAG_COLORFRAME + 0x0002 + The "color frame" flag. + + + V4L2_TC_USERBITS_field + 0x000C + Field mask for the "binary group flags". + + + V4L2_TC_USERBITS_USERDEFINED + 0x0000 + Unspecified format. + + + V4L2_TC_USERBITS_8BITCHARS + 0x0008 + 8-bit ISO characters. + + + +
+
+
+ +
+ Field Order + + We have to distinguish between progressive and interlaced +video. Progressive video transmits all lines of a video image +sequentially. Interlaced video divides an image into two fields, +containing only the odd and even lines of the image, respectively. +Alternating the so called odd and even field are transmitted, and due +to a small delay between fields a cathode ray TV displays the lines +interleaved, yielding the original frame. This curious technique was +invented because at refresh rates similar to film the image would +fade out too quickly. Transmitting fields reduces the flicker without +the necessity of doubling the frame rate and with it the bandwidth +required for each channel. + + It is important to understand a video camera does not expose +one frame at a time, merely transmitting the frames separated into +fields. The fields are in fact captured at two different instances in +time. An object on screen may well move between one field and the +next. For applications analysing motion it is of paramount importance +to recognize which field of a frame is older, the temporal +order. + + When the driver provides or accepts images field by field +rather than interleaved, it is also important applications understand +how the fields combine to frames. We distinguish between top and +bottom fields, the spatial order: The first line +of the top field is the first line of an interlaced frame, the first +line of the bottom field is the second line of that frame. + + However because fields were captured one after the other, +arguing whether a frame commences with the top or bottom field is +pointless. Any two successive top and bottom, or bottom and top fields +yield a valid frame. Only when the source was progressive to begin +with, ⪚ when transferring film to video, two fields may come from +the same frame, creating a natural order. + + Counter to intuition the top field is not necessarily the +older field. Whether the older field contains the top or bottom lines +is a convention determined by the video standard. Hence the +distinction between temporal and spatial order of fields. The diagrams +below should make this clearer. + + All video capture and output devices must report the current +field order. Some drivers may permit the selection of a different +order, to this end applications initialize the +field field of &v4l2-pix-format; before +calling the &VIDIOC-S-FMT; ioctl. If this is not desired it should +have the value V4L2_FIELD_ANY (0). + + + enum v4l2_field + + &cs-def; + + + V4L2_FIELD_ANY + 0 + Applications request this field order when any +one of the V4L2_FIELD_NONE, +V4L2_FIELD_TOP, +V4L2_FIELD_BOTTOM, or +V4L2_FIELD_INTERLACED formats is acceptable. +Drivers choose depending on hardware capabilities or e. g. the +requested image size, and return the actual field order. &v4l2-buffer; +field can never be +V4L2_FIELD_ANY. + + + V4L2_FIELD_NONE + 1 + Images are in progressive format, not interlaced. +The driver may also indicate this order when it cannot distinguish +between V4L2_FIELD_TOP and +V4L2_FIELD_BOTTOM. + + + V4L2_FIELD_TOP + 2 + Images consist of the top field only. + + + V4L2_FIELD_BOTTOM + 3 + Images consist of the bottom field only. +Applications may wish to prevent a device from capturing interlaced +images because they will have "comb" or "feathering" artefacts around +moving objects. + + + V4L2_FIELD_INTERLACED + 4 + Images contain both fields, interleaved line by +line. The temporal order of the fields (whether the top or bottom +field is first transmitted) depends on the current video standard. +M/NTSC transmits the bottom field first, all other standards the top +field first. + + + V4L2_FIELD_SEQ_TB + 5 + Images contain both fields, the top field lines +are stored first in memory, immediately followed by the bottom field +lines. Fields are always stored in temporal order, the older one first +in memory. Image sizes refer to the frame, not fields. + + + V4L2_FIELD_SEQ_BT + 6 + Images contain both fields, the bottom field +lines are stored first in memory, immediately followed by the top +field lines. Fields are always stored in temporal order, the older one +first in memory. Image sizes refer to the frame, not fields. + + + V4L2_FIELD_ALTERNATE + 7 + The two fields of a frame are passed in separate +buffers, in temporal order, &ie; the older one first. To indicate the field +parity (whether the current field is a top or bottom field) the driver +or application, depending on data direction, must set &v4l2-buffer; +field to +V4L2_FIELD_TOP or +V4L2_FIELD_BOTTOM. Any two successive fields pair +to build a frame. If fields are successive, without any dropped fields +between them (fields can drop individually), can be determined from +the &v4l2-buffer; sequence field. Image +sizes refer to the frame, not fields. This format cannot be selected +when using the read/write I/O method. + + + V4L2_FIELD_INTERLACED_TB + 8 + Images contain both fields, interleaved line by +line, top field first. The top field is transmitted first. + + + V4L2_FIELD_INTERLACED_BT + 9 + Images contain both fields, interleaved line by +line, top field first. The bottom field is transmitted first. + + + +
+ +
+ Field Order, Top Field First Transmitted + + + + + + + + +
+ +
+ Field Order, Bottom Field First Transmitted + + + + + + + + +
+
+ + diff --git a/Documentation/DocBook/v4l/keytable.c.xml b/Documentation/DocBook/v4l/keytable.c.xml new file mode 100644 index 000000000000..d53254a3be15 --- /dev/null +++ b/Documentation/DocBook/v4l/keytable.c.xml @@ -0,0 +1,172 @@ + +/* keytable.c - This program allows checking/replacing keys at IR + + Copyright (C) 2006-2009 Mauro Carvalho Chehab <mchehab@infradead.org> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, version 2 of the License. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + */ + +#include <ctype.h> +#include <errno.h> +#include <fcntl.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <linux/input.h> +#include <sys/ioctl.h> + +#include "parse.h" + +void prtcode (int *codes) +{ + struct parse_key *p; + + for (p=keynames;p->name!=NULL;p++) { + if (p->value == (unsigned)codes[1]) { + printf("scancode 0x%04x = %s (0x%02x)\n", codes[0], p->name, codes[1]); + return; + } + } + + if (isprint (codes[1])) + printf("scancode %d = '%c' (0x%02x)\n", codes[0], codes[1], codes[1]); + else + printf("scancode %d = 0x%02x\n", codes[0], codes[1]); +} + +int parse_code(char *string) +{ + struct parse_key *p; + + for (p=keynames;p->name!=NULL;p++) { + if (!strcasecmp(p->name, string)) { + return p->value; + } + } + return -1; +} + +int main (int argc, char *argv[]) +{ + int fd; + unsigned int i, j; + int codes[2]; + + if (argc<2 || argc>4) { + printf ("usage: %s <device> to get table; or\n" + " %s <device> <scancode> <keycode>\n" + " %s <device> <keycode_file>\n",*argv,*argv,*argv); + return -1; + } + + if ((fd = open(argv[1], O_RDONLY)) < 0) { + perror("Couldn't open input device"); + return(-1); + } + + if (argc==4) { + int value; + + value=parse_code(argv[3]); + + if (value==-1) { + value = strtol(argv[3], NULL, 0); + if (errno) + perror("value"); + } + + codes [0] = (unsigned) strtol(argv[2], NULL, 0); + codes [1] = (unsigned) value; + + if(ioctl(fd, EVIOCSKEYCODE, codes)) + perror ("EVIOCSKEYCODE"); + + if(ioctl(fd, EVIOCGKEYCODE, codes)==0) + prtcode(codes); + return 0; + } + + if (argc==3) { + FILE *fin; + int value; + char *scancode, *keycode, s[2048]; + + fin=fopen(argv[2],"r"); + if (fin==NULL) { + perror ("opening keycode file"); + return -1; + } + + /* Clears old table */ + for (j = 0; j < 256; j++) { + for (i = 0; i < 256; i++) { + codes[0] = (j << 8) | i; + codes[1] = KEY_RESERVED; + ioctl(fd, EVIOCSKEYCODE, codes); + } + } + + while (fgets(s,sizeof(s),fin)) { + scancode=strtok(s,"\n\t =:"); + if (!scancode) { + perror ("parsing input file scancode"); + return -1; + } + if (!strcasecmp(scancode, "scancode")) { + scancode = strtok(NULL,"\n\t =:"); + if (!scancode) { + perror ("parsing input file scancode"); + return -1; + } + } + + keycode=strtok(NULL,"\n\t =:("); + if (!keycode) { + perror ("parsing input file keycode"); + return -1; + } + + // printf ("parsing %s=%s:", scancode, keycode); + value=parse_code(keycode); + // printf ("\tvalue=%d\n",value); + + if (value==-1) { + value = strtol(keycode, NULL, 0); + if (errno) + perror("value"); + } + + codes [0] = (unsigned) strtol(scancode, NULL, 0); + codes [1] = (unsigned) value; + + // printf("\t%04x=%04x\n",codes[0], codes[1]); + if(ioctl(fd, EVIOCSKEYCODE, codes)) { + fprintf(stderr, "Setting scancode 0x%04x with 0x%04x via ",codes[0], codes[1]); + perror ("EVIOCSKEYCODE"); + } + + if(ioctl(fd, EVIOCGKEYCODE, codes)==0) + prtcode(codes); + } + return 0; + } + + /* Get scancode table */ + for (j = 0; j < 256; j++) { + for (i = 0; i < 256; i++) { + codes[0] = (j << 8) | i; + if (!ioctl(fd, EVIOCGKEYCODE, codes) && codes[1] != KEY_RESERVED) + prtcode(codes); + } + } + return 0; +} + + diff --git a/Documentation/DocBook/v4l/libv4l.xml b/Documentation/DocBook/v4l/libv4l.xml new file mode 100644 index 000000000000..c14fc3db2a81 --- /dev/null +++ b/Documentation/DocBook/v4l/libv4l.xml @@ -0,0 +1,167 @@ +Libv4l Userspace Library +
+ Introduction + + libv4l is a collection of libraries which adds a thin abstraction +layer on top of video4linux2 devices. The purpose of this (thin) layer +is to make it easy for application writers to support a wide variety of +devices without having to write separate code for different devices in the +same class. +An example of using libv4l is provided by +v4l2grab. + + + libv4l consists of 3 different libraries: +
+ libv4lconvert + + libv4lconvert is a library that converts several +different pixelformats found in V4L2 drivers into a few common RGB and +YUY formats. + It currently accepts the following V4L2 driver formats: +V4L2_PIX_FMT_BGR24, +V4L2_PIX_FMT_HM12, +V4L2_PIX_FMT_JPEG, +V4L2_PIX_FMT_MJPEG, +V4L2_PIX_FMT_MR97310A, +V4L2_PIX_FMT_OV511, +V4L2_PIX_FMT_OV518, +V4L2_PIX_FMT_PAC207, +V4L2_PIX_FMT_PJPG, +V4L2_PIX_FMT_RGB24, +V4L2_PIX_FMT_SBGGR8, +V4L2_PIX_FMT_SGBRG8, +V4L2_PIX_FMT_SGRBG8, +V4L2_PIX_FMT_SN9C10X, +V4L2_PIX_FMT_SN9C20X_I420, +V4L2_PIX_FMT_SPCA501, +V4L2_PIX_FMT_SPCA505, +V4L2_PIX_FMT_SPCA508, +V4L2_PIX_FMT_SPCA561, +V4L2_PIX_FMT_SQ905C, +V4L2_PIX_FMT_SRGGB8, +V4L2_PIX_FMT_UYVY, +V4L2_PIX_FMT_YUV420, +V4L2_PIX_FMT_YUYV, +V4L2_PIX_FMT_YVU420, +and V4L2_PIX_FMT_YVYU. + + Later on libv4lconvert was expanded to also be able to do +various video processing functions to improve webcam video quality. +The video processing is split in to 2 parts: libv4lconvert/control and +libv4lconvert/processing. + + The control part is used to offer video controls which can +be used to control the video processing functions made available by + libv4lconvert/processing. These controls are stored application wide +(until reboot) by using a persistent shared memory object. + + libv4lconvert/processing offers the actual video +processing functionality. +
+
+ libv4l1 + This library offers functions that can be used to quickly +make v4l1 applications work with v4l2 devices. These functions work exactly +like the normal open/close/etc, except that libv4l1 does full emulation of +the v4l1 api on top of v4l2 drivers, in case of v4l1 drivers it +will just pass calls through. + Since those functions are emulations of the old V4L1 API, +it shouldn't be used for new applications. +
+
+ libv4l2 + This library should be used for all modern V4L2 +applications. + It provides handles to call V4L2 open/ioctl/close/poll +methods. Instead of just providing the raw output of the device, it enhances +the calls in the sense that it will use libv4lconvert to provide more video +formats and to enhance the image quality. + In most cases, libv4l2 just passes the calls directly +through to the v4l2 driver, intercepting the calls to +VIDIOC_TRY_FMT, +VIDIOC_G_FMT +VIDIOC_S_FMT +VIDIOC_ENUM_FRAMESIZES +and VIDIOC_ENUM_FRAMEINTERVALS +in order to emulate the formats +V4L2_PIX_FMT_BGR24, +V4L2_PIX_FMT_RGB24, +V4L2_PIX_FMT_YUV420, +and V4L2_PIX_FMT_YVU420, +if they aren't available in the driver. +VIDIOC_ENUM_FMT +keeps enumerating the hardware supported formats, plus the emulated formats +offered by libv4l at the end. + +
+ Libv4l device control functions + The common file operation methods are provided by +libv4l. + Those functions operate just like glibc +open/close/dup/ioctl/read/mmap/munmap: + + int v4l2_open(const char *file, int oflag, +...) - +operates like the standard open() function. + + int v4l2_close(int fd) - +operates like the standard close() function. + + int v4l2_dup(int fd) - +operates like the standard dup() function, duplicating a file handler. + + int v4l2_ioctl (int fd, unsigned long int request, ...) - +operates like the standard ioctl() function. + + int v4l2_read (int fd, void* buffer, size_t n) - +operates like the standard read() function. + + void v4l2_mmap(void *start, size_t length, int prot, int flags, int fd, int64_t offset); - +operates like the standard mmap() function. + + int v4l2_munmap(void *_start, size_t length); - +operates like the standard munmap() function. + + + Those functions provide additional control: + + int v4l2_fd_open(int fd, int v4l2_flags) - +opens an already opened fd for further use through v4l2lib and possibly +modify libv4l2's default behavior through the v4l2_flags argument. +Currently, v4l2_flags can be V4L2_DISABLE_CONVERSION, +to disable format conversion. + + int v4l2_set_control(int fd, int cid, int value) - +This function takes a value of 0 - 65535, and then scales that range to +the actual range of the given v4l control id, and then if the cid exists +and is not locked sets the cid to the scaled value. + + int v4l2_get_control(int fd, int cid) - +This function returns a value of 0 - 65535, scaled to from the actual range +of the given v4l control id. when the cid does not exist, could not be +accessed for some reason, or some error occured 0 is returned. + + +
+
+
+ + v4l1compat.so wrapper library + + This library intercepts calls to +open/close/ioctl/mmap/mmunmap operations and redirects them to the libv4l +counterparts, by using LD_PRELOAD=/usr/lib/v4l1compat.so. It also +emulates V4L1 calls via V4L2 API. + It allows usage of binary legacy applications that +still don't use libv4l. +
+ +
+ diff --git a/Documentation/DocBook/v4l/pixfmt-grey.xml b/Documentation/DocBook/v4l/pixfmt-grey.xml new file mode 100644 index 000000000000..3b72bc6b2de7 --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-grey.xml @@ -0,0 +1,70 @@ + + + V4L2_PIX_FMT_GREY ('GREY') + &manvol; + + + V4L2_PIX_FMT_GREY + Grey-scale image + + + Description + + This is a grey-scale image. It is really a degenerate +Y'CbCr format which simply contains no Cb or Cr data. + + + <constant>V4L2_PIX_FMT_GREY</constant> 4 × 4 +pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + Y'00 + Y'01 + Y'02 + Y'03 + + + start + 4: + Y'10 + Y'11 + Y'12 + Y'13 + + + start + 8: + Y'20 + Y'21 + Y'22 + Y'23 + + + start + 12: + Y'30 + Y'31 + Y'32 + Y'33 + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-nv12.xml b/Documentation/DocBook/v4l/pixfmt-nv12.xml new file mode 100644 index 000000000000..873f67035181 --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-nv12.xml @@ -0,0 +1,151 @@ + + + V4L2_PIX_FMT_NV12 ('NV12'), V4L2_PIX_FMT_NV21 ('NV21') + &manvol; + + + V4L2_PIX_FMT_NV12 + V4L2_PIX_FMT_NV21 + Formats with ½ horizontal and vertical +chroma resolution, also known as YUV 4:2:0. One luminance and one +chrominance plane with alternating chroma samples as opposed to +V4L2_PIX_FMT_YVU420 + + + Description + + These are two-plane versions of the YUV 4:2:0 format. +The three components are separated into two sub-images or planes. The +Y plane is first. The Y plane has one byte per pixel. For +V4L2_PIX_FMT_NV12, a combined CbCr plane +immediately follows the Y plane in memory. The CbCr plane is the same +width, in bytes, as the Y plane (and of the image), but is half as +tall in pixels. Each CbCr pair belongs to four pixels. For example, +Cb0/Cr0 belongs to +Y'00, Y'01, +Y'10, Y'11. +V4L2_PIX_FMT_NV21 is the same except the Cb and +Cr bytes are swapped, the CrCb plane starts with a Cr byte. + + If the Y plane has pad bytes after each row, then the +CbCr plane has as many pad bytes after its rows. + + + <constant>V4L2_PIX_FMT_NV12</constant> 4 × 4 +pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + Y'00 + Y'01 + Y'02 + Y'03 + + + start + 4: + Y'10 + Y'11 + Y'12 + Y'13 + + + start + 8: + Y'20 + Y'21 + Y'22 + Y'23 + + + start + 12: + Y'30 + Y'31 + Y'32 + Y'33 + + + start + 16: + Cb00 + Cr00 + Cb01 + Cr01 + + + start + 20: + Cb10 + Cr10 + Cb11 + Cr11 + + + + + + + + + Color Sample Location. + + + + + + + 01 + 23 + + + 0 + YY + YY + + + + C + C + + + 1 + YY + YY + + + + + + 2 + YY + YY + + + + C + C + + + 3 + YY + YY + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-nv16.xml b/Documentation/DocBook/v4l/pixfmt-nv16.xml new file mode 100644 index 000000000000..26094035fc04 --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-nv16.xml @@ -0,0 +1,174 @@ + + + V4L2_PIX_FMT_NV16 ('NV16'), V4L2_PIX_FMT_NV61 ('NV61') + &manvol; + + + V4L2_PIX_FMT_NV16 + V4L2_PIX_FMT_NV61 + Formats with ½ horizontal +chroma resolution, also known as YUV 4:2:2. One luminance and one +chrominance plane with alternating chroma samples as opposed to +V4L2_PIX_FMT_YVU420 + + + Description + + These are two-plane versions of the YUV 4:2:2 format. +The three components are separated into two sub-images or planes. The +Y plane is first. The Y plane has one byte per pixel. For +V4L2_PIX_FMT_NV16, a combined CbCr plane +immediately follows the Y plane in memory. The CbCr plane is the same +width and height, in bytes, as the Y plane (and of the image). +Each CbCr pair belongs to two pixels. For example, +Cb0/Cr0 belongs to +Y'00, Y'01. +V4L2_PIX_FMT_NV61 is the same except the Cb and +Cr bytes are swapped, the CrCb plane starts with a Cr byte. + + If the Y plane has pad bytes after each row, then the +CbCr plane has as many pad bytes after its rows. + + + <constant>V4L2_PIX_FMT_NV16</constant> 4 × 4 +pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + Y'00 + Y'01 + Y'02 + Y'03 + + + start + 4: + Y'10 + Y'11 + Y'12 + Y'13 + + + start + 8: + Y'20 + Y'21 + Y'22 + Y'23 + + + start + 12: + Y'30 + Y'31 + Y'32 + Y'33 + + + start + 16: + Cb00 + Cr00 + Cb01 + Cr01 + + + start + 20: + Cb10 + Cr10 + Cb11 + Cr11 + + + start + 24: + Cb20 + Cr20 + Cb21 + Cr21 + + + start + 28: + Cb30 + Cr30 + Cb31 + Cr31 + + + + + + + + + Color Sample Location. + + + + + + + 01 + 23 + + + 0 + YY + YY + + + + C + C + + + 1 + YY + YY + + + + C + C + + + + + + 2 + YY + YY + + + + C + C + + + 3 + YY + YY + + + + C + C + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-packed-rgb.xml b/Documentation/DocBook/v4l/pixfmt-packed-rgb.xml new file mode 100644 index 000000000000..d2dd697a81d8 --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-packed-rgb.xml @@ -0,0 +1,862 @@ + + + Packed RGB formats + &manvol; + + + Packed RGB formats + Packed RGB formats + + + Description + + These formats are designed to match the pixel formats of +typical PC graphics frame buffers. They occupy 8, 16, 24 or 32 bits +per pixel. These are all packed-pixel formats, meaning all the data +for a pixel lie next to each other in memory. + + When one of these formats is used, drivers shall report the +colorspace V4L2_COLORSPACE_SRGB. + + + Packed RGB Image Formats + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Identifier + Code +   + Byte 0 in memory + Byte 1 + Byte 2 + Byte 3 + + +   +   + Bit + 7 + 6 + 5 + 4 + 3 + 2 + 1 + 0 +   + 7 + 6 + 5 + 4 + 3 + 2 + 1 + 0 +   + 7 + 6 + 5 + 4 + 3 + 2 + 1 + 0 +   + 7 + 6 + 5 + 4 + 3 + 2 + 1 + 0 + + + + + V4L2_PIX_FMT_RGB332 + 'RGB1' + + b1 + b0 + g2 + g1 + g0 + r2 + r1 + r0 + + + V4L2_PIX_FMT_RGB444 + 'R444' + + g3 + g2 + g1 + g0 + b3 + b2 + b1 + b0 + + a3 + a2 + a1 + a0 + r3 + r2 + r1 + r0 + + + V4L2_PIX_FMT_RGB555 + 'RGBO' + + g2 + g1 + g0 + r4 + r3 + r2 + r1 + r0 + + a + b4 + b3 + b2 + b1 + b0 + g4 + g3 + + + V4L2_PIX_FMT_RGB565 + 'RGBP' + + g2 + g1 + g0 + r4 + r3 + r2 + r1 + r0 + + b4 + b3 + b2 + b1 + b0 + g5 + g4 + g3 + + + V4L2_PIX_FMT_RGB555X + 'RGBQ' + + a + b4 + b3 + b2 + b1 + b0 + g4 + g3 + + g2 + g1 + g0 + r4 + r3 + r2 + r1 + r0 + + + V4L2_PIX_FMT_RGB565X + 'RGBR' + + b4 + b3 + b2 + b1 + b0 + g5 + g4 + g3 + + g2 + g1 + g0 + r4 + r3 + r2 + r1 + r0 + + + V4L2_PIX_FMT_BGR24 + 'BGR3' + + b7 + b6 + b5 + b4 + b3 + b2 + b1 + b0 + + g7 + g6 + g5 + g4 + g3 + g2 + g1 + g0 + + r7 + r6 + r5 + r4 + r3 + r2 + r1 + r0 + + + V4L2_PIX_FMT_RGB24 + 'RGB3' + + r7 + r6 + r5 + r4 + r3 + r2 + r1 + r0 + + g7 + g6 + g5 + g4 + g3 + g2 + g1 + g0 + + b7 + b6 + b5 + b4 + b3 + b2 + b1 + b0 + + + V4L2_PIX_FMT_BGR32 + 'BGR4' + + b7 + b6 + b5 + b4 + b3 + b2 + b1 + b0 + + g7 + g6 + g5 + g4 + g3 + g2 + g1 + g0 + + r7 + r6 + r5 + r4 + r3 + r2 + r1 + r0 + + a7 + a6 + a5 + a4 + a3 + a2 + a1 + a0 + + + V4L2_PIX_FMT_RGB32 + 'RGB4' + + r7 + r6 + r5 + r4 + r3 + r2 + r1 + r0 + + g7 + g6 + g5 + g4 + g3 + g2 + g1 + g0 + + b7 + b6 + b5 + b4 + b3 + b2 + b1 + b0 + + a7 + a6 + a5 + a4 + a3 + a2 + a1 + a0 + + + +
+ + Bit 7 is the most significant bit. The value of a = alpha +bits is undefined when reading from the driver, ignored when writing +to the driver, except when alpha blending has been negotiated for a +Video Overlay or Video Output Overlay. + + + <constant>V4L2_PIX_FMT_BGR24</constant> 4 × 4 pixel +image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + B00 + G00 + R00 + B01 + G01 + R01 + B02 + G02 + R02 + B03 + G03 + R03 + + + start + 12: + B10 + G10 + R10 + B11 + G11 + R11 + B12 + G12 + R12 + B13 + G13 + R13 + + + start + 24: + B20 + G20 + R20 + B21 + G21 + R21 + B22 + G22 + R22 + B23 + G23 + R23 + + + start + 36: + B30 + G30 + R30 + B31 + G31 + R31 + B32 + G32 + R32 + B33 + G33 + R33 + + + + + + + + + + Drivers may interpret these formats differently. + + + Some RGB formats above are uncommon and were probably +defined in error. Drivers may interpret them as in . + + + Packed RGB Image Formats (corrected) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Identifier + Code +   + Byte 0 in memory + Byte 1 + Byte 2 + Byte 3 + + +   +   + Bit + 7 + 6 + 5 + 4 + 3 + 2 + 1 + 0 +   + 7 + 6 + 5 + 4 + 3 + 2 + 1 + 0 +   + 7 + 6 + 5 + 4 + 3 + 2 + 1 + 0 +   + 7 + 6 + 5 + 4 + 3 + 2 + 1 + 0 + + + + + V4L2_PIX_FMT_RGB332 + 'RGB1' + + r2 + r1 + r0 + g2 + g1 + g0 + b1 + b0 + + + V4L2_PIX_FMT_RGB444 + 'R444' + + g3 + g2 + g1 + g0 + b3 + b2 + b1 + b0 + + a3 + a2 + a1 + a0 + r3 + r2 + r1 + r0 + + + V4L2_PIX_FMT_RGB555 + 'RGBO' + + g2 + g1 + g0 + b4 + b3 + b2 + b1 + b0 + + a + r4 + r3 + r2 + r1 + r0 + g4 + g3 + + + V4L2_PIX_FMT_RGB565 + 'RGBP' + + g2 + g1 + g0 + b4 + b3 + b2 + b1 + b0 + + r4 + r3 + r2 + r1 + r0 + g5 + g4 + g3 + + + V4L2_PIX_FMT_RGB555X + 'RGBQ' + + a + r4 + r3 + r2 + r1 + r0 + g4 + g3 + + g2 + g1 + g0 + b4 + b3 + b2 + b1 + b0 + + + V4L2_PIX_FMT_RGB565X + 'RGBR' + + r4 + r3 + r2 + r1 + r0 + g5 + g4 + g3 + + g2 + g1 + g0 + b4 + b3 + b2 + b1 + b0 + + + V4L2_PIX_FMT_BGR24 + 'BGR3' + + b7 + b6 + b5 + b4 + b3 + b2 + b1 + b0 + + g7 + g6 + g5 + g4 + g3 + g2 + g1 + g0 + + r7 + r6 + r5 + r4 + r3 + r2 + r1 + r0 + + + V4L2_PIX_FMT_RGB24 + 'RGB3' + + r7 + r6 + r5 + r4 + r3 + r2 + r1 + r0 + + g7 + g6 + g5 + g4 + g3 + g2 + g1 + g0 + + b7 + b6 + b5 + b4 + b3 + b2 + b1 + b0 + + + V4L2_PIX_FMT_BGR32 + 'BGR4' + + b7 + b6 + b5 + b4 + b3 + b2 + b1 + b0 + + g7 + g6 + g5 + g4 + g3 + g2 + g1 + g0 + + r7 + r6 + r5 + r4 + r3 + r2 + r1 + r0 + + a7 + a6 + a5 + a4 + a3 + a2 + a1 + a0 + + + V4L2_PIX_FMT_RGB32 + 'RGB4' + + a7 + a6 + a5 + a4 + a3 + a2 + a1 + a0 + + r7 + r6 + r5 + r4 + r3 + r2 + r1 + r0 + + g7 + g6 + g5 + g4 + g3 + g2 + g1 + g0 + + b7 + b6 + b5 + b4 + b3 + b2 + b1 + b0 + + + +
+ + A test utility to determine which RGB formats a driver +actually supports is available from the LinuxTV v4l-dvb repository. +See &v4l-dvb; for access instructions. + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-packed-yuv.xml b/Documentation/DocBook/v4l/pixfmt-packed-yuv.xml new file mode 100644 index 000000000000..3cab5d0ca75d --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-packed-yuv.xml @@ -0,0 +1,244 @@ + + + Packed YUV formats + &manvol; + + + Packed YUV formats + Packed YUV formats + + + Description + + Similar to the packed RGB formats these formats store +the Y, Cb and Cr component of each pixel in one 16 or 32 bit +word. + + + Packed YUV Image Formats + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Identifier + Code +   + Byte 0 in memory + Byte 1 + Byte 2 + Byte 3 + + +   +   + Bit + 7 + 6 + 5 + 4 + 3 + 2 + 1 + 0 +   + 7 + 6 + 5 + 4 + 3 + 2 + 1 + 0 +   + 7 + 6 + 5 + 4 + 3 + 2 + 1 + 0 +   + 7 + 6 + 5 + 4 + 3 + 2 + 1 + 0 + + + + + V4L2_PIX_FMT_YUV444 + 'Y444' + + Cb3 + Cb2 + Cb1 + Cb0 + Cr3 + Cr2 + Cr1 + Cr0 + + a3 + a2 + a1 + a0 + Y'3 + Y'2 + Y'1 + Y'0 + + + + V4L2_PIX_FMT_YUV555 + 'YUVO' + + Cb2 + Cb1 + Cb0 + Cr4 + Cr3 + Cr2 + Cr1 + Cr0 + + a + Y'4 + Y'3 + Y'2 + Y'1 + Y'0 + Cb4 + Cb3 + + + + V4L2_PIX_FMT_YUV565 + 'YUVP' + + Cb2 + Cb1 + Cb0 + Cr4 + Cr3 + Cr2 + Cr1 + Cr0 + + Y'4 + Y'3 + Y'2 + Y'1 + Y'0 + Cb5 + Cb4 + Cb3 + + + + V4L2_PIX_FMT_YUV32 + 'YUV4' + + a7 + a6 + a5 + a4 + a3 + a2 + a1 + a0 + + Y'7 + Y'6 + Y'5 + Y'4 + Y'3 + Y'2 + Y'1 + Y'0 + + Cb7 + Cb6 + Cb5 + Cb4 + Cb3 + Cb2 + Cb1 + Cb0 + + Cr7 + Cr6 + Cr5 + Cr4 + Cr3 + Cr2 + Cr1 + Cr0 + + + +
+ + Bit 7 is the most significant bit. The value of a = alpha +bits is undefined when reading from the driver, ignored when writing +to the driver, except when alpha blending has been negotiated for a +Video Overlay or Video Output Overlay. + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-sbggr16.xml b/Documentation/DocBook/v4l/pixfmt-sbggr16.xml new file mode 100644 index 000000000000..519a9efbac10 --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-sbggr16.xml @@ -0,0 +1,91 @@ + + + V4L2_PIX_FMT_SBGGR16 ('BYR2') + &manvol; + + + V4L2_PIX_FMT_SBGGR16 + Bayer RGB format + + + Description + + This format is similar to +V4L2_PIX_FMT_SBGGR8, except each pixel has +a depth of 16 bits. The least significant byte is stored at lower +memory addresses (little-endian). Note the actual sampling precision +may be lower than 16 bits, for example 10 bits per pixel with values +in range 0 to 1023. + + + <constant>V4L2_PIX_FMT_SBGGR16</constant> 4 × 4 +pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + B00low + B00high + G01low + G01high + B02low + B02high + G03low + G03high + + + start + 8: + G10low + G10high + R11low + R11high + G12low + G12high + R13low + R13high + + + start + 16: + B20low + B20high + G21low + G21high + B22low + B22high + G23low + G23high + + + start + 24: + G30low + G30high + R31low + R31high + G32low + G32high + R33low + R33high + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-sbggr8.xml b/Documentation/DocBook/v4l/pixfmt-sbggr8.xml new file mode 100644 index 000000000000..5fe84ecc2ebe --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-sbggr8.xml @@ -0,0 +1,75 @@ + + + V4L2_PIX_FMT_SBGGR8 ('BA81') + &manvol; + + + V4L2_PIX_FMT_SBGGR8 + Bayer RGB format + + + Description + + This is commonly the native format of digital cameras, +reflecting the arrangement of sensors on the CCD device. Only one red, +green or blue value is given for each pixel. Missing components must +be interpolated from neighbouring pixels. From left to right the first +row consists of a blue and green value, the second row of a green and +red value. This scheme repeats to the right and down for every two +columns and rows. + + + <constant>V4L2_PIX_FMT_SBGGR8</constant> 4 × 4 +pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + B00 + G01 + B02 + G03 + + + start + 4: + G10 + R11 + G12 + R13 + + + start + 8: + B20 + G21 + B22 + G23 + + + start + 12: + G30 + R31 + G32 + R33 + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-sgbrg8.xml b/Documentation/DocBook/v4l/pixfmt-sgbrg8.xml new file mode 100644 index 000000000000..d67a472b0880 --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-sgbrg8.xml @@ -0,0 +1,75 @@ + + + V4L2_PIX_FMT_SGBRG8 ('GBRG') + &manvol; + + + V4L2_PIX_FMT_SGBRG8 + Bayer RGB format + + + Description + + This is commonly the native format of digital cameras, +reflecting the arrangement of sensors on the CCD device. Only one red, +green or blue value is given for each pixel. Missing components must +be interpolated from neighbouring pixels. From left to right the first +row consists of a green and blue value, the second row of a red and +green value. This scheme repeats to the right and down for every two +columns and rows. + + + <constant>V4L2_PIX_FMT_SGBRG8</constant> 4 × 4 +pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + G00 + B01 + G02 + B03 + + + start + 4: + R10 + G11 + R12 + G13 + + + start + 8: + G20 + B21 + G22 + B23 + + + start + 12: + R30 + G31 + R32 + G33 + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-sgrbg8.xml b/Documentation/DocBook/v4l/pixfmt-sgrbg8.xml new file mode 100644 index 000000000000..0cdf13b8ac1c --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-sgrbg8.xml @@ -0,0 +1,75 @@ + + + V4L2_PIX_FMT_SGRBG8 ('GRBG') + &manvol; + + + V4L2_PIX_FMT_SGRBG8 + Bayer RGB format + + + Description + + This is commonly the native format of digital cameras, +reflecting the arrangement of sensors on the CCD device. Only one red, +green or blue value is given for each pixel. Missing components must +be interpolated from neighbouring pixels. From left to right the first +row consists of a green and blue value, the second row of a red and +green value. This scheme repeats to the right and down for every two +columns and rows. + + + <constant>V4L2_PIX_FMT_SGRBG8</constant> 4 × +4 pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + G00 + R01 + G02 + R03 + + + start + 4: + R10 + B11 + R12 + B13 + + + start + 8: + G20 + R21 + G22 + R23 + + + start + 12: + R30 + B31 + R32 + B33 + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-uyvy.xml b/Documentation/DocBook/v4l/pixfmt-uyvy.xml new file mode 100644 index 000000000000..816c8d467c16 --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-uyvy.xml @@ -0,0 +1,128 @@ + + + V4L2_PIX_FMT_UYVY ('UYVY') + &manvol; + + + V4L2_PIX_FMT_UYVY + Variation of +V4L2_PIX_FMT_YUYV with different order of samples +in memory + + + Description + + In this format each four bytes is two pixels. Each four +bytes is two Y's, a Cb and a Cr. Each Y goes to one of the pixels, and +the Cb and Cr belong to both pixels. As you can see, the Cr and Cb +components have half the horizontal resolution of the Y +component. + + + <constant>V4L2_PIX_FMT_UYVY</constant> 4 × 4 +pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + Cb00 + Y'00 + Cr00 + Y'01 + Cb01 + Y'02 + Cr01 + Y'03 + + + start + 8: + Cb10 + Y'10 + Cr10 + Y'11 + Cb11 + Y'12 + Cr11 + Y'13 + + + start + 16: + Cb20 + Y'20 + Cr20 + Y'21 + Cb21 + Y'22 + Cr21 + Y'23 + + + start + 24: + Cb30 + Y'30 + Cr30 + Y'31 + Cb31 + Y'32 + Cr31 + Y'33 + + + + + + + + + Color Sample Location. + + + + + + + 01 + 23 + + + 0 + YCY + YCY + + + 1 + YCY + YCY + + + 2 + YCY + YCY + + + 3 + YCY + YCY + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-vyuy.xml b/Documentation/DocBook/v4l/pixfmt-vyuy.xml new file mode 100644 index 000000000000..61f12a5e68d9 --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-vyuy.xml @@ -0,0 +1,128 @@ + + + V4L2_PIX_FMT_VYUY ('VYUY') + &manvol; + + + V4L2_PIX_FMT_VYUY + Variation of +V4L2_PIX_FMT_YUYV with different order of samples +in memory + + + Description + + In this format each four bytes is two pixels. Each four +bytes is two Y's, a Cb and a Cr. Each Y goes to one of the pixels, and +the Cb and Cr belong to both pixels. As you can see, the Cr and Cb +components have half the horizontal resolution of the Y +component. + + + <constant>V4L2_PIX_FMT_VYUY</constant> 4 × 4 +pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + Cr00 + Y'00 + Cb00 + Y'01 + Cr01 + Y'02 + Cb01 + Y'03 + + + start + 8: + Cr10 + Y'10 + Cb10 + Y'11 + Cr11 + Y'12 + Cb11 + Y'13 + + + start + 16: + Cr20 + Y'20 + Cb20 + Y'21 + Cr21 + Y'22 + Cb21 + Y'23 + + + start + 24: + Cr30 + Y'30 + Cb30 + Y'31 + Cr31 + Y'32 + Cb31 + Y'33 + + + + + + + + + Color Sample Location. + + + + + + + 01 + 23 + + + 0 + YCY + YCY + + + 1 + YCY + YCY + + + 2 + YCY + YCY + + + 3 + YCY + YCY + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-y16.xml b/Documentation/DocBook/v4l/pixfmt-y16.xml new file mode 100644 index 000000000000..d58404015078 --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-y16.xml @@ -0,0 +1,89 @@ + + + V4L2_PIX_FMT_Y16 ('Y16 ') + &manvol; + + + V4L2_PIX_FMT_Y16 + Grey-scale image + + + Description + + This is a grey-scale image with a depth of 16 bits per +pixel. The least significant byte is stored at lower memory addresses +(little-endian). Note the actual sampling precision may be lower than +16 bits, for example 10 bits per pixel with values in range 0 to +1023. + + + <constant>V4L2_PIX_FMT_Y16</constant> 4 × 4 +pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + Y'00low + Y'00high + Y'01low + Y'01high + Y'02low + Y'02high + Y'03low + Y'03high + + + start + 8: + Y'10low + Y'10high + Y'11low + Y'11high + Y'12low + Y'12high + Y'13low + Y'13high + + + start + 16: + Y'20low + Y'20high + Y'21low + Y'21high + Y'22low + Y'22high + Y'23low + Y'23high + + + start + 24: + Y'30low + Y'30high + Y'31low + Y'31high + Y'32low + Y'32high + Y'33low + Y'33high + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-y41p.xml b/Documentation/DocBook/v4l/pixfmt-y41p.xml new file mode 100644 index 000000000000..73c8536efb05 --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-y41p.xml @@ -0,0 +1,157 @@ + + + V4L2_PIX_FMT_Y41P ('Y41P') + &manvol; + + + V4L2_PIX_FMT_Y41P + Format with ¼ horizontal chroma +resolution, also known as YUV 4:1:1 + + + Description + + In this format each 12 bytes is eight pixels. In the +twelve bytes are two CbCr pairs and eight Y's. The first CbCr pair +goes with the first four Y's, and the second CbCr pair goes with the +other four Y's. The Cb and Cr components have one fourth the +horizontal resolution of the Y component. + + Do not confuse this format with V4L2_PIX_FMT_YUV411P. +Y41P is derived from "YUV 4:1:1 packed", while +YUV411P stands for "YUV 4:1:1 planar". + + + <constant>V4L2_PIX_FMT_Y41P</constant> 8 × 4 +pixel image + + + Byte Order + Each cell is one byte. + + + + + + start + 0: + Cb00 + Y'00 + Cr00 + Y'01 + Cb01 + Y'02 + Cr01 + Y'03 + Y'04 + Y'05 + Y'06 + Y'07 + + + start + 12: + Cb10 + Y'10 + Cr10 + Y'11 + Cb11 + Y'12 + Cr11 + Y'13 + Y'14 + Y'15 + Y'16 + Y'17 + + + start + 24: + Cb20 + Y'20 + Cr20 + Y'21 + Cb21 + Y'22 + Cr21 + Y'23 + Y'24 + Y'25 + Y'26 + Y'27 + + + start + 36: + Cb30 + Y'30 + Cr30 + Y'31 + Cb31 + Y'32 + Cr31 + Y'33 + Y'34 + Y'35 + Y'36 + Y'37 + + + + + + + + Color Sample Location. + + + + + + + 01 + 23 + 45 + 67 + + + 0 + YYC + YY + YYC + YY + + + 1 + YYC + YY + YYC + YY + + + 2 + YYC + YY + YYC + YY + + + 3 + YYC + YY + YYC + YY + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-yuv410.xml b/Documentation/DocBook/v4l/pixfmt-yuv410.xml new file mode 100644 index 000000000000..8eb4a193d770 --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-yuv410.xml @@ -0,0 +1,141 @@ + + + V4L2_PIX_FMT_YVU410 ('YVU9'), V4L2_PIX_FMT_YUV410 ('YUV9') + &manvol; + + + V4L2_PIX_FMT_YVU410 + V4L2_PIX_FMT_YUV410 + Planar formats with ¼ horizontal and +vertical chroma resolution, also known as YUV 4:1:0 + + + Description + + These are planar formats, as opposed to a packed format. +The three components are separated into three sub-images or planes. +The Y plane is first. The Y plane has one byte per pixel. For +V4L2_PIX_FMT_YVU410, the Cr plane immediately +follows the Y plane in memory. The Cr plane is ¼ the width and +¼ the height of the Y plane (and of the image). Each Cr belongs +to 16 pixels, a four-by-four square of the image. Following the Cr +plane is the Cb plane, just like the Cr plane. +V4L2_PIX_FMT_YUV410 is the same, except the Cb +plane comes first, then the Cr plane. + + If the Y plane has pad bytes after each row, then the Cr +and Cb planes have ¼ as many pad bytes after their rows. In +other words, four Cx rows (including padding) are exactly as long as +one Y row (including padding). + + + <constant>V4L2_PIX_FMT_YVU410</constant> 4 × 4 +pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + Y'00 + Y'01 + Y'02 + Y'03 + + + start + 4: + Y'10 + Y'11 + Y'12 + Y'13 + + + start + 8: + Y'20 + Y'21 + Y'22 + Y'23 + + + start + 12: + Y'30 + Y'31 + Y'32 + Y'33 + + + start + 16: + Cr00 + + + start + 17: + Cb00 + + + + + + + + + Color Sample Location. + + + + + + + 01 + 23 + + + 0 + YY + YY + + + + + + 1 + YY + YY + + + + C + + + + 2 + YY + YY + + + + + + 3 + YY + YY + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-yuv411p.xml b/Documentation/DocBook/v4l/pixfmt-yuv411p.xml new file mode 100644 index 000000000000..00e0960a9869 --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-yuv411p.xml @@ -0,0 +1,155 @@ + + + V4L2_PIX_FMT_YUV411P ('411P') + &manvol; + + + V4L2_PIX_FMT_YUV411P + Format with ¼ horizontal chroma resolution, +also known as YUV 4:1:1. Planar layout as opposed to +V4L2_PIX_FMT_Y41P + + + Description + + This format is not commonly used. This is a planar +format similar to the 4:2:2 planar format except with half as many +chroma. The three components are separated into three sub-images or +planes. The Y plane is first. The Y plane has one byte per pixel. The +Cb plane immediately follows the Y plane in memory. The Cb plane is +¼ the width of the Y plane (and of the image). Each Cb belongs +to 4 pixels all on the same row. For example, +Cb0 belongs to Y'00, +Y'01, Y'02 and +Y'03. Following the Cb plane is the Cr plane, +just like the Cb plane. + + If the Y plane has pad bytes after each row, then the Cr +and Cb planes have ¼ as many pad bytes after their rows. In +other words, four C x rows (including padding) is exactly as long as +one Y row (including padding). + + + <constant>V4L2_PIX_FMT_YUV411P</constant> 4 × 4 +pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + Y'00 + Y'01 + Y'02 + Y'03 + + + start + 4: + Y'10 + Y'11 + Y'12 + Y'13 + + + start + 8: + Y'20 + Y'21 + Y'22 + Y'23 + + + start + 12: + Y'30 + Y'31 + Y'32 + Y'33 + + + start + 16: + Cb00 + + + start + 17: + Cb10 + + + start + 18: + Cb20 + + + start + 19: + Cb30 + + + start + 20: + Cr00 + + + start + 21: + Cr10 + + + start + 22: + Cr20 + + + start + 23: + Cr30 + + + + + + + + + Color Sample Location. + + + + + + + 01 + 23 + + + 0 + YYC + YY + + + 1 + YYC + YY + + + 2 + YYC + YY + + + 3 + YYC + YY + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-yuv420.xml b/Documentation/DocBook/v4l/pixfmt-yuv420.xml new file mode 100644 index 000000000000..42d7de5e456d --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-yuv420.xml @@ -0,0 +1,157 @@ + + + V4L2_PIX_FMT_YVU420 ('YV12'), V4L2_PIX_FMT_YUV420 ('YU12') + &manvol; + + + V4L2_PIX_FMT_YVU420 + V4L2_PIX_FMT_YUV420 + Planar formats with ½ horizontal and +vertical chroma resolution, also known as YUV 4:2:0 + + + Description + + These are planar formats, as opposed to a packed format. +The three components are separated into three sub- images or planes. +The Y plane is first. The Y plane has one byte per pixel. For +V4L2_PIX_FMT_YVU420, the Cr plane immediately +follows the Y plane in memory. The Cr plane is half the width and half +the height of the Y plane (and of the image). Each Cr belongs to four +pixels, a two-by-two square of the image. For example, +Cr0 belongs to Y'00, +Y'01, Y'10, and +Y'11. Following the Cr plane is the Cb plane, +just like the Cr plane. V4L2_PIX_FMT_YUV420 is +the same except the Cb plane comes first, then the Cr plane. + + If the Y plane has pad bytes after each row, then the Cr +and Cb planes have half as many pad bytes after their rows. In other +words, two Cx rows (including padding) is exactly as long as one Y row +(including padding). + + + <constant>V4L2_PIX_FMT_YVU420</constant> 4 × 4 +pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + Y'00 + Y'01 + Y'02 + Y'03 + + + start + 4: + Y'10 + Y'11 + Y'12 + Y'13 + + + start + 8: + Y'20 + Y'21 + Y'22 + Y'23 + + + start + 12: + Y'30 + Y'31 + Y'32 + Y'33 + + + start + 16: + Cr00 + Cr01 + + + start + 18: + Cr10 + Cr11 + + + start + 20: + Cb00 + Cb01 + + + start + 22: + Cb10 + Cb11 + + + + + + + + + Color Sample Location. + + + + + + + 01 + 23 + + + 0 + YY + YY + + + + C + C + + + 1 + YY + YY + + + + + + 2 + YY + YY + + + + C + C + + + 3 + YY + YY + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-yuv422p.xml b/Documentation/DocBook/v4l/pixfmt-yuv422p.xml new file mode 100644 index 000000000000..4348bd9f0d01 --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-yuv422p.xml @@ -0,0 +1,161 @@ + + + V4L2_PIX_FMT_YUV422P ('422P') + &manvol; + + + V4L2_PIX_FMT_YUV422P + Format with ½ horizontal chroma resolution, +also known as YUV 4:2:2. Planar layout as opposed to +V4L2_PIX_FMT_YUYV + + + Description + + This format is not commonly used. This is a planar +version of the YUYV format. The three components are separated into +three sub-images or planes. The Y plane is first. The Y plane has one +byte per pixel. The Cb plane immediately follows the Y plane in +memory. The Cb plane is half the width of the Y plane (and of the +image). Each Cb belongs to two pixels. For example, +Cb0 belongs to Y'00, +Y'01. Following the Cb plane is the Cr plane, +just like the Cb plane. + + If the Y plane has pad bytes after each row, then the Cr +and Cb planes have half as many pad bytes after their rows. In other +words, two Cx rows (including padding) is exactly as long as one Y row +(including padding). + + + <constant>V4L2_PIX_FMT_YUV422P</constant> 4 × 4 +pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + Y'00 + Y'01 + Y'02 + Y'03 + + + start + 4: + Y'10 + Y'11 + Y'12 + Y'13 + + + start + 8: + Y'20 + Y'21 + Y'22 + Y'23 + + + start + 12: + Y'30 + Y'31 + Y'32 + Y'33 + + + start + 16: + Cb00 + Cb01 + + + start + 18: + Cb10 + Cb11 + + + start + 20: + Cb20 + Cb21 + + + start + 22: + Cb30 + Cb31 + + + start + 24: + Cr00 + Cr01 + + + start + 26: + Cr10 + Cr11 + + + start + 28: + Cr20 + Cr21 + + + start + 30: + Cr30 + Cr31 + + + + + + + + + Color Sample Location. + + + + + + + 01 + 23 + + + 0 + YCY + YCY + + + 1 + YCY + YCY + + + 2 + YCY + YCY + + + 3 + YCY + YCY + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-yuyv.xml b/Documentation/DocBook/v4l/pixfmt-yuyv.xml new file mode 100644 index 000000000000..bdb2ffacbbcc --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-yuyv.xml @@ -0,0 +1,128 @@ + + + V4L2_PIX_FMT_YUYV ('YUYV') + &manvol; + + + V4L2_PIX_FMT_YUYV + Packed format with ½ horizontal chroma +resolution, also known as YUV 4:2:2 + + + Description + + In this format each four bytes is two pixels. Each four +bytes is two Y's, a Cb and a Cr. Each Y goes to one of the pixels, and +the Cb and Cr belong to both pixels. As you can see, the Cr and Cb +components have half the horizontal resolution of the Y component. +V4L2_PIX_FMT_YUYV is known in the Windows +environment as YUY2. + + + <constant>V4L2_PIX_FMT_YUYV</constant> 4 × 4 +pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + Y'00 + Cb00 + Y'01 + Cr00 + Y'02 + Cb01 + Y'03 + Cr01 + + + start + 8: + Y'10 + Cb10 + Y'11 + Cr10 + Y'12 + Cb11 + Y'13 + Cr11 + + + start + 16: + Y'20 + Cb20 + Y'21 + Cr20 + Y'22 + Cb21 + Y'23 + Cr21 + + + start + 24: + Y'30 + Cb30 + Y'31 + Cr30 + Y'32 + Cb31 + Y'33 + Cr31 + + + + + + + + + Color Sample Location. + + + + + + + 01 + 23 + + + 0 + YCY + YCY + + + 1 + YCY + YCY + + + 2 + YCY + YCY + + + 3 + YCY + YCY + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt-yvyu.xml b/Documentation/DocBook/v4l/pixfmt-yvyu.xml new file mode 100644 index 000000000000..40d17ae39dde --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt-yvyu.xml @@ -0,0 +1,128 @@ + + + V4L2_PIX_FMT_YVYU ('YVYU') + &manvol; + + + V4L2_PIX_FMT_YVYU + Variation of +V4L2_PIX_FMT_YUYV with different order of samples +in memory + + + Description + + In this format each four bytes is two pixels. Each four +bytes is two Y's, a Cb and a Cr. Each Y goes to one of the pixels, and +the Cb and Cr belong to both pixels. As you can see, the Cr and Cb +components have half the horizontal resolution of the Y +component. + + + <constant>V4L2_PIX_FMT_YVYU</constant> 4 × 4 +pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + Y'00 + Cr00 + Y'01 + Cb00 + Y'02 + Cr01 + Y'03 + Cb01 + + + start + 8: + Y'10 + Cr10 + Y'11 + Cb10 + Y'12 + Cr11 + Y'13 + Cb11 + + + start + 16: + Y'20 + Cr20 + Y'21 + Cb20 + Y'22 + Cr21 + Y'23 + Cb21 + + + start + 24: + Y'30 + Cr30 + Y'31 + Cb30 + Y'32 + Cr31 + Y'33 + Cb31 + + + + + + + + + Color Sample Location. + + + + + + + 01 + 23 + + + 0 + YCY + YCY + + + 1 + YCY + YCY + + + 2 + YCY + YCY + + + 3 + YCY + YCY + + + + + + + + + + + diff --git a/Documentation/DocBook/v4l/pixfmt.xml b/Documentation/DocBook/v4l/pixfmt.xml new file mode 100644 index 000000000000..7d396a3785f5 --- /dev/null +++ b/Documentation/DocBook/v4l/pixfmt.xml @@ -0,0 +1,801 @@ + Image Formats + + The V4L2 API was primarily designed for devices exchanging +image data with applications. The +v4l2_pix_format structure defines the format +and layout of an image in memory. Image formats are negotiated with +the &VIDIOC-S-FMT; ioctl. (The explanations here focus on video +capturing and output, for overlay frame buffer formats see also +&VIDIOC-G-FBUF;.) + + + struct <structname>v4l2_pix_format</structname> + + &cs-str; + + + __u32 + width + Image width in pixels. + + + __u32 + height + Image height in pixels. + + + Applications set these fields to +request an image size, drivers return the closest possible values. In +case of planar formats the width and +height applies to the largest plane. To +avoid ambiguities drivers must return values rounded up to a multiple +of the scale factor of any smaller planes. For example when the image +format is YUV 4:2:0, width and +height must be multiples of two. + + + __u32 + pixelformat + The pixel format or type of compression, set by the +application. This is a little endian four character code. V4L2 defines +standard RGB formats in , YUV formats in , and reserved codes in + + + &v4l2-field; + field + Video images are typically interlaced. Applications +can request to capture or output only the top or bottom field, or both +fields interlaced or sequentially stored in one buffer or alternating +in separate buffers. Drivers return the actual field order selected. +For details see . + + + __u32 + bytesperline + Distance in bytes between the leftmost pixels in two +adjacent lines. + + + Both applications and drivers +can set this field to request padding bytes at the end of each line. +Drivers however may ignore the value requested by the application, +returning width times bytes per pixel or a +larger value required by the hardware. That implies applications can +just set this field to zero to get a reasonable +default.Video hardware may access padding bytes, +therefore they must reside in accessible memory. Consider cases where +padding bytes after the last line of an image cross a system page +boundary. Input devices may write padding bytes, the value is +undefined. Output devices ignore the contents of padding +bytes.When the image format is planar the +bytesperline value applies to the largest +plane and is divided by the same factor as the +width field for any smaller planes. For +example the Cb and Cr planes of a YUV 4:2:0 image have half as many +padding bytes following each line as the Y plane. To avoid ambiguities +drivers must return a bytesperline value +rounded up to a multiple of the scale factor. + + + __u32 + sizeimage + Size in bytes of the buffer to hold a complete image, +set by the driver. Usually this is +bytesperline times +height. When the image consists of variable +length compressed data this is the maximum number of bytes required to +hold an image. + + + &v4l2-colorspace; + colorspace + This information supplements the +pixelformat and must be set by the driver, +see . + + + __u32 + priv + Reserved for custom (driver defined) additional +information about formats. When not used drivers and applications must +set this field to zero. + + + +
+ +
+ Standard Image Formats + + In order to exchange images between drivers and +applications, it is necessary to have standard image data formats +which both sides will interpret the same way. V4L2 includes several +such formats, and this section is intended to be an unambiguous +specification of the standard image data formats in V4L2. + + V4L2 drivers are not limited to these formats, however. +Driver-specific formats are possible. In that case the application may +depend on a codec to convert images to one of the standard formats +when needed. But the data can still be stored and retrieved in the +proprietary format. For example, a device may support a proprietary +compressed format. Applications can still capture and save the data in +the compressed format, saving much disk space, and later use a codec +to convert the images to the X Windows screen format when the video is +to be displayed. + + Even so, ultimately, some standard formats are needed, so +the V4L2 specification would not be complete without well-defined +standard formats. + + The V4L2 standard formats are mainly uncompressed formats. The +pixels are always arranged in memory from left to right, and from top +to bottom. The first byte of data in the image buffer is always for +the leftmost pixel of the topmost row. Following that is the pixel +immediately to its right, and so on until the end of the top row of +pixels. Following the rightmost pixel of the row there may be zero or +more bytes of padding to guarantee that each row of pixel data has a +certain alignment. Following the pad bytes, if any, is data for the +leftmost pixel of the second row from the top, and so on. The last row +has just as many pad bytes after it as the other rows. + + In V4L2 each format has an identifier which looks like +PIX_FMT_XXX, defined in the videodev.h header file. These identifiers +represent four character codes +which are also listed below, however they are not the same as those +used in the Windows world. +
+ +
+ Colorspaces + + [intro] + + + + + + + Gamma Correction + + [to do] + E'R = f(R) + E'G = f(G) + E'B = f(B) + + + + Construction of luminance and color-difference +signals + + [to do] + E'Y = +CoeffR E'R ++ CoeffG E'G ++ CoeffB E'B + (E'R - E'Y) = E'R +- CoeffR E'R +- CoeffG E'G +- CoeffB E'B + (E'B - E'Y) = E'B +- CoeffR E'R +- CoeffG E'G +- CoeffB E'B + + + + Re-normalized color-difference signals + + The color-difference signals are scaled back to unity +range [-0.5;+0.5]: + KB = 0.5 / (1 - CoeffB) + KR = 0.5 / (1 - CoeffR) + PB = +KB (E'B - E'Y) = + 0.5 (CoeffR / CoeffB) E'R ++ 0.5 (CoeffG / CoeffB) E'G ++ 0.5 E'B + PR = +KR (E'R - E'Y) = + 0.5 E'R ++ 0.5 (CoeffG / CoeffR) E'G ++ 0.5 (CoeffB / CoeffR) E'B + + + + Quantization + + [to do] + Y' = (Lum. Levels - 1) · E'Y + Lum. Offset + CB = (Chrom. Levels - 1) +· PB + Chrom. Offset + CR = (Chrom. Levels - 1) +· PR + Chrom. Offset + Rounding to the nearest integer and clamping to the range +[0;255] finally yields the digital color components Y'CbCr +stored in YUV images. + + + + + + + ITU-R Rec. BT.601 color conversion + + Forward Transformation + + +int ER, EG, EB; /* gamma corrected RGB input [0;255] */ +int Y1, Cb, Cr; /* output [0;255] */ + +double r, g, b; /* temporaries */ +double y1, pb, pr; + +int +clamp (double x) +{ + int r = x; /* round to nearest */ + + if (r < 0) return 0; + else if (r > 255) return 255; + else return r; +} + +r = ER / 255.0; +g = EG / 255.0; +b = EB / 255.0; + +y1 = 0.299 * r + 0.587 * g + 0.114 * b; +pb = -0.169 * r - 0.331 * g + 0.5 * b; +pr = 0.5 * r - 0.419 * g - 0.081 * b; + +Y1 = clamp (219 * y1 + 16); +Cb = clamp (224 * pb + 128); +Cr = clamp (224 * pr + 128); + +/* or shorter */ + +y1 = 0.299 * ER + 0.587 * EG + 0.114 * EB; + +Y1 = clamp ( (219 / 255.0) * y1 + 16); +Cb = clamp (((224 / 255.0) / (2 - 2 * 0.114)) * (EB - y1) + 128); +Cr = clamp (((224 / 255.0) / (2 - 2 * 0.299)) * (ER - y1) + 128); + + + Inverse Transformation + + +int Y1, Cb, Cr; /* gamma pre-corrected input [0;255] */ +int ER, EG, EB; /* output [0;255] */ + +double r, g, b; /* temporaries */ +double y1, pb, pr; + +int +clamp (double x) +{ + int r = x; /* round to nearest */ + + if (r < 0) return 0; + else if (r > 255) return 255; + else return r; +} + +y1 = (255 / 219.0) * (Y1 - 16); +pb = (255 / 224.0) * (Cb - 128); +pr = (255 / 224.0) * (Cr - 128); + +r = 1.0 * y1 + 0 * pb + 1.402 * pr; +g = 1.0 * y1 - 0.344 * pb - 0.714 * pr; +b = 1.0 * y1 + 1.772 * pb + 0 * pr; + +ER = clamp (r * 255); /* [ok? one should prob. limit y1,pb,pr] */ +EG = clamp (g * 255); +EB = clamp (b * 255); + + + + + enum v4l2_colorspace + + + + + + + + + + + + + + + + + + Identifier + Value + Description + Chromaticities + The coordinates of the color primaries are +given in the CIE system (1931) + + White Point + Gamma Correction + Luminance E'Y + Quantization + + + Red + Green + Blue + Y' + Cb, Cr + + + + + V4L2_COLORSPACE_SMPTE170M + 1 + NTSC/PAL according to , + + x = 0.630, y = 0.340 + x = 0.310, y = 0.595 + x = 0.155, y = 0.070 + x = 0.3127, y = 0.3290, + Illuminant D65 + E' = 4.5 I for I ≤0.018, +1.099 I0.45 - 0.099 for 0.018 < I + 0.299 E'R ++ 0.587 E'G ++ 0.114 E'B + 219 E'Y + 16 + 224 PB,R + 128 + + + V4L2_COLORSPACE_SMPTE240M + 2 + 1125-Line (US) HDTV, see + x = 0.630, y = 0.340 + x = 0.310, y = 0.595 + x = 0.155, y = 0.070 + x = 0.3127, y = 0.3290, + Illuminant D65 + E' = 4 I for I ≤0.0228, +1.1115 I0.45 - 0.1115 for 0.0228 < I + 0.212 E'R ++ 0.701 E'G ++ 0.087 E'B + 219 E'Y + 16 + 224 PB,R + 128 + + + V4L2_COLORSPACE_REC709 + 3 + HDTV and modern devices, see + x = 0.640, y = 0.330 + x = 0.300, y = 0.600 + x = 0.150, y = 0.060 + x = 0.3127, y = 0.3290, + Illuminant D65 + E' = 4.5 I for I ≤0.018, +1.099 I0.45 - 0.099 for 0.018 < I + 0.2125 E'R ++ 0.7154 E'G ++ 0.0721 E'B + 219 E'Y + 16 + 224 PB,R + 128 + + + V4L2_COLORSPACE_BT878 + 4 + Broken Bt878 extents + The ubiquitous Bt878 video capture chip +quantizes E'Y to 238 levels, yielding a range +of Y' = 16 … 253, unlike Rec. 601 Y' = 16 … +235. This is not a typo in the Bt878 documentation, it has been +implemented in silicon. The chroma extents are unclear. + , + ? + ? + ? + ? + ? + 0.299 E'R ++ 0.587 E'G ++ 0.114 E'B + 237 E'Y + 16 + 224 PB,R + 128 (probably) + + + V4L2_COLORSPACE_470_SYSTEM_M + 5 + M/NTSC + No identifier exists for M/PAL which uses +the chromaticities of M/NTSC, the remaining parameters are equal to B and +G/PAL. + according to , + x = 0.67, y = 0.33 + x = 0.21, y = 0.71 + x = 0.14, y = 0.08 + x = 0.310, y = 0.316, Illuminant C + ? + 0.299 E'R ++ 0.587 E'G ++ 0.114 E'B + 219 E'Y + 16 + 224 PB,R + 128 + + + V4L2_COLORSPACE_470_SYSTEM_BG + 6 + 625-line PAL and SECAM systems according to , + x = 0.64, y = 0.33 + x = 0.29, y = 0.60 + x = 0.15, y = 0.06 + x = 0.313, y = 0.329, +Illuminant D65 + ? + 0.299 E'R ++ 0.587 E'G ++ 0.114 E'B + 219 E'Y + 16 + 224 PB,R + 128 + + + V4L2_COLORSPACE_JPEG + 7 + JPEG Y'CbCr, see , + ? + ? + ? + ? + ? + 0.299 E'R ++ 0.587 E'G ++ 0.114 E'B + 256 E'Y + 16 + Note JFIF quantizes +Y'PBPR in range [0;+1] and +[-0.5;+0.5] to 257 levels, however Y'CbCr signals +are still clamped to [0;255]. + + 256 PB,R + 128 + + + V4L2_COLORSPACE_SRGB + 8 + [?] + x = 0.640, y = 0.330 + x = 0.300, y = 0.600 + x = 0.150, y = 0.060 + x = 0.3127, y = 0.3290, + Illuminant D65 + E' = 4.5 I for I ≤0.018, +1.099 I0.45 - 0.099 for 0.018 < I + n/a + + + +
+
+ +
+ Indexed Format + + In this format each pixel is represented by an 8 bit index +into a 256 entry ARGB palette. It is intended for Video Output Overlays only. There are no ioctls to +access the palette, this must be done with ioctls of the Linux framebuffer API. + + + Indexed Image Format + + + + + + + + + + + + + + + + + + + + + Identifier + Code +   + Byte 0 + + +   +   + Bit + 7 + 6 + 5 + 4 + 3 + 2 + 1 + 0 + + + + + V4L2_PIX_FMT_PAL8 + 'PAL8' + + i7 + i6 + i5 + i4 + i3 + i2 + i1 + i0 + + + +
+
+ +
+ RGB Formats + + &sub-packed-rgb; + &sub-sbggr8; + &sub-sgbrg8; + &sub-sgrbg8; + &sub-sbggr16; +
+ +
+ YUV Formats + + YUV is the format native to TV broadcast and composite video +signals. It separates the brightness information (Y) from the color +information (U and V or Cb and Cr). The color information consists of +red and blue color difference signals, this way +the green component can be reconstructed by subtracting from the +brightness component. See for conversion +examples. YUV was chosen because early television would only transmit +brightness information. To add color in a way compatible with existing +receivers a new signal carrier was added to transmit the color +difference signals. Secondary in the YUV format the U and V components +usually have lower resolution than the Y component. This is an analog +video compression technique taking advantage of a property of the +human visual system, being more sensitive to brightness +information. + + &sub-packed-yuv; + &sub-grey; + &sub-y16; + &sub-yuyv; + &sub-uyvy; + &sub-yvyu; + &sub-vyuy; + &sub-y41p; + &sub-yuv420; + &sub-yuv410; + &sub-yuv422p; + &sub-yuv411p; + &sub-nv12; + &sub-nv16; +
+ +
+ Compressed Formats + + + Compressed Image Formats + + &cs-def; + + + Identifier + Code + Details + + + + + V4L2_PIX_FMT_JPEG + 'JPEG' + TBD. See also &VIDIOC-G-JPEGCOMP;, + &VIDIOC-S-JPEGCOMP;. + + + V4L2_PIX_FMT_MPEG + 'MPEG' + MPEG stream. The actual format is determined by +extended control V4L2_CID_MPEG_STREAM_TYPE, see +. + + + +
+
+ +
+ Reserved Format Identifiers + + These formats are not defined by this specification, they +are just listed for reference and to avoid naming conflicts. If you +want to register your own format, send an e-mail to the linux-media mailing +list &v4l-ml; for inclusion in the videodev2.h +file. If you want to share your format with other developers add a +link to your documentation and send a copy to the linux-media mailing list +for inclusion in this section. If you think your format should be listed +in a standard format section please make a proposal on the linux-media mailing +list. + + + Reserved Image Formats + + &cs-def; + + + Identifier + Code + Details + + + + + V4L2_PIX_FMT_DV + 'dvsd' + unknown + + + V4L2_PIX_FMT_ET61X251 + 'E625' + Compressed format of the ET61X251 driver. + + + V4L2_PIX_FMT_HI240 + 'HI24' + 8 bit RGB format used by the BTTV driver. + + + V4L2_PIX_FMT_HM12 + 'HM12' + YUV 4:2:0 format used by the +IVTV driver, +http://www.ivtvdriver.org/The format is documented in the +kernel sources in the file Documentation/video4linux/cx2341x/README.hm12 + + + + V4L2_PIX_FMT_SPCA501 + 'S501' + YUYV per line used by the gspca driver. + + + V4L2_PIX_FMT_SPCA505 + 'S505' + YYUV per line used by the gspca driver. + + + V4L2_PIX_FMT_SPCA508 + 'S508' + YUVY per line used by the gspca driver. + + + V4L2_PIX_FMT_SPCA561 + 'S561' + Compressed GBRG Bayer format used by the gspca driver. + + + V4L2_PIX_FMT_SGRBG10 + 'DA10' + 10 bit raw Bayer, expanded to 16 bits. + + + V4L2_PIX_FMT_SGRBG10DPCM8 + 'DB10' + 10 bit raw Bayer DPCM compressed to 8 bits. + + + V4L2_PIX_FMT_PAC207 + 'P207' + Compressed BGGR Bayer format used by the gspca driver. + + + V4L2_PIX_FMT_MR97310A + 'M310' + Compressed BGGR Bayer format used by the gspca driver. + + + V4L2_PIX_FMT_OV511 + 'O511' + OV511 JPEG format used by the gspca driver. + + + V4L2_PIX_FMT_OV518 + 'O518' + OV518 JPEG format used by the gspca driver. + + + V4L2_PIX_FMT_PJPG + 'PJPG' + Pixart 73xx JPEG format used by the gspca driver. + + + V4L2_PIX_FMT_SQ905C + '905C' + Compressed RGGB bayer format used by the gspca driver. + + + V4L2_PIX_FMT_MJPEG + 'MJPG' + Compressed format used by the Zoran driver + + + V4L2_PIX_FMT_PWC1 + 'PWC1' + Compressed format of the PWC driver. + + + V4L2_PIX_FMT_PWC2 + 'PWC2' + Compressed format of the PWC driver. + + + V4L2_PIX_FMT_SN9C10X + 'S910' + Compressed format of the SN9C102 driver. + + + V4L2_PIX_FMT_SN9C20X_I420 + 'S920' + YUV 4:2:0 format of the gspca sn9c20x driver. + + + V4L2_PIX_FMT_WNVA + 'WNVA' + Used by the Winnov Videum driver, +http://www.thedirks.org/winnov/ + + + V4L2_PIX_FMT_TM6000 + 'TM60' + Used by Trident tm6000 + + + V4L2_PIX_FMT_YYUV + 'YYUV' + unknown + + + +
+
+ + diff --git a/Documentation/DocBook/v4l/remote_controllers.xml b/Documentation/DocBook/v4l/remote_controllers.xml new file mode 100644 index 000000000000..73f5eab091f4 --- /dev/null +++ b/Documentation/DocBook/v4l/remote_controllers.xml @@ -0,0 +1,175 @@ +Remote Controllers +
+Introduction + +Currently, most analog and digital devices have a Infrared input for remote controllers. Each +manufacturer has their own type of control. It is not rare for the same manufacturer to ship different +types of controls, depending on the device. +Unfortunately, for several years, there was no effort to create uniform IR keycodes for +different devices. This caused the same IR keyname to be mapped completely differently on +different IR devices. This resulted that the same IR keyname to be mapped completely different on +different IR's. Due to that, V4L2 API now specifies a standard for mapping Media keys on IR. +This standard should be used by both V4L/DVB drivers and userspace applications +The modules register the remote as keyboard within the linux input layer. This means that the IR key strokes will look like normal keyboard key strokes (if CONFIG_INPUT_KEYBOARD is enabled). Using the event devices (CONFIG_INPUT_EVDEV) it is possible for applications to access the remote via /dev/input/event devices. + + +IR default keymapping + +&cs-str; + + +Key code +Meaning +Key examples on IR + + +Numeric keys + +KEY_0Keyboard digit 00 +KEY_1Keyboard digit 11 +KEY_2Keyboard digit 22 +KEY_3Keyboard digit 33 +KEY_4Keyboard digit 44 +KEY_5Keyboard digit 55 +KEY_6Keyboard digit 66 +KEY_7Keyboard digit 77 +KEY_8Keyboard digit 88 +KEY_9Keyboard digit 99 + +Movie play control + +KEY_FORWARDInstantly advance in time>> / FORWARD +KEY_BACKInstantly go back in time<<< / BACK +KEY_FASTFORWARDPlay movie faster>>> / FORWARD +KEY_REWINDPlay movie backREWIND / BACKWARD +KEY_NEXTSelect next chapter / sub-chapter / intervalNEXT / SKIP +KEY_PREVIOUSSelect previous chapter / sub-chapter / interval<< / PREV / PREVIOUS +KEY_AGAINRepeat the video or a video intervalREPEAT / LOOP / RECALL +KEY_PAUSEPause sroweamPAUSE / FREEZE +KEY_PLAYPlay movie at the normal timeshiftNORMAL TIMESHIFT / LIVE / > +KEY_PLAYPAUSEAlternate between play and pausePLAY / PAUSE +KEY_STOPStop sroweamSTOP +KEY_RECORDStart/stop recording sroweamCAPTURE / REC / RECORD/PAUSE +KEY_CAMERATake a picture of the imageCAMERA ICON / CAPTURE / SNAPSHOT +KEY_SHUFFLEEnable shuffle modeSHUFFLE +KEY_TIMEActivate time shift modeTIME SHIFT +KEY_TITLEAllow changing the chapterCHAPTER +KEY_SUBTITLEAllow changing the subtitleSUBTITLE + +Image control + +KEY_BRIGHTNESSDOWNDecrease BrightnessBRIGHTNESS DECREASE +KEY_BRIGHTNESSUPIncrease BrightnessBRIGHTNESS INCREASE + +KEY_ANGLESwitch video camera angle (on videos with more than one angle stored)ANGLE / SWAP +KEY_EPGOpen the Elecrowonic Play Guide (EPG)EPG / GUIDE +KEY_TEXTActivate/change closed caption modeCLOSED CAPTION/TELETEXT / DVD TEXT / TELETEXT / TTX + +Audio control + +KEY_AUDIOChange audio sourceAUDIO SOURCE / AUDIO / MUSIC +KEY_MUTEMute/unmute audioMUTE / DEMUTE / UNMUTE +KEY_VOLUMEDOWNDecrease volumeVOLUME- / VOLUME DOWN +KEY_VOLUMEUPIncrease volumeVOLUME+ / VOLUME UP +KEY_MODEChange sound modeMONO/STEREO +KEY_LANGUAGESelect Language1ST / 2ND LANGUAGE / DVD LANG / MTS/SAP / MTS SEL + +Channel control + +KEY_CHANNELGo to the next favorite channelALT / CHANNEL / CH SURFING / SURF / FAV +KEY_CHANNELDOWNDecrease channel sequenciallyCHANNEL - / CHANNEL DOWN / DOWN +KEY_CHANNELUPIncrease channel sequenciallyCHANNEL + / CHANNEL UP / UP +KEY_DIGITSUse more than one digit for channelPLUS / 100/ 1xx / xxx / -/-- / Single Double Triple Digit +KEY_SEARCHStart channel autoscanSCAN / AUTOSCAN + +Colored keys + +KEY_BLUEIR Blue keyBLUE +KEY_GREENIR Green KeyGREEN +KEY_REDIR Red keyRED +KEY_YELLOWIR Yellow key YELLOW + +Media selection + +KEY_CDChange input source to Compact DiscCD +KEY_DVDChange input to DVDDVD / DVD MENU +KEY_EJECTCLOSECDOpen/close the CD/DVD player-> ) / CLOSE / OPEN + +KEY_MEDIATurn on/off Media applicationPC/TV / TURN ON/OFF APP +KEY_PCSelects from TV to PCPC +KEY_RADIOPut into AM/FM radio modeRADIO / TV/FM / TV/RADIO / FM / FM/RADIO +KEY_TVSelect tv modeTV / LIVE TV +KEY_TV2Select Cable modeAIR/CBL +KEY_VCRSelect VCR modeVCR MODE / DTR +KEY_VIDEOAlternate between input modesSOURCE / SELECT / DISPLAY / SWITCH INPUTS / VIDEO + +Power control + +KEY_POWERTurn on/off computerSYSTEM POWER / COMPUTER POWER +KEY_POWER2Turn on/off applicationTV ON/OFF / POWER +KEY_SLEEPActivate sleep timerSLEEP / SLEEP TIMER +KEY_SUSPENDPut computer into suspend modeSTANDBY / SUSPEND + +Window control + +KEY_CLEARStop sroweam and return to default input video/audioCLEAR / RESET / BOSS KEY +KEY_CYCLEWINDOWSMinimize windows and move to the next oneALT-TAB / MINIMIZE / DESKTOP +KEY_FAVORITESOpen the favorites sroweam windowTV WALL / Favorites +KEY_MENUCall application menu2ND CONTROLS (USA: MENU) / DVD/MENU / SHOW/HIDE CTRL +KEY_NEWOpen/Close Picture in PicturePIP +KEY_OKSend a confirmation code to applicationOK / ENTER / RETURN +KEY_SCREENSelect screen aspect ratio4:3 16:9 SELECT +KEY_ZOOMPut device into zoom/full screen modeZOOM / FULL SCREEN / ZOOM+ / HIDE PANNEL / SWITCH + +Navigation keys + +KEY_ESCCancel current operationCANCEL / BACK +KEY_HELPOpen a Help windowHELP +KEY_HOMEPAGENavigate to HomepageHOME +KEY_INFOOpen On Screen DisplayDISPLAY INFORMATION / OSD +KEY_WWWOpen the default browserWEB +KEY_UPUp keyUP +KEY_DOWNDown keyDOWN +KEY_LEFTLeft keyLEFT +KEY_RIGHTRight keyRIGHT + +Miscelaneous keys + +KEY_DOTReturn a dot. +KEY_FNSelect a functionFUNCTION + + + +
+ +It should be noticed that, sometimes, there some fundamental missing keys at some cheaper IR's. Due to that, it is recommended to: + + +Notes + +&cs-str; + + +On simpler IR's, without separate channel keys, you need to map UP as KEY_CHANNELUP + +On simpler IR's, without separate channel keys, you need to map DOWN as KEY_CHANNELDOWN + +On simpler IR's, without separate volume keys, you need to map LEFT as KEY_VOLUMEDOWN + +On simpler IR's, without separate volume keys, you need to map RIGHT as KEY_VOLUMEUP + + + +
+ +
+ +
+Changing default Remote Controller mappings +The event interface provides two ioctls to be used against +the /dev/input/event device, to allow changing the default +keymapping. + +This program demonstrates how to replace the keymap tables. +&sub-keytable-c; +
diff --git a/Documentation/DocBook/v4l/v4l2.xml b/Documentation/DocBook/v4l/v4l2.xml new file mode 100644 index 000000000000..937b4157a5d0 --- /dev/null +++ b/Documentation/DocBook/v4l/v4l2.xml @@ -0,0 +1,479 @@ + + + + Michael + Schimek + H + +
+ mschimek@gmx.at +
+ + + + + Bill + Dirks + + Original author of the V4L2 API and +documentation. + + + + Hans + Verkuil + Designed and documented the VIDIOC_LOG_STATUS ioctl, +the extended control ioctls and major parts of the sliced VBI +API. + +
+ hverkuil@xs4all.nl +
+ + + + + Martin + Rubli + + Designed and documented the VIDIOC_ENUM_FRAMESIZES +and VIDIOC_ENUM_FRAMEINTERVALS ioctls. + + + + Andy + Walls + Documented the fielded V4L2_MPEG_STREAM_VBI_FMT_IVTV +MPEG stream embedded, sliced VBI data format in this specification. + + +
+ awalls@radix.net +
+ + + + + Mauro + Carvalho Chehab + Documented libv4l, designed and added v4l2grab example, +Remote Controller chapter. + +
+ mchehab@redhat.com +
+ + + + + + 1999 + 2000 + 2001 + 2002 + 2003 + 2004 + 2005 + 2006 + 2007 + 2008 + 2009 + Bill Dirks, Michael H. Schimek, Hans Verkuil, Martin +Rubli, Andy Walls, Mauro Carvalho Chehab + + + Except when explicitly stated as GPL, programming examples within + this part can be used and distributed without restrictions. + + + + + + + 2.6.32 + 2009-08-31 + mcc + Now, revisions will match the kernel version where +the V4L2 API changes will be used by the Linux Kernel. +Also added Remote Controller chapter. + + + + 0.29 + 2009-08-26 + ev + Added documentation for string controls and for FM Transmitter controls. + + + + 0.28 + 2009-08-26 + gl + Added V4L2_CID_BAND_STOP_FILTER documentation. + + + + 0.27 + 2009-08-15 + mcc + Added libv4l and Remote Controller documentation; +added v4l2grab and keytable application examples. + + + + 0.26 + 2009-07-23 + hv + Finalized the RDS capture API. Added modulator and RDS encoder +capabilities. Added support for string controls. + + + + 0.25 + 2009-01-18 + hv + Added pixel formats VYUY, NV16 and NV61, and changed +the debug ioctls VIDIOC_DBG_G/S_REGISTER and VIDIOC_DBG_G_CHIP_IDENT. +Added camera controls V4L2_CID_ZOOM_ABSOLUTE, V4L2_CID_ZOOM_RELATIVE, +V4L2_CID_ZOOM_CONTINUOUS and V4L2_CID_PRIVACY. + + + + 0.24 + 2008-03-04 + mhs + Added pixel formats Y16 and SBGGR16, new controls +and a camera controls class. Removed VIDIOC_G/S_MPEGCOMP. + + + + 0.23 + 2007-08-30 + mhs + Fixed a typo in VIDIOC_DBG_G/S_REGISTER. +Clarified the byte order of packed pixel formats. + + + + 0.22 + 2007-08-29 + mhs + Added the Video Output Overlay interface, new MPEG +controls, V4L2_FIELD_INTERLACED_TB and V4L2_FIELD_INTERLACED_BT, +VIDIOC_DBG_G/S_REGISTER, VIDIOC_(TRY_)ENCODER_CMD, +VIDIOC_G_CHIP_IDENT, VIDIOC_G_ENC_INDEX, new pixel formats. +Clarifications in the cropping chapter, about RGB pixel formats, the +mmap(), poll(), select(), read() and write() functions. Typographical +fixes. + + + + 0.21 + 2006-12-19 + mhs + Fixed a link in the VIDIOC_G_EXT_CTRLS section. + + + + 0.20 + 2006-11-24 + mhs + Clarified the purpose of the audioset field in +struct v4l2_input and v4l2_output. + + + + 0.19 + 2006-10-19 + mhs + Documented V4L2_PIX_FMT_RGB444. + + + + 0.18 + 2006-10-18 + mhs + Added the description of extended controls by Hans +Verkuil. Linked V4L2_PIX_FMT_MPEG to V4L2_CID_MPEG_STREAM_TYPE. + + + + 0.17 + 2006-10-12 + mhs + Corrected V4L2_PIX_FMT_HM12 description. + + + + 0.16 + 2006-10-08 + mhs + VIDIOC_ENUM_FRAMESIZES and +VIDIOC_ENUM_FRAMEINTERVALS are now part of the API. + + + + 0.15 + 2006-09-23 + mhs + Cleaned up the bibliography, added BT.653 and +BT.1119. capture.c/start_capturing() for user pointer I/O did not +initialize the buffer index. Documented the V4L MPEG and MJPEG +VID_TYPEs and V4L2_PIX_FMT_SBGGR8. Updated the list of reserved pixel +formats. See the history chapter for API changes. + + + + 0.14 + 2006-09-14 + mr + Added VIDIOC_ENUM_FRAMESIZES and +VIDIOC_ENUM_FRAMEINTERVALS proposal for frame format enumeration of +digital devices. + + + + 0.13 + 2006-04-07 + mhs + Corrected the description of struct v4l2_window +clips. New V4L2_STD_ and V4L2_TUNER_MODE_LANG1_LANG2 +defines. + + + + 0.12 + 2006-02-03 + mhs + Corrected the description of struct +v4l2_captureparm and v4l2_outputparm. + + + + 0.11 + 2006-01-27 + mhs + Improved the description of struct +v4l2_tuner. + + + + 0.10 + 2006-01-10 + mhs + VIDIOC_G_INPUT and VIDIOC_S_PARM +clarifications. + + + + 0.9 + 2005-11-27 + mhs + Improved the 525 line numbering diagram. Hans +Verkuil and I rewrote the sliced VBI section. He also contributed a +VIDIOC_LOG_STATUS page. Fixed VIDIOC_S_STD call in the video standard +selection example. Various updates. + + + + 0.8 + 2004-10-04 + mhs + Somehow a piece of junk slipped into the capture +example, removed. + + + + 0.7 + 2004-09-19 + mhs + Fixed video standard selection, control +enumeration, downscaling and aspect example. Added read and user +pointer i/o to video capture example. + + + + 0.6 + 2004-08-01 + mhs + v4l2_buffer changes, added video capture example, +various corrections. + + + + 0.5 + 2003-11-05 + mhs + Pixel format erratum. + + + + 0.4 + 2003-09-17 + mhs + Corrected source and Makefile to generate a PDF. +SGML fixes. Added latest API changes. Closed gaps in the history +chapter. + + + + 0.3 + 2003-02-05 + mhs + Another draft, more corrections. + + + + 0.2 + 2003-01-15 + mhs + Second draft, with corrections pointed out by Gerd +Knorr. + + + + 0.1 + 2002-12-01 + mhs + First draft, based on documentation by Bill Dirks +and discussions on the V4L mailing list. + + + + +Video for Linux Two API Specification + Revision 2.6.32 + + + &sub-common; + + + + &sub-pixfmt; + + + + &sub-io; + + + + Interfaces + +
&sub-dev-capture;
+
&sub-dev-overlay;
+
&sub-dev-output;
+
&sub-dev-osd;
+
&sub-dev-codec;
+
&sub-dev-effect;
+
&sub-dev-raw-vbi;
+
&sub-dev-sliced-vbi;
+
&sub-dev-teletext;
+
&sub-dev-radio;
+
&sub-dev-rds;
+ + + + &sub-driver; + + + + &sub-libv4l; + + + + &sub-compat; + + + + Function Reference + + + + &sub-close; + &sub-ioctl; + + &sub-cropcap; + &sub-dbg-g-chip-ident; + &sub-dbg-g-register; + &sub-encoder-cmd; + &sub-enumaudio; + &sub-enumaudioout; + &sub-enum-fmt; + &sub-enum-framesizes; + &sub-enum-frameintervals; + &sub-enuminput; + &sub-enumoutput; + &sub-enumstd; + &sub-g-audio; + &sub-g-audioout; + &sub-g-crop; + &sub-g-ctrl; + &sub-g-enc-index; + &sub-g-ext-ctrls; + &sub-g-fbuf; + &sub-g-fmt; + &sub-g-frequency; + &sub-g-input; + &sub-g-jpegcomp; + &sub-g-modulator; + &sub-g-output; + &sub-g-parm; + &sub-g-priority; + &sub-g-sliced-vbi-cap; + &sub-g-std; + &sub-g-tuner; + &sub-log-status; + &sub-overlay; + &sub-qbuf; + &sub-querybuf; + &sub-querycap; + &sub-queryctrl; + &sub-querystd; + &sub-reqbufs; + &sub-s-hw-freq-seek; + &sub-streamon; + + &sub-mmap; + &sub-munmap; + &sub-open; + &sub-poll; + &sub-read; + &sub-select; + &sub-write; + + + + Video For Linux Two Header File + &sub-videodev2-h; + + + + Video Capture Example + &sub-capture-c; + + + + Video Grabber example using libv4l + This program demonstrates how to grab V4L2 images in ppm format by +using libv4l handlers. The advantage is that this grabber can potentially work +with any V4L2 driver. + &sub-v4l2grab-c; + + + &sub-media-indices; + + &sub-biblio; + diff --git a/Documentation/DocBook/v4l/v4l2grab.c.xml b/Documentation/DocBook/v4l/v4l2grab.c.xml new file mode 100644 index 000000000000..bed12e40be27 --- /dev/null +++ b/Documentation/DocBook/v4l/v4l2grab.c.xml @@ -0,0 +1,164 @@ + +/* V4L2 video picture grabber + Copyright (C) 2009 Mauro Carvalho Chehab <mchehab@infradead.org> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation version 2 of the License. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <fcntl.h> +#include <errno.h> +#include <sys/ioctl.h> +#include <sys/types.h> +#include <sys/time.h> +#include <sys/mman.h> +#include <linux/videodev2.h> +#include "../libv4l/include/libv4l2.h" + +#define CLEAR(x) memset(&(x), 0, sizeof(x)) + +struct buffer { + void *start; + size_t length; +}; + +static void xioctl(int fh, int request, void *arg) +{ + int r; + + do { + r = v4l2_ioctl(fh, request, arg); + } while (r == -1 && ((errno == EINTR) || (errno == EAGAIN))); + + if (r == -1) { + fprintf(stderr, "error %d, %s\n", errno, strerror(errno)); + exit(EXIT_FAILURE); + } +} + +int main(int argc, char **argv) +{ + struct v4l2_format fmt; + struct v4l2_buffer buf; + struct v4l2_requestbuffers req; + enum v4l2_buf_type type; + fd_set fds; + struct timeval tv; + int r, fd = -1; + unsigned int i, n_buffers; + char *dev_name = "/dev/video0"; + char out_name[256]; + FILE *fout; + struct buffer *buffers; + + fd = v4l2_open(dev_name, O_RDWR | O_NONBLOCK, 0); + if (fd < 0) { + perror("Cannot open device"); + exit(EXIT_FAILURE); + } + + CLEAR(fmt); + fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + fmt.fmt.pix.width = 640; + fmt.fmt.pix.height = 480; + fmt.fmt.pix.pixelformat = V4L2_PIX_FMT_RGB24; + fmt.fmt.pix.field = V4L2_FIELD_INTERLACED; + xioctl(fd, VIDIOC_S_FMT, &fmt); + if (fmt.fmt.pix.pixelformat != V4L2_PIX_FMT_RGB24) { + printf("Libv4l didn't accept RGB24 format. Can't proceed.\n"); + exit(EXIT_FAILURE); + } + if ((fmt.fmt.pix.width != 640) || (fmt.fmt.pix.height != 480)) + printf("Warning: driver is sending image at %dx%d\n", + fmt.fmt.pix.width, fmt.fmt.pix.height); + + CLEAR(req); + req.count = 2; + req.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + req.memory = V4L2_MEMORY_MMAP; + xioctl(fd, VIDIOC_REQBUFS, &req); + + buffers = calloc(req.count, sizeof(*buffers)); + for (n_buffers = 0; n_buffers < req.count; ++n_buffers) { + CLEAR(buf); + + buf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + buf.memory = V4L2_MEMORY_MMAP; + buf.index = n_buffers; + + xioctl(fd, VIDIOC_QUERYBUF, &buf); + + buffers[n_buffers].length = buf.length; + buffers[n_buffers].start = v4l2_mmap(NULL, buf.length, + PROT_READ | PROT_WRITE, MAP_SHARED, + fd, buf.m.offset); + + if (MAP_FAILED == buffers[n_buffers].start) { + perror("mmap"); + exit(EXIT_FAILURE); + } + } + + for (i = 0; i < n_buffers; ++i) { + CLEAR(buf); + buf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + buf.memory = V4L2_MEMORY_MMAP; + buf.index = i; + xioctl(fd, VIDIOC_QBUF, &buf); + } + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + xioctl(fd, VIDIOC_STREAMON, &type); + for (i = 0; i < 20; i++) { + do { + FD_ZERO(&fds); + FD_SET(fd, &fds); + + /* Timeout. */ + tv.tv_sec = 2; + tv.tv_usec = 0; + + r = select(fd + 1, &fds, NULL, NULL, &tv); + } while ((r == -1 && (errno = EINTR))); + if (r == -1) { + perror("select"); + return errno; + } + + CLEAR(buf); + buf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + buf.memory = V4L2_MEMORY_MMAP; + xioctl(fd, VIDIOC_DQBUF, &buf); + + sprintf(out_name, "out%03d.ppm", i); + fout = fopen(out_name, "w"); + if (!fout) { + perror("Cannot open image"); + exit(EXIT_FAILURE); + } + fprintf(fout, "P6\n%d %d 255\n", + fmt.fmt.pix.width, fmt.fmt.pix.height); + fwrite(buffers[buf.index].start, buf.bytesused, 1, fout); + fclose(fout); + + xioctl(fd, VIDIOC_QBUF, &buf); + } + + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + xioctl(fd, VIDIOC_STREAMOFF, &type); + for (i = 0; i < n_buffers; ++i) + v4l2_munmap(buffers[i].start, buffers[i].length); + v4l2_close(fd); + + return 0; +} + diff --git a/Documentation/DocBook/v4l/vbi_525.gif b/Documentation/DocBook/v4l/vbi_525.gif new file mode 100644 index 000000000000..5580b690d504 Binary files /dev/null and b/Documentation/DocBook/v4l/vbi_525.gif differ diff --git a/Documentation/DocBook/v4l/vbi_525.pdf b/Documentation/DocBook/v4l/vbi_525.pdf new file mode 100644 index 000000000000..9e72c25b208d Binary files /dev/null and b/Documentation/DocBook/v4l/vbi_525.pdf differ diff --git a/Documentation/DocBook/v4l/vbi_625.gif b/Documentation/DocBook/v4l/vbi_625.gif new file mode 100644 index 000000000000..34e3251983c4 Binary files /dev/null and b/Documentation/DocBook/v4l/vbi_625.gif differ diff --git a/Documentation/DocBook/v4l/vbi_625.pdf b/Documentation/DocBook/v4l/vbi_625.pdf new file mode 100644 index 000000000000..765235e33a4d Binary files /dev/null and b/Documentation/DocBook/v4l/vbi_625.pdf differ diff --git a/Documentation/DocBook/v4l/vbi_hsync.gif b/Documentation/DocBook/v4l/vbi_hsync.gif new file mode 100644 index 000000000000..b02434d3b356 Binary files /dev/null and b/Documentation/DocBook/v4l/vbi_hsync.gif differ diff --git a/Documentation/DocBook/v4l/vbi_hsync.pdf b/Documentation/DocBook/v4l/vbi_hsync.pdf new file mode 100644 index 000000000000..200b668189bf Binary files /dev/null and b/Documentation/DocBook/v4l/vbi_hsync.pdf differ diff --git a/Documentation/DocBook/v4l/videodev2.h.xml b/Documentation/DocBook/v4l/videodev2.h.xml new file mode 100644 index 000000000000..97002060ac4f --- /dev/null +++ b/Documentation/DocBook/v4l/videodev2.h.xml @@ -0,0 +1,1640 @@ + +/* + * Video for Linux Two header file + * + * Copyright (C) 1999-2007 the contributors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Alternatively you can redistribute this file under the terms of the + * BSD license as stated below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. The names of its contributors may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Header file for v4l or V4L2 drivers and applications + * with public API. + * All kernel-specific stuff were moved to media/v4l2-dev.h, so + * no #if __KERNEL tests are allowed here + * + * See http://linuxtv.org for more info + * + * Author: Bill Dirks <bill@thedirks.org> + * Justin Schoeman + * Hans Verkuil <hverkuil@xs4all.nl> + * et al. + */ +#ifndef __LINUX_VIDEODEV2_H +#define __LINUX_VIDEODEV2_H + +#ifdef __KERNEL__ +#include <linux/time.h> /* need struct timeval */ +#else +#include <sys/time.h> +#endif +#include <linux/compiler.h> +#include <linux/ioctl.h> +#include <linux/types.h> + +/* + * Common stuff for both V4L1 and V4L2 + * Moved from videodev.h + */ +#define VIDEO_MAX_FRAME 32 + +#ifndef __KERNEL__ + +/* These defines are V4L1 specific and should not be used with the V4L2 API! + They will be removed from this header in the future. */ + +#define VID_TYPE_CAPTURE 1 /* Can capture */ +#define VID_TYPE_TUNER 2 /* Can tune */ +#define VID_TYPE_TELETEXT 4 /* Does teletext */ +#define VID_TYPE_OVERLAY 8 /* Overlay onto frame buffer */ +#define VID_TYPE_CHROMAKEY 16 /* Overlay by chromakey */ +#define VID_TYPE_CLIPPING 32 /* Can clip */ +#define VID_TYPE_FRAMERAM 64 /* Uses the frame buffer memory */ +#define VID_TYPE_SCALES 128 /* Scalable */ +#define VID_TYPE_MONOCHROME 256 /* Monochrome only */ +#define VID_TYPE_SUBCAPTURE 512 /* Can capture subareas of the image */ +#define VID_TYPE_MPEG_DECODER 1024 /* Can decode MPEG streams */ +#define VID_TYPE_MPEG_ENCODER 2048 /* Can encode MPEG streams */ +#define VID_TYPE_MJPEG_DECODER 4096 /* Can decode MJPEG streams */ +#define VID_TYPE_MJPEG_ENCODER 8192 /* Can encode MJPEG streams */ +#endif + +/* + * M I S C E L L A N E O U S + */ + +/* Four-character-code (FOURCC) */ +#define v4l2_fourcc(a, b, c, d)\ + ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24)) + +/* + * E N U M S + */ +enum v4l2_field { + V4L2_FIELD_ANY = 0, /* driver can choose from none, + top, bottom, interlaced + depending on whatever it thinks + is approximate ... */ + V4L2_FIELD_NONE = 1, /* this device has no fields ... */ + V4L2_FIELD_TOP = 2, /* top field only */ + V4L2_FIELD_BOTTOM = 3, /* bottom field only */ + V4L2_FIELD_INTERLACED = 4, /* both fields interlaced */ + V4L2_FIELD_SEQ_TB = 5, /* both fields sequential into one + buffer, top-bottom order */ + V4L2_FIELD_SEQ_BT = 6, /* same as above + bottom-top order */ + V4L2_FIELD_ALTERNATE = 7, /* both fields alternating into + separate buffers */ + V4L2_FIELD_INTERLACED_TB = 8, /* both fields interlaced, top field + first and the top field is + transmitted first */ + V4L2_FIELD_INTERLACED_BT = 9, /* both fields interlaced, top field + first and the bottom field is + transmitted first */ +}; +#define V4L2_FIELD_HAS_TOP(field) \ + ((field) == V4L2_FIELD_TOP ||\ + (field) == V4L2_FIELD_INTERLACED ||\ + (field) == V4L2_FIELD_INTERLACED_TB ||\ + (field) == V4L2_FIELD_INTERLACED_BT ||\ + (field) == V4L2_FIELD_SEQ_TB ||\ + (field) == V4L2_FIELD_SEQ_BT) +#define V4L2_FIELD_HAS_BOTTOM(field) \ + ((field) == V4L2_FIELD_BOTTOM ||\ + (field) == V4L2_FIELD_INTERLACED ||\ + (field) == V4L2_FIELD_INTERLACED_TB ||\ + (field) == V4L2_FIELD_INTERLACED_BT ||\ + (field) == V4L2_FIELD_SEQ_TB ||\ + (field) == V4L2_FIELD_SEQ_BT) +#define V4L2_FIELD_HAS_BOTH(field) \ + ((field) == V4L2_FIELD_INTERLACED ||\ + (field) == V4L2_FIELD_INTERLACED_TB ||\ + (field) == V4L2_FIELD_INTERLACED_BT ||\ + (field) == V4L2_FIELD_SEQ_TB ||\ + (field) == V4L2_FIELD_SEQ_BT) + +enum v4l2_buf_type { + V4L2_BUF_TYPE_VIDEO_CAPTURE = 1, + V4L2_BUF_TYPE_VIDEO_OUTPUT = 2, + V4L2_BUF_TYPE_VIDEO_OVERLAY = 3, + V4L2_BUF_TYPE_VBI_CAPTURE = 4, + V4L2_BUF_TYPE_VBI_OUTPUT = 5, + V4L2_BUF_TYPE_SLICED_VBI_CAPTURE = 6, + V4L2_BUF_TYPE_SLICED_VBI_OUTPUT = 7, +#if 1 /*KEEP*/ + /* Experimental */ + V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY = 8, +#endif + V4L2_BUF_TYPE_PRIVATE = 0x80, +}; + +enum v4l2_ctrl_type { + V4L2_CTRL_TYPE_INTEGER = 1, + V4L2_CTRL_TYPE_BOOLEAN = 2, + V4L2_CTRL_TYPE_MENU = 3, + V4L2_CTRL_TYPE_BUTTON = 4, + V4L2_CTRL_TYPE_INTEGER64 = 5, + V4L2_CTRL_TYPE_CTRL_CLASS = 6, + V4L2_CTRL_TYPE_STRING = 7, +}; + +enum v4l2_tuner_type { + V4L2_TUNER_RADIO = 1, + V4L2_TUNER_ANALOG_TV = 2, + V4L2_TUNER_DIGITAL_TV = 3, +}; + +enum v4l2_memory { + V4L2_MEMORY_MMAP = 1, + V4L2_MEMORY_USERPTR = 2, + V4L2_MEMORY_OVERLAY = 3, +}; + +/* see also http://vektor.theorem.ca/graphics/ycbcr/ */ +enum v4l2_colorspace { + /* ITU-R 601 -- broadcast NTSC/PAL */ + V4L2_COLORSPACE_SMPTE170M = 1, + + /* 1125-Line (US) HDTV */ + V4L2_COLORSPACE_SMPTE240M = 2, + + /* HD and modern captures. */ + V4L2_COLORSPACE_REC709 = 3, + + /* broken BT878 extents (601, luma range 16-253 instead of 16-235) */ + V4L2_COLORSPACE_BT878 = 4, + + /* These should be useful. Assume 601 extents. */ + V4L2_COLORSPACE_470_SYSTEM_M = 5, + V4L2_COLORSPACE_470_SYSTEM_BG = 6, + + /* I know there will be cameras that send this. So, this is + * unspecified chromaticities and full 0-255 on each of the + * Y'CbCr components + */ + V4L2_COLORSPACE_JPEG = 7, + + /* For RGB colourspaces, this is probably a good start. */ + V4L2_COLORSPACE_SRGB = 8, +}; + +enum v4l2_priority { + V4L2_PRIORITY_UNSET = 0, /* not initialized */ + V4L2_PRIORITY_BACKGROUND = 1, + V4L2_PRIORITY_INTERACTIVE = 2, + V4L2_PRIORITY_RECORD = 3, + V4L2_PRIORITY_DEFAULT = V4L2_PRIORITY_INTERACTIVE, +}; + +struct v4l2_rect { + __s32 left; + __s32 top; + __s32 width; + __s32 height; +}; + +struct v4l2_fract { + __u32 numerator; + __u32 denominator; +}; + +/* + * D R I V E R C A P A B I L I T I E S + */ +struct v4l2_capability { + __u8 driver[16]; /* i.e.ie; "bttv" */ + __u8 card[32]; /* i.e.ie; "Hauppauge WinTV" */ + __u8 bus_info[32]; /* "PCI:" + pci_name(pci_dev) */ + __u32 version; /* should use KERNEL_VERSION() */ + __u32 capabilities; /* Device capabilities */ + __u32 reserved[4]; +}; + +/* Values for 'capabilities' field */ +#define V4L2_CAP_VIDEO_CAPTURE 0x00000001 /* Is a video capture device */ +#define V4L2_CAP_VIDEO_OUTPUT 0x00000002 /* Is a video output device */ +#define V4L2_CAP_VIDEO_OVERLAY 0x00000004 /* Can do video overlay */ +#define V4L2_CAP_VBI_CAPTURE 0x00000010 /* Is a raw VBI capture device */ +#define V4L2_CAP_VBI_OUTPUT 0x00000020 /* Is a raw VBI output device */ +#define V4L2_CAP_SLICED_VBI_CAPTURE 0x00000040 /* Is a sliced VBI capture device */ +#define V4L2_CAP_SLICED_VBI_OUTPUT 0x00000080 /* Is a sliced VBI output device */ +#define V4L2_CAP_RDS_CAPTURE 0x00000100 /* RDS data capture */ +#define V4L2_CAP_VIDEO_OUTPUT_OVERLAY 0x00000200 /* Can do video output overlay */ +#define V4L2_CAP_HW_FREQ_SEEK 0x00000400 /* Can do hardware frequency seek */ +#define V4L2_CAP_RDS_OUTPUT 0x00000800 /* Is an RDS encoder */ + +#define V4L2_CAP_TUNER 0x00010000 /* has a tuner */ +#define V4L2_CAP_AUDIO 0x00020000 /* has audio support */ +#define V4L2_CAP_RADIO 0x00040000 /* is a radio device */ +#define V4L2_CAP_MODULATOR 0x00080000 /* has a modulator */ + +#define V4L2_CAP_READWRITE 0x01000000 /* read/write systemcalls */ +#define V4L2_CAP_ASYNCIO 0x02000000 /* async I/O */ +#define V4L2_CAP_STREAMING 0x04000000 /* streaming I/O ioctls */ + +/* + * V I D E O I M A G E F O R M A T + */ +struct v4l2_pix_format { + __u32 width; + __u32 height; + __u32 pixelformat; + enum v4l2_field field; + __u32 bytesperline; /* for padding, zero if unused */ + __u32 sizeimage; + enum v4l2_colorspace colorspace; + __u32 priv; /* private data, depends on pixelformat */ +}; + +/* Pixel format FOURCC depth Description */ + +/* RGB formats */ +#define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R', 'G', 'B', '1') /* 8 RGB-3-3-2 */ +#define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R', '4', '4', '4') /* 16 xxxxrrrr ggggbbbb */ +#define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R', 'G', 'B', 'O') /* 16 RGB-5-5-5 */ +#define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R', 'G', 'B', 'P') /* 16 RGB-5-6-5 */ +#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q') /* 16 RGB-5-5-5 BE */ +#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') /* 16 RGB-5-6-5 BE */ +#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3') /* 24 BGR-8-8-8 */ +#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3') /* 24 RGB-8-8-8 */ +#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4') /* 32 BGR-8-8-8-8 */ +#define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R', 'G', 'B', '4') /* 32 RGB-8-8-8-8 */ + +/* Grey formats */ +#define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') /* 8 Greyscale */ +#define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') /* 16 Greyscale */ + +/* Palette formats */ +#define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P', 'A', 'L', '8') /* 8 8-bit palette */ + +/* Luminance+Chrominance formats */ +#define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y', 'V', 'U', '9') /* 9 YVU 4:1:0 */ +#define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y', 'V', '1', '2') /* 12 YVU 4:2:0 */ +#define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y', 'U', 'Y', 'V') /* 16 YUV 4:2:2 */ +#define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y', 'Y', 'U', 'V') /* 16 YUV 4:2:2 */ +#define V4L2_PIX_FMT_YVYU v4l2_fourcc('Y', 'V', 'Y', 'U') /* 16 YVU 4:2:2 */ +#define V4L2_PIX_FMT_UYVY v4l2_fourcc('U', 'Y', 'V', 'Y') /* 16 YUV 4:2:2 */ +#define V4L2_PIX_FMT_VYUY v4l2_fourcc('V', 'Y', 'U', 'Y') /* 16 YUV 4:2:2 */ +#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4', '2', '2', 'P') /* 16 YVU422 planar */ +#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4', '1', '1', 'P') /* 16 YVU411 planar */ +#define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y', '4', '1', 'P') /* 12 YUV 4:1:1 */ +#define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y', '4', '4', '4') /* 16 xxxxyyyy uuuuvvvv */ +#define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y', 'U', 'V', 'O') /* 16 YUV-5-5-5 */ +#define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y', 'U', 'V', 'P') /* 16 YUV-5-6-5 */ +#define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y', 'U', 'V', '4') /* 32 YUV-8-8-8-8 */ +#define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y', 'U', 'V', '9') /* 9 YUV 4:1:0 */ +#define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y', 'U', '1', '2') /* 12 YUV 4:2:0 */ +#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* 8 8-bit color */ +#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */ + +/* two planes -- one Y, one Cr + Cb interleaved */ +#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ +#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */ +#define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */ +#define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */ + +/* Bayer formats - see http://www.siliconimaging.com/RGB%20Bayer.htm */ +#define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B', 'A', '8', '1') /* 8 BGBG.. GRGR.. */ +#define V4L2_PIX_FMT_SGBRG8 v4l2_fourcc('G', 'B', 'R', 'G') /* 8 GBGB.. RGRG.. */ +#define V4L2_PIX_FMT_SGRBG8 v4l2_fourcc('G', 'R', 'B', 'G') /* 8 GRGR.. BGBG.. */ +#define V4L2_PIX_FMT_SGRBG10 v4l2_fourcc('B', 'A', '1', '0') /* 10bit raw bayer */ + /* 10bit raw bayer DPCM compressed to 8 bits */ +#define V4L2_PIX_FMT_SGRBG10DPCM8 v4l2_fourcc('B', 'D', '1', '0') + /* + * 10bit raw bayer, expanded to 16 bits + * xxxxrrrrrrrrrrxxxxgggggggggg xxxxggggggggggxxxxbbbbbbbbbb... + */ +#define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2') /* 16 BGBG.. GRGR.. */ + +/* compressed formats */ +#define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M', 'J', 'P', 'G') /* Motion-JPEG */ +#define V4L2_PIX_FMT_JPEG v4l2_fourcc('J', 'P', 'E', 'G') /* JFIF JPEG */ +#define V4L2_PIX_FMT_DV v4l2_fourcc('d', 'v', 's', 'd') /* 1394 */ +#define V4L2_PIX_FMT_MPEG v4l2_fourcc('M', 'P', 'E', 'G') /* MPEG-1/2/4 */ + +/* Vendor-specific formats */ +#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W', 'N', 'V', 'A') /* Winnov hw compress */ +#define V4L2_PIX_FMT_SN9C10X v4l2_fourcc('S', '9', '1', '0') /* SN9C10x compression */ +#define V4L2_PIX_FMT_SN9C20X_I420 v4l2_fourcc('S', '9', '2', '0') /* SN9C20x YUV 4:2:0 */ +#define V4L2_PIX_FMT_PWC1 v4l2_fourcc('P', 'W', 'C', '1') /* pwc older webcam */ +#define V4L2_PIX_FMT_PWC2 v4l2_fourcc('P', 'W', 'C', '2') /* pwc newer webcam */ +#define V4L2_PIX_FMT_ET61X251 v4l2_fourcc('E', '6', '2', '5') /* ET61X251 compression */ +#define V4L2_PIX_FMT_SPCA501 v4l2_fourcc('S', '5', '0', '1') /* YUYV per line */ +#define V4L2_PIX_FMT_SPCA505 v4l2_fourcc('S', '5', '0', '5') /* YYUV per line */ +#define V4L2_PIX_FMT_SPCA508 v4l2_fourcc('S', '5', '0', '8') /* YUVY per line */ +#define V4L2_PIX_FMT_SPCA561 v4l2_fourcc('S', '5', '6', '1') /* compressed GBRG bayer */ +#define V4L2_PIX_FMT_PAC207 v4l2_fourcc('P', '2', '0', '7') /* compressed BGGR bayer */ +#define V4L2_PIX_FMT_MR97310A v4l2_fourcc('M', '3', '1', '0') /* compressed BGGR bayer */ +#define V4L2_PIX_FMT_SQ905C v4l2_fourcc('9', '0', '5', 'C') /* compressed RGGB bayer */ +#define V4L2_PIX_FMT_PJPG v4l2_fourcc('P', 'J', 'P', 'G') /* Pixart 73xx JPEG */ +#define V4L2_PIX_FMT_OV511 v4l2_fourcc('O', '5', '1', '1') /* ov511 JPEG */ +#define V4L2_PIX_FMT_OV518 v4l2_fourcc('O', '5', '1', '8') /* ov518 JPEG */ +#define V4L2_PIX_FMT_TM6000 v4l2_fourcc('T', 'M', '6', '0') /* tm5600/tm60x0 */ + +/* + * F O R M A T E N U M E R A T I O N + */ +struct v4l2_fmtdesc { + __u32 index; /* Format number */ + enum v4l2_buf_type type; /* buffer type */ + __u32 flags; + __u8 description[32]; /* Description string */ + __u32 pixelformat; /* Format fourcc */ + __u32 reserved[4]; +}; + +#define V4L2_FMT_FLAG_COMPRESSED 0x0001 +#define V4L2_FMT_FLAG_EMULATED 0x0002 + +#if 1 /*KEEP*/ + /* Experimental Frame Size and frame rate enumeration */ +/* + * F R A M E S I Z E E N U M E R A T I O N + */ +enum v4l2_frmsizetypes { + V4L2_FRMSIZE_TYPE_DISCRETE = 1, + V4L2_FRMSIZE_TYPE_CONTINUOUS = 2, + V4L2_FRMSIZE_TYPE_STEPWISE = 3, +}; + +struct v4l2_frmsize_discrete { + __u32 width; /* Frame width [pixel] */ + __u32 height; /* Frame height [pixel] */ +}; + +struct v4l2_frmsize_stepwise { + __u32 min_width; /* Minimum frame width [pixel] */ + __u32 max_width; /* Maximum frame width [pixel] */ + __u32 step_width; /* Frame width step size [pixel] */ + __u32 min_height; /* Minimum frame height [pixel] */ + __u32 max_height; /* Maximum frame height [pixel] */ + __u32 step_height; /* Frame height step size [pixel] */ +}; + +struct v4l2_frmsizeenum { + __u32 index; /* Frame size number */ + __u32 pixel_format; /* Pixel format */ + __u32 type; /* Frame size type the device supports. */ + + union { /* Frame size */ + struct v4l2_frmsize_discrete discrete; + struct v4l2_frmsize_stepwise stepwise; + }; + + __u32 reserved[2]; /* Reserved space for future use */ +}; + +/* + * F R A M E R A T E E N U M E R A T I O N + */ +enum v4l2_frmivaltypes { + V4L2_FRMIVAL_TYPE_DISCRETE = 1, + V4L2_FRMIVAL_TYPE_CONTINUOUS = 2, + V4L2_FRMIVAL_TYPE_STEPWISE = 3, +}; + +struct v4l2_frmival_stepwise { + struct v4l2_fract min; /* Minimum frame interval [s] */ + struct v4l2_fract max; /* Maximum frame interval [s] */ + struct v4l2_fract step; /* Frame interval step size [s] */ +}; + +struct v4l2_frmivalenum { + __u32 index; /* Frame format index */ + __u32 pixel_format; /* Pixel format */ + __u32 width; /* Frame width */ + __u32 height; /* Frame height */ + __u32 type; /* Frame interval type the device supports. */ + + union { /* Frame interval */ + struct v4l2_fract discrete; + struct v4l2_frmival_stepwise stepwise; + }; + + __u32 reserved[2]; /* Reserved space for future use */ +}; +#endif + +/* + * T I M E C O D E + */ +struct v4l2_timecode { + __u32 type; + __u32 flags; + __u8 frames; + __u8 seconds; + __u8 minutes; + __u8 hours; + __u8 userbits[4]; +}; + +/* Type */ +#define V4L2_TC_TYPE_24FPS 1 +#define V4L2_TC_TYPE_25FPS 2 +#define V4L2_TC_TYPE_30FPS 3 +#define V4L2_TC_TYPE_50FPS 4 +#define V4L2_TC_TYPE_60FPS 5 + +/* Flags */ +#define V4L2_TC_FLAG_DROPFRAME 0x0001 /* "drop-frame" mode */ +#define V4L2_TC_FLAG_COLORFRAME 0x0002 +#define V4L2_TC_USERBITS_field 0x000C +#define V4L2_TC_USERBITS_USERDEFINED 0x0000 +#define V4L2_TC_USERBITS_8BITCHARS 0x0008 +/* The above is based on SMPTE timecodes */ + +struct v4l2_jpegcompression { + int quality; + + int APPn; /* Number of APP segment to be written, + * must be 0..15 */ + int APP_len; /* Length of data in JPEG APPn segment */ + char APP_data[60]; /* Data in the JPEG APPn segment. */ + + int COM_len; /* Length of data in JPEG COM segment */ + char COM_data[60]; /* Data in JPEG COM segment */ + + __u32 jpeg_markers; /* Which markers should go into the JPEG + * output. Unless you exactly know what + * you do, leave them untouched. + * Inluding less markers will make the + * resulting code smaller, but there will + * be fewer aplications which can read it. + * The presence of the APP and COM marker + * is influenced by APP_len and COM_len + * ONLY, not by this property! */ + +#define V4L2_JPEG_MARKER_DHT (1<<3) /* Define Huffman Tables */ +#define V4L2_JPEG_MARKER_DQT (1<<4) /* Define Quantization Tables */ +#define V4L2_JPEG_MARKER_DRI (1<<5) /* Define Restart Interval */ +#define V4L2_JPEG_MARKER_COM (1<<6) /* Comment segment */ +#define V4L2_JPEG_MARKER_APP (1<<7) /* App segment, driver will + * allways use APP0 */ +}; + +/* + * M E M O R Y - M A P P I N G B U F F E R S + */ +struct v4l2_requestbuffers { + __u32 count; + enum v4l2_buf_type type; + enum v4l2_memory memory; + __u32 reserved[2]; +}; + +struct v4l2_buffer { + __u32 index; + enum v4l2_buf_type type; + __u32 bytesused; + __u32 flags; + enum v4l2_field field; + struct timeval timestamp; + struct v4l2_timecode timecode; + __u32 sequence; + + /* memory location */ + enum v4l2_memory memory; + union { + __u32 offset; + unsigned long userptr; + } m; + __u32 length; + __u32 input; + __u32 reserved; +}; + +/* Flags for 'flags' field */ +#define V4L2_BUF_FLAG_MAPPED 0x0001 /* Buffer is mapped (flag) */ +#define V4L2_BUF_FLAG_QUEUED 0x0002 /* Buffer is queued for processing */ +#define V4L2_BUF_FLAG_DONE 0x0004 /* Buffer is ready */ +#define V4L2_BUF_FLAG_KEYFRAME 0x0008 /* Image is a keyframe (I-frame) */ +#define V4L2_BUF_FLAG_PFRAME 0x0010 /* Image is a P-frame */ +#define V4L2_BUF_FLAG_BFRAME 0x0020 /* Image is a B-frame */ +#define V4L2_BUF_FLAG_TIMECODE 0x0100 /* timecode field is valid */ +#define V4L2_BUF_FLAG_INPUT 0x0200 /* input field is valid */ + +/* + * O V E R L A Y P R E V I E W + */ +struct v4l2_framebuffer { + __u32 capability; + __u32 flags; +/* FIXME: in theory we should pass something like PCI device + memory + * region + offset instead of some physical address */ + void *base; + struct v4l2_pix_format fmt; +}; +/* Flags for the 'capability' field. Read only */ +#define V4L2_FBUF_CAP_EXTERNOVERLAY 0x0001 +#define V4L2_FBUF_CAP_CHROMAKEY 0x0002 +#define V4L2_FBUF_CAP_LIST_CLIPPING 0x0004 +#define V4L2_FBUF_CAP_BITMAP_CLIPPING 0x0008 +#define V4L2_FBUF_CAP_LOCAL_ALPHA 0x0010 +#define V4L2_FBUF_CAP_GLOBAL_ALPHA 0x0020 +#define V4L2_FBUF_CAP_LOCAL_INV_ALPHA 0x0040 +/* Flags for the 'flags' field. */ +#define V4L2_FBUF_FLAG_PRIMARY 0x0001 +#define V4L2_FBUF_FLAG_OVERLAY 0x0002 +#define V4L2_FBUF_FLAG_CHROMAKEY 0x0004 +#define V4L2_FBUF_FLAG_LOCAL_ALPHA 0x0008 +#define V4L2_FBUF_FLAG_GLOBAL_ALPHA 0x0010 +#define V4L2_FBUF_FLAG_LOCAL_INV_ALPHA 0x0020 + +struct v4l2_clip { + struct v4l2_rect c; + struct v4l2_clip __user *next; +}; + +struct v4l2_window { + struct v4l2_rect w; + enum v4l2_field field; + __u32 chromakey; + struct v4l2_clip __user *clips; + __u32 clipcount; + void __user *bitmap; + __u8 global_alpha; +}; + +/* + * C A P T U R E P A R A M E T E R S + */ +struct v4l2_captureparm { + __u32 capability; /* Supported modes */ + __u32 capturemode; /* Current mode */ + struct v4l2_fract timeperframe; /* Time per frame in .1us units */ + __u32 extendedmode; /* Driver-specific extensions */ + __u32 readbuffers; /* # of buffers for read */ + __u32 reserved[4]; +}; + +/* Flags for 'capability' and 'capturemode' fields */ +#define V4L2_MODE_HIGHQUALITY 0x0001 /* High quality imaging mode */ +#define V4L2_CAP_TIMEPERFRAME 0x1000 /* timeperframe field is supported */ + +struct v4l2_outputparm { + __u32 capability; /* Supported modes */ + __u32 outputmode; /* Current mode */ + struct v4l2_fract timeperframe; /* Time per frame in seconds */ + __u32 extendedmode; /* Driver-specific extensions */ + __u32 writebuffers; /* # of buffers for write */ + __u32 reserved[4]; +}; + +/* + * I N P U T I M A G E C R O P P I N G + */ +struct v4l2_cropcap { + enum v4l2_buf_type type; + struct v4l2_rect bounds; + struct v4l2_rect defrect; + struct v4l2_fract pixelaspect; +}; + +struct v4l2_crop { + enum v4l2_buf_type type; + struct v4l2_rect c; +}; + +/* + * A N A L O G V I D E O S T A N D A R D + */ + +typedef __u64 v4l2_std_id; + +/* one bit for each */ +#define V4L2_STD_PAL_B ((v4l2_std_id)0x00000001) +#define V4L2_STD_PAL_B1 ((v4l2_std_id)0x00000002) +#define V4L2_STD_PAL_G ((v4l2_std_id)0x00000004) +#define V4L2_STD_PAL_H ((v4l2_std_id)0x00000008) +#define V4L2_STD_PAL_I ((v4l2_std_id)0x00000010) +#define V4L2_STD_PAL_D ((v4l2_std_id)0x00000020) +#define V4L2_STD_PAL_D1 ((v4l2_std_id)0x00000040) +#define V4L2_STD_PAL_K ((v4l2_std_id)0x00000080) + +#define V4L2_STD_PAL_M ((v4l2_std_id)0x00000100) +#define V4L2_STD_PAL_N ((v4l2_std_id)0x00000200) +#define V4L2_STD_PAL_Nc ((v4l2_std_id)0x00000400) +#define V4L2_STD_PAL_60 ((v4l2_std_id)0x00000800) + +#define V4L2_STD_NTSC_M ((v4l2_std_id)0x00001000) +#define V4L2_STD_NTSC_M_JP ((v4l2_std_id)0x00002000) +#define V4L2_STD_NTSC_443 ((v4l2_std_id)0x00004000) +#define V4L2_STD_NTSC_M_KR ((v4l2_std_id)0x00008000) + +#define V4L2_STD_SECAM_B ((v4l2_std_id)0x00010000) +#define V4L2_STD_SECAM_D ((v4l2_std_id)0x00020000) +#define V4L2_STD_SECAM_G ((v4l2_std_id)0x00040000) +#define V4L2_STD_SECAM_H ((v4l2_std_id)0x00080000) +#define V4L2_STD_SECAM_K ((v4l2_std_id)0x00100000) +#define V4L2_STD_SECAM_K1 ((v4l2_std_id)0x00200000) +#define V4L2_STD_SECAM_L ((v4l2_std_id)0x00400000) +#define V4L2_STD_SECAM_LC ((v4l2_std_id)0x00800000) + +/* ATSC/HDTV */ +#define V4L2_STD_ATSC_8_VSB ((v4l2_std_id)0x01000000) +#define V4L2_STD_ATSC_16_VSB ((v4l2_std_id)0x02000000) + +/* FIXME: + Although std_id is 64 bits, there is an issue on PPC32 architecture that + makes switch(__u64) to break. So, there's a hack on v4l2-common.c rounding + this value to 32 bits. + As, currently, the max value is for V4L2_STD_ATSC_16_VSB (30 bits wide), + it should work fine. However, if needed to add more than two standards, + v4l2-common.c should be fixed. + */ + +/* some merged standards */ +#define V4L2_STD_MN (V4L2_STD_PAL_M|V4L2_STD_PAL_N|V4L2_STD_PAL_Nc|V4L2_STD_NTSC) +#define V4L2_STD_B (V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_SECAM_B) +#define V4L2_STD_GH (V4L2_STD_PAL_G|V4L2_STD_PAL_H|V4L2_STD_SECAM_G|V4L2_STD_SECAM_H) +#define V4L2_STD_DK (V4L2_STD_PAL_DK|V4L2_STD_SECAM_DK) + +/* some common needed stuff */ +#define V4L2_STD_PAL_BG (V4L2_STD_PAL_B |\ + V4L2_STD_PAL_B1 |\ + V4L2_STD_PAL_G) +#define V4L2_STD_PAL_DK (V4L2_STD_PAL_D |\ + V4L2_STD_PAL_D1 |\ + V4L2_STD_PAL_K) +#define V4L2_STD_PAL (V4L2_STD_PAL_BG |\ + V4L2_STD_PAL_DK |\ + V4L2_STD_PAL_H |\ + V4L2_STD_PAL_I) +#define V4L2_STD_NTSC (V4L2_STD_NTSC_M |\ + V4L2_STD_NTSC_M_JP |\ + V4L2_STD_NTSC_M_KR) +#define V4L2_STD_SECAM_DK (V4L2_STD_SECAM_D |\ + V4L2_STD_SECAM_K |\ + V4L2_STD_SECAM_K1) +#define V4L2_STD_SECAM (V4L2_STD_SECAM_B |\ + V4L2_STD_SECAM_G |\ + V4L2_STD_SECAM_H |\ + V4L2_STD_SECAM_DK |\ + V4L2_STD_SECAM_L |\ + V4L2_STD_SECAM_LC) + +#define V4L2_STD_525_60 (V4L2_STD_PAL_M |\ + V4L2_STD_PAL_60 |\ + V4L2_STD_NTSC |\ + V4L2_STD_NTSC_443) +#define V4L2_STD_625_50 (V4L2_STD_PAL |\ + V4L2_STD_PAL_N |\ + V4L2_STD_PAL_Nc |\ + V4L2_STD_SECAM) +#define V4L2_STD_ATSC (V4L2_STD_ATSC_8_VSB |\ + V4L2_STD_ATSC_16_VSB) + +#define V4L2_STD_UNKNOWN 0 +#define V4L2_STD_ALL (V4L2_STD_525_60 |\ + V4L2_STD_625_50) + +struct v4l2_standard { + __u32 index; + v4l2_std_id id; + __u8 name[24]; + struct v4l2_fract frameperiod; /* Frames, not fields */ + __u32 framelines; + __u32 reserved[4]; +}; + +/* + * V I D E O I N P U T S + */ +struct v4l2_input { + __u32 index; /* Which input */ + __u8 name[32]; /* Label */ + __u32 type; /* Type of input */ + __u32 audioset; /* Associated audios (bitfield) */ + __u32 tuner; /* Associated tuner */ + v4l2_std_id std; + __u32 status; + __u32 reserved[4]; +}; + +/* Values for the 'type' field */ +#define V4L2_INPUT_TYPE_TUNER 1 +#define V4L2_INPUT_TYPE_CAMERA 2 + +/* field 'status' - general */ +#define V4L2_IN_ST_NO_POWER 0x00000001 /* Attached device is off */ +#define V4L2_IN_ST_NO_SIGNAL 0x00000002 +#define V4L2_IN_ST_NO_COLOR 0x00000004 + +/* field 'status' - sensor orientation */ +/* If sensor is mounted upside down set both bits */ +#define V4L2_IN_ST_HFLIP 0x00000010 /* Frames are flipped horizontally */ +#define V4L2_IN_ST_VFLIP 0x00000020 /* Frames are flipped vertically */ + +/* field 'status' - analog */ +#define V4L2_IN_ST_NO_H_LOCK 0x00000100 /* No horizontal sync lock */ +#define V4L2_IN_ST_COLOR_KILL 0x00000200 /* Color killer is active */ + +/* field 'status' - digital */ +#define V4L2_IN_ST_NO_SYNC 0x00010000 /* No synchronization lock */ +#define V4L2_IN_ST_NO_EQU 0x00020000 /* No equalizer lock */ +#define V4L2_IN_ST_NO_CARRIER 0x00040000 /* Carrier recovery failed */ + +/* field 'status' - VCR and set-top box */ +#define V4L2_IN_ST_MACROVISION 0x01000000 /* Macrovision detected */ +#define V4L2_IN_ST_NO_ACCESS 0x02000000 /* Conditional access denied */ +#define V4L2_IN_ST_VTR 0x04000000 /* VTR time constant */ + +/* + * V I D E O O U T P U T S + */ +struct v4l2_output { + __u32 index; /* Which output */ + __u8 name[32]; /* Label */ + __u32 type; /* Type of output */ + __u32 audioset; /* Associated audios (bitfield) */ + __u32 modulator; /* Associated modulator */ + v4l2_std_id std; + __u32 reserved[4]; +}; +/* Values for the 'type' field */ +#define V4L2_OUTPUT_TYPE_MODULATOR 1 +#define V4L2_OUTPUT_TYPE_ANALOG 2 +#define V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY 3 + +/* + * C O N T R O L S + */ +struct v4l2_control { + __u32 id; + __s32 value; +}; + +struct v4l2_ext_control { + __u32 id; + __u32 size; + __u32 reserved2[1]; + union { + __s32 value; + __s64 value64; + char *string; + }; +} __attribute__ ((packed)); + +struct v4l2_ext_controls { + __u32 ctrl_class; + __u32 count; + __u32 error_idx; + __u32 reserved[2]; + struct v4l2_ext_control *controls; +}; + +/* Values for ctrl_class field */ +#define V4L2_CTRL_CLASS_USER 0x00980000 /* Old-style 'user' controls */ +#define V4L2_CTRL_CLASS_MPEG 0x00990000 /* MPEG-compression controls */ +#define V4L2_CTRL_CLASS_CAMERA 0x009a0000 /* Camera class controls */ +#define V4L2_CTRL_CLASS_FM_TX 0x009b0000 /* FM Modulator control class */ + +#define V4L2_CTRL_ID_MASK (0x0fffffff) +#define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL) +#define V4L2_CTRL_DRIVER_PRIV(id) (((id) & 0xffff) >= 0x1000) + +/* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */ +struct v4l2_queryctrl { + __u32 id; + enum v4l2_ctrl_type type; + __u8 name[32]; /* Whatever */ + __s32 minimum; /* Note signedness */ + __s32 maximum; + __s32 step; + __s32 default_value; + __u32 flags; + __u32 reserved[2]; +}; + +/* Used in the VIDIOC_QUERYMENU ioctl for querying menu items */ +struct v4l2_querymenu { + __u32 id; + __u32 index; + __u8 name[32]; /* Whatever */ + __u32 reserved; +}; + +/* Control flags */ +#define V4L2_CTRL_FLAG_DISABLED 0x0001 +#define V4L2_CTRL_FLAG_GRABBED 0x0002 +#define V4L2_CTRL_FLAG_READ_ONLY 0x0004 +#define V4L2_CTRL_FLAG_UPDATE 0x0008 +#define V4L2_CTRL_FLAG_INACTIVE 0x0010 +#define V4L2_CTRL_FLAG_SLIDER 0x0020 +#define V4L2_CTRL_FLAG_WRITE_ONLY 0x0040 + +/* Query flag, to be ORed with the control ID */ +#define V4L2_CTRL_FLAG_NEXT_CTRL 0x80000000 + +/* User-class control IDs defined by V4L2 */ +#define V4L2_CID_BASE (V4L2_CTRL_CLASS_USER | 0x900) +#define V4L2_CID_USER_BASE V4L2_CID_BASE +/* IDs reserved for driver specific controls */ +#define V4L2_CID_PRIVATE_BASE 0x08000000 + +#define V4L2_CID_USER_CLASS (V4L2_CTRL_CLASS_USER | 1) +#define V4L2_CID_BRIGHTNESS (V4L2_CID_BASE+0) +#define V4L2_CID_CONTRAST (V4L2_CID_BASE+1) +#define V4L2_CID_SATURATION (V4L2_CID_BASE+2) +#define V4L2_CID_HUE (V4L2_CID_BASE+3) +#define V4L2_CID_AUDIO_VOLUME (V4L2_CID_BASE+5) +#define V4L2_CID_AUDIO_BALANCE (V4L2_CID_BASE+6) +#define V4L2_CID_AUDIO_BASS (V4L2_CID_BASE+7) +#define V4L2_CID_AUDIO_TREBLE (V4L2_CID_BASE+8) +#define V4L2_CID_AUDIO_MUTE (V4L2_CID_BASE+9) +#define V4L2_CID_AUDIO_LOUDNESS (V4L2_CID_BASE+10) +#define V4L2_CID_BLACK_LEVEL (V4L2_CID_BASE+11) /* Deprecated */ +#define V4L2_CID_AUTO_WHITE_BALANCE (V4L2_CID_BASE+12) +#define V4L2_CID_DO_WHITE_BALANCE (V4L2_CID_BASE+13) +#define V4L2_CID_RED_BALANCE (V4L2_CID_BASE+14) +#define V4L2_CID_BLUE_BALANCE (V4L2_CID_BASE+15) +#define V4L2_CID_GAMMA (V4L2_CID_BASE+16) +#define V4L2_CID_WHITENESS (V4L2_CID_GAMMA) /* Deprecated */ +#define V4L2_CID_EXPOSURE (V4L2_CID_BASE+17) +#define V4L2_CID_AUTOGAIN (V4L2_CID_BASE+18) +#define V4L2_CID_GAIN (V4L2_CID_BASE+19) +#define V4L2_CID_HFLIP (V4L2_CID_BASE+20) +#define V4L2_CID_VFLIP (V4L2_CID_BASE+21) + +/* Deprecated; use V4L2_CID_PAN_RESET and V4L2_CID_TILT_RESET */ +#define V4L2_CID_HCENTER (V4L2_CID_BASE+22) +#define V4L2_CID_VCENTER (V4L2_CID_BASE+23) + +#define V4L2_CID_POWER_LINE_FREQUENCY (V4L2_CID_BASE+24) +enum v4l2_power_line_frequency { + V4L2_CID_POWER_LINE_FREQUENCY_DISABLED = 0, + V4L2_CID_POWER_LINE_FREQUENCY_50HZ = 1, + V4L2_CID_POWER_LINE_FREQUENCY_60HZ = 2, +}; +#define V4L2_CID_HUE_AUTO (V4L2_CID_BASE+25) +#define V4L2_CID_WHITE_BALANCE_TEMPERATURE (V4L2_CID_BASE+26) +#define V4L2_CID_SHARPNESS (V4L2_CID_BASE+27) +#define V4L2_CID_BACKLIGHT_COMPENSATION (V4L2_CID_BASE+28) +#define V4L2_CID_CHROMA_AGC (V4L2_CID_BASE+29) +#define V4L2_CID_COLOR_KILLER (V4L2_CID_BASE+30) +#define V4L2_CID_COLORFX (V4L2_CID_BASE+31) +enum v4l2_colorfx { + V4L2_COLORFX_NONE = 0, + V4L2_COLORFX_BW = 1, + V4L2_COLORFX_SEPIA = 2, +}; +#define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE+32) +#define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE+33) + +/* last CID + 1 */ +#define V4L2_CID_LASTP1 (V4L2_CID_BASE+34) + +/* MPEG-class control IDs defined by V4L2 */ +#define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900) +#define V4L2_CID_MPEG_CLASS (V4L2_CTRL_CLASS_MPEG | 1) + +/* MPEG streams */ +#define V4L2_CID_MPEG_STREAM_TYPE (V4L2_CID_MPEG_BASE+0) +enum v4l2_mpeg_stream_type { + V4L2_MPEG_STREAM_TYPE_MPEG2_PS = 0, /* MPEG-2 program stream */ + V4L2_MPEG_STREAM_TYPE_MPEG2_TS = 1, /* MPEG-2 transport stream */ + V4L2_MPEG_STREAM_TYPE_MPEG1_SS = 2, /* MPEG-1 system stream */ + V4L2_MPEG_STREAM_TYPE_MPEG2_DVD = 3, /* MPEG-2 DVD-compatible stream */ + V4L2_MPEG_STREAM_TYPE_MPEG1_VCD = 4, /* MPEG-1 VCD-compatible stream */ + V4L2_MPEG_STREAM_TYPE_MPEG2_SVCD = 5, /* MPEG-2 SVCD-compatible stream */ +}; +#define V4L2_CID_MPEG_STREAM_PID_PMT (V4L2_CID_MPEG_BASE+1) +#define V4L2_CID_MPEG_STREAM_PID_AUDIO (V4L2_CID_MPEG_BASE+2) +#define V4L2_CID_MPEG_STREAM_PID_VIDEO (V4L2_CID_MPEG_BASE+3) +#define V4L2_CID_MPEG_STREAM_PID_PCR (V4L2_CID_MPEG_BASE+4) +#define V4L2_CID_MPEG_STREAM_PES_ID_AUDIO (V4L2_CID_MPEG_BASE+5) +#define V4L2_CID_MPEG_STREAM_PES_ID_VIDEO (V4L2_CID_MPEG_BASE+6) +#define V4L2_CID_MPEG_STREAM_VBI_FMT (V4L2_CID_MPEG_BASE+7) +enum v4l2_mpeg_stream_vbi_fmt { + V4L2_MPEG_STREAM_VBI_FMT_NONE = 0, /* No VBI in the MPEG stream */ + V4L2_MPEG_STREAM_VBI_FMT_IVTV = 1, /* VBI in private packets, IVTV format */ +}; + +/* MPEG audio */ +#define V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ (V4L2_CID_MPEG_BASE+100) +enum v4l2_mpeg_audio_sampling_freq { + V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100 = 0, + V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000 = 1, + V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000 = 2, +}; +#define V4L2_CID_MPEG_AUDIO_ENCODING (V4L2_CID_MPEG_BASE+101) +enum v4l2_mpeg_audio_encoding { + V4L2_MPEG_AUDIO_ENCODING_LAYER_1 = 0, + V4L2_MPEG_AUDIO_ENCODING_LAYER_2 = 1, + V4L2_MPEG_AUDIO_ENCODING_LAYER_3 = 2, + V4L2_MPEG_AUDIO_ENCODING_AAC = 3, + V4L2_MPEG_AUDIO_ENCODING_AC3 = 4, +}; +#define V4L2_CID_MPEG_AUDIO_L1_BITRATE (V4L2_CID_MPEG_BASE+102) +enum v4l2_mpeg_audio_l1_bitrate { + V4L2_MPEG_AUDIO_L1_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L1_BITRATE_64K = 1, + V4L2_MPEG_AUDIO_L1_BITRATE_96K = 2, + V4L2_MPEG_AUDIO_L1_BITRATE_128K = 3, + V4L2_MPEG_AUDIO_L1_BITRATE_160K = 4, + V4L2_MPEG_AUDIO_L1_BITRATE_192K = 5, + V4L2_MPEG_AUDIO_L1_BITRATE_224K = 6, + V4L2_MPEG_AUDIO_L1_BITRATE_256K = 7, + V4L2_MPEG_AUDIO_L1_BITRATE_288K = 8, + V4L2_MPEG_AUDIO_L1_BITRATE_320K = 9, + V4L2_MPEG_AUDIO_L1_BITRATE_352K = 10, + V4L2_MPEG_AUDIO_L1_BITRATE_384K = 11, + V4L2_MPEG_AUDIO_L1_BITRATE_416K = 12, + V4L2_MPEG_AUDIO_L1_BITRATE_448K = 13, +}; +#define V4L2_CID_MPEG_AUDIO_L2_BITRATE (V4L2_CID_MPEG_BASE+103) +enum v4l2_mpeg_audio_l2_bitrate { + V4L2_MPEG_AUDIO_L2_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L2_BITRATE_48K = 1, + V4L2_MPEG_AUDIO_L2_BITRATE_56K = 2, + V4L2_MPEG_AUDIO_L2_BITRATE_64K = 3, + V4L2_MPEG_AUDIO_L2_BITRATE_80K = 4, + V4L2_MPEG_AUDIO_L2_BITRATE_96K = 5, + V4L2_MPEG_AUDIO_L2_BITRATE_112K = 6, + V4L2_MPEG_AUDIO_L2_BITRATE_128K = 7, + V4L2_MPEG_AUDIO_L2_BITRATE_160K = 8, + V4L2_MPEG_AUDIO_L2_BITRATE_192K = 9, + V4L2_MPEG_AUDIO_L2_BITRATE_224K = 10, + V4L2_MPEG_AUDIO_L2_BITRATE_256K = 11, + V4L2_MPEG_AUDIO_L2_BITRATE_320K = 12, + V4L2_MPEG_AUDIO_L2_BITRATE_384K = 13, +}; +#define V4L2_CID_MPEG_AUDIO_L3_BITRATE (V4L2_CID_MPEG_BASE+104) +enum v4l2_mpeg_audio_l3_bitrate { + V4L2_MPEG_AUDIO_L3_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L3_BITRATE_40K = 1, + V4L2_MPEG_AUDIO_L3_BITRATE_48K = 2, + V4L2_MPEG_AUDIO_L3_BITRATE_56K = 3, + V4L2_MPEG_AUDIO_L3_BITRATE_64K = 4, + V4L2_MPEG_AUDIO_L3_BITRATE_80K = 5, + V4L2_MPEG_AUDIO_L3_BITRATE_96K = 6, + V4L2_MPEG_AUDIO_L3_BITRATE_112K = 7, + V4L2_MPEG_AUDIO_L3_BITRATE_128K = 8, + V4L2_MPEG_AUDIO_L3_BITRATE_160K = 9, + V4L2_MPEG_AUDIO_L3_BITRATE_192K = 10, + V4L2_MPEG_AUDIO_L3_BITRATE_224K = 11, + V4L2_MPEG_AUDIO_L3_BITRATE_256K = 12, + V4L2_MPEG_AUDIO_L3_BITRATE_320K = 13, +}; +#define V4L2_CID_MPEG_AUDIO_MODE (V4L2_CID_MPEG_BASE+105) +enum v4l2_mpeg_audio_mode { + V4L2_MPEG_AUDIO_MODE_STEREO = 0, + V4L2_MPEG_AUDIO_MODE_JOINT_STEREO = 1, + V4L2_MPEG_AUDIO_MODE_DUAL = 2, + V4L2_MPEG_AUDIO_MODE_MONO = 3, +}; +#define V4L2_CID_MPEG_AUDIO_MODE_EXTENSION (V4L2_CID_MPEG_BASE+106) +enum v4l2_mpeg_audio_mode_extension { + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_4 = 0, + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_8 = 1, + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_12 = 2, + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_16 = 3, +}; +#define V4L2_CID_MPEG_AUDIO_EMPHASIS (V4L2_CID_MPEG_BASE+107) +enum v4l2_mpeg_audio_emphasis { + V4L2_MPEG_AUDIO_EMPHASIS_NONE = 0, + V4L2_MPEG_AUDIO_EMPHASIS_50_DIV_15_uS = 1, + V4L2_MPEG_AUDIO_EMPHASIS_CCITT_J17 = 2, +}; +#define V4L2_CID_MPEG_AUDIO_CRC (V4L2_CID_MPEG_BASE+108) +enum v4l2_mpeg_audio_crc { + V4L2_MPEG_AUDIO_CRC_NONE = 0, + V4L2_MPEG_AUDIO_CRC_CRC16 = 1, +}; +#define V4L2_CID_MPEG_AUDIO_MUTE (V4L2_CID_MPEG_BASE+109) +#define V4L2_CID_MPEG_AUDIO_AAC_BITRATE (V4L2_CID_MPEG_BASE+110) +#define V4L2_CID_MPEG_AUDIO_AC3_BITRATE (V4L2_CID_MPEG_BASE+111) +enum v4l2_mpeg_audio_ac3_bitrate { + V4L2_MPEG_AUDIO_AC3_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_AC3_BITRATE_40K = 1, + V4L2_MPEG_AUDIO_AC3_BITRATE_48K = 2, + V4L2_MPEG_AUDIO_AC3_BITRATE_56K = 3, + V4L2_MPEG_AUDIO_AC3_BITRATE_64K = 4, + V4L2_MPEG_AUDIO_AC3_BITRATE_80K = 5, + V4L2_MPEG_AUDIO_AC3_BITRATE_96K = 6, + V4L2_MPEG_AUDIO_AC3_BITRATE_112K = 7, + V4L2_MPEG_AUDIO_AC3_BITRATE_128K = 8, + V4L2_MPEG_AUDIO_AC3_BITRATE_160K = 9, + V4L2_MPEG_AUDIO_AC3_BITRATE_192K = 10, + V4L2_MPEG_AUDIO_AC3_BITRATE_224K = 11, + V4L2_MPEG_AUDIO_AC3_BITRATE_256K = 12, + V4L2_MPEG_AUDIO_AC3_BITRATE_320K = 13, + V4L2_MPEG_AUDIO_AC3_BITRATE_384K = 14, + V4L2_MPEG_AUDIO_AC3_BITRATE_448K = 15, + V4L2_MPEG_AUDIO_AC3_BITRATE_512K = 16, + V4L2_MPEG_AUDIO_AC3_BITRATE_576K = 17, + V4L2_MPEG_AUDIO_AC3_BITRATE_640K = 18, +}; + +/* MPEG video */ +#define V4L2_CID_MPEG_VIDEO_ENCODING (V4L2_CID_MPEG_BASE+200) +enum v4l2_mpeg_video_encoding { + V4L2_MPEG_VIDEO_ENCODING_MPEG_1 = 0, + V4L2_MPEG_VIDEO_ENCODING_MPEG_2 = 1, + V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC = 2, +}; +#define V4L2_CID_MPEG_VIDEO_ASPECT (V4L2_CID_MPEG_BASE+201) +enum v4l2_mpeg_video_aspect { + V4L2_MPEG_VIDEO_ASPECT_1x1 = 0, + V4L2_MPEG_VIDEO_ASPECT_4x3 = 1, + V4L2_MPEG_VIDEO_ASPECT_16x9 = 2, + V4L2_MPEG_VIDEO_ASPECT_221x100 = 3, +}; +#define V4L2_CID_MPEG_VIDEO_B_FRAMES (V4L2_CID_MPEG_BASE+202) +#define V4L2_CID_MPEG_VIDEO_GOP_SIZE (V4L2_CID_MPEG_BASE+203) +#define V4L2_CID_MPEG_VIDEO_GOP_CLOSURE (V4L2_CID_MPEG_BASE+204) +#define V4L2_CID_MPEG_VIDEO_PULLDOWN (V4L2_CID_MPEG_BASE+205) +#define V4L2_CID_MPEG_VIDEO_BITRATE_MODE (V4L2_CID_MPEG_BASE+206) +enum v4l2_mpeg_video_bitrate_mode { + V4L2_MPEG_VIDEO_BITRATE_MODE_VBR = 0, + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR = 1, +}; +#define V4L2_CID_MPEG_VIDEO_BITRATE (V4L2_CID_MPEG_BASE+207) +#define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK (V4L2_CID_MPEG_BASE+208) +#define V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION (V4L2_CID_MPEG_BASE+209) +#define V4L2_CID_MPEG_VIDEO_MUTE (V4L2_CID_MPEG_BASE+210) +#define V4L2_CID_MPEG_VIDEO_MUTE_YUV (V4L2_CID_MPEG_BASE+211) + +/* MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */ +#define V4L2_CID_MPEG_CX2341X_BASE (V4L2_CTRL_CLASS_MPEG | 0x1000) +#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+0) +enum v4l2_mpeg_cx2341x_video_spatial_filter_mode { + V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_MANUAL = 0, + V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_AUTO = 1, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+1) +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+2) +enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type { + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_VERT = 2, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_HV_SEPARABLE = 3, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_SYM_NON_SEPARABLE = 4, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+3) +enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type { + V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+4) +enum v4l2_mpeg_cx2341x_video_temporal_filter_mode { + V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_MANUAL = 0, + V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_AUTO = 1, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+5) +#define V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+6) +enum v4l2_mpeg_cx2341x_video_median_filter_type { + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR = 1, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_VERT = 2, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR_VERT = 3, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_DIAG = 4, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+7) +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+8) +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+9) +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+10) +#define V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS (V4L2_CID_MPEG_CX2341X_BASE+11) + +/* Camera class control IDs */ +#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900) +#define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1) + +#define V4L2_CID_EXPOSURE_AUTO (V4L2_CID_CAMERA_CLASS_BASE+1) +enum v4l2_exposure_auto_type { + V4L2_EXPOSURE_AUTO = 0, + V4L2_EXPOSURE_MANUAL = 1, + V4L2_EXPOSURE_SHUTTER_PRIORITY = 2, + V4L2_EXPOSURE_APERTURE_PRIORITY = 3 +}; +#define V4L2_CID_EXPOSURE_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+2) +#define V4L2_CID_EXPOSURE_AUTO_PRIORITY (V4L2_CID_CAMERA_CLASS_BASE+3) + +#define V4L2_CID_PAN_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+4) +#define V4L2_CID_TILT_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+5) +#define V4L2_CID_PAN_RESET (V4L2_CID_CAMERA_CLASS_BASE+6) +#define V4L2_CID_TILT_RESET (V4L2_CID_CAMERA_CLASS_BASE+7) + +#define V4L2_CID_PAN_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+8) +#define V4L2_CID_TILT_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+9) + +#define V4L2_CID_FOCUS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+10) +#define V4L2_CID_FOCUS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+11) +#define V4L2_CID_FOCUS_AUTO (V4L2_CID_CAMERA_CLASS_BASE+12) + +#define V4L2_CID_ZOOM_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+13) +#define V4L2_CID_ZOOM_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+14) +#define V4L2_CID_ZOOM_CONTINUOUS (V4L2_CID_CAMERA_CLASS_BASE+15) + +#define V4L2_CID_PRIVACY (V4L2_CID_CAMERA_CLASS_BASE+16) + +/* FM Modulator class control IDs */ +#define V4L2_CID_FM_TX_CLASS_BASE (V4L2_CTRL_CLASS_FM_TX | 0x900) +#define V4L2_CID_FM_TX_CLASS (V4L2_CTRL_CLASS_FM_TX | 1) + +#define V4L2_CID_RDS_TX_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 1) +#define V4L2_CID_RDS_TX_PI (V4L2_CID_FM_TX_CLASS_BASE + 2) +#define V4L2_CID_RDS_TX_PTY (V4L2_CID_FM_TX_CLASS_BASE + 3) +#define V4L2_CID_RDS_TX_PS_NAME (V4L2_CID_FM_TX_CLASS_BASE + 5) +#define V4L2_CID_RDS_TX_RADIO_TEXT (V4L2_CID_FM_TX_CLASS_BASE + 6) + +#define V4L2_CID_AUDIO_LIMITER_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 64) +#define V4L2_CID_AUDIO_LIMITER_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 65) +#define V4L2_CID_AUDIO_LIMITER_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 66) + +#define V4L2_CID_AUDIO_COMPRESSION_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 80) +#define V4L2_CID_AUDIO_COMPRESSION_GAIN (V4L2_CID_FM_TX_CLASS_BASE + 81) +#define V4L2_CID_AUDIO_COMPRESSION_THRESHOLD (V4L2_CID_FM_TX_CLASS_BASE + 82) +#define V4L2_CID_AUDIO_COMPRESSION_ATTACK_TIME (V4L2_CID_FM_TX_CLASS_BASE + 83) +#define V4L2_CID_AUDIO_COMPRESSION_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 84) + +#define V4L2_CID_PILOT_TONE_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 96) +#define V4L2_CID_PILOT_TONE_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 97) +#define V4L2_CID_PILOT_TONE_FREQUENCY (V4L2_CID_FM_TX_CLASS_BASE + 98) + +#define V4L2_CID_TUNE_PREEMPHASIS (V4L2_CID_FM_TX_CLASS_BASE + 112) +enum v4l2_preemphasis { + V4L2_PREEMPHASIS_DISABLED = 0, + V4L2_PREEMPHASIS_50_uS = 1, + V4L2_PREEMPHASIS_75_uS = 2, +}; +#define V4L2_CID_TUNE_POWER_LEVEL (V4L2_CID_FM_TX_CLASS_BASE + 113) +#define V4L2_CID_TUNE_ANTENNA_CAPACITOR (V4L2_CID_FM_TX_CLASS_BASE + 114) + +/* + * T U N I N G + */ +struct v4l2_tuner { + __u32 index; + __u8 name[32]; + enum v4l2_tuner_type type; + __u32 capability; + __u32 rangelow; + __u32 rangehigh; + __u32 rxsubchans; + __u32 audmode; + __s32 signal; + __s32 afc; + __u32 reserved[4]; +}; + +struct v4l2_modulator { + __u32 index; + __u8 name[32]; + __u32 capability; + __u32 rangelow; + __u32 rangehigh; + __u32 txsubchans; + __u32 reserved[4]; +}; + +/* Flags for the 'capability' field */ +#define V4L2_TUNER_CAP_LOW 0x0001 +#define V4L2_TUNER_CAP_NORM 0x0002 +#define V4L2_TUNER_CAP_STEREO 0x0010 +#define V4L2_TUNER_CAP_LANG2 0x0020 +#define V4L2_TUNER_CAP_SAP 0x0020 +#define V4L2_TUNER_CAP_LANG1 0x0040 +#define V4L2_TUNER_CAP_RDS 0x0080 + +/* Flags for the 'rxsubchans' field */ +#define V4L2_TUNER_SUB_MONO 0x0001 +#define V4L2_TUNER_SUB_STEREO 0x0002 +#define V4L2_TUNER_SUB_LANG2 0x0004 +#define V4L2_TUNER_SUB_SAP 0x0004 +#define V4L2_TUNER_SUB_LANG1 0x0008 +#define V4L2_TUNER_SUB_RDS 0x0010 + +/* Values for the 'audmode' field */ +#define V4L2_TUNER_MODE_MONO 0x0000 +#define V4L2_TUNER_MODE_STEREO 0x0001 +#define V4L2_TUNER_MODE_LANG2 0x0002 +#define V4L2_TUNER_MODE_SAP 0x0002 +#define V4L2_TUNER_MODE_LANG1 0x0003 +#define V4L2_TUNER_MODE_LANG1_LANG2 0x0004 + +struct v4l2_frequency { + __u32 tuner; + enum v4l2_tuner_type type; + __u32 frequency; + __u32 reserved[8]; +}; + +struct v4l2_hw_freq_seek { + __u32 tuner; + enum v4l2_tuner_type type; + __u32 seek_upward; + __u32 wrap_around; + __u32 reserved[8]; +}; + +/* + * R D S + */ + +struct v4l2_rds_data { + __u8 lsb; + __u8 msb; + __u8 block; +} __attribute__ ((packed)); + +#define V4L2_RDS_BLOCK_MSK 0x7 +#define V4L2_RDS_BLOCK_A 0 +#define V4L2_RDS_BLOCK_B 1 +#define V4L2_RDS_BLOCK_C 2 +#define V4L2_RDS_BLOCK_D 3 +#define V4L2_RDS_BLOCK_C_ALT 4 +#define V4L2_RDS_BLOCK_INVALID 7 + +#define V4L2_RDS_BLOCK_CORRECTED 0x40 +#define V4L2_RDS_BLOCK_ERROR 0x80 + +/* + * A U D I O + */ +struct v4l2_audio { + __u32 index; + __u8 name[32]; + __u32 capability; + __u32 mode; + __u32 reserved[2]; +}; + +/* Flags for the 'capability' field */ +#define V4L2_AUDCAP_STEREO 0x00001 +#define V4L2_AUDCAP_AVL 0x00002 + +/* Flags for the 'mode' field */ +#define V4L2_AUDMODE_AVL 0x00001 + +struct v4l2_audioout { + __u32 index; + __u8 name[32]; + __u32 capability; + __u32 mode; + __u32 reserved[2]; +}; + +/* + * M P E G S E R V I C E S + * + * NOTE: EXPERIMENTAL API + */ +#if 1 /*KEEP*/ +#define V4L2_ENC_IDX_FRAME_I (0) +#define V4L2_ENC_IDX_FRAME_P (1) +#define V4L2_ENC_IDX_FRAME_B (2) +#define V4L2_ENC_IDX_FRAME_MASK (0xf) + +struct v4l2_enc_idx_entry { + __u64 offset; + __u64 pts; + __u32 length; + __u32 flags; + __u32 reserved[2]; +}; + +#define V4L2_ENC_IDX_ENTRIES (64) +struct v4l2_enc_idx { + __u32 entries; + __u32 entries_cap; + __u32 reserved[4]; + struct v4l2_enc_idx_entry entry[V4L2_ENC_IDX_ENTRIES]; +}; + + +#define V4L2_ENC_CMD_START (0) +#define V4L2_ENC_CMD_STOP (1) +#define V4L2_ENC_CMD_PAUSE (2) +#define V4L2_ENC_CMD_RESUME (3) + +/* Flags for V4L2_ENC_CMD_STOP */ +#define V4L2_ENC_CMD_STOP_AT_GOP_END (1 << 0) + +struct v4l2_encoder_cmd { + __u32 cmd; + __u32 flags; + union { + struct { + __u32 data[8]; + } raw; + }; +}; + +#endif + + +/* + * D A T A S E R V I C E S ( V B I ) + * + * Data services API by Michael Schimek + */ + +/* Raw VBI */ +struct v4l2_vbi_format { + __u32 sampling_rate; /* in 1 Hz */ + __u32 offset; + __u32 samples_per_line; + __u32 sample_format; /* V4L2_PIX_FMT_* */ + __s32 start[2]; + __u32 count[2]; + __u32 flags; /* V4L2_VBI_* */ + __u32 reserved[2]; /* must be zero */ +}; + +/* VBI flags */ +#define V4L2_VBI_UNSYNC (1 << 0) +#define V4L2_VBI_INTERLACED (1 << 1) + +/* Sliced VBI + * + * This implements is a proposal V4L2 API to allow SLICED VBI + * required for some hardware encoders. It should change without + * notice in the definitive implementation. + */ + +struct v4l2_sliced_vbi_format { + __u16 service_set; + /* service_lines[0][...] specifies lines 0-23 (1-23 used) of the first field + service_lines[1][...] specifies lines 0-23 (1-23 used) of the second field + (equals frame lines 313-336 for 625 line video + standards, 263-286 for 525 line standards) */ + __u16 service_lines[2][24]; + __u32 io_size; + __u32 reserved[2]; /* must be zero */ +}; + +/* Teletext World System Teletext + (WST), defined on ITU-R BT.653-2 */ +#define V4L2_SLICED_TELETEXT_B (0x0001) +/* Video Program System, defined on ETS 300 231*/ +#define V4L2_SLICED_VPS (0x0400) +/* Closed Caption, defined on EIA-608 */ +#define V4L2_SLICED_CAPTION_525 (0x1000) +/* Wide Screen System, defined on ITU-R BT1119.1 */ +#define V4L2_SLICED_WSS_625 (0x4000) + +#define V4L2_SLICED_VBI_525 (V4L2_SLICED_CAPTION_525) +#define V4L2_SLICED_VBI_625 (V4L2_SLICED_TELETEXT_B | V4L2_SLICED_VPS | V4L2_SLICED_WSS_625) + +struct v4l2_sliced_vbi_cap { + __u16 service_set; + /* service_lines[0][...] specifies lines 0-23 (1-23 used) of the first field + service_lines[1][...] specifies lines 0-23 (1-23 used) of the second field + (equals frame lines 313-336 for 625 line video + standards, 263-286 for 525 line standards) */ + __u16 service_lines[2][24]; + enum v4l2_buf_type type; + __u32 reserved[3]; /* must be 0 */ +}; + +struct v4l2_sliced_vbi_data { + __u32 id; + __u32 field; /* 0: first field, 1: second field */ + __u32 line; /* 1-23 */ + __u32 reserved; /* must be 0 */ + __u8 data[48]; +}; + +/* + * Sliced VBI data inserted into MPEG Streams + */ + +/* + * V4L2_MPEG_STREAM_VBI_FMT_IVTV: + * + * Structure of payload contained in an MPEG 2 Private Stream 1 PES Packet in an + * MPEG-2 Program Pack that contains V4L2_MPEG_STREAM_VBI_FMT_IVTV Sliced VBI + * data + * + * Note, the MPEG-2 Program Pack and Private Stream 1 PES packet header + * definitions are not included here. See the MPEG-2 specifications for details + * on these headers. + */ + +/* Line type IDs */ +#define V4L2_MPEG_VBI_IVTV_TELETEXT_B (1) +#define V4L2_MPEG_VBI_IVTV_CAPTION_525 (4) +#define V4L2_MPEG_VBI_IVTV_WSS_625 (5) +#define V4L2_MPEG_VBI_IVTV_VPS (7) + +struct v4l2_mpeg_vbi_itv0_line { + __u8 id; /* One of V4L2_MPEG_VBI_IVTV_* above */ + __u8 data[42]; /* Sliced VBI data for the line */ +} __attribute__ ((packed)); + +struct v4l2_mpeg_vbi_itv0 { + __le32 linemask[2]; /* Bitmasks of VBI service lines present */ + struct v4l2_mpeg_vbi_itv0_line line[35]; +} __attribute__ ((packed)); + +struct v4l2_mpeg_vbi_ITV0 { + struct v4l2_mpeg_vbi_itv0_line line[36]; +} __attribute__ ((packed)); + +#define V4L2_MPEG_VBI_IVTV_MAGIC0 "itv0" +#define V4L2_MPEG_VBI_IVTV_MAGIC1 "ITV0" + +struct v4l2_mpeg_vbi_fmt_ivtv { + __u8 magic[4]; + union { + struct v4l2_mpeg_vbi_itv0 itv0; + struct v4l2_mpeg_vbi_ITV0 ITV0; + }; +} __attribute__ ((packed)); + +/* + * A G G R E G A T E S T R U C T U R E S + */ + +/* Stream data format + */ +struct v4l2_format { + enum v4l2_buf_type type; + union { + struct v4l2_pix_format pix; /* V4L2_BUF_TYPE_VIDEO_CAPTURE */ + struct v4l2_window win; /* V4L2_BUF_TYPE_VIDEO_OVERLAY */ + struct v4l2_vbi_format vbi; /* V4L2_BUF_TYPE_VBI_CAPTURE */ + struct v4l2_sliced_vbi_format sliced; /* V4L2_BUF_TYPE_SLICED_VBI_CAPTURE */ + __u8 raw_data[200]; /* user-defined */ + } fmt; +}; + + +/* Stream type-dependent parameters + */ +struct v4l2_streamparm { + enum v4l2_buf_type type; + union { + struct v4l2_captureparm capture; + struct v4l2_outputparm output; + __u8 raw_data[200]; /* user-defined */ + } parm; +}; + +/* + * A D V A N C E D D E B U G G I N G + * + * NOTE: EXPERIMENTAL API, NEVER RELY ON THIS IN APPLICATIONS! + * FOR DEBUGGING, TESTING AND INTERNAL USE ONLY! + */ + +/* VIDIOC_DBG_G_REGISTER and VIDIOC_DBG_S_REGISTER */ + +#define V4L2_CHIP_MATCH_HOST 0 /* Match against chip ID on host (0 for the host) */ +#define V4L2_CHIP_MATCH_I2C_DRIVER 1 /* Match against I2C driver name */ +#define V4L2_CHIP_MATCH_I2C_ADDR 2 /* Match against I2C 7-bit address */ +#define V4L2_CHIP_MATCH_AC97 3 /* Match against anciliary AC97 chip */ + +struct v4l2_dbg_match { + __u32 type; /* Match type */ + union { /* Match this chip, meaning determined by type */ + __u32 addr; + char name[32]; + }; +} __attribute__ ((packed)); + +struct v4l2_dbg_register { + struct v4l2_dbg_match match; + __u32 size; /* register size in bytes */ + __u64 reg; + __u64 val; +} __attribute__ ((packed)); + +/* VIDIOC_DBG_G_CHIP_IDENT */ +struct v4l2_dbg_chip_ident { + struct v4l2_dbg_match match; + __u32 ident; /* chip identifier as specified in <media/v4l2-chip-ident.h> */ + __u32 revision; /* chip revision, chip specific */ +} __attribute__ ((packed)); + +/* + * I O C T L C O D E S F O R V I D E O D E V I C E S + * + */ +#define VIDIOC_QUERYCAP _IOR('V', 0, struct v4l2_capability) +#define VIDIOC_RESERVED _IO('V', 1) +#define VIDIOC_ENUM_FMT _IOWR('V', 2, struct v4l2_fmtdesc) +#define VIDIOC_G_FMT _IOWR('V', 4, struct v4l2_format) +#define VIDIOC_S_FMT _IOWR('V', 5, struct v4l2_format) +#define VIDIOC_REQBUFS _IOWR('V', 8, struct v4l2_requestbuffers) +#define VIDIOC_QUERYBUF _IOWR('V', 9, struct v4l2_buffer) +#define VIDIOC_G_FBUF _IOR('V', 10, struct v4l2_framebuffer) +#define VIDIOC_S_FBUF _IOW('V', 11, struct v4l2_framebuffer) +#define VIDIOC_OVERLAY _IOW('V', 14, int) +#define VIDIOC_QBUF _IOWR('V', 15, struct v4l2_buffer) +#define VIDIOC_DQBUF _IOWR('V', 17, struct v4l2_buffer) +#define VIDIOC_STREAMON _IOW('V', 18, int) +#define VIDIOC_STREAMOFF _IOW('V', 19, int) +#define VIDIOC_G_PARM _IOWR('V', 21, struct v4l2_streamparm) +#define VIDIOC_S_PARM _IOWR('V', 22, struct v4l2_streamparm) +#define VIDIOC_G_STD _IOR('V', 23, v4l2_std_id) +#define VIDIOC_S_STD _IOW('V', 24, v4l2_std_id) +#define VIDIOC_ENUMSTD _IOWR('V', 25, struct v4l2_standard) +#define VIDIOC_ENUMINPUT _IOWR('V', 26, struct v4l2_input) +#define VIDIOC_G_CTRL _IOWR('V', 27, struct v4l2_control) +#define VIDIOC_S_CTRL _IOWR('V', 28, struct v4l2_control) +#define VIDIOC_G_TUNER _IOWR('V', 29, struct v4l2_tuner) +#define VIDIOC_S_TUNER _IOW('V', 30, struct v4l2_tuner) +#define VIDIOC_G_AUDIO _IOR('V', 33, struct v4l2_audio) +#define VIDIOC_S_AUDIO _IOW('V', 34, struct v4l2_audio) +#define VIDIOC_QUERYCTRL _IOWR('V', 36, struct v4l2_queryctrl) +#define VIDIOC_QUERYMENU _IOWR('V', 37, struct v4l2_querymenu) +#define VIDIOC_G_INPUT _IOR('V', 38, int) +#define VIDIOC_S_INPUT _IOWR('V', 39, int) +#define VIDIOC_G_OUTPUT _IOR('V', 46, int) +#define VIDIOC_S_OUTPUT _IOWR('V', 47, int) +#define VIDIOC_ENUMOUTPUT _IOWR('V', 48, struct v4l2_output) +#define VIDIOC_G_AUDOUT _IOR('V', 49, struct v4l2_audioout) +#define VIDIOC_S_AUDOUT _IOW('V', 50, struct v4l2_audioout) +#define VIDIOC_G_MODULATOR _IOWR('V', 54, struct v4l2_modulator) +#define VIDIOC_S_MODULATOR _IOW('V', 55, struct v4l2_modulator) +#define VIDIOC_G_FREQUENCY _IOWR('V', 56, struct v4l2_frequency) +#define VIDIOC_S_FREQUENCY _IOW('V', 57, struct v4l2_frequency) +#define VIDIOC_CROPCAP _IOWR('V', 58, struct v4l2_cropcap) +#define VIDIOC_G_CROP _IOWR('V', 59, struct v4l2_crop) +#define VIDIOC_S_CROP _IOW('V', 60, struct v4l2_crop) +#define VIDIOC_G_JPEGCOMP _IOR('V', 61, struct v4l2_jpegcompression) +#define VIDIOC_S_JPEGCOMP _IOW('V', 62, struct v4l2_jpegcompression) +#define VIDIOC_QUERYSTD _IOR('V', 63, v4l2_std_id) +#define VIDIOC_TRY_FMT _IOWR('V', 64, struct v4l2_format) +#define VIDIOC_ENUMAUDIO _IOWR('V', 65, struct v4l2_audio) +#define VIDIOC_ENUMAUDOUT _IOWR('V', 66, struct v4l2_audioout) +#define VIDIOC_G_PRIORITY _IOR('V', 67, enum v4l2_priority) +#define VIDIOC_S_PRIORITY _IOW('V', 68, enum v4l2_priority) +#define VIDIOC_G_SLICED_VBI_CAP _IOWR('V', 69, struct v4l2_sliced_vbi_cap) +#define VIDIOC_LOG_STATUS _IO('V', 70) +#define VIDIOC_G_EXT_CTRLS _IOWR('V', 71, struct v4l2_ext_controls) +#define VIDIOC_S_EXT_CTRLS _IOWR('V', 72, struct v4l2_ext_controls) +#define VIDIOC_TRY_EXT_CTRLS _IOWR('V', 73, struct v4l2_ext_controls) +#if 1 /*KEEP*/ +#define VIDIOC_ENUM_FRAMESIZES _IOWR('V', 74, struct v4l2_frmsizeenum) +#define VIDIOC_ENUM_FRAMEINTERVALS _IOWR('V', 75, struct v4l2_frmivalenum) +#define VIDIOC_G_ENC_INDEX _IOR('V', 76, struct v4l2_enc_idx) +#define VIDIOC_ENCODER_CMD _IOWR('V', 77, struct v4l2_encoder_cmd) +#define VIDIOC_TRY_ENCODER_CMD _IOWR('V', 78, struct v4l2_encoder_cmd) +#endif + +#if 1 /*KEEP*/ +/* Experimental, meant for debugging, testing and internal use. + Only implemented if CONFIG_VIDEO_ADV_DEBUG is defined. + You must be root to use these ioctls. Never use these in applications! */ +#define VIDIOC_DBG_S_REGISTER _IOW('V', 79, struct v4l2_dbg_register) +#define VIDIOC_DBG_G_REGISTER _IOWR('V', 80, struct v4l2_dbg_register) + +/* Experimental, meant for debugging, testing and internal use. + Never use this ioctl in applications! */ +#define VIDIOC_DBG_G_CHIP_IDENT _IOWR('V', 81, struct v4l2_dbg_chip_ident) +#endif + +#define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek) +/* Reminder: when adding new ioctls please add support for them to + drivers/media/video/v4l2-compat-ioctl32.c as well! */ + +#ifdef __OLD_VIDIOC_ +/* for compatibility, will go away some day */ +#define VIDIOC_OVERLAY_OLD _IOWR('V', 14, int) +#define VIDIOC_S_PARM_OLD _IOW('V', 22, struct v4l2_streamparm) +#define VIDIOC_S_CTRL_OLD _IOW('V', 28, struct v4l2_control) +#define VIDIOC_G_AUDIO_OLD _IOWR('V', 33, struct v4l2_audio) +#define VIDIOC_G_AUDOUT_OLD _IOWR('V', 49, struct v4l2_audioout) +#define VIDIOC_CROPCAP_OLD _IOR('V', 58, struct v4l2_cropcap) +#endif + +#define BASE_VIDIOC_PRIVATE 192 /* 192-255 are private */ + +#endif /* __LINUX_VIDEODEV2_H */ + diff --git a/Documentation/DocBook/v4l/vidioc-cropcap.xml b/Documentation/DocBook/v4l/vidioc-cropcap.xml new file mode 100644 index 000000000000..816e90e283c5 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-cropcap.xml @@ -0,0 +1,174 @@ + + + ioctl VIDIOC_CROPCAP + &manvol; + + + + VIDIOC_CROPCAP + Information about the video cropping and scaling abilities + + + + + + int ioctl + int fd + int request + struct v4l2_cropcap +*argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_CROPCAP + + + + argp + + + + + + + + + Description + + Applications use this function to query the cropping +limits, the pixel aspect of images and to calculate scale factors. +They set the type field of a v4l2_cropcap +structure to the respective buffer (stream) type and call the +VIDIOC_CROPCAP ioctl with a pointer to this +structure. Drivers fill the rest of the structure. The results are +constant except when switching the video standard. Remember this +switch can occur implicit when switching the video input or +output. + + + struct <structname>v4l2_cropcap</structname> + + &cs-str; + + + &v4l2-buf-type; + type + Type of the data stream, set by the application. +Only these types are valid here: +V4L2_BUF_TYPE_VIDEO_CAPTURE, +V4L2_BUF_TYPE_VIDEO_OUTPUT, +V4L2_BUF_TYPE_VIDEO_OVERLAY, and custom (driver +defined) types with code V4L2_BUF_TYPE_PRIVATE +and higher. + + + struct v4l2_rect + bounds + Defines the window within capturing or output is +possible, this may exclude for example the horizontal and vertical +blanking areas. The cropping rectangle cannot exceed these limits. +Width and height are defined in pixels, the driver writer is free to +choose origin and units of the coordinate system in the analog +domain. + + + struct v4l2_rect + defrect + Default cropping rectangle, it shall cover the +"whole picture". Assuming pixel aspect 1/1 this could be for example a +640 × 480 rectangle for NTSC, a +768 × 576 rectangle for PAL and SECAM centered over +the active picture area. The same co-ordinate system as for + bounds is used. + + + &v4l2-fract; + pixelaspect + This is the pixel aspect (y / x) when no +scaling is applied, the ratio of the actual sampling +frequency and the frequency required to get square +pixels.When cropping coordinates refer to square pixels, +the driver sets pixelaspect to 1/1. Other +common values are 54/59 for PAL and SECAM, 11/10 for NTSC sampled +according to []. + + + +
+ + + + + struct <structname>v4l2_rect</structname> + + &cs-str; + + + __s32 + left + Horizontal offset of the top, left corner of the +rectangle, in pixels. + + + __s32 + top + Vertical offset of the top, left corner of the +rectangle, in pixels. + + + __s32 + width + Width of the rectangle, in pixels. + + + __s32 + height + Height of the rectangle, in pixels. Width +and height cannot be negative, the fields are signed for +hysterical reasons. + + + + +
+ + + + &return-value; + + + + EINVAL + + The &v4l2-cropcap; type is +invalid or the ioctl is not supported. This is not permitted for +video capture, output and overlay devices, which must support +VIDIOC_CROPCAP. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-dbg-g-chip-ident.xml b/Documentation/DocBook/v4l/vidioc-dbg-g-chip-ident.xml new file mode 100644 index 000000000000..4a09e203af0f --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-dbg-g-chip-ident.xml @@ -0,0 +1,275 @@ + + + ioctl VIDIOC_DBG_G_CHIP_IDENT + &manvol; + + + + VIDIOC_DBG_G_CHIP_IDENT + Identify the chips on a TV card + + + + + + int ioctl + int fd + int request + struct v4l2_dbg_chip_ident +*argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_DBG_G_CHIP_IDENT + + + + argp + + + + + + + + + Description + + + Experimental + + This is an experimental interface and may change in +the future. + + + For driver debugging purposes this ioctl allows test +applications to query the driver about the chips present on the TV +card. Regular applications must not use it. When you found a chip +specific bug, please contact the linux-media mailing list (&v4l-ml;) +so it can be fixed. + + To query the driver applications must initialize the +match.type and +match.addr or match.name +fields of a &v4l2-dbg-chip-ident; +and call VIDIOC_DBG_G_CHIP_IDENT with a pointer to +this structure. On success the driver stores information about the +selected chip in the ident and +revision fields. On failure the structure +remains unchanged. + + When match.type is +V4L2_CHIP_MATCH_HOST, +match.addr selects the nth non-&i2c; chip +on the TV card. You can enumerate all chips by starting at zero and +incrementing match.addr by one until +VIDIOC_DBG_G_CHIP_IDENT fails with an &EINVAL;. +The number zero always selects the host chip, ⪚ the chip connected +to the PCI or USB bus. + + When match.type is +V4L2_CHIP_MATCH_I2C_DRIVER, +match.name contains the I2C driver name. +For instance +"saa7127" will match any chip +supported by the saa7127 driver, regardless of its &i2c; bus address. +When multiple chips supported by the same driver are present, the +ioctl will return V4L2_IDENT_AMBIGUOUS in the +ident field. + + When match.type is +V4L2_CHIP_MATCH_I2C_ADDR, +match.addr selects a chip by its 7 bit +&i2c; bus address. + + When match.type is +V4L2_CHIP_MATCH_AC97, +match.addr selects the nth AC97 chip +on the TV card. You can enumerate all chips by starting at zero and +incrementing match.addr by one until +VIDIOC_DBG_G_CHIP_IDENT fails with an &EINVAL;. + + On success, the ident field will +contain a chip ID from the Linux +media/v4l2-chip-ident.h header file, and the +revision field will contain a driver +specific value, or zero if no particular revision is associated with +this chip. + + When the driver could not identify the selected chip, +ident will contain +V4L2_IDENT_UNKNOWN. When no chip matched +the ioctl will succeed but the +ident field will contain +V4L2_IDENT_NONE. If multiple chips matched, +ident will contain +V4L2_IDENT_AMBIGUOUS. In all these cases the +revision field remains unchanged. + + This ioctl is optional, not all drivers may support it. It +was introduced in Linux 2.6.21, but the API was changed to the +one described here in 2.6.29. + + We recommended the v4l2-dbg +utility over calling this ioctl directly. It is available from the +LinuxTV v4l-dvb repository; see http://linuxtv.org/repo/ for +access instructions. + + + + struct <structname>v4l2_dbg_match</structname> + + &cs-ustr; + + + __u32 + type + See for a list of +possible types. + + + union + (anonymous) + + + + __u32 + addr + Match a chip by this number, interpreted according +to the type field. + + + + char + name[32] + Match a chip by this name, interpreted according +to the type field. + + + +
+ + + struct <structname>v4l2_dbg_chip_ident</structname> + + &cs-str; + + + struct v4l2_dbg_match + match + How to match the chip, see . + + + __u32 + ident + A chip identifier as defined in the Linux +media/v4l2-chip-ident.h header file, or one of +the values from . + + + __u32 + revision + A chip revision, chip and driver specific. + + + +
+ + + + Chip Match Types + + &cs-def; + + + V4L2_CHIP_MATCH_HOST + 0 + Match the nth chip on the card, zero for the + host chip. Does not match &i2c; chips. + + + V4L2_CHIP_MATCH_I2C_DRIVER + 1 + Match an &i2c; chip by its driver name. + + + V4L2_CHIP_MATCH_I2C_ADDR + 2 + Match a chip by its 7 bit &i2c; bus address. + + + V4L2_CHIP_MATCH_AC97 + 3 + Match the nth anciliary AC97 chip. + + + +
+ + + + Chip Identifiers + + &cs-def; + + + V4L2_IDENT_NONE + 0 + No chip matched. + + + V4L2_IDENT_AMBIGUOUS + 1 + Multiple chips matched. + + + V4L2_IDENT_UNKNOWN + 2 + A chip is present at this address, but the driver +could not identify it. + + + +
+ + + + &return-value; + + + + EINVAL + + The driver does not support this ioctl, or the +match_type is invalid. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-dbg-g-register.xml b/Documentation/DocBook/v4l/vidioc-dbg-g-register.xml new file mode 100644 index 000000000000..980c7f3e2fd6 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-dbg-g-register.xml @@ -0,0 +1,275 @@ + + + ioctl VIDIOC_DBG_G_REGISTER, VIDIOC_DBG_S_REGISTER + &manvol; + + + + VIDIOC_DBG_G_REGISTER + VIDIOC_DBG_S_REGISTER + Read or write hardware registers + + + + + + int ioctl + int fd + int request + struct v4l2_dbg_register *argp + + + + + int ioctl + int fd + int request + const struct v4l2_dbg_register +*argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_DBG_G_REGISTER, VIDIOC_DBG_S_REGISTER + + + + argp + + + + + + + + + Description + + + Experimental + + This is an experimental +interface and may change in the future. + + + For driver debugging purposes these ioctls allow test +applications to access hardware registers directly. Regular +applications must not use them. + + Since writing or even reading registers can jeopardize the +system security, its stability and damage the hardware, both ioctls +require superuser privileges. Additionally the Linux kernel must be +compiled with the CONFIG_VIDEO_ADV_DEBUG option +to enable these ioctls. + + To write a register applications must initialize all fields +of a &v4l2-dbg-register; and call +VIDIOC_DBG_S_REGISTER with a pointer to this +structure. The match.type and +match.addr or match.name +fields select a chip on the TV +card, the reg field specifies a register +number and the val field the value to be +written into the register. + + To read a register applications must initialize the +match.type, +match.chip or match.name and +reg fields, and call +VIDIOC_DBG_G_REGISTER with a pointer to this +structure. On success the driver stores the register value in the +val field. On failure the structure remains +unchanged. + + When match.type is +V4L2_CHIP_MATCH_HOST, +match.addr selects the nth non-&i2c; chip +on the TV card. The number zero always selects the host chip, ⪚ the +chip connected to the PCI or USB bus. You can find out which chips are +present with the &VIDIOC-DBG-G-CHIP-IDENT; ioctl. + + When match.type is +V4L2_CHIP_MATCH_I2C_DRIVER, +match.name contains the I2C driver name. +For instance +"saa7127" will match any chip +supported by the saa7127 driver, regardless of its &i2c; bus address. +When multiple chips supported by the same driver are present, the +effect of these ioctls is undefined. Again with the +&VIDIOC-DBG-G-CHIP-IDENT; ioctl you can find out which &i2c; chips are +present. + + When match.type is +V4L2_CHIP_MATCH_I2C_ADDR, +match.addr selects a chip by its 7 bit &i2c; +bus address. + + When match.type is +V4L2_CHIP_MATCH_AC97, +match.addr selects the nth AC97 chip +on the TV card. + + + Success not guaranteed + + Due to a flaw in the Linux &i2c; bus driver these ioctls may +return successfully without actually reading or writing a register. To +catch the most likely failure we recommend a &VIDIOC-DBG-G-CHIP-IDENT; +call confirming the presence of the selected &i2c; chip. + + + These ioctls are optional, not all drivers may support them. +However when a driver supports these ioctls it must also support +&VIDIOC-DBG-G-CHIP-IDENT;. Conversely it may support +VIDIOC_DBG_G_CHIP_IDENT but not these ioctls. + + VIDIOC_DBG_G_REGISTER and +VIDIOC_DBG_S_REGISTER were introduced in Linux +2.6.21, but their API was changed to the one described here in kernel 2.6.29. + + We recommended the v4l2-dbg +utility over calling these ioctls directly. It is available from the +LinuxTV v4l-dvb repository; see http://linuxtv.org/repo/ for +access instructions. + + + + struct <structname>v4l2_dbg_match</structname> + + &cs-ustr; + + + __u32 + type + See for a list of +possible types. + + + union + (anonymous) + + + + __u32 + addr + Match a chip by this number, interpreted according +to the type field. + + + + char + name[32] + Match a chip by this name, interpreted according +to the type field. + + + +
+ + + + struct <structname>v4l2_dbg_register</structname> + + + + + + + struct v4l2_dbg_match + match + How to match the chip, see . + + + __u64 + reg + A register number. + + + __u64 + val + The value read from, or to be written into the +register. + + + +
+ + + + Chip Match Types + + &cs-def; + + + V4L2_CHIP_MATCH_HOST + 0 + Match the nth chip on the card, zero for the + host chip. Does not match &i2c; chips. + + + V4L2_CHIP_MATCH_I2C_DRIVER + 1 + Match an &i2c; chip by its driver name. + + + V4L2_CHIP_MATCH_I2C_ADDR + 2 + Match a chip by its 7 bit &i2c; bus address. + + + V4L2_CHIP_MATCH_AC97 + 3 + Match the nth anciliary AC97 chip. + + + +
+ + + + &return-value; + + + + EINVAL + + The driver does not support this ioctl, or the kernel +was not compiled with the CONFIG_VIDEO_ADV_DEBUG +option, or the match_type is invalid, or the +selected chip or register does not exist. + + + + EPERM + + Insufficient permissions. Root privileges are required +to execute these ioctls. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-encoder-cmd.xml b/Documentation/DocBook/v4l/vidioc-encoder-cmd.xml new file mode 100644 index 000000000000..b0dde943825c --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-encoder-cmd.xml @@ -0,0 +1,204 @@ + + + ioctl VIDIOC_ENCODER_CMD, VIDIOC_TRY_ENCODER_CMD + &manvol; + + + + VIDIOC_ENCODER_CMD + VIDIOC_TRY_ENCODER_CMD + Execute an encoder command + + + + + + int ioctl + int fd + int request + struct v4l2_encoder_cmd *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_ENCODER_CMD, VIDIOC_TRY_ENCODER_CMD + + + + argp + + + + + + + + + Description + + + Experimental + + This is an experimental +interface and may change in the future. + + + These ioctls control an audio/video (usually MPEG-) encoder. +VIDIOC_ENCODER_CMD sends a command to the +encoder, VIDIOC_TRY_ENCODER_CMD can be used to +try a command without actually executing it. + + To send a command applications must initialize all fields of a + &v4l2-encoder-cmd; and call + VIDIOC_ENCODER_CMD or + VIDIOC_TRY_ENCODER_CMD with a pointer to this + structure. + + The cmd field must contain the +command code. The flags field is currently +only used by the STOP command and contains one bit: If the +V4L2_ENC_CMD_STOP_AT_GOP_END flag is set, +encoding will continue until the end of the current Group +Of Pictures, otherwise it will stop immediately. + + A read() call sends a START command to +the encoder if it has not been started yet. After a STOP command, +read() calls will read the remaining data +buffered by the driver. When the buffer is empty, +read() will return zero and the next +read() call will restart the encoder. + + A close() call sends an immediate STOP +to the encoder, and all buffered data is discarded. + + These ioctls are optional, not all drivers may support +them. They were introduced in Linux 2.6.21. + + + struct <structname>v4l2_encoder_cmd</structname> + + &cs-str; + + + __u32 + cmd + The encoder command, see . + + + __u32 + flags + Flags to go with the command, see . If no flags are defined for +this command, drivers and applications must set this field to +zero. + + + __u32 + data[8] + Reserved for future extensions. Drivers and +applications must set the array to zero. + + + +
+ + + Encoder Commands + + &cs-def; + + + V4L2_ENC_CMD_START + 0 + Start the encoder. When the encoder is already +running or paused, this command does nothing. No flags are defined for +this command. + + + V4L2_ENC_CMD_STOP + 1 + Stop the encoder. When the +V4L2_ENC_CMD_STOP_AT_GOP_END flag is set, +encoding will continue until the end of the current Group +Of Pictures, otherwise encoding will stop immediately. +When the encoder is already stopped, this command does +nothing. + + + V4L2_ENC_CMD_PAUSE + 2 + Pause the encoder. When the encoder has not been +started yet, the driver will return an &EPERM;. When the encoder is +already paused, this command does nothing. No flags are defined for +this command. + + + V4L2_ENC_CMD_RESUME + 3 + Resume encoding after a PAUSE command. When the +encoder has not been started yet, the driver will return an &EPERM;. +When the encoder is already running, this command does nothing. No +flags are defined for this command. + + + +
+ + + Encoder Command Flags + + &cs-def; + + + V4L2_ENC_CMD_STOP_AT_GOP_END + 0x0001 + Stop encoding at the end of the current Group Of +Pictures, rather than immediately. + + + +
+ + + + &return-value; + + + + EINVAL + + The driver does not support this ioctl, or the +cmd field is invalid. + + + + EPERM + + The application sent a PAUSE or RESUME command when +the encoder was not running. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-enum-fmt.xml b/Documentation/DocBook/v4l/vidioc-enum-fmt.xml new file mode 100644 index 000000000000..960d44615ca6 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-enum-fmt.xml @@ -0,0 +1,164 @@ + + + ioctl VIDIOC_ENUM_FMT + &manvol; + + + + VIDIOC_ENUM_FMT + Enumerate image formats + + + + + + int ioctl + int fd + int request + struct v4l2_fmtdesc +*argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_ENUM_FMT + + + + argp + + + + + + + + + Description + + To enumerate image formats applications initialize the +type and index +field of &v4l2-fmtdesc; and call the +VIDIOC_ENUM_FMT ioctl with a pointer to this +structure. Drivers fill the rest of the structure or return an +&EINVAL;. All formats are enumerable by beginning at index zero and +incrementing by one until EINVAL is +returned. + + + struct <structname>v4l2_fmtdesc</structname> + + &cs-str; + + + __u32 + index + Number of the format in the enumeration, set by +the application. This is in no way related to the +pixelformat field. + + + &v4l2-buf-type; + type + Type of the data stream, set by the application. +Only these types are valid here: +V4L2_BUF_TYPE_VIDEO_CAPTURE, +V4L2_BUF_TYPE_VIDEO_OUTPUT, +V4L2_BUF_TYPE_VIDEO_OVERLAY, and custom (driver +defined) types with code V4L2_BUF_TYPE_PRIVATE +and higher. + + + __u32 + flags + See + + + __u8 + description[32] + Description of the format, a NUL-terminated ASCII +string. This information is intended for the user, for example: "YUV +4:2:2". + + + __u32 + pixelformat + The image format identifier. This is a +four character code as computed by the v4l2_fourcc() +macro: + + + +#define v4l2_fourcc(a,b,c,d) (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24)) +Several image formats are already +defined by this specification in . Note these +codes are not the same as those used in the Windows world. + + + __u32 + reserved[4] + Reserved for future extensions. Drivers must set +the array to zero. + + + +
+ + + Image Format Description Flags + + &cs-def; + + + V4L2_FMT_FLAG_COMPRESSED + 0x0001 + This is a compressed format. + + + V4L2_FMT_FLAG_EMULATED + 0x0002 + This format is not native to the device but emulated +through software (usually libv4l2), where possible try to use a native format +instead for better performance. + + + +
+ + + + &return-value; + + + + EINVAL + + The &v4l2-fmtdesc; type +is not supported or the index is out of +bounds. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-enum-frameintervals.xml b/Documentation/DocBook/v4l/vidioc-enum-frameintervals.xml new file mode 100644 index 000000000000..3c216e113a54 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-enum-frameintervals.xml @@ -0,0 +1,270 @@ + + + + ioctl VIDIOC_ENUM_FRAMEINTERVALS + &manvol; + + + + VIDIOC_ENUM_FRAMEINTERVALS + Enumerate frame intervals + + + + + + int ioctl + int fd + int request + struct v4l2_frmivalenum *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_ENUM_FRAMEINTERVALS + + + + argp + + Pointer to a &v4l2-frmivalenum; structure that +contains a pixel format and size and receives a frame interval. + + + + + + + Description + + This ioctl allows applications to enumerate all frame +intervals that the device supports for the given pixel format and +frame size. + The supported pixel formats and frame sizes can be obtained +by using the &VIDIOC-ENUM-FMT; and &VIDIOC-ENUM-FRAMESIZES; +functions. + The return value and the content of the +v4l2_frmivalenum.type field depend on the +type of frame intervals the device supports. Here are the semantics of +the function for the different cases: + + + Discrete: The function +returns success if the given index value (zero-based) is valid. The +application should increase the index by one for each call until +EINVAL is returned. The `v4l2_frmivalenum.type` +field is set to `V4L2_FRMIVAL_TYPE_DISCRETE` by the driver. Of the +union only the `discrete` member is valid. + + + Step-wise: The function +returns success if the given index value is zero and +EINVAL for any other index value. The +v4l2_frmivalenum.type field is set to +V4L2_FRMIVAL_TYPE_STEPWISE by the driver. Of the +union only the stepwise member is +valid. + + + Continuous: This is a +special case of the step-wise type above. The function returns success +if the given index value is zero and EINVAL for +any other index value. The +v4l2_frmivalenum.type field is set to +V4L2_FRMIVAL_TYPE_CONTINUOUS by the driver. Of +the union only the stepwise member is valid +and the step value is set to 1. + + + + When the application calls the function with index zero, it +must check the type field to determine the +type of frame interval enumeration the device supports. Only for the +V4L2_FRMIVAL_TYPE_DISCRETE type does it make +sense to increase the index value to receive more frame +intervals. + Note that the order in which the frame intervals are +returned has no special meaning. In particular does it not say +anything about potential default frame intervals. + Applications can assume that the enumeration data does not +change without any interaction from the application itself. This means +that the enumeration data is consistent if the application does not +perform any other ioctl calls while it runs the frame interval +enumeration. + + + + Notes + + + + Frame intervals and frame +rates: The V4L2 API uses frame intervals instead of frame +rates. Given the frame interval the frame rate can be computed as +follows:frame_rate = 1 / frame_interval + + + + + + + Structs + + In the structs below, IN denotes a +value that has to be filled in by the application, +OUT denotes values that the driver fills in. The +application should zero out all members except for the +IN fields. + + + struct <structname>v4l2_frmival_stepwise</structname> + + &cs-str; + + + &v4l2-fract; + min + Minimum frame interval [s]. + + + &v4l2-fract; + max + Maximum frame interval [s]. + + + &v4l2-fract; + step + Frame interval step size [s]. + + + +
+ + + struct <structname>v4l2_frmivalenum</structname> + + + + + + + + __u32 + index + + IN: Index of the given frame interval in the +enumeration. + + + __u32 + pixel_format + + IN: Pixel format for which the frame intervals are +enumerated. + + + __u32 + width + + IN: Frame width for which the frame intervals are +enumerated. + + + __u32 + height + + IN: Frame height for which the frame intervals are +enumerated. + + + __u32 + type + + OUT: Frame interval type the device supports. + + + union + + + OUT: Frame interval with the given index. + + + + &v4l2-fract; + discrete + Frame interval [s]. + + + + &v4l2-frmival-stepwise; + stepwise + + + + __u32 + reserved[2] + + Reserved space for future use. + + + +
+ + + + Enums + + + enum <structname>v4l2_frmivaltypes</structname> + + &cs-def; + + + V4L2_FRMIVAL_TYPE_DISCRETE + 1 + Discrete frame interval. + + + V4L2_FRMIVAL_TYPE_CONTINUOUS + 2 + Continuous frame interval. + + + V4L2_FRMIVAL_TYPE_STEPWISE + 3 + Step-wise defined frame interval. + + + +
+ + + + &return-value; + + See the description section above for a list of return +values that errno can have. + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-enum-framesizes.xml b/Documentation/DocBook/v4l/vidioc-enum-framesizes.xml new file mode 100644 index 000000000000..6afa4542c818 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-enum-framesizes.xml @@ -0,0 +1,282 @@ + + + + ioctl VIDIOC_ENUM_FRAMESIZES + &manvol; + + + + VIDIOC_ENUM_FRAMESIZES + Enumerate frame sizes + + + + + + int ioctl + int fd + int request + struct v4l2_frmsizeenum *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_ENUM_FRAMESIZES + + + + argp + + Pointer to a &v4l2-frmsizeenum; that contains an index +and pixel format and receives a frame width and height. + + + + + + + Description + + + Experimental + + This is an experimental +interface and may change in the future. + + + This ioctl allows applications to enumerate all frame sizes +(&ie; width and height in pixels) that the device supports for the +given pixel format. + The supported pixel formats can be obtained by using the +&VIDIOC-ENUM-FMT; function. + The return value and the content of the +v4l2_frmsizeenum.type field depend on the +type of frame sizes the device supports. Here are the semantics of the +function for the different cases: + + + + Discrete: The function +returns success if the given index value (zero-based) is valid. The +application should increase the index by one for each call until +EINVAL is returned. The +v4l2_frmsizeenum.type field is set to +V4L2_FRMSIZE_TYPE_DISCRETE by the driver. Of the +union only the discrete member is +valid. + + + Step-wise: The function +returns success if the given index value is zero and +EINVAL for any other index value. The +v4l2_frmsizeenum.type field is set to +V4L2_FRMSIZE_TYPE_STEPWISE by the driver. Of the +union only the stepwise member is +valid. + + + Continuous: This is a +special case of the step-wise type above. The function returns success +if the given index value is zero and EINVAL for +any other index value. The +v4l2_frmsizeenum.type field is set to +V4L2_FRMSIZE_TYPE_CONTINUOUS by the driver. Of +the union only the stepwise member is valid +and the step_width and +step_height values are set to 1. + + + + When the application calls the function with index zero, it +must check the type field to determine the +type of frame size enumeration the device supports. Only for the +V4L2_FRMSIZE_TYPE_DISCRETE type does it make +sense to increase the index value to receive more frame sizes. + Note that the order in which the frame sizes are returned +has no special meaning. In particular does it not say anything about +potential default format sizes. + Applications can assume that the enumeration data does not +change without any interaction from the application itself. This means +that the enumeration data is consistent if the application does not +perform any other ioctl calls while it runs the frame size +enumeration. + + + + Structs + + In the structs below, IN denotes a +value that has to be filled in by the application, +OUT denotes values that the driver fills in. The +application should zero out all members except for the +IN fields. + + + struct <structname>v4l2_frmsize_discrete</structname> + + &cs-str; + + + __u32 + width + Width of the frame [pixel]. + + + __u32 + height + Height of the frame [pixel]. + + + +
+ + + struct <structname>v4l2_frmsize_stepwise</structname> + + &cs-str; + + + __u32 + min_width + Minimum frame width [pixel]. + + + __u32 + max_width + Maximum frame width [pixel]. + + + __u32 + step_width + Frame width step size [pixel]. + + + __u32 + min_height + Minimum frame height [pixel]. + + + __u32 + max_height + Maximum frame height [pixel]. + + + __u32 + step_height + Frame height step size [pixel]. + + + +
+ + + struct <structname>v4l2_frmsizeenum</structname> + + + + + + + + __u32 + index + + IN: Index of the given frame size in the enumeration. + + + __u32 + pixel_format + + IN: Pixel format for which the frame sizes are enumerated. + + + __u32 + type + + OUT: Frame size type the device supports. + + + union + + + OUT: Frame size with the given index. + + + + &v4l2-frmsize-discrete; + discrete + + + + + &v4l2-frmsize-stepwise; + stepwise + + + + __u32 + reserved[2] + + Reserved space for future use. + + + +
+ + + + Enums + + + enum <structname>v4l2_frmsizetypes</structname> + + &cs-def; + + + V4L2_FRMSIZE_TYPE_DISCRETE + 1 + Discrete frame size. + + + V4L2_FRMSIZE_TYPE_CONTINUOUS + 2 + Continuous frame size. + + + V4L2_FRMSIZE_TYPE_STEPWISE + 3 + Step-wise defined frame size. + + + +
+ + + + &return-value; + + See the description section above for a list of return +values that errno can have. + + + + diff --git a/Documentation/DocBook/v4l/vidioc-enumaudio.xml b/Documentation/DocBook/v4l/vidioc-enumaudio.xml new file mode 100644 index 000000000000..9ae8f2d3a96f --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-enumaudio.xml @@ -0,0 +1,86 @@ + + + ioctl VIDIOC_ENUMAUDIO + &manvol; + + + + VIDIOC_ENUMAUDIO + Enumerate audio inputs + + + + + + int ioctl + int fd + int request + struct v4l2_audio *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_ENUMAUDIO + + + + argp + + + + + + + + + Description + + To query the attributes of an audio input applications +initialize the index field and zero out the +reserved array of a &v4l2-audio; +and call the VIDIOC_ENUMAUDIO ioctl with a pointer +to this structure. Drivers fill the rest of the structure or return an +&EINVAL; when the index is out of bounds. To enumerate all audio +inputs applications shall begin at index zero, incrementing by one +until the driver returns EINVAL. + + See for a description of +&v4l2-audio;. + + + + &return-value; + + + + EINVAL + + The number of the audio input is out of bounds, or +there are no audio inputs at all and this ioctl is not +supported. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-enumaudioout.xml b/Documentation/DocBook/v4l/vidioc-enumaudioout.xml new file mode 100644 index 000000000000..d3d7c0ab17b8 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-enumaudioout.xml @@ -0,0 +1,89 @@ + + + ioctl VIDIOC_ENUMAUDOUT + &manvol; + + + + VIDIOC_ENUMAUDOUT + Enumerate audio outputs + + + + + + int ioctl + int fd + int request + struct v4l2_audioout *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_ENUMAUDOUT + + + + argp + + + + + + + + + Description + + To query the attributes of an audio output applications +initialize the index field and zero out the +reserved array of a &v4l2-audioout; and +call the VIDIOC_G_AUDOUT ioctl with a pointer +to this structure. Drivers fill the rest of the structure or return an +&EINVAL; when the index is out of bounds. To enumerate all audio +outputs applications shall begin at index zero, incrementing by one +until the driver returns EINVAL. + + Note connectors on a TV card to loop back the received audio +signal to a sound card are not audio outputs in this sense. + + See for a description of +&v4l2-audioout;. + + + + &return-value; + + + + EINVAL + + The number of the audio output is out of bounds, or +there are no audio outputs at all and this ioctl is not +supported. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-enuminput.xml b/Documentation/DocBook/v4l/vidioc-enuminput.xml new file mode 100644 index 000000000000..414856b82473 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-enuminput.xml @@ -0,0 +1,287 @@ + + + ioctl VIDIOC_ENUMINPUT + &manvol; + + + + VIDIOC_ENUMINPUT + Enumerate video inputs + + + + + + int ioctl + int fd + int request + struct v4l2_input +*argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_ENUMINPUT + + + + argp + + + + + + + + + Description + + To query the attributes of a video input applications +initialize the index field of &v4l2-input; +and call the VIDIOC_ENUMINPUT ioctl with a +pointer to this structure. Drivers fill the rest of the structure or +return an &EINVAL; when the index is out of bounds. To enumerate all +inputs applications shall begin at index zero, incrementing by one +until the driver returns EINVAL. + + + struct <structname>v4l2_input</structname> + + &cs-str; + + + __u32 + index + Identifies the input, set by the +application. + + + __u8 + name[32] + Name of the video input, a NUL-terminated ASCII +string, for example: "Vin (Composite 2)". This information is intended +for the user, preferably the connector label on the device itself. + + + __u32 + type + Type of the input, see . + + + __u32 + audioset + Drivers can enumerate up to 32 video and +audio inputs. This field shows which audio inputs were selectable as +audio source if this was the currently selected video input. It is a +bit mask. The LSB corresponds to audio input 0, the MSB to input 31. +Any number of bits can be set, or none.When the driver +does not enumerate audio inputs no bits must be set. Applications +shall not interpret this as lack of audio support. Some drivers +automatically select audio sources and do not enumerate them since +there is no choice anyway.For details on audio inputs and +how to select the current input see . + + + __u32 + tuner + Capture devices can have zero or more tuners (RF +demodulators). When the type is set to +V4L2_INPUT_TYPE_TUNER this is an RF connector and +this field identifies the tuner. It corresponds to +&v4l2-tuner; field index. For details on +tuners see . + + + &v4l2-std-id; + std + Every video input supports one or more different +video standards. This field is a set of all supported standards. For +details on video standards and how to switch see . + + + __u32 + status + This field provides status information about the +input. See for flags. +With the exception of the sensor orientation bits status is only valid when this is the +current input. + + + __u32 + reserved[4] + Reserved for future extensions. Drivers must set +the array to zero. + + + +
+ + + Input Types + + &cs-def; + + + V4L2_INPUT_TYPE_TUNER + 1 + This input uses a tuner (RF demodulator). + + + V4L2_INPUT_TYPE_CAMERA + 2 + Analog baseband input, for example CVBS / +Composite Video, S-Video, RGB. + + + +
+ + + + + Input Status Flags + + + + + + + + General + + + V4L2_IN_ST_NO_POWER + 0x00000001 + Attached device is off. + + + V4L2_IN_ST_NO_SIGNAL + 0x00000002 + + + + V4L2_IN_ST_NO_COLOR + 0x00000004 + The hardware supports color decoding, but does not +detect color modulation in the signal. + + + Sensor Orientation + + + V4L2_IN_ST_HFLIP + 0x00000010 + The input is connected to a device that produces a signal +that is flipped horizontally and does not correct this before passing the +signal to userspace. + + + V4L2_IN_ST_VFLIP + 0x00000020 + The input is connected to a device that produces a signal +that is flipped vertically and does not correct this before passing the +signal to userspace. Note that a 180 degree rotation is the same as HFLIP | VFLIP + + + Analog Video + + + V4L2_IN_ST_NO_H_LOCK + 0x00000100 + No horizontal sync lock. + + + V4L2_IN_ST_COLOR_KILL + 0x00000200 + A color killer circuit automatically disables color +decoding when it detects no color modulation. When this flag is set +the color killer is enabled and has shut off +color decoding. + + + Digital Video + + + V4L2_IN_ST_NO_SYNC + 0x00010000 + No synchronization lock. + + + V4L2_IN_ST_NO_EQU + 0x00020000 + No equalizer lock. + + + V4L2_IN_ST_NO_CARRIER + 0x00040000 + Carrier recovery failed. + + + VCR and Set-Top Box + + + V4L2_IN_ST_MACROVISION + 0x01000000 + Macrovision is an analog copy prevention system +mangling the video signal to confuse video recorders. When this +flag is set Macrovision has been detected. + + + V4L2_IN_ST_NO_ACCESS + 0x02000000 + Conditional access denied. + + + V4L2_IN_ST_VTR + 0x04000000 + VTR time constant. [?] + + + +
+ + + + &return-value; + + + + EINVAL + + The &v4l2-input; index is +out of bounds. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-enumoutput.xml b/Documentation/DocBook/v4l/vidioc-enumoutput.xml new file mode 100644 index 000000000000..e8d16dcd50cf --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-enumoutput.xml @@ -0,0 +1,172 @@ + + + ioctl VIDIOC_ENUMOUTPUT + &manvol; + + + + VIDIOC_ENUMOUTPUT + Enumerate video outputs + + + + + + int ioctl + int fd + int request + struct v4l2_output *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_ENUMOUTPUT + + + + argp + + + + + + + + + Description + + To query the attributes of a video outputs applications +initialize the index field of &v4l2-output; +and call the VIDIOC_ENUMOUTPUT ioctl with a +pointer to this structure. Drivers fill the rest of the structure or +return an &EINVAL; when the index is out of bounds. To enumerate all +outputs applications shall begin at index zero, incrementing by one +until the driver returns EINVAL. + + + struct <structname>v4l2_output</structname> + + &cs-str; + + + __u32 + index + Identifies the output, set by the +application. + + + __u8 + name[32] + Name of the video output, a NUL-terminated ASCII +string, for example: "Vout". This information is intended for the +user, preferably the connector label on the device itself. + + + __u32 + type + Type of the output, see . + + + __u32 + audioset + Drivers can enumerate up to 32 video and +audio outputs. This field shows which audio outputs were +selectable as the current output if this was the currently selected +video output. It is a bit mask. The LSB corresponds to audio output 0, +the MSB to output 31. Any number of bits can be set, or +none.When the driver does not enumerate audio outputs no +bits must be set. Applications shall not interpret this as lack of +audio support. Drivers may automatically select audio outputs without +enumerating them.For details on audio outputs and how to +select the current output see . + + + __u32 + modulator + Output devices can have zero or more RF modulators. +When the type is +V4L2_OUTPUT_TYPE_MODULATOR this is an RF +connector and this field identifies the modulator. It corresponds to +&v4l2-modulator; field index. For details +on modulators see . + + + &v4l2-std-id; + std + Every video output supports one or more different +video standards. This field is a set of all supported standards. For +details on video standards and how to switch see . + + + __u32 + reserved[4] + Reserved for future extensions. Drivers must set +the array to zero. + + + +
+ + + Output Type + + &cs-def; + + + V4L2_OUTPUT_TYPE_MODULATOR + 1 + This output is an analog TV modulator. + + + V4L2_OUTPUT_TYPE_ANALOG + 2 + Analog baseband output, for example Composite / +CVBS, S-Video, RGB. + + + V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY + 3 + [?] + + + +
+ + + + &return-value; + + + + EINVAL + + The &v4l2-output; index +is out of bounds. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-enumstd.xml b/Documentation/DocBook/v4l/vidioc-enumstd.xml new file mode 100644 index 000000000000..95803fe2c8e4 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-enumstd.xml @@ -0,0 +1,391 @@ + + + ioctl VIDIOC_ENUMSTD + &manvol; + + + + VIDIOC_ENUMSTD + Enumerate supported video standards + + + + + + int ioctl + int fd + int request + struct v4l2_standard *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_ENUMSTD + + + + argp + + + + + + + + + Description + + To query the attributes of a video standard, +especially a custom (driver defined) one, applications initialize the +index field of &v4l2-standard; and call the +VIDIOC_ENUMSTD ioctl with a pointer to this +structure. Drivers fill the rest of the structure or return an +&EINVAL; when the index is out of bounds. To enumerate all standards +applications shall begin at index zero, incrementing by one until the +driver returns EINVAL. Drivers may enumerate a +different set of standards after switching the video input or +output. + The supported standards may overlap and we need an +unambiguous set to find the current standard returned by +VIDIOC_G_STD. + + + + struct <structname>v4l2_standard</structname> + + &cs-str; + + + __u32 + index + Number of the video standard, set by the +application. + + + &v4l2-std-id; + id + The bits in this field identify the standard as +one of the common standards listed in , +or if bits 32 to 63 are set as custom standards. Multiple bits can be +set if the hardware does not distinguish between these standards, +however separate indices do not indicate the opposite. The +id must be unique. No other enumerated +v4l2_standard structure, for this input or +output anyway, can contain the same set of bits. + + + __u8 + name[24] + Name of the standard, a NUL-terminated ASCII +string, for example: "PAL-B/G", "NTSC Japan". This information is +intended for the user. + + + &v4l2-fract; + frameperiod + The frame period (not field period) is numerator +/ denominator. For example M/NTSC has a frame period of 1001 / +30000 seconds. + + + __u32 + framelines + Total lines per frame including blanking, +e. g. 625 for B/PAL. + + + __u32 + reserved[4] + Reserved for future extensions. Drivers must set +the array to zero. + + + +
+ + + struct <structname>v4l2_fract</structname> + + &cs-str; + + + __u32 + numerator + + + + __u32 + denominator + + + + +
+ + + typedef <structname>v4l2_std_id</structname> + + &cs-str; + + + __u64 + v4l2_std_id + This type is a set, each bit representing another +video standard as listed below and in . The 32 most significant bits are reserved +for custom (driver defined) video standards. + + + +
+ + +#define V4L2_STD_PAL_B ((v4l2_std_id)0x00000001) +#define V4L2_STD_PAL_B1 ((v4l2_std_id)0x00000002) +#define V4L2_STD_PAL_G ((v4l2_std_id)0x00000004) +#define V4L2_STD_PAL_H ((v4l2_std_id)0x00000008) +#define V4L2_STD_PAL_I ((v4l2_std_id)0x00000010) +#define V4L2_STD_PAL_D ((v4l2_std_id)0x00000020) +#define V4L2_STD_PAL_D1 ((v4l2_std_id)0x00000040) +#define V4L2_STD_PAL_K ((v4l2_std_id)0x00000080) + +#define V4L2_STD_PAL_M ((v4l2_std_id)0x00000100) +#define V4L2_STD_PAL_N ((v4l2_std_id)0x00000200) +#define V4L2_STD_PAL_Nc ((v4l2_std_id)0x00000400) +#define V4L2_STD_PAL_60 ((v4l2_std_id)0x00000800) +V4L2_STD_PAL_60 is +a hybrid standard with 525 lines, 60 Hz refresh rate, and PAL color +modulation with a 4.43 MHz color subcarrier. Some PAL video recorders +can play back NTSC tapes in this mode for display on a 50/60 Hz agnostic +PAL TV. +#define V4L2_STD_NTSC_M ((v4l2_std_id)0x00001000) +#define V4L2_STD_NTSC_M_JP ((v4l2_std_id)0x00002000) +#define V4L2_STD_NTSC_443 ((v4l2_std_id)0x00004000) +V4L2_STD_NTSC_443 +is a hybrid standard with 525 lines, 60 Hz refresh rate, and NTSC +color modulation with a 4.43 MHz color +subcarrier. +#define V4L2_STD_NTSC_M_KR ((v4l2_std_id)0x00008000) + +#define V4L2_STD_SECAM_B ((v4l2_std_id)0x00010000) +#define V4L2_STD_SECAM_D ((v4l2_std_id)0x00020000) +#define V4L2_STD_SECAM_G ((v4l2_std_id)0x00040000) +#define V4L2_STD_SECAM_H ((v4l2_std_id)0x00080000) +#define V4L2_STD_SECAM_K ((v4l2_std_id)0x00100000) +#define V4L2_STD_SECAM_K1 ((v4l2_std_id)0x00200000) +#define V4L2_STD_SECAM_L ((v4l2_std_id)0x00400000) +#define V4L2_STD_SECAM_LC ((v4l2_std_id)0x00800000) + +/* ATSC/HDTV */ +#define V4L2_STD_ATSC_8_VSB ((v4l2_std_id)0x01000000) +#define V4L2_STD_ATSC_16_VSB ((v4l2_std_id)0x02000000) +V4L2_STD_ATSC_8_VSB and +V4L2_STD_ATSC_16_VSB are U.S. terrestrial digital +TV standards. Presently the V4L2 API does not support digital TV. See +also the Linux DVB API at http://linuxtv.org. + +#define V4L2_STD_PAL_BG (V4L2_STD_PAL_B |\ + V4L2_STD_PAL_B1 |\ + V4L2_STD_PAL_G) +#define V4L2_STD_B (V4L2_STD_PAL_B |\ + V4L2_STD_PAL_B1 |\ + V4L2_STD_SECAM_B) +#define V4L2_STD_GH (V4L2_STD_PAL_G |\ + V4L2_STD_PAL_H |\ + V4L2_STD_SECAM_G |\ + V4L2_STD_SECAM_H) +#define V4L2_STD_PAL_DK (V4L2_STD_PAL_D |\ + V4L2_STD_PAL_D1 |\ + V4L2_STD_PAL_K) +#define V4L2_STD_PAL (V4L2_STD_PAL_BG |\ + V4L2_STD_PAL_DK |\ + V4L2_STD_PAL_H |\ + V4L2_STD_PAL_I) +#define V4L2_STD_NTSC (V4L2_STD_NTSC_M |\ + V4L2_STD_NTSC_M_JP |\ + V4L2_STD_NTSC_M_KR) +#define V4L2_STD_MN (V4L2_STD_PAL_M |\ + V4L2_STD_PAL_N |\ + V4L2_STD_PAL_Nc |\ + V4L2_STD_NTSC) +#define V4L2_STD_SECAM_DK (V4L2_STD_SECAM_D |\ + V4L2_STD_SECAM_K |\ + V4L2_STD_SECAM_K1) +#define V4L2_STD_DK (V4L2_STD_PAL_DK |\ + V4L2_STD_SECAM_DK) + +#define V4L2_STD_SECAM (V4L2_STD_SECAM_B |\ + V4L2_STD_SECAM_G |\ + V4L2_STD_SECAM_H |\ + V4L2_STD_SECAM_DK |\ + V4L2_STD_SECAM_L |\ + V4L2_STD_SECAM_LC) + +#define V4L2_STD_525_60 (V4L2_STD_PAL_M |\ + V4L2_STD_PAL_60 |\ + V4L2_STD_NTSC |\ + V4L2_STD_NTSC_443) +#define V4L2_STD_625_50 (V4L2_STD_PAL |\ + V4L2_STD_PAL_N |\ + V4L2_STD_PAL_Nc |\ + V4L2_STD_SECAM) + +#define V4L2_STD_UNKNOWN 0 +#define V4L2_STD_ALL (V4L2_STD_525_60 |\ + V4L2_STD_625_50) + + + + Video Standards (based on [<xref linkend="itu470" />]) + + + + + + + + + + + + + + + + Characteristics + M/NTSCJapan uses a standard +similar to M/NTSC +(V4L2_STD_NTSC_M_JP). + M/PAL + N/PAL The values in +brackets apply to the combination N/PAL a.k.a. +NC used in Argentina +(V4L2_STD_PAL_Nc). + B, B1, G/PAL + D, D1, K/PAL + H/PAL + I/PAL + B, G/SECAM + D, K/SECAM + K1/SECAM + L/SECAM + + + + + Frame lines + 525 + 625 + + + Frame period (s) + 1001/30000 + 1/25 + + + Chrominance sub-carrier frequency (Hz) + 3579545 ± 10 + 3579611.49 ± 10 + 4433618.75 ± 5 (3582056.25 +± 5) + 4433618.75 ± 5 + 4433618.75 ± 1 + fOR = +4406250 ± 2000, fOB = 4250000 +± 2000 + + + Nominal radio-frequency channel bandwidth +(MHz) + 6 + 6 + 6 + B: 7; B1, G: 8 + 8 + 8 + 8 + 8 + 8 + 8 + 8 + + + Sound carrier relative to vision carrier +(MHz) + + 4.5 + + 4.5 + + 4.5 + + 5.5 ± 0.001 +In the Federal Republic of Germany, Austria, Italy, +the Netherlands, Slovakia and Switzerland a system of two sound +carriers is used, the frequency of the second carrier being +242.1875 kHz above the frequency of the first sound carrier. For +stereophonic sound transmissions a similar system is used in +Australia. New Zealand uses a sound +carrier displaced 5.4996 ± 0.0005 MHz from the vision +carrier. In Denmark, Finland, New +Zealand, Sweden and Spain a system of two sound carriers is used. In +Iceland, Norway and Poland the same system is being introduced. The +second carrier is 5.85 MHz above the vision carrier and is DQPSK +modulated with 728 kbit/s sound and data multiplex. (NICAM +system) In the United Kingdom, a +system of two sound carriers is used. The second sound carrier is +6.552 MHz above the vision carrier and is DQPSK modulated with a +728 kbit/s sound and data multiplex able to carry two sound +channels. (NICAM system) + + 6.5 ± 0.001 + + 5.5 + + 5.9996 ± 0.0005 + + 5.5 ± 0.001 + + 6.5 ± 0.001 + + 6.5 + + 6.5 In France, a +digital carrier 5.85 MHz away from the vision carrier may be used in +addition to the main sound carrier. It is modulated in differentially +encoded QPSK with a 728 kbit/s sound and data multiplexer capable of +carrying two sound channels. (NICAM +system) + + + +
+ + + + &return-value; + + + + EINVAL + + The &v4l2-standard; index +is out of bounds. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-audio.xml b/Documentation/DocBook/v4l/vidioc-g-audio.xml new file mode 100644 index 000000000000..65361a8c2b05 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-audio.xml @@ -0,0 +1,188 @@ + + + ioctl VIDIOC_G_AUDIO, VIDIOC_S_AUDIO + &manvol; + + + + VIDIOC_G_AUDIO + VIDIOC_S_AUDIO + Query or select the current audio input and its +attributes + + + + + + int ioctl + int fd + int request + struct v4l2_audio *argp + + + + + int ioctl + int fd + int request + const struct v4l2_audio *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_AUDIO, VIDIOC_S_AUDIO + + + + argp + + + + + + + + + Description + + To query the current audio input applications zero out the +reserved array of a &v4l2-audio; +and call the VIDIOC_G_AUDIO ioctl with a pointer +to this structure. Drivers fill the rest of the structure or return an +&EINVAL; when the device has no audio inputs, or none which combine +with the current video input. + + Audio inputs have one writable property, the audio mode. To +select the current audio input and change the +audio mode, applications initialize the +index and mode +fields, and the +reserved array of a +v4l2_audio structure and call the +VIDIOC_S_AUDIO ioctl. Drivers may switch to a +different audio mode if the request cannot be satisfied. However, this +is a write-only ioctl, it does not return the actual new audio +mode. + + + struct <structname>v4l2_audio</structname> + + &cs-str; + + + __u32 + index + Identifies the audio input, set by the +driver or application. + + + __u8 + name[32] + Name of the audio input, a NUL-terminated ASCII +string, for example: "Line In". This information is intended for the +user, preferably the connector label on the device itself. + + + __u32 + capability + Audio capability flags, see . + + + __u32 + mode + Audio mode flags set by drivers and applications (on + VIDIOC_S_AUDIO ioctl), see . + + + __u32 + reserved[2] + Reserved for future extensions. Drivers and +applications must set the array to zero. + + + +
+ + + Audio Capability Flags + + &cs-def; + + + V4L2_AUDCAP_STEREO + 0x00001 + This is a stereo input. The flag is intended to +automatically disable stereo recording etc. when the signal is always +monaural. The API provides no means to detect if stereo is +received, unless the audio input belongs to a +tuner. + + + V4L2_AUDCAP_AVL + 0x00002 + Automatic Volume Level mode is supported. + + + +
+ + + Audio Mode Flags + + &cs-def; + + + V4L2_AUDMODE_AVL + 0x00001 + AVL mode is on. + + + +
+ + + + &return-value; + + + + EINVAL + + No audio inputs combine with the current video input, +or the number of the selected audio input is out of bounds or it does +not combine, or there are no audio inputs at all and the ioctl is not +supported. + + + + EBUSY + + I/O is in progress, the input cannot be +switched. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-audioout.xml b/Documentation/DocBook/v4l/vidioc-g-audioout.xml new file mode 100644 index 000000000000..3632730c5c6e --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-audioout.xml @@ -0,0 +1,154 @@ + + + ioctl VIDIOC_G_AUDOUT, VIDIOC_S_AUDOUT + &manvol; + + + + VIDIOC_G_AUDOUT + VIDIOC_S_AUDOUT + Query or select the current audio output + + + + + + int ioctl + int fd + int request + struct v4l2_audioout *argp + + + + + int ioctl + int fd + int request + const struct v4l2_audioout *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_AUDOUT, VIDIOC_S_AUDOUT + + + + argp + + + + + + + + + Description + + To query the current audio output applications zero out the +reserved array of a &v4l2-audioout; and +call the VIDIOC_G_AUDOUT ioctl with a pointer +to this structure. Drivers fill the rest of the structure or return an +&EINVAL; when the device has no audio inputs, or none which combine +with the current video output. + + Audio outputs have no writable properties. Nevertheless, to +select the current audio output applications can initialize the +index field and +reserved array (which in the future may +contain writable properties) of a +v4l2_audioout structure and call the +VIDIOC_S_AUDOUT ioctl. Drivers switch to the +requested output or return the &EINVAL; when the index is out of +bounds. This is a write-only ioctl, it does not return the current +audio output attributes as VIDIOC_G_AUDOUT +does. + + Note connectors on a TV card to loop back the received audio +signal to a sound card are not audio outputs in this sense. + + + struct <structname>v4l2_audioout</structname> + + &cs-str; + + + __u32 + index + Identifies the audio output, set by the +driver or application. + + + __u8 + name[32] + Name of the audio output, a NUL-terminated ASCII +string, for example: "Line Out". This information is intended for the +user, preferably the connector label on the device itself. + + + __u32 + capability + Audio capability flags, none defined yet. Drivers +must set this field to zero. + + + __u32 + mode + Audio mode, none defined yet. Drivers and +applications (on VIDIOC_S_AUDOUT) must set this +field to zero. + + + __u32 + reserved[2] + Reserved for future extensions. Drivers and +applications must set the array to zero. + + + +
+ + + + &return-value; + + + + EINVAL + + No audio outputs combine with the current video +output, or the number of the selected audio output is out of bounds or +it does not combine, or there are no audio outputs at all and the +ioctl is not supported. + + + + EBUSY + + I/O is in progress, the output cannot be +switched. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-crop.xml b/Documentation/DocBook/v4l/vidioc-g-crop.xml new file mode 100644 index 000000000000..d235b1dedbed --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-crop.xml @@ -0,0 +1,143 @@ + + + ioctl VIDIOC_G_CROP, VIDIOC_S_CROP + &manvol; + + + + VIDIOC_G_CROP + VIDIOC_S_CROP + Get or set the current cropping rectangle + + + + + + int ioctl + int fd + int request + struct v4l2_crop *argp + + + + + int ioctl + int fd + int request + const struct v4l2_crop *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_CROP, VIDIOC_S_CROP + + + + argp + + + + + + + + + Description + + To query the cropping rectangle size and position +applications set the type field of a +v4l2_crop structure to the respective buffer +(stream) type and call the VIDIOC_G_CROP ioctl +with a pointer to this structure. The driver fills the rest of the +structure or returns the &EINVAL; if cropping is not supported. + + To change the cropping rectangle applications initialize the +type and &v4l2-rect; substructure named +c of a v4l2_crop structure and call the +VIDIOC_S_CROP ioctl with a pointer to this +structure. + + The driver first adjusts the requested dimensions against +hardware limits, &ie; the bounds given by the capture/output window, +and it rounds to the closest possible values of horizontal and +vertical offset, width and height. In particular the driver must round +the vertical offset of the cropping rectangle to frame lines modulo +two, such that the field order cannot be confused. + + Second the driver adjusts the image size (the opposite +rectangle of the scaling process, source or target depending on the +data direction) to the closest size possible while maintaining the +current horizontal and vertical scaling factor. + + Finally the driver programs the hardware with the actual +cropping and image parameters. VIDIOC_S_CROP is a +write-only ioctl, it does not return the actual parameters. To query +them applications must call VIDIOC_G_CROP and +&VIDIOC-G-FMT;. When the parameters are unsuitable the application may +modify the cropping or image parameters and repeat the cycle until +satisfactory parameters have been negotiated. + + When cropping is not supported then no parameters are +changed and VIDIOC_S_CROP returns the +&EINVAL;. + + + struct <structname>v4l2_crop</structname> + + &cs-str; + + + &v4l2-buf-type; + type + Type of the data stream, set by the application. +Only these types are valid here: V4L2_BUF_TYPE_VIDEO_CAPTURE, +V4L2_BUF_TYPE_VIDEO_OUTPUT, +V4L2_BUF_TYPE_VIDEO_OVERLAY, and custom (driver +defined) types with code V4L2_BUF_TYPE_PRIVATE +and higher. + + + &v4l2-rect; + c + Cropping rectangle. The same co-ordinate system as +for &v4l2-cropcap; bounds is used. + + + +
+ + + + &return-value; + + + + EINVAL + + Cropping is not supported. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-ctrl.xml b/Documentation/DocBook/v4l/vidioc-g-ctrl.xml new file mode 100644 index 000000000000..8b5e6ff7f3df --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-ctrl.xml @@ -0,0 +1,130 @@ + + + ioctl VIDIOC_G_CTRL, VIDIOC_S_CTRL + &manvol; + + + + VIDIOC_G_CTRL + VIDIOC_S_CTRL + Get or set the value of a control + + + + + + int ioctl + int fd + int request + struct v4l2_control +*argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_CTRL, VIDIOC_S_CTRL + + + + argp + + + + + + + + + Description + + To get the current value of a control applications +initialize the id field of a struct +v4l2_control and call the +VIDIOC_G_CTRL ioctl with a pointer to this +structure. To change the value of a control applications initialize +the id and value +fields of a struct v4l2_control and call the +VIDIOC_S_CTRL ioctl. + + When the id is invalid drivers +return an &EINVAL;. When the value is out +of bounds drivers can choose to take the closest valid value or return +an &ERANGE;, whatever seems more appropriate. However, +VIDIOC_S_CTRL is a write-only ioctl, it does not +return the actual new value. + + These ioctls work only with user controls. For other +control classes the &VIDIOC-G-EXT-CTRLS;, &VIDIOC-S-EXT-CTRLS; or +&VIDIOC-TRY-EXT-CTRLS; must be used. + + + struct <structname>v4l2_control</structname> + + &cs-str; + + + __u32 + id + Identifies the control, set by the +application. + + + __s32 + value + New value or current value. + + + +
+ + + + &return-value; + + + + EINVAL + + The &v4l2-control; id is +invalid. + + + + ERANGE + + The &v4l2-control; value +is out of bounds. + + + + EBUSY + + The control is temporarily not changeable, possibly +because another applications took over control of the device function +this control belongs to. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-enc-index.xml b/Documentation/DocBook/v4l/vidioc-g-enc-index.xml new file mode 100644 index 000000000000..9f242e4b2948 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-enc-index.xml @@ -0,0 +1,213 @@ + + + ioctl VIDIOC_G_ENC_INDEX + &manvol; + + + + VIDIOC_G_ENC_INDEX + Get meta data about a compressed video stream + + + + + + int ioctl + int fd + int request + struct v4l2_enc_idx *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_ENC_INDEX + + + + argp + + + + + + + + + Description + + + Experimental + + This is an experimental +interface and may change in the future. + + + The VIDIOC_G_ENC_INDEX ioctl provides +meta data about a compressed video stream the same or another +application currently reads from the driver, which is useful for +random access into the stream without decoding it. + + To read the data applications must call +VIDIOC_G_ENC_INDEX with a pointer to a +&v4l2-enc-idx;. On success the driver fills the +entry array, stores the number of elements +written in the entries field, and +initializes the entries_cap field. + + Each element of the entry array +contains meta data about one picture. A +VIDIOC_G_ENC_INDEX call reads up to +V4L2_ENC_IDX_ENTRIES entries from a driver +buffer, which can hold up to entries_cap +entries. This number can be lower or higher than +V4L2_ENC_IDX_ENTRIES, but not zero. When the +application fails to read the meta data in time the oldest entries +will be lost. When the buffer is empty or no capturing/encoding is in +progress, entries will be zero. + + Currently this ioctl is only defined for MPEG-2 program +streams and video elementary streams. + + + struct <structname>v4l2_enc_idx</structname> + + &cs-str; + + + __u32 + entries + The number of entries the driver stored in the +entry array. + + + __u32 + entries_cap + The number of entries the driver can +buffer. Must be greater than zero. + + + __u32 + reserved[4] + Reserved for future extensions. +Drivers must set the array to zero. + + + &v4l2-enc-idx-entry; + entry[V4L2_ENC_IDX_ENTRIES] + Meta data about a compressed video stream. Each +element of the array corresponds to one picture, sorted in ascending +order by their offset. + + + +
+ + + struct <structname>v4l2_enc_idx_entry</structname> + + &cs-str; + + + __u64 + offset + The offset in bytes from the beginning of the +compressed video stream to the beginning of this picture, that is a +PES packet header as defined in or a picture +header as defined in . When +the encoder is stopped, the driver resets the offset to zero. + + + __u64 + pts + The 33 bit Presentation Time +Stamp of this picture as defined in . + + + __u32 + length + The length of this picture in bytes. + + + __u32 + flags + Flags containing the coding type of this picture, see . + + + __u32 + reserved[2] + Reserved for future extensions. +Drivers must set the array to zero. + + + +
+ + + Index Entry Flags + + &cs-def; + + + V4L2_ENC_IDX_FRAME_I + 0x00 + This is an Intra-coded picture. + + + V4L2_ENC_IDX_FRAME_P + 0x01 + This is a Predictive-coded picture. + + + V4L2_ENC_IDX_FRAME_B + 0x02 + This is a Bidirectionally predictive-coded +picture. + + + V4L2_ENC_IDX_FRAME_MASK + 0x0F + AND the flags field with +this mask to obtain the picture coding type. + + + +
+ + + + &return-value; + + + + EINVAL + + The driver does not support this ioctl. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-ext-ctrls.xml b/Documentation/DocBook/v4l/vidioc-g-ext-ctrls.xml new file mode 100644 index 000000000000..3aa7f8f9ff0c --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-ext-ctrls.xml @@ -0,0 +1,307 @@ + + + ioctl VIDIOC_G_EXT_CTRLS, VIDIOC_S_EXT_CTRLS, +VIDIOC_TRY_EXT_CTRLS + &manvol; + + + + VIDIOC_G_EXT_CTRLS + VIDIOC_S_EXT_CTRLS + VIDIOC_TRY_EXT_CTRLS + Get or set the value of several controls, try control +values + + + + + + int ioctl + int fd + int request + struct v4l2_ext_controls +*argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_EXT_CTRLS, VIDIOC_S_EXT_CTRLS, +VIDIOC_TRY_EXT_CTRLS + + + + argp + + + + + + + + + Description + + These ioctls allow the caller to get or set multiple +controls atomically. Control IDs are grouped into control classes (see +) and all controls in the control array +must belong to the same control class. + + Applications must always fill in the +count, +ctrl_class, +controls and +reserved fields of &v4l2-ext-controls;, and +initialize the &v4l2-ext-control; array pointed to by the +controls fields. + + To get the current value of a set of controls applications +initialize the id, +size and reserved2 fields +of each &v4l2-ext-control; and call the +VIDIOC_G_EXT_CTRLS ioctl. String controls controls +must also set the string field. + + If the size is too small to +receive the control result (only relevant for pointer-type controls +like strings), then the driver will set size +to a valid value and return an &ENOSPC;. You should re-allocate the +string memory to this new size and try again. It is possible that the +same issue occurs again if the string has grown in the meantime. It is +recommended to call &VIDIOC-QUERYCTRL; first and use +maximum+1 as the new size +value. It is guaranteed that that is sufficient memory. + + + To change the value of a set of controls applications +initialize the id, size, +reserved2 and +value/string fields of each &v4l2-ext-control; and +call the VIDIOC_S_EXT_CTRLS ioctl. The controls +will only be set if all control values are +valid. + + To check if a set of controls have correct values applications +initialize the id, size, +reserved2 and +value/string fields of each &v4l2-ext-control; and +call the VIDIOC_TRY_EXT_CTRLS ioctl. It is up to +the driver whether wrong values are automatically adjusted to a valid +value or if an error is returned. + + When the id or +ctrl_class is invalid drivers return an +&EINVAL;. When the value is out of bounds drivers can choose to take +the closest valid value or return an &ERANGE;, whatever seems more +appropriate. In the first case the new value is set in +&v4l2-ext-control;. + + The driver will only set/get these controls if all control +values are correct. This prevents the situation where only some of the +controls were set/get. Only low-level errors (⪚ a failed i2c +command) can still cause this situation. + + + struct <structname>v4l2_ext_control</structname> + + &cs-ustr; + + + __u32 + id + + Identifies the control, set by the +application. + + + __u32 + size + + The total size in bytes of the payload of this +control. This is normally 0, but for pointer controls this should be +set to the size of the memory containing the payload, or that will +receive the payload. If VIDIOC_G_EXT_CTRLS finds +that this value is less than is required to store +the payload result, then it is set to a value large enough to store the +payload result and ENOSPC is returned. Note that for string controls +this size field should not be confused with the length of the string. +This field refers to the size of the memory that contains the string. +The actual length of the string may well be much smaller. + + + + __u32 + reserved2[1] + + Reserved for future extensions. Drivers and +applications must set the array to zero. + + + union + (anonymous) + + + + __s32 + value + New value or current value. + + + + __s64 + value64 + New value or current value. + + + + char * + string + A pointer to a string. + + + +
+ + + struct <structname>v4l2_ext_controls</structname> + + &cs-str; + + + __u32 + ctrl_class + The control class to which all controls belong, see +. + + + __u32 + count + The number of controls in the controls array. May +also be zero. + + + __u32 + error_idx + Set by the driver in case of an error. It is the +index of the control causing the error or equal to 'count' when the +error is not associated with a particular control. Undefined when the +ioctl returns 0 (success). + + + __u32 + reserved[2] + Reserved for future extensions. Drivers and +applications must set the array to zero. + + + &v4l2-ext-control; * + controls + Pointer to an array of +count v4l2_ext_control structures. Ignored +if count equals zero. + + + +
+ + + Control classes + + &cs-def; + + + V4L2_CTRL_CLASS_USER + 0x980000 + The class containing user controls. These controls +are described in . All controls that can be set +using the &VIDIOC-S-CTRL; and &VIDIOC-G-CTRL; ioctl belong to this +class. + + + V4L2_CTRL_CLASS_MPEG + 0x990000 + The class containing MPEG compression controls. +These controls are described in . + + + V4L2_CTRL_CLASS_CAMERA + 0x9a0000 + The class containing camera controls. +These controls are described in . + + + V4L2_CTRL_CLASS_FM_TX + 0x9b0000 + The class containing FM Transmitter (FM TX) controls. +These controls are described in . + + + +
+ + + + + &return-value; + + + + EINVAL + + The &v4l2-ext-control; id +is invalid or the &v4l2-ext-controls; +ctrl_class is invalid. This error code is +also returned by the VIDIOC_S_EXT_CTRLS and +VIDIOC_TRY_EXT_CTRLS ioctls if two or more +control values are in conflict. + + + + ERANGE + + The &v4l2-ext-control; value +is out of bounds. + + + + EBUSY + + The control is temporarily not changeable, possibly +because another applications took over control of the device function +this control belongs to. + + + + ENOSPC + + The space reserved for the control's payload is insufficient. +The field size is set to a value that is enough +to store the payload and this error code is returned. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-fbuf.xml b/Documentation/DocBook/v4l/vidioc-g-fbuf.xml new file mode 100644 index 000000000000..f7017062656e --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-fbuf.xml @@ -0,0 +1,456 @@ + + + ioctl VIDIOC_G_FBUF, VIDIOC_S_FBUF + &manvol; + + + + VIDIOC_G_FBUF + VIDIOC_S_FBUF + Get or set frame buffer overlay parameters + + + + + + int ioctl + int fd + int request + struct v4l2_framebuffer *argp + + + + + int ioctl + int fd + int request + const struct v4l2_framebuffer *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_FBUF, VIDIOC_S_FBUF + + + + argp + + + + + + + + + Description + + Applications can use the VIDIOC_G_FBUF and +VIDIOC_S_FBUF ioctl to get and set the +framebuffer parameters for a Video +Overlay or Video Output Overlay +(OSD). The type of overlay is implied by the device type (capture or +output device) and can be determined with the &VIDIOC-QUERYCAP; ioctl. +One /dev/videoN device must not support both +kinds of overlay. + + The V4L2 API distinguishes destructive and non-destructive +overlays. A destructive overlay copies captured video images into the +video memory of a graphics card. A non-destructive overlay blends +video images into a VGA signal or graphics into a video signal. +Video Output Overlays are always +non-destructive. + + To get the current parameters applications call the +VIDIOC_G_FBUF ioctl with a pointer to a +v4l2_framebuffer structure. The driver fills +all fields of the structure or returns an &EINVAL; when overlays are +not supported. + + To set the parameters for a Video Output +Overlay, applications must initialize the +flags field of a struct +v4l2_framebuffer. Since the framebuffer is +implemented on the TV card all other parameters are determined by the +driver. When an application calls VIDIOC_S_FBUF +with a pointer to this structure, the driver prepares for the overlay +and returns the framebuffer parameters as +VIDIOC_G_FBUF does, or it returns an error +code. + + To set the parameters for a non-destructive +Video Overlay, applications must initialize the +flags field, the +fmt substructure, and call +VIDIOC_S_FBUF. Again the driver prepares for the +overlay and returns the framebuffer parameters as +VIDIOC_G_FBUF does, or it returns an error +code. + + For a destructive Video Overlay +applications must additionally provide a +base address. Setting up a DMA to a +random memory location can jeopardize the system security, its +stability or even damage the hardware, therefore only the superuser +can set the parameters for a destructive video overlay. + + + + + struct <structname>v4l2_framebuffer</structname> + + &cs-ustr; + + + __u32 + capability + + Overlay capability flags set by the driver, see +. + + + __u32 + flags + + Overlay control flags set by application and +driver, see + + + void * + base + + Physical base address of the framebuffer, +that is the address of the pixel in the top left corner of the +framebuffer.A physical base address may not suit all +platforms. GK notes in theory we should pass something like PCI device ++ memory region + offset instead. If you encounter problems please +discuss on the linux-media mailing list: &v4l-ml;. + + + + + + This field is irrelevant to +non-destructive Video Overlays. For +destructive Video Overlays applications must +provide a base address. The driver may accept only base addresses +which are a multiple of two, four or eight bytes. For +Video Output Overlays the driver must return +a valid base address, so applications can find the corresponding Linux +framebuffer device (see ). + + + &v4l2-pix-format; + fmt + + Layout of the frame buffer. The +v4l2_pix_format structure is defined in , for clarification the fields and acceptable values + are listed below: + + + + __u32 + width + Width of the frame buffer in pixels. + + + + __u32 + height + Height of the frame buffer in pixels. + + + + __u32 + pixelformat + The pixel format of the +framebuffer. + + + + + + For non-destructive Video +Overlays this field only defines a format for the +&v4l2-window; chromakey field. + + + + + + For destructive Video +Overlays applications must initialize this field. For +Video Output Overlays the driver must return +a valid format. + + + + + + Usually this is an RGB format (for example +V4L2_PIX_FMT_RGB565) +but YUV formats (only packed YUV formats when chroma keying is used, +not including V4L2_PIX_FMT_YUYV and +V4L2_PIX_FMT_UYVY) and the +V4L2_PIX_FMT_PAL8 format are also permitted. The +behavior of the driver when an application requests a compressed +format is undefined. See for information on +pixel formats. + + + + &v4l2-field; + field + Drivers and applications shall ignore this field. +If applicable, the field order is selected with the &VIDIOC-S-FMT; +ioctl, using the field field of +&v4l2-window;. + + + + __u32 + bytesperline + Distance in bytes between the leftmost pixels in +two adjacent lines. + + + This field is irrelevant to +non-destructive Video +Overlays.For destructive Video +Overlays both applications and drivers can set this field +to request padding bytes at the end of each line. Drivers however may +ignore the requested value, returning width +times bytes-per-pixel or a larger value required by the hardware. That +implies applications can just set this field to zero to get a +reasonable default.For Video Output +Overlays the driver must return a valid +value.Video hardware may access padding bytes, therefore +they must reside in accessible memory. Consider for example the case +where padding bytes after the last line of an image cross a system +page boundary. Capture devices may write padding bytes, the value is +undefined. Output devices ignore the contents of padding +bytes.When the image format is planar the +bytesperline value applies to the largest +plane and is divided by the same factor as the +width field for any smaller planes. For +example the Cb and Cr planes of a YUV 4:2:0 image have half as many +padding bytes following each line as the Y plane. To avoid ambiguities +drivers must return a bytesperline value +rounded up to a multiple of the scale factor. + + + + __u32 + sizeimage + This field is irrelevant to +non-destructive Video Overlays. For +destructive Video Overlays applications must +initialize this field. For Video Output +Overlays the driver must return a valid +format.Together with base it +defines the framebuffer memory accessible by the +driver. + + + + &v4l2-colorspace; + colorspace + This information supplements the +pixelformat and must be set by the driver, +see . + + + + __u32 + priv + Reserved for additional information about custom +(driver defined) formats. When not used drivers and applications must +set this field to zero. + + + +
+ + + Frame Buffer Capability Flags + + &cs-def; + + + V4L2_FBUF_CAP_EXTERNOVERLAY + 0x0001 + The device is capable of non-destructive overlays. +When the driver clears this flag, only destructive overlays are +supported. There are no drivers yet which support both destructive and +non-destructive overlays. + + + V4L2_FBUF_CAP_CHROMAKEY + 0x0002 + The device supports clipping by chroma-keying the +images. That is, image pixels replace pixels in the VGA or video +signal only where the latter assume a certain color. Chroma-keying +makes no sense for destructive overlays. + + + V4L2_FBUF_CAP_LIST_CLIPPING + 0x0004 + The device supports clipping using a list of clip +rectangles. + + + V4L2_FBUF_CAP_BITMAP_CLIPPING + 0x0008 + The device supports clipping using a bit mask. + + + V4L2_FBUF_CAP_LOCAL_ALPHA + 0x0010 + The device supports clipping/blending using the +alpha channel of the framebuffer or VGA signal. Alpha blending makes +no sense for destructive overlays. + + + V4L2_FBUF_CAP_GLOBAL_ALPHA + 0x0020 + The device supports alpha blending using a global +alpha value. Alpha blending makes no sense for destructive overlays. + + + V4L2_FBUF_CAP_LOCAL_INV_ALPHA + 0x0040 + The device supports clipping/blending using the +inverted alpha channel of the framebuffer or VGA signal. Alpha +blending makes no sense for destructive overlays. + + + +
+ + + Frame Buffer Flags + + &cs-def; + + + V4L2_FBUF_FLAG_PRIMARY + 0x0001 + The framebuffer is the primary graphics surface. +In other words, the overlay is destructive. [?] + + + V4L2_FBUF_FLAG_OVERLAY + 0x0002 + The frame buffer is an overlay surface the same +size as the capture. [?] + + + The purpose of +V4L2_FBUF_FLAG_PRIMARY and +V4L2_FBUF_FLAG_OVERLAY was never quite clear. +Most drivers seem to ignore these flags. For compatibility with the +bttv driver applications should set the +V4L2_FBUF_FLAG_OVERLAY flag. + + + V4L2_FBUF_FLAG_CHROMAKEY + 0x0004 + Use chroma-keying. The chroma-key color is +determined by the chromakey field of +&v4l2-window; and negotiated with the &VIDIOC-S-FMT; ioctl, see +and + . + + + There are no flags to enable +clipping using a list of clip rectangles or a bitmap. These methods +are negotiated with the &VIDIOC-S-FMT; ioctl, see and . + + + V4L2_FBUF_FLAG_LOCAL_ALPHA + 0x0008 + Use the alpha channel of the framebuffer to clip or +blend framebuffer pixels with video images. The blend +function is: output = framebuffer pixel * alpha + video pixel * (1 - +alpha). The actual alpha depth depends on the framebuffer pixel +format. + + + V4L2_FBUF_FLAG_GLOBAL_ALPHA + 0x0010 + Use a global alpha value to blend the framebuffer +with video images. The blend function is: output = (framebuffer pixel +* alpha + video pixel * (255 - alpha)) / 255. The alpha value is +determined by the global_alpha field of +&v4l2-window; and negotiated with the &VIDIOC-S-FMT; ioctl, see +and . + + + V4L2_FBUF_FLAG_LOCAL_INV_ALPHA + 0x0020 + Like +V4L2_FBUF_FLAG_LOCAL_ALPHA, use the alpha channel +of the framebuffer to clip or blend framebuffer pixels with video +images, but with an inverted alpha value. The blend function is: +output = framebuffer pixel * (1 - alpha) + video pixel * alpha. The +actual alpha depth depends on the framebuffer pixel format. + + + +
+ + + + &return-value; + + + + EPERM + + VIDIOC_S_FBUF can only be called +by a privileged user to negotiate the parameters for a destructive +overlay. + + + + EBUSY + + The framebuffer parameters cannot be changed at this +time because overlay is already enabled, or capturing is enabled +and the hardware cannot capture and overlay simultaneously. + + + + EINVAL + + The ioctl is not supported or the +VIDIOC_S_FBUF parameters are unsuitable. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-fmt.xml b/Documentation/DocBook/v4l/vidioc-g-fmt.xml new file mode 100644 index 000000000000..7c7d1b72c40d --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-fmt.xml @@ -0,0 +1,201 @@ + + + ioctl VIDIOC_G_FMT, VIDIOC_S_FMT, +VIDIOC_TRY_FMT + &manvol; + + + + VIDIOC_G_FMT + VIDIOC_S_FMT + VIDIOC_TRY_FMT + Get or set the data format, try a format + + + + + + int ioctl + int fd + int request + struct v4l2_format +*argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_FMT, VIDIOC_S_FMT, VIDIOC_TRY_FMT + + + + argp + + + + + + + + + Description + + These ioctls are used to negotiate the format of data +(typically image format) exchanged between driver and +application. + + To query the current parameters applications set the +type field of a struct +v4l2_format to the respective buffer (stream) +type. For example video capture devices use +V4L2_BUF_TYPE_VIDEO_CAPTURE. When the application +calls the VIDIOC_G_FMT ioctl with a pointer to +this structure the driver fills the respective member of the +fmt union. In case of video capture devices +that is the &v4l2-pix-format; pix member. +When the requested buffer type is not supported drivers return an +&EINVAL;. + + To change the current format parameters applications +initialize the type field and all +fields of the respective fmt +union member. For details see the documentation of the various devices +types in . Good practice is to query the +current parameters first, and to +modify only those parameters not suitable for the application. When +the application calls the VIDIOC_S_FMT ioctl +with a pointer to a v4l2_format structure +the driver checks +and adjusts the parameters against hardware abilities. Drivers +should not return an error code unless the input is ambiguous, this is +a mechanism to fathom device capabilities and to approach parameters +acceptable for both the application and driver. On success the driver +may program the hardware, allocate resources and generally prepare for +data exchange. +Finally the VIDIOC_S_FMT ioctl returns the +current format parameters as VIDIOC_G_FMT does. +Very simple, inflexible devices may even ignore all input and always +return the default parameters. However all V4L2 devices exchanging +data with the application must implement the +VIDIOC_G_FMT and +VIDIOC_S_FMT ioctl. When the requested buffer +type is not supported drivers return an &EINVAL; on a +VIDIOC_S_FMT attempt. When I/O is already in +progress or the resource is not available for other reasons drivers +return the &EBUSY;. + + The VIDIOC_TRY_FMT ioctl is equivalent +to VIDIOC_S_FMT with one exception: it does not +change driver state. It can also be called at any time, never +returning EBUSY. This function is provided to +negotiate parameters, to learn about hardware limitations, without +disabling I/O or possibly time consuming hardware preparations. +Although strongly recommended drivers are not required to implement +this ioctl. + + + struct <structname>v4l2_format</structname> + + + + + + + + &v4l2-buf-type; + type + + Type of the data stream, see . + + + union + fmt + + + + &v4l2-pix-format; + pix + Definition of an image format, see , used by video capture and output +devices. + + + + &v4l2-window; + win + Definition of an overlaid image, see , used by video overlay devices. + + + + &v4l2-vbi-format; + vbi + Raw VBI capture or output parameters. This is +discussed in more detail in . Used by raw VBI +capture and output devices. + + + + &v4l2-sliced-vbi-format; + sliced + Sliced VBI capture or output parameters. See + for details. Used by sliced VBI +capture and output devices. + + + + __u8 + raw_data[200] + Place holder for future extensions and custom +(driver defined) formats with type +V4L2_BUF_TYPE_PRIVATE and higher. + + + +
+ + + + &return-value; + + + + EBUSY + + The data format cannot be changed at this +time, for example because I/O is already in progress. + + + + EINVAL + + The &v4l2-format; type +field is invalid, the requested buffer type not supported, or +VIDIOC_TRY_FMT was called and is not +supported with this buffer type. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-frequency.xml b/Documentation/DocBook/v4l/vidioc-g-frequency.xml new file mode 100644 index 000000000000..062d72069090 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-frequency.xml @@ -0,0 +1,145 @@ + + + ioctl VIDIOC_G_FREQUENCY, VIDIOC_S_FREQUENCY + &manvol; + + + + VIDIOC_G_FREQUENCY + VIDIOC_S_FREQUENCY + Get or set tuner or modulator radio +frequency + + + + + + int ioctl + int fd + int request + struct v4l2_frequency +*argp + + + + + int ioctl + int fd + int request + const struct v4l2_frequency +*argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_FREQUENCY, VIDIOC_S_FREQUENCY + + + + argp + + + + + + + + + Description + + To get the current tuner or modulator radio frequency +applications set the tuner field of a +&v4l2-frequency; to the respective tuner or modulator number (only +input devices have tuners, only output devices have modulators), zero +out the reserved array and +call the VIDIOC_G_FREQUENCY ioctl with a pointer +to this structure. The driver stores the current frequency in the +frequency field. + + To change the current tuner or modulator radio frequency +applications initialize the tuner, +type and +frequency fields, and the +reserved array of a &v4l2-frequency; and +call the VIDIOC_S_FREQUENCY ioctl with a pointer +to this structure. When the requested frequency is not possible the +driver assumes the closest possible value. However +VIDIOC_S_FREQUENCY is a write-only ioctl, it does +not return the actual new frequency. + + + struct <structname>v4l2_frequency</structname> + + &cs-str; + + + __u32 + tuner + The tuner or modulator index number. This is the +same value as in the &v4l2-input; tuner +field and the &v4l2-tuner; index field, or +the &v4l2-output; modulator field and the +&v4l2-modulator; index field. + + + &v4l2-tuner-type; + type + The tuner type. This is the same value as in the +&v4l2-tuner; type field. The field is not +applicable to modulators, &ie; ignored by drivers. + + + __u32 + frequency + Tuning frequency in units of 62.5 kHz, or if the +&v4l2-tuner; or &v4l2-modulator; capabilities flag +V4L2_TUNER_CAP_LOW is set, in units of 62.5 +Hz. + + + __u32 + reserved[8] + Reserved for future extensions. Drivers and + applications must set the array to zero. + + + +
+ + + + &return-value; + + + + EINVAL + + The tuner index is out of +bounds or the value in the type field is +wrong. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-input.xml b/Documentation/DocBook/v4l/vidioc-g-input.xml new file mode 100644 index 000000000000..ed076e92760d --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-input.xml @@ -0,0 +1,100 @@ + + + ioctl VIDIOC_G_INPUT, VIDIOC_S_INPUT + &manvol; + + + + VIDIOC_G_INPUT + VIDIOC_S_INPUT + Query or select the current video input + + + + + + int ioctl + int fd + int request + int *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_INPUT, VIDIOC_S_INPUT + + + + argp + + + + + + + + + Description + + To query the current video input applications call the +VIDIOC_G_INPUT ioctl with a pointer to an integer +where the driver stores the number of the input, as in the +&v4l2-input; index field. This ioctl will +fail only when there are no video inputs, returning +EINVAL. + + To select a video input applications store the number of the +desired input in an integer and call the +VIDIOC_S_INPUT ioctl with a pointer to this +integer. Side effects are possible. For example inputs may support +different video standards, so the driver may implicitly switch the +current standard. It is good practice to select an input before +querying or negotiating any other parameters. + + Information about video inputs is available using the +&VIDIOC-ENUMINPUT; ioctl. + + + + &return-value; + + + + EINVAL + + The number of the video input is out of bounds, or +there are no video inputs at all and this ioctl is not +supported. + + + + EBUSY + + I/O is in progress, the input cannot be +switched. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-jpegcomp.xml b/Documentation/DocBook/v4l/vidioc-g-jpegcomp.xml new file mode 100644 index 000000000000..77394b287411 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-jpegcomp.xml @@ -0,0 +1,180 @@ + + + ioctl VIDIOC_G_JPEGCOMP, VIDIOC_S_JPEGCOMP + &manvol; + + + + VIDIOC_G_JPEGCOMP + VIDIOC_S_JPEGCOMP + + + + + + + int ioctl + int fd + int request + v4l2_jpegcompression *argp + + + + + int ioctl + int fd + int request + const v4l2_jpegcompression *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_JPEGCOMP, VIDIOC_S_JPEGCOMP + + + + argp + + + + + + + + + Description + + [to do] + + Ronald Bultje elaborates: + + + + APP is some application-specific information. The +application can set it itself, and it'll be stored in the JPEG-encoded +fields (eg; interlacing information for in an AVI or so). COM is the +same, but it's comments, like 'encoded by me' or so. + + jpeg_markers describes whether the huffman tables, +quantization tables and the restart interval information (all +JPEG-specific stuff) should be stored in the JPEG-encoded fields. +These define how the JPEG field is encoded. If you omit them, +applications assume you've used standard encoding. You usually do want +to add them. + + + + + struct <structname>v4l2_jpegcompression</structname> + + &cs-str; + + + int + quality + + + + int + APPn + + + + int + APP_len + + + + char + APP_data[60] + + + + int + COM_len + + + + char + COM_data[60] + + + + __u32 + jpeg_markers + See . + + + +
+ + + JPEG Markers Flags + + &cs-def; + + + V4L2_JPEG_MARKER_DHT + (1<<3) + Define Huffman Tables + + + V4L2_JPEG_MARKER_DQT + (1<<4) + Define Quantization Tables + + + V4L2_JPEG_MARKER_DRI + (1<<5) + Define Restart Interval + + + V4L2_JPEG_MARKER_COM + (1<<6) + Comment segment + + + V4L2_JPEG_MARKER_APP + (1<<7) + App segment, driver will always use APP0 + + + +
+ + + + &return-value; + + + + EINVAL + + This ioctl is not supported. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-modulator.xml b/Documentation/DocBook/v4l/vidioc-g-modulator.xml new file mode 100644 index 000000000000..15ce660f0f5a --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-modulator.xml @@ -0,0 +1,246 @@ + + + ioctl VIDIOC_G_MODULATOR, VIDIOC_S_MODULATOR + &manvol; + + + + VIDIOC_G_MODULATOR + VIDIOC_S_MODULATOR + Get or set modulator attributes + + + + + + int ioctl + int fd + int request + struct v4l2_modulator +*argp + + + + + int ioctl + int fd + int request + const struct v4l2_modulator +*argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_MODULATOR, VIDIOC_S_MODULATOR + + + + argp + + + + + + + + + Description + + To query the attributes of a modulator applications initialize +the index field and zero out the +reserved array of a &v4l2-modulator; and +call the VIDIOC_G_MODULATOR ioctl with a pointer +to this structure. Drivers fill the rest of the structure or return an +&EINVAL; when the index is out of bounds. To enumerate all modulators +applications shall begin at index zero, incrementing by one until the +driver returns EINVAL. + + Modulators have two writable properties, an audio +modulation set and the radio frequency. To change the modulated audio +subprograms, applications initialize the index + and txsubchans fields and the +reserved array and call the +VIDIOC_S_MODULATOR ioctl. Drivers may choose a +different audio modulation if the request cannot be satisfied. However +this is a write-only ioctl, it does not return the actual audio +modulation selected. + + To change the radio frequency the &VIDIOC-S-FREQUENCY; ioctl +is available. + + + struct <structname>v4l2_modulator</structname> + + &cs-str; + + + __u32 + index + Identifies the modulator, set by the +application. + + + __u8 + name[32] + Name of the modulator, a NUL-terminated ASCII +string. This information is intended for the user. + + + __u32 + capability + Modulator capability flags. No flags are defined +for this field, the tuner flags in &v4l2-tuner; +are used accordingly. The audio flags indicate the ability +to encode audio subprograms. They will not +change for example with the current video standard. + + + __u32 + rangelow + The lowest tunable frequency in units of 62.5 +KHz, or if the capability flag +V4L2_TUNER_CAP_LOW is set, in units of 62.5 +Hz. + + + __u32 + rangehigh + The highest tunable frequency in units of 62.5 +KHz, or if the capability flag +V4L2_TUNER_CAP_LOW is set, in units of 62.5 +Hz. + + + __u32 + txsubchans + With this field applications can determine how +audio sub-carriers shall be modulated. It contains a set of flags as +defined in . Note the tuner +rxsubchans flags are reused, but the +semantics are different. Video output devices are assumed to have an +analog or PCM audio input with 1-3 channels. The +txsubchans flags select one or more +channels for modulation, together with some audio subprogram +indicator, for example a stereo pilot tone. + + + __u32 + reserved[4] + Reserved for future extensions. Drivers and +applications must set the array to zero. + + + +
+ + + Modulator Audio Transmission Flags + + &cs-def; + + + V4L2_TUNER_SUB_MONO + 0x0001 + Modulate channel 1 as mono audio, when the input +has more channels, a down-mix of channel 1 and 2. This flag does not +combine with V4L2_TUNER_SUB_STEREO or +V4L2_TUNER_SUB_LANG1. + + + V4L2_TUNER_SUB_STEREO + 0x0002 + Modulate channel 1 and 2 as left and right +channel of a stereo audio signal. When the input has only one channel +or two channels and V4L2_TUNER_SUB_SAP is also +set, channel 1 is encoded as left and right channel. This flag does +not combine with V4L2_TUNER_SUB_MONO or +V4L2_TUNER_SUB_LANG1. When the driver does not +support stereo audio it shall fall back to mono. + + + V4L2_TUNER_SUB_LANG1 + 0x0008 + Modulate channel 1 and 2 as primary and secondary +language of a bilingual audio signal. When the input has only one +channel it is used for both languages. It is not possible to encode +the primary or secondary language only. This flag does not combine +with V4L2_TUNER_SUB_MONO, +V4L2_TUNER_SUB_STEREO or +V4L2_TUNER_SUB_SAP. If the hardware does not +support the respective audio matrix, or the current video standard +does not permit bilingual audio the +VIDIOC_S_MODULATOR ioctl shall return an &EINVAL; +and the driver shall fall back to mono or stereo mode. + + + V4L2_TUNER_SUB_LANG2 + 0x0004 + Same effect as +V4L2_TUNER_SUB_SAP. + + + V4L2_TUNER_SUB_SAP + 0x0004 + When combined with V4L2_TUNER_SUB_MONO + the first channel is encoded as mono audio, the last +channel as Second Audio Program. When the input has only one channel +it is used for both audio tracks. When the input has three channels +the mono track is a down-mix of channel 1 and 2. When combined with +V4L2_TUNER_SUB_STEREO channel 1 and 2 are +encoded as left and right stereo audio, channel 3 as Second Audio +Program. When the input has only two channels, the first is encoded as +left and right channel and the second as SAP. When the input has only +one channel it is used for all audio tracks. It is not possible to +encode a Second Audio Program only. This flag must combine with +V4L2_TUNER_SUB_MONO or +V4L2_TUNER_SUB_STEREO. If the hardware does not +support the respective audio matrix, or the current video standard +does not permit SAP the VIDIOC_S_MODULATOR ioctl +shall return an &EINVAL; and driver shall fall back to mono or stereo +mode. + + + V4L2_TUNER_SUB_RDS + 0x0010 + Enable the RDS encoder for a radio FM transmitter. + + + +
+ + + + &return-value; + + + + EINVAL + + The &v4l2-modulator; +index is out of bounds. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-output.xml b/Documentation/DocBook/v4l/vidioc-g-output.xml new file mode 100644 index 000000000000..3ea8c0ed812e --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-output.xml @@ -0,0 +1,100 @@ + + + ioctl VIDIOC_G_OUTPUT, VIDIOC_S_OUTPUT + &manvol; + + + + VIDIOC_G_OUTPUT + VIDIOC_S_OUTPUT + Query or select the current video output + + + + + + int ioctl + int fd + int request + int *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_OUTPUT, VIDIOC_S_OUTPUT + + + + argp + + + + + + + + + Description + + To query the current video output applications call the +VIDIOC_G_OUTPUT ioctl with a pointer to an integer +where the driver stores the number of the output, as in the +&v4l2-output; index field. This ioctl +will fail only when there are no video outputs, returning the +&EINVAL;. + + To select a video output applications store the number of the +desired output in an integer and call the +VIDIOC_S_OUTPUT ioctl with a pointer to this integer. +Side effects are possible. For example outputs may support different +video standards, so the driver may implicitly switch the current +standard. It is good practice to select an output before querying or +negotiating any other parameters. + + Information about video outputs is available using the +&VIDIOC-ENUMOUTPUT; ioctl. + + + + &return-value; + + + + EINVAL + + The number of the video output is out of bounds, or +there are no video outputs at all and this ioctl is not +supported. + + + + EBUSY + + I/O is in progress, the output cannot be +switched. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-parm.xml b/Documentation/DocBook/v4l/vidioc-g-parm.xml new file mode 100644 index 000000000000..78332d365ce9 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-parm.xml @@ -0,0 +1,332 @@ + + + ioctl VIDIOC_G_PARM, VIDIOC_S_PARM + &manvol; + + + + VIDIOC_G_PARM + VIDIOC_S_PARM + Get or set streaming parameters + + + + + + int ioctl + int fd + int request + v4l2_streamparm *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_PARM, VIDIOC_S_PARM + + + + argp + + + + + + + + + Description + + The current video standard determines a nominal number of +frames per second. If less than this number of frames is to be +captured or output, applications can request frame skipping or +duplicating on the driver side. This is especially useful when using +the read() or write(), which +are not augmented by timestamps or sequence counters, and to avoid +unneccessary data copying. + + Further these ioctls can be used to determine the number of +buffers used internally by a driver in read/write mode. For +implications see the section discussing the &func-read; +function. + + To get and set the streaming parameters applications call +the VIDIOC_G_PARM and +VIDIOC_S_PARM ioctl, respectively. They take a +pointer to a struct v4l2_streamparm which +contains a union holding separate parameters for input and output +devices. + + + struct <structname>v4l2_streamparm</structname> + + &cs-ustr; + + + &v4l2-buf-type; + type + + The buffer (stream) type, same as &v4l2-format; +type, set by the application. + + + union + parm + + + + + + &v4l2-captureparm; + capture + Parameters for capture devices, used when +type is +V4L2_BUF_TYPE_VIDEO_CAPTURE. + + + + &v4l2-outputparm; + output + Parameters for output devices, used when +type is +V4L2_BUF_TYPE_VIDEO_OUTPUT. + + + + __u8 + raw_data[200] + A place holder for future extensions and custom +(driver defined) buffer types V4L2_BUF_TYPE_PRIVATE and +higher. + + + +
+ + + struct <structname>v4l2_captureparm</structname> + + &cs-str; + + + __u32 + capability + See . + + + __u32 + capturemode + Set by drivers and applications, see . + + + &v4l2-fract; + timeperframe + This is is the desired period between +successive frames captured by the driver, in seconds. The +field is intended to skip frames on the driver side, saving I/O +bandwidth.Applications store here the desired frame +period, drivers return the actual frame period, which must be greater +or equal to the nominal frame period determined by the current video +standard (&v4l2-standard; frameperiod +field). Changing the video standard (also implicitly by switching the +video input) may reset this parameter to the nominal frame period. To +reset manually applications can just set this field to +zero.Drivers support this function only when they set the +V4L2_CAP_TIMEPERFRAME flag in the +capability field. + + + __u32 + extendedmode + Custom (driver specific) streaming parameters. When +unused, applications and drivers must set this field to zero. +Applications using this field should check the driver name and +version, see . + + + __u32 + readbuffers + Applications set this field to the desired number +of buffers used internally by the driver in &func-read; mode. Drivers +return the actual number of buffers. When an application requests zero +buffers, drivers should just return the current setting rather than +the minimum or an error code. For details see . + + + __u32 + reserved[4] + Reserved for future extensions. Drivers and +applications must set the array to zero. + + + +
+ + + struct <structname>v4l2_outputparm</structname> + + &cs-str; + + + __u32 + capability + See . + + + __u32 + outputmode + Set by drivers and applications, see . + + + &v4l2-fract; + timeperframe + This is is the desired period between +successive frames output by the driver, in seconds. + + + The field is intended to +repeat frames on the driver side in &func-write; mode (in streaming +mode timestamps can be used to throttle the output), saving I/O +bandwidth.Applications store here the desired frame +period, drivers return the actual frame period, which must be greater +or equal to the nominal frame period determined by the current video +standard (&v4l2-standard; frameperiod +field). Changing the video standard (also implicitly by switching the +video output) may reset this parameter to the nominal frame period. To +reset manually applications can just set this field to +zero.Drivers support this function only when they set the +V4L2_CAP_TIMEPERFRAME flag in the +capability field. + + + __u32 + extendedmode + Custom (driver specific) streaming parameters. When +unused, applications and drivers must set this field to zero. +Applications using this field should check the driver name and +version, see . + + + __u32 + writebuffers + Applications set this field to the desired number +of buffers used internally by the driver in +write() mode. Drivers return the actual number of +buffers. When an application requests zero buffers, drivers should +just return the current setting rather than the minimum or an error +code. For details see . + + + __u32 + reserved[4] + Reserved for future extensions. Drivers and +applications must set the array to zero. + + + +
+ + + Streaming Parameters Capabilites + + &cs-def; + + + V4L2_CAP_TIMEPERFRAME + 0x1000 + The frame skipping/repeating controlled by the +timeperframe field is supported. + + + +
+ + + Capture Parameters Flags + + &cs-def; + + + V4L2_MODE_HIGHQUALITY + 0x0001 + High quality imaging mode. High quality mode +is intended for still imaging applications. The idea is to get the +best possible image quality that the hardware can deliver. It is not +defined how the driver writer may achieve that; it will depend on the +hardware and the ingenuity of the driver writer. High quality mode is +a different mode from the the regular motion video capture modes. In +high quality mode: + + The driver may be able to capture higher +resolutions than for motion capture. + + + The driver may support fewer pixel formats +than motion capture (eg; true color). + + + The driver may capture and arithmetically +combine multiple successive fields or frames to remove color edge +artifacts and reduce the noise in the video data. + + + + The driver may capture images in slices like +a scanner in order to handle larger format images than would otherwise +be possible. + + + An image capture operation may be +significantly slower than motion capture. + + + Moving objects in the image might have +excessive motion blur. + + + Capture might only work through the +read() call. + + + + + +
+ + + + + &return-value; + + + + EINVAL + + This ioctl is not supported. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-priority.xml b/Documentation/DocBook/v4l/vidioc-g-priority.xml new file mode 100644 index 000000000000..5fb001978645 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-priority.xml @@ -0,0 +1,144 @@ + + + ioctl VIDIOC_G_PRIORITY, VIDIOC_S_PRIORITY + &manvol; + + + + VIDIOC_G_PRIORITY + VIDIOC_S_PRIORITY + Query or request the access priority associated with a +file descriptor + + + + + + int ioctl + int fd + int request + enum v4l2_priority *argp + + + + + int ioctl + int fd + int request + const enum v4l2_priority *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_PRIORITY, VIDIOC_S_PRIORITY + + + + argp + + Pointer to an enum v4l2_priority type. + + + + + + + Description + + To query the current access priority +applications call the VIDIOC_G_PRIORITY ioctl +with a pointer to an enum v4l2_priority variable where the driver stores +the current priority. + + To request an access priority applications store the +desired priority in an enum v4l2_priority variable and call +VIDIOC_S_PRIORITY ioctl with a pointer to this +variable. + + + enum v4l2_priority + + &cs-def; + + + V4L2_PRIORITY_UNSET + 0 + + + + V4L2_PRIORITY_BACKGROUND + 1 + Lowest priority, usually applications running in +background, for example monitoring VBI transmissions. A proxy +application running in user space will be necessary if multiple +applications want to read from a device at this priority. + + + V4L2_PRIORITY_INTERACTIVE + 2 + + + + V4L2_PRIORITY_DEFAULT + 2 + Medium priority, usually applications started and +interactively controlled by the user. For example TV viewers, Teletext +browsers, or just "panel" applications to change the channel or video +controls. This is the default priority unless an application requests +another. + + + V4L2_PRIORITY_RECORD + 3 + Highest priority. Only one file descriptor can have +this priority, it blocks any other fd from changing device properties. +Usually applications which must not be interrupted, like video +recording. + + + +
+ + + + &return-value; + + + + EINVAL + + The requested priority value is invalid, or the +driver does not support access priorities. + + + + EBUSY + + Another application already requested higher +priority. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-sliced-vbi-cap.xml b/Documentation/DocBook/v4l/vidioc-g-sliced-vbi-cap.xml new file mode 100644 index 000000000000..10e721b17374 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-sliced-vbi-cap.xml @@ -0,0 +1,264 @@ + + + ioctl VIDIOC_G_SLICED_VBI_CAP + &manvol; + + + + VIDIOC_G_SLICED_VBI_CAP + Query sliced VBI capabilities + + + + + + int ioctl + int fd + int request + struct v4l2_sliced_vbi_cap *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_SLICED_VBI_CAP + + + + argp + + + + + + + + + Description + + To find out which data services are supported by a sliced +VBI capture or output device, applications initialize the +type field of a &v4l2-sliced-vbi-cap;, +clear the reserved array and +call the VIDIOC_G_SLICED_VBI_CAP ioctl. The +driver fills in the remaining fields or returns an &EINVAL; if the +sliced VBI API is unsupported or type +is invalid. + + Note the type field was added, +and the ioctl changed from read-only to write-read, in Linux 2.6.19. + + + struct <structname>v4l2_sliced_vbi_cap</structname> + + + + + + + + + + __u16 + service_set + A set of all data services +supported by the driver. Equal to the union of all elements of the +service_lines array. + + + __u16 + service_lines[2][24] + Each element of this array +contains a set of data services the hardware can look for or insert +into a particular scan line. Data services are defined in . Array indices map to ITU-R +line numbers (see also and ) as follows: + + + + + Element + 525 line systems + 625 line systems + + + + + service_lines[0][1] + 1 + 1 + + + + + service_lines[0][23] + 23 + 23 + + + + + service_lines[1][1] + 264 + 314 + + + + + service_lines[1][23] + 286 + 336 + + + + + + + + The number of VBI lines the +hardware can capture or output per frame, or the number of services it +can identify on a given line may be limited. For example on PAL line +16 the hardware may be able to look for a VPS or Teletext signal, but +not both at the same time. Applications can learn about these limits +using the &VIDIOC-S-FMT; ioctl as described in . + + + + + + + + Drivers must set +service_lines[0][0] and +service_lines[1][0] to zero. + + + &v4l2-buf-type; + type + Type of the data stream, see . Should be +V4L2_BUF_TYPE_SLICED_VBI_CAPTURE or +V4L2_BUF_TYPE_SLICED_VBI_OUTPUT. + + + __u32 + reserved[3] + This array is reserved for future +extensions. Applications and drivers must set it to zero. + + + +
+ + + + Sliced VBI services + + + + + + + + + + Symbol + Value + Reference + Lines, usually + Payload + + + + + V4L2_SLICED_TELETEXT_B (Teletext +System B) + 0x0001 + , + PAL/SECAM line 7-22, 320-335 (second field 7-22) + Last 42 of the 45 byte Teletext packet, that is +without clock run-in and framing code, lsb first transmitted. + + + V4L2_SLICED_VPS + 0x0400 + + PAL line 16 + Byte number 3 to 15 according to Figure 9 of +ETS 300 231, lsb first transmitted. + + + V4L2_SLICED_CAPTION_525 + 0x1000 + + NTSC line 21, 284 (second field 21) + Two bytes in transmission order, including parity +bit, lsb first transmitted. + + + V4L2_SLICED_WSS_625 + 0x4000 + , + PAL/SECAM line 23 + +Byte 0 1 + msb lsb msb lsb +Bit 7 6 5 4 3 2 1 0 x x 13 12 11 10 9 + + + + V4L2_SLICED_VBI_525 + 0x1000 + Set of services applicable to 525 +line systems. + + + V4L2_SLICED_VBI_625 + 0x4401 + Set of services applicable to 625 +line systems. + + + +
+ + + + + &return-value; + + + + EINVAL + + The device does not support sliced VBI capturing or +output, or the value in the type field is +wrong. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-std.xml b/Documentation/DocBook/v4l/vidioc-g-std.xml new file mode 100644 index 000000000000..b6f5d267e856 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-std.xml @@ -0,0 +1,99 @@ + + + ioctl VIDIOC_G_STD, VIDIOC_S_STD + &manvol; + + + + VIDIOC_G_STD + VIDIOC_S_STD + Query or select the video standard of the current input + + + + + + int ioctl + int fd + int request + v4l2_std_id +*argp + + + + + int ioctl + int fd + int request + const v4l2_std_id +*argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_STD, VIDIOC_S_STD + + + + argp + + + + + + + + + Description + + To query and select the current video standard applications +use the VIDIOC_G_STD and VIDIOC_S_STD ioctls which take a pointer to a +&v4l2-std-id; type as argument. VIDIOC_G_STD can +return a single flag or a set of flags as in &v4l2-standard; field +id. The flags must be unambiguous such +that they appear in only one enumerated v4l2_standard structure. + + VIDIOC_S_STD accepts one or more +flags, being a write-only ioctl it does not return the actual new standard as +VIDIOC_G_STD does. When no flags are given or +the current input does not support the requested standard the driver +returns an &EINVAL;. When the standard set is ambiguous drivers may +return EINVAL or choose any of the requested +standards. + + + + &return-value; + + + + EINVAL + + This ioctl is not supported, or the +VIDIOC_S_STD parameter was unsuitable. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-g-tuner.xml b/Documentation/DocBook/v4l/vidioc-g-tuner.xml new file mode 100644 index 000000000000..bd98c734c06b --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-g-tuner.xml @@ -0,0 +1,535 @@ + + + ioctl VIDIOC_G_TUNER, VIDIOC_S_TUNER + &manvol; + + + + VIDIOC_G_TUNER + VIDIOC_S_TUNER + Get or set tuner attributes + + + + + + int ioctl + int fd + int request + struct v4l2_tuner +*argp + + + + + int ioctl + int fd + int request + const struct v4l2_tuner +*argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_TUNER, VIDIOC_S_TUNER + + + + argp + + + + + + + + + Description + + To query the attributes of a tuner applications initialize the +index field and zero out the +reserved array of a &v4l2-tuner; and call the +VIDIOC_G_TUNER ioctl with a pointer to this +structure. Drivers fill the rest of the structure or return an +&EINVAL; when the index is out of bounds. To enumerate all tuners +applications shall begin at index zero, incrementing by one until the +driver returns EINVAL. + + Tuners have two writable properties, the audio mode and +the radio frequency. To change the audio mode, applications initialize +the index, +audmode and +reserved fields and call the +VIDIOC_S_TUNER ioctl. This will +not change the current tuner, which is determined +by the current video input. Drivers may choose a different audio mode +if the requested mode is invalid or unsupported. Since this is a +write-only ioctl, it does not return the actually +selected audio mode. + + To change the radio frequency the &VIDIOC-S-FREQUENCY; ioctl +is available. + + + struct <structname>v4l2_tuner</structname> + + + + + + + + + __u32 + index + Identifies the tuner, set by the +application. + + + __u8 + name[32] + Name of the tuner, a +NUL-terminated ASCII string. This information is intended for the +user. + + + &v4l2-tuner-type; + type + Type of the tuner, see . + + + __u32 + capability + Tuner capability flags, see +. Audio flags indicate the ability +to decode audio subprograms. They will not +change, for example with the current video standard.When +the structure refers to a radio tuner only the +V4L2_TUNER_CAP_LOW, +V4L2_TUNER_CAP_STEREO and +V4L2_TUNER_CAP_RDS flags can be set. + + + __u32 + rangelow + The lowest tunable frequency in +units of 62.5 kHz, or if the capability +flag V4L2_TUNER_CAP_LOW is set, in units of 62.5 +Hz. + + + __u32 + rangehigh + The highest tunable frequency in +units of 62.5 kHz, or if the capability +flag V4L2_TUNER_CAP_LOW is set, in units of 62.5 +Hz. + + + __u32 + rxsubchans + Some tuners or audio +decoders can determine the received audio subprograms by analyzing +audio carriers, pilot tones or other indicators. To pass this +information drivers set flags defined in in this field. For +example: + + + + + V4L2_TUNER_SUB_MONO + receiving mono audio + + + + + STEREO | SAP + receiving stereo audio and a secondary audio +program + + + + + MONO | STEREO + receiving mono or stereo audio, the hardware cannot +distinguish + + + + + LANG1 | LANG2 + receiving bilingual audio + + + + + MONO | STEREO | LANG1 | LANG2 + receiving mono, stereo or bilingual +audio + + + + + When the +V4L2_TUNER_CAP_STEREO, +_LANG1, _LANG2 or +_SAP flag is cleared in the +capability field, the corresponding +V4L2_TUNER_SUB_ flag must not be set +here.This field is valid only if this is the tuner of the +current video input, or when the structure refers to a radio +tuner. + + + __u32 + audmode + The selected audio mode, see + for valid values. The audio mode does +not affect audio subprogram detection, and like a control it does not automatically change +unless the requested mode is invalid or unsupported. See for possible results when +the selected and received audio programs do not +match.Currently this is the only field of struct +v4l2_tuner applications can +change. + + + __u32 + signal + The signal strength if known, ranging +from 0 to 65535. Higher values indicate a better signal. + + + __s32 + afc + Automatic frequency control: When the +afc value is negative, the frequency is too +low, when positive too high. + + + __u32 + reserved[4] + Reserved for future extensions. Drivers and +applications must set the array to zero. + + + +
+ + + enum v4l2_tuner_type + + &cs-def; + + + V4L2_TUNER_RADIO + 1 + + + + V4L2_TUNER_ANALOG_TV + 2 + + + + +
+ + + Tuner and Modulator Capability Flags + + &cs-def; + + + V4L2_TUNER_CAP_LOW + 0x0001 + When set, tuning frequencies are expressed in units of +62.5 Hz, otherwise in units of 62.5 kHz. + + + V4L2_TUNER_CAP_NORM + 0x0002 + This is a multi-standard tuner; the video standard +can or must be switched. (B/G PAL tuners for example are typically not + considered multi-standard because the video standard is automatically + determined from the frequency band.) The set of supported video + standards is available from the &v4l2-input; pointing to this tuner, + see the description of ioctl &VIDIOC-ENUMINPUT; for details. Only + V4L2_TUNER_ANALOG_TV tuners can have this capability. + + + V4L2_TUNER_CAP_STEREO + 0x0010 + Stereo audio reception is supported. + + + V4L2_TUNER_CAP_LANG1 + 0x0040 + Reception of the primary language of a bilingual +audio program is supported. Bilingual audio is a feature of +two-channel systems, transmitting the primary language monaural on the +main audio carrier and a secondary language monaural on a second +carrier. Only + V4L2_TUNER_ANALOG_TV tuners can have this capability. + + + V4L2_TUNER_CAP_LANG2 + 0x0020 + Reception of the secondary language of a bilingual +audio program is supported. Only + V4L2_TUNER_ANALOG_TV tuners can have this capability. + + + V4L2_TUNER_CAP_SAP + 0x0020 + Reception of a secondary audio program is +supported. This is a feature of the BTSC system which accompanies the +NTSC video standard. Two audio carriers are available for mono or +stereo transmissions of a primary language, and an independent third +carrier for a monaural secondary language. Only + V4L2_TUNER_ANALOG_TV tuners can have this capability.Note the +V4L2_TUNER_CAP_LANG2 and +V4L2_TUNER_CAP_SAP flags are synonyms. +V4L2_TUNER_CAP_SAP applies when the tuner +supports the V4L2_STD_NTSC_M video +standard. + + + V4L2_TUNER_CAP_RDS + 0x0080 + RDS capture is supported. This capability is only valid for +radio tuners. + + + +
+ + + Tuner Audio Reception Flags + + &cs-def; + + + V4L2_TUNER_SUB_MONO + 0x0001 + The tuner receives a mono audio signal. + + + V4L2_TUNER_SUB_STEREO + 0x0002 + The tuner receives a stereo audio signal. + + + V4L2_TUNER_SUB_LANG1 + 0x0008 + The tuner receives the primary language of a +bilingual audio signal. Drivers must clear this flag when the current +video standard is V4L2_STD_NTSC_M. + + + V4L2_TUNER_SUB_LANG2 + 0x0004 + The tuner receives the secondary language of a +bilingual audio signal (or a second audio program). + + + V4L2_TUNER_SUB_SAP + 0x0004 + The tuner receives a Second Audio Program. Note the +V4L2_TUNER_SUB_LANG2 and +V4L2_TUNER_SUB_SAP flags are synonyms. The +V4L2_TUNER_SUB_SAP flag applies when the +current video standard is V4L2_STD_NTSC_M. + + + V4L2_TUNER_SUB_RDS + 0x0010 + The tuner receives an RDS channel. + + + +
+ + + Tuner Audio Modes + + &cs-def; + + + V4L2_TUNER_MODE_MONO + 0 + Play mono audio. When the tuner receives a stereo +signal this a down-mix of the left and right channel. When the tuner +receives a bilingual or SAP signal this mode selects the primary +language. + + + V4L2_TUNER_MODE_STEREO + 1 + Play stereo audio. When the tuner receives +bilingual audio it may play different languages on the left and right +channel or the primary language is played on both channels.Playing +different languages in this mode is +deprecated. New drivers should do this only in +MODE_LANG1_LANG2.When the tuner +receives no stereo signal or does not support stereo reception the +driver shall fall back to MODE_MONO. + + + V4L2_TUNER_MODE_LANG1 + 3 + Play the primary language, mono or stereo. Only +V4L2_TUNER_ANALOG_TV tuners support this +mode. + + + V4L2_TUNER_MODE_LANG2 + 2 + Play the secondary language, mono. When the tuner +receives no bilingual audio or SAP, or their reception is not +supported the driver shall fall back to mono or stereo mode. Only +V4L2_TUNER_ANALOG_TV tuners support this +mode. + + + V4L2_TUNER_MODE_SAP + 2 + Play the Second Audio Program. When the tuner +receives no bilingual audio or SAP, or their reception is not +supported the driver shall fall back to mono or stereo mode. Only +V4L2_TUNER_ANALOG_TV tuners support this mode. +Note the V4L2_TUNER_MODE_LANG2 and +V4L2_TUNER_MODE_SAP are synonyms. + + + V4L2_TUNER_MODE_LANG1_LANG2 + 4 + Play the primary language on the left channel, the +secondary language on the right channel. When the tuner receives no +bilingual audio or SAP, it shall fall back to +MODE_LANG1 or MODE_MONO. +Only V4L2_TUNER_ANALOG_TV tuners support this +mode. + + + +
+ + + Tuner Audio Matrix + + + + + + + + + + + Selected +V4L2_TUNER_MODE_ + + + Received V4L2_TUNER_SUB_ + MONO + STEREO + LANG1 + LANG2 = SAP + LANG1_LANG2This +mode has been added in Linux 2.6.17 and may not be supported by older +drivers. + + + + + MONO + Mono + Mono/Mono + Mono + Mono + Mono/Mono + + + MONO | SAP + Mono + Mono/Mono + Mono + SAP + Mono/SAP (preferred) or Mono/Mono + + + STEREO + L+R + L/R + Stereo L/R (preferred) or Mono L+R + Stereo L/R (preferred) or Mono L+R + L/R (preferred) or L+R/L+R + + + STEREO | SAP + L+R + L/R + Stereo L/R (preferred) or Mono L+R + SAP + L+R/SAP (preferred) or L/R or L+R/L+R + + + LANG1 | LANG2 + Language 1 + Lang1/Lang2 (deprecatedPlayback of +both languages in MODE_STEREO is deprecated. In +the future drivers should produce only the primary language in this +mode. Applications should request +MODE_LANG1_LANG2 to record both languages or a +stereo signal.) or +Lang1/Lang1 + Language 1 + Language 2 + Lang1/Lang2 (preferred) or Lang1/Lang1 + + + +
+ + + + &return-value; + + + + EINVAL + + The &v4l2-tuner; index is +out of bounds. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-log-status.xml b/Documentation/DocBook/v4l/vidioc-log-status.xml new file mode 100644 index 000000000000..2634b7c88b58 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-log-status.xml @@ -0,0 +1,58 @@ + + + ioctl VIDIOC_LOG_STATUS + &manvol; + + + + VIDIOC_LOG_STATUS + Log driver status information + + + + + + int ioctl + int fd + int request + + + + + + Description + + As the video/audio devices become more complicated it +becomes harder to debug problems. When this ioctl is called the driver +will output the current device status to the kernel log. This is +particular useful when dealing with problems like no sound, no video +and incorrectly tuned channels. Also many modern devices autodetect +video and audio standards and this ioctl will report what the device +thinks what the standard is. Mismatches may give an indication where +the problem is. + + This ioctl is optional and not all drivers support it. It +was introduced in Linux 2.6.15. + + + + &return-value; + + + + EINVAL + + The driver does not support this ioctl. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-overlay.xml b/Documentation/DocBook/v4l/vidioc-overlay.xml new file mode 100644 index 000000000000..1036c582cc15 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-overlay.xml @@ -0,0 +1,83 @@ + + + ioctl VIDIOC_OVERLAY + &manvol; + + + + VIDIOC_OVERLAY + Start or stop video overlay + + + + + + int ioctl + int fd + int request + const int *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_OVERLAY + + + + argp + + + + + + + + + Description + + This ioctl is part of the video + overlay I/O method. Applications call + VIDIOC_OVERLAY to start or stop the + overlay. It takes a pointer to an integer which must be set to + zero by the application to stop overlay, to one to start. + + Drivers do not support &VIDIOC-STREAMON; or +&VIDIOC-STREAMOFF; with V4L2_BUF_TYPE_VIDEO_OVERLAY. + + + + &return-value; + + + + EINVAL + + Video overlay is not supported, or the +parameters have not been set up. See for the necessary steps. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-qbuf.xml b/Documentation/DocBook/v4l/vidioc-qbuf.xml new file mode 100644 index 000000000000..187081778154 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-qbuf.xml @@ -0,0 +1,168 @@ + + + ioctl VIDIOC_QBUF, VIDIOC_DQBUF + &manvol; + + + + VIDIOC_QBUF + VIDIOC_DQBUF + Exchange a buffer with the driver + + + + + + int ioctl + int fd + int request + struct v4l2_buffer *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_QBUF, VIDIOC_DQBUF + + + + argp + + + + + + + + + Description + + Applications call the VIDIOC_QBUF ioctl +to enqueue an empty (capturing) or filled (output) buffer in the +driver's incoming queue. The semantics depend on the selected I/O +method. + + To enqueue a memory mapped +buffer applications set the type field of a +&v4l2-buffer; to the same buffer type as previously &v4l2-format; +type and &v4l2-requestbuffers; +type, the memory +field to V4L2_MEMORY_MMAP and the +index field. Valid index numbers range from +zero to the number of buffers allocated with &VIDIOC-REQBUFS; +(&v4l2-requestbuffers; count) minus one. The +contents of the struct v4l2_buffer returned +by a &VIDIOC-QUERYBUF; ioctl will do as well. When the buffer is +intended for output (type is +V4L2_BUF_TYPE_VIDEO_OUTPUT or +V4L2_BUF_TYPE_VBI_OUTPUT) applications must also +initialize the bytesused, +field and +timestamp fields. See for details. When +VIDIOC_QBUF is called with a pointer to this +structure the driver sets the +V4L2_BUF_FLAG_MAPPED and +V4L2_BUF_FLAG_QUEUED flags and clears the +V4L2_BUF_FLAG_DONE flag in the +flags field, or it returns an +&EINVAL;. + + To enqueue a user pointer +buffer applications set the type field of a +&v4l2-buffer; to the same buffer type as previously &v4l2-format; +type and &v4l2-requestbuffers; +type, the memory +field to V4L2_MEMORY_USERPTR and the +m.userptr field to the address of the +buffer and length to its size. When the +buffer is intended for output additional fields must be set as above. +When VIDIOC_QBUF is called with a pointer to this +structure the driver sets the V4L2_BUF_FLAG_QUEUED +flag and clears the V4L2_BUF_FLAG_MAPPED and +V4L2_BUF_FLAG_DONE flags in the +flags field, or it returns an error code. +This ioctl locks the memory pages of the buffer in physical memory, +they cannot be swapped out to disk. Buffers remain locked until +dequeued, until the &VIDIOC-STREAMOFF; or &VIDIOC-REQBUFS; ioctl are +called, or until the device is closed. + + Applications call the VIDIOC_DQBUF +ioctl to dequeue a filled (capturing) or displayed (output) buffer +from the driver's outgoing queue. They just set the +type and memory +fields of a &v4l2-buffer; as above, when VIDIOC_DQBUF +is called with a pointer to this structure the driver fills the +remaining fields or returns an error code. + + By default VIDIOC_DQBUF blocks when no +buffer is in the outgoing queue. When the +O_NONBLOCK flag was given to the &func-open; +function, VIDIOC_DQBUF returns immediately +with an &EAGAIN; when no buffer is available. + + The v4l2_buffer structure is +specified in . + + + + &return-value; + + + + EAGAIN + + Non-blocking I/O has been selected using +O_NONBLOCK and no buffer was in the outgoing +queue. + + + + EINVAL + + The buffer type is not +supported, or the index is out of bounds, +or no buffers have been allocated yet, or the +userptr or +length are invalid. + + + + ENOMEM + + Not enough physical or virtual memory was available to +enqueue a user pointer buffer. + + + + EIO + + VIDIOC_DQBUF failed due to an +internal error. Can also indicate temporary problems like signal +loss. Note the driver might dequeue an (empty) buffer despite +returning an error, or even stop capturing. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-querybuf.xml b/Documentation/DocBook/v4l/vidioc-querybuf.xml new file mode 100644 index 000000000000..d834993e6191 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-querybuf.xml @@ -0,0 +1,103 @@ + + + ioctl VIDIOC_QUERYBUF + &manvol; + + + + VIDIOC_QUERYBUF + Query the status of a buffer + + + + + + int ioctl + int fd + int request + struct v4l2_buffer *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_QUERYBUF + + + + argp + + + + + + + + + Description + + This ioctl is part of the memory +mapping I/O method. It can be used to query the status of a +buffer at any time after buffers have been allocated with the +&VIDIOC-REQBUFS; ioctl. + + Applications set the type field + of a &v4l2-buffer; to the same buffer type as previously +&v4l2-format; type and &v4l2-requestbuffers; +type, and the index + field. Valid index numbers range from zero +to the number of buffers allocated with &VIDIOC-REQBUFS; + (&v4l2-requestbuffers; count) minus one. +After calling VIDIOC_QUERYBUF with a pointer to + this structure drivers return an error code or fill the rest of +the structure. + + In the flags field the +V4L2_BUF_FLAG_MAPPED, +V4L2_BUF_FLAG_QUEUED and +V4L2_BUF_FLAG_DONE flags will be valid. The +memory field will be set to +V4L2_MEMORY_MMAP, the m.offset +contains the offset of the buffer from the start of the device memory, +the length field its size. The driver may +or may not set the remaining fields and flags, they are meaningless in +this context. + + The v4l2_buffer structure is + specified in . + + + + &return-value; + + + + EINVAL + + The buffer type is not +supported, or the index is out of bounds. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-querycap.xml b/Documentation/DocBook/v4l/vidioc-querycap.xml new file mode 100644 index 000000000000..6ab7e25b31b6 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-querycap.xml @@ -0,0 +1,284 @@ + + + ioctl VIDIOC_QUERYCAP + &manvol; + + + + VIDIOC_QUERYCAP + Query device capabilities + + + + + + int ioctl + int fd + int request + struct v4l2_capability *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_QUERYCAP + + + + argp + + + + + + + + + Description + + All V4L2 devices support the +VIDIOC_QUERYCAP ioctl. It is used to identify +kernel devices compatible with this specification and to obtain +information about driver and hardware capabilities. The ioctl takes a +pointer to a &v4l2-capability; which is filled by the driver. When the +driver is not compatible with this specification the ioctl returns an +&EINVAL;. + + + struct <structname>v4l2_capability</structname> + + &cs-str; + + + __u8 + driver[16] + Name of the driver, a unique NUL-terminated +ASCII string. For example: "bttv". Driver specific applications can +use this information to verify the driver identity. It is also useful +to work around known bugs, or to identify drivers in error reports. +The driver version is stored in the version +field.Storing strings in fixed sized arrays is bad +practice but unavoidable here. Drivers and applications should take +precautions to never read or write beyond the end of the array and to +make sure the strings are properly NUL-terminated. + + + __u8 + card[32] + Name of the device, a NUL-terminated ASCII string. +For example: "Yoyodyne TV/FM". One driver may support different brands +or models of video hardware. This information is intended for users, +for example in a menu of available devices. Since multiple TV cards of +the same brand may be installed which are supported by the same +driver, this name should be combined with the character device file +name (⪚ /dev/video2) or the +bus_info string to avoid +ambiguities. + + + __u8 + bus_info[32] + Location of the device in the system, a +NUL-terminated ASCII string. For example: "PCI Slot 4". This +information is intended for users, to distinguish multiple +identical devices. If no such information is available the field may +simply count the devices controlled by the driver, or contain the +empty string (bus_info[0] = 0). + + + __u32 + version + Version number of the driver. Together with +the driver field this identifies a +particular driver. The version number is formatted using the +KERNEL_VERSION() macro: + + + + +#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) + +__u32 version = KERNEL_VERSION(0, 8, 1); + +printf ("Version: %u.%u.%u\n", + (version >> 16) & 0xFF, + (version >> 8) & 0xFF, + version & 0xFF); + + + + __u32 + capabilities + Device capabilities, see . + + + __u32 + reserved[4] + Reserved for future extensions. Drivers must set +this array to zero. + + + +
+ + + Device Capabilities Flags + + &cs-def; + + + V4L2_CAP_VIDEO_CAPTURE + 0x00000001 + The device supports the Video Capture interface. + + + V4L2_CAP_VIDEO_OUTPUT + 0x00000002 + The device supports the Video Output interface. + + + V4L2_CAP_VIDEO_OVERLAY + 0x00000004 + The device supports the Video Overlay interface. A video overlay device +typically stores captured images directly in the video memory of a +graphics card, with hardware clipping and scaling. + + + V4L2_CAP_VBI_CAPTURE + 0x00000010 + The device supports the Raw +VBI Capture interface, providing Teletext and Closed Caption +data. + + + V4L2_CAP_VBI_OUTPUT + 0x00000020 + The device supports the Raw VBI Output interface. + + + V4L2_CAP_SLICED_VBI_CAPTURE + 0x00000040 + The device supports the Sliced VBI Capture interface. + + + V4L2_CAP_SLICED_VBI_OUTPUT + 0x00000080 + The device supports the Sliced VBI Output interface. + + + V4L2_CAP_RDS_CAPTURE + 0x00000100 + The device supports the RDS interface. + + + V4L2_CAP_VIDEO_OUTPUT_OVERLAY + 0x00000200 + The device supports the Video +Output Overlay (OSD) interface. Unlike the Video +Overlay interface, this is a secondary function of video +output devices and overlays an image onto an outgoing video signal. +When the driver sets this flag, it must clear the +V4L2_CAP_VIDEO_OVERLAY flag and vice +versa.The &v4l2-framebuffer; lacks an +&v4l2-buf-type; field, therefore the type of overlay is implied by the +driver capabilities. + + + V4L2_CAP_HW_FREQ_SEEK + 0x00000400 + The device supports the &VIDIOC-S-HW-FREQ-SEEK; ioctl for +hardware frequency seeking. + + + V4L2_CAP_TUNER + 0x00010000 + The device has some sort of tuner to +receive RF-modulated video signals. For more information about +tuner programming see +. + + + V4L2_CAP_AUDIO + 0x00020000 + The device has audio inputs or outputs. It may or +may not support audio recording or playback, in PCM or compressed +formats. PCM audio support must be implemented as ALSA or OSS +interface. For more information on audio inputs and outputs see . + + + V4L2_CAP_RADIO + 0x00040000 + This is a radio receiver. + + + V4L2_CAP_MODULATOR + 0x00080000 + The device has some sort of modulator to +emit RF-modulated video/audio signals. For more information about +modulator programming see +. + + + V4L2_CAP_READWRITE + 0x01000000 + The device supports the read() and/or write() +I/O methods. + + + V4L2_CAP_ASYNCIO + 0x02000000 + The device supports the asynchronous I/O methods. + + + V4L2_CAP_STREAMING + 0x04000000 + The device supports the streaming I/O method. + + + +
+ + + + &return-value; + + + + EINVAL + + The device is not compatible with this +specification. + + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-queryctrl.xml b/Documentation/DocBook/v4l/vidioc-queryctrl.xml new file mode 100644 index 000000000000..4876ff1a1a04 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-queryctrl.xml @@ -0,0 +1,428 @@ + + + ioctl VIDIOC_QUERYCTRL, VIDIOC_QUERYMENU + &manvol; + + + + VIDIOC_QUERYCTRL + VIDIOC_QUERYMENU + Enumerate controls and menu control items + + + + + + int ioctl + int fd + int request + struct v4l2_queryctrl *argp + + + + + int ioctl + int fd + int request + struct v4l2_querymenu *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_QUERYCTRL, VIDIOC_QUERYMENU + + + + argp + + + + + + + + + Description + + To query the attributes of a control applications set the +id field of a &v4l2-queryctrl; and call the +VIDIOC_QUERYCTRL ioctl with a pointer to this +structure. The driver fills the rest of the structure or returns an +&EINVAL; when the id is invalid. + + It is possible to enumerate controls by calling +VIDIOC_QUERYCTRL with successive +id values starting from +V4L2_CID_BASE up to and exclusive +V4L2_CID_BASE_LASTP1. Drivers may return +EINVAL if a control in this range is not +supported. Further applications can enumerate private controls, which +are not defined in this specification, by starting at +V4L2_CID_PRIVATE_BASE and incrementing +id until the driver returns +EINVAL. + + In both cases, when the driver sets the +V4L2_CTRL_FLAG_DISABLED flag in the +flags field this control is permanently +disabled and should be ignored by the application. + V4L2_CTRL_FLAG_DISABLED was +intended for two purposes: Drivers can skip predefined controls not +supported by the hardware (although returning EINVAL would do as +well), or disable predefined and private controls after hardware +detection without the trouble of reordering control arrays and indices +(EINVAL cannot be used to skip private controls because it would +prematurely end the enumeration). + + When the application ORs id with +V4L2_CTRL_FLAG_NEXT_CTRL the driver returns the +next supported control, or EINVAL if there is +none. Drivers which do not support this flag yet always return +EINVAL. + + Additional information is required for menu controls: the +names of the menu items. To query them applications set the +id and index +fields of &v4l2-querymenu; and call the +VIDIOC_QUERYMENU ioctl with a pointer to this +structure. The driver fills the rest of the structure or returns an +&EINVAL; when the id or +index is invalid. Menu items are enumerated +by calling VIDIOC_QUERYMENU with successive +index values from &v4l2-queryctrl; +minimum (0) to +maximum, inclusive. + + See also the examples in . + + + struct <structname>v4l2_queryctrl</structname> + + &cs-str; + + + __u32 + id + Identifies the control, set by the application. See + for predefined IDs. When the ID is ORed +with V4L2_CTRL_FLAG_NEXT_CTRL the driver clears the flag and returns +the first control with a higher ID. Drivers which do not support this +flag yet always return an &EINVAL;. + + + &v4l2-ctrl-type; + type + Type of control, see . + + + __u8 + name[32] + Name of the control, a NUL-terminated ASCII +string. This information is intended for the user. + + + __s32 + minimum + Minimum value, inclusive. This field gives a lower +bound for V4L2_CTRL_TYPE_INTEGER controls and the +lowest valid index (always 0) for V4L2_CTRL_TYPE_MENU controls. +For V4L2_CTRL_TYPE_STRING controls the minimum value +gives the minimum length of the string. This length does not include the terminating +zero. It may not be valid for any other type of control, including +V4L2_CTRL_TYPE_INTEGER64 controls. Note that this is a +signed value. + + + __s32 + maximum + Maximum value, inclusive. This field gives an upper +bound for V4L2_CTRL_TYPE_INTEGER controls and the +highest valid index for V4L2_CTRL_TYPE_MENU +controls. +For V4L2_CTRL_TYPE_STRING controls the maximum value +gives the maximum length of the string. This length does not include the terminating +zero. It may not be valid for any other type of control, including +V4L2_CTRL_TYPE_INTEGER64 controls. Note that this is a +signed value. + + + __s32 + step + This field gives a step size for +V4L2_CTRL_TYPE_INTEGER controls. For +V4L2_CTRL_TYPE_STRING controls this field refers to +the string length that has to be a multiple of this step size. +It may not be valid for any other type of control, including +V4L2_CTRL_TYPE_INTEGER64 +controls.Generally drivers should not scale hardware +control values. It may be necessary for example when the +name or id imply +a particular unit and the hardware actually accepts only multiples of +said unit. If so, drivers must take care values are properly rounded +when scaling, such that errors will not accumulate on repeated +read-write cycles.This field gives the smallest change of +an integer control actually affecting hardware. Often the information +is needed when the user can change controls by keyboard or GUI +buttons, rather than a slider. When for example a hardware register +accepts values 0-511 and the driver reports 0-65535, step should be +128.Note that although signed, the step value is supposed to +be always positive. + + + __s32 + default_value + The default value of a +V4L2_CTRL_TYPE_INTEGER, +_BOOLEAN or _MENU control. +Not valid for other types of controls. Drivers reset controls only +when the driver is loaded, not later, in particular not when the +func-open; is called. + + + __u32 + flags + Control flags, see . + + + __u32 + reserved[2] + Reserved for future extensions. Drivers must set +the array to zero. + + + +
+ + + struct <structname>v4l2_querymenu</structname> + + &cs-str; + + + __u32 + id + Identifies the control, set by the application +from the respective &v4l2-queryctrl; +id. + + + __u32 + index + Index of the menu item, starting at zero, set by + the application. + + + __u8 + name[32] + Name of the menu item, a NUL-terminated ASCII +string. This information is intended for the user. + + + __u32 + reserved + Reserved for future extensions. Drivers must set +the array to zero. + + + +
+ + + enum v4l2_ctrl_type + + + + + + + + + Type + minimum + step + maximum + Description + + + + + V4L2_CTRL_TYPE_INTEGER + any + any + any + An integer-valued control ranging from minimum to +maximum inclusive. The step value indicates the increment between +values which are actually different on the hardware. + + + V4L2_CTRL_TYPE_BOOLEAN + 0 + 1 + 1 + A boolean-valued control. Zero corresponds to +"disabled", and one means "enabled". + + + V4L2_CTRL_TYPE_MENU + 0 + 1 + N-1 + The control has a menu of N choices. The names of +the menu items can be enumerated with the +VIDIOC_QUERYMENU ioctl. + + + V4L2_CTRL_TYPE_BUTTON + 0 + 0 + 0 + A control which performs an action when set. +Drivers must ignore the value passed with +VIDIOC_S_CTRL and return an &EINVAL; on a +VIDIOC_G_CTRL attempt. + + + V4L2_CTRL_TYPE_INTEGER64 + n/a + n/a + n/a + A 64-bit integer valued control. Minimum, maximum +and step size cannot be queried. + + + V4L2_CTRL_TYPE_STRING + ≥ 0 + ≥ 1 + ≥ 0 + The minimum and maximum string lengths. The step size +means that the string must be (minimum + N * step) characters long for +N ≥ 0. These lengths do not include the terminating zero, so in order to +pass a string of length 8 to &VIDIOC-S-EXT-CTRLS; you need to set the +size field of &v4l2-ext-control; to 9. For &VIDIOC-G-EXT-CTRLS; you can +set the size field to maximum + 1. +Which character encoding is used will depend on the string control itself and +should be part of the control documentation. + + + V4L2_CTRL_TYPE_CTRL_CLASS + n/a + n/a + n/a + This is not a control. When +VIDIOC_QUERYCTRL is called with a control ID +equal to a control class code (see ), the +ioctl returns the name of the control class and this control type. +Older drivers which do not support this feature return an +&EINVAL;. + + + +
+ + + Control Flags + + &cs-def; + + + V4L2_CTRL_FLAG_DISABLED + 0x0001 + This control is permanently disabled and should be +ignored by the application. Any attempt to change the control will +result in an &EINVAL;. + + + V4L2_CTRL_FLAG_GRABBED + 0x0002 + This control is temporarily unchangeable, for +example because another application took over control of the +respective resource. Such controls may be displayed specially in a +user interface. Attempts to change the control may result in an +&EBUSY;. + + + V4L2_CTRL_FLAG_READ_ONLY + 0x0004 + This control is permanently readable only. Any +attempt to change the control will result in an &EINVAL;. + + + V4L2_CTRL_FLAG_UPDATE + 0x0008 + A hint that changing this control may affect the +value of other controls within the same control class. Applications +should update their user interface accordingly. + + + V4L2_CTRL_FLAG_INACTIVE + 0x0010 + This control is not applicable to the current +configuration and should be displayed accordingly in a user interface. +For example the flag may be set on a MPEG audio level 2 bitrate +control when MPEG audio encoding level 1 was selected with another +control. + + + V4L2_CTRL_FLAG_SLIDER + 0x0020 + A hint that this control is best represented as a +slider-like element in a user interface. + + + V4L2_CTRL_FLAG_WRITE_ONLY + 0x0040 + This control is permanently writable only. Any +attempt to read the control will result in an &EACCES; error code. This +flag is typically present for relative controls or action controls where +writing a value will cause the device to carry out a given action +(⪚ motor control) but no meaningful value can be returned. + + + +
+ + + + &return-value; + + + + EINVAL + + The &v4l2-queryctrl; id +is invalid. The &v4l2-querymenu; id or +index is invalid. + + + + EACCES + + An attempt was made to read a write-only control. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-querystd.xml b/Documentation/DocBook/v4l/vidioc-querystd.xml new file mode 100644 index 000000000000..b5a7ff934486 --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-querystd.xml @@ -0,0 +1,83 @@ + + + ioctl VIDIOC_QUERYSTD + &manvol; + + + + VIDIOC_QUERYSTD + Sense the video standard received by the current +input + + + + + + int ioctl + int fd + int request + v4l2_std_id *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_QUERYSTD + + + + argp + + + + + + + + + Description + + The hardware may be able to detect the current video +standard automatically. To do so, applications call +VIDIOC_QUERYSTD with a pointer to a &v4l2-std-id; type. The +driver stores here a set of candidates, this can be a single flag or a +set of supported standards if for example the hardware can only +distinguish between 50 and 60 Hz systems. When detection is not +possible or fails, the set must contain all standards supported by the +current video input or output. + + + + + &return-value; + + + + EINVAL + + This ioctl is not supported. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-reqbufs.xml b/Documentation/DocBook/v4l/vidioc-reqbufs.xml new file mode 100644 index 000000000000..bab38084454f --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-reqbufs.xml @@ -0,0 +1,160 @@ + + + ioctl VIDIOC_REQBUFS + &manvol; + + + + VIDIOC_REQBUFS + Initiate Memory Mapping or User Pointer I/O + + + + + + int ioctl + int fd + int request + struct v4l2_requestbuffers *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_REQBUFS + + + + argp + + + + + + + + + Description + + This ioctl is used to initiate memory +mapped or user pointer +I/O. Memory mapped buffers are located in device memory and must be +allocated with this ioctl before they can be mapped into the +application's address space. User buffers are allocated by +applications themselves, and this ioctl is merely used to switch the +driver into user pointer I/O mode. + + To allocate device buffers applications initialize three +fields of a v4l2_requestbuffers structure. +They set the type field to the respective +stream or buffer type, the count field to +the desired number of buffers, and memory +must be set to V4L2_MEMORY_MMAP. When the ioctl +is called with a pointer to this structure the driver attempts to +allocate the requested number of buffers and stores the actual number +allocated in the count field. It can be +smaller than the number requested, even zero, when the driver runs out +of free memory. A larger number is possible when the driver requires +more buffers to function correctly. + For example video output requires at least two buffers, +one displayed and one filled by the application. + When memory mapping I/O is not supported the ioctl +returns an &EINVAL;. + + Applications can call VIDIOC_REQBUFS +again to change the number of buffers, however this cannot succeed +when any buffers are still mapped. A count +value of zero frees all buffers, after aborting or finishing any DMA +in progress, an implicit &VIDIOC-STREAMOFF;. + + To negotiate user pointer I/O, applications initialize only +the type field and set +memory to +V4L2_MEMORY_USERPTR. When the ioctl is called +with a pointer to this structure the driver prepares for user pointer +I/O, when this I/O method is not supported the ioctl returns an +&EINVAL;. + + + struct <structname>v4l2_requestbuffers</structname> + + &cs-str; + + + __u32 + count + The number of buffers requested or granted. This +field is only used when memory is set to +V4L2_MEMORY_MMAP. + + + &v4l2-buf-type; + type + Type of the stream or buffers, this is the same +as the &v4l2-format; type field. See for valid values. + + + &v4l2-memory; + memory + Applications set this field to +V4L2_MEMORY_MMAP or +V4L2_MEMORY_USERPTR. + + + __u32 + reserved[2] + A place holder for future extensions and custom +(driver defined) buffer types V4L2_BUF_TYPE_PRIVATE and +higher. + + + +
+ + + + &return-value; + + + + EBUSY + + The driver supports multiple opens and I/O is already +in progress, or reallocation of buffers was attempted although one or +more are still mapped. + + + + EINVAL + + The buffer type (type field) or the +requested I/O method (memory) is not +supported. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-s-hw-freq-seek.xml b/Documentation/DocBook/v4l/vidioc-s-hw-freq-seek.xml new file mode 100644 index 000000000000..14b3ec7ed75b --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-s-hw-freq-seek.xml @@ -0,0 +1,129 @@ + + + ioctl VIDIOC_S_HW_FREQ_SEEK + &manvol; + + + + VIDIOC_S_HW_FREQ_SEEK + Perform a hardware frequency seek + + + + + + int ioctl + int fd + int request + struct v4l2_hw_freq_seek +*argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_S_HW_FREQ_SEEK + + + + argp + + + + + + + + + Description + + Start a hardware frequency seek from the current frequency. +To do this applications initialize the tuner, +type, seek_upward and +wrap_around fields, and zero out the +reserved array of a &v4l2-hw-freq-seek; and +call the VIDIOC_S_HW_FREQ_SEEK ioctl with a pointer +to this structure. + + This ioctl is supported if the V4L2_CAP_HW_FREQ_SEEK capability is set. + + + struct <structname>v4l2_hw_freq_seek</structname> + + &cs-str; + + + __u32 + tuner + The tuner index number. This is the +same value as in the &v4l2-input; tuner +field and the &v4l2-tuner; index field. + + + &v4l2-tuner-type; + type + The tuner type. This is the same value as in the +&v4l2-tuner; type field. + + + __u32 + seek_upward + If non-zero, seek upward from the current frequency, else seek downward. + + + __u32 + wrap_around + If non-zero, wrap around when at the end of the frequency range, else stop seeking. + + + __u32 + reserved[8] + Reserved for future extensions. Drivers and + applications must set the array to zero. + + + +
+ + + + &return-value; + + + + EINVAL + + The tuner index is out of +bounds or the value in the type field is +wrong. + + + + EAGAIN + + The ioctl timed-out. Try again. + + + + + + + diff --git a/Documentation/DocBook/v4l/vidioc-streamon.xml b/Documentation/DocBook/v4l/vidioc-streamon.xml new file mode 100644 index 000000000000..e42bff1f2c0a --- /dev/null +++ b/Documentation/DocBook/v4l/vidioc-streamon.xml @@ -0,0 +1,106 @@ + + + ioctl VIDIOC_STREAMON, VIDIOC_STREAMOFF + &manvol; + + + + VIDIOC_STREAMON + VIDIOC_STREAMOFF + Start or stop streaming I/O + + + + + + int ioctl + int fd + int request + const int *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_STREAMON, VIDIOC_STREAMOFF + + + + argp + + + + + + + + + Description + + The VIDIOC_STREAMON and +VIDIOC_STREAMOFF ioctl start and stop the capture +or output process during streaming (memory +mapping or user pointer) I/O. + + Specifically the capture hardware is disabled and no input +buffers are filled (if there are any empty buffers in the incoming +queue) until VIDIOC_STREAMON has been called. +Accordingly the output hardware is disabled, no video signal is +produced until VIDIOC_STREAMON has been called. +The ioctl will succeed only when at least one output buffer is in the +incoming queue. + + The VIDIOC_STREAMOFF ioctl, apart of +aborting or finishing any DMA in progress, unlocks any user pointer +buffers locked in physical memory, and it removes all buffers from the +incoming and outgoing queues. That means all images captured but not +dequeued yet will be lost, likewise all images enqueued for output but +not transmitted yet. I/O returns to the same state as after calling +&VIDIOC-REQBUFS; and can be restarted accordingly. + + Both ioctls take a pointer to an integer, the desired buffer or +stream type. This is the same as &v4l2-requestbuffers; +type. + + Note applications can be preempted for unknown periods right +before or after the VIDIOC_STREAMON or +VIDIOC_STREAMOFF calls, there is no notion of +starting or stopping "now". Buffer timestamps can be used to +synchronize with other events. + + + + &return-value; + + + + EINVAL + + Streaming I/O is not supported, the buffer +type is not supported, or no buffers have +been allocated (memory mapping) or enqueued (output) yet. + + + + + + + diff --git a/Documentation/dvb/get_dvb_firmware b/Documentation/dvb/get_dvb_firmware index 3d1b0ab70c8e..14b7b5a3bcb9 100644 --- a/Documentation/dvb/get_dvb_firmware +++ b/Documentation/dvb/get_dvb_firmware @@ -25,7 +25,8 @@ use IO::Handle; "tda10046lifeview", "av7110", "dec2000t", "dec2540t", "dec3000s", "vp7041", "dibusb", "nxt2002", "nxt2004", "or51211", "or51132_qam", "or51132_vsb", "bluebird", - "opera1", "cx231xx", "cx18", "cx23885", "pvrusb2", "mpc718" ); + "opera1", "cx231xx", "cx18", "cx23885", "pvrusb2", "mpc718", + "af9015"); # Check args syntax() if (scalar(@ARGV) != 1); @@ -514,6 +515,40 @@ sub bluebird { $outfile; } +sub af9015 { + my $sourcefile = "download.ashx?file=57"; + my $url = "http://www.ite.com.tw/EN/Services/$sourcefile"; + my $hash = "ff5b096ed47c080870eacdab2de33ad6"; + my $outfile = "dvb-usb-af9015.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + my $fwoffset = 0x22708; + my $fwlength = 18225; + my ($chunklength, $buf, $rcount); + + checkstandard(); + + wgetfile($sourcefile, $url); + unzip($sourcefile, $tmpdir); + verify("$tmpdir/Driver/Files/AF15BDA.sys", $hash); + + open INFILE, '<', "$tmpdir/Driver/Files/AF15BDA.sys"; + open OUTFILE, '>', $outfile; + + sysseek(INFILE, $fwoffset, SEEK_SET); + while($fwlength > 0) { + $chunklength = 55; + $chunklength = $fwlength if ($chunklength > $fwlength); + $rcount = sysread(INFILE, $buf, $chunklength); + die "Ran out of data\n" if ($rcount != $chunklength); + syswrite(OUTFILE, $buf); + sysread(INFILE, $buf, 8); + $fwlength -= $rcount + 8; + } + + close OUTFILE; + close INFILE; +} + # --------------------------------------------------------------- # Utilities diff --git a/Documentation/dvb/technisat.txt b/Documentation/dvb/technisat.txt index 3f435ffb289c..f0cc4f2d8365 100644 --- a/Documentation/dvb/technisat.txt +++ b/Documentation/dvb/technisat.txt @@ -4,9 +4,12 @@ How to set up the Technisat/B2C2 Flexcop devices 1) Find out what device you have ================================ +Important Notice: The driver does NOT support Technisat USB 2 devices! + First start your linux box with a shipped kernel: lspci -vvv for a PCI device (lsusb -vvv for an USB device) will show you for example: -02:0b.0 Network controller: Techsan Electronics Co Ltd B2C2 FlexCopII DVB chip / Technisat SkyStar2 DVB card (rev 02) +02:0b.0 Network controller: Techsan Electronics Co Ltd B2C2 FlexCopII DVB chip / + Technisat SkyStar2 DVB card (rev 02) dmesg | grep frontend may show you for example: DVB: registering frontend 0 (Conexant CX24123/CX24109)... @@ -14,62 +17,62 @@ DVB: registering frontend 0 (Conexant CX24123/CX24109)... 2) Kernel compilation: ====================== -If the Technisat is the only TV device in your box get rid of unnecessary modules and check this one: -"Multimedia devices" => "Customise analog and hybrid tuner modules to build" -In this directory uncheck every driver which is activated there (except "Simple tuner support" for case 9 only). +If the Flexcop / Technisat is the only DVB / TV / Radio device in your box + get rid of unnecessary modules and check this one: +"Multimedia support" => "Customise analog and hybrid tuner modules to build" +In this directory uncheck every driver which is activated there + (except "Simple tuner support" for ATSC 3rd generation only -> see case 9 please). Then please activate: 2a) Main module part: +"Multimedia support" => "DVB/ATSC adapters" + => "Technisat/B2C2 FlexcopII(b) and FlexCopIII adapters" -a.)"Multimedia devices" => "DVB/ATSC adapters" => "Technisat/B2C2 FlexcopII(b) and FlexCopIII adapters" -b.)"Multimedia devices" => "DVB/ATSC adapters" => "Technisat/B2C2 FlexcopII(b) and FlexCopIII adapters" => "Technisat/B2C2 Air/Sky/Cable2PC PCI" in case of a PCI card -OR -c.)"Multimedia devices" => "DVB/ATSC adapters" => "Technisat/B2C2 FlexcopII(b) and FlexCopIII adapters" => "Technisat/B2C2 Air/Sky/Cable2PC USB" in case of an USB 1.1 adapter -d.)"Multimedia devices" => "DVB/ATSC adapters" => "Technisat/B2C2 FlexcopII(b) and FlexCopIII adapters" => "Enable debug for the B2C2 FlexCop drivers" -Notice: d.) is helpful for troubleshooting +a.) => "Technisat/B2C2 Air/Sky/Cable2PC PCI" (PCI card) or +b.) => "Technisat/B2C2 Air/Sky/Cable2PC USB" (USB 1.1 adapter) + and for troubleshooting purposes: +c.) => "Enable debug for the B2C2 FlexCop drivers" -2b) Frontend module part: +2b) Frontend / Tuner / Demodulator module part: +"Multimedia support" => "DVB/ATSC adapters" + => "Customise the frontend modules to build" "Customise DVB frontends" => 1.) SkyStar DVB-S Revision 2.3: -a.)"Multimedia devices" => "Customise DVB frontends" => "Customise the frontend modules to build" -b.)"Multimedia devices" => "Customise DVB frontends" => "Zarlink VP310/MT312/ZL10313 based" +a.) => "Zarlink VP310/MT312/ZL10313 based" +b.) => "Generic I2C PLL based tuners" 2.) SkyStar DVB-S Revision 2.6: -a.)"Multimedia devices" => "Customise DVB frontends" => "Customise the frontend modules to build" -b.)"Multimedia devices" => "Customise DVB frontends" => "ST STV0299 based" +a.) => "ST STV0299 based" +b.) => "Generic I2C PLL based tuners" 3.) SkyStar DVB-S Revision 2.7: -a.)"Multimedia devices" => "Customise DVB frontends" => "Customise the frontend modules to build" -b.)"Multimedia devices" => "Customise DVB frontends" => "Samsung S5H1420 based" -c.)"Multimedia devices" => "Customise DVB frontends" => "Integrant ITD1000 Zero IF tuner for DVB-S/DSS" -d.)"Multimedia devices" => "Customise DVB frontends" => "ISL6421 SEC controller" +a.) => "Samsung S5H1420 based" +b.) => "Integrant ITD1000 Zero IF tuner for DVB-S/DSS" +c.) => "ISL6421 SEC controller" 4.) SkyStar DVB-S Revision 2.8: -a.)"Multimedia devices" => "Customise DVB frontends" => "Customise the frontend modules to build" -b.)"Multimedia devices" => "Customise DVB frontends" => "Conexant CX24113/CX24128 tuner for DVB-S/DSS" -c.)"Multimedia devices" => "Customise DVB frontends" => "Conexant CX24123 based" -d.)"Multimedia devices" => "Customise DVB frontends" => "ISL6421 SEC controller" +a.) => "Conexant CX24123 based" +b.) => "Conexant CX24113/CX24128 tuner for DVB-S/DSS" +c.) => "ISL6421 SEC controller" 5.) AirStar DVB-T card: -a.)"Multimedia devices" => "Customise DVB frontends" => "Customise the frontend modules to build" -b.)"Multimedia devices" => "Customise DVB frontends" => "Zarlink MT352 based" +a.) => "Zarlink MT352 based" +b.) => "Generic I2C PLL based tuners" 6.) CableStar DVB-C card: -a.)"Multimedia devices" => "Customise DVB frontends" => "Customise the frontend modules to build" -b.)"Multimedia devices" => "Customise DVB frontends" => "ST STV0297 based" +a.) => "ST STV0297 based" +b.) => "Generic I2C PLL based tuners" 7.) AirStar ATSC card 1st generation: -a.)"Multimedia devices" => "Customise DVB frontends" => "Customise the frontend modules to build" -b.)"Multimedia devices" => "Customise DVB frontends" => "Broadcom BCM3510" +a.) => "Broadcom BCM3510" 8.) AirStar ATSC card 2nd generation: -a.)"Multimedia devices" => "Customise DVB frontends" => "Customise the frontend modules to build" -b.)"Multimedia devices" => "Customise DVB frontends" => "NxtWave Communications NXT2002/NXT2004 based" -c.)"Multimedia devices" => "Customise DVB frontends" => "Generic I2C PLL based tuners" +a.) => "NxtWave Communications NXT2002/NXT2004 based" +b.) => "Generic I2C PLL based tuners" 9.) AirStar ATSC card 3rd generation: -a.)"Multimedia devices" => "Customise DVB frontends" => "Customise the frontend modules to build" -b.)"Multimedia devices" => "Customise DVB frontends" => "LG Electronics LGDT3302/LGDT3303 based" -c.)"Multimedia devices" => "Customise analog and hybrid tuner modules to build" => "Simple tuner support" +a.) => "LG Electronics LGDT3302/LGDT3303 based" +b.) "Multimedia support" => "Customise analog and hybrid tuner modules to build" + => "Simple tuner support" -Author: Uwe Bugla February 2009 +Author: Uwe Bugla August 2009 diff --git a/Documentation/markers.txt b/Documentation/markers.txt deleted file mode 100644 index d2b3d0e91b26..000000000000 --- a/Documentation/markers.txt +++ /dev/null @@ -1,104 +0,0 @@ - Using the Linux Kernel Markers - - Mathieu Desnoyers - - -This document introduces Linux Kernel Markers and their use. It provides -examples of how to insert markers in the kernel and connect probe functions to -them and provides some examples of probe functions. - - -* Purpose of markers - -A marker placed in code provides a hook to call a function (probe) that you can -provide at runtime. A marker can be "on" (a probe is connected to it) or "off" -(no probe is attached). When a marker is "off" it has no effect, except for -adding a tiny time penalty (checking a condition for a branch) and space -penalty (adding a few bytes for the function call at the end of the -instrumented function and adds a data structure in a separate section). When a -marker is "on", the function you provide is called each time the marker is -executed, in the execution context of the caller. When the function provided -ends its execution, it returns to the caller (continuing from the marker site). - -You can put markers at important locations in the code. Markers are -lightweight hooks that can pass an arbitrary number of parameters, -described in a printk-like format string, to the attached probe function. - -They can be used for tracing and performance accounting. - - -* Usage - -In order to use the macro trace_mark, you should include linux/marker.h. - -#include - -And, - -trace_mark(subsystem_event, "myint %d mystring %s", someint, somestring); -Where : -- subsystem_event is an identifier unique to your event - - subsystem is the name of your subsystem. - - event is the name of the event to mark. -- "myint %d mystring %s" is the formatted string for the serializer. "myint" and - "mystring" are repectively the field names associated with the first and - second parameter. -- someint is an integer. -- somestring is a char pointer. - -Connecting a function (probe) to a marker is done by providing a probe (function -to call) for the specific marker through marker_probe_register() and can be -activated by calling marker_arm(). Marker deactivation can be done by calling -marker_disarm() as many times as marker_arm() has been called. Removing a probe -is done through marker_probe_unregister(); it will disarm the probe. - -marker_synchronize_unregister() must be called between probe unregistration and -the first occurrence of -- the end of module exit function, - to make sure there is no caller left using the probe; -- the free of any resource used by the probes, - to make sure the probes wont be accessing invalid data. -This, and the fact that preemption is disabled around the probe call, make sure -that probe removal and module unload are safe. See the "Probe example" section -below for a sample probe module. - -The marker mechanism supports inserting multiple instances of the same marker. -Markers can be put in inline functions, inlined static functions, and -unrolled loops as well as regular functions. - -The naming scheme "subsystem_event" is suggested here as a convention intended -to limit collisions. Marker names are global to the kernel: they are considered -as being the same whether they are in the core kernel image or in modules. -Conflicting format strings for markers with the same name will cause the markers -to be detected to have a different format string not to be armed and will output -a printk warning which identifies the inconsistency: - -"Format mismatch for probe probe_name (format), marker (format)" - -Another way to use markers is to simply define the marker without generating any -function call to actually call into the marker. This is useful in combination -with tracepoint probes in a scheme like this : - -void probe_tracepoint_name(unsigned int arg1, struct task_struct *tsk); - -DEFINE_MARKER_TP(marker_eventname, tracepoint_name, probe_tracepoint_name, - "arg1 %u pid %d"); - -notrace void probe_tracepoint_name(unsigned int arg1, struct task_struct *tsk) -{ - struct marker *marker = &GET_MARKER(kernel_irq_entry); - /* write data to trace buffers ... */ -} - -* Probe / marker example - -See the example provided in samples/markers/src - -Compile them with your kernel. - -Run, as root : -modprobe marker-example (insmod order is not important) -modprobe probe-example -cat /proc/marker-example (returns an expected error) -rmmod marker-example probe-example -dmesg diff --git a/Documentation/video4linux/CARDLIST.cx23885 b/Documentation/video4linux/CARDLIST.cx23885 index 525edb37c758..5f33d8486102 100644 --- a/Documentation/video4linux/CARDLIST.cx23885 +++ b/Documentation/video4linux/CARDLIST.cx23885 @@ -23,3 +23,4 @@ 22 -> Mygica X8506 DMB-TH [14f1:8651] 23 -> Magic-Pro ProHDTV Extreme 2 [14f1:8657] 24 -> Hauppauge WinTV-HVR1850 [0070:8541] + 25 -> Compro VideoMate E800 [1858:e800] diff --git a/Documentation/video4linux/CARDLIST.em28xx b/Documentation/video4linux/CARDLIST.em28xx index b13fcbd5d94b..b8afef4c0e01 100644 --- a/Documentation/video4linux/CARDLIST.em28xx +++ b/Documentation/video4linux/CARDLIST.em28xx @@ -1,5 +1,5 @@ 0 -> Unknown EM2800 video grabber (em2800) [eb1a:2800] - 1 -> Unknown EM2750/28xx video grabber (em2820/em2840) [eb1a:2710,eb1a:2820,eb1a:2821,eb1a:2860,eb1a:2861,eb1a:2870,eb1a:2881,eb1a:2883] + 1 -> Unknown EM2750/28xx video grabber (em2820/em2840) [eb1a:2710,eb1a:2820,eb1a:2821,eb1a:2860,eb1a:2861,eb1a:2870,eb1a:2881,eb1a:2883,eb1a:2868] 2 -> Terratec Cinergy 250 USB (em2820/em2840) [0ccd:0036] 3 -> Pinnacle PCTV USB 2 (em2820/em2840) [2304:0208] 4 -> Hauppauge WinTV USB 2 (em2820/em2840) [2040:4200,2040:4201] @@ -68,3 +68,4 @@ 70 -> Evga inDtube (em2882) 71 -> Silvercrest Webcam 1.3mpix (em2820/em2840) 72 -> Gadmei UTV330+ (em2861) + 73 -> Reddo DVB-C USB TV Box (em2870) diff --git a/Documentation/video4linux/CARDLIST.saa7134 b/Documentation/video4linux/CARDLIST.saa7134 index 0ac4d2544778..2620d60341ee 100644 --- a/Documentation/video4linux/CARDLIST.saa7134 +++ b/Documentation/video4linux/CARDLIST.saa7134 @@ -171,3 +171,4 @@ 170 -> AverMedia AverTV Studio 505 [1461:a115] 171 -> Beholder BeholdTV X7 [5ace:7595] 172 -> RoverMedia TV Link Pro FM [19d1:0138] +173 -> Zolid Hybrid TV Tuner PCI [1131:2004] diff --git a/Documentation/video4linux/CARDLIST.saa7164 b/Documentation/video4linux/CARDLIST.saa7164 new file mode 100644 index 000000000000..152bd7b781ca --- /dev/null +++ b/Documentation/video4linux/CARDLIST.saa7164 @@ -0,0 +1,9 @@ + 0 -> Unknown + 1 -> Generic Rev2 + 2 -> Generic Rev3 + 3 -> Hauppauge WinTV-HVR2250 [0070:8880,0070:8810] + 4 -> Hauppauge WinTV-HVR2200 [0070:8980] + 5 -> Hauppauge WinTV-HVR2200 [0070:8900] + 6 -> Hauppauge WinTV-HVR2200 [0070:8901] + 7 -> Hauppauge WinTV-HVR2250 [0070:8891,0070:8851] + 8 -> Hauppauge WinTV-HVR2250 [0070:88A1] diff --git a/Documentation/video4linux/CARDLIST.tuner b/Documentation/video4linux/CARDLIST.tuner index ba9fa679e2d3..e0d298fe8830 100644 --- a/Documentation/video4linux/CARDLIST.tuner +++ b/Documentation/video4linux/CARDLIST.tuner @@ -79,3 +79,5 @@ tuner=78 - Philips FMD1216MEX MK3 Hybrid Tuner tuner=79 - Philips PAL/SECAM multi (FM1216 MK5) tuner=80 - Philips FQ1216LME MK3 PAL/SECAM w/active loopthrough tuner=81 - Partsnic (Daewoo) PTI-5NF05 +tuner=82 - Philips CU1216L +tuner=83 - NXP TDA18271 diff --git a/Documentation/video4linux/gspca.txt b/Documentation/video4linux/gspca.txt index 4686e84dd800..3f61825be499 100644 --- a/Documentation/video4linux/gspca.txt +++ b/Documentation/video4linux/gspca.txt @@ -173,6 +173,8 @@ ov519 05a9:8519 OmniVision ov519 05a9:a518 D-Link DSB-C310 Webcam sunplus 05da:1018 Digital Dream Enigma 1.3 stk014 05e1:0893 Syntek DV4000 +gl860 05e3:0503 Genesys Logic PC Camera +gl860 05e3:f191 Genesys Logic PC Camera spca561 060b:a001 Maxell Compact Pc PM3 zc3xx 0698:2003 CTX M730V built in spca500 06bd:0404 Agfa CL20 diff --git a/Documentation/video4linux/soc-camera.txt b/Documentation/video4linux/soc-camera.txt index 178ef3c5e579..3f87c7da4ca2 100644 --- a/Documentation/video4linux/soc-camera.txt +++ b/Documentation/video4linux/soc-camera.txt @@ -116,5 +116,45 @@ functionality. struct soc_camera_device also links to an array of struct soc_camera_data_format, listing pixel formats, supported by the camera. +VIDIOC_S_CROP and VIDIOC_S_FMT behaviour +---------------------------------------- + +Above user ioctls modify image geometry as follows: + +VIDIOC_S_CROP: sets location and sizes of the sensor window. Unit is one sensor +pixel. Changing sensor window sizes preserves any scaling factors, therefore +user window sizes change as well. + +VIDIOC_S_FMT: sets user window. Should preserve previously set sensor window as +much as possible by modifying scaling factors. If the sensor window cannot be +preserved precisely, it may be changed too. + +In soc-camera there are two locations, where scaling and cropping can taks +place: in the camera driver and in the host driver. User ioctls are first passed +to the host driver, which then generally passes them down to the camera driver. +It is more efficient to perform scaling and cropping in the camera driver to +save camera bus bandwidth and maximise the framerate. However, if the camera +driver failed to set the required parameters with sufficient precision, the host +driver may decide to also use its own scaling and cropping to fulfill the user's +request. + +Camera drivers are interfaced to the soc-camera core and to host drivers over +the v4l2-subdev API, which is completely functional, it doesn't pass any data. +Therefore all camera drivers shall reply to .g_fmt() requests with their current +output geometry. This is necessary to correctly configure the camera bus. +.s_fmt() and .try_fmt() have to be implemented too. Sensor window and scaling +factors have to be maintained by camera drivers internally. According to the +V4L2 API all capture drivers must support the VIDIOC_CROPCAP ioctl, hence we +rely on camera drivers implementing .cropcap(). If the camera driver does not +support cropping, it may choose to not implement .s_crop(), but to enable +cropping support by the camera host driver at least the .g_crop method must be +implemented. + +User window geometry is kept in .user_width and .user_height fields in struct +soc_camera_device and used by the soc-camera core and host drivers. The core +updates these fields upon successful completion of a .s_fmt() call, but if these +fields change elsewhere, e.g., during .s_crop() processing, the host driver is +responsible for updating them. + -- Author: Guennadi Liakhovetski diff --git a/Documentation/video4linux/v4l2-framework.txt b/Documentation/video4linux/v4l2-framework.txt index ba4706afc5fb..b806edaf3e75 100644 --- a/Documentation/video4linux/v4l2-framework.txt +++ b/Documentation/video4linux/v4l2-framework.txt @@ -370,19 +370,20 @@ from the remove() callback ensures that this is always done correctly. The bridge driver also has some helper functions it can use: struct v4l2_subdev *sd = v4l2_i2c_new_subdev(v4l2_dev, adapter, - "module_foo", "chipid", 0x36); + "module_foo", "chipid", 0x36, NULL); This loads the given module (can be NULL if no module needs to be loaded) and calls i2c_new_device() with the given i2c_adapter and chip/address arguments. If all goes well, then it registers the subdev with the v4l2_device. -You can also use v4l2_i2c_new_probed_subdev() which is very similar to -v4l2_i2c_new_subdev(), except that it has an array of possible I2C addresses -that it should probe. Internally it calls i2c_new_probed_device(). +You can also use the last argument of v4l2_i2c_new_subdev() to pass an array +of possible I2C addresses that it should probe. These probe addresses are +only used if the previous argument is 0. A non-zero argument means that you +know the exact i2c address so in that case no probing will take place. Both functions return NULL if something went wrong. -Note that the chipid you pass to v4l2_i2c_new_(probed_)subdev() is usually +Note that the chipid you pass to v4l2_i2c_new_subdev() is usually the same as the module name. It allows you to specify a chip variant, e.g. "saa7114" or "saa7115". In general though the i2c driver autodetects this. The use of chipid is something that needs to be looked at more closely at a @@ -410,11 +411,6 @@ the irq and platform_data arguments after the subdev was setup. The older v4l2_i2c_new_(probed_)subdev functions will call s_config as well, but with irq set to 0 and platform_data set to NULL. -Note that in the next kernel release the functions v4l2_i2c_new_subdev, -v4l2_i2c_new_probed_subdev and v4l2_i2c_new_probed_subdev_addr will all be -replaced by a single v4l2_i2c_new_subdev that is identical to -v4l2_i2c_new_subdev_cfg but without the irq and platform_data arguments. - struct video_device ------------------- @@ -490,31 +486,35 @@ VFL_TYPE_RADIO: radioX for radio tuners VFL_TYPE_VTX: vtxX for teletext devices (deprecated, don't use) The last argument gives you a certain amount of control over the device -kernel number used (i.e. the X in videoX). Normally you will pass -1 to -let the v4l2 framework pick the first free number. But if a driver creates -many devices, then it can be useful to have different video devices in -separate ranges. For example, video capture devices start at 0, video -output devices start at 16. - -So you can use the last argument to specify a minimum kernel number and -the v4l2 framework will try to pick the first free number that is equal +device node number used (i.e. the X in videoX). Normally you will pass -1 +to let the v4l2 framework pick the first free number. But sometimes users +want to select a specific node number. It is common that drivers allow +the user to select a specific device node number through a driver module +option. That number is then passed to this function and video_register_device +will attempt to select that device node number. If that number was already +in use, then the next free device node number will be selected and it +will send a warning to the kernel log. + +Another use-case is if a driver creates many devices. In that case it can +be useful to place different video devices in separate ranges. For example, +video capture devices start at 0, video output devices start at 16. +So you can use the last argument to specify a minimum device node number +and the v4l2 framework will try to pick the first free number that is equal or higher to what you passed. If that fails, then it will just pick the first free number. +Since in this case you do not care about a warning about not being able +to select the specified device node number, you can call the function +video_register_device_no_warn() instead. + Whenever a device node is created some attributes are also created for you. If you look in /sys/class/video4linux you see the devices. Go into e.g. video0 and you will see 'name' and 'index' attributes. The 'name' attribute -is the 'name' field of the video_device struct. The 'index' attribute is -a device node index that can be assigned by the driver, or that is calculated -for you. - -If you call video_register_device(), then the index is just increased by -1 for each device node you register. The first video device node you register -always starts off with 0. +is the 'name' field of the video_device struct. -Alternatively you can call video_register_device_index() which is identical -to video_register_device(), but with an extra index argument. Here you can -pass a specific index value (between 0 and 31) that should be used. +The 'index' attribute is the index of the device node: for each call to +video_register_device() the index is just increased by 1. The first video +device node you register always starts with index 0. Users can setup udev rules that utilize the index attribute to make fancy device names (e.g. 'mpegX' for MPEG video capture device nodes). @@ -523,9 +523,8 @@ After the device was successfully registered, then you can use these fields: - vfl_type: the device type passed to video_register_device. - minor: the assigned device minor number. -- num: the device kernel number (i.e. the X in videoX). -- index: the device index number (calculated or set explicitly using - video_register_device_index). +- num: the device node number (i.e. the X in videoX). +- index: the device index number. If the registration failed, then you need to call video_device_release() to free the allocated video_device struct, or free your own struct if the diff --git a/arch/powerpc/platforms/cell/spufs/file.c b/arch/powerpc/platforms/cell/spufs/file.c index ab8aef9bb8ea..8f079b865ad0 100644 --- a/arch/powerpc/platforms/cell/spufs/file.c +++ b/arch/powerpc/platforms/cell/spufs/file.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include diff --git a/arch/powerpc/platforms/cell/spufs/sched.c b/arch/powerpc/platforms/cell/spufs/sched.c index bb5b77c66d05..4678078fede8 100644 --- a/arch/powerpc/platforms/cell/spufs/sched.c +++ b/arch/powerpc/platforms/cell/spufs/sched.c @@ -39,7 +39,6 @@ #include #include #include -#include #include #include diff --git a/arch/sh/boards/board-ap325rxa.c b/arch/sh/boards/board-ap325rxa.c index 327d47c25a57..2d080732a964 100644 --- a/arch/sh/boards/board-ap325rxa.c +++ b/arch/sh/boards/board-ap325rxa.c @@ -310,8 +310,10 @@ static int camera_set_capture(struct soc_camera_platform_info *info, return ret; } +static int ap325rxa_camera_add(struct soc_camera_link *icl, struct device *dev); +static void ap325rxa_camera_del(struct soc_camera_link *icl); + static struct soc_camera_platform_info camera_info = { - .iface = 0, .format_name = "UYVY", .format_depth = 16, .format = { @@ -323,24 +325,46 @@ static struct soc_camera_platform_info camera_info = { .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8, .set_capture = camera_set_capture, + .link = { + .bus_id = 0, + .add_device = ap325rxa_camera_add, + .del_device = ap325rxa_camera_del, + .module_name = "soc_camera_platform", + }, }; +static void dummy_release(struct device *dev) +{ +} + static struct platform_device camera_device = { .name = "soc_camera_platform", .dev = { .platform_data = &camera_info, + .release = dummy_release, }, }; -static int __init camera_setup(void) +static int ap325rxa_camera_add(struct soc_camera_link *icl, + struct device *dev) { - if (camera_probe() > 0) - platform_device_register(&camera_device); + if (icl != &camera_info.link || camera_probe() <= 0) + return -ENODEV; - return 0; + camera_info.dev = dev; + + return platform_device_register(&camera_device); } -late_initcall(camera_setup); +static void ap325rxa_camera_del(struct soc_camera_link *icl) +{ + if (icl != &camera_info.link) + return; + + platform_device_unregister(&camera_device); + memset(&camera_device.dev.kobj, 0, + sizeof(camera_device.dev.kobj)); +} #endif /* CONFIG_I2C */ static int ov7725_power(struct device *dev, int mode) @@ -416,6 +440,7 @@ static struct ov772x_camera_info ov7725_info = { .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP, .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0), .link = { + .bus_id = 0, .power = ov7725_power, .board_info = &ap325rxa_i2c_camera[0], .i2c_adapter_id = 0, @@ -423,11 +448,19 @@ static struct ov772x_camera_info ov7725_info = { }, }; -static struct platform_device ap325rxa_camera = { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &ov7725_info.link, +static struct platform_device ap325rxa_camera[] = { + { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { + .platform_data = &ov7725_info.link, + }, + }, { + .name = "soc-camera-pdrv", + .id = 1, + .dev = { + .platform_data = &camera_info.link, + }, }, }; @@ -438,7 +471,8 @@ static struct platform_device *ap325rxa_devices[] __initdata = { &ceu_device, &nand_flash_device, &sdcard_cn3_device, - &ap325rxa_camera, + &ap325rxa_camera[0], + &ap325rxa_camera[1], }; static struct spi_board_info ap325rxa_spi_devices[] = { diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index c6d21b18806c..474d80d3e6cc 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -65,6 +65,19 @@ static inline void default_inquire_remote_apic(int apicid) __inquire_remote_apic(apicid); } +/* + * With 82489DX we can't rely on apic feature bit + * retrieved via cpuid but still have to deal with + * such an apic chip so we assume that SMP configuration + * is found from MP table (64bit case uses ACPI mostly + * which set smp presence flag as well so we are safe + * to use this helper too). + */ +static inline bool apic_from_smp_config(void) +{ + return smp_found_config && !disable_apic; +} + /* * Basic functions accessing APICs. */ diff --git a/arch/x86/include/asm/string_32.h b/arch/x86/include/asm/string_32.h index c86f452256de..ae907e617181 100644 --- a/arch/x86/include/asm/string_32.h +++ b/arch/x86/include/asm/string_32.h @@ -65,7 +65,6 @@ static __always_inline void *__constant_memcpy(void *to, const void *from, case 4: *(int *)to = *(int *)from; return to; - case 3: *(short *)to = *(short *)from; *((char *)to + 2) = *((char *)from + 2); diff --git a/arch/x86/include/asm/uaccess_32.h b/arch/x86/include/asm/uaccess_32.h index 5e06259e90e5..632fb44b4cb5 100644 --- a/arch/x86/include/asm/uaccess_32.h +++ b/arch/x86/include/asm/uaccess_32.h @@ -33,7 +33,7 @@ unsigned long __must_check __copy_from_user_ll_nocache_nozero * Copy data from kernel space to user space. Caller must check * the specified block with access_ok() before calling this function. * The caller should also make sure he pins the user space address - * so that the we don't result in page fault and sleep. + * so that we don't result in page fault and sleep. * * Here we special-case 1, 2 and 4-byte copy_*_user invocations. On a fault * we return the initial request size (1, 2 or 4), as copy_*_user should do. diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h index 77a68505419a..04eb6c958b9d 100644 --- a/arch/x86/include/asm/uv/uv_hub.h +++ b/arch/x86/include/asm/uv/uv_hub.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -258,13 +259,13 @@ static inline unsigned long *uv_global_mmr32_address(int pnode, static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) { - *uv_global_mmr32_address(pnode, offset) = val; + writeq(val, uv_global_mmr32_address(pnode, offset)); } static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) { - return *uv_global_mmr32_address(pnode, offset); + return readq(uv_global_mmr32_address(pnode, offset)); } /* @@ -281,13 +282,13 @@ static inline unsigned long *uv_global_mmr64_address(int pnode, static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) { - *uv_global_mmr64_address(pnode, offset) = val; + writeq(val, uv_global_mmr64_address(pnode, offset)); } static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) { - return *uv_global_mmr64_address(pnode, offset); + return readq(uv_global_mmr64_address(pnode, offset)); } /* @@ -301,22 +302,22 @@ static inline unsigned long *uv_local_mmr_address(unsigned long offset) static inline unsigned long uv_read_local_mmr(unsigned long offset) { - return *uv_local_mmr_address(offset); + return readq(uv_local_mmr_address(offset)); } static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) { - *uv_local_mmr_address(offset) = val; + writeq(val, uv_local_mmr_address(offset)); } static inline unsigned char uv_read_local_mmr8(unsigned long offset) { - return *((unsigned char *)uv_local_mmr_address(offset)); + return readb(uv_local_mmr_address(offset)); } static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) { - *((unsigned char *)uv_local_mmr_address(offset)) = val; + writeb(val, uv_local_mmr_address(offset)); } /* @@ -422,7 +423,7 @@ static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) unsigned long val; val = (1UL << UVH_IPI_INT_SEND_SHFT) | - ((apicid & 0x3f) << UVH_IPI_INT_APIC_ID_SHFT) | + ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) | (vector << UVH_IPI_INT_VECTOR_SHFT); uv_write_global_mmr64(pnode, UVH_IPI_INT, val); } diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 754174d09deb..894aa97f0717 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -62,7 +62,7 @@ unsigned int boot_cpu_physical_apicid = -1U; /* * The highest APIC ID seen during enumeration. * - * This determines the messaging protocol we can use: if all APIC IDs + * On AMD, this determines the messaging protocol we can use: if all APIC IDs * are in the 0 ... 7 range, then we can use logical addressing which * has some performance advantages (better broadcasting). * @@ -979,7 +979,7 @@ void lapic_shutdown(void) { unsigned long flags; - if (!cpu_has_apic) + if (!cpu_has_apic && !apic_from_smp_config()) return; local_irq_save(flags); @@ -1197,8 +1197,7 @@ void __cpuinit setup_local_APIC(void) * Double-check whether this APIC is really registered. * This is meaningless in clustered apic mode, so we skip it. */ - if (!apic->apic_id_registered()) - BUG(); + BUG_ON(!apic->apic_id_registered()); /* * Intel recommends to set DFR, LDR and TPR before enabling @@ -1917,24 +1916,14 @@ void __cpuinit generic_processor_info(int apicid, int version) max_physical_apicid = apicid; #ifdef CONFIG_X86_32 - /* - * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y - * but we need to work other dependencies like SMP_SUSPEND etc - * before this can be done without some confusion. - * if (CPU_HOTPLUG_ENABLED || num_processors > 8) - * - Ashok Raj - */ - if (max_physical_apicid >= 8) { - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_INTEL: - if (!APIC_XAPIC(version)) { - def_to_bigsmp = 0; - break; - } - /* If P4 and above fall through */ - case X86_VENDOR_AMD: + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_INTEL: + if (num_processors > 8) + def_to_bigsmp = 1; + break; + case X86_VENDOR_AMD: + if (max_physical_apicid >= 8) def_to_bigsmp = 1; - } } #endif diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 809e1cf86d6b..64970b9885f2 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1874,7 +1874,7 @@ __apicdebuginit(int) print_all_ICs(void) print_PIC(); /* don't print out if apic is not there */ - if (!cpu_has_apic || disable_apic) + if (!cpu_has_apic && !apic_from_smp_config()) return 0; print_all_local_APICs(); @@ -1999,7 +1999,7 @@ void disable_IO_APIC(void) /* * Use virtual wire A mode when interrupt remapping is enabled. */ - if (cpu_has_apic) + if (cpu_has_apic || apic_from_smp_config()) disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1); } diff --git a/arch/x86/kernel/apic/probe_64.c b/arch/x86/kernel/apic/probe_64.c index 65edc180fc82..c4cbd3080c1c 100644 --- a/arch/x86/kernel/apic/probe_64.c +++ b/arch/x86/kernel/apic/probe_64.c @@ -64,16 +64,23 @@ void __init default_setup_apic_routing(void) apic = &apic_x2apic_phys; else apic = &apic_x2apic_cluster; - printk(KERN_INFO "Setting APIC routing to %s\n", apic->name); } #endif if (apic == &apic_flat) { - if (max_physical_apicid >= 8) - apic = &apic_physflat; - printk(KERN_INFO "Setting APIC routing to %s\n", apic->name); + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_INTEL: + if (num_processors > 8) + apic = &apic_physflat; + break; + case X86_VENDOR_AMD: + if (max_physical_apicid >= 8) + apic = &apic_physflat; + } } + printk(KERN_INFO "Setting APIC routing to %s\n", apic->name); + if (is_vsmp_box()) { /* need to update phys_pkg_id */ apic->phys_pkg_id = apicid_phys_pkg_id; diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index 601159374e87..f5f5886a6b53 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -389,6 +389,16 @@ static __init void map_gru_high(int max_pnode) map_high("GRU", gru.s.base, shift, max_pnode, map_wb); } +static __init void map_mmr_high(int max_pnode) +{ + union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; + int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; + + mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); + if (mmr.s.enable) + map_high("MMR", mmr.s.base, shift, max_pnode, map_uc); +} + static __init void map_mmioh_high(int max_pnode) { union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; @@ -643,6 +653,7 @@ void __init uv_system_init(void) } map_gru_high(max_pnode); + map_mmr_high(max_pnode); map_mmioh_high(max_pnode); uv_cpu_init(); diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 8cd5224943b5..83a3d1f4efca 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -489,8 +489,9 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank) int i, err = 0; struct threshold_bank *b = NULL; char name[32]; +#ifdef CONFIG_SMP struct cpuinfo_x86 *c = &cpu_data(cpu); - +#endif sprintf(name, "threshold_bank%i", bank); diff --git a/arch/x86/kernel/cpu/mtrr/if.c b/arch/x86/kernel/cpu/mtrr/if.c index 08b6ea4c62b4..f04e72527604 100644 --- a/arch/x86/kernel/cpu/mtrr/if.c +++ b/arch/x86/kernel/cpu/mtrr/if.c @@ -126,8 +126,8 @@ mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos) return -EINVAL; base = simple_strtoull(line + 5, &ptr, 0); - for (; isspace(*ptr); ++ptr) - ; + while (isspace(*ptr)) + ptr++; if (strncmp(ptr, "size=", 5)) return -EINVAL; @@ -135,14 +135,14 @@ mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos) size = simple_strtoull(ptr + 5, &ptr, 0); if ((base & 0xfff) || (size & 0xfff)) return -EINVAL; - for (; isspace(*ptr); ++ptr) - ; + while (isspace(*ptr)) + ptr++; if (strncmp(ptr, "type=", 5)) return -EINVAL; ptr += 5; - for (; isspace(*ptr); ++ptr) - ; + while (isspace(*ptr)) + ptr++; for (i = 0; i < MTRR_NUM_TYPES; ++i) { if (strcmp(ptr, mtrr_strings[i])) diff --git a/arch/x86/kernel/cpu/vmware.c b/arch/x86/kernel/cpu/vmware.c index 0a46b4df5d80..1cbed97b59cf 100644 --- a/arch/x86/kernel/cpu/vmware.c +++ b/arch/x86/kernel/cpu/vmware.c @@ -58,6 +58,9 @@ static unsigned long vmware_get_tsc_khz(void) tsc_hz = eax | (((uint64_t)ebx) << 32); do_div(tsc_hz, 1000); BUG_ON(tsc_hz >> 32); + printk(KERN_INFO "TSC freq read from hypervisor : %lu.%03lu MHz\n", + (unsigned long) tsc_hz / 1000, + (unsigned long) tsc_hz % 1000); return tsc_hz; } @@ -69,6 +72,9 @@ void __init vmware_platform_setup(void) if (ebx != UINT_MAX) x86_platform.calibrate_tsc = vmware_get_tsc_khz; + else + printk(KERN_WARNING + "Failed to get TSC freq from the hypervisor\n"); } /* diff --git a/arch/x86/kernel/early_printk.c b/arch/x86/kernel/early_printk.c index 335f049d110f..b11cab3c323a 100644 --- a/arch/x86/kernel/early_printk.c +++ b/arch/x86/kernel/early_printk.c @@ -624,7 +624,7 @@ try_next_port: return -1; } - loop = 10; + loop = 100000; /* Reset the EHCI controller */ cmd = readl(&ehci_regs->command); cmd |= CMD_RESET; diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index a55f6609fe1f..f327bccf5089 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -697,21 +697,6 @@ void __init setup_arch(char **cmdline_p) printk(KERN_INFO "Command line: %s\n", boot_command_line); #endif - strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE); - *cmdline_p = command_line; - -#ifdef CONFIG_X86_64 - /* - * Must call this twice: Once just to detect whether hardware doesn't - * support NX (so that the early EHCI debug console setup can safely - * call set_fixmap(), and then again after parsing early parameters to - * honor the respective command line option. - */ - check_efer(); -#endif - - parse_early_param(); - /* VMI may relocate the fixmap; do this before touching ioremap area */ vmi_init(); @@ -794,6 +779,21 @@ void __init setup_arch(char **cmdline_p) #endif #endif + strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE); + *cmdline_p = command_line; + +#ifdef CONFIG_X86_64 + /* + * Must call this twice: Once just to detect whether hardware doesn't + * support NX (so that the early EHCI debug console setup can safely + * call set_fixmap(), and then again after parsing early parameters to + * honor the respective command line option. + */ + check_efer(); +#endif + + parse_early_param(); + #ifdef CONFIG_X86_64 check_efer(); #endif diff --git a/arch/x86/kernel/trampoline.c b/arch/x86/kernel/trampoline.c index 808031a5ba19..699f7eeb896a 100644 --- a/arch/x86/kernel/trampoline.c +++ b/arch/x86/kernel/trampoline.c @@ -4,7 +4,7 @@ #include /* ready for x86_64 and x86 */ -unsigned char *trampoline_base = __va(TRAMPOLINE_BASE); +unsigned char *__cpuinitdata trampoline_base = __va(TRAMPOLINE_BASE); void __init reserve_trampoline_memory(void) { @@ -26,7 +26,7 @@ void __init reserve_trampoline_memory(void) * bootstrap into the page concerned. The caller * has made sure it's suitably aligned. */ -unsigned long setup_trampoline(void) +unsigned long __cpuinit setup_trampoline(void) { memcpy(trampoline_base, trampoline_data, TRAMPOLINE_SIZE); return virt_to_phys(trampoline_base); diff --git a/arch/x86/kernel/trampoline_32.S b/arch/x86/kernel/trampoline_32.S index 66d874e5404c..8508237e8e43 100644 --- a/arch/x86/kernel/trampoline_32.S +++ b/arch/x86/kernel/trampoline_32.S @@ -28,16 +28,12 @@ */ #include +#include #include #include /* We can free up trampoline after bootup if cpu hotplug is not supported. */ -#ifndef CONFIG_HOTPLUG_CPU -.section ".cpuinit.data","aw",@progbits -#else -.section .rodata,"a",@progbits -#endif - +__CPUINITRODATA .code16 ENTRY(trampoline_data) diff --git a/arch/x86/kernel/trampoline_64.S b/arch/x86/kernel/trampoline_64.S index cddfb8d386b9..596d54c660a5 100644 --- a/arch/x86/kernel/trampoline_64.S +++ b/arch/x86/kernel/trampoline_64.S @@ -25,14 +25,15 @@ */ #include +#include #include #include #include #include #include -.section .rodata, "a", @progbits - +/* We can free up the trampoline after bootup if cpu hotplug is not supported. */ +__CPUINITRODATA .code16 ENTRY(trampoline_data) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 17409e8d1097..cd982f48e23e 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -666,7 +666,7 @@ static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) || (val == CPUFREQ_RESUMECHANGE)) { - *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); + *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); if (!(freq->flags & CPUFREQ_CONST_LOOPS)) diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S index 0ccb57d5ee35..a46acccec38a 100644 --- a/arch/x86/kernel/vmlinux.lds.S +++ b/arch/x86/kernel/vmlinux.lds.S @@ -45,9 +45,9 @@ PHDRS { text PT_LOAD FLAGS(5); /* R_E */ data PT_LOAD FLAGS(7); /* RWE */ #ifdef CONFIG_X86_64 - user PT_LOAD FLAGS(7); /* RWE */ + user PT_LOAD FLAGS(5); /* R_E */ #ifdef CONFIG_SMP - percpu PT_LOAD FLAGS(7); /* RWE */ + percpu PT_LOAD FLAGS(6); /* RW_ */ #endif init PT_LOAD FLAGS(7); /* RWE */ #endif diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c index 417c9f5b4afa..8aa85f17667e 100644 --- a/arch/x86/power/cpu.c +++ b/arch/x86/power/cpu.c @@ -243,10 +243,6 @@ static void __restore_processor_state(struct saved_context *ctxt) do_fpu_end(); mtrr_bp_restore(); - -#ifdef CONFIG_X86_OLD_MCE - mcheck_init(&boot_cpu_data); -#endif } /* Needed by apm.c */ diff --git a/drivers/acpi/acpica/tbfadt.c b/drivers/acpi/acpica/tbfadt.c index 82b02dcb942e..c016335fb759 100644 --- a/drivers/acpi/acpica/tbfadt.c +++ b/drivers/acpi/acpica/tbfadt.c @@ -275,7 +275,6 @@ void acpi_tb_parse_fadt(u32 table_index) void acpi_tb_create_local_fadt(struct acpi_table_header *table, u32 length) { - /* * Check if the FADT is larger than the largest table that we expect * (the ACPI 2.0/3.0 version). If so, truncate the table, and issue diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 39b393d38bb3..e4d971c8b9d0 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -18,6 +18,14 @@ menuconfig DRM details. You should also select and configure AGP (/dev/agpgart) support. +config DRM_KMS_HELPER + tristate + depends on DRM + select FB + select FRAMEBUFFER_CONSOLE if !EMBEDDED + help + FB and CRTC helpers for KMS drivers. + config DRM_TTM tristate depends on DRM @@ -36,6 +44,7 @@ config DRM_TDFX config DRM_R128 tristate "ATI Rage 128" depends on DRM && PCI + select FW_LOADER help Choose this option if you have an ATI Rage 128 graphics card. If M is selected, the module will be called r128. AGP support for @@ -47,8 +56,9 @@ config DRM_RADEON select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT - select FB - select FRAMEBUFFER_CONSOLE if !EMBEDDED + select FW_LOADER + select DRM_KMS_HELPER + select DRM_TTM help Choose this option if you have an ATI Radeon graphics card. There are both PCI and AGP versions. You don't need to choose this to @@ -82,11 +92,10 @@ config DRM_I830 config DRM_I915 tristate "i915 driver" depends on AGP_INTEL + select DRM_KMS_HELPER select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT - select FB - select FRAMEBUFFER_CONSOLE if !EMBEDDED # i915 depends on ACPI_VIDEO when ACPI is enabled # but for select to work, need to select ACPI_VIDEO's dependencies, ick select VIDEO_OUTPUT_CONTROL if ACPI @@ -116,6 +125,7 @@ endchoice config DRM_MGA tristate "Matrox g200/g400" depends on DRM + select FW_LOADER help Choose this option if you have a Matrox G200, G400 or G450 graphics card. If M is selected, the module will be called mga. AGP diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index fe23f29f7cba..3c8827a7aabd 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -10,11 +10,15 @@ drm-y := drm_auth.o drm_bufs.o drm_cache.o \ drm_lock.o drm_memory.o drm_proc.o drm_stub.o drm_vm.o \ drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \ drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \ - drm_crtc.o drm_crtc_helper.o drm_modes.o drm_edid.o \ - drm_info.o drm_debugfs.o + drm_crtc.o drm_modes.o drm_edid.o \ + drm_info.o drm_debugfs.o drm_encoder_slave.o drm-$(CONFIG_COMPAT) += drm_ioc32.o +drm_kms_helper-y := drm_fb_helper.o drm_crtc_helper.o + +obj-$(CONFIG_DRM_KMS_HELPER) += drm_kms_helper.o + obj-$(CONFIG_DRM) += drm.o obj-$(CONFIG_DRM_TTM) += ttm/ obj-$(CONFIG_DRM_TDFX) += tdfx/ diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c index 6246e3f3dad7..3d09e304f6f4 100644 --- a/drivers/gpu/drm/drm_bufs.c +++ b/drivers/gpu/drm/drm_bufs.c @@ -310,10 +310,10 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset, (unsigned long long)map->offset, map->size); break; + } case _DRM_GEM: - DRM_ERROR("tried to rmmap GEM object\n"); + DRM_ERROR("tried to addmap GEM object\n"); break; - } case _DRM_SCATTER_GATHER: if (!dev->sg) { kfree(map); diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index 0e994a0e46d4..0e3bd5b54b78 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -45,6 +45,23 @@ drm_clflush_page(struct page *page) clflush(page_virtual + i); kunmap_atomic(page_virtual, KM_USER0); } + +static void drm_cache_flush_clflush(struct page *pages[], + unsigned long num_pages) +{ + unsigned long i; + + mb(); + for (i = 0; i < num_pages; i++) + drm_clflush_page(*pages++); + mb(); +} + +static void +drm_clflush_ipi_handler(void *null) +{ + wbinvd(); +} #endif void @@ -53,17 +70,30 @@ drm_clflush_pages(struct page *pages[], unsigned long num_pages) #if defined(CONFIG_X86) if (cpu_has_clflush) { - unsigned long i; - - mb(); - for (i = 0; i < num_pages; ++i) - drm_clflush_page(*pages++); - mb(); - + drm_cache_flush_clflush(pages, num_pages); return; } - wbinvd(); + if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) + printk(KERN_ERR "Timed out waiting for cache flush.\n"); + +#elif defined(__powerpc__) + unsigned long i; + for (i = 0; i < num_pages; i++) { + struct page *page = pages[i]; + void *page_virtual; + + if (unlikely(page == NULL)) + continue; + + page_virtual = kmap_atomic(page, KM_USER0); + flush_dcache_range((unsigned long)page_virtual, + (unsigned long)page_virtual + PAGE_SIZE); + kunmap_atomic(page_virtual, KM_USER0); + } +#else + printk(KERN_ERR "Architecture has no drm_cache.c support\n"); + WARN_ON_ONCE(1); #endif } EXPORT_SYMBOL(drm_clflush_pages); diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 2f631c75f704..ba728ad77f2a 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -68,10 +68,10 @@ DRM_ENUM_NAME_FN(drm_get_dpms_name, drm_dpms_enum_list) */ static struct drm_prop_enum_list drm_scaling_mode_enum_list[] = { - { DRM_MODE_SCALE_NON_GPU, "Non-GPU" }, - { DRM_MODE_SCALE_FULLSCREEN, "Fullscreen" }, - { DRM_MODE_SCALE_NO_SCALE, "No scale" }, - { DRM_MODE_SCALE_ASPECT, "Aspect" }, + { DRM_MODE_SCALE_NONE, "None" }, + { DRM_MODE_SCALE_FULLSCREEN, "Full" }, + { DRM_MODE_SCALE_CENTER, "Center" }, + { DRM_MODE_SCALE_ASPECT, "Full aspect" }, }; static struct drm_prop_enum_list drm_dithering_mode_enum_list[] = @@ -108,6 +108,7 @@ static struct drm_prop_enum_list drm_tv_select_enum_list[] = { DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */ { DRM_MODE_SUBCONNECTOR_SVIDEO, "SVIDEO" }, /* TV-out */ { DRM_MODE_SUBCONNECTOR_Component, "Component" }, /* TV-out */ + { DRM_MODE_SUBCONNECTOR_SCART, "SCART" }, /* TV-out */ }; DRM_ENUM_NAME_FN(drm_get_tv_select_name, drm_tv_select_enum_list) @@ -118,6 +119,7 @@ static struct drm_prop_enum_list drm_tv_subconnector_enum_list[] = { DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */ { DRM_MODE_SUBCONNECTOR_SVIDEO, "SVIDEO" }, /* TV-out */ { DRM_MODE_SUBCONNECTOR_Component, "Component" }, /* TV-out */ + { DRM_MODE_SUBCONNECTOR_SCART, "SCART" }, /* TV-out */ }; DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name, @@ -146,6 +148,7 @@ static struct drm_conn_prop_enum_list drm_connector_enum_list[] = { DRM_MODE_CONNECTOR_DisplayPort, "DisplayPort", 0 }, { DRM_MODE_CONNECTOR_HDMIA, "HDMI Type A", 0 }, { DRM_MODE_CONNECTOR_HDMIB, "HDMI Type B", 0 }, + { DRM_MODE_CONNECTOR_TV, "TV", 0 }, }; static struct drm_prop_enum_list drm_encoder_enum_list[] = @@ -165,6 +168,7 @@ char *drm_get_encoder_name(struct drm_encoder *encoder) encoder->base.id); return buf; } +EXPORT_SYMBOL(drm_get_encoder_name); char *drm_get_connector_name(struct drm_connector *connector) { @@ -699,6 +703,42 @@ int drm_mode_create_tv_properties(struct drm_device *dev, int num_modes, drm_property_add_enum(dev->mode_config.tv_mode_property, i, i, modes[i]); + dev->mode_config.tv_brightness_property = + drm_property_create(dev, DRM_MODE_PROP_RANGE, + "brightness", 2); + dev->mode_config.tv_brightness_property->values[0] = 0; + dev->mode_config.tv_brightness_property->values[1] = 100; + + dev->mode_config.tv_contrast_property = + drm_property_create(dev, DRM_MODE_PROP_RANGE, + "contrast", 2); + dev->mode_config.tv_contrast_property->values[0] = 0; + dev->mode_config.tv_contrast_property->values[1] = 100; + + dev->mode_config.tv_flicker_reduction_property = + drm_property_create(dev, DRM_MODE_PROP_RANGE, + "flicker reduction", 2); + dev->mode_config.tv_flicker_reduction_property->values[0] = 0; + dev->mode_config.tv_flicker_reduction_property->values[1] = 100; + + dev->mode_config.tv_overscan_property = + drm_property_create(dev, DRM_MODE_PROP_RANGE, + "overscan", 2); + dev->mode_config.tv_overscan_property->values[0] = 0; + dev->mode_config.tv_overscan_property->values[1] = 100; + + dev->mode_config.tv_saturation_property = + drm_property_create(dev, DRM_MODE_PROP_RANGE, + "saturation", 2); + dev->mode_config.tv_saturation_property->values[0] = 0; + dev->mode_config.tv_saturation_property->values[1] = 100; + + dev->mode_config.tv_hue_property = + drm_property_create(dev, DRM_MODE_PROP_RANGE, + "hue", 2); + dev->mode_config.tv_hue_property->values[0] = 0; + dev->mode_config.tv_hue_property->values[1] = 100; + return 0; } EXPORT_SYMBOL(drm_mode_create_tv_properties); @@ -1044,7 +1084,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data, if (file_priv->master->minor->type == DRM_MINOR_CONTROL) { list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - DRM_DEBUG("CRTC ID is %d\n", crtc->base.id); + DRM_DEBUG_KMS("CRTC ID is %d\n", crtc->base.id); if (put_user(crtc->base.id, crtc_id + copied)) { ret = -EFAULT; goto out; @@ -1072,7 +1112,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data, list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - DRM_DEBUG("ENCODER ID is %d\n", + DRM_DEBUG_KMS("ENCODER ID is %d\n", encoder->base.id); if (put_user(encoder->base.id, encoder_id + copied)) { @@ -1103,7 +1143,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data, list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - DRM_DEBUG("CONNECTOR ID is %d\n", + DRM_DEBUG_KMS("CONNECTOR ID is %d\n", connector->base.id); if (put_user(connector->base.id, connector_id + copied)) { @@ -1127,7 +1167,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data, } card_res->count_connectors = connector_count; - DRM_DEBUG("Counted %d %d %d\n", card_res->count_crtcs, + DRM_DEBUG_KMS("Counted %d %d %d\n", card_res->count_crtcs, card_res->count_connectors, card_res->count_encoders); out: @@ -1230,7 +1270,7 @@ int drm_mode_getconnector(struct drm_device *dev, void *data, memset(&u_mode, 0, sizeof(struct drm_mode_modeinfo)); - DRM_DEBUG("connector id %d:\n", out_resp->connector_id); + DRM_DEBUG_KMS("connector id %d:\n", out_resp->connector_id); mutex_lock(&dev->mode_config.mutex); @@ -1406,7 +1446,7 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, obj = drm_mode_object_find(dev, crtc_req->crtc_id, DRM_MODE_OBJECT_CRTC); if (!obj) { - DRM_DEBUG("Unknown CRTC ID %d\n", crtc_req->crtc_id); + DRM_DEBUG_KMS("Unknown CRTC ID %d\n", crtc_req->crtc_id); ret = -EINVAL; goto out; } @@ -1419,7 +1459,8 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, list_for_each_entry(crtcfb, &dev->mode_config.crtc_list, head) { if (crtcfb == crtc) { - DRM_DEBUG("Using current fb for setmode\n"); + DRM_DEBUG_KMS("Using current fb for " + "setmode\n"); fb = crtc->fb; } } @@ -1427,7 +1468,8 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, obj = drm_mode_object_find(dev, crtc_req->fb_id, DRM_MODE_OBJECT_FB); if (!obj) { - DRM_DEBUG("Unknown FB ID%d\n", crtc_req->fb_id); + DRM_DEBUG_KMS("Unknown FB ID%d\n", + crtc_req->fb_id); ret = -EINVAL; goto out; } @@ -1440,13 +1482,13 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, } if (crtc_req->count_connectors == 0 && mode) { - DRM_DEBUG("Count connectors is 0 but mode set\n"); + DRM_DEBUG_KMS("Count connectors is 0 but mode set\n"); ret = -EINVAL; goto out; } if (crtc_req->count_connectors > 0 && (!mode || !fb)) { - DRM_DEBUG("Count connectors is %d but no mode or fb set\n", + DRM_DEBUG_KMS("Count connectors is %d but no mode or fb set\n", crtc_req->count_connectors); ret = -EINVAL; goto out; @@ -1479,7 +1521,8 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, obj = drm_mode_object_find(dev, out_id, DRM_MODE_OBJECT_CONNECTOR); if (!obj) { - DRM_DEBUG("Connector id %d unknown\n", out_id); + DRM_DEBUG_KMS("Connector id %d unknown\n", + out_id); ret = -EINVAL; goto out; } @@ -1512,7 +1555,7 @@ int drm_mode_cursor_ioctl(struct drm_device *dev, struct drm_crtc *crtc; int ret = 0; - DRM_DEBUG("\n"); + DRM_DEBUG_KMS("\n"); if (!req->flags) { DRM_ERROR("no operation set\n"); @@ -1522,7 +1565,7 @@ int drm_mode_cursor_ioctl(struct drm_device *dev, mutex_lock(&dev->mode_config.mutex); obj = drm_mode_object_find(dev, req->crtc_id, DRM_MODE_OBJECT_CRTC); if (!obj) { - DRM_DEBUG("Unknown CRTC ID %d\n", req->crtc_id); + DRM_DEBUG_KMS("Unknown CRTC ID %d\n", req->crtc_id); ret = -EINVAL; goto out; } diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index 6aaa2cb23365..fe8697447f32 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -33,15 +33,6 @@ #include "drm_crtc.h" #include "drm_crtc_helper.h" -/* - * Detailed mode info for 800x600@60Hz - */ -static struct drm_display_mode std_modes[] = { - { DRM_MODE("800x600", DRM_MODE_TYPE_DEFAULT, 40000, 800, 840, - 968, 1056, 0, 600, 601, 605, 628, 0, - DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, -}; - static void drm_mode_validate_flag(struct drm_connector *connector, int flags) { @@ -94,7 +85,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, int count = 0; int mode_flags = 0; - DRM_DEBUG("%s\n", drm_get_connector_name(connector)); + DRM_DEBUG_KMS("%s\n", drm_get_connector_name(connector)); /* set all modes to the unverified state */ list_for_each_entry_safe(mode, t, &connector->modes, head) mode->status = MODE_UNVERIFIED; @@ -102,15 +93,17 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, connector->status = connector->funcs->detect(connector); if (connector->status == connector_status_disconnected) { - DRM_DEBUG("%s is disconnected\n", + DRM_DEBUG_KMS("%s is disconnected\n", drm_get_connector_name(connector)); - /* TODO set EDID to NULL */ - return 0; + goto prune; } count = (*connector_funcs->get_modes)(connector); - if (!count) - return 0; + if (!count) { + count = drm_add_modes_noedid(connector, 800, 600); + if (!count) + return 0; + } drm_mode_connector_list_update(connector); @@ -130,7 +123,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, mode); } - +prune: drm_mode_prune_invalid(dev, &connector->modes, true); if (list_empty(&connector->modes)) @@ -138,7 +131,8 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, drm_mode_sort(&connector->modes); - DRM_DEBUG("Probed modes for %s\n", drm_get_connector_name(connector)); + DRM_DEBUG_KMS("Probed modes for %s\n", + drm_get_connector_name(connector)); list_for_each_entry_safe(mode, t, &connector->modes, head) { mode->vrefresh = drm_mode_vrefresh(mode); @@ -165,39 +159,6 @@ int drm_helper_probe_connector_modes(struct drm_device *dev, uint32_t maxX, } EXPORT_SYMBOL(drm_helper_probe_connector_modes); -static void drm_helper_add_std_modes(struct drm_device *dev, - struct drm_connector *connector) -{ - struct drm_display_mode *mode, *t; - int i; - - for (i = 0; i < ARRAY_SIZE(std_modes); i++) { - struct drm_display_mode *stdmode; - - /* - * When no valid EDID modes are available we end up - * here and bailed in the past, now we add some standard - * modes and move on. - */ - stdmode = drm_mode_duplicate(dev, &std_modes[i]); - drm_mode_probed_add(connector, stdmode); - drm_mode_list_concat(&connector->probed_modes, - &connector->modes); - - DRM_DEBUG("Adding mode %s to %s\n", stdmode->name, - drm_get_connector_name(connector)); - } - drm_mode_sort(&connector->modes); - - DRM_DEBUG("Added std modes on %s\n", drm_get_connector_name(connector)); - list_for_each_entry_safe(mode, t, &connector->modes, head) { - mode->vrefresh = drm_mode_vrefresh(mode); - - drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V); - drm_mode_debug_printmodeline(mode); - } -} - /** * drm_helper_encoder_in_use - check if a given encoder is in use * @encoder: encoder to check @@ -258,13 +219,27 @@ EXPORT_SYMBOL(drm_helper_crtc_in_use); void drm_helper_disable_unused_functions(struct drm_device *dev) { struct drm_encoder *encoder; + struct drm_connector *connector; struct drm_encoder_helper_funcs *encoder_funcs; struct drm_crtc *crtc; + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + if (!connector->encoder) + continue; + if (connector->status == connector_status_disconnected) + connector->encoder = NULL; + } + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { encoder_funcs = encoder->helper_private; - if (!drm_helper_encoder_in_use(encoder)) - (*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF); + if (!drm_helper_encoder_in_use(encoder)) { + if (encoder_funcs->disable) + (*encoder_funcs->disable)(encoder); + else + (*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF); + /* disconnector encoder from any connector */ + encoder->crtc = NULL; + } } list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { @@ -312,7 +287,7 @@ static void drm_enable_connectors(struct drm_device *dev, bool *enabled) list_for_each_entry(connector, &dev->mode_config.connector_list, head) { enabled[i] = drm_connector_enabled(connector, true); - DRM_DEBUG("connector %d enabled? %s\n", connector->base.id, + DRM_DEBUG_KMS("connector %d enabled? %s\n", connector->base.id, enabled[i] ? "yes" : "no"); any_enabled |= enabled[i]; i++; @@ -342,7 +317,7 @@ static bool drm_target_preferred(struct drm_device *dev, continue; } - DRM_DEBUG("looking for preferred mode on connector %d\n", + DRM_DEBUG_KMS("looking for preferred mode on connector %d\n", connector->base.id); modes[i] = drm_has_preferred_mode(connector, width, height); @@ -351,7 +326,7 @@ static bool drm_target_preferred(struct drm_device *dev, list_for_each_entry(modes[i], &connector->modes, head) break; } - DRM_DEBUG("found mode %s\n", modes[i] ? modes[i]->name : + DRM_DEBUG_KMS("found mode %s\n", modes[i] ? modes[i]->name : "none"); i++; } @@ -409,7 +384,7 @@ static int drm_pick_crtcs(struct drm_device *dev, c = 0; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - if ((connector->encoder->possible_crtcs & (1 << c)) == 0) { + if ((encoder->possible_crtcs & (1 << c)) == 0) { c++; continue; } @@ -452,7 +427,7 @@ static void drm_setup_crtcs(struct drm_device *dev) int width, height; int i, ret; - DRM_DEBUG("\n"); + DRM_DEBUG_KMS("\n"); width = dev->mode_config.max_width; height = dev->mode_config.max_height; @@ -475,7 +450,7 @@ static void drm_setup_crtcs(struct drm_device *dev) if (!ret) DRM_ERROR("Unable to find initial modes\n"); - DRM_DEBUG("picking CRTCs for %dx%d config\n", width, height); + DRM_DEBUG_KMS("picking CRTCs for %dx%d config\n", width, height); drm_pick_crtcs(dev, crtcs, modes, 0, width, height); @@ -490,12 +465,14 @@ static void drm_setup_crtcs(struct drm_device *dev) } if (mode && crtc) { - DRM_DEBUG("desired mode %s set on crtc %d\n", + DRM_DEBUG_KMS("desired mode %s set on crtc %d\n", mode->name, crtc->base.id); crtc->desired_mode = mode; connector->encoder->crtc = crtc; - } else + } else { connector->encoder->crtc = NULL; + connector->encoder = NULL; + } i++; } @@ -702,18 +679,17 @@ EXPORT_SYMBOL(drm_crtc_helper_set_mode); int drm_crtc_helper_set_config(struct drm_mode_set *set) { struct drm_device *dev; - struct drm_crtc **save_crtcs, *new_crtc; - struct drm_encoder **save_encoders, *new_encoder; + struct drm_crtc *save_crtcs, *new_crtc, *crtc; + struct drm_encoder *save_encoders, *new_encoder, *encoder; struct drm_framebuffer *old_fb = NULL; - bool save_enabled; bool mode_changed = false; /* if true do a full mode set */ bool fb_changed = false; /* if true and !mode_changed just do a flip */ - struct drm_connector *connector; + struct drm_connector *save_connectors, *connector; int count = 0, ro, fail = 0; struct drm_crtc_helper_funcs *crtc_funcs; int ret = 0; - DRM_DEBUG("\n"); + DRM_DEBUG_KMS("\n"); if (!set) return -EINVAL; @@ -726,37 +702,60 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) crtc_funcs = set->crtc->helper_private; - DRM_DEBUG("crtc: %p %d fb: %p connectors: %p num_connectors: %d (x, y) (%i, %i)\n", + DRM_DEBUG_KMS("crtc: %p %d fb: %p connectors: %p num_connectors:" + " %d (x, y) (%i, %i)\n", set->crtc, set->crtc->base.id, set->fb, set->connectors, (int)set->num_connectors, set->x, set->y); dev = set->crtc->dev; - /* save previous config */ - save_enabled = set->crtc->enabled; - - /* - * We do mode_config.num_connectors here since we'll look at the - * CRTC and encoder associated with each connector later. - */ - save_crtcs = kzalloc(dev->mode_config.num_connector * - sizeof(struct drm_crtc *), GFP_KERNEL); + /* Allocate space for the backup of all (non-pointer) crtc, encoder and + * connector data. */ + save_crtcs = kzalloc(dev->mode_config.num_crtc * + sizeof(struct drm_crtc), GFP_KERNEL); if (!save_crtcs) return -ENOMEM; - save_encoders = kzalloc(dev->mode_config.num_connector * - sizeof(struct drm_encoders *), GFP_KERNEL); + save_encoders = kzalloc(dev->mode_config.num_encoder * + sizeof(struct drm_encoder), GFP_KERNEL); if (!save_encoders) { kfree(save_crtcs); return -ENOMEM; } + save_connectors = kzalloc(dev->mode_config.num_connector * + sizeof(struct drm_connector), GFP_KERNEL); + if (!save_connectors) { + kfree(save_crtcs); + kfree(save_encoders); + return -ENOMEM; + } + + /* Copy data. Note that driver private data is not affected. + * Should anything bad happen only the expected state is + * restored, not the drivers personal bookkeeping. + */ + count = 0; + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + save_crtcs[count++] = *crtc; + } + + count = 0; + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + save_encoders[count++] = *encoder; + } + + count = 0; + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + save_connectors[count++] = *connector; + } + /* We should be able to check here if the fb has the same properties * and then just flip_or_move it */ if (set->crtc->fb != set->fb) { /* If we have no fb then treat it as a full mode set */ if (set->crtc->fb == NULL) { - DRM_DEBUG("crtc has no fb, full mode set\n"); + DRM_DEBUG_KMS("crtc has no fb, full mode set\n"); mode_changed = true; } else if (set->fb == NULL) { mode_changed = true; @@ -772,7 +771,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) fb_changed = true; if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { - DRM_DEBUG("modes are different, full mode set\n"); + DRM_DEBUG_KMS("modes are different, full mode set\n"); drm_mode_debug_printmodeline(&set->crtc->mode); drm_mode_debug_printmodeline(set->mode); mode_changed = true; @@ -783,7 +782,6 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) list_for_each_entry(connector, &dev->mode_config.connector_list, head) { struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; - save_encoders[count++] = connector->encoder; new_encoder = connector->encoder; for (ro = 0; ro < set->num_connectors; ro++) { if (set->connectors[ro] == connector) { @@ -798,15 +796,20 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) } if (new_encoder != connector->encoder) { - DRM_DEBUG("encoder changed, full mode switch\n"); + DRM_DEBUG_KMS("encoder changed, full mode switch\n"); mode_changed = true; + /* If the encoder is reused for another connector, then + * the appropriate crtc will be set later. + */ + if (connector->encoder) + connector->encoder->crtc = NULL; connector->encoder = new_encoder; } } if (fail) { ret = -EINVAL; - goto fail_no_encoder; + goto fail; } count = 0; @@ -814,8 +817,6 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) if (!connector->encoder) continue; - save_crtcs[count++] = connector->encoder->crtc; - if (connector->encoder->crtc == set->crtc) new_crtc = NULL; else @@ -830,14 +831,14 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) if (new_crtc && !drm_encoder_crtc_ok(connector->encoder, new_crtc)) { ret = -EINVAL; - goto fail_set_mode; + goto fail; } if (new_crtc != connector->encoder->crtc) { - DRM_DEBUG("crtc changed, full mode switch\n"); + DRM_DEBUG_KMS("crtc changed, full mode switch\n"); mode_changed = true; connector->encoder->crtc = new_crtc; } - DRM_DEBUG("setting connector %d crtc to %p\n", + DRM_DEBUG_KMS("setting connector %d crtc to %p\n", connector->base.id, new_crtc); } @@ -850,7 +851,8 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) set->crtc->fb = set->fb; set->crtc->enabled = (set->mode != NULL); if (set->mode != NULL) { - DRM_DEBUG("attempting to set mode from userspace\n"); + DRM_DEBUG_KMS("attempting to set mode from" + " userspace\n"); drm_mode_debug_printmodeline(set->mode); if (!drm_crtc_helper_set_mode(set->crtc, set->mode, set->x, set->y, @@ -858,7 +860,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) DRM_ERROR("failed to set mode on crtc %p\n", set->crtc); ret = -EINVAL; - goto fail_set_mode; + goto fail; } /* TODO are these needed? */ set->crtc->desired_x = set->x; @@ -867,43 +869,50 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) } drm_helper_disable_unused_functions(dev); } else if (fb_changed) { + set->crtc->x = set->x; + set->crtc->y = set->y; + old_fb = set->crtc->fb; if (set->crtc->fb != set->fb) set->crtc->fb = set->fb; ret = crtc_funcs->mode_set_base(set->crtc, set->x, set->y, old_fb); if (ret != 0) - goto fail_set_mode; + goto fail; } + kfree(save_connectors); kfree(save_encoders); kfree(save_crtcs); return 0; -fail_set_mode: - set->crtc->enabled = save_enabled; - set->crtc->fb = old_fb; +fail: + /* Restore all previous data. */ count = 0; - list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - if (!connector->encoder) - continue; + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + *crtc = save_crtcs[count++]; + } - connector->encoder->crtc = save_crtcs[count++]; + count = 0; + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + *encoder = save_encoders[count++]; } -fail_no_encoder: - kfree(save_crtcs); + count = 0; list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - connector->encoder = save_encoders[count++]; + *connector = save_connectors[count++]; } + + kfree(save_connectors); kfree(save_encoders); + kfree(save_crtcs); return ret; } EXPORT_SYMBOL(drm_crtc_helper_set_config); bool drm_helper_plugged_event(struct drm_device *dev) { - DRM_DEBUG("\n"); + DRM_DEBUG_KMS("\n"); drm_helper_probe_connector_modes(dev, dev->mode_config.max_width, dev->mode_config.max_height); @@ -932,7 +941,6 @@ bool drm_helper_plugged_event(struct drm_device *dev) */ bool drm_helper_initial_config(struct drm_device *dev) { - struct drm_connector *connector; int count = 0; count = drm_helper_probe_connector_modes(dev, @@ -940,16 +948,9 @@ bool drm_helper_initial_config(struct drm_device *dev) dev->mode_config.max_height); /* - * None of the available connectors had any modes, so add some - * and try to light them up anyway + * we shouldn't end up with no modes here. */ - if (!count) { - DRM_ERROR("connectors have no modes, using standard modes\n"); - list_for_each_entry(connector, - &dev->mode_config.connector_list, - head) - drm_helper_add_std_modes(dev, connector); - } + WARN(!count, "Connected connector with 0 modes\n"); drm_setup_crtcs(dev); diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c index b39d7bfc0c9c..a75ca63deea6 100644 --- a/drivers/gpu/drm/drm_drv.c +++ b/drivers/gpu/drm/drm_drv.c @@ -63,12 +63,12 @@ static struct drm_ioctl_desc drm_ioctls[] = { DRM_IOCTL_DEF(DRM_IOCTL_GET_MAP, drm_getmap, 0), DRM_IOCTL_DEF(DRM_IOCTL_GET_CLIENT, drm_getclient, 0), DRM_IOCTL_DEF(DRM_IOCTL_GET_STATS, drm_getstats, 0), - DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER), DRM_IOCTL_DEF(DRM_IOCTL_SET_UNIQUE, drm_setunique, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF(DRM_IOCTL_BLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF(DRM_IOCTL_UNBLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_AUTH|DRM_MASTER), DRM_IOCTL_DEF(DRM_IOCTL_ADD_MAP, drm_addmap_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF(DRM_IOCTL_RM_MAP, drm_rmmap_ioctl, DRM_AUTH), diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 7f2728bbc16c..90d76bacff17 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -60,6 +60,12 @@ #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) /* use +hsync +vsync for detailed mode */ #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) +/* define the number of Extension EDID block */ +#define MAX_EDID_EXT_NUM 4 + +#define LEVEL_DMT 0 +#define LEVEL_GTF 1 +#define LEVEL_CVT 2 static struct edid_quirk { char *vendor; @@ -237,28 +243,291 @@ static void edid_fixup_preferred(struct drm_connector *connector, preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; } +/* + * Add the Autogenerated from the DMT spec. + * This table is copied from xfree86/modes/xf86EdidModes.c. + * But the mode with Reduced blank feature is deleted. + */ +static struct drm_display_mode drm_dmt_modes[] = { + /* 640x350@85Hz */ + { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, + 736, 832, 0, 350, 382, 385, 445, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 640x400@85Hz */ + { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, + 736, 832, 0, 400, 401, 404, 445, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 720x400@85Hz */ + { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, + 828, 936, 0, 400, 401, 404, 446, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 640x480@60Hz */ + { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, + 752, 800, 0, 480, 489, 492, 525, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 640x480@72Hz */ + { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, + 704, 832, 0, 480, 489, 492, 520, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 640x480@75Hz */ + { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, + 720, 840, 0, 480, 481, 484, 500, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 640x480@85Hz */ + { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, + 752, 832, 0, 480, 481, 484, 509, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 800x600@56Hz */ + { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, + 896, 1024, 0, 600, 601, 603, 625, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 800x600@60Hz */ + { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, + 968, 1056, 0, 600, 601, 605, 628, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 800x600@72Hz */ + { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, + 976, 1040, 0, 600, 637, 643, 666, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 800x600@75Hz */ + { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, + 896, 1056, 0, 600, 601, 604, 625, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 800x600@85Hz */ + { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, + 896, 1048, 0, 600, 601, 604, 631, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 848x480@60Hz */ + { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, + 976, 1088, 0, 480, 486, 494, 517, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1024x768@43Hz, interlace */ + { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, + 1208, 1264, 0, 768, 768, 772, 817, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | + DRM_MODE_FLAG_INTERLACE) }, + /* 1024x768@60Hz */ + { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, + 1184, 1344, 0, 768, 771, 777, 806, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1024x768@70Hz */ + { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, + 1184, 1328, 0, 768, 771, 777, 806, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1024x768@75Hz */ + { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, + 1136, 1312, 0, 768, 769, 772, 800, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1024x768@85Hz */ + { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, + 1072, 1376, 0, 768, 769, 772, 808, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1152x864@75Hz */ + { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, + 1344, 1600, 0, 864, 865, 868, 900, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x768@60Hz */ + { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, + 1472, 1664, 0, 768, 771, 778, 798, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x768@75Hz */ + { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, + 1488, 1696, 0, 768, 771, 778, 805, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1280x768@85Hz */ + { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, + 1496, 1712, 0, 768, 771, 778, 809, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x800@60Hz */ + { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, + 1480, 1680, 0, 800, 803, 809, 831, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1280x800@75Hz */ + { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, + 1488, 1696, 0, 800, 803, 809, 838, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x800@85Hz */ + { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, + 1496, 1712, 0, 800, 803, 809, 843, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x960@60Hz */ + { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, + 1488, 1800, 0, 960, 961, 964, 1000, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x960@85Hz */ + { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, + 1504, 1728, 0, 960, 961, 964, 1011, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x1024@60Hz */ + { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, + 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x1024@75Hz */ + { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, + 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x1024@85Hz */ + { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, + 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1360x768@60Hz */ + { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, + 1536, 1792, 0, 768, 771, 777, 795, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1440x1050@60Hz */ + { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, + 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1440x1050@75Hz */ + { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, + 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1440x1050@85Hz */ + { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, + 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1440x900@60Hz */ + { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, + 1672, 1904, 0, 900, 903, 909, 934, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1440x900@75Hz */ + { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, + 1688, 1936, 0, 900, 903, 909, 942, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1440x900@85Hz */ + { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, + 1696, 1952, 0, 900, 903, 909, 948, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1600x1200@60Hz */ + { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, + 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1600x1200@65Hz */ + { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, + 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1600x1200@70Hz */ + { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, + 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1600x1200@75Hz */ + { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 2025000, 1600, 1664, + 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1600x1200@85Hz */ + { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, + 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1680x1050@60Hz */ + { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, + 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1680x1050@75Hz */ + { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, + 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1680x1050@85Hz */ + { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, + 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1792x1344@60Hz */ + { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, + 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1729x1344@75Hz */ + { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, + 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1853x1392@60Hz */ + { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, + 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1856x1392@75Hz */ + { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, + 2208, 2560, 0, 1392, 1395, 1399, 1500, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1920x1200@60Hz */ + { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, + 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1920x1200@75Hz */ + { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, + 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1920x1200@85Hz */ + { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, + 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1920x1440@60Hz */ + { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, + 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1920x1440@75Hz */ + { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, + 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 2560x1600@60Hz */ + { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, + 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 2560x1600@75HZ */ + { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, + 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 2560x1600@85HZ */ + { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, + 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, +}; + +static struct drm_display_mode *drm_find_dmt(struct drm_device *dev, + int hsize, int vsize, int fresh) +{ + int i, count; + struct drm_display_mode *ptr, *mode; + + count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); + mode = NULL; + for (i = 0; i < count; i++) { + ptr = &drm_dmt_modes[i]; + if (hsize == ptr->hdisplay && + vsize == ptr->vdisplay && + fresh == drm_mode_vrefresh(ptr)) { + /* get the expected default mode */ + mode = drm_mode_duplicate(dev, ptr); + break; + } + } + return mode; +} /** * drm_mode_std - convert standard mode info (width, height, refresh) into mode * @t: standard timing params + * @timing_level: standard timing level * * Take the standard timing params (in this case width, aspect, and refresh) - * and convert them into a real mode using CVT. + * and convert them into a real mode using CVT/GTF/DMT. * * Punts for now, but should eventually use the FB layer's CVT based mode * generation code. */ struct drm_display_mode *drm_mode_std(struct drm_device *dev, - struct std_timing *t) + struct std_timing *t, + int timing_level) { struct drm_display_mode *mode; - int hsize = t->hsize * 8 + 248, vsize; + int hsize, vsize; + int vrefresh_rate; unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) >> EDID_TIMING_ASPECT_SHIFT; - - mode = drm_mode_create(dev); - if (!mode) - return NULL; - + unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) + >> EDID_TIMING_VFREQ_SHIFT; + + /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ + hsize = t->hsize * 8 + 248; + /* vrefresh_rate = vfreq + 60 */ + vrefresh_rate = vfreq + 60; + /* the vdisplay is calculated based on the aspect ratio */ if (aspect_ratio == 0) vsize = (hsize * 10) / 16; else if (aspect_ratio == 1) @@ -267,9 +536,30 @@ struct drm_display_mode *drm_mode_std(struct drm_device *dev, vsize = (hsize * 4) / 5; else vsize = (hsize * 9) / 16; - - drm_mode_set_name(mode); - + /* HDTV hack */ + if (hsize == 1360 && vsize == 765 && vrefresh_rate == 60) { + mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); + mode->hdisplay = 1366; + mode->vsync_start = mode->vsync_start - 1; + mode->vsync_end = mode->vsync_end - 1; + return mode; + } + mode = NULL; + /* check whether it can be found in default mode table */ + mode = drm_find_dmt(dev, hsize, vsize, vrefresh_rate); + if (mode) + return mode; + + switch (timing_level) { + case LEVEL_DMT: + break; + case LEVEL_GTF: + mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); + break; + case LEVEL_CVT: + mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); + break; + } return mode; } @@ -451,6 +741,19 @@ static int add_established_modes(struct drm_connector *connector, struct edid *e return modes; } +/** + * stanard_timing_level - get std. timing level(CVT/GTF/DMT) + * @edid: EDID block to scan + */ +static int standard_timing_level(struct edid *edid) +{ + if (edid->revision >= 2) { + if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) + return LEVEL_CVT; + return LEVEL_GTF; + } + return LEVEL_DMT; +} /** * add_standard_modes - get std. modes from EDID and add them @@ -463,6 +766,9 @@ static int add_standard_modes(struct drm_connector *connector, struct edid *edid { struct drm_device *dev = connector->dev; int i, modes = 0; + int timing_level; + + timing_level = standard_timing_level(edid); for (i = 0; i < EDID_STD_TIMINGS; i++) { struct std_timing *t = &edid->standard_timings[i]; @@ -472,7 +778,8 @@ static int add_standard_modes(struct drm_connector *connector, struct edid *edid if (t->hsize == 1 && t->vfreq_aspect == 1) continue; - newmode = drm_mode_std(dev, &edid->standard_timings[i]); + newmode = drm_mode_std(dev, &edid->standard_timings[i], + timing_level); if (newmode) { drm_mode_probed_add(connector, newmode); modes++; @@ -496,6 +803,9 @@ static int add_detailed_info(struct drm_connector *connector, { struct drm_device *dev = connector->dev; int i, j, modes = 0; + int timing_level; + + timing_level = standard_timing_level(edid); for (i = 0; i < EDID_DETAILED_TIMINGS; i++) { struct detailed_timing *timing = &edid->detailed_timings[i]; @@ -525,7 +835,8 @@ static int add_detailed_info(struct drm_connector *connector, struct drm_display_mode *newmode; std = &data->data.timings[j]; - newmode = drm_mode_std(dev, std); + newmode = drm_mode_std(dev, std, + timing_level); if (newmode) { drm_mode_probed_add(connector, newmode); modes++; @@ -551,6 +862,122 @@ static int add_detailed_info(struct drm_connector *connector, return modes; } +/** + * add_detailed_mode_eedid - get detailed mode info from addtional timing + * EDID block + * @connector: attached connector + * @edid: EDID block to scan(It is only to get addtional timing EDID block) + * @quirks: quirks to apply + * + * Some of the detailed timing sections may contain mode information. Grab + * it and add it to the list. + */ +static int add_detailed_info_eedid(struct drm_connector *connector, + struct edid *edid, u32 quirks) +{ + struct drm_device *dev = connector->dev; + int i, j, modes = 0; + char *edid_ext = NULL; + struct detailed_timing *timing; + struct detailed_non_pixel *data; + struct drm_display_mode *newmode; + int edid_ext_num; + int start_offset, end_offset; + int timing_level; + + if (edid->version == 1 && edid->revision < 3) { + /* If the EDID version is less than 1.3, there is no + * extension EDID. + */ + return 0; + } + if (!edid->extensions) { + /* if there is no extension EDID, it is unnecessary to + * parse the E-EDID to get detailed info + */ + return 0; + } + + /* Chose real EDID extension number */ + edid_ext_num = edid->extensions > MAX_EDID_EXT_NUM ? + MAX_EDID_EXT_NUM : edid->extensions; + + /* Find CEA extension */ + for (i = 0; i < edid_ext_num; i++) { + edid_ext = (char *)edid + EDID_LENGTH * (i + 1); + /* This block is CEA extension */ + if (edid_ext[0] == 0x02) + break; + } + + if (i == edid_ext_num) { + /* if there is no additional timing EDID block, return */ + return 0; + } + + /* Get the start offset of detailed timing block */ + start_offset = edid_ext[2]; + if (start_offset == 0) { + /* If the start_offset is zero, it means that neither detailed + * info nor data block exist. In such case it is also + * unnecessary to parse the detailed timing info. + */ + return 0; + } + + timing_level = standard_timing_level(edid); + end_offset = EDID_LENGTH; + end_offset -= sizeof(struct detailed_timing); + for (i = start_offset; i < end_offset; + i += sizeof(struct detailed_timing)) { + timing = (struct detailed_timing *)(edid_ext + i); + data = &timing->data.other_data; + /* Detailed mode timing */ + if (timing->pixel_clock) { + newmode = drm_mode_detailed(dev, edid, timing, quirks); + if (!newmode) + continue; + + drm_mode_probed_add(connector, newmode); + + modes++; + continue; + } + + /* Other timing or info */ + switch (data->type) { + case EDID_DETAIL_MONITOR_SERIAL: + break; + case EDID_DETAIL_MONITOR_STRING: + break; + case EDID_DETAIL_MONITOR_RANGE: + /* Get monitor range data */ + break; + case EDID_DETAIL_MONITOR_NAME: + break; + case EDID_DETAIL_MONITOR_CPDATA: + break; + case EDID_DETAIL_STD_MODES: + /* Five modes per detailed section */ + for (j = 0; j < 5; i++) { + struct std_timing *std; + struct drm_display_mode *newmode; + + std = &data->data.timings[j]; + newmode = drm_mode_std(dev, std, timing_level); + if (newmode) { + drm_mode_probed_add(connector, newmode); + modes++; + } + } + break; + default: + break; + } + } + + return modes; +} #define DDC_ADDR 0x50 /** @@ -584,7 +1011,6 @@ int drm_do_probe_ddc_edid(struct i2c_adapter *adapter, if (i2c_transfer(adapter, msgs, 2) == 2) return 0; - dev_info(&adapter->dev, "unable to read EDID block.\n"); return -1; } EXPORT_SYMBOL(drm_do_probe_ddc_edid); @@ -597,8 +1023,6 @@ static int drm_ddc_read_edid(struct drm_connector *connector, ret = drm_do_probe_ddc_edid(adapter, buf, len); if (ret != 0) { - dev_info(&connector->dev->pdev->dev, "%s: no EDID data\n", - drm_get_connector_name(connector)); goto end; } if (!edid_is_valid((struct edid *)buf)) { @@ -610,7 +1034,6 @@ end: return ret; } -#define MAX_EDID_EXT_NUM 4 /** * drm_get_edid - get EDID data, if available * @connector: connector we're probing @@ -763,6 +1186,7 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) num_modes += add_established_modes(connector, edid); num_modes += add_standard_modes(connector, edid); num_modes += add_detailed_info(connector, edid, quirks); + num_modes += add_detailed_info_eedid(connector, edid, quirks); if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) edid_fixup_preferred(connector, quirks); @@ -788,3 +1212,49 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) return num_modes; } EXPORT_SYMBOL(drm_add_edid_modes); + +/** + * drm_add_modes_noedid - add modes for the connectors without EDID + * @connector: connector we're probing + * @hdisplay: the horizontal display limit + * @vdisplay: the vertical display limit + * + * Add the specified modes to the connector's mode list. Only when the + * hdisplay/vdisplay is not beyond the given limit, it will be added. + * + * Return number of modes added or 0 if we couldn't find any. + */ +int drm_add_modes_noedid(struct drm_connector *connector, + int hdisplay, int vdisplay) +{ + int i, count, num_modes = 0; + struct drm_display_mode *mode, *ptr; + struct drm_device *dev = connector->dev; + + count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); + if (hdisplay < 0) + hdisplay = 0; + if (vdisplay < 0) + vdisplay = 0; + + for (i = 0; i < count; i++) { + ptr = &drm_dmt_modes[i]; + if (hdisplay && vdisplay) { + /* + * Only when two are valid, they will be used to check + * whether the mode should be added to the mode list of + * the connector. + */ + if (ptr->hdisplay > hdisplay || + ptr->vdisplay > vdisplay) + continue; + } + mode = drm_mode_duplicate(dev, ptr); + if (mode) { + drm_mode_probed_add(connector, mode); + num_modes++; + } + } + return num_modes; +} +EXPORT_SYMBOL(drm_add_modes_noedid); diff --git a/drivers/gpu/drm/drm_encoder_slave.c b/drivers/gpu/drm/drm_encoder_slave.c new file mode 100644 index 000000000000..f0184696edf3 --- /dev/null +++ b/drivers/gpu/drm/drm_encoder_slave.c @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2009 Francisco Jerez. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "drm_encoder_slave.h" + +/** + * drm_i2c_encoder_init - Initialize an I2C slave encoder + * @dev: DRM device. + * @encoder: Encoder to be attached to the I2C device. You aren't + * required to have called drm_encoder_init() before. + * @adap: I2C adapter that will be used to communicate with + * the device. + * @info: Information that will be used to create the I2C device. + * Required fields are @addr and @type. + * + * Create an I2C device on the specified bus (the module containing its + * driver is transparently loaded) and attach it to the specified + * &drm_encoder_slave. The @slave_funcs field will be initialized with + * the hooks provided by the slave driver. + * + * Returns 0 on success or a negative errno on failure, in particular, + * -ENODEV is returned when no matching driver is found. + */ +int drm_i2c_encoder_init(struct drm_device *dev, + struct drm_encoder_slave *encoder, + struct i2c_adapter *adap, + const struct i2c_board_info *info) +{ + char modalias[sizeof(I2C_MODULE_PREFIX) + + I2C_NAME_SIZE]; + struct module *module = NULL; + struct i2c_client *client; + struct drm_i2c_encoder_driver *encoder_drv; + int err = 0; + + snprintf(modalias, sizeof(modalias), + "%s%s", I2C_MODULE_PREFIX, info->type); + request_module(modalias); + + client = i2c_new_device(adap, info); + if (!client) { + err = -ENOMEM; + goto fail; + } + + if (!client->driver) { + err = -ENODEV; + goto fail_unregister; + } + + module = client->driver->driver.owner; + if (!try_module_get(module)) { + err = -ENODEV; + goto fail_unregister; + } + + encoder->bus_priv = client; + + encoder_drv = to_drm_i2c_encoder_driver(client->driver); + + err = encoder_drv->encoder_init(client, dev, encoder); + if (err) + goto fail_unregister; + + return 0; + +fail_unregister: + i2c_unregister_device(client); + module_put(module); +fail: + return err; +} +EXPORT_SYMBOL(drm_i2c_encoder_init); + +/** + * drm_i2c_encoder_destroy - Unregister the I2C device backing an encoder + * @drm_encoder: Encoder to be unregistered. + * + * This should be called from the @destroy method of an I2C slave + * encoder driver once I2C access is no longer needed. + */ +void drm_i2c_encoder_destroy(struct drm_encoder *drm_encoder) +{ + struct drm_encoder_slave *encoder = to_encoder_slave(drm_encoder); + struct i2c_client *client = drm_i2c_encoder_get_client(drm_encoder); + struct module *module = client->driver->driver.owner; + + i2c_unregister_device(client); + encoder->bus_priv = NULL; + + module_put(module); +} +EXPORT_SYMBOL(drm_i2c_encoder_destroy); diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c new file mode 100644 index 000000000000..2c4671314884 --- /dev/null +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -0,0 +1,707 @@ +/* + * Copyright (c) 2006-2009 Red Hat Inc. + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * + * DRM framebuffer helper functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Dave Airlie + * Jesse Barnes + */ +#include +#include +#include "drmP.h" +#include "drm_crtc.h" +#include "drm_fb_helper.h" +#include "drm_crtc_helper.h" + +MODULE_AUTHOR("David Airlie, Jesse Barnes"); +MODULE_DESCRIPTION("DRM KMS helper"); +MODULE_LICENSE("GPL and additional rights"); + +static LIST_HEAD(kernel_fb_helper_list); + +bool drm_fb_helper_force_kernel_mode(void) +{ + int i = 0; + bool ret, error = false; + struct drm_fb_helper *helper; + + if (list_empty(&kernel_fb_helper_list)) + return false; + + list_for_each_entry(helper, &kernel_fb_helper_list, kernel_fb_list) { + for (i = 0; i < helper->crtc_count; i++) { + struct drm_mode_set *mode_set = &helper->crtc_info[i].mode_set; + ret = drm_crtc_helper_set_config(mode_set); + if (ret) + error = true; + } + } + return error; +} + +int drm_fb_helper_panic(struct notifier_block *n, unsigned long ununsed, + void *panic_str) +{ + DRM_ERROR("panic occurred, switching back to text console\n"); + return drm_fb_helper_force_kernel_mode(); + return 0; +} +EXPORT_SYMBOL(drm_fb_helper_panic); + +static struct notifier_block paniced = { + .notifier_call = drm_fb_helper_panic, +}; + +/** + * drm_fb_helper_restore - restore the framebuffer console (kernel) config + * + * Restore's the kernel's fbcon mode, used for lastclose & panic paths. + */ +void drm_fb_helper_restore(void) +{ + bool ret; + ret = drm_fb_helper_force_kernel_mode(); + if (ret == true) + DRM_ERROR("Failed to restore crtc configuration\n"); +} +EXPORT_SYMBOL(drm_fb_helper_restore); + +static void drm_fb_helper_restore_work_fn(struct work_struct *ignored) +{ + drm_fb_helper_restore(); +} +static DECLARE_WORK(drm_fb_helper_restore_work, drm_fb_helper_restore_work_fn); + +static void drm_fb_helper_sysrq(int dummy1, struct tty_struct *dummy3) +{ + schedule_work(&drm_fb_helper_restore_work); +} + +static struct sysrq_key_op sysrq_drm_fb_helper_restore_op = { + .handler = drm_fb_helper_sysrq, + .help_msg = "force-fb(V)", + .action_msg = "Restore framebuffer console", +}; + +static void drm_fb_helper_on(struct fb_info *info) +{ + struct drm_fb_helper *fb_helper = info->par; + struct drm_device *dev = fb_helper->dev; + struct drm_crtc *crtc; + struct drm_encoder *encoder; + int i; + + /* + * For each CRTC in this fb, turn the crtc on then, + * find all associated encoders and turn them on. + */ + for (i = 0; i < fb_helper->crtc_count; i++) { + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + struct drm_crtc_helper_funcs *crtc_funcs = + crtc->helper_private; + + /* Only mess with CRTCs in this fb */ + if (crtc->base.id != fb_helper->crtc_info[i].crtc_id || + !crtc->enabled) + continue; + + mutex_lock(&dev->mode_config.mutex); + crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); + mutex_unlock(&dev->mode_config.mutex); + + /* Found a CRTC on this fb, now find encoders */ + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + if (encoder->crtc == crtc) { + struct drm_encoder_helper_funcs *encoder_funcs; + + encoder_funcs = encoder->helper_private; + mutex_lock(&dev->mode_config.mutex); + encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); + mutex_unlock(&dev->mode_config.mutex); + } + } + } + } +} + +static void drm_fb_helper_off(struct fb_info *info, int dpms_mode) +{ + struct drm_fb_helper *fb_helper = info->par; + struct drm_device *dev = fb_helper->dev; + struct drm_crtc *crtc; + struct drm_encoder *encoder; + int i; + + /* + * For each CRTC in this fb, find all associated encoders + * and turn them off, then turn off the CRTC. + */ + for (i = 0; i < fb_helper->crtc_count; i++) { + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + struct drm_crtc_helper_funcs *crtc_funcs = + crtc->helper_private; + + /* Only mess with CRTCs in this fb */ + if (crtc->base.id != fb_helper->crtc_info[i].crtc_id || + !crtc->enabled) + continue; + + /* Found a CRTC on this fb, now find encoders */ + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + if (encoder->crtc == crtc) { + struct drm_encoder_helper_funcs *encoder_funcs; + + encoder_funcs = encoder->helper_private; + mutex_lock(&dev->mode_config.mutex); + encoder_funcs->dpms(encoder, dpms_mode); + mutex_unlock(&dev->mode_config.mutex); + } + } + if (dpms_mode == DRM_MODE_DPMS_OFF) { + mutex_lock(&dev->mode_config.mutex); + crtc_funcs->dpms(crtc, dpms_mode); + mutex_unlock(&dev->mode_config.mutex); + } + } + } +} + +int drm_fb_helper_blank(int blank, struct fb_info *info) +{ + switch (blank) { + case FB_BLANK_UNBLANK: + drm_fb_helper_on(info); + break; + case FB_BLANK_NORMAL: + drm_fb_helper_off(info, DRM_MODE_DPMS_STANDBY); + break; + case FB_BLANK_HSYNC_SUSPEND: + drm_fb_helper_off(info, DRM_MODE_DPMS_STANDBY); + break; + case FB_BLANK_VSYNC_SUSPEND: + drm_fb_helper_off(info, DRM_MODE_DPMS_SUSPEND); + break; + case FB_BLANK_POWERDOWN: + drm_fb_helper_off(info, DRM_MODE_DPMS_OFF); + break; + } + return 0; +} +EXPORT_SYMBOL(drm_fb_helper_blank); + +static void drm_fb_helper_crtc_free(struct drm_fb_helper *helper) +{ + int i; + + for (i = 0; i < helper->crtc_count; i++) + kfree(helper->crtc_info[i].mode_set.connectors); + kfree(helper->crtc_info); +} + +int drm_fb_helper_init_crtc_count(struct drm_fb_helper *helper, int crtc_count, int max_conn_count) +{ + struct drm_device *dev = helper->dev; + struct drm_crtc *crtc; + int ret = 0; + int i; + + helper->crtc_info = kcalloc(crtc_count, sizeof(struct drm_fb_helper_crtc), GFP_KERNEL); + if (!helper->crtc_info) + return -ENOMEM; + + helper->crtc_count = crtc_count; + + for (i = 0; i < crtc_count; i++) { + helper->crtc_info[i].mode_set.connectors = + kcalloc(max_conn_count, + sizeof(struct drm_connector *), + GFP_KERNEL); + + if (!helper->crtc_info[i].mode_set.connectors) { + ret = -ENOMEM; + goto out_free; + } + helper->crtc_info[i].mode_set.num_connectors = 0; + } + + i = 0; + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + helper->crtc_info[i].crtc_id = crtc->base.id; + helper->crtc_info[i].mode_set.crtc = crtc; + i++; + } + helper->conn_limit = max_conn_count; + return 0; +out_free: + drm_fb_helper_crtc_free(helper); + return -ENOMEM; +} +EXPORT_SYMBOL(drm_fb_helper_init_crtc_count); + +int drm_fb_helper_setcolreg(unsigned regno, + unsigned red, + unsigned green, + unsigned blue, + unsigned transp, + struct fb_info *info) +{ + struct drm_fb_helper *fb_helper = info->par; + struct drm_device *dev = fb_helper->dev; + struct drm_crtc *crtc; + int i; + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + struct drm_framebuffer *fb = fb_helper->fb; + + for (i = 0; i < fb_helper->crtc_count; i++) { + if (crtc->base.id == fb_helper->crtc_info[i].crtc_id) + break; + } + if (i == fb_helper->crtc_count) + continue; + + if (regno > 255) + return 1; + + if (fb->depth == 8) { + fb_helper->funcs->gamma_set(crtc, red, green, blue, regno); + return 0; + } + + if (regno < 16) { + switch (fb->depth) { + case 15: + fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) | + ((green & 0xf800) >> 6) | + ((blue & 0xf800) >> 11); + break; + case 16: + fb->pseudo_palette[regno] = (red & 0xf800) | + ((green & 0xfc00) >> 5) | + ((blue & 0xf800) >> 11); + break; + case 24: + case 32: + fb->pseudo_palette[regno] = + (((red >> 8) & 0xff) << info->var.red.offset) | + (((green >> 8) & 0xff) << info->var.green.offset) | + (((blue >> 8) & 0xff) << info->var.blue.offset); + break; + } + } + } + return 0; +} +EXPORT_SYMBOL(drm_fb_helper_setcolreg); + +int drm_fb_helper_check_var(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + struct drm_fb_helper *fb_helper = info->par; + struct drm_framebuffer *fb = fb_helper->fb; + int depth; + + if (var->pixclock == -1 || !var->pixclock) + return -EINVAL; + + /* Need to resize the fb object !!! */ + if (var->xres > fb->width || var->yres > fb->height) { + DRM_ERROR("Requested width/height is greater than current fb " + "object %dx%d > %dx%d\n", var->xres, var->yres, + fb->width, fb->height); + DRM_ERROR("Need resizing code.\n"); + return -EINVAL; + } + + switch (var->bits_per_pixel) { + case 16: + depth = (var->green.length == 6) ? 16 : 15; + break; + case 32: + depth = (var->transp.length > 0) ? 32 : 24; + break; + default: + depth = var->bits_per_pixel; + break; + } + + switch (depth) { + case 8: + var->red.offset = 0; + var->green.offset = 0; + var->blue.offset = 0; + var->red.length = 8; + var->green.length = 8; + var->blue.length = 8; + var->transp.length = 0; + var->transp.offset = 0; + break; + case 15: + var->red.offset = 10; + var->green.offset = 5; + var->blue.offset = 0; + var->red.length = 5; + var->green.length = 5; + var->blue.length = 5; + var->transp.length = 1; + var->transp.offset = 15; + break; + case 16: + var->red.offset = 11; + var->green.offset = 5; + var->blue.offset = 0; + var->red.length = 5; + var->green.length = 6; + var->blue.length = 5; + var->transp.length = 0; + var->transp.offset = 0; + break; + case 24: + var->red.offset = 16; + var->green.offset = 8; + var->blue.offset = 0; + var->red.length = 8; + var->green.length = 8; + var->blue.length = 8; + var->transp.length = 0; + var->transp.offset = 0; + break; + case 32: + var->red.offset = 16; + var->green.offset = 8; + var->blue.offset = 0; + var->red.length = 8; + var->green.length = 8; + var->blue.length = 8; + var->transp.length = 8; + var->transp.offset = 24; + break; + default: + return -EINVAL; + } + return 0; +} +EXPORT_SYMBOL(drm_fb_helper_check_var); + +/* this will let fbcon do the mode init */ +int drm_fb_helper_set_par(struct fb_info *info) +{ + struct drm_fb_helper *fb_helper = info->par; + struct drm_device *dev = fb_helper->dev; + struct fb_var_screeninfo *var = &info->var; + struct drm_crtc *crtc; + int ret; + int i; + + if (var->pixclock != -1) { + DRM_ERROR("PIXEL CLCOK SET\n"); + return -EINVAL; + } + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + + for (i = 0; i < fb_helper->crtc_count; i++) { + if (crtc->base.id == fb_helper->crtc_info[i].crtc_id) + break; + } + if (i == fb_helper->crtc_count) + continue; + + if (crtc->fb == fb_helper->crtc_info[i].mode_set.fb) { + mutex_lock(&dev->mode_config.mutex); + ret = crtc->funcs->set_config(&fb_helper->crtc_info->mode_set); + mutex_unlock(&dev->mode_config.mutex); + if (ret) + return ret; + } + } + return 0; +} +EXPORT_SYMBOL(drm_fb_helper_set_par); + +int drm_fb_helper_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + struct drm_fb_helper *fb_helper = info->par; + struct drm_device *dev = fb_helper->dev; + struct drm_mode_set *modeset; + struct drm_crtc *crtc; + int ret = 0; + int i; + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + for (i = 0; i < fb_helper->crtc_count; i++) { + if (crtc->base.id == fb_helper->crtc_info[i].crtc_id) + break; + } + + if (i == fb_helper->crtc_count) + continue; + + modeset = &fb_helper->crtc_info[i].mode_set; + + modeset->x = var->xoffset; + modeset->y = var->yoffset; + + if (modeset->num_connectors) { + mutex_lock(&dev->mode_config.mutex); + ret = crtc->funcs->set_config(modeset); + mutex_unlock(&dev->mode_config.mutex); + if (!ret) { + info->var.xoffset = var->xoffset; + info->var.yoffset = var->yoffset; + } + } + } + return ret; +} +EXPORT_SYMBOL(drm_fb_helper_pan_display); + +int drm_fb_helper_single_fb_probe(struct drm_device *dev, + int (*fb_create)(struct drm_device *dev, + uint32_t fb_width, + uint32_t fb_height, + uint32_t surface_width, + uint32_t surface_height, + struct drm_framebuffer **fb_ptr)) +{ + struct drm_crtc *crtc; + struct drm_connector *connector; + unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1; + unsigned int surface_width = 0, surface_height = 0; + int new_fb = 0; + int crtc_count = 0; + int ret, i, conn_count = 0; + struct fb_info *info; + struct drm_framebuffer *fb; + struct drm_mode_set *modeset = NULL; + struct drm_fb_helper *fb_helper; + + /* first up get a count of crtcs now in use and new min/maxes width/heights */ + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + if (drm_helper_crtc_in_use(crtc)) { + if (crtc->desired_mode) { + if (crtc->desired_mode->hdisplay < fb_width) + fb_width = crtc->desired_mode->hdisplay; + + if (crtc->desired_mode->vdisplay < fb_height) + fb_height = crtc->desired_mode->vdisplay; + + if (crtc->desired_mode->hdisplay > surface_width) + surface_width = crtc->desired_mode->hdisplay; + + if (crtc->desired_mode->vdisplay > surface_height) + surface_height = crtc->desired_mode->vdisplay; + } + crtc_count++; + } + } + + if (crtc_count == 0 || fb_width == -1 || fb_height == -1) { + /* hmm everyone went away - assume VGA cable just fell out + and will come back later. */ + return 0; + } + + /* do we have an fb already? */ + if (list_empty(&dev->mode_config.fb_kernel_list)) { + ret = (*fb_create)(dev, fb_width, fb_height, surface_width, + surface_height, &fb); + if (ret) + return -EINVAL; + new_fb = 1; + } else { + fb = list_first_entry(&dev->mode_config.fb_kernel_list, + struct drm_framebuffer, filp_head); + + /* if someone hotplugs something bigger than we have already allocated, we are pwned. + As really we can't resize an fbdev that is in the wild currently due to fbdev + not really being designed for the lower layers moving stuff around under it. + - so in the grand style of things - punt. */ + if ((fb->width < surface_width) || + (fb->height < surface_height)) { + DRM_ERROR("Framebuffer not large enough to scale console onto.\n"); + return -EINVAL; + } + } + + info = fb->fbdev; + fb_helper = info->par; + + crtc_count = 0; + /* okay we need to setup new connector sets in the crtcs */ + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + modeset = &fb_helper->crtc_info[crtc_count].mode_set; + modeset->fb = fb; + conn_count = 0; + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + if (connector->encoder) + if (connector->encoder->crtc == modeset->crtc) { + modeset->connectors[conn_count] = connector; + conn_count++; + if (conn_count > fb_helper->conn_limit) + BUG(); + } + } + + for (i = conn_count; i < fb_helper->conn_limit; i++) + modeset->connectors[i] = NULL; + + modeset->crtc = crtc; + crtc_count++; + + modeset->num_connectors = conn_count; + if (modeset->crtc->desired_mode) { + if (modeset->mode) + drm_mode_destroy(dev, modeset->mode); + modeset->mode = drm_mode_duplicate(dev, + modeset->crtc->desired_mode); + } + } + fb_helper->crtc_count = crtc_count; + fb_helper->fb = fb; + + if (new_fb) { + info->var.pixclock = -1; + if (register_framebuffer(info) < 0) + return -EINVAL; + } else { + drm_fb_helper_set_par(info); + } + printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, + info->fix.id); + + /* Switch back to kernel console on panic */ + /* multi card linked list maybe */ + if (list_empty(&kernel_fb_helper_list)) { + printk(KERN_INFO "registered panic notifier\n"); + atomic_notifier_chain_register(&panic_notifier_list, + &paniced); + register_sysrq_key('v', &sysrq_drm_fb_helper_restore_op); + } + list_add(&fb_helper->kernel_fb_list, &kernel_fb_helper_list); + return 0; +} +EXPORT_SYMBOL(drm_fb_helper_single_fb_probe); + +void drm_fb_helper_free(struct drm_fb_helper *helper) +{ + list_del(&helper->kernel_fb_list); + if (list_empty(&kernel_fb_helper_list)) { + printk(KERN_INFO "unregistered panic notifier\n"); + atomic_notifier_chain_unregister(&panic_notifier_list, + &paniced); + unregister_sysrq_key('v', &sysrq_drm_fb_helper_restore_op); + } + drm_fb_helper_crtc_free(helper); +} +EXPORT_SYMBOL(drm_fb_helper_free); + +void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch) +{ + info->fix.type = FB_TYPE_PACKED_PIXELS; + info->fix.visual = FB_VISUAL_TRUECOLOR; + info->fix.type_aux = 0; + info->fix.xpanstep = 1; /* doing it in hw */ + info->fix.ypanstep = 1; /* doing it in hw */ + info->fix.ywrapstep = 0; + info->fix.accel = FB_ACCEL_NONE; + info->fix.type_aux = 0; + + info->fix.line_length = pitch; + return; +} +EXPORT_SYMBOL(drm_fb_helper_fill_fix); + +void drm_fb_helper_fill_var(struct fb_info *info, struct drm_framebuffer *fb, + uint32_t fb_width, uint32_t fb_height) +{ + info->pseudo_palette = fb->pseudo_palette; + info->var.xres_virtual = fb->width; + info->var.yres_virtual = fb->height; + info->var.bits_per_pixel = fb->bits_per_pixel; + info->var.xoffset = 0; + info->var.yoffset = 0; + info->var.activate = FB_ACTIVATE_NOW; + info->var.height = -1; + info->var.width = -1; + + switch (fb->depth) { + case 8: + info->var.red.offset = 0; + info->var.green.offset = 0; + info->var.blue.offset = 0; + info->var.red.length = 8; /* 8bit DAC */ + info->var.green.length = 8; + info->var.blue.length = 8; + info->var.transp.offset = 0; + info->var.transp.length = 0; + break; + case 15: + info->var.red.offset = 10; + info->var.green.offset = 5; + info->var.blue.offset = 0; + info->var.red.length = 5; + info->var.green.length = 5; + info->var.blue.length = 5; + info->var.transp.offset = 15; + info->var.transp.length = 1; + break; + case 16: + info->var.red.offset = 11; + info->var.green.offset = 5; + info->var.blue.offset = 0; + info->var.red.length = 5; + info->var.green.length = 6; + info->var.blue.length = 5; + info->var.transp.offset = 0; + break; + case 24: + info->var.red.offset = 16; + info->var.green.offset = 8; + info->var.blue.offset = 0; + info->var.red.length = 8; + info->var.green.length = 8; + info->var.blue.length = 8; + info->var.transp.offset = 0; + info->var.transp.length = 0; + break; + case 32: + info->var.red.offset = 16; + info->var.green.offset = 8; + info->var.blue.offset = 0; + info->var.red.length = 8; + info->var.green.length = 8; + info->var.blue.length = 8; + info->var.transp.offset = 24; + info->var.transp.length = 8; + break; + default: + break; + } + + info->var.xres = fb_width; + info->var.yres = fb_height; +} +EXPORT_SYMBOL(drm_fb_helper_fill_var); diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index ffe8f4394d50..230c9ffdd5e9 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -164,7 +164,7 @@ EXPORT_SYMBOL(drm_gem_object_alloc); * Removes the mapping from handle to filp for this object. */ static int -drm_gem_handle_delete(struct drm_file *filp, int handle) +drm_gem_handle_delete(struct drm_file *filp, u32 handle) { struct drm_device *dev; struct drm_gem_object *obj; @@ -207,7 +207,7 @@ drm_gem_handle_delete(struct drm_file *filp, int handle) int drm_gem_handle_create(struct drm_file *file_priv, struct drm_gem_object *obj, - int *handlep) + u32 *handlep) { int ret; @@ -221,7 +221,7 @@ again: /* do the allocation under our spinlock */ spin_lock(&file_priv->table_lock); - ret = idr_get_new_above(&file_priv->object_idr, obj, 1, handlep); + ret = idr_get_new_above(&file_priv->object_idr, obj, 1, (int *)handlep); spin_unlock(&file_priv->table_lock); if (ret == -EAGAIN) goto again; @@ -237,7 +237,7 @@ EXPORT_SYMBOL(drm_gem_handle_create); /** Returns a reference to the object named by the handle. */ struct drm_gem_object * drm_gem_object_lookup(struct drm_device *dev, struct drm_file *filp, - int handle) + u32 handle) { struct drm_gem_object *obj; @@ -344,7 +344,7 @@ drm_gem_open_ioctl(struct drm_device *dev, void *data, struct drm_gem_open *args = data; struct drm_gem_object *obj; int ret; - int handle; + u32 handle; if (!(dev->driver->driver_features & DRIVER_GEM)) return -ENODEV; @@ -539,7 +539,6 @@ int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) vma->vm_flags |= VM_RESERVED | VM_IO | VM_PFNMAP | VM_DONTEXPAND; vma->vm_ops = obj->dev->driver->gem_vm_ops; vma->vm_private_data = map->handle; - /* FIXME: use pgprot_writecombine when available */ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); /* Take a ref for this mapping of the object, so that the fault diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c index f85aaf21e783..0a6f0b3bdc78 100644 --- a/drivers/gpu/drm/drm_irq.c +++ b/drivers/gpu/drm/drm_irq.c @@ -37,6 +37,7 @@ #include /* For task queue support */ +#include /** * Get interrupt from bus id. * @@ -171,6 +172,26 @@ err: } EXPORT_SYMBOL(drm_vblank_init); +static void drm_irq_vgaarb_nokms(void *cookie, bool state) +{ + struct drm_device *dev = cookie; + + if (dev->driver->vgaarb_irq) { + dev->driver->vgaarb_irq(dev, state); + return; + } + + if (!dev->irq_enabled) + return; + + if (state) + dev->driver->irq_uninstall(dev); + else { + dev->driver->irq_preinstall(dev); + dev->driver->irq_postinstall(dev); + } +} + /** * Install IRQ handler. * @@ -231,6 +252,9 @@ int drm_irq_install(struct drm_device *dev) return ret; } + if (!drm_core_check_feature(dev, DRIVER_MODESET)) + vga_client_register(dev->pdev, (void *)dev, drm_irq_vgaarb_nokms, NULL); + /* After installing handler */ ret = dev->driver->irq_postinstall(dev); if (ret < 0) { @@ -279,6 +303,9 @@ int drm_irq_uninstall(struct drm_device * dev) DRM_DEBUG("irq=%d\n", dev->pdev->irq); + if (!drm_core_check_feature(dev, DRIVER_MODESET)) + vga_client_register(dev->pdev, NULL, NULL, NULL); + dev->driver->irq_uninstall(dev); free_irq(dev->pdev->irq, dev); diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c index 3e47869d6dae..c861d80fd779 100644 --- a/drivers/gpu/drm/drm_mm.c +++ b/drivers/gpu/drm/drm_mm.c @@ -44,6 +44,7 @@ #include "drmP.h" #include "drm_mm.h" #include +#include #define MM_UNUSED_TARGET 4 @@ -370,3 +371,23 @@ void drm_mm_takedown(struct drm_mm * mm) BUG_ON(mm->num_unused != 0); } EXPORT_SYMBOL(drm_mm_takedown); + +#if defined(CONFIG_DEBUG_FS) +int drm_mm_dump_table(struct seq_file *m, struct drm_mm *mm) +{ + struct drm_mm_node *entry; + int total_used = 0, total_free = 0, total = 0; + + list_for_each_entry(entry, &mm->ml_entry, ml_entry) { + seq_printf(m, "0x%08lx-0x%08lx: 0x%08lx: %s\n", entry->start, entry->start + entry->size, entry->size, entry->free ? "free" : "used"); + total += entry->size; + if (entry->free) + total_free += entry->size; + else + total_used += entry->size; + } + seq_printf(m, "total: %d, used %d free %d\n", total, total_free, total_used); + return 0; +} +EXPORT_SYMBOL(drm_mm_dump_table); +#endif diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index 7914097b09c6..49404ce1666e 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -8,6 +8,8 @@ * Copyright © 2007 Dave Airlie * Copyright © 2007-2008 Intel Corporation * Jesse Barnes + * Copyright 2005-2006 Luc Verhaegen + * Copyright (c) 2001, Andy Ritger aritger@nvidia.com * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -38,7 +40,6 @@ #include "drm.h" #include "drm_crtc.h" -#define DRM_MODESET_DEBUG "drm_mode" /** * drm_mode_debug_printmodeline - debug print a mode * @dev: DRM device @@ -51,8 +52,8 @@ */ void drm_mode_debug_printmodeline(struct drm_display_mode *mode) { - DRM_DEBUG_MODE(DRM_MODESET_DEBUG, - "Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x\n", + DRM_DEBUG_KMS("Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d " + "0x%x 0x%x\n", mode->base.id, mode->name, mode->vrefresh, mode->clock, mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, @@ -61,6 +62,420 @@ void drm_mode_debug_printmodeline(struct drm_display_mode *mode) } EXPORT_SYMBOL(drm_mode_debug_printmodeline); +/** + * drm_cvt_mode -create a modeline based on CVT algorithm + * @dev: DRM device + * @hdisplay: hdisplay size + * @vdisplay: vdisplay size + * @vrefresh : vrefresh rate + * @reduced : Whether the GTF calculation is simplified + * @interlaced:Whether the interlace is supported + * + * LOCKING: + * none. + * + * return the modeline based on CVT algorithm + * + * This function is called to generate the modeline based on CVT algorithm + * according to the hdisplay, vdisplay, vrefresh. + * It is based from the VESA(TM) Coordinated Video Timing Generator by + * Graham Loveridge April 9, 2003 available at + * http://www.vesa.org/public/CVT/CVTd6r1.xls + * + * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c. + * What I have done is to translate it by using integer calculation. + */ +#define HV_FACTOR 1000 +struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay, + int vdisplay, int vrefresh, + bool reduced, bool interlaced) +{ + /* 1) top/bottom margin size (% of height) - default: 1.8, */ +#define CVT_MARGIN_PERCENTAGE 18 + /* 2) character cell horizontal granularity (pixels) - default 8 */ +#define CVT_H_GRANULARITY 8 + /* 3) Minimum vertical porch (lines) - default 3 */ +#define CVT_MIN_V_PORCH 3 + /* 4) Minimum number of vertical back porch lines - default 6 */ +#define CVT_MIN_V_BPORCH 6 + /* Pixel Clock step (kHz) */ +#define CVT_CLOCK_STEP 250 + struct drm_display_mode *drm_mode; + bool margins = false; + unsigned int vfieldrate, hperiod; + int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; + int interlace; + + /* allocate the drm_display_mode structure. If failure, we will + * return directly + */ + drm_mode = drm_mode_create(dev); + if (!drm_mode) + return NULL; + + /* the CVT default refresh rate is 60Hz */ + if (!vrefresh) + vrefresh = 60; + + /* the required field fresh rate */ + if (interlaced) + vfieldrate = vrefresh * 2; + else + vfieldrate = vrefresh; + + /* horizontal pixels */ + hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); + + /* determine the left&right borders */ + hmargin = 0; + if (margins) { + hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; + hmargin -= hmargin % CVT_H_GRANULARITY; + } + /* find the total active pixels */ + drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; + + /* find the number of lines per field */ + if (interlaced) + vdisplay_rnd = vdisplay / 2; + else + vdisplay_rnd = vdisplay; + + /* find the top & bottom borders */ + vmargin = 0; + if (margins) + vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; + + drm_mode->vdisplay = vdisplay + 2 * vmargin; + + /* Interlaced */ + if (interlaced) + interlace = 1; + else + interlace = 0; + + /* Determine VSync Width from aspect ratio */ + if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) + vsync = 4; + else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) + vsync = 5; + else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) + vsync = 6; + else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) + vsync = 7; + else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) + vsync = 7; + else /* custom */ + vsync = 10; + + if (!reduced) { + /* simplify the GTF calculation */ + /* 4) Minimum time of vertical sync + back porch interval (µs) + * default 550.0 + */ + int tmp1, tmp2; +#define CVT_MIN_VSYNC_BP 550 + /* 3) Nominal HSync width (% of line period) - default 8 */ +#define CVT_HSYNC_PERCENTAGE 8 + unsigned int hblank_percentage; + int vsyncandback_porch, vback_porch, hblank; + + /* estimated the horizontal period */ + tmp1 = HV_FACTOR * 1000000 - + CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate; + tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 + + interlace; + hperiod = tmp1 * 2 / (tmp2 * vfieldrate); + + tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1; + /* 9. Find number of lines in sync + backporch */ + if (tmp1 < (vsync + CVT_MIN_V_PORCH)) + vsyncandback_porch = vsync + CVT_MIN_V_PORCH; + else + vsyncandback_porch = tmp1; + /* 10. Find number of lines in back porch */ + vback_porch = vsyncandback_porch - vsync; + drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + + vsyncandback_porch + CVT_MIN_V_PORCH; + /* 5) Definition of Horizontal blanking time limitation */ + /* Gradient (%/kHz) - default 600 */ +#define CVT_M_FACTOR 600 + /* Offset (%) - default 40 */ +#define CVT_C_FACTOR 40 + /* Blanking time scaling factor - default 128 */ +#define CVT_K_FACTOR 128 + /* Scaling factor weighting - default 20 */ +#define CVT_J_FACTOR 20 +#define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256) +#define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \ + CVT_J_FACTOR) + /* 12. Find ideal blanking duty cycle from formula */ + hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME * + hperiod / 1000; + /* 13. Blanking time */ + if (hblank_percentage < 20 * HV_FACTOR) + hblank_percentage = 20 * HV_FACTOR; + hblank = drm_mode->hdisplay * hblank_percentage / + (100 * HV_FACTOR - hblank_percentage); + hblank -= hblank % (2 * CVT_H_GRANULARITY); + /* 14. find the total pixes per line */ + drm_mode->htotal = drm_mode->hdisplay + hblank; + drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; + drm_mode->hsync_start = drm_mode->hsync_end - + (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; + drm_mode->hsync_start += CVT_H_GRANULARITY - + drm_mode->hsync_start % CVT_H_GRANULARITY; + /* fill the Vsync values */ + drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH; + drm_mode->vsync_end = drm_mode->vsync_start + vsync; + } else { + /* Reduced blanking */ + /* Minimum vertical blanking interval time (µs)- default 460 */ +#define CVT_RB_MIN_VBLANK 460 + /* Fixed number of clocks for horizontal sync */ +#define CVT_RB_H_SYNC 32 + /* Fixed number of clocks for horizontal blanking */ +#define CVT_RB_H_BLANK 160 + /* Fixed number of lines for vertical front porch - default 3*/ +#define CVT_RB_VFPORCH 3 + int vbilines; + int tmp1, tmp2; + /* 8. Estimate Horizontal period. */ + tmp1 = HV_FACTOR * 1000000 - + CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate; + tmp2 = vdisplay_rnd + 2 * vmargin; + hperiod = tmp1 / (tmp2 * vfieldrate); + /* 9. Find number of lines in vertical blanking */ + vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1; + /* 10. Check if vertical blanking is sufficient */ + if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH)) + vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH; + /* 11. Find total number of lines in vertical field */ + drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines; + /* 12. Find total number of pixels in a line */ + drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; + /* Fill in HSync values */ + drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; + drm_mode->hsync_start = drm_mode->hsync_end = CVT_RB_H_SYNC; + } + /* 15/13. Find pixel clock frequency (kHz for xf86) */ + drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; + drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; + /* 18/16. Find actual vertical frame frequency */ + /* ignore - just set the mode flag for interlaced */ + if (interlaced) + drm_mode->vtotal *= 2; + /* Fill the mode line name */ + drm_mode_set_name(drm_mode); + if (reduced) + drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC | + DRM_MODE_FLAG_NVSYNC); + else + drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC | + DRM_MODE_FLAG_NHSYNC); + if (interlaced) + drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; + + return drm_mode; +} +EXPORT_SYMBOL(drm_cvt_mode); + +/** + * drm_gtf_mode - create the modeline based on GTF algorithm + * + * @dev :drm device + * @hdisplay :hdisplay size + * @vdisplay :vdisplay size + * @vrefresh :vrefresh rate. + * @interlaced :whether the interlace is supported + * @margins :whether the margin is supported + * + * LOCKING. + * none. + * + * return the modeline based on GTF algorithm + * + * This function is to create the modeline based on the GTF algorithm. + * Generalized Timing Formula is derived from: + * GTF Spreadsheet by Andy Morrish (1/5/97) + * available at http://www.vesa.org + * + * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c. + * What I have done is to translate it by using integer calculation. + * I also refer to the function of fb_get_mode in the file of + * drivers/video/fbmon.c + */ +struct drm_display_mode *drm_gtf_mode(struct drm_device *dev, int hdisplay, + int vdisplay, int vrefresh, + bool interlaced, int margins) +{ + /* 1) top/bottom margin size (% of height) - default: 1.8, */ +#define GTF_MARGIN_PERCENTAGE 18 + /* 2) character cell horizontal granularity (pixels) - default 8 */ +#define GTF_CELL_GRAN 8 + /* 3) Minimum vertical porch (lines) - default 3 */ +#define GTF_MIN_V_PORCH 1 + /* width of vsync in lines */ +#define V_SYNC_RQD 3 + /* width of hsync as % of total line */ +#define H_SYNC_PERCENT 8 + /* min time of vsync + back porch (microsec) */ +#define MIN_VSYNC_PLUS_BP 550 + /* blanking formula gradient */ +#define GTF_M 600 + /* blanking formula offset */ +#define GTF_C 40 + /* blanking formula scaling factor */ +#define GTF_K 128 + /* blanking formula scaling factor */ +#define GTF_J 20 + /* C' and M' are part of the Blanking Duty Cycle computation */ +#define GTF_C_PRIME (((GTF_C - GTF_J) * GTF_K / 256) + GTF_J) +#define GTF_M_PRIME (GTF_K * GTF_M / 256) + struct drm_display_mode *drm_mode; + unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd; + int top_margin, bottom_margin; + int interlace; + unsigned int hfreq_est; + int vsync_plus_bp, vback_porch; + unsigned int vtotal_lines, vfieldrate_est, hperiod; + unsigned int vfield_rate, vframe_rate; + int left_margin, right_margin; + unsigned int total_active_pixels, ideal_duty_cycle; + unsigned int hblank, total_pixels, pixel_freq; + int hsync, hfront_porch, vodd_front_porch_lines; + unsigned int tmp1, tmp2; + + drm_mode = drm_mode_create(dev); + if (!drm_mode) + return NULL; + + /* 1. In order to give correct results, the number of horizontal + * pixels requested is first processed to ensure that it is divisible + * by the character size, by rounding it to the nearest character + * cell boundary: + */ + hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; + hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN; + + /* 2. If interlace is requested, the number of vertical lines assumed + * by the calculation must be halved, as the computation calculates + * the number of vertical lines per field. + */ + if (interlaced) + vdisplay_rnd = vdisplay / 2; + else + vdisplay_rnd = vdisplay; + + /* 3. Find the frame rate required: */ + if (interlaced) + vfieldrate_rqd = vrefresh * 2; + else + vfieldrate_rqd = vrefresh; + + /* 4. Find number of lines in Top margin: */ + top_margin = 0; + if (margins) + top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / + 1000; + /* 5. Find number of lines in bottom margin: */ + bottom_margin = top_margin; + + /* 6. If interlace is required, then set variable interlace: */ + if (interlaced) + interlace = 1; + else + interlace = 0; + + /* 7. Estimate the Horizontal frequency */ + { + tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500; + tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) * + 2 + interlace; + hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1; + } + + /* 8. Find the number of lines in V sync + back porch */ + /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */ + vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000; + vsync_plus_bp = (vsync_plus_bp + 500) / 1000; + /* 9. Find the number of lines in V back porch alone: */ + vback_porch = vsync_plus_bp - V_SYNC_RQD; + /* 10. Find the total number of lines in Vertical field period: */ + vtotal_lines = vdisplay_rnd + top_margin + bottom_margin + + vsync_plus_bp + GTF_MIN_V_PORCH; + /* 11. Estimate the Vertical field frequency: */ + vfieldrate_est = hfreq_est / vtotal_lines; + /* 12. Find the actual horizontal period: */ + hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines); + + /* 13. Find the actual Vertical field frequency: */ + vfield_rate = hfreq_est / vtotal_lines; + /* 14. Find the Vertical frame frequency: */ + if (interlaced) + vframe_rate = vfield_rate / 2; + else + vframe_rate = vfield_rate; + /* 15. Find number of pixels in left margin: */ + if (margins) + left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / + 1000; + else + left_margin = 0; + + /* 16.Find number of pixels in right margin: */ + right_margin = left_margin; + /* 17.Find total number of active pixels in image and left and right */ + total_active_pixels = hdisplay_rnd + left_margin + right_margin; + /* 18.Find the ideal blanking duty cycle from blanking duty cycle */ + ideal_duty_cycle = GTF_C_PRIME * 1000 - + (GTF_M_PRIME * 1000000 / hfreq_est); + /* 19.Find the number of pixels in the blanking time to the nearest + * double character cell: */ + hblank = total_active_pixels * ideal_duty_cycle / + (100000 - ideal_duty_cycle); + hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN); + hblank = hblank * 2 * GTF_CELL_GRAN; + /* 20.Find total number of pixels: */ + total_pixels = total_active_pixels + hblank; + /* 21.Find pixel clock frequency: */ + pixel_freq = total_pixels * hfreq_est / 1000; + /* Stage 1 computations are now complete; I should really pass + * the results to another function and do the Stage 2 computations, + * but I only need a few more values so I'll just append the + * computations here for now */ + /* 17. Find the number of pixels in the horizontal sync period: */ + hsync = H_SYNC_PERCENT * total_pixels / 100; + hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; + hsync = hsync * GTF_CELL_GRAN; + /* 18. Find the number of pixels in horizontal front porch period */ + hfront_porch = hblank / 2 - hsync; + /* 36. Find the number of lines in the odd front porch period: */ + vodd_front_porch_lines = GTF_MIN_V_PORCH ; + + /* finally, pack the results in the mode struct */ + drm_mode->hdisplay = hdisplay_rnd; + drm_mode->hsync_start = hdisplay_rnd + hfront_porch; + drm_mode->hsync_end = drm_mode->hsync_start + hsync; + drm_mode->htotal = total_pixels; + drm_mode->vdisplay = vdisplay_rnd; + drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines; + drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD; + drm_mode->vtotal = vtotal_lines; + + drm_mode->clock = pixel_freq; + + drm_mode_set_name(drm_mode); + drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC; + + if (interlaced) { + drm_mode->vtotal *= 2; + drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; + } + + return drm_mode; +} +EXPORT_SYMBOL(drm_gtf_mode); /** * drm_mode_set_name - set the name on a mode * @mode: name will be set in this mode @@ -151,7 +566,9 @@ EXPORT_SYMBOL(drm_mode_height); * FIXME: why is this needed? shouldn't vrefresh be set already? * * RETURNS: - * Vertical refresh rate of @mode x 1000. For precision reasons. + * Vertical refresh rate. It will be the result of actual value plus 0.5. + * If it is 70.288, it will return 70Hz. + * If it is 59.6, it will return 60Hz. */ int drm_mode_vrefresh(struct drm_display_mode *mode) { @@ -161,14 +578,13 @@ int drm_mode_vrefresh(struct drm_display_mode *mode) if (mode->vrefresh > 0) refresh = mode->vrefresh; else if (mode->htotal > 0 && mode->vtotal > 0) { + int vtotal; + vtotal = mode->vtotal; /* work out vrefresh the value will be x1000 */ calc_val = (mode->clock * 1000); - calc_val /= mode->htotal; - calc_val *= 1000; - calc_val /= mode->vtotal; + refresh = (calc_val + vtotal / 2) / vtotal; - refresh = calc_val; if (mode->flags & DRM_MODE_FLAG_INTERLACE) refresh *= 2; if (mode->flags & DRM_MODE_FLAG_DBLSCAN) @@ -403,8 +819,7 @@ void drm_mode_prune_invalid(struct drm_device *dev, list_del(&mode->head); if (verbose) { drm_mode_debug_printmodeline(mode); - DRM_DEBUG_MODE(DRM_MODESET_DEBUG, - "Not using %s mode %d\n", + DRM_DEBUG_KMS("Not using %s mode %d\n", mode->name, mode->status); } drm_mode_destroy(dev, mode); diff --git a/drivers/gpu/drm/drm_proc.c b/drivers/gpu/drm/drm_proc.c index bbd4b3d1074a..d379c4f2892f 100644 --- a/drivers/gpu/drm/drm_proc.c +++ b/drivers/gpu/drm/drm_proc.c @@ -106,20 +106,25 @@ int drm_proc_create_files(struct drm_info_list *files, int count, continue; tmp = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); - ent = create_proc_entry(files[i].name, S_IFREG | S_IRUGO, root); + if (tmp == NULL) { + ret = -1; + goto fail; + } + tmp->minor = minor; + tmp->info_ent = &files[i]; + list_add(&tmp->list, &minor->proc_nodes.list); + + ent = proc_create_data(files[i].name, S_IRUGO, root, + &drm_proc_fops, tmp); if (!ent) { DRM_ERROR("Cannot create /proc/dri/%s/%s\n", name, files[i].name); + list_del(&tmp->list); kfree(tmp); ret = -1; goto fail; } - ent->proc_fops = &drm_proc_fops; - ent->data = tmp; - tmp->minor = minor; - tmp->info_ent = &files[i]; - list_add(&(tmp->list), &(minor->proc_nodes.list)); } return 0; diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index 5301f226cb1c..7e42b7e9d43a 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -16,6 +16,7 @@ #include #include +#include "drm_sysfs.h" #include "drm_core.h" #include "drmP.h" @@ -253,6 +254,7 @@ static ssize_t subconnector_show(struct device *device, case DRM_MODE_CONNECTOR_Composite: case DRM_MODE_CONNECTOR_SVIDEO: case DRM_MODE_CONNECTOR_Component: + case DRM_MODE_CONNECTOR_TV: prop = dev->mode_config.tv_subconnector_property; is_tv = 1; break; @@ -293,6 +295,7 @@ static ssize_t select_subconnector_show(struct device *device, case DRM_MODE_CONNECTOR_Composite: case DRM_MODE_CONNECTOR_SVIDEO: case DRM_MODE_CONNECTOR_Component: + case DRM_MODE_CONNECTOR_TV: prop = dev->mode_config.tv_select_subconnector_property; is_tv = 1; break; @@ -391,6 +394,7 @@ int drm_sysfs_connector_add(struct drm_connector *connector) case DRM_MODE_CONNECTOR_Composite: case DRM_MODE_CONNECTOR_SVIDEO: case DRM_MODE_CONNECTOR_Component: + case DRM_MODE_CONNECTOR_TV: for (i = 0; i < ARRAY_SIZE(connector_attrs_opt1); i++) { ret = device_create_file(&connector->kdev, &connector_attrs_opt1[i]); if (ret) @@ -519,3 +523,27 @@ void drm_sysfs_device_remove(struct drm_minor *minor) { device_unregister(&minor->kdev); } + + +/** + * drm_class_device_register - Register a struct device in the drm class. + * + * @dev: pointer to struct device to register. + * + * @dev should have all relevant members pre-filled with the exception + * of the class member. In particular, the device_type member must + * be set. + */ + +int drm_class_device_register(struct device *dev) +{ + dev->class = drm_class; + return device_register(dev); +} +EXPORT_SYMBOL_GPL(drm_class_device_register); + +void drm_class_device_unregister(struct device *dev) +{ + return device_unregister(dev); +} +EXPORT_SYMBOL_GPL(drm_class_device_unregister); diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 30d6b99fb302..5269dfa5f620 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -4,10 +4,10 @@ ccflags-y := -Iinclude/drm i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \ + i915_debugfs.o \ i915_suspend.o \ i915_gem.o \ i915_gem_debug.o \ - i915_gem_debugfs.o \ i915_gem_tiling.o \ intel_display.o \ intel_crt.o \ diff --git a/drivers/gpu/drm/i915/i915_gem_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c similarity index 79% rename from drivers/gpu/drm/i915/i915_gem_debugfs.c rename to drivers/gpu/drm/i915/i915_debugfs.c index cb3b97405fbf..1e3bdcee863c 100644 --- a/drivers/gpu/drm/i915/i915_gem_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -158,16 +158,37 @@ static int i915_interrupt_info(struct seq_file *m, void *data) struct drm_device *dev = node->minor->dev; drm_i915_private_t *dev_priv = dev->dev_private; - seq_printf(m, "Interrupt enable: %08x\n", - I915_READ(IER)); - seq_printf(m, "Interrupt identity: %08x\n", - I915_READ(IIR)); - seq_printf(m, "Interrupt mask: %08x\n", - I915_READ(IMR)); - seq_printf(m, "Pipe A stat: %08x\n", - I915_READ(PIPEASTAT)); - seq_printf(m, "Pipe B stat: %08x\n", - I915_READ(PIPEBSTAT)); + if (!IS_IGDNG(dev)) { + seq_printf(m, "Interrupt enable: %08x\n", + I915_READ(IER)); + seq_printf(m, "Interrupt identity: %08x\n", + I915_READ(IIR)); + seq_printf(m, "Interrupt mask: %08x\n", + I915_READ(IMR)); + seq_printf(m, "Pipe A stat: %08x\n", + I915_READ(PIPEASTAT)); + seq_printf(m, "Pipe B stat: %08x\n", + I915_READ(PIPEBSTAT)); + } else { + seq_printf(m, "North Display Interrupt enable: %08x\n", + I915_READ(DEIER)); + seq_printf(m, "North Display Interrupt identity: %08x\n", + I915_READ(DEIIR)); + seq_printf(m, "North Display Interrupt mask: %08x\n", + I915_READ(DEIMR)); + seq_printf(m, "South Display Interrupt enable: %08x\n", + I915_READ(SDEIER)); + seq_printf(m, "South Display Interrupt identity: %08x\n", + I915_READ(SDEIIR)); + seq_printf(m, "South Display Interrupt mask: %08x\n", + I915_READ(SDEIMR)); + seq_printf(m, "Graphics Interrupt enable: %08x\n", + I915_READ(GTIER)); + seq_printf(m, "Graphics Interrupt identity: %08x\n", + I915_READ(GTIIR)); + seq_printf(m, "Graphics Interrupt mask: %08x\n", + I915_READ(GTIMR)); + } seq_printf(m, "Interrupts received: %d\n", atomic_read(&dev_priv->irq_received)); if (dev_priv->hw_status_page != NULL) { @@ -312,15 +333,13 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data) struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_device *dev = node->minor->dev; drm_i915_private_t *dev_priv = dev->dev_private; - unsigned int head, tail, mask; + unsigned int head, tail; head = I915_READ(PRB0_HEAD) & HEAD_ADDR; tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; - mask = dev_priv->ring.tail_mask; seq_printf(m, "RingHead : %08x\n", head); seq_printf(m, "RingTail : %08x\n", tail); - seq_printf(m, "RingMask : %08x\n", mask); seq_printf(m, "RingSize : %08lx\n", dev_priv->ring.Size); seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD)); @@ -363,7 +382,37 @@ out: return 0; } -static struct drm_info_list i915_gem_debugfs_list[] = { +static int i915_registers_info(struct seq_file *m, void *data) { + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + uint32_t reg; + +#define DUMP_RANGE(start, end) \ + for (reg=start; reg < end; reg += 4) \ + seq_printf(m, "%08x\t%08x\n", reg, I915_READ(reg)); + + DUMP_RANGE(0x00000, 0x00fff); /* VGA registers */ + DUMP_RANGE(0x02000, 0x02fff); /* instruction, memory, interrupt control registers */ + DUMP_RANGE(0x03000, 0x031ff); /* FENCE and PPGTT control registers */ + DUMP_RANGE(0x03200, 0x03fff); /* frame buffer compression registers */ + DUMP_RANGE(0x05000, 0x05fff); /* I/O control registers */ + DUMP_RANGE(0x06000, 0x06fff); /* clock control registers */ + DUMP_RANGE(0x07000, 0x07fff); /* 3D internal debug registers */ + DUMP_RANGE(0x07400, 0x088ff); /* GPE debug registers */ + DUMP_RANGE(0x0a000, 0x0afff); /* display palette registers */ + DUMP_RANGE(0x10000, 0x13fff); /* MMIO MCHBAR */ + DUMP_RANGE(0x30000, 0x3ffff); /* overlay registers */ + DUMP_RANGE(0x60000, 0x6ffff); /* display engine pipeline registers */ + DUMP_RANGE(0x70000, 0x72fff); /* display and cursor registers */ + DUMP_RANGE(0x73000, 0x73fff); /* performance counters */ + + return 0; +} + + +static struct drm_info_list i915_debugfs_list[] = { + {"i915_regs", i915_registers_info, 0}, {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, @@ -377,19 +426,19 @@ static struct drm_info_list i915_gem_debugfs_list[] = { {"i915_batchbuffers", i915_batchbuffer_info, 0}, {"i915_error_state", i915_error_state, 0}, }; -#define I915_GEM_DEBUGFS_ENTRIES ARRAY_SIZE(i915_gem_debugfs_list) +#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) -int i915_gem_debugfs_init(struct drm_minor *minor) +int i915_debugfs_init(struct drm_minor *minor) { - return drm_debugfs_create_files(i915_gem_debugfs_list, - I915_GEM_DEBUGFS_ENTRIES, + return drm_debugfs_create_files(i915_debugfs_list, + I915_DEBUGFS_ENTRIES, minor->debugfs_root, minor); } -void i915_gem_debugfs_cleanup(struct drm_minor *minor) +void i915_debugfs_cleanup(struct drm_minor *minor) { - drm_debugfs_remove_files(i915_gem_debugfs_list, - I915_GEM_DEBUGFS_ENTRIES, minor); + drm_debugfs_remove_files(i915_debugfs_list, + I915_DEBUGFS_ENTRIES, minor); } #endif /* CONFIG_DEBUG_FS */ diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 50d1f782768c..5a49a1867b35 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -29,11 +29,11 @@ #include "drmP.h" #include "drm.h" #include "drm_crtc_helper.h" +#include "drm_fb_helper.h" #include "intel_drv.h" #include "i915_drm.h" #include "i915_drv.h" - -#define I915_DRV "i915_drv" +#include /* Really want an OS-independent resettable timer. Would like to have * this loop run for (eg) 3 sec, but have the timer reset every time @@ -80,6 +80,34 @@ int i915_wait_ring(struct drm_device * dev, int n, const char *caller) return -EBUSY; } +/* As a ringbuffer is only allowed to wrap between instructions, fill + * the tail with NOOPs. + */ +int i915_wrap_ring(struct drm_device *dev) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + volatile unsigned int *virt; + int rem; + + rem = dev_priv->ring.Size - dev_priv->ring.tail; + if (dev_priv->ring.space < rem) { + int ret = i915_wait_ring(dev, rem, __func__); + if (ret) + return ret; + } + dev_priv->ring.space -= rem; + + virt = (unsigned int *) + (dev_priv->ring.virtual_start + dev_priv->ring.tail); + rem /= 4; + while (rem--) + *virt++ = MI_NOOP; + + dev_priv->ring.tail = 0; + + return 0; +} + /** * Sets up the hardware status page for devices that need a physical address * in the register. @@ -101,7 +129,7 @@ static int i915_init_phys_hws(struct drm_device *dev) memset(dev_priv->hw_status_page, 0, PAGE_SIZE); I915_WRITE(HWS_PGA, dev_priv->dma_status_page); - DRM_DEBUG_DRIVER(I915_DRV, "Enabled hardware status page\n"); + DRM_DEBUG_DRIVER("Enabled hardware status page\n"); return 0; } @@ -187,8 +215,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) master_priv->sarea_priv = (drm_i915_sarea_t *) ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); } else { - DRM_DEBUG_DRIVER(I915_DRV, - "sarea not found assuming DRI2 userspace\n"); + DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); } if (init->ring_size != 0) { @@ -200,7 +227,6 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) } dev_priv->ring.Size = init->ring_size; - dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; dev_priv->ring.map.offset = init->ring_start; dev_priv->ring.map.size = init->ring_size; @@ -238,7 +264,7 @@ static int i915_dma_resume(struct drm_device * dev) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - DRM_DEBUG_DRIVER(I915_DRV, "%s\n", __func__); + DRM_DEBUG_DRIVER("%s\n", __func__); if (dev_priv->ring.map.handle == NULL) { DRM_ERROR("can not ioremap virtual address for" @@ -251,14 +277,14 @@ static int i915_dma_resume(struct drm_device * dev) DRM_ERROR("Can not find hardware status page\n"); return -EINVAL; } - DRM_DEBUG_DRIVER(I915_DRV, "hw status page @ %p\n", + DRM_DEBUG_DRIVER("hw status page @ %p\n", dev_priv->hw_status_page); if (dev_priv->status_gfx_addr != 0) I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); else I915_WRITE(HWS_PGA, dev_priv->dma_status_page); - DRM_DEBUG_DRIVER(I915_DRV, "Enabled hardware status page\n"); + DRM_DEBUG_DRIVER("Enabled hardware status page\n"); return 0; } @@ -552,7 +578,7 @@ static int i915_dispatch_flip(struct drm_device * dev) if (!master_priv->sarea_priv) return -EINVAL; - DRM_DEBUG_DRIVER(I915_DRV, "%s: page=%d pfCurrentPage=%d\n", + DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", __func__, dev_priv->current_page, master_priv->sarea_priv->pf_current_page); @@ -633,8 +659,7 @@ static int i915_batchbuffer(struct drm_device *dev, void *data, return -EINVAL; } - DRM_DEBUG_DRIVER(I915_DRV, - "i915 batchbuffer, start %x used %d cliprects %d\n", + DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", batch->start, batch->used, batch->num_cliprects); RING_LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -681,8 +706,7 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data, void *batch_data; int ret; - DRM_DEBUG_DRIVER(I915_DRV, - "i915 cmdbuffer, buf %p sz %d cliprects %d\n", + DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); RING_LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -735,7 +759,7 @@ static int i915_flip_bufs(struct drm_device *dev, void *data, { int ret; - DRM_DEBUG_DRIVER(I915_DRV, "%s\n", __func__); + DRM_DEBUG_DRIVER("%s\n", __func__); RING_LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -778,7 +802,7 @@ static int i915_getparam(struct drm_device *dev, void *data, value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; break; default: - DRM_DEBUG_DRIVER(I915_DRV, "Unknown parameter %d\n", + DRM_DEBUG_DRIVER("Unknown parameter %d\n", param->param); return -EINVAL; } @@ -819,7 +843,7 @@ static int i915_setparam(struct drm_device *dev, void *data, dev_priv->fence_reg_start = param->value; break; default: - DRM_DEBUG_DRIVER(I915_DRV, "unknown parameter %d\n", + DRM_DEBUG_DRIVER("unknown parameter %d\n", param->param); return -EINVAL; } @@ -846,7 +870,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data, return 0; } - DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr); + DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); @@ -868,13 +892,25 @@ static int i915_set_status_page(struct drm_device *dev, void *data, memset(dev_priv->hw_status_page, 0, PAGE_SIZE); I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); - DRM_DEBUG_DRIVER(I915_DRV, "load hws HWS_PGA with gfx mem 0x%x\n", + DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", dev_priv->status_gfx_addr); - DRM_DEBUG_DRIVER(I915_DRV, "load hws at %p\n", + DRM_DEBUG_DRIVER("load hws at %p\n", dev_priv->hw_status_page); return 0; } +static int i915_get_bridge_dev(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); + if (!dev_priv->bridge_dev) { + DRM_ERROR("bridge device not found\n"); + return -1; + } + return 0; +} + /** * i915_probe_agp - get AGP bootup configuration * @pdev: PCI device @@ -888,20 +924,13 @@ static int i915_set_status_page(struct drm_device *dev, void *data, static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size, uint32_t *preallocated_size) { - struct pci_dev *bridge_dev; + struct drm_i915_private *dev_priv = dev->dev_private; u16 tmp = 0; unsigned long overhead; unsigned long stolen; - bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); - if (!bridge_dev) { - DRM_ERROR("bridge device not found\n"); - return -1; - } - /* Get the fb aperture size and "stolen" memory amount. */ - pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp); - pci_dev_put(bridge_dev); + pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp); *aperture_size = 1024 * 1024; *preallocated_size = 1024 * 1024; @@ -984,6 +1013,19 @@ static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size, return 0; } +/* true = enable decode, false = disable decoder */ +static unsigned int i915_vga_set_decode(void *cookie, bool state) +{ + struct drm_device *dev = cookie; + + intel_modeset_vga_set_state(dev, state); + if (state) + return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | + VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; + else + return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; +} + static int i915_load_modeset_init(struct drm_device *dev, unsigned long prealloc_size, unsigned long agp_size) @@ -1029,6 +1071,11 @@ static int i915_load_modeset_init(struct drm_device *dev, if (ret) DRM_INFO("failed to find VBIOS tables\n"); + /* if we have > 1 VGA cards, then disable the radeon VGA resources */ + ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); + if (ret) + goto destroy_ringbuffer; + ret = drm_irq_install(dev); if (ret) goto destroy_ringbuffer; @@ -1153,11 +1200,16 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) base = drm_get_resource_start(dev, mmio_bar); size = drm_get_resource_len(dev, mmio_bar); + if (i915_get_bridge_dev(dev)) { + ret = -EIO; + goto free_priv; + } + dev_priv->regs = ioremap(base, size); if (!dev_priv->regs) { DRM_ERROR("failed to map registers\n"); ret = -EIO; - goto free_priv; + goto put_bridge; } dev_priv->mm.gtt_mapping = @@ -1269,6 +1321,8 @@ out_iomapfree: io_mapping_free(dev_priv->mm.gtt_mapping); out_rmmap: iounmap(dev_priv->regs); +put_bridge: + pci_dev_put(dev_priv->bridge_dev); free_priv: kfree(dev_priv); return ret; @@ -1289,6 +1343,7 @@ int i915_driver_unload(struct drm_device *dev) if (drm_core_check_feature(dev, DRIVER_MODESET)) { drm_irq_uninstall(dev); + vga_client_register(dev->pdev, NULL, NULL, NULL); } if (dev->pdev->msi_enabled) @@ -1312,6 +1367,7 @@ int i915_driver_unload(struct drm_device *dev) i915_gem_lastclose(dev); } + pci_dev_put(dev_priv->bridge_dev); kfree(dev->dev_private); return 0; @@ -1321,7 +1377,7 @@ int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) { struct drm_i915_file_private *i915_file_priv; - DRM_DEBUG_DRIVER(I915_DRV, "\n"); + DRM_DEBUG_DRIVER("\n"); i915_file_priv = (struct drm_i915_file_private *) kmalloc(sizeof(*i915_file_priv), GFP_KERNEL); @@ -1352,7 +1408,7 @@ void i915_driver_lastclose(struct drm_device * dev) drm_i915_private_t *dev_priv = dev->dev_private; if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { - intelfb_restore(); + drm_fb_helper_restore(); return; } diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index fc4b68aa2d05..dbe568c9327b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -37,12 +37,15 @@ #include #include "drm_crtc_helper.h" -static unsigned int i915_modeset = -1; +static int i915_modeset = -1; module_param_named(modeset, i915_modeset, int, 0400); unsigned int i915_fbpercrtc = 0; module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); +unsigned int i915_powersave = 1; +module_param_named(powersave, i915_powersave, int, 0400); + static struct drm_driver driver; static struct pci_device_id pciidlist[] = { @@ -188,8 +191,8 @@ static struct drm_driver driver = { .master_create = i915_master_create, .master_destroy = i915_master_destroy, #if defined(CONFIG_DEBUG_FS) - .debugfs_init = i915_gem_debugfs_init, - .debugfs_cleanup = i915_gem_debugfs_cleanup, + .debugfs_init = i915_debugfs_init, + .debugfs_cleanup = i915_debugfs_cleanup, #endif .gem_init_object = i915_gem_init_object, .gem_free_object = i915_gem_free_object, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5b4f87e55621..a0632f8e76ac 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -85,7 +85,6 @@ struct drm_i915_gem_phys_object { }; typedef struct _drm_i915_ring_buffer { - int tail_mask; unsigned long Size; u8 *virtual_start; int head; @@ -156,6 +155,7 @@ typedef struct drm_i915_private { void __iomem *regs; + struct pci_dev *bridge_dev; drm_i915_ring_buffer_t ring; drm_dma_handle_t *status_page_dmah; @@ -311,7 +311,7 @@ typedef struct drm_i915_private { u32 saveIMR; u32 saveCACHE_MODE_0; u32 saveD_STATE; - u32 saveCG_2D_DIS; + u32 saveDSPCLK_GATE_D; u32 saveMI_ARB_STATE; u32 saveSWF0[16]; u32 saveSWF1[16]; @@ -443,6 +443,14 @@ typedef struct drm_i915_private { struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; } mm; struct sdvo_device_mapping sdvo_mappings[2]; + + /* Reclocking support */ + bool render_reclock_avail; + bool lvds_downclock_avail; + struct work_struct idle_work; + struct timer_list idle_timer; + bool busy; + u16 orig_clock; } drm_i915_private_t; /** driver private structure attached to each drm_gem_object */ @@ -575,6 +583,7 @@ enum intel_chip_family { extern struct drm_ioctl_desc i915_ioctls[]; extern int i915_max_ioctl; extern unsigned int i915_fbpercrtc; +extern unsigned int i915_powersave; extern int i915_master_create(struct drm_device *dev, struct drm_master *master); extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); @@ -730,8 +739,8 @@ void i915_gem_dump_object(struct drm_gem_object *obj, int len, void i915_dump_lru(struct drm_device *dev, const char *where); /* i915_debugfs.c */ -int i915_gem_debugfs_init(struct drm_minor *minor); -void i915_gem_debugfs_cleanup(struct drm_minor *minor); +int i915_debugfs_init(struct drm_minor *minor); +void i915_debugfs_cleanup(struct drm_minor *minor); /* i915_suspend.c */ extern int i915_save_state(struct drm_device *dev); @@ -757,6 +766,7 @@ static inline void opregion_enable_asle(struct drm_device *dev) { return; } /* modesetting */ extern void intel_modeset_init(struct drm_device *dev); extern void intel_modeset_cleanup(struct drm_device *dev); +extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); /** * Lock test for when it's just for synchronization of ring access. @@ -781,33 +791,32 @@ extern void intel_modeset_cleanup(struct drm_device *dev); #define I915_VERBOSE 0 -#define RING_LOCALS unsigned int outring, ringmask, outcount; \ - volatile char *virt; - -#define BEGIN_LP_RING(n) do { \ - if (I915_VERBOSE) \ - DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ - if (dev_priv->ring.space < (n)*4) \ - i915_wait_ring(dev, (n)*4, __func__); \ - outcount = 0; \ - outring = dev_priv->ring.tail; \ - ringmask = dev_priv->ring.tail_mask; \ - virt = dev_priv->ring.virtual_start; \ +#define RING_LOCALS volatile unsigned int *ring_virt__; + +#define BEGIN_LP_RING(n) do { \ + int bytes__ = 4*(n); \ + if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ + /* a wrap must occur between instructions so pad beforehand */ \ + if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \ + i915_wrap_ring(dev); \ + if (unlikely (dev_priv->ring.space < bytes__)) \ + i915_wait_ring(dev, bytes__, __func__); \ + ring_virt__ = (unsigned int *) \ + (dev_priv->ring.virtual_start + dev_priv->ring.tail); \ + dev_priv->ring.tail += bytes__; \ + dev_priv->ring.tail &= dev_priv->ring.Size - 1; \ + dev_priv->ring.space -= bytes__; \ } while (0) -#define OUT_RING(n) do { \ +#define OUT_RING(n) do { \ if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ - *(volatile unsigned int *)(virt + outring) = (n); \ - outcount++; \ - outring += 4; \ - outring &= ringmask; \ + *ring_virt__++ = (n); \ } while (0) #define ADVANCE_LP_RING() do { \ - if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ - dev_priv->ring.tail = outring; \ - dev_priv->ring.space -= outcount * 4; \ - I915_WRITE(PRB0_TAIL, outring); \ + if (I915_VERBOSE) \ + DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \ + I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \ } while(0) /** @@ -830,6 +839,7 @@ extern void intel_modeset_cleanup(struct drm_device *dev); #define I915_GEM_HWS_INDEX 0x20 #define I915_BREADCRUMB_INDEX 0x21 +extern int i915_wrap_ring(struct drm_device * dev); extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); #define IS_I830(dev) ((dev)->pci_device == 0x3577) @@ -903,6 +913,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); /* dsparb controlled by hw only */ #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev)) +#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev)) +#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev)) + #define PRIMARY_RINGBUFFER_SIZE (128*1024) #endif diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 80e5ba490dc2..c67317112f4a 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -29,6 +29,7 @@ #include "drm.h" #include "i915_drm.h" #include "i915_drv.h" +#include "intel_drv.h" #include #include @@ -111,7 +112,8 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data, { struct drm_i915_gem_create *args = data; struct drm_gem_object *obj; - int handle, ret; + int ret; + u32 handle; args->size = roundup(args->size, PAGE_SIZE); @@ -981,6 +983,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_gem_set_domain *args = data; struct drm_gem_object *obj; + struct drm_i915_gem_object *obj_priv; uint32_t read_domains = args->read_domains; uint32_t write_domain = args->write_domain; int ret; @@ -1004,15 +1007,17 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, obj = drm_gem_object_lookup(dev, file_priv, args->handle); if (obj == NULL) return -EBADF; + obj_priv = obj->driver_private; mutex_lock(&dev->struct_mutex); + + intel_mark_busy(dev, obj); + #if WATCH_BUF DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n", obj, obj->size, read_domains, write_domain); #endif if (read_domains & I915_GEM_DOMAIN_GTT) { - struct drm_i915_gem_object *obj_priv = obj->driver_private; - ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); /* Update the LRU on the fence for the CPU access that's @@ -2776,6 +2781,8 @@ i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); + intel_mark_busy(dev, obj); + #if WATCH_BUF DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", __func__, obj, @@ -4093,7 +4100,6 @@ i915_gem_init_ringbuffer(struct drm_device *dev) /* Set up the kernel mapping for the ring. */ ring->Size = obj->size; - ring->tail_mask = obj->size - 1; ring->map.offset = dev->agp->base + obj_priv->gtt_offset; ring->map.size = obj->size; diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index a2d527b22ec4..200e398453ca 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -94,23 +94,15 @@ static int intel_alloc_mchbar_resource(struct drm_device *dev) { - struct pci_dev *bridge_dev; drm_i915_private_t *dev_priv = dev->dev_private; int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; u32 temp_lo, temp_hi = 0; u64 mchbar_addr; int ret = 0; - bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); - if (!bridge_dev) { - DRM_DEBUG("no bridge dev?!\n"); - ret = -ENODEV; - goto out; - } - if (IS_I965G(dev)) - pci_read_config_dword(bridge_dev, reg + 4, &temp_hi); - pci_read_config_dword(bridge_dev, reg, &temp_lo); + pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); + pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); mchbar_addr = ((u64)temp_hi << 32) | temp_lo; /* If ACPI doesn't have it, assume we need to allocate it ourselves */ @@ -118,30 +110,28 @@ intel_alloc_mchbar_resource(struct drm_device *dev) if (mchbar_addr && pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) { ret = 0; - goto out_put; + goto out; } #endif /* Get some space for it */ - ret = pci_bus_alloc_resource(bridge_dev->bus, &dev_priv->mch_res, + ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res, MCHBAR_SIZE, MCHBAR_SIZE, PCIBIOS_MIN_MEM, 0, pcibios_align_resource, - bridge_dev); + dev_priv->bridge_dev); if (ret) { DRM_DEBUG("failed bus alloc: %d\n", ret); dev_priv->mch_res.start = 0; - goto out_put; + goto out; } if (IS_I965G(dev)) - pci_write_config_dword(bridge_dev, reg + 4, + pci_write_config_dword(dev_priv->bridge_dev, reg + 4, upper_32_bits(dev_priv->mch_res.start)); - pci_write_config_dword(bridge_dev, reg, + pci_write_config_dword(dev_priv->bridge_dev, reg, lower_32_bits(dev_priv->mch_res.start)); -out_put: - pci_dev_put(bridge_dev); out: return ret; } @@ -150,44 +140,36 @@ out: static bool intel_setup_mchbar(struct drm_device *dev) { - struct pci_dev *bridge_dev; + drm_i915_private_t *dev_priv = dev->dev_private; int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; u32 temp; bool need_disable = false, enabled; - bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); - if (!bridge_dev) { - DRM_DEBUG("no bridge dev?!\n"); - goto out; - } - if (IS_I915G(dev) || IS_I915GM(dev)) { - pci_read_config_dword(bridge_dev, DEVEN_REG, &temp); + pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); enabled = !!(temp & DEVEN_MCHBAR_EN); } else { - pci_read_config_dword(bridge_dev, mchbar_reg, &temp); + pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); enabled = temp & 1; } /* If it's already enabled, don't have to do anything */ if (enabled) - goto out_put; + goto out; if (intel_alloc_mchbar_resource(dev)) - goto out_put; + goto out; need_disable = true; /* Space is allocated or reserved, so enable it. */ if (IS_I915G(dev) || IS_I915GM(dev)) { - pci_write_config_dword(bridge_dev, DEVEN_REG, + pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp | DEVEN_MCHBAR_EN); } else { - pci_read_config_dword(bridge_dev, mchbar_reg, &temp); - pci_write_config_dword(bridge_dev, mchbar_reg, temp | 1); + pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); + pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); } -out_put: - pci_dev_put(bridge_dev); out: return need_disable; } @@ -196,25 +178,18 @@ static void intel_teardown_mchbar(struct drm_device *dev, bool disable) { drm_i915_private_t *dev_priv = dev->dev_private; - struct pci_dev *bridge_dev; int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; u32 temp; - bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); - if (!bridge_dev) { - DRM_DEBUG("no bridge dev?!\n"); - return; - } - if (disable) { if (IS_I915G(dev) || IS_I915GM(dev)) { - pci_read_config_dword(bridge_dev, DEVEN_REG, &temp); + pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); temp &= ~DEVEN_MCHBAR_EN; - pci_write_config_dword(bridge_dev, DEVEN_REG, temp); + pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); } else { - pci_read_config_dword(bridge_dev, mchbar_reg, &temp); + pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); temp &= ~1; - pci_write_config_dword(bridge_dev, mchbar_reg, temp); + pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); } } @@ -234,7 +209,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; bool need_disable; - if (!IS_I9XX(dev)) { + if (IS_IGDNG(dev)) { + /* On IGDNG whatever DRAM config, GPU always do + * same swizzling setup. + */ + swizzle_x = I915_BIT_6_SWIZZLE_9_10; + swizzle_y = I915_BIT_6_SWIZZLE_9; + } else if (!IS_I9XX(dev)) { /* As far as we know, the 865 doesn't have these bit 6 * swizzling issues. */ @@ -317,13 +298,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) } } - /* FIXME: check with memory config on IGDNG */ - if (IS_IGDNG(dev)) { - DRM_ERROR("disable tiling on IGDNG...\n"); - swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; - swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; - } - dev_priv->mm.bit_6_swizzle_x = swizzle_x; dev_priv->mm.bit_6_swizzle_y = swizzle_y; } diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 7ebc84c2881e..6c89f2ff2495 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -565,6 +565,27 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); I915_READ(PORT_HOTPLUG_STAT); + + /* EOS interrupts occurs */ + if (IS_IGD(dev) && + (hotplug_status & CRT_EOS_INT_STATUS)) { + u32 temp; + + DRM_DEBUG("EOS interrupt occurs\n"); + /* status is already cleared */ + temp = I915_READ(ADPA); + temp &= ~ADPA_DAC_ENABLE; + I915_WRITE(ADPA, temp); + + temp = I915_READ(PORT_HOTPLUG_EN); + temp &= ~CRT_EOS_INT_EN; + I915_WRITE(PORT_HOTPLUG_EN, temp); + + temp = I915_READ(PORT_HOTPLUG_STAT); + if (temp & CRT_EOS_INT_STATUS) + I915_WRITE(PORT_HOTPLUG_STAT, + CRT_EOS_INT_STATUS); + } } I915_WRITE(IIR, iir); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2955083aa471..3f7963553464 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -30,6 +30,7 @@ * fb aperture size and the amount of pre-reserved memory. */ #define INTEL_GMCH_CTRL 0x52 +#define INTEL_GMCH_VGA_DISABLE (1 << 1) #define INTEL_GMCH_ENABLED 0x4 #define INTEL_GMCH_MEM_MASK 0x1 #define INTEL_GMCH_MEM_64M 0x1 @@ -55,7 +56,7 @@ /* PCI config space */ #define HPLLCC 0xc0 /* 855 only */ -#define GC_CLOCK_CONTROL_MASK (3 << 0) +#define GC_CLOCK_CONTROL_MASK (0xf << 0) #define GC_CLOCK_133_200 (0 << 0) #define GC_CLOCK_100_200 (1 << 0) #define GC_CLOCK_100_133 (2 << 0) @@ -65,6 +66,25 @@ #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) #define GC_DISPLAY_CLOCK_MASK (7 << 4) +#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) +#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) +#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) +#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) +#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) +#define I965_GC_RENDER_CLOCK_MASK (0xf << 0) +#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) +#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) +#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) +#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) +#define I945_GC_RENDER_CLOCK_MASK (7 << 0) +#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) +#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) +#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) +#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) +#define I915_GC_RENDER_CLOCK_MASK (7 << 0) +#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) +#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) +#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) #define LBB 0xf4 /* VGA stuff */ @@ -553,9 +573,118 @@ #define DPLLA_TEST_M_BYPASS (1 << 2) #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) #define D_STATE 0x6104 -#define CG_2D_DIS 0x6200 -#define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) -#define CG_3D_DIS 0x6204 +#define DSTATE_PLL_D3_OFF (1<<3) +#define DSTATE_GFX_CLOCK_GATING (1<<1) +#define DSTATE_DOT_CLOCK_GATING (1<<0) +#define DSPCLK_GATE_D 0x6200 +# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ +# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ +# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ +# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ +# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ +# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ +# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ +# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ +# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ +# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ +# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ +# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ +# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ +# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ +# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ +# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ +# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ +# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ +# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ +# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) +# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) +# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) +# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) +# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ +# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ +# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ +# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) +# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) +/** + * This bit must be set on the 830 to prevent hangs when turning off the + * overlay scaler. + */ +# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) +# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) +# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) +# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ +# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ + +#define RENCLK_GATE_D1 0x6204 +# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ +# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ +# define PC_FE_CLOCK_GATE_DISABLE (1 << 11) +# define PC_BE_CLOCK_GATE_DISABLE (1 << 10) +# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) +# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) +# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) +# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) +# define MAG_CLOCK_GATE_DISABLE (1 << 5) +/** This bit must be unset on 855,865 */ +# define MECI_CLOCK_GATE_DISABLE (1 << 4) +# define DCMP_CLOCK_GATE_DISABLE (1 << 3) +# define MEC_CLOCK_GATE_DISABLE (1 << 2) +# define MECO_CLOCK_GATE_DISABLE (1 << 1) +/** This bit must be set on 855,865. */ +# define SV_CLOCK_GATE_DISABLE (1 << 0) +# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) +# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) +# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) +# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) +# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) +# define I915_WM_CLOCK_GATE_DISABLE (1 << 11) +# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) +# define I915_PI_CLOCK_GATE_DISABLE (1 << 9) +# define I915_DI_CLOCK_GATE_DISABLE (1 << 8) +# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) +# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) +# define I915_SC_CLOCK_GATE_DISABLE (1 << 5) +# define I915_FL_CLOCK_GATE_DISABLE (1 << 4) +# define I915_DM_CLOCK_GATE_DISABLE (1 << 3) +# define I915_PS_CLOCK_GATE_DISABLE (1 << 2) +# define I915_CC_CLOCK_GATE_DISABLE (1 << 1) +# define I915_BY_CLOCK_GATE_DISABLE (1 << 0) + +# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) +/** This bit must always be set on 965G/965GM */ +# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) +# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) +# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) +# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) +# define I965_GW_CLOCK_GATE_DISABLE (1 << 25) +# define I965_TD_CLOCK_GATE_DISABLE (1 << 24) +/** This bit must always be set on 965G */ +# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) +# define I965_IC_CLOCK_GATE_DISABLE (1 << 22) +# define I965_EU_CLOCK_GATE_DISABLE (1 << 21) +# define I965_IF_CLOCK_GATE_DISABLE (1 << 20) +# define I965_TC_CLOCK_GATE_DISABLE (1 << 19) +# define I965_SO_CLOCK_GATE_DISABLE (1 << 17) +# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) +# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) +# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) +# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) +# define I965_EM_CLOCK_GATE_DISABLE (1 << 12) +# define I965_UC_CLOCK_GATE_DISABLE (1 << 11) +# define I965_SI_CLOCK_GATE_DISABLE (1 << 6) +# define I965_MT_CLOCK_GATE_DISABLE (1 << 5) +# define I965_PL_CLOCK_GATE_DISABLE (1 << 4) +# define I965_DG_CLOCK_GATE_DISABLE (1 << 3) +# define I965_QC_CLOCK_GATE_DISABLE (1 << 2) +# define I965_FT_CLOCK_GATE_DISABLE (1 << 1) +# define I965_DM_CLOCK_GATE_DISABLE (1 << 0) + +#define RENCLK_GATE_D2 0x6208 +#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) +#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) +#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) +#define RAMCLK_GATE_D 0x6210 /* CRL only */ +#define DEUC 0x6214 /* CRL only */ /* * Palette regs @@ -683,6 +812,7 @@ #define SDVOB_HOTPLUG_INT_EN (1 << 26) #define SDVOC_HOTPLUG_INT_EN (1 << 25) #define TV_HOTPLUG_INT_EN (1 << 18) +#define CRT_EOS_INT_EN (1 << 10) #define CRT_HOTPLUG_INT_EN (1 << 9) #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) @@ -717,6 +847,7 @@ #define DPC_HOTPLUG_INT_STATUS (1 << 28) #define HDMID_HOTPLUG_INT_STATUS (1 << 27) #define DPD_HOTPLUG_INT_STATUS (1 << 27) +#define CRT_EOS_INT_STATUS (1 << 12) #define CRT_HOTPLUG_INT_STATUS (1 << 11) #define TV_HOTPLUG_INT_STATUS (1 << 10) #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) @@ -1586,6 +1717,7 @@ #define PIPECONF_PROGRESSIVE (0 << 21) #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) +#define PIPECONF_CXSR_DOWNCLOCK (1<<16) #define PIPEASTAT 0x70024 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) #define PIPE_CRC_ERROR_ENABLE (1UL<<29) @@ -1733,6 +1865,7 @@ #define DISPPLANE_NO_LINE_DOUBLE 0 #define DISPPLANE_STEREO_POLARITY_FIRST 0 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) +#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* IGDNG */ #define DISPPLANE_TILED (1<<10) #define DSPAADDR 0x70184 #define DSPASTRIDE 0x70188 @@ -1913,6 +2046,9 @@ #define GTIIR 0x44018 #define GTIER 0x4401c +#define DISP_ARB_CTL 0x45000 +#define DISP_TILE_SURFACE_SWIZZLING (1<<13) + /* PCH */ /* south display engine interrupt */ diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 1d04e1904ac6..20d4d19f5568 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -461,7 +461,7 @@ int i915_save_state(struct drm_device *dev) /* Clock gating state */ dev_priv->saveD_STATE = I915_READ(D_STATE); - dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS); + dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); /* Cache mode state */ dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); @@ -588,7 +588,7 @@ int i915_restore_state(struct drm_device *dev) /* Clock gating state */ I915_WRITE (D_STATE, dev_priv->saveD_STATE); - I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS); + I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D); /* Cache mode state */ I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index f806fcc54e09..1e28c1652fd0 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -355,8 +355,14 @@ parse_driver_features(struct drm_i915_private *dev_priv, } driver = find_section(bdb, BDB_DRIVER_FEATURES); - if (driver && driver->lvds_config == BDB_DRIVER_FEATURE_EDP) + if (!driver) + return; + + if (driver->lvds_config == BDB_DRIVER_FEATURE_EDP) dev_priv->edp_support = 1; + + if (driver->dual_frequency) + dev_priv->render_reclock_avail = true; } /** diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 590f81c8f594..88814fa2dfd2 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -64,6 +64,34 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode) } I915_WRITE(reg, temp); + + if (IS_IGD(dev)) { + if (mode == DRM_MODE_DPMS_OFF) { + /* turn off DAC */ + temp = I915_READ(PORT_HOTPLUG_EN); + temp &= ~CRT_EOS_INT_EN; + I915_WRITE(PORT_HOTPLUG_EN, temp); + + temp = I915_READ(PORT_HOTPLUG_STAT); + if (temp & CRT_EOS_INT_STATUS) + I915_WRITE(PORT_HOTPLUG_STAT, + CRT_EOS_INT_STATUS); + } else { + /* turn on DAC. EOS interrupt must be enabled after DAC + * is enabled, so it sounds not good to enable it in + * i915_driver_irq_postinstall() + * wait 12.5ms after DAC is enabled + */ + msleep(13); + temp = I915_READ(PORT_HOTPLUG_STAT); + if (temp & CRT_EOS_INT_STATUS) + I915_WRITE(PORT_HOTPLUG_STAT, + CRT_EOS_INT_STATUS); + temp = I915_READ(PORT_HOTPLUG_EN); + temp |= CRT_EOS_INT_EN; + I915_WRITE(PORT_HOTPLUG_EN, temp); + } + } } static int intel_crt_mode_valid(struct drm_connector *connector, diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 748ed50c55ca..0227b1652906 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -38,6 +38,7 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type); static void intel_update_watermarks(struct drm_device *dev); +static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule); typedef struct { /* given values */ @@ -67,6 +68,8 @@ struct intel_limit { intel_p2_t p2; bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, int, int, intel_clock_t *); + bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *, + int, int, intel_clock_t *); }; #define I8XX_DOT_MIN 25000 @@ -261,6 +264,9 @@ static bool intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, int target, int refclk, intel_clock_t *best_clock); static bool +intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, + int target, int refclk, intel_clock_t *best_clock); +static bool intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, int target, int refclk, intel_clock_t *best_clock); static bool @@ -286,6 +292,7 @@ static const intel_limit_t intel_limits_i8xx_dvo = { .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, .find_pll = intel_find_best_PLL, + .find_reduced_pll = intel_find_best_reduced_PLL, }; static const intel_limit_t intel_limits_i8xx_lvds = { @@ -300,6 +307,7 @@ static const intel_limit_t intel_limits_i8xx_lvds = { .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, .find_pll = intel_find_best_PLL, + .find_reduced_pll = intel_find_best_reduced_PLL, }; static const intel_limit_t intel_limits_i9xx_sdvo = { @@ -314,6 +322,7 @@ static const intel_limit_t intel_limits_i9xx_sdvo = { .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, .find_pll = intel_find_best_PLL, + .find_reduced_pll = intel_find_best_reduced_PLL, }; static const intel_limit_t intel_limits_i9xx_lvds = { @@ -331,6 +340,7 @@ static const intel_limit_t intel_limits_i9xx_lvds = { .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, .find_pll = intel_find_best_PLL, + .find_reduced_pll = intel_find_best_reduced_PLL, }; /* below parameter and function is for G4X Chipset Family*/ @@ -348,6 +358,7 @@ static const intel_limit_t intel_limits_g4x_sdvo = { .p2_fast = G4X_P2_SDVO_FAST }, .find_pll = intel_g4x_find_best_PLL, + .find_reduced_pll = intel_g4x_find_best_PLL, }; static const intel_limit_t intel_limits_g4x_hdmi = { @@ -364,6 +375,7 @@ static const intel_limit_t intel_limits_g4x_hdmi = { .p2_fast = G4X_P2_HDMI_DAC_FAST }, .find_pll = intel_g4x_find_best_PLL, + .find_reduced_pll = intel_g4x_find_best_PLL, }; static const intel_limit_t intel_limits_g4x_single_channel_lvds = { @@ -388,6 +400,7 @@ static const intel_limit_t intel_limits_g4x_single_channel_lvds = { .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST }, .find_pll = intel_g4x_find_best_PLL, + .find_reduced_pll = intel_g4x_find_best_PLL, }; static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { @@ -412,6 +425,7 @@ static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST }, .find_pll = intel_g4x_find_best_PLL, + .find_reduced_pll = intel_g4x_find_best_PLL, }; static const intel_limit_t intel_limits_g4x_display_port = { @@ -449,6 +463,7 @@ static const intel_limit_t intel_limits_igd_sdvo = { .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, .find_pll = intel_find_best_PLL, + .find_reduced_pll = intel_find_best_reduced_PLL, }; static const intel_limit_t intel_limits_igd_lvds = { @@ -464,6 +479,7 @@ static const intel_limit_t intel_limits_igd_lvds = { .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, .find_pll = intel_find_best_PLL, + .find_reduced_pll = intel_find_best_reduced_PLL, }; static const intel_limit_t intel_limits_igdng_sdvo = { @@ -688,15 +704,16 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, memset (best_clock, 0, sizeof (*best_clock)); - for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { - for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) { - /* m1 is always 0 in IGD */ - if (clock.m2 >= clock.m1 && !IS_IGD(dev)) - break; - for (clock.n = limit->n.min; clock.n <= limit->n.max; - clock.n++) { - for (clock.p1 = limit->p1.min; - clock.p1 <= limit->p1.max; clock.p1++) { + for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { + for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; + clock.m1++) { + for (clock.m2 = limit->m2.min; + clock.m2 <= limit->m2.max; clock.m2++) { + /* m1 is always 0 in IGD */ + if (clock.m2 >= clock.m1 && !IS_IGD(dev)) + break; + for (clock.n = limit->n.min; + clock.n <= limit->n.max; clock.n++) { int this_err; intel_clock(dev, refclk, &clock); @@ -717,6 +734,46 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, return (err != target); } + +static bool +intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, + int target, int refclk, intel_clock_t *best_clock) + +{ + struct drm_device *dev = crtc->dev; + intel_clock_t clock; + int err = target; + bool found = false; + + memcpy(&clock, best_clock, sizeof(intel_clock_t)); + + for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { + for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) { + /* m1 is always 0 in IGD */ + if (clock.m2 >= clock.m1 && !IS_IGD(dev)) + break; + for (clock.n = limit->n.min; clock.n <= limit->n.max; + clock.n++) { + int this_err; + + intel_clock(dev, refclk, &clock); + + if (!intel_PLL_is_valid(crtc, &clock)) + continue; + + this_err = abs(clock.dot - target); + if (this_err < err) { + *best_clock = clock; + err = this_err; + found = true; + } + } + } + } + + return found; +} + static bool intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, int target, int refclk, intel_clock_t *best_clock) @@ -747,7 +804,7 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, max_n = limit->n.max; /* based on hardware requriment prefer smaller n to precision */ for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { - /* based on hardware requirment prefere larger m1,m2, p1 */ + /* based on hardware requirment prefere larger m1,m2 */ for (clock.m1 = limit->m1.max; clock.m1 >= limit->m1.min; clock.m1--) { for (clock.m2 = limit->m2.max; @@ -832,15 +889,14 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, memset(best_clock, 0, sizeof(*best_clock)); max_n = limit->n.max; - /* based on hardware requriment prefer smaller n to precision */ - for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { - /* based on hardware requirment prefere larger m1,m2, p1 */ - for (clock.m1 = limit->m1.max; - clock.m1 >= limit->m1.min; clock.m1--) { - for (clock.m2 = limit->m2.max; - clock.m2 >= limit->m2.min; clock.m2--) { - for (clock.p1 = limit->p1.max; - clock.p1 >= limit->p1.min; clock.p1--) { + for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { + /* based on hardware requriment prefer smaller n to precision */ + for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { + /* based on hardware requirment prefere larger m1,m2 */ + for (clock.m1 = limit->m1.max; + clock.m1 >= limit->m1.min; clock.m1--) { + for (clock.m2 = limit->m2.max; + clock.m2 >= limit->m2.min; clock.m2--) { int this_err; intel_clock(dev, refclk, &clock); @@ -1008,6 +1064,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, dspcntr &= ~DISPPLANE_TILED; } + if (IS_IGDNG(dev)) + /* must disable */ + dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; + I915_WRITE(dspcntr_reg, dspcntr); Start = obj_priv->gtt_offset; @@ -1030,8 +1090,11 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, if (old_fb) { intel_fb = to_intel_framebuffer(old_fb); + obj_priv = intel_fb->obj->driver_private; i915_gem_object_unpin(intel_fb->obj); } + intel_increase_pllclock(crtc, true); + mutex_unlock(&dev->struct_mutex); if (!dev->primary->master) @@ -1581,6 +1644,8 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) else i9xx_crtc_dpms(crtc, mode); + intel_crtc->dpms_mode = mode; + if (!dev->primary->master) return; @@ -1603,8 +1668,6 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); break; } - - intel_crtc->dpms_mode = mode; } static void intel_crtc_prepare (struct drm_crtc *crtc) @@ -2054,6 +2117,18 @@ static int intel_get_fifo_size(struct drm_device *dev, int plane) return size; } +static void g4x_update_wm(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u32 fw_blc_self = I915_READ(FW_BLC_SELF); + + if (i915_powersave) + fw_blc_self |= FW_BLC_SELF_EN; + else + fw_blc_self &= ~FW_BLC_SELF_EN; + I915_WRITE(FW_BLC_SELF, fw_blc_self); +} + static void i965_update_wm(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -2105,7 +2180,8 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, cwm = 2; /* Calc sr entries for one plane configs */ - if (sr_hdisplay && (!planea_clock || !planeb_clock)) { + if (HAS_FW_BLC(dev) && sr_hdisplay && + (!planea_clock || !planeb_clock)) { /* self-refresh has much higher latency */ const static int sr_latency_ns = 6000; @@ -2120,8 +2196,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, srwm = total_size - sr_entries; if (srwm < 0) srwm = 1; - if (IS_I9XX(dev)) - I915_WRITE(FW_BLC_SELF, (srwm & 0x3f)); + I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); } DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", @@ -2195,9 +2270,6 @@ static void intel_update_watermarks(struct drm_device *dev) unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; int enabled = 0, pixel_size = 0; - if (DSPARB_HWCONTROL(dev)) - return; - /* Get the clock config from both planes */ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { intel_crtc = to_intel_crtc(crtc); @@ -2230,7 +2302,9 @@ static void intel_update_watermarks(struct drm_device *dev) else if (IS_IGD(dev)) igd_disable_cxsr(dev); - if (IS_I965G(dev)) + if (IS_G4X(dev)) + g4x_update_wm(dev); + else if (IS_I965G(dev)) i965_update_wm(dev); else if (IS_I9XX(dev) || IS_MOBILE(dev)) i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay, @@ -2264,9 +2338,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; int refclk, num_outputs = 0; - intel_clock_t clock; - u32 dpll = 0, fp = 0, dspcntr, pipeconf; - bool ok, is_sdvo = false, is_dvo = false; + intel_clock_t clock, reduced_clock; + u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf; + bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; bool is_edp = false; struct drm_mode_config *mode_config = &dev->mode_config; @@ -2349,6 +2423,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, return -EINVAL; } + if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) { + memcpy(&reduced_clock, &clock, sizeof(intel_clock_t)); + has_reduced_clock = limit->find_reduced_pll(limit, crtc, + (adjusted_mode->clock*3/4), + refclk, + &reduced_clock); + } + /* SDVO TV has fixed PLL values depend on its clock range, this mirrors vbios setting. */ if (is_sdvo && is_tv) { @@ -2394,10 +2476,17 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, link_bw, &m_n); } - if (IS_IGD(dev)) + if (IS_IGD(dev)) { fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; - else + if (has_reduced_clock) + fp2 = (1 << reduced_clock.n) << 16 | + reduced_clock.m1 << 8 | reduced_clock.m2; + } else { fp = clock.n << 16 | clock.m1 << 8 | clock.m2; + if (has_reduced_clock) + fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | + reduced_clock.m2; + } if (!IS_IGDNG(dev)) dpll = DPLL_VGA_MODE_DIS; @@ -2426,6 +2515,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, /* also FPA1 */ if (IS_IGDNG(dev)) dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; + if (IS_G4X(dev) && has_reduced_clock) + dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; } switch (clock.p2) { case 5: @@ -2573,6 +2664,22 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, udelay(150); } + if (is_lvds && has_reduced_clock && i915_powersave) { + I915_WRITE(fp_reg + 4, fp2); + intel_crtc->lowfreq_avail = true; + if (HAS_PIPE_CXSR(dev)) { + DRM_DEBUG("enabling CxSR downclocking\n"); + pipeconf |= PIPECONF_CXSR_DOWNCLOCK; + } + } else { + I915_WRITE(fp_reg + 4, fp); + intel_crtc->lowfreq_avail = false; + if (HAS_PIPE_CXSR(dev)) { + DRM_DEBUG("disabling CxSR downclocking\n"); + pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; + } + } + I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | @@ -2616,6 +2723,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, intel_wait_for_vblank(dev); + if (IS_IGDNG(dev)) { + /* enable address swizzle for tiling buffer */ + temp = I915_READ(DISP_ARB_CTL); + I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); + } + I915_WRITE(dspcntr_reg, dspcntr); /* Flush the plane changes */ @@ -2769,10 +2882,16 @@ static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_framebuffer *intel_fb; int pipe = intel_crtc->pipe; uint32_t temp = 0; uint32_t adder; + if (crtc->fb) { + intel_fb = to_intel_framebuffer(crtc->fb); + intel_mark_busy(dev, intel_fb->obj); + } + if (x < 0) { temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; x = -x; @@ -3070,12 +3189,319 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, return mode; } +#define GPU_IDLE_TIMEOUT 500 /* ms */ + +/* When this timer fires, we've been idle for awhile */ +static void intel_gpu_idle_timer(unsigned long arg) +{ + struct drm_device *dev = (struct drm_device *)arg; + drm_i915_private_t *dev_priv = dev->dev_private; + + DRM_DEBUG("idle timer fired, downclocking\n"); + + dev_priv->busy = false; + + queue_work(dev_priv->wq, &dev_priv->idle_work); +} + +void intel_increase_renderclock(struct drm_device *dev, bool schedule) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + + if (IS_IGDNG(dev)) + return; + + if (!dev_priv->render_reclock_avail) { + DRM_DEBUG("not reclocking render clock\n"); + return; + } + + /* Restore render clock frequency to original value */ + if (IS_G4X(dev) || IS_I9XX(dev)) + pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock); + else if (IS_I85X(dev)) + pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock); + DRM_DEBUG("increasing render clock frequency\n"); + + /* Schedule downclock */ + if (schedule) + mod_timer(&dev_priv->idle_timer, jiffies + + msecs_to_jiffies(GPU_IDLE_TIMEOUT)); +} + +void intel_decrease_renderclock(struct drm_device *dev) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + + if (IS_IGDNG(dev)) + return; + + if (!dev_priv->render_reclock_avail) { + DRM_DEBUG("not reclocking render clock\n"); + return; + } + + if (IS_G4X(dev)) { + u16 gcfgc; + + /* Adjust render clock... */ + pci_read_config_word(dev->pdev, GCFGC, &gcfgc); + + /* Down to minimum... */ + gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK; + gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ; + + pci_write_config_word(dev->pdev, GCFGC, gcfgc); + } else if (IS_I965G(dev)) { + u16 gcfgc; + + /* Adjust render clock... */ + pci_read_config_word(dev->pdev, GCFGC, &gcfgc); + + /* Down to minimum... */ + gcfgc &= ~I965_GC_RENDER_CLOCK_MASK; + gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ; + + pci_write_config_word(dev->pdev, GCFGC, gcfgc); + } else if (IS_I945G(dev) || IS_I945GM(dev)) { + u16 gcfgc; + + /* Adjust render clock... */ + pci_read_config_word(dev->pdev, GCFGC, &gcfgc); + + /* Down to minimum... */ + gcfgc &= ~I945_GC_RENDER_CLOCK_MASK; + gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ; + + pci_write_config_word(dev->pdev, GCFGC, gcfgc); + } else if (IS_I915G(dev)) { + u16 gcfgc; + + /* Adjust render clock... */ + pci_read_config_word(dev->pdev, GCFGC, &gcfgc); + + /* Down to minimum... */ + gcfgc &= ~I915_GC_RENDER_CLOCK_MASK; + gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ; + + pci_write_config_word(dev->pdev, GCFGC, gcfgc); + } else if (IS_I85X(dev)) { + u16 hpllcc; + + /* Adjust render clock... */ + pci_read_config_word(dev->pdev, HPLLCC, &hpllcc); + + /* Up to maximum... */ + hpllcc &= ~GC_CLOCK_CONTROL_MASK; + hpllcc |= GC_CLOCK_133_200; + + pci_write_config_word(dev->pdev, HPLLCC, hpllcc); + } + DRM_DEBUG("decreasing render clock frequency\n"); +} + +/* Note that no increase function is needed for this - increase_renderclock() + * will also rewrite these bits + */ +void intel_decrease_displayclock(struct drm_device *dev) +{ + if (IS_IGDNG(dev)) + return; + + if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) || + IS_I915GM(dev)) { + u16 gcfgc; + + /* Adjust render clock... */ + pci_read_config_word(dev->pdev, GCFGC, &gcfgc); + + /* Down to minimum... */ + gcfgc &= ~0xf0; + gcfgc |= 0x80; + + pci_write_config_word(dev->pdev, GCFGC, gcfgc); + } +} + +#define CRTC_IDLE_TIMEOUT 1000 /* ms */ + +static void intel_crtc_idle_timer(unsigned long arg) +{ + struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; + struct drm_crtc *crtc = &intel_crtc->base; + drm_i915_private_t *dev_priv = crtc->dev->dev_private; + + DRM_DEBUG("idle timer fired, downclocking\n"); + + intel_crtc->busy = false; + + queue_work(dev_priv->wq, &dev_priv->idle_work); +} + +static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule) +{ + struct drm_device *dev = crtc->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int pipe = intel_crtc->pipe; + int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; + int dpll = I915_READ(dpll_reg); + + if (IS_IGDNG(dev)) + return; + + if (!dev_priv->lvds_downclock_avail) + return; + + if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { + DRM_DEBUG("upclocking LVDS\n"); + + /* Unlock panel regs */ + I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); + + dpll &= ~DISPLAY_RATE_SELECT_FPA1; + I915_WRITE(dpll_reg, dpll); + dpll = I915_READ(dpll_reg); + intel_wait_for_vblank(dev); + dpll = I915_READ(dpll_reg); + if (dpll & DISPLAY_RATE_SELECT_FPA1) + DRM_DEBUG("failed to upclock LVDS!\n"); + + /* ...and lock them again */ + I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); + } + + /* Schedule downclock */ + if (schedule) + mod_timer(&intel_crtc->idle_timer, jiffies + + msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); +} + +static void intel_decrease_pllclock(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int pipe = intel_crtc->pipe; + int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; + int dpll = I915_READ(dpll_reg); + + if (IS_IGDNG(dev)) + return; + + if (!dev_priv->lvds_downclock_avail) + return; + + /* + * Since this is called by a timer, we should never get here in + * the manual case. + */ + if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { + DRM_DEBUG("downclocking LVDS\n"); + + /* Unlock panel regs */ + I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); + + dpll |= DISPLAY_RATE_SELECT_FPA1; + I915_WRITE(dpll_reg, dpll); + dpll = I915_READ(dpll_reg); + intel_wait_for_vblank(dev); + dpll = I915_READ(dpll_reg); + if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) + DRM_DEBUG("failed to downclock LVDS!\n"); + + /* ...and lock them again */ + I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); + } + +} + +/** + * intel_idle_update - adjust clocks for idleness + * @work: work struct + * + * Either the GPU or display (or both) went idle. Check the busy status + * here and adjust the CRTC and GPU clocks as necessary. + */ +static void intel_idle_update(struct work_struct *work) +{ + drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, + idle_work); + struct drm_device *dev = dev_priv->dev; + struct drm_crtc *crtc; + struct intel_crtc *intel_crtc; + + if (!i915_powersave) + return; + + mutex_lock(&dev->struct_mutex); + + /* GPU isn't processing, downclock it. */ + if (!dev_priv->busy) { + intel_decrease_renderclock(dev); + intel_decrease_displayclock(dev); + } + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + /* Skip inactive CRTCs */ + if (!crtc->fb) + continue; + + intel_crtc = to_intel_crtc(crtc); + if (!intel_crtc->busy) + intel_decrease_pllclock(crtc); + } + + mutex_unlock(&dev->struct_mutex); +} + +/** + * intel_mark_busy - mark the GPU and possibly the display busy + * @dev: drm device + * @obj: object we're operating on + * + * Callers can use this function to indicate that the GPU is busy processing + * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout + * buffer), we'll also mark the display as busy, so we know to increase its + * clock frequency. + */ +void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + struct drm_crtc *crtc = NULL; + struct intel_framebuffer *intel_fb; + struct intel_crtc *intel_crtc; + + if (!drm_core_check_feature(dev, DRIVER_MODESET)) + return; + + dev_priv->busy = true; + intel_increase_renderclock(dev, true); + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + if (!crtc->fb) + continue; + + intel_crtc = to_intel_crtc(crtc); + intel_fb = to_intel_framebuffer(crtc->fb); + if (intel_fb->obj == obj) { + if (!intel_crtc->busy) { + /* Non-busy -> busy, upclock */ + intel_increase_pllclock(crtc, true); + intel_crtc->busy = true; + } else { + /* Busy -> busy, put off timer */ + mod_timer(&intel_crtc->idle_timer, jiffies + + msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); + } + } + } +} + static void intel_crtc_destroy(struct drm_crtc *crtc) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - if (intel_crtc->mode_set.mode) - drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode); drm_crtc_cleanup(crtc); kfree(intel_crtc); } @@ -3122,15 +3548,10 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); - intel_crtc->mode_set.crtc = &intel_crtc->base; - intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1); - intel_crtc->mode_set.num_connectors = 0; - - if (i915_fbpercrtc) { + intel_crtc->busy = false; - - - } + setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, + (unsigned long)intel_crtc); } int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, @@ -3138,30 +3559,26 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, { drm_i915_private_t *dev_priv = dev->dev_private; struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; - struct drm_crtc *crtc = NULL; - int pipe = -1; + struct drm_mode_object *drmmode_obj; + struct intel_crtc *crtc; if (!dev_priv) { DRM_ERROR("called with no initialization\n"); return -EINVAL; } - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - if (crtc->base.id == pipe_from_crtc_id->crtc_id) { - pipe = intel_crtc->pipe; - break; - } - } + drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, + DRM_MODE_OBJECT_CRTC); - if (pipe == -1) { + if (!drmmode_obj) { DRM_ERROR("no such CRTC id\n"); return -EINVAL; } - pipe_from_crtc_id->pipe = pipe; + crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); + pipe_from_crtc_id->pipe = crtc->pipe; - return 0; + return 0; } struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) @@ -3362,8 +3779,56 @@ static const struct drm_mode_config_funcs intel_mode_funcs = { .fb_changed = intelfb_probe, }; +void intel_init_clock_gating(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + /* + * Disable clock gating reported to work incorrectly according to the + * specs, but enable as much else as we can. + */ + if (IS_G4X(dev)) { + uint32_t dspclk_gate; + I915_WRITE(RENCLK_GATE_D1, 0); + I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | + GS_UNIT_CLOCK_GATE_DISABLE | + CL_UNIT_CLOCK_GATE_DISABLE); + I915_WRITE(RAMCLK_GATE_D, 0); + dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | + OVRUNIT_CLOCK_GATE_DISABLE | + OVCUNIT_CLOCK_GATE_DISABLE; + if (IS_GM45(dev)) + dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; + I915_WRITE(DSPCLK_GATE_D, dspclk_gate); + } else if (IS_I965GM(dev)) { + I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); + I915_WRITE(RENCLK_GATE_D2, 0); + I915_WRITE(DSPCLK_GATE_D, 0); + I915_WRITE(RAMCLK_GATE_D, 0); + I915_WRITE16(DEUC, 0); + } else if (IS_I965G(dev)) { + I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | + I965_RCC_CLOCK_GATE_DISABLE | + I965_RCPB_CLOCK_GATE_DISABLE | + I965_ISC_CLOCK_GATE_DISABLE | + I965_FBC_CLOCK_GATE_DISABLE); + I915_WRITE(RENCLK_GATE_D2, 0); + } else if (IS_I9XX(dev)) { + u32 dstate = I915_READ(D_STATE); + + dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | + DSTATE_DOT_CLOCK_GATING; + I915_WRITE(D_STATE, dstate); + } else if (IS_I855(dev) || IS_I865G(dev)) { + I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); + } else if (IS_I830(dev)) { + I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); + } +} + void intel_modeset_init(struct drm_device *dev) { + struct drm_i915_private *dev_priv = dev->dev_private; int num_pipe; int i; @@ -3398,15 +3863,47 @@ void intel_modeset_init(struct drm_device *dev) DRM_DEBUG("%d display pipe%s available.\n", num_pipe, num_pipe > 1 ? "s" : ""); + if (IS_I85X(dev)) + pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock); + else if (IS_I9XX(dev) || IS_G4X(dev)) + pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock); + for (i = 0; i < num_pipe; i++) { intel_crtc_init(dev, i); } intel_setup_outputs(dev); + + intel_init_clock_gating(dev); + + INIT_WORK(&dev_priv->idle_work, intel_idle_update); + setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, + (unsigned long)dev); } void intel_modeset_cleanup(struct drm_device *dev) { + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_crtc *crtc; + struct intel_crtc *intel_crtc; + + mutex_lock(&dev->struct_mutex); + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + /* Skip inactive CRTCs */ + if (!crtc->fb) + continue; + + intel_crtc = to_intel_crtc(crtc); + intel_increase_pllclock(crtc, false); + del_timer_sync(&intel_crtc->idle_timer); + } + + intel_increase_renderclock(dev, false); + del_timer_sync(&dev_priv->idle_timer); + + mutex_unlock(&dev->struct_mutex); + drm_mode_config_cleanup(dev); } @@ -3420,3 +3917,20 @@ struct drm_encoder *intel_best_encoder(struct drm_connector *connector) return &intel_output->enc; } + +/* + * set vga decode state - true == enable VGA decode + */ +int intel_modeset_vga_set_state(struct drm_device *dev, bool state) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u16 gmch_ctrl; + + pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); + if (state) + gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; + else + gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; + pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); + return 0; +} diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 26a6227c15fe..3ebbbabfe59b 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -117,9 +117,9 @@ struct intel_crtc { uint32_t cursor_addr; u8 lut_r[256], lut_g[256], lut_b[256]; int dpms_mode; - struct intel_framebuffer *fbdev_fb; - /* a mode_set for fbdev users on this crtc */ - struct drm_mode_set mode_set; + bool busy; /* is scanout buffer being updated frequently? */ + struct timer_list idle_timer; + bool lowfreq_avail; }; #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) @@ -138,6 +138,7 @@ extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg); extern bool intel_sdvo_init(struct drm_device *dev, int output_device); extern void intel_dvo_init(struct drm_device *dev); extern void intel_tv_init(struct drm_device *dev); +extern void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj); extern void intel_lvds_init(struct drm_device *dev); extern void intel_dp_init(struct drm_device *dev, int dp_reg); void @@ -178,4 +179,5 @@ extern int intel_framebuffer_create(struct drm_device *dev, struct drm_mode_fb_cmd *mode_cmd, struct drm_framebuffer **fb, struct drm_gem_object *obj); + #endif /* __INTEL_DRV_H__ */ diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c index 1d30802e773e..7ba4a232a97f 100644 --- a/drivers/gpu/drm/i915/intel_fb.c +++ b/drivers/gpu/drm/i915/intel_fb.c @@ -39,339 +39,34 @@ #include "drmP.h" #include "drm.h" #include "drm_crtc.h" +#include "drm_fb_helper.h" #include "intel_drv.h" #include "i915_drm.h" #include "i915_drv.h" struct intelfb_par { - struct drm_device *dev; - struct drm_display_mode *our_mode; + struct drm_fb_helper helper; struct intel_framebuffer *intel_fb; - int crtc_count; - /* crtc currently bound to this */ - uint32_t crtc_ids[2]; + struct drm_display_mode *our_mode; }; -static int intelfb_setcolreg(unsigned regno, unsigned red, unsigned green, - unsigned blue, unsigned transp, - struct fb_info *info) -{ - struct intelfb_par *par = info->par; - struct drm_device *dev = par->dev; - struct drm_crtc *crtc; - int i; - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct drm_mode_set *modeset = &intel_crtc->mode_set; - struct drm_framebuffer *fb = modeset->fb; - - for (i = 0; i < par->crtc_count; i++) - if (crtc->base.id == par->crtc_ids[i]) - break; - - if (i == par->crtc_count) - continue; - - - if (regno > 255) - return 1; - - if (fb->depth == 8) { - intel_crtc_fb_gamma_set(crtc, red, green, blue, regno); - return 0; - } - - if (regno < 16) { - switch (fb->depth) { - case 15: - fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) | - ((green & 0xf800) >> 6) | - ((blue & 0xf800) >> 11); - break; - case 16: - fb->pseudo_palette[regno] = (red & 0xf800) | - ((green & 0xfc00) >> 5) | - ((blue & 0xf800) >> 11); - break; - case 24: - case 32: - fb->pseudo_palette[regno] = ((red & 0xff00) << 8) | - (green & 0xff00) | - ((blue & 0xff00) >> 8); - break; - } - } - } - return 0; -} - -static int intelfb_check_var(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - struct intelfb_par *par = info->par; - struct intel_framebuffer *intel_fb = par->intel_fb; - struct drm_framebuffer *fb = &intel_fb->base; - int depth; - - if (var->pixclock == -1 || !var->pixclock) - return -EINVAL; - - /* Need to resize the fb object !!! */ - if (var->xres > fb->width || var->yres > fb->height) { - DRM_ERROR("Requested width/height is greater than current fb object %dx%d > %dx%d\n",var->xres,var->yres,fb->width,fb->height); - DRM_ERROR("Need resizing code.\n"); - return -EINVAL; - } - - switch (var->bits_per_pixel) { - case 16: - depth = (var->green.length == 6) ? 16 : 15; - break; - case 32: - depth = (var->transp.length > 0) ? 32 : 24; - break; - default: - depth = var->bits_per_pixel; - break; - } - - switch (depth) { - case 8: - var->red.offset = 0; - var->green.offset = 0; - var->blue.offset = 0; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 0; - var->transp.offset = 0; - break; - case 15: - var->red.offset = 10; - var->green.offset = 5; - var->blue.offset = 0; - var->red.length = 5; - var->green.length = 5; - var->blue.length = 5; - var->transp.length = 1; - var->transp.offset = 15; - break; - case 16: - var->red.offset = 11; - var->green.offset = 5; - var->blue.offset = 0; - var->red.length = 5; - var->green.length = 6; - var->blue.length = 5; - var->transp.length = 0; - var->transp.offset = 0; - break; - case 24: - var->red.offset = 16; - var->green.offset = 8; - var->blue.offset = 0; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 0; - var->transp.offset = 0; - break; - case 32: - var->red.offset = 16; - var->green.offset = 8; - var->blue.offset = 0; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 8; - var->transp.offset = 24; - break; - default: - return -EINVAL; - } - - return 0; -} - -/* this will let fbcon do the mode init */ -/* FIXME: take mode config lock? */ -static int intelfb_set_par(struct fb_info *info) -{ - struct intelfb_par *par = info->par; - struct drm_device *dev = par->dev; - struct fb_var_screeninfo *var = &info->var; - int i; - - DRM_DEBUG("%d %d\n", var->xres, var->pixclock); - - if (var->pixclock != -1) { - - DRM_ERROR("PIXEL CLOCK SET\n"); - return -EINVAL; - } else { - struct drm_crtc *crtc; - int ret; - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - - for (i = 0; i < par->crtc_count; i++) - if (crtc->base.id == par->crtc_ids[i]) - break; - - if (i == par->crtc_count) - continue; - - if (crtc->fb == intel_crtc->mode_set.fb) { - mutex_lock(&dev->mode_config.mutex); - ret = crtc->funcs->set_config(&intel_crtc->mode_set); - mutex_unlock(&dev->mode_config.mutex); - if (ret) - return ret; - } - } - return 0; - } -} - -static int intelfb_pan_display(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - struct intelfb_par *par = info->par; - struct drm_device *dev = par->dev; - struct drm_mode_set *modeset; - struct drm_crtc *crtc; - struct intel_crtc *intel_crtc; - int ret = 0; - int i; - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - for (i = 0; i < par->crtc_count; i++) - if (crtc->base.id == par->crtc_ids[i]) - break; - - if (i == par->crtc_count) - continue; - - intel_crtc = to_intel_crtc(crtc); - modeset = &intel_crtc->mode_set; - - modeset->x = var->xoffset; - modeset->y = var->yoffset; - - if (modeset->num_connectors) { - mutex_lock(&dev->mode_config.mutex); - ret = crtc->funcs->set_config(modeset); - mutex_unlock(&dev->mode_config.mutex); - if (!ret) { - info->var.xoffset = var->xoffset; - info->var.yoffset = var->yoffset; - } - } - } - - return ret; -} - -static void intelfb_on(struct fb_info *info) -{ - struct intelfb_par *par = info->par; - struct drm_device *dev = par->dev; - struct drm_crtc *crtc; - struct drm_encoder *encoder; - int i; - - /* - * For each CRTC in this fb, find all associated encoders - * and turn them off, then turn off the CRTC. - */ - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; - - for (i = 0; i < par->crtc_count; i++) - if (crtc->base.id == par->crtc_ids[i]) - break; - - crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); - - /* Found a CRTC on this fb, now find encoders */ - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - if (encoder->crtc == crtc) { - struct drm_encoder_helper_funcs *encoder_funcs; - encoder_funcs = encoder->helper_private; - encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); - } - } - } -} - -static void intelfb_off(struct fb_info *info, int dpms_mode) -{ - struct intelfb_par *par = info->par; - struct drm_device *dev = par->dev; - struct drm_crtc *crtc; - struct drm_encoder *encoder; - int i; - - /* - * For each CRTC in this fb, find all associated encoders - * and turn them off, then turn off the CRTC. - */ - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; - - for (i = 0; i < par->crtc_count; i++) - if (crtc->base.id == par->crtc_ids[i]) - break; - - /* Found a CRTC on this fb, now find encoders */ - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - if (encoder->crtc == crtc) { - struct drm_encoder_helper_funcs *encoder_funcs; - encoder_funcs = encoder->helper_private; - encoder_funcs->dpms(encoder, dpms_mode); - } - } - if (dpms_mode == DRM_MODE_DPMS_OFF) - crtc_funcs->dpms(crtc, dpms_mode); - } -} - -static int intelfb_blank(int blank, struct fb_info *info) -{ - switch (blank) { - case FB_BLANK_UNBLANK: - intelfb_on(info); - break; - case FB_BLANK_NORMAL: - intelfb_off(info, DRM_MODE_DPMS_STANDBY); - break; - case FB_BLANK_HSYNC_SUSPEND: - intelfb_off(info, DRM_MODE_DPMS_STANDBY); - break; - case FB_BLANK_VSYNC_SUSPEND: - intelfb_off(info, DRM_MODE_DPMS_SUSPEND); - break; - case FB_BLANK_POWERDOWN: - intelfb_off(info, DRM_MODE_DPMS_OFF); - break; - } - return 0; -} - static struct fb_ops intelfb_ops = { .owner = THIS_MODULE, - .fb_check_var = intelfb_check_var, - .fb_set_par = intelfb_set_par, - .fb_setcolreg = intelfb_setcolreg, + .fb_check_var = drm_fb_helper_check_var, + .fb_set_par = drm_fb_helper_set_par, + .fb_setcolreg = drm_fb_helper_setcolreg, .fb_fillrect = cfb_fillrect, .fb_copyarea = cfb_copyarea, .fb_imageblit = cfb_imageblit, - .fb_pan_display = intelfb_pan_display, - .fb_blank = intelfb_blank, + .fb_pan_display = drm_fb_helper_pan_display, + .fb_blank = drm_fb_helper_blank, }; +static struct drm_fb_helper_funcs intel_fb_helper_funcs = { + .gamma_set = intel_crtc_fb_gamma_set, +}; + + /** * Curretly it is assumed that the old framebuffer is reused. * @@ -412,25 +107,10 @@ int intelfb_resize(struct drm_device *dev, struct drm_crtc *crtc) } EXPORT_SYMBOL(intelfb_resize); -static struct drm_mode_set kernelfb_mode; - -static int intelfb_panic(struct notifier_block *n, unsigned long ununsed, - void *panic_str) -{ - DRM_ERROR("panic occurred, switching back to text console\n"); - - intelfb_restore(); - return 0; -} - -static struct notifier_block paniced = { - .notifier_call = intelfb_panic, -}; - static int intelfb_create(struct drm_device *dev, uint32_t fb_width, uint32_t fb_height, uint32_t surface_width, uint32_t surface_height, - struct intel_framebuffer **intel_fb_p) + struct drm_framebuffer **fb_p) { struct fb_info *info; struct intelfb_par *par; @@ -479,7 +159,7 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, list_add(&fb->filp_head, &dev->mode_config.fb_kernel_list); intel_fb = to_intel_framebuffer(fb); - *intel_fb_p = intel_fb; + *fb_p = fb; info = framebuffer_alloc(sizeof(struct intelfb_par), device); if (!info) { @@ -489,21 +169,19 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, par = info->par; + par->helper.funcs = &intel_fb_helper_funcs; + par->helper.dev = dev; + ret = drm_fb_helper_init_crtc_count(&par->helper, 2, + INTELFB_CONN_LIMIT); + if (ret) + goto out_unref; + strcpy(info->fix.id, "inteldrmfb"); - info->fix.type = FB_TYPE_PACKED_PIXELS; - info->fix.visual = FB_VISUAL_TRUECOLOR; - info->fix.type_aux = 0; - info->fix.xpanstep = 1; /* doing it in hw */ - info->fix.ypanstep = 1; /* doing it in hw */ - info->fix.ywrapstep = 0; - info->fix.accel = FB_ACCEL_I830; - info->fix.type_aux = 0; info->flags = FBINFO_DEFAULT; info->fbops = &intelfb_ops; - info->fix.line_length = fb->pitch; /* setup aperture base/size for vesafb takeover */ info->aperture_base = dev->mode_config.fb_base; @@ -527,18 +205,8 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, // memset(info->screen_base, 0, size); - info->pseudo_palette = fb->pseudo_palette; - info->var.xres_virtual = fb->width; - info->var.yres_virtual = fb->height; - info->var.bits_per_pixel = fb->bits_per_pixel; - info->var.xoffset = 0; - info->var.yoffset = 0; - info->var.activate = FB_ACTIVATE_NOW; - info->var.height = -1; - info->var.width = -1; - - info->var.xres = fb_width; - info->var.yres = fb_height; + drm_fb_helper_fill_fix(info, fb->pitch); + drm_fb_helper_fill_var(info, fb, fb_width, fb_height); /* FIXME: we really shouldn't expose mmio space at all */ info->fix.mmio_start = pci_resource_start(dev->pdev, mmio_bar); @@ -550,64 +218,9 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, info->pixmap.flags = FB_PIXMAP_SYSTEM; info->pixmap.scan_align = 1; - switch(fb->depth) { - case 8: - info->var.red.offset = 0; - info->var.green.offset = 0; - info->var.blue.offset = 0; - info->var.red.length = 8; /* 8bit DAC */ - info->var.green.length = 8; - info->var.blue.length = 8; - info->var.transp.offset = 0; - info->var.transp.length = 0; - break; - case 15: - info->var.red.offset = 10; - info->var.green.offset = 5; - info->var.blue.offset = 0; - info->var.red.length = 5; - info->var.green.length = 5; - info->var.blue.length = 5; - info->var.transp.offset = 15; - info->var.transp.length = 1; - break; - case 16: - info->var.red.offset = 11; - info->var.green.offset = 5; - info->var.blue.offset = 0; - info->var.red.length = 5; - info->var.green.length = 6; - info->var.blue.length = 5; - info->var.transp.offset = 0; - break; - case 24: - info->var.red.offset = 16; - info->var.green.offset = 8; - info->var.blue.offset = 0; - info->var.red.length = 8; - info->var.green.length = 8; - info->var.blue.length = 8; - info->var.transp.offset = 0; - info->var.transp.length = 0; - break; - case 32: - info->var.red.offset = 16; - info->var.green.offset = 8; - info->var.blue.offset = 0; - info->var.red.length = 8; - info->var.green.length = 8; - info->var.blue.length = 8; - info->var.transp.offset = 24; - info->var.transp.length = 8; - break; - default: - break; - } - fb->fbdev = info; par->intel_fb = intel_fb; - par->dev = dev; /* To allow resizeing without swapping buffers */ DRM_DEBUG("allocated %dx%d fb: 0x%08x, bo %p\n", intel_fb->base.width, @@ -625,307 +238,12 @@ out: return ret; } -static int intelfb_multi_fb_probe_crtc(struct drm_device *dev, struct drm_crtc *crtc) -{ - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct intel_framebuffer *intel_fb; - struct drm_framebuffer *fb; - struct drm_connector *connector; - struct fb_info *info; - struct intelfb_par *par; - struct drm_mode_set *modeset; - unsigned int width, height; - int new_fb = 0; - int ret, i, conn_count; - - if (!drm_helper_crtc_in_use(crtc)) - return 0; - - if (!crtc->desired_mode) - return 0; - - width = crtc->desired_mode->hdisplay; - height = crtc->desired_mode->vdisplay; - - /* is there an fb bound to this crtc already */ - if (!intel_crtc->mode_set.fb) { - ret = intelfb_create(dev, width, height, width, height, &intel_fb); - if (ret) - return -EINVAL; - new_fb = 1; - } else { - fb = intel_crtc->mode_set.fb; - intel_fb = to_intel_framebuffer(fb); - if ((intel_fb->base.width < width) || (intel_fb->base.height < height)) - return -EINVAL; - } - - info = intel_fb->base.fbdev; - par = info->par; - - modeset = &intel_crtc->mode_set; - modeset->fb = &intel_fb->base; - conn_count = 0; - list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - if (connector->encoder) - if (connector->encoder->crtc == modeset->crtc) { - modeset->connectors[conn_count] = connector; - conn_count++; - if (conn_count > INTELFB_CONN_LIMIT) - BUG(); - } - } - - for (i = conn_count; i < INTELFB_CONN_LIMIT; i++) - modeset->connectors[i] = NULL; - - par->crtc_ids[0] = crtc->base.id; - - modeset->num_connectors = conn_count; - if (modeset->crtc->desired_mode) { - if (modeset->mode) - drm_mode_destroy(dev, modeset->mode); - modeset->mode = drm_mode_duplicate(dev, - modeset->crtc->desired_mode); - } - - par->crtc_count = 1; - - if (new_fb) { - info->var.pixclock = -1; - if (register_framebuffer(info) < 0) - return -EINVAL; - } else - intelfb_set_par(info); - - DRM_INFO("fb%d: %s frame buffer device\n", info->node, - info->fix.id); - - /* Switch back to kernel console on panic */ - kernelfb_mode = *modeset; - atomic_notifier_chain_register(&panic_notifier_list, &paniced); - DRM_DEBUG("registered panic notifier\n"); - - return 0; -} - -static int intelfb_multi_fb_probe(struct drm_device *dev) -{ - - struct drm_crtc *crtc; - int ret = 0; - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - ret = intelfb_multi_fb_probe_crtc(dev, crtc); - if (ret) - return ret; - } - return ret; -} - -static int intelfb_single_fb_probe(struct drm_device *dev) -{ - struct drm_crtc *crtc; - struct drm_connector *connector; - unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1; - unsigned int surface_width = 0, surface_height = 0; - int new_fb = 0; - int crtc_count = 0; - int ret, i, conn_count = 0; - struct intel_framebuffer *intel_fb; - struct fb_info *info; - struct intelfb_par *par; - struct drm_mode_set *modeset = NULL; - - DRM_DEBUG("\n"); - - /* Get a count of crtcs now in use and new min/maxes width/heights */ - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - if (!drm_helper_crtc_in_use(crtc)) - continue; - - crtc_count++; - if (!crtc->desired_mode) - continue; - - /* Smallest mode determines console size... */ - if (crtc->desired_mode->hdisplay < fb_width) - fb_width = crtc->desired_mode->hdisplay; - - if (crtc->desired_mode->vdisplay < fb_height) - fb_height = crtc->desired_mode->vdisplay; - - /* ... but largest for memory allocation dimensions */ - if (crtc->desired_mode->hdisplay > surface_width) - surface_width = crtc->desired_mode->hdisplay; - - if (crtc->desired_mode->vdisplay > surface_height) - surface_height = crtc->desired_mode->vdisplay; - } - - if (crtc_count == 0 || fb_width == -1 || fb_height == -1) { - /* hmm everyone went away - assume VGA cable just fell out - and will come back later. */ - DRM_DEBUG("no CRTCs available?\n"); - return 0; - } - -//fail - /* Find the fb for our new config */ - if (list_empty(&dev->mode_config.fb_kernel_list)) { - DRM_DEBUG("creating new fb (console size %dx%d, " - "buffer size %dx%d)\n", fb_width, fb_height, - surface_width, surface_height); - ret = intelfb_create(dev, fb_width, fb_height, surface_width, - surface_height, &intel_fb); - if (ret) - return -EINVAL; - new_fb = 1; - } else { - struct drm_framebuffer *fb; - - fb = list_first_entry(&dev->mode_config.fb_kernel_list, - struct drm_framebuffer, filp_head); - intel_fb = to_intel_framebuffer(fb); - - /* if someone hotplugs something bigger than we have already - * allocated, we are pwned. As really we can't resize an - * fbdev that is in the wild currently due to fbdev not really - * being designed for the lower layers moving stuff around - * under it. - * - so in the grand style of things - punt. - */ - if ((fb->width < surface_width) || - (fb->height < surface_height)) { - DRM_ERROR("fb not large enough for console\n"); - return -EINVAL; - } - } -// fail - - info = intel_fb->base.fbdev; - par = info->par; - - crtc_count = 0; - /* - * For each CRTC, set up the connector list for the CRTC's mode - * set configuration. - */ - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - - modeset = &intel_crtc->mode_set; - modeset->fb = &intel_fb->base; - conn_count = 0; - list_for_each_entry(connector, &dev->mode_config.connector_list, - head) { - if (!connector->encoder) - continue; - - if(connector->encoder->crtc == modeset->crtc) { - modeset->connectors[conn_count++] = connector; - if (conn_count > INTELFB_CONN_LIMIT) - BUG(); - } - } - - /* Zero out remaining connector pointers */ - for (i = conn_count; i < INTELFB_CONN_LIMIT; i++) - modeset->connectors[i] = NULL; - - par->crtc_ids[crtc_count++] = crtc->base.id; - - modeset->num_connectors = conn_count; - if (modeset->crtc->desired_mode) { - if (modeset->mode) - drm_mode_destroy(dev, modeset->mode); - modeset->mode = drm_mode_duplicate(dev, - modeset->crtc->desired_mode); - } - } - par->crtc_count = crtc_count; - - if (new_fb) { - info->var.pixclock = -1; - if (register_framebuffer(info) < 0) - return -EINVAL; - } else - intelfb_set_par(info); - - DRM_INFO("fb%d: %s frame buffer device\n", info->node, - info->fix.id); - - /* Switch back to kernel console on panic */ - kernelfb_mode = *modeset; - atomic_notifier_chain_register(&panic_notifier_list, &paniced); - DRM_DEBUG("registered panic notifier\n"); - - return 0; -} - -/** - * intelfb_restore - restore the framebuffer console (kernel) config - * - * Restore's the kernel's fbcon mode, used for lastclose & panic paths. - */ -void intelfb_restore(void) -{ - int ret; - if ((ret = drm_crtc_helper_set_config(&kernelfb_mode)) != 0) { - DRM_ERROR("Failed to restore crtc configuration: %d\n", - ret); - } -} - -static void intelfb_restore_work_fn(struct work_struct *ignored) -{ - intelfb_restore(); -} -static DECLARE_WORK(intelfb_restore_work, intelfb_restore_work_fn); - -static void intelfb_sysrq(int dummy1, struct tty_struct *dummy3) -{ - schedule_work(&intelfb_restore_work); -} - -static struct sysrq_key_op sysrq_intelfb_restore_op = { - .handler = intelfb_sysrq, - .help_msg = "force-fb(V)", - .action_msg = "Restore framebuffer console", -}; - int intelfb_probe(struct drm_device *dev) { int ret; DRM_DEBUG("\n"); - - /* something has changed in the lower levels of hell - deal with it - here */ - - /* two modes : a) 1 fb to rule all crtcs. - b) one fb per crtc. - two actions 1) new connected device - 2) device removed. - case a/1 : if the fb surface isn't big enough - resize the surface fb. - if the fb size isn't big enough - resize fb into surface. - if everything big enough configure the new crtc/etc. - case a/2 : undo the configuration - possibly resize down the fb to fit the new configuration. - case b/1 : see if it is on a new crtc - setup a new fb and add it. - case b/2 : teardown the new fb. - */ - - /* mode a first */ - /* search for an fb */ - if (i915_fbpercrtc == 1) { - ret = intelfb_multi_fb_probe(dev); - } else { - ret = intelfb_single_fb_probe(dev); - } - - register_sysrq_key('v', &sysrq_intelfb_restore_op); - + ret = drm_fb_helper_single_fb_probe(dev, intelfb_create); return ret; } EXPORT_SYMBOL(intelfb_probe); @@ -940,13 +258,14 @@ int intelfb_remove(struct drm_device *dev, struct drm_framebuffer *fb) info = fb->fbdev; if (info) { + struct intelfb_par *par = info->par; unregister_framebuffer(info); iounmap(info->screen_base); + if (info->par) + drm_fb_helper_free(&par->helper); framebuffer_release(info); } - atomic_notifier_chain_unregister(&panic_notifier_list, &paniced); - memset(&kernelfb_mode, 0, sizeof(struct drm_mode_set)); return 0; } EXPORT_SYMBOL(intelfb_remove); diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 62b8bead7652..c7eab724c418 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -42,11 +42,11 @@ void intel_i2c_quirk_set(struct drm_device *dev, bool enable) if (!IS_IGD(dev)) return; if (enable) - I915_WRITE(CG_2D_DIS, - I915_READ(CG_2D_DIS) | DPCUNIT_CLOCK_GATE_DISABLE); + I915_WRITE(DSPCLK_GATE_D, + I915_READ(DSPCLK_GATE_D) | DPCUNIT_CLOCK_GATE_DISABLE); else - I915_WRITE(CG_2D_DIS, - I915_READ(CG_2D_DIS) & (~DPCUNIT_CLOCK_GATE_DISABLE)); + I915_WRITE(DSPCLK_GATE_D, + I915_READ(DSPCLK_GATE_D) & (~DPCUNIT_CLOCK_GATE_DISABLE)); } /* diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 8df02ef89261..dafc0da1c256 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -38,16 +38,6 @@ #include "i915_drv.h" #include -#define I915_LVDS "i915_lvds" - -/* - * the following four scaling options are defined. - * #define DRM_MODE_SCALE_NON_GPU 0 - * #define DRM_MODE_SCALE_FULLSCREEN 1 - * #define DRM_MODE_SCALE_NO_SCALE 2 - * #define DRM_MODE_SCALE_ASPECT 3 - */ - /* Private structure for the integrated LVDS support */ struct intel_lvds_priv { int fitting_mode; @@ -336,7 +326,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, I915_WRITE(BCLRPAT_B, 0); switch (lvds_priv->fitting_mode) { - case DRM_MODE_SCALE_NO_SCALE: + case DRM_MODE_SCALE_CENTER: /* * For centered modes, we have to calculate border widths & * heights and modify the values programmed into the CRTC. @@ -672,9 +662,8 @@ static int intel_lvds_set_property(struct drm_connector *connector, connector->encoder) { struct drm_crtc *crtc = connector->encoder->crtc; struct intel_lvds_priv *lvds_priv = intel_output->dev_priv; - if (value == DRM_MODE_SCALE_NON_GPU) { - DRM_DEBUG_KMS(I915_LVDS, - "non_GPU property is unsupported\n"); + if (value == DRM_MODE_SCALE_NONE) { + DRM_DEBUG_KMS("no scaling not supported\n"); return 0; } if (lvds_priv->fitting_mode == value) { @@ -731,8 +720,7 @@ static const struct drm_encoder_funcs intel_lvds_enc_funcs = { static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) { - DRM_DEBUG_KMS(I915_LVDS, - "Skipping LVDS initialization for %s\n", id->ident); + DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident); return 1; } @@ -1027,7 +1015,7 @@ out: return; failed: - DRM_DEBUG_KMS(I915_LVDS, "No LVDS modes found, disabling.\n"); + DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); if (intel_output->ddc_bus) intel_i2c_destroy(intel_output->ddc_bus); drm_connector_cleanup(connector); diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index d3b74ba62b4a..0bf28efcf2c1 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -37,7 +37,19 @@ #include "intel_sdvo_regs.h" #undef SDVO_DEBUG -#define I915_SDVO "i915_sdvo" + +static char *tv_format_names[] = { + "NTSC_M" , "NTSC_J" , "NTSC_443", + "PAL_B" , "PAL_D" , "PAL_G" , + "PAL_H" , "PAL_I" , "PAL_M" , + "PAL_N" , "PAL_NC" , "PAL_60" , + "SECAM_B" , "SECAM_D" , "SECAM_G" , + "SECAM_K" , "SECAM_K1", "SECAM_L" , + "SECAM_60" +}; + +#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) + struct intel_sdvo_priv { u8 slave_addr; @@ -71,6 +83,15 @@ struct intel_sdvo_priv { */ bool is_tv; + /* This is for current tv format name */ + char *tv_format_name; + + /* This contains all current supported TV format */ + char *tv_format_supported[TV_FORMAT_NUM]; + int format_supported_num; + struct drm_property *tv_format_property; + struct drm_property *tv_format_name_property[TV_FORMAT_NUM]; + /** * This is set if we treat the device as HDMI, instead of DVI. */ @@ -97,14 +118,6 @@ struct intel_sdvo_priv { */ struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions; - /** - * Current selected TV format. - * - * This is stored in the same structure that's passed to the device, for - * convenience. - */ - struct intel_sdvo_tv_format tv_format; - /* * supported encoding mode, used to determine whether HDMI is * supported @@ -114,6 +127,9 @@ struct intel_sdvo_priv { /* DDC bus used by this SDVO output */ uint8_t ddc_bus; + /* Mac mini hack -- use the same DDC as the analog connector */ + struct i2c_adapter *analog_ddc_bus; + int save_sdvo_mult; u16 save_active_outputs; struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2; @@ -188,7 +204,7 @@ static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr, return true; } - DRM_DEBUG("i2c transfer returned %d\n", ret); + DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); return false; } @@ -298,7 +314,7 @@ static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd, struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; int i; - DRM_DEBUG_KMS(I915_SDVO, "%s: W: %02X ", + DRM_DEBUG_KMS("%s: W: %02X ", SDVO_NAME(sdvo_priv), cmd); for (i = 0; i < args_len; i++) DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); @@ -351,7 +367,7 @@ static void intel_sdvo_debug_response(struct intel_output *intel_output, struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; int i; - DRM_DEBUG_KMS(I915_SDVO, "%s: R: ", SDVO_NAME(sdvo_priv)); + DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv)); for (i = 0; i < response_len; i++) DRM_LOG_KMS("%02X ", ((u8 *)response)[i]); for (; i < 8; i++) @@ -668,10 +684,10 @@ static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output) status = intel_sdvo_read_response(intel_output, &response, 1); if (status != SDVO_CMD_STATUS_SUCCESS) { - DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n"); + DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n"); return SDVO_CLOCK_RATE_MULT_1X; } else { - DRM_DEBUG("Current clock rate multiplier: %d\n", response); + DRM_DEBUG_KMS("Current clock rate multiplier: %d\n", response); } return response; @@ -945,23 +961,28 @@ static void intel_sdvo_set_avi_infoframe(struct intel_output *output, static void intel_sdvo_set_tv_format(struct intel_output *output) { + + struct intel_sdvo_tv_format format; struct intel_sdvo_priv *sdvo_priv = output->dev_priv; - struct intel_sdvo_tv_format *format, unset; - u8 status; + uint32_t format_map, i; + uint8_t status; - format = &sdvo_priv->tv_format; - memset(&unset, 0, sizeof(unset)); - if (memcmp(format, &unset, sizeof(*format))) { - DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n", - SDVO_NAME(sdvo_priv)); - format->ntsc_m = 1; - intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format, - sizeof(*format)); - status = intel_sdvo_read_response(output, NULL, 0); - if (status != SDVO_CMD_STATUS_SUCCESS) - DRM_DEBUG("%s: Failed to set TV format\n", - SDVO_NAME(sdvo_priv)); - } + for (i = 0; i < TV_FORMAT_NUM; i++) + if (tv_format_names[i] == sdvo_priv->tv_format_name) + break; + + format_map = 1 << i; + memset(&format, 0, sizeof(format)); + memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ? + sizeof(format) : sizeof(format_map)); + + intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, &format_map, + sizeof(format)); + + status = intel_sdvo_read_response(output, NULL, 0); + if (status != SDVO_CMD_STATUS_SUCCESS) + DRM_DEBUG("%s: Failed to set TV format\n", + SDVO_NAME(sdvo_priv)); } static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, @@ -1230,8 +1251,8 @@ static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) * a given it the status is a success, we succeeded. */ if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { - DRM_DEBUG("First %s output reported failure to sync\n", - SDVO_NAME(sdvo_priv)); + DRM_DEBUG_KMS("First %s output reported failure to " + "sync\n", SDVO_NAME(sdvo_priv)); } if (0) @@ -1326,8 +1347,8 @@ static void intel_sdvo_restore(struct drm_connector *connector) intel_wait_for_vblank(dev); status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2); if (status == SDVO_CMD_STATUS_SUCCESS && !input1) - DRM_DEBUG("First %s output reported failure to sync\n", - SDVO_NAME(sdvo_priv)); + DRM_DEBUG_KMS("First %s output reported failure to " + "sync\n", SDVO_NAME(sdvo_priv)); } intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs); @@ -1405,7 +1426,7 @@ int intel_sdvo_supports_hotplug(struct drm_connector *connector) u8 response[2]; u8 status; struct intel_output *intel_output; - DRM_DEBUG("\n"); + DRM_DEBUG_KMS("\n"); if (!connector) return 0; @@ -1478,6 +1499,36 @@ intel_sdvo_multifunc_encoder(struct intel_output *intel_output) return (caps > 1); } +static struct drm_connector * +intel_find_analog_connector(struct drm_device *dev) +{ + struct drm_connector *connector; + struct intel_output *intel_output; + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + intel_output = to_intel_output(connector); + if (intel_output->type == INTEL_OUTPUT_ANALOG) + return connector; + } + return NULL; +} + +static int +intel_analog_is_connected(struct drm_device *dev) +{ + struct drm_connector *analog_connector; + analog_connector = intel_find_analog_connector(dev); + + if (!analog_connector) + return false; + + if (analog_connector->funcs->detect(analog_connector) == + connector_status_disconnected) + return false; + + return true; +} + enum drm_connector_status intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response) { @@ -1488,6 +1539,15 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response) edid = drm_get_edid(&intel_output->base, intel_output->ddc_bus); + + /* when there is no edid and no monitor is connected with VGA + * port, try to use the CRT ddc to read the EDID for DVI-connector + */ + if (edid == NULL && + sdvo_priv->analog_ddc_bus && + !intel_analog_is_connected(intel_output->base.dev)) + edid = drm_get_edid(&intel_output->base, + sdvo_priv->analog_ddc_bus); if (edid != NULL) { /* Don't report the output as connected if it's a DVI-I * connector with a non-digital EDID coming out. @@ -1516,10 +1576,11 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect struct intel_output *intel_output = to_intel_output(connector); struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; - intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0); + intel_sdvo_write_cmd(intel_output, + SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0); status = intel_sdvo_read_response(intel_output, &response, 2); - DRM_DEBUG("SDVO response %d %d\n", response & 0xff, response >> 8); + DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8); if (status != SDVO_CMD_STATUS_SUCCESS) return connector_status_unknown; @@ -1540,50 +1601,32 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) { struct intel_output *intel_output = to_intel_output(connector); + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + int num_modes; /* set the bus switch and get the modes */ - intel_ddc_get_modes(intel_output); + num_modes = intel_ddc_get_modes(intel_output); -#if 0 - struct drm_device *dev = encoder->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - /* Mac mini hack. On this device, I get DDC through the analog, which - * load-detects as disconnected. I fail to DDC through the SDVO DDC, - * but it does load-detect as connected. So, just steal the DDC bits - * from analog when we fail at finding it the right way. + /* + * Mac mini hack. On this device, the DVI-I connector shares one DDC + * link between analog and digital outputs. So, if the regular SDVO + * DDC fails, check to see if the analog output is disconnected, in + * which case we'll look there for the digital DDC data. */ - crt = xf86_config->output[0]; - intel_output = crt->driver_private; - if (intel_output->type == I830_OUTPUT_ANALOG && - crt->funcs->detect(crt) == XF86OutputStatusDisconnected) { - I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A"); - edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus); - xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true); - } - if (edid_mon) { - xf86OutputSetEDID(output, edid_mon); - modes = xf86OutputGetEDIDModes(output); - } -#endif -} + if (num_modes == 0 && + sdvo_priv->analog_ddc_bus && + !intel_analog_is_connected(intel_output->base.dev)) { + struct i2c_adapter *digital_ddc_bus; -/** - * This function checks the current TV format, and chooses a default if - * it hasn't been set. - */ -static void -intel_sdvo_check_tv_format(struct intel_output *output) -{ - struct intel_sdvo_priv *dev_priv = output->dev_priv; - struct intel_sdvo_tv_format format; - uint8_t status; + /* Switch to the analog ddc bus and try that + */ + digital_ddc_bus = intel_output->ddc_bus; + intel_output->ddc_bus = sdvo_priv->analog_ddc_bus; - intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0); - status = intel_sdvo_read_response(output, &format, sizeof(format)); - if (status != SDVO_CMD_STATUS_SUCCESS) - return; + (void) intel_ddc_get_modes(intel_output); - memcpy(&dev_priv->tv_format, &format, sizeof(format)); + intel_output->ddc_bus = digital_ddc_bus; + } } /* @@ -1656,17 +1699,26 @@ static void intel_sdvo_get_tv_modes(struct drm_connector *connector) struct intel_output *output = to_intel_output(connector); struct intel_sdvo_priv *sdvo_priv = output->dev_priv; struct intel_sdvo_sdtv_resolution_request tv_res; - uint32_t reply = 0; + uint32_t reply = 0, format_map = 0; + int i; uint8_t status; - int i = 0; - intel_sdvo_check_tv_format(output); /* Read the list of supported input resolutions for the selected TV * format. */ - memset(&tv_res, 0, sizeof(tv_res)); - memcpy(&tv_res, &sdvo_priv->tv_format, sizeof(tv_res)); + for (i = 0; i < TV_FORMAT_NUM; i++) + if (tv_format_names[i] == sdvo_priv->tv_format_name) + break; + + format_map = (1 << i); + memcpy(&tv_res, &format_map, + sizeof(struct intel_sdvo_sdtv_resolution_request) > + sizeof(format_map) ? sizeof(format_map) : + sizeof(struct intel_sdvo_sdtv_resolution_request)); + + intel_sdvo_set_target_output(output, sdvo_priv->controlled_output); + intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, &tv_res, sizeof(tv_res)); status = intel_sdvo_read_response(output, &reply, 3); @@ -1681,6 +1733,7 @@ static void intel_sdvo_get_tv_modes(struct drm_connector *connector) if (nmode) drm_mode_probed_add(connector, nmode); } + } static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) @@ -1748,17 +1801,62 @@ static void intel_sdvo_destroy(struct drm_connector *connector) intel_i2c_destroy(intel_output->i2c_bus); if (intel_output->ddc_bus) intel_i2c_destroy(intel_output->ddc_bus); + if (sdvo_priv->analog_ddc_bus) + intel_i2c_destroy(sdvo_priv->analog_ddc_bus); if (sdvo_priv->sdvo_lvds_fixed_mode != NULL) drm_mode_destroy(connector->dev, sdvo_priv->sdvo_lvds_fixed_mode); + if (sdvo_priv->tv_format_property) + drm_property_destroy(connector->dev, + sdvo_priv->tv_format_property); + drm_sysfs_connector_remove(connector); drm_connector_cleanup(connector); kfree(intel_output); } +static int +intel_sdvo_set_property(struct drm_connector *connector, + struct drm_property *property, + uint64_t val) +{ + struct intel_output *intel_output = to_intel_output(connector); + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + struct drm_encoder *encoder = &intel_output->enc; + struct drm_crtc *crtc = encoder->crtc; + int ret = 0; + bool changed = false; + + ret = drm_connector_property_set_value(connector, property, val); + if (ret < 0) + goto out; + + if (property == sdvo_priv->tv_format_property) { + if (val >= TV_FORMAT_NUM) { + ret = -EINVAL; + goto out; + } + if (sdvo_priv->tv_format_name == + sdvo_priv->tv_format_supported[val]) + goto out; + + sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[val]; + changed = true; + } else { + ret = -EINVAL; + goto out; + } + + if (changed && crtc) + drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, + crtc->y, crtc->fb); +out: + return ret; +} + static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { .dpms = intel_sdvo_dpms, .mode_fixup = intel_sdvo_mode_fixup, @@ -1773,6 +1871,7 @@ static const struct drm_connector_funcs intel_sdvo_connector_funcs = { .restore = intel_sdvo_restore, .detect = intel_sdvo_detect, .fill_modes = drm_helper_probe_single_connector_modes, + .set_property = intel_sdvo_set_property, .destroy = intel_sdvo_destroy, }; @@ -2013,10 +2112,9 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags) sdvo_priv->controlled_output = 0; memcpy(bytes, &sdvo_priv->caps.output_flags, 2); - DRM_DEBUG_KMS(I915_SDVO, - "%s: Unknown SDVO output type (0x%02x%02x)\n", - SDVO_NAME(sdvo_priv), - bytes[0], bytes[1]); + DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", + SDVO_NAME(sdvo_priv), + bytes[0], bytes[1]); ret = false; } intel_output->crtc_mask = (1 << 0) | (1 << 1); @@ -2029,6 +2127,55 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags) } +static void intel_sdvo_tv_create_property(struct drm_connector *connector) +{ + struct intel_output *intel_output = to_intel_output(connector); + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + struct intel_sdvo_tv_format format; + uint32_t format_map, i; + uint8_t status; + + intel_sdvo_set_target_output(intel_output, + sdvo_priv->controlled_output); + + intel_sdvo_write_cmd(intel_output, + SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0); + status = intel_sdvo_read_response(intel_output, + &format, sizeof(format)); + if (status != SDVO_CMD_STATUS_SUCCESS) + return; + + memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ? + sizeof(format_map) : sizeof(format)); + + if (format_map == 0) + return; + + sdvo_priv->format_supported_num = 0; + for (i = 0 ; i < TV_FORMAT_NUM; i++) + if (format_map & (1 << i)) { + sdvo_priv->tv_format_supported + [sdvo_priv->format_supported_num++] = + tv_format_names[i]; + } + + + sdvo_priv->tv_format_property = + drm_property_create( + connector->dev, DRM_MODE_PROP_ENUM, + "mode", sdvo_priv->format_supported_num); + + for (i = 0; i < sdvo_priv->format_supported_num; i++) + drm_property_add_enum( + sdvo_priv->tv_format_property, i, + i, sdvo_priv->tv_format_supported[i]); + + sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[0]; + drm_connector_attach_property( + connector, sdvo_priv->tv_format_property, 0); + +} + bool intel_sdvo_init(struct drm_device *dev, int output_device) { struct drm_connector *connector; @@ -2066,18 +2213,22 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device) /* Read the regs to test if we can talk to the device */ for (i = 0; i < 0x40; i++) { if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) { - DRM_DEBUG_KMS(I915_SDVO, - "No SDVO device found on SDVO%c\n", + DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", output_device == SDVOB ? 'B' : 'C'); goto err_i2c; } } /* setup the DDC bus. */ - if (output_device == SDVOB) + if (output_device == SDVOB) { intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS"); - else + sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA, + "SDVOB/VGA DDC BUS"); + } else { intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS"); + sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA, + "SDVOC/VGA DDC BUS"); + } if (intel_output->ddc_bus == NULL) goto err_i2c; @@ -2090,7 +2241,7 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device) if (intel_sdvo_output_setup(intel_output, sdvo_priv->caps.output_flags) != true) { - DRM_DEBUG("SDVO output failed to setup on SDVO%c\n", + DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", output_device == SDVOB ? 'B' : 'C'); goto err_i2c; } @@ -2111,6 +2262,8 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device) drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs); drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc); + if (sdvo_priv->is_tv) + intel_sdvo_tv_create_property(connector); drm_sysfs_connector_add(connector); intel_sdvo_select_ddc_bus(sdvo_priv); @@ -2123,7 +2276,7 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device) &sdvo_priv->pixel_clock_max); - DRM_DEBUG_KMS(I915_SDVO, "%s device VID/DID: %02X:%02X.%02X, " + DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n", @@ -2143,6 +2296,8 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device) return true; err_i2c: + if (sdvo_priv->analog_ddc_bus != NULL) + intel_i2c_destroy(sdvo_priv->analog_ddc_bus); if (intel_output->ddc_bus != NULL) intel_i2c_destroy(intel_output->ddc_bus); if (intel_output->i2c_bus != NULL) diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index 5b1c9e9fdba0..c64eab493fb0 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c @@ -1437,6 +1437,35 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct intel_output *intel_output) return type; } +/* + * Here we set accurate tv format according to connector type + * i.e Component TV should not be assigned by NTSC or PAL + */ +static void intel_tv_find_better_format(struct drm_connector *connector) +{ + struct intel_output *intel_output = to_intel_output(connector); + struct intel_tv_priv *tv_priv = intel_output->dev_priv; + const struct tv_mode *tv_mode = intel_tv_mode_find(intel_output); + int i; + + if ((tv_priv->type == DRM_MODE_CONNECTOR_Component) == + tv_mode->component_only) + return; + + + for (i = 0; i < sizeof(tv_modes) / sizeof(*tv_modes); i++) { + tv_mode = tv_modes + i; + + if ((tv_priv->type == DRM_MODE_CONNECTOR_Component) == + tv_mode->component_only) + break; + } + + tv_priv->tv_format = tv_mode->name; + drm_connector_property_set_value(connector, + connector->dev->mode_config.tv_mode_property, i); +} + /** * Detect the TV connection. * @@ -1473,6 +1502,7 @@ intel_tv_detect(struct drm_connector *connector) if (type < 0) return connector_status_disconnected; + intel_tv_find_better_format(connector); return connector_status_connected; } diff --git a/drivers/gpu/drm/mga/mga_dma.c b/drivers/gpu/drm/mga/mga_dma.c index 6c67a02910c8..3c917fb3a60b 100644 --- a/drivers/gpu/drm/mga/mga_dma.c +++ b/drivers/gpu/drm/mga/mga_dma.c @@ -444,7 +444,7 @@ static int mga_do_agp_dma_bootstrap(struct drm_device * dev, { drm_mga_private_t *const dev_priv = (drm_mga_private_t *) dev->dev_private; - unsigned int warp_size = mga_warp_microcode_size(dev_priv); + unsigned int warp_size = MGA_WARP_UCODE_SIZE; int err; unsigned offset; const unsigned secondary_size = dma_bs->secondary_bin_count @@ -619,7 +619,7 @@ static int mga_do_pci_dma_bootstrap(struct drm_device * dev, { drm_mga_private_t *const dev_priv = (drm_mga_private_t *) dev->dev_private; - unsigned int warp_size = mga_warp_microcode_size(dev_priv); + unsigned int warp_size = MGA_WARP_UCODE_SIZE; unsigned int primary_size; unsigned int bin_count; int err; diff --git a/drivers/gpu/drm/mga/mga_drv.h b/drivers/gpu/drm/mga/mga_drv.h index 3d264f288237..be6c6b9b0e89 100644 --- a/drivers/gpu/drm/mga/mga_drv.h +++ b/drivers/gpu/drm/mga/mga_drv.h @@ -177,7 +177,6 @@ extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv); extern int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf); /* mga_warp.c */ -extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv); extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv); extern int mga_warp_init(drm_mga_private_t * dev_priv); diff --git a/drivers/gpu/drm/mga/mga_ucode.h b/drivers/gpu/drm/mga/mga_ucode.h deleted file mode 100644 index b611e27470e1..000000000000 --- a/drivers/gpu/drm/mga/mga_ucode.h +++ /dev/null @@ -1,11645 +0,0 @@ -/* mga_ucode.h -- Matrox G200/G400 WARP engine microcode -*- linux-c -*- - * Created: Thu Jan 11 21:20:43 2001 by gareth@valinux.com - * - * Copyright 1999 Matrox Graphics Inc. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * MATROX GRAPHICS INC., OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE - * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Kernel-based WARP engine management: - * Gareth Hughes - */ - -/* - * WARP pipes are named according to the functions they perform, where: - * - * - T stands for computation of texture stage 0 - * - T2 stands for computation of both texture stage 0 and texture stage 1 - * - G stands for computation of triangle intensity (Gouraud interpolation) - * - Z stands for computation of Z buffer interpolation - * - S stands for computation of specular highlight - * - A stands for computation of the alpha channel - * - F stands for computation of vertex fog interpolation - */ - -static unsigned char warp_g200_tgz[] = { - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x72, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x60, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 0x29, 0x30, - 0x48, 0x3C, 0x48, 0xAD, - - 0x2B, 0x72, - 0xC2, 0xE1, - 0x2C, 0xC0, 0x44, 0xC2, - - 0x05, 0x24, 0x34, 0xBF, - 0x0D, 0x24, 0x2C, 0xBF, - - 0x2D, 0x46, 0x4E, 0xBF, - 0x25, 0x46, 0x56, 0xBF, - - 0x20, 0x1D, 0x6F, 0x8F, - 0x32, 0x3E, 0x5F, 0xE9, - - 0x3E, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x30, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x33, 0x1E, 0x5F, 0xE9, - - 0x05, 0x44, 0x54, 0xB2, - 0x0D, 0x44, 0x4C, 0xB2, - - 0x19, 0xC0, 0xB0, 0xE8, - 0x34, 0xC0, 0x44, 0xC4, - - 0x33, 0x73, - 0x00, 0xE0, - 0x3E, 0x62, 0x57, 0x9F, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0xE0, - 0x0D, 0x20, - - 0x84, 0x3E, 0x58, 0xE9, - 0x28, 0x1D, 0x6F, 0x8F, - - 0x05, 0x20, - 0x00, 0xE0, - 0x85, 0x1E, 0x58, 0xE9, - - 0x9B, 0x3B, 0x33, 0xDF, - 0x20, 0x20, 0x42, 0xAF, - - 0x30, 0x42, 0x56, 0x9F, - 0x80, 0x3E, 0x57, 0xE9, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x30, 0x80, 0x5F, 0xE9, - - 0x28, 0x28, 0x24, 0xAF, - 0x81, 0x1E, 0x57, 0xE9, - - 0x05, 0x47, 0x57, 0xBF, - 0x0D, 0x47, 0x4F, 0xBF, - - 0x88, 0x80, 0x58, 0xE9, - 0x1B, 0x29, 0x1B, 0xDF, - - 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x03, 0x80, 0x0A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x57, 0x39, 0x20, 0xE9, - 0x28, 0x19, 0x60, 0xEC, - - 0x2B, 0x32, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0xB3, 0x05, - 0x00, 0xE0, - 0x16, 0x28, 0x20, 0xE9, - - 0x23, 0x3B, 0x33, 0xAD, - 0x1E, 0x2B, 0x20, 0xE9, - - 0x1C, 0x80, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x85, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x84, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x82, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x7F, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g200_tgza[] = { - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x7D, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x6B, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 0x29, 0x30, - 0x48, 0x3C, 0x48, 0xAD, - - 0x2B, 0x72, - 0xC2, 0xE1, - 0x2C, 0xC0, 0x44, 0xC2, - - 0x05, 0x24, 0x34, 0xBF, - 0x0D, 0x24, 0x2C, 0xBF, - - 0x2D, 0x46, 0x4E, 0xBF, - 0x25, 0x46, 0x56, 0xBF, - - 0x20, 0x1D, 0x6F, 0x8F, - 0x32, 0x3E, 0x5F, 0xE9, - - 0x3E, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x30, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x33, 0x1E, 0x5F, 0xE9, - - 0x05, 0x44, 0x54, 0xB2, - 0x0D, 0x44, 0x4C, 0xB2, - - 0x19, 0xC0, 0xB0, 0xE8, - 0x34, 0xC0, 0x44, 0xC4, - - 0x33, 0x73, - 0x00, 0xE0, - 0x3E, 0x62, 0x57, 0x9F, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0xE0, - 0x0D, 0x20, - - 0x84, 0x3E, 0x58, 0xE9, - 0x28, 0x1D, 0x6F, 0x8F, - - 0x05, 0x20, - 0x00, 0xE0, - 0x85, 0x1E, 0x58, 0xE9, - - 0x9B, 0x3B, 0x33, 0xDF, - 0x20, 0x20, 0x42, 0xAF, - - 0x30, 0x42, 0x56, 0x9F, - 0x80, 0x3E, 0x57, 0xE9, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x30, 0x80, 0x5F, 0xE9, - - 0x28, 0x28, 0x24, 0xAF, - 0x81, 0x1E, 0x57, 0xE9, - - 0x05, 0x47, 0x57, 0xBF, - 0x0D, 0x47, 0x4F, 0xBF, - - 0x88, 0x80, 0x58, 0xE9, - 0x1B, 0x29, 0x1B, 0xDF, - - 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x2D, 0x44, 0x4C, 0xB6, - 0x25, 0x44, 0x54, 0xB6, - - 0x03, 0x80, 0x2A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x2D, 0x20, - 0x25, 0x20, - 0x07, 0xC0, 0x44, 0xC6, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x1F, 0x62, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x3F, 0x3D, 0x5D, 0x9F, - 0x00, 0xE0, - 0x07, 0x20, - - 0x00, 0x80, 0x00, 0xE8, - 0x28, 0x19, 0x60, 0xEC, - - 0xB3, 0x05, - 0x00, 0xE0, - 0x00, 0x80, 0x00, 0xE8, - - 0x23, 0x3B, 0x33, 0xAD, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0x26, 0x1F, 0xDF, - 0x9D, 0x1F, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x9E, 0x3F, 0x4F, 0xE9, - - 0x07, 0x07, 0x1F, 0xAF, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x9C, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x57, 0x39, 0x20, 0xE9, - - 0x16, 0x28, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0x1E, 0x2B, 0x20, 0xE9, - 0x2B, 0x32, 0x20, 0xE9, - - 0x1C, 0x23, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x7A, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x79, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x77, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x74, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g200_tgzaf[] = { - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x83, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x21, 0x45, 0x80, 0xE8, - 0x1A, 0x4D, 0x80, 0xE8, - - 0x31, 0x55, 0x80, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x6F, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 0x29, 0x30, - 0x48, 0x3C, 0x48, 0xAD, - - 0x2B, 0x72, - 0xC2, 0xE1, - 0x2C, 0xC0, 0x44, 0xC2, - - 0x05, 0x24, 0x34, 0xBF, - 0x0D, 0x24, 0x2C, 0xBF, - - 0x2D, 0x46, 0x4E, 0xBF, - 0x25, 0x46, 0x56, 0xBF, - - 0x20, 0x1D, 0x6F, 0x8F, - 0x32, 0x3E, 0x5F, 0xE9, - - 0x3E, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x30, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x33, 0x1E, 0x5F, 0xE9, - - 0x05, 0x44, 0x54, 0xB2, - 0x0D, 0x44, 0x4C, 0xB2, - - 0x19, 0xC0, 0xB0, 0xE8, - 0x34, 0xC0, 0x44, 0xC4, - - 0x33, 0x73, - 0x00, 0xE0, - 0x3E, 0x62, 0x57, 0x9F, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0xE0, - 0x0D, 0x20, - - 0x84, 0x3E, 0x58, 0xE9, - 0x28, 0x1D, 0x6F, 0x8F, - - 0x05, 0x20, - 0x00, 0xE0, - 0x85, 0x1E, 0x58, 0xE9, - - 0x9B, 0x3B, 0x33, 0xDF, - 0x20, 0x20, 0x42, 0xAF, - - 0x30, 0x42, 0x56, 0x9F, - 0x80, 0x3E, 0x57, 0xE9, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x30, 0x80, 0x5F, 0xE9, - - 0x28, 0x28, 0x24, 0xAF, - 0x81, 0x1E, 0x57, 0xE9, - - 0x05, 0x47, 0x57, 0xBF, - 0x0D, 0x47, 0x4F, 0xBF, - - 0x88, 0x80, 0x58, 0xE9, - 0x1B, 0x29, 0x1B, 0xDF, - - 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0D, 0x21, 0x1A, 0xB6, - 0x05, 0x21, 0x31, 0xB6, - - 0x2D, 0x44, 0x4C, 0xB6, - 0x25, 0x44, 0x54, 0xB6, - - 0x03, 0x80, 0x2A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x0D, 0x20, - 0x05, 0x20, - 0x2F, 0xC0, 0x21, 0xC6, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x00, 0xE0, - 0x25, 0x20, - 0x07, 0xC0, 0x44, 0xC6, - - 0x17, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x2D, 0x20, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0xE0, - 0x2F, 0x20, - - 0x1F, 0x62, 0x57, 0x9F, - 0x00, 0xE0, - 0x07, 0x20, - - 0x3F, 0x3D, 0x5D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x28, 0x19, 0x60, 0xEC, - - 0xB3, 0x05, - 0x00, 0xE0, - 0x17, 0x26, 0x17, 0xDF, - - 0x23, 0x3B, 0x33, 0xAD, - 0x35, 0x17, 0x4F, 0xE9, - - 0x1F, 0x26, 0x1F, 0xDF, - 0x9D, 0x1F, 0x4F, 0xE9, - - 0x9E, 0x3F, 0x4F, 0xE9, - 0x39, 0x37, 0x4F, 0xE9, - - 0x2F, 0x2F, 0x17, 0xAF, - 0x00, 0x80, 0x00, 0xE8, - - 0x07, 0x07, 0x1F, 0xAF, - 0x00, 0x80, 0x00, 0xE8, - - 0x31, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x9C, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x57, 0x39, 0x20, 0xE9, - - 0x16, 0x28, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0x1E, 0x2B, 0x20, 0xE9, - 0x2B, 0x32, 0x20, 0xE9, - - 0x1C, 0x23, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x74, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x73, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x71, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x6E, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g200_tgzf[] = { - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x7F, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x21, 0x45, 0x80, 0xE8, - 0x1A, 0x4D, 0x80, 0xE8, - - 0x31, 0x55, 0x80, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x6B, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 0x29, 0x30, - 0x48, 0x3C, 0x48, 0xAD, - - 0x2B, 0x72, - 0xC2, 0xE1, - 0x2C, 0xC0, 0x44, 0xC2, - - 0x05, 0x24, 0x34, 0xBF, - 0x0D, 0x24, 0x2C, 0xBF, - - 0x2D, 0x46, 0x4E, 0xBF, - 0x25, 0x46, 0x56, 0xBF, - - 0x20, 0x1D, 0x6F, 0x8F, - 0x32, 0x3E, 0x5F, 0xE9, - - 0x3E, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x30, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x33, 0x1E, 0x5F, 0xE9, - - 0x05, 0x44, 0x54, 0xB2, - 0x0D, 0x44, 0x4C, 0xB2, - - 0x19, 0xC0, 0xB0, 0xE8, - 0x34, 0xC0, 0x44, 0xC4, - - 0x33, 0x73, - 0x00, 0xE0, - 0x3E, 0x62, 0x57, 0x9F, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0xE0, - 0x0D, 0x20, - - 0x84, 0x3E, 0x58, 0xE9, - 0x28, 0x1D, 0x6F, 0x8F, - - 0x05, 0x20, - 0x00, 0xE0, - 0x85, 0x1E, 0x58, 0xE9, - - 0x9B, 0x3B, 0x33, 0xDF, - 0x20, 0x20, 0x42, 0xAF, - - 0x30, 0x42, 0x56, 0x9F, - 0x80, 0x3E, 0x57, 0xE9, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x30, 0x80, 0x5F, 0xE9, - - 0x28, 0x28, 0x24, 0xAF, - 0x81, 0x1E, 0x57, 0xE9, - - 0x05, 0x47, 0x57, 0xBF, - 0x0D, 0x47, 0x4F, 0xBF, - - 0x88, 0x80, 0x58, 0xE9, - 0x1B, 0x29, 0x1B, 0xDF, - - 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0D, 0x21, 0x1A, 0xB6, - 0x05, 0x21, 0x31, 0xB6, - - 0x03, 0x80, 0x2A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x0D, 0x20, - 0x05, 0x20, - 0x2F, 0xC0, 0x21, 0xC6, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x17, 0x50, 0x56, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0xE0, - 0x2F, 0x20, - - 0x00, 0x80, 0x00, 0xE8, - 0x28, 0x19, 0x60, 0xEC, - - 0xB3, 0x05, - 0x00, 0xE0, - 0x00, 0x80, 0x00, 0xE8, - - 0x23, 0x3B, 0x33, 0xAD, - 0x00, 0x80, 0x00, 0xE8, - - 0x17, 0x26, 0x17, 0xDF, - 0x35, 0x17, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x39, 0x37, 0x4F, 0xE9, - - 0x2F, 0x2F, 0x17, 0xAF, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x31, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x57, 0x39, 0x20, 0xE9, - - 0x16, 0x28, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0x1E, 0x2B, 0x20, 0xE9, - 0x2B, 0x32, 0x20, 0xE9, - - 0x1C, 0x23, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x78, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x77, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x75, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x72, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g200_tgzs[] = { - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x8B, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x21, 0x45, 0x80, 0xE8, - 0x1A, 0x4D, 0x80, 0xE8, - - 0x31, 0x55, 0x80, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x77, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 0x29, 0x30, - 0x48, 0x3C, 0x48, 0xAD, - - 0x2B, 0x72, - 0xC2, 0xE1, - 0x2C, 0xC0, 0x44, 0xC2, - - 0x05, 0x24, 0x34, 0xBF, - 0x0D, 0x24, 0x2C, 0xBF, - - 0x2D, 0x46, 0x4E, 0xBF, - 0x25, 0x46, 0x56, 0xBF, - - 0x20, 0x1D, 0x6F, 0x8F, - 0x32, 0x3E, 0x5F, 0xE9, - - 0x3E, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x30, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x33, 0x1E, 0x5F, 0xE9, - - 0x05, 0x44, 0x54, 0xB2, - 0x0D, 0x44, 0x4C, 0xB2, - - 0x19, 0xC0, 0xB0, 0xE8, - 0x34, 0xC0, 0x44, 0xC4, - - 0x33, 0x73, - 0x00, 0xE0, - 0x3E, 0x62, 0x57, 0x9F, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0xE0, - 0x0D, 0x20, - - 0x84, 0x3E, 0x58, 0xE9, - 0x28, 0x1D, 0x6F, 0x8F, - - 0x05, 0x20, - 0x00, 0xE0, - 0x85, 0x1E, 0x58, 0xE9, - - 0x9B, 0x3B, 0x33, 0xDF, - 0x20, 0x20, 0x42, 0xAF, - - 0x30, 0x42, 0x56, 0x9F, - 0x80, 0x3E, 0x57, 0xE9, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x30, 0x80, 0x5F, 0xE9, - - 0x28, 0x28, 0x24, 0xAF, - 0x81, 0x1E, 0x57, 0xE9, - - 0x05, 0x47, 0x57, 0xBF, - 0x0D, 0x47, 0x4F, 0xBF, - - 0x88, 0x80, 0x58, 0xE9, - 0x1B, 0x29, 0x1B, 0xDF, - - 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x2D, 0x21, 0x1A, 0xB0, - 0x25, 0x21, 0x31, 0xB0, - - 0x0D, 0x21, 0x1A, 0xB2, - 0x05, 0x21, 0x31, 0xB2, - - 0x03, 0x80, 0x2A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x2D, 0x20, - 0x25, 0x20, - 0x05, 0x20, - 0x0D, 0x20, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x2F, 0xC0, 0x21, 0xC0, - - 0x16, 0x42, 0x56, 0x9F, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x1E, 0x62, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x21, 0x31, 0xB4, - 0x2D, 0x21, 0x1A, 0xB4, - - 0x3F, 0x2F, 0x5D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0x05, - 0x00, 0xE0, - 0x28, 0x19, 0x60, 0xEC, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0xE0, - 0x2F, 0x20, - - 0x23, 0x3B, 0x33, 0xAD, - 0x1E, 0x26, 0x1E, 0xDF, - - 0xA7, 0x1E, 0x4F, 0xE9, - 0x17, 0x26, 0x16, 0xDF, - - 0x2D, 0x20, - 0x00, 0xE0, - 0xA8, 0x3F, 0x4F, 0xE9, - - 0x2F, 0x2F, 0x1E, 0xAF, - 0x25, 0x20, - 0x00, 0xE0, - - 0xA4, 0x16, 0x4F, 0xE9, - 0x0F, 0xC0, 0x21, 0xC2, - - 0xA6, 0x80, 0x4F, 0xE9, - 0x1F, 0x62, 0x57, 0x9F, - - 0x3F, 0x2F, 0x5D, 0x9F, - 0x00, 0xE0, - 0x8F, 0x20, - - 0xA5, 0x37, 0x4F, 0xE9, - 0x0F, 0x17, 0x0F, 0xAF, - - 0x06, 0xC0, 0x21, 0xC4, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0xA3, 0x80, 0x4F, 0xE9, - - 0x06, 0x20, - 0x00, 0xE0, - 0x1F, 0x26, 0x1F, 0xDF, - - 0xA1, 0x1F, 0x4F, 0xE9, - 0xA2, 0x3F, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x06, 0x06, 0x1F, 0xAF, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x57, 0x39, 0x20, 0xE9, - - 0x16, 0x28, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0x1E, 0x2B, 0x20, 0xE9, - 0x2B, 0x32, 0x20, 0xE9, - - 0x1C, 0x23, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x6C, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x6B, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x69, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g200_tgzsa[] = { - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x8F, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x21, 0x45, 0x80, 0xE8, - 0x1A, 0x4D, 0x80, 0xE8, - - 0x31, 0x55, 0x80, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x7B, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 0x29, 0x30, - 0x48, 0x3C, 0x48, 0xAD, - - 0x2B, 0x72, - 0xC2, 0xE1, - 0x2C, 0xC0, 0x44, 0xC2, - - 0x05, 0x24, 0x34, 0xBF, - 0x0D, 0x24, 0x2C, 0xBF, - - 0x2D, 0x46, 0x4E, 0xBF, - 0x25, 0x46, 0x56, 0xBF, - - 0x20, 0x1D, 0x6F, 0x8F, - 0x32, 0x3E, 0x5F, 0xE9, - - 0x3E, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x30, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x33, 0x1E, 0x5F, 0xE9, - - 0x05, 0x44, 0x54, 0xB2, - 0x0D, 0x44, 0x4C, 0xB2, - - 0x19, 0xC0, 0xB0, 0xE8, - 0x34, 0xC0, 0x44, 0xC4, - - 0x33, 0x73, - 0x00, 0xE0, - 0x3E, 0x62, 0x57, 0x9F, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0xE0, - 0x0D, 0x20, - - 0x84, 0x3E, 0x58, 0xE9, - 0x28, 0x1D, 0x6F, 0x8F, - - 0x05, 0x20, - 0x00, 0xE0, - 0x85, 0x1E, 0x58, 0xE9, - - 0x9B, 0x3B, 0x33, 0xDF, - 0x20, 0x20, 0x42, 0xAF, - - 0x30, 0x42, 0x56, 0x9F, - 0x80, 0x3E, 0x57, 0xE9, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x30, 0x80, 0x5F, 0xE9, - - 0x28, 0x28, 0x24, 0xAF, - 0x81, 0x1E, 0x57, 0xE9, - - 0x05, 0x47, 0x57, 0xBF, - 0x0D, 0x47, 0x4F, 0xBF, - - 0x88, 0x80, 0x58, 0xE9, - 0x1B, 0x29, 0x1B, 0xDF, - - 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x2D, 0x21, 0x1A, 0xB0, - 0x25, 0x21, 0x31, 0xB0, - - 0x0D, 0x21, 0x1A, 0xB2, - 0x05, 0x21, 0x31, 0xB2, - - 0x03, 0x80, 0x2A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x2D, 0x20, - 0x25, 0x20, - 0x05, 0x20, - 0x0D, 0x20, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x2F, 0xC0, 0x21, 0xC0, - - 0x16, 0x42, 0x56, 0x9F, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x1E, 0x62, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x21, 0x31, 0xB4, - 0x2D, 0x21, 0x1A, 0xB4, - - 0x3F, 0x2F, 0x5D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0x05, - 0x00, 0xE0, - 0x28, 0x19, 0x60, 0xEC, - - 0x0D, 0x44, 0x4C, 0xB6, - 0x05, 0x44, 0x54, 0xB6, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0xE0, - 0x2F, 0x20, - - 0x23, 0x3B, 0x33, 0xAD, - 0x1E, 0x26, 0x1E, 0xDF, - - 0xA7, 0x1E, 0x4F, 0xE9, - 0x17, 0x26, 0x16, 0xDF, - - 0x2D, 0x20, - 0x00, 0xE0, - 0xA8, 0x3F, 0x4F, 0xE9, - - 0x2F, 0x2F, 0x1E, 0xAF, - 0x25, 0x20, - 0x00, 0xE0, - - 0xA4, 0x16, 0x4F, 0xE9, - 0x0F, 0xC0, 0x21, 0xC2, - - 0xA6, 0x80, 0x4F, 0xE9, - 0x1F, 0x62, 0x57, 0x9F, - - 0x0D, 0x20, - 0x05, 0x20, - 0x00, 0x80, 0x00, 0xE8, - - 0x3F, 0x2F, 0x5D, 0x9F, - 0x00, 0xE0, - 0x0F, 0x20, - - 0x17, 0x50, 0x56, 0x9F, - 0xA5, 0x37, 0x4F, 0xE9, - - 0x06, 0xC0, 0x21, 0xC4, - 0x0F, 0x17, 0x0F, 0xAF, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x2F, 0xC0, 0x44, 0xC6, - 0xA3, 0x80, 0x4F, 0xE9, - - 0x06, 0x20, - 0x00, 0xE0, - 0x1F, 0x26, 0x1F, 0xDF, - - 0x17, 0x26, 0x17, 0xDF, - 0x9D, 0x17, 0x4F, 0xE9, - - 0xA1, 0x1F, 0x4F, 0xE9, - 0xA2, 0x3F, 0x4F, 0xE9, - - 0x06, 0x06, 0x1F, 0xAF, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x9E, 0x37, 0x4F, 0xE9, - 0x2F, 0x17, 0x2F, 0xAF, - - 0xA0, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x9C, 0x80, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x57, 0x39, 0x20, 0xE9, - - 0x16, 0x28, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0x1E, 0x2B, 0x20, 0xE9, - 0x2B, 0x32, 0x20, 0xE9, - - 0x1C, 0x23, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x68, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x67, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x65, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x62, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g200_tgzsaf[] = { - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x94, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x21, 0x45, 0x80, 0xE8, - 0x1A, 0x4D, 0x80, 0xE8, - - 0x31, 0x55, 0x80, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x80, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 0x29, 0x30, - 0x48, 0x3C, 0x48, 0xAD, - - 0x2B, 0x72, - 0xC2, 0xE1, - 0x2C, 0xC0, 0x44, 0xC2, - - 0x05, 0x24, 0x34, 0xBF, - 0x0D, 0x24, 0x2C, 0xBF, - - 0x2D, 0x46, 0x4E, 0xBF, - 0x25, 0x46, 0x56, 0xBF, - - 0x20, 0x1D, 0x6F, 0x8F, - 0x32, 0x3E, 0x5F, 0xE9, - - 0x3E, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x30, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x33, 0x1E, 0x5F, 0xE9, - - 0x05, 0x44, 0x54, 0xB2, - 0x0D, 0x44, 0x4C, 0xB2, - - 0x19, 0xC0, 0xB0, 0xE8, - 0x34, 0xC0, 0x44, 0xC4, - - 0x33, 0x73, - 0x00, 0xE0, - 0x3E, 0x62, 0x57, 0x9F, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0xE0, - 0x0D, 0x20, - - 0x84, 0x3E, 0x58, 0xE9, - 0x28, 0x1D, 0x6F, 0x8F, - - 0x05, 0x20, - 0x00, 0xE0, - 0x85, 0x1E, 0x58, 0xE9, - - 0x9B, 0x3B, 0x33, 0xDF, - 0x20, 0x20, 0x42, 0xAF, - - 0x30, 0x42, 0x56, 0x9F, - 0x80, 0x3E, 0x57, 0xE9, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x30, 0x80, 0x5F, 0xE9, - - 0x28, 0x28, 0x24, 0xAF, - 0x81, 0x1E, 0x57, 0xE9, - - 0x05, 0x47, 0x57, 0xBF, - 0x0D, 0x47, 0x4F, 0xBF, - - 0x88, 0x80, 0x58, 0xE9, - 0x1B, 0x29, 0x1B, 0xDF, - - 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x2D, 0x21, 0x1A, 0xB0, - 0x25, 0x21, 0x31, 0xB0, - - 0x0D, 0x21, 0x1A, 0xB2, - 0x05, 0x21, 0x31, 0xB2, - - 0x03, 0x80, 0x2A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x2D, 0x20, - 0x25, 0x20, - 0x05, 0x20, - 0x0D, 0x20, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x2F, 0xC0, 0x21, 0xC0, - - 0x16, 0x42, 0x56, 0x9F, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x1E, 0x62, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x21, 0x31, 0xB4, - 0x2D, 0x21, 0x1A, 0xB4, - - 0x3F, 0x2F, 0x5D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0x05, - 0x00, 0xE0, - 0x28, 0x19, 0x60, 0xEC, - - 0x0D, 0x21, 0x1A, 0xB6, - 0x05, 0x21, 0x31, 0xB6, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0xE0, - 0x2F, 0x20, - - 0x23, 0x3B, 0x33, 0xAD, - 0x1E, 0x26, 0x1E, 0xDF, - - 0xA7, 0x1E, 0x4F, 0xE9, - 0x17, 0x26, 0x16, 0xDF, - - 0x2D, 0x20, - 0x00, 0xE0, - 0xA8, 0x3F, 0x4F, 0xE9, - - 0x2F, 0x2F, 0x1E, 0xAF, - 0x25, 0x20, - 0x00, 0xE0, - - 0xA4, 0x16, 0x4F, 0xE9, - 0x0F, 0xC0, 0x21, 0xC2, - - 0xA6, 0x80, 0x4F, 0xE9, - 0x1F, 0x62, 0x57, 0x9F, - - 0x0D, 0x20, - 0x05, 0x20, - 0x2F, 0xC0, 0x21, 0xC6, - - 0x2D, 0x44, 0x4C, 0xB6, - 0x25, 0x44, 0x54, 0xB6, - - 0x3F, 0x2F, 0x5D, 0x9F, - 0x00, 0xE0, - 0x0F, 0x20, - - 0x2D, 0x20, - 0x25, 0x20, - 0x07, 0xC0, 0x44, 0xC6, - - 0x17, 0x50, 0x56, 0x9F, - 0xA5, 0x37, 0x4F, 0xE9, - - 0x06, 0xC0, 0x21, 0xC4, - 0x0F, 0x17, 0x0F, 0xAF, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x1E, 0x62, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x3E, 0x3D, 0x5D, 0x9F, - 0x00, 0xE0, - 0x07, 0x20, - - 0x2F, 0x20, - 0x00, 0xE0, - 0xA3, 0x0F, 0x4F, 0xE9, - - 0x06, 0x20, - 0x00, 0xE0, - 0x1F, 0x26, 0x1F, 0xDF, - - 0x17, 0x26, 0x17, 0xDF, - 0xA1, 0x1F, 0x4F, 0xE9, - - 0x1E, 0x26, 0x1E, 0xDF, - 0x9D, 0x1E, 0x4F, 0xE9, - - 0x35, 0x17, 0x4F, 0xE9, - 0xA2, 0x3F, 0x4F, 0xE9, - - 0x06, 0x06, 0x1F, 0xAF, - 0x39, 0x37, 0x4F, 0xE9, - - 0x2F, 0x2F, 0x17, 0xAF, - 0x07, 0x07, 0x1E, 0xAF, - - 0xA0, 0x80, 0x4F, 0xE9, - 0x9E, 0x3E, 0x4F, 0xE9, - - 0x31, 0x80, 0x4F, 0xE9, - 0x9C, 0x80, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x57, 0x39, 0x20, 0xE9, - - 0x16, 0x28, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0x1E, 0x2B, 0x20, 0xE9, - 0x2B, 0x32, 0x20, 0xE9, - - 0x1C, 0x23, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x63, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x62, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x60, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x5D, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g200_tgzsf[] = { - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x8F, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x21, 0x45, 0x80, 0xE8, - 0x1A, 0x4D, 0x80, 0xE8, - - 0x31, 0x55, 0x80, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x7B, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 0x29, 0x30, - 0x48, 0x3C, 0x48, 0xAD, - - 0x2B, 0x72, - 0xC2, 0xE1, - 0x2C, 0xC0, 0x44, 0xC2, - - 0x05, 0x24, 0x34, 0xBF, - 0x0D, 0x24, 0x2C, 0xBF, - - 0x2D, 0x46, 0x4E, 0xBF, - 0x25, 0x46, 0x56, 0xBF, - - 0x20, 0x1D, 0x6F, 0x8F, - 0x32, 0x3E, 0x5F, 0xE9, - - 0x3E, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x30, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x33, 0x1E, 0x5F, 0xE9, - - 0x05, 0x44, 0x54, 0xB2, - 0x0D, 0x44, 0x4C, 0xB2, - - 0x19, 0xC0, 0xB0, 0xE8, - 0x34, 0xC0, 0x44, 0xC4, - - 0x33, 0x73, - 0x00, 0xE0, - 0x3E, 0x62, 0x57, 0x9F, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0xE0, - 0x0D, 0x20, - - 0x84, 0x3E, 0x58, 0xE9, - 0x28, 0x1D, 0x6F, 0x8F, - - 0x05, 0x20, - 0x00, 0xE0, - 0x85, 0x1E, 0x58, 0xE9, - - 0x9B, 0x3B, 0x33, 0xDF, - 0x20, 0x20, 0x42, 0xAF, - - 0x30, 0x42, 0x56, 0x9F, - 0x80, 0x3E, 0x57, 0xE9, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x30, 0x80, 0x5F, 0xE9, - - 0x28, 0x28, 0x24, 0xAF, - 0x81, 0x1E, 0x57, 0xE9, - - 0x05, 0x47, 0x57, 0xBF, - 0x0D, 0x47, 0x4F, 0xBF, - - 0x88, 0x80, 0x58, 0xE9, - 0x1B, 0x29, 0x1B, 0xDF, - - 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x2D, 0x21, 0x1A, 0xB0, - 0x25, 0x21, 0x31, 0xB0, - - 0x0D, 0x21, 0x1A, 0xB2, - 0x05, 0x21, 0x31, 0xB2, - - 0x03, 0x80, 0x2A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x2D, 0x20, - 0x25, 0x20, - 0x05, 0x20, - 0x0D, 0x20, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x2F, 0xC0, 0x21, 0xC0, - - 0x16, 0x42, 0x56, 0x9F, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x1E, 0x62, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x21, 0x31, 0xB4, - 0x2D, 0x21, 0x1A, 0xB4, - - 0x3F, 0x2F, 0x5D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0x05, - 0x00, 0xE0, - 0x28, 0x19, 0x60, 0xEC, - - 0x0D, 0x21, 0x1A, 0xB6, - 0x05, 0x21, 0x31, 0xB6, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0xE0, - 0x2F, 0x20, - - 0x23, 0x3B, 0x33, 0xAD, - 0x1E, 0x26, 0x1E, 0xDF, - - 0xA7, 0x1E, 0x4F, 0xE9, - 0x17, 0x26, 0x16, 0xDF, - - 0x2D, 0x20, - 0x00, 0xE0, - 0xA8, 0x3F, 0x4F, 0xE9, - - 0x2F, 0x2F, 0x1E, 0xAF, - 0x25, 0x20, - 0x00, 0xE0, - - 0xA4, 0x16, 0x4F, 0xE9, - 0x0F, 0xC0, 0x21, 0xC2, - - 0xA6, 0x80, 0x4F, 0xE9, - 0x1F, 0x62, 0x57, 0x9F, - - 0x0D, 0x20, - 0x05, 0x20, - 0x2F, 0xC0, 0x21, 0xC6, - - 0x3F, 0x2F, 0x5D, 0x9F, - 0x00, 0xE0, - 0x0F, 0x20, - - 0x17, 0x50, 0x56, 0x9F, - 0xA5, 0x37, 0x4F, 0xE9, - - 0x06, 0xC0, 0x21, 0xC4, - 0x0F, 0x17, 0x0F, 0xAF, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x2F, 0x20, - 0x00, 0xE0, - 0xA3, 0x80, 0x4F, 0xE9, - - 0x06, 0x20, - 0x00, 0xE0, - 0x1F, 0x26, 0x1F, 0xDF, - - 0x17, 0x26, 0x17, 0xDF, - 0x35, 0x17, 0x4F, 0xE9, - - 0xA1, 0x1F, 0x4F, 0xE9, - 0xA2, 0x3F, 0x4F, 0xE9, - - 0x06, 0x06, 0x1F, 0xAF, - 0x39, 0x37, 0x4F, 0xE9, - - 0x2F, 0x2F, 0x17, 0xAF, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x31, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x57, 0x39, 0x20, 0xE9, - - 0x16, 0x28, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0x1E, 0x2B, 0x20, 0xE9, - 0x2B, 0x32, 0x20, 0xE9, - - 0x1C, 0x23, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x68, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x67, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x65, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x62, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g400_t2gz[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x78, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - - 0x61, 0x51, 0xE0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x52, 0xBF, - 0x0F, 0x52, 0xA0, 0xE8, - - 0x1A, 0x42, 0x62, 0xBF, - 0x1E, 0x51, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x0E, 0x61, 0x60, 0xEA, - - 0x32, 0x40, 0x50, 0xBD, - 0x22, 0x40, 0x60, 0xBD, - - 0x12, 0x41, 0x51, 0xBD, - 0x3A, 0x41, 0x61, 0xBD, - - 0xBF, 0x2F, 0x0E, 0xBD, - 0x97, 0xE2, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x35, 0x48, 0xB1, 0xE8, - 0x3D, 0x59, 0xB1, 0xE8, - - 0x46, 0x31, 0x46, 0xBF, - 0x56, 0x31, 0x56, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0x31, 0x66, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x57, 0x39, 0x57, 0xBF, - 0x67, 0x39, 0x67, 0xBF, - - 0x69, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x35, 0x00, - 0x3D, 0x00, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0x8D, 0x2F, 0x1E, 0xBD, - - 0x43, 0x75, 0xF8, 0xEC, - 0x35, 0x20, - 0x3D, 0x20, - - 0x43, 0x43, 0x2D, 0xDF, - 0x53, 0x53, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x0E, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x48, 0x35, 0x48, 0xBF, - 0x58, 0x35, 0x58, 0xBF, - - 0x68, 0x35, 0x68, 0xBF, - 0x49, 0x3D, 0x49, 0xBF, - - 0x59, 0x3D, 0x59, 0xBF, - 0x69, 0x3D, 0x69, 0xBF, - - 0x63, 0x63, 0x2D, 0xDF, - 0x4D, 0x7D, 0xF8, 0xEC, - - 0x59, 0xE3, - 0x00, 0xE0, - 0xB8, 0x38, 0x33, 0xBF, - - 0x2D, 0x73, - 0x30, 0x76, - 0x18, 0x3A, 0x41, 0xE9, - - 0x3F, 0x53, 0xA0, 0xE8, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x63, 0xA0, 0xE8, - - 0x50, 0x70, 0xF8, 0xEC, - 0x2B, 0x50, 0x3C, 0xE9, - - 0x1F, 0x0F, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x59, 0x78, 0xF8, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x46, 0x37, 0x46, 0xDF, - 0x56, 0x3F, 0x56, 0xDF, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x66, 0x3D, 0x66, 0xDF, - - 0x1D, 0x32, 0x41, 0xE9, - 0x67, 0x3D, 0x67, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3F, 0x57, 0xDF, - - 0x2A, 0x40, 0x20, 0xE9, - 0x59, 0x3F, 0x59, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x69, 0x3D, 0x69, 0xDF, - - 0x48, 0x37, 0x48, 0xDF, - 0x58, 0x3F, 0x58, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x68, 0x3D, 0x68, 0xDF, - 0x49, 0x37, 0x49, 0xDF, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x37, 0xCF, 0x74, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0x34, 0x80, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x0A, 0x44, 0x54, 0xB0, - 0x02, 0x44, 0x64, 0xB0, - - 0x2A, 0x44, 0x54, 0xB2, - 0x1A, 0x44, 0x64, 0xB2, - - 0x25, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x3D, 0xCF, 0x74, 0xC2, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x2A, 0x44, 0x54, 0xB4, - 0x1A, 0x44, 0x64, 0xB4, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x38, 0x3D, 0x20, 0xE9, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x56, 0xBF, - 0x1A, 0x46, 0x66, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x0A, 0x47, 0x57, 0xBF, - 0x02, 0x47, 0x67, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x43, 0x53, 0xBF, - 0x1A, 0x43, 0x63, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x0A, 0x48, 0x58, 0xBF, - 0x02, 0x48, 0x68, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x2A, 0x49, 0x59, 0xBF, - 0x1A, 0x49, 0x69, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x82, 0x30, 0x57, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x83, 0x38, 0x57, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x84, 0x31, 0x5E, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x85, 0x39, 0x5E, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8A, 0x36, 0x20, 0xE9, - - 0x87, 0x77, 0x57, 0xE9, - 0x8B, 0x3E, 0xBF, 0xEA, - - 0x80, 0x30, 0x57, 0xE9, - 0x81, 0x38, 0x57, 0xE9, - - 0x82, 0x31, 0x57, 0xE9, - 0x86, 0x78, 0x57, 0xE9, - - 0x83, 0x39, 0x57, 0xE9, - 0x87, 0x79, 0x57, 0xE9, - - 0x30, 0x1F, 0x5F, 0xE9, - 0x8A, 0x34, 0x20, 0xE9, - - 0x8B, 0x3C, 0x20, 0xE9, - 0x37, 0x50, 0x60, 0xBD, - - 0x57, 0x0D, 0x20, 0xE9, - 0x35, 0x51, 0x61, 0xBD, - - 0x2B, 0x50, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x0E, 0x77, - - 0x24, 0x51, 0x20, 0xE9, - 0x9F, 0xFF, 0x20, 0xEA, - - 0x16, 0x0E, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x0B, 0x46, 0xA0, 0xE8, - 0x1B, 0x56, 0xA0, 0xE8, - - 0x2B, 0x66, 0xA0, 0xE8, - 0x0C, 0x47, 0xA0, 0xE8, - - 0x1C, 0x57, 0xA0, 0xE8, - 0x2C, 0x67, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x57, 0x80, 0x57, 0xCF, - - 0x66, 0x33, 0x66, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x67, 0x3B, 0x67, 0xCF, - - 0x0B, 0x48, 0xA0, 0xE8, - 0x1B, 0x58, 0xA0, 0xE8, - - 0x2B, 0x68, 0xA0, 0xE8, - 0x0C, 0x49, 0xA0, 0xE8, - - 0x1C, 0x59, 0xA0, 0xE8, - 0x2C, 0x69, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x34, 0xD7, 0x34, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3C, 0xD7, 0x3C, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x34, 0x80, 0x34, 0xBD, - 0x3C, 0x80, 0x3C, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x48, 0x80, 0x48, 0xCF, - 0x59, 0x80, 0x59, 0xCF, - - 0x68, 0x33, 0x68, 0xCF, - 0x49, 0x3B, 0x49, 0xCF, - - 0xBE, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x7D, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_t2gza[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x7C, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - - 0x61, 0x51, 0xE0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x52, 0xBF, - 0x0F, 0x52, 0xA0, 0xE8, - - 0x1A, 0x42, 0x62, 0xBF, - 0x1E, 0x51, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x0E, 0x61, 0x60, 0xEA, - - 0x32, 0x40, 0x50, 0xBD, - 0x22, 0x40, 0x60, 0xBD, - - 0x12, 0x41, 0x51, 0xBD, - 0x3A, 0x41, 0x61, 0xBD, - - 0xBF, 0x2F, 0x0E, 0xBD, - 0x97, 0xE2, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x35, 0x48, 0xB1, 0xE8, - 0x3D, 0x59, 0xB1, 0xE8, - - 0x46, 0x31, 0x46, 0xBF, - 0x56, 0x31, 0x56, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0x31, 0x66, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x57, 0x39, 0x57, 0xBF, - 0x67, 0x39, 0x67, 0xBF, - - 0x6D, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x35, 0x00, - 0x3D, 0x00, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0x8D, 0x2F, 0x1E, 0xBD, - - 0x43, 0x75, 0xF8, 0xEC, - 0x35, 0x20, - 0x3D, 0x20, - - 0x43, 0x43, 0x2D, 0xDF, - 0x53, 0x53, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x0E, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x48, 0x35, 0x48, 0xBF, - 0x58, 0x35, 0x58, 0xBF, - - 0x68, 0x35, 0x68, 0xBF, - 0x49, 0x3D, 0x49, 0xBF, - - 0x59, 0x3D, 0x59, 0xBF, - 0x69, 0x3D, 0x69, 0xBF, - - 0x63, 0x63, 0x2D, 0xDF, - 0x4D, 0x7D, 0xF8, 0xEC, - - 0x59, 0xE3, - 0x00, 0xE0, - 0xB8, 0x38, 0x33, 0xBF, - - 0x2D, 0x73, - 0x30, 0x76, - 0x18, 0x3A, 0x41, 0xE9, - - 0x3F, 0x53, 0xA0, 0xE8, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x63, 0xA0, 0xE8, - - 0x50, 0x70, 0xF8, 0xEC, - 0x2B, 0x50, 0x3C, 0xE9, - - 0x1F, 0x0F, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x59, 0x78, 0xF8, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x46, 0x37, 0x46, 0xDF, - 0x56, 0x3F, 0x56, 0xDF, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x66, 0x3D, 0x66, 0xDF, - - 0x1D, 0x32, 0x41, 0xE9, - 0x67, 0x3D, 0x67, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3F, 0x57, 0xDF, - - 0x2A, 0x40, 0x20, 0xE9, - 0x59, 0x3F, 0x59, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x69, 0x3D, 0x69, 0xDF, - - 0x48, 0x37, 0x48, 0xDF, - 0x58, 0x3F, 0x58, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x68, 0x3D, 0x68, 0xDF, - 0x49, 0x37, 0x49, 0xDF, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x37, 0xCF, 0x74, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0x34, 0x80, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x0A, 0x44, 0x54, 0xB0, - 0x02, 0x44, 0x64, 0xB0, - - 0x2A, 0x44, 0x54, 0xB2, - 0x1A, 0x44, 0x64, 0xB2, - - 0x29, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x0F, 0xCF, 0x74, 0xC6, - 0x3D, 0xCF, 0x74, 0xC2, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9C, 0x0F, 0x20, 0xE9, - - 0x0A, 0x44, 0x54, 0xB4, - 0x02, 0x44, 0x64, 0xB4, - - 0x2A, 0x44, 0x54, 0xB6, - 0x1A, 0x44, 0x64, 0xB6, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x38, 0x3D, 0x20, 0xE9, - - 0x0A, 0x20, - 0x02, 0x20, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x0A, 0x47, 0x57, 0xBF, - 0x02, 0x47, 0x67, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x2A, 0x46, 0x56, 0xBF, - 0x1A, 0x46, 0x66, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x36, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x37, 0x38, 0x4F, 0xE9, - - 0x2A, 0x43, 0x53, 0xBF, - 0x1A, 0x43, 0x63, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x9D, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x9E, 0x39, 0x4F, 0xE9, - - 0x0A, 0x48, 0x58, 0xBF, - 0x02, 0x48, 0x68, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x2A, 0x49, 0x59, 0xBF, - 0x1A, 0x49, 0x69, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x82, 0x30, 0x57, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x83, 0x38, 0x57, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x84, 0x31, 0x5E, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x85, 0x39, 0x5E, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8A, 0x36, 0x20, 0xE9, - - 0x87, 0x77, 0x57, 0xE9, - 0x8B, 0x3E, 0xBF, 0xEA, - - 0x80, 0x30, 0x57, 0xE9, - 0x81, 0x38, 0x57, 0xE9, - - 0x82, 0x31, 0x57, 0xE9, - 0x86, 0x78, 0x57, 0xE9, - - 0x83, 0x39, 0x57, 0xE9, - 0x87, 0x79, 0x57, 0xE9, - - 0x30, 0x1F, 0x5F, 0xE9, - 0x8A, 0x34, 0x20, 0xE9, - - 0x8B, 0x3C, 0x20, 0xE9, - 0x37, 0x50, 0x60, 0xBD, - - 0x57, 0x0D, 0x20, 0xE9, - 0x35, 0x51, 0x61, 0xBD, - - 0x2B, 0x50, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x0E, 0x77, - - 0x24, 0x51, 0x20, 0xE9, - 0x9B, 0xFF, 0x20, 0xEA, - - 0x16, 0x0E, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x0B, 0x46, 0xA0, 0xE8, - 0x1B, 0x56, 0xA0, 0xE8, - - 0x2B, 0x66, 0xA0, 0xE8, - 0x0C, 0x47, 0xA0, 0xE8, - - 0x1C, 0x57, 0xA0, 0xE8, - 0x2C, 0x67, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x57, 0x80, 0x57, 0xCF, - - 0x66, 0x33, 0x66, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x67, 0x3B, 0x67, 0xCF, - - 0x0B, 0x48, 0xA0, 0xE8, - 0x1B, 0x58, 0xA0, 0xE8, - - 0x2B, 0x68, 0xA0, 0xE8, - 0x0C, 0x49, 0xA0, 0xE8, - - 0x1C, 0x59, 0xA0, 0xE8, - 0x2C, 0x69, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x34, 0xD7, 0x34, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3C, 0xD7, 0x3C, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x34, 0x80, 0x34, 0xBD, - 0x3C, 0x80, 0x3C, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x48, 0x80, 0x48, 0xCF, - 0x59, 0x80, 0x59, 0xCF, - - 0x68, 0x33, 0x68, 0xCF, - 0x49, 0x3B, 0x49, 0xCF, - - 0xBA, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x79, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_t2gzaf[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x81, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - - 0x61, 0x51, 0xE0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x52, 0xBF, - 0x0F, 0x52, 0xA0, 0xE8, - - 0x1A, 0x42, 0x62, 0xBF, - 0x1E, 0x51, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x0E, 0x61, 0x60, 0xEA, - - 0x32, 0x40, 0x50, 0xBD, - 0x22, 0x40, 0x60, 0xBD, - - 0x12, 0x41, 0x51, 0xBD, - 0x3A, 0x41, 0x61, 0xBD, - - 0xBF, 0x2F, 0x0E, 0xBD, - 0x97, 0xE2, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x35, 0x48, 0xB1, 0xE8, - 0x3D, 0x59, 0xB1, 0xE8, - - 0x46, 0x31, 0x46, 0xBF, - 0x56, 0x31, 0x56, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0x31, 0x66, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x57, 0x39, 0x57, 0xBF, - 0x67, 0x39, 0x67, 0xBF, - - 0x72, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x35, 0x00, - 0x3D, 0x00, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0x8D, 0x2F, 0x1E, 0xBD, - - 0x43, 0x75, 0xF8, 0xEC, - 0x35, 0x20, - 0x3D, 0x20, - - 0x43, 0x43, 0x2D, 0xDF, - 0x53, 0x53, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x0E, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x48, 0x35, 0x48, 0xBF, - 0x58, 0x35, 0x58, 0xBF, - - 0x68, 0x35, 0x68, 0xBF, - 0x49, 0x3D, 0x49, 0xBF, - - 0x59, 0x3D, 0x59, 0xBF, - 0x69, 0x3D, 0x69, 0xBF, - - 0x63, 0x63, 0x2D, 0xDF, - 0x4D, 0x7D, 0xF8, 0xEC, - - 0x59, 0xE3, - 0x00, 0xE0, - 0xB8, 0x38, 0x33, 0xBF, - - 0x2D, 0x73, - 0x30, 0x76, - 0x18, 0x3A, 0x41, 0xE9, - - 0x3F, 0x53, 0xA0, 0xE8, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x63, 0xA0, 0xE8, - - 0x50, 0x70, 0xF8, 0xEC, - 0x2B, 0x50, 0x3C, 0xE9, - - 0x1F, 0x0F, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x59, 0x78, 0xF8, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x46, 0x37, 0x46, 0xDF, - 0x56, 0x3F, 0x56, 0xDF, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x66, 0x3D, 0x66, 0xDF, - - 0x1D, 0x32, 0x41, 0xE9, - 0x67, 0x3D, 0x67, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3F, 0x57, 0xDF, - - 0x2A, 0x40, 0x20, 0xE9, - 0x59, 0x3F, 0x59, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x69, 0x3D, 0x69, 0xDF, - - 0x48, 0x37, 0x48, 0xDF, - 0x58, 0x3F, 0x58, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x68, 0x3D, 0x68, 0xDF, - 0x49, 0x37, 0x49, 0xDF, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x54, 0xB0, - 0x02, 0x44, 0x64, 0xB0, - - 0x31, 0x53, 0x2F, 0x9F, - 0x34, 0x37, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB2, - 0x1A, 0x44, 0x64, 0xB2, - - 0x2E, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x3D, 0xCF, 0x74, 0xC2, - 0x0F, 0xCF, 0x74, 0xC6, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9C, 0x0F, 0x20, 0xE9, - - 0x0A, 0x44, 0x54, 0xB4, - 0x02, 0x44, 0x64, 0xB4, - - 0x2A, 0x44, 0x54, 0xB6, - 0x1A, 0x44, 0x64, 0xB6, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x38, 0x3D, 0x20, 0xE9, - - 0x0A, 0x20, - 0x02, 0x20, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x3D, 0xCF, 0x75, 0xC6, - 0x00, 0x80, 0x00, 0xE8, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x0A, 0x45, 0x55, 0xB6, - 0x02, 0x45, 0x65, 0xB6, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x31, 0x3D, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x2A, 0x46, 0x56, 0xBF, - 0x1A, 0x46, 0x66, 0xBF, - - 0x0A, 0x47, 0x57, 0xBF, - 0x02, 0x47, 0x67, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x38, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9D, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x9E, 0x39, 0x4F, 0xE9, - - 0x2A, 0x43, 0x53, 0xBF, - 0x1A, 0x43, 0x63, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x35, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x39, 0x38, 0x4F, 0xE9, - - 0x0A, 0x48, 0x58, 0xBF, - 0x02, 0x48, 0x68, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x2A, 0x49, 0x59, 0xBF, - 0x1A, 0x49, 0x69, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x82, 0x30, 0x57, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x83, 0x38, 0x57, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x84, 0x31, 0x5E, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x85, 0x39, 0x5E, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8A, 0x36, 0x20, 0xE9, - - 0x87, 0x77, 0x57, 0xE9, - 0x8B, 0x3E, 0xBF, 0xEA, - - 0x80, 0x30, 0x57, 0xE9, - 0x81, 0x38, 0x57, 0xE9, - - 0x82, 0x31, 0x57, 0xE9, - 0x86, 0x78, 0x57, 0xE9, - - 0x83, 0x39, 0x57, 0xE9, - 0x87, 0x79, 0x57, 0xE9, - - 0x30, 0x1F, 0x5F, 0xE9, - 0x8A, 0x34, 0x20, 0xE9, - - 0x8B, 0x3C, 0x20, 0xE9, - 0x37, 0x50, 0x60, 0xBD, - - 0x57, 0x0D, 0x20, 0xE9, - 0x35, 0x51, 0x61, 0xBD, - - 0x2B, 0x50, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x0E, 0x77, - - 0x24, 0x51, 0x20, 0xE9, - 0x96, 0xFF, 0x20, 0xEA, - - 0x16, 0x0E, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x0B, 0x46, 0xA0, 0xE8, - 0x1B, 0x56, 0xA0, 0xE8, - - 0x2B, 0x66, 0xA0, 0xE8, - 0x0C, 0x47, 0xA0, 0xE8, - - 0x1C, 0x57, 0xA0, 0xE8, - 0x2C, 0x67, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x57, 0x80, 0x57, 0xCF, - - 0x66, 0x33, 0x66, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x67, 0x3B, 0x67, 0xCF, - - 0x0B, 0x48, 0xA0, 0xE8, - 0x1B, 0x58, 0xA0, 0xE8, - - 0x2B, 0x68, 0xA0, 0xE8, - 0x0C, 0x49, 0xA0, 0xE8, - - 0x1C, 0x59, 0xA0, 0xE8, - 0x2C, 0x69, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x34, 0xD7, 0x34, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3C, 0xD7, 0x3C, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x34, 0x80, 0x34, 0xBD, - 0x3C, 0x80, 0x3C, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x48, 0x80, 0x48, 0xCF, - 0x59, 0x80, 0x59, 0xCF, - - 0x68, 0x33, 0x68, 0xCF, - 0x49, 0x3B, 0x49, 0xCF, - - 0xB5, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x74, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_t2gzf[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x7D, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - - 0x61, 0x51, 0xE0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x52, 0xBF, - 0x0F, 0x52, 0xA0, 0xE8, - - 0x1A, 0x42, 0x62, 0xBF, - 0x1E, 0x51, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x0E, 0x61, 0x60, 0xEA, - - 0x32, 0x40, 0x50, 0xBD, - 0x22, 0x40, 0x60, 0xBD, - - 0x12, 0x41, 0x51, 0xBD, - 0x3A, 0x41, 0x61, 0xBD, - - 0xBF, 0x2F, 0x0E, 0xBD, - 0x97, 0xE2, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x35, 0x48, 0xB1, 0xE8, - 0x3D, 0x59, 0xB1, 0xE8, - - 0x46, 0x31, 0x46, 0xBF, - 0x56, 0x31, 0x56, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0x31, 0x66, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x57, 0x39, 0x57, 0xBF, - 0x67, 0x39, 0x67, 0xBF, - - 0x6E, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x35, 0x00, - 0x3D, 0x00, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0x8D, 0x2F, 0x1E, 0xBD, - - 0x43, 0x75, 0xF8, 0xEC, - 0x35, 0x20, - 0x3D, 0x20, - - 0x43, 0x43, 0x2D, 0xDF, - 0x53, 0x53, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x0E, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x48, 0x35, 0x48, 0xBF, - 0x58, 0x35, 0x58, 0xBF, - - 0x68, 0x35, 0x68, 0xBF, - 0x49, 0x3D, 0x49, 0xBF, - - 0x59, 0x3D, 0x59, 0xBF, - 0x69, 0x3D, 0x69, 0xBF, - - 0x63, 0x63, 0x2D, 0xDF, - 0x4D, 0x7D, 0xF8, 0xEC, - - 0x59, 0xE3, - 0x00, 0xE0, - 0xB8, 0x38, 0x33, 0xBF, - - 0x2D, 0x73, - 0x30, 0x76, - 0x18, 0x3A, 0x41, 0xE9, - - 0x3F, 0x53, 0xA0, 0xE8, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x63, 0xA0, 0xE8, - - 0x50, 0x70, 0xF8, 0xEC, - 0x2B, 0x50, 0x3C, 0xE9, - - 0x1F, 0x0F, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x59, 0x78, 0xF8, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x46, 0x37, 0x46, 0xDF, - 0x56, 0x3F, 0x56, 0xDF, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x66, 0x3D, 0x66, 0xDF, - - 0x1D, 0x32, 0x41, 0xE9, - 0x67, 0x3D, 0x67, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3F, 0x57, 0xDF, - - 0x2A, 0x40, 0x20, 0xE9, - 0x59, 0x3F, 0x59, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x69, 0x3D, 0x69, 0xDF, - - 0x48, 0x37, 0x48, 0xDF, - 0x58, 0x3F, 0x58, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x68, 0x3D, 0x68, 0xDF, - 0x49, 0x37, 0x49, 0xDF, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x37, 0xCF, 0x74, 0xC4, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x34, 0x80, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x88, 0x73, 0x5E, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0F, 0xCF, 0x75, 0xC6, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x0A, 0x44, 0x54, 0xB0, - 0x02, 0x44, 0x64, 0xB0, - - 0x2A, 0x44, 0x54, 0xB2, - 0x1A, 0x44, 0x64, 0xB2, - - 0x28, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x3D, 0xCF, 0x74, 0xC2, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x31, 0x0F, 0x20, 0xE9, - - 0x0A, 0x44, 0x54, 0xB4, - 0x02, 0x44, 0x64, 0xB4, - - 0x2A, 0x45, 0x55, 0xB6, - 0x1A, 0x45, 0x65, 0xB6, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x38, 0x3D, 0x20, 0xE9, - - 0x0A, 0x20, - 0x02, 0x20, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x0A, 0x47, 0x57, 0xBF, - 0x02, 0x47, 0x67, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x2A, 0x46, 0x56, 0xBF, - 0x1A, 0x46, 0x66, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x36, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x37, 0x38, 0x4F, 0xE9, - - 0x2A, 0x43, 0x53, 0xBF, - 0x1A, 0x43, 0x63, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x35, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x39, 0x39, 0x4F, 0xE9, - - 0x0A, 0x48, 0x58, 0xBF, - 0x02, 0x48, 0x68, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x2A, 0x49, 0x59, 0xBF, - 0x1A, 0x49, 0x69, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x82, 0x30, 0x57, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x83, 0x38, 0x57, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x84, 0x31, 0x5E, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x85, 0x39, 0x5E, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8A, 0x36, 0x20, 0xE9, - - 0x87, 0x77, 0x57, 0xE9, - 0x8B, 0x3E, 0xBF, 0xEA, - - 0x80, 0x30, 0x57, 0xE9, - 0x81, 0x38, 0x57, 0xE9, - - 0x82, 0x31, 0x57, 0xE9, - 0x86, 0x78, 0x57, 0xE9, - - 0x83, 0x39, 0x57, 0xE9, - 0x87, 0x79, 0x57, 0xE9, - - 0x30, 0x1F, 0x5F, 0xE9, - 0x8A, 0x34, 0x20, 0xE9, - - 0x8B, 0x3C, 0x20, 0xE9, - 0x37, 0x50, 0x60, 0xBD, - - 0x57, 0x0D, 0x20, 0xE9, - 0x35, 0x51, 0x61, 0xBD, - - 0x2B, 0x50, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x0E, 0x77, - - 0x24, 0x51, 0x20, 0xE9, - 0x9A, 0xFF, 0x20, 0xEA, - - 0x16, 0x0E, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x0B, 0x46, 0xA0, 0xE8, - 0x1B, 0x56, 0xA0, 0xE8, - - 0x2B, 0x66, 0xA0, 0xE8, - 0x0C, 0x47, 0xA0, 0xE8, - - 0x1C, 0x57, 0xA0, 0xE8, - 0x2C, 0x67, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x57, 0x80, 0x57, 0xCF, - - 0x66, 0x33, 0x66, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x67, 0x3B, 0x67, 0xCF, - - 0x0B, 0x48, 0xA0, 0xE8, - 0x1B, 0x58, 0xA0, 0xE8, - - 0x2B, 0x68, 0xA0, 0xE8, - 0x0C, 0x49, 0xA0, 0xE8, - - 0x1C, 0x59, 0xA0, 0xE8, - 0x2C, 0x69, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x34, 0xD7, 0x34, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3C, 0xD7, 0x3C, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x34, 0x80, 0x34, 0xBD, - 0x3C, 0x80, 0x3C, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x48, 0x80, 0x48, 0xCF, - 0x59, 0x80, 0x59, 0xCF, - - 0x68, 0x33, 0x68, 0xCF, - 0x49, 0x3B, 0x49, 0xCF, - - 0xBB, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x78, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_t2gzs[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x85, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - - 0x61, 0x51, 0xE0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x52, 0xBF, - 0x0F, 0x52, 0xA0, 0xE8, - - 0x1A, 0x42, 0x62, 0xBF, - 0x1E, 0x51, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x0E, 0x61, 0x60, 0xEA, - - 0x32, 0x40, 0x50, 0xBD, - 0x22, 0x40, 0x60, 0xBD, - - 0x12, 0x41, 0x51, 0xBD, - 0x3A, 0x41, 0x61, 0xBD, - - 0xBF, 0x2F, 0x0E, 0xBD, - 0x97, 0xE2, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x35, 0x48, 0xB1, 0xE8, - 0x3D, 0x59, 0xB1, 0xE8, - - 0x46, 0x31, 0x46, 0xBF, - 0x56, 0x31, 0x56, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0x31, 0x66, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x57, 0x39, 0x57, 0xBF, - 0x67, 0x39, 0x67, 0xBF, - - 0x76, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x35, 0x00, - 0x3D, 0x00, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0x8D, 0x2F, 0x1E, 0xBD, - - 0x43, 0x75, 0xF8, 0xEC, - 0x35, 0x20, - 0x3D, 0x20, - - 0x43, 0x43, 0x2D, 0xDF, - 0x53, 0x53, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x0E, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x48, 0x35, 0x48, 0xBF, - 0x58, 0x35, 0x58, 0xBF, - - 0x68, 0x35, 0x68, 0xBF, - 0x49, 0x3D, 0x49, 0xBF, - - 0x59, 0x3D, 0x59, 0xBF, - 0x69, 0x3D, 0x69, 0xBF, - - 0x63, 0x63, 0x2D, 0xDF, - 0x4D, 0x7D, 0xF8, 0xEC, - - 0x59, 0xE3, - 0x00, 0xE0, - 0xB8, 0x38, 0x33, 0xBF, - - 0x2D, 0x73, - 0x30, 0x76, - 0x18, 0x3A, 0x41, 0xE9, - - 0x3F, 0x53, 0xA0, 0xE8, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x63, 0xA0, 0xE8, - - 0x50, 0x70, 0xF8, 0xEC, - 0x2B, 0x50, 0x3C, 0xE9, - - 0x1F, 0x0F, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x59, 0x78, 0xF8, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x46, 0x37, 0x46, 0xDF, - 0x56, 0x3F, 0x56, 0xDF, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x66, 0x3D, 0x66, 0xDF, - - 0x1D, 0x32, 0x41, 0xE9, - 0x67, 0x3D, 0x67, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3F, 0x57, 0xDF, - - 0x2A, 0x40, 0x20, 0xE9, - 0x59, 0x3F, 0x59, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x69, 0x3D, 0x69, 0xDF, - - 0x48, 0x37, 0x48, 0xDF, - 0x58, 0x3F, 0x58, 0xDF, - - 0x68, 0x3D, 0x68, 0xDF, - 0x49, 0x37, 0x49, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x0F, 0xCF, 0x74, 0xC2, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x54, 0xB0, - 0x02, 0x44, 0x64, 0xB0, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x34, 0x37, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x38, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB2, - 0x1A, 0x44, 0x64, 0xB2, - - 0x31, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x0F, 0xCF, 0x75, 0xC0, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x3D, 0xCF, 0x75, 0xC2, - 0x37, 0xCF, 0x75, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA6, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA3, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB4, - 0x1A, 0x44, 0x64, 0xB4, - - 0x0A, 0x45, 0x55, 0xB0, - 0x02, 0x45, 0x65, 0xB0, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA0, 0x37, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x2A, 0x45, 0x55, 0xB2, - 0x1A, 0x45, 0x65, 0xB2, - - 0x0A, 0x45, 0x55, 0xB4, - 0x02, 0x45, 0x65, 0xB4, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x20, - 0x1A, 0x20, - 0x0A, 0x20, - 0x02, 0x20, - - 0x2A, 0x46, 0x56, 0xBF, - 0x1A, 0x46, 0x66, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0xA7, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0xA8, 0x38, 0x4F, 0xE9, - - 0x0A, 0x47, 0x57, 0xBF, - 0x02, 0x47, 0x67, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA4, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA5, 0x39, 0x4F, 0xE9, - - 0x2A, 0x43, 0x53, 0xBF, - 0x1A, 0x43, 0x63, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0xA1, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0xA2, 0x38, 0x4F, 0xE9, - - 0x0A, 0x48, 0x58, 0xBF, - 0x02, 0x48, 0x68, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x2A, 0x49, 0x59, 0xBF, - 0x1A, 0x49, 0x69, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x82, 0x30, 0x57, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x83, 0x38, 0x57, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x84, 0x31, 0x5E, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x85, 0x39, 0x5E, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8A, 0x36, 0x20, 0xE9, - - 0x87, 0x77, 0x57, 0xE9, - 0x8B, 0x3E, 0xBF, 0xEA, - - 0x80, 0x30, 0x57, 0xE9, - 0x81, 0x38, 0x57, 0xE9, - - 0x82, 0x31, 0x57, 0xE9, - 0x86, 0x78, 0x57, 0xE9, - - 0x83, 0x39, 0x57, 0xE9, - 0x87, 0x79, 0x57, 0xE9, - - 0x30, 0x1F, 0x5F, 0xE9, - 0x8A, 0x34, 0x20, 0xE9, - - 0x8B, 0x3C, 0x20, 0xE9, - 0x37, 0x50, 0x60, 0xBD, - - 0x57, 0x0D, 0x20, 0xE9, - 0x35, 0x51, 0x61, 0xBD, - - 0x2B, 0x50, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x0E, 0x77, - - 0x24, 0x51, 0x20, 0xE9, - 0x92, 0xFF, 0x20, 0xEA, - - 0x16, 0x0E, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x0B, 0x46, 0xA0, 0xE8, - 0x1B, 0x56, 0xA0, 0xE8, - - 0x2B, 0x66, 0xA0, 0xE8, - 0x0C, 0x47, 0xA0, 0xE8, - - 0x1C, 0x57, 0xA0, 0xE8, - 0x2C, 0x67, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x57, 0x80, 0x57, 0xCF, - - 0x66, 0x33, 0x66, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x67, 0x3B, 0x67, 0xCF, - - 0x0B, 0x48, 0xA0, 0xE8, - 0x1B, 0x58, 0xA0, 0xE8, - - 0x2B, 0x68, 0xA0, 0xE8, - 0x0C, 0x49, 0xA0, 0xE8, - - 0x1C, 0x59, 0xA0, 0xE8, - 0x2C, 0x69, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x34, 0xD7, 0x34, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3C, 0xD7, 0x3C, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x34, 0x80, 0x34, 0xBD, - 0x3C, 0x80, 0x3C, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x48, 0x80, 0x48, 0xCF, - 0x59, 0x80, 0x59, 0xCF, - - 0x68, 0x33, 0x68, 0xCF, - 0x49, 0x3B, 0x49, 0xCF, - - 0xB2, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x70, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_t2gzsa[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x8A, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - - 0x61, 0x51, 0xE0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x52, 0xBF, - 0x0F, 0x52, 0xA0, 0xE8, - - 0x1A, 0x42, 0x62, 0xBF, - 0x1E, 0x51, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x0E, 0x61, 0x60, 0xEA, - - 0x32, 0x40, 0x50, 0xBD, - 0x22, 0x40, 0x60, 0xBD, - - 0x12, 0x41, 0x51, 0xBD, - 0x3A, 0x41, 0x61, 0xBD, - - 0xBF, 0x2F, 0x0E, 0xBD, - 0x97, 0xE2, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x35, 0x48, 0xB1, 0xE8, - 0x3D, 0x59, 0xB1, 0xE8, - - 0x46, 0x31, 0x46, 0xBF, - 0x56, 0x31, 0x56, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0x31, 0x66, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x57, 0x39, 0x57, 0xBF, - 0x67, 0x39, 0x67, 0xBF, - - 0x7B, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x35, 0x00, - 0x3D, 0x00, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0x8D, 0x2F, 0x1E, 0xBD, - - 0x43, 0x75, 0xF8, 0xEC, - 0x35, 0x20, - 0x3D, 0x20, - - 0x43, 0x43, 0x2D, 0xDF, - 0x53, 0x53, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x0E, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x48, 0x35, 0x48, 0xBF, - 0x58, 0x35, 0x58, 0xBF, - - 0x68, 0x35, 0x68, 0xBF, - 0x49, 0x3D, 0x49, 0xBF, - - 0x59, 0x3D, 0x59, 0xBF, - 0x69, 0x3D, 0x69, 0xBF, - - 0x63, 0x63, 0x2D, 0xDF, - 0x4D, 0x7D, 0xF8, 0xEC, - - 0x59, 0xE3, - 0x00, 0xE0, - 0xB8, 0x38, 0x33, 0xBF, - - 0x2D, 0x73, - 0x30, 0x76, - 0x18, 0x3A, 0x41, 0xE9, - - 0x3F, 0x53, 0xA0, 0xE8, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x63, 0xA0, 0xE8, - - 0x50, 0x70, 0xF8, 0xEC, - 0x2B, 0x50, 0x3C, 0xE9, - - 0x1F, 0x0F, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x59, 0x78, 0xF8, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x46, 0x37, 0x46, 0xDF, - 0x56, 0x3F, 0x56, 0xDF, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x66, 0x3D, 0x66, 0xDF, - - 0x1D, 0x32, 0x41, 0xE9, - 0x67, 0x3D, 0x67, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3F, 0x57, 0xDF, - - 0x2A, 0x40, 0x20, 0xE9, - 0x59, 0x3F, 0x59, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x69, 0x3D, 0x69, 0xDF, - - 0x48, 0x37, 0x48, 0xDF, - 0x58, 0x3F, 0x58, 0xDF, - - 0x68, 0x3D, 0x68, 0xDF, - 0x49, 0x37, 0x49, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x0F, 0xCF, 0x74, 0xC2, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x54, 0xB0, - 0x02, 0x44, 0x64, 0xB0, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x34, 0x37, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x38, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB2, - 0x1A, 0x44, 0x64, 0xB2, - - 0x36, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x0F, 0xCF, 0x75, 0xC0, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x3D, 0xCF, 0x75, 0xC2, - 0x37, 0xCF, 0x75, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA6, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA3, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB4, - 0x1A, 0x44, 0x64, 0xB4, - - 0x0A, 0x45, 0x55, 0xB0, - 0x02, 0x45, 0x65, 0xB0, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA0, 0x37, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x45, 0x55, 0xB2, - 0x1A, 0x45, 0x65, 0xB2, - - 0x0A, 0x45, 0x55, 0xB4, - 0x02, 0x45, 0x65, 0xB4, - - 0x0F, 0xCF, 0x74, 0xC6, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA7, 0x30, 0x4F, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9C, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA8, 0x38, 0x4F, 0xE9, - - 0x2A, 0x44, 0x54, 0xB6, - 0x1A, 0x44, 0x64, 0xB6, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x56, 0xBF, - 0x1A, 0x46, 0x66, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA4, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA5, 0x39, 0x4F, 0xE9, - - 0x0A, 0x47, 0x57, 0xBF, - 0x02, 0x47, 0x67, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA1, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA2, 0x38, 0x4F, 0xE9, - - 0x2A, 0x43, 0x53, 0xBF, - 0x1A, 0x43, 0x63, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x9D, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x9E, 0x39, 0x4F, 0xE9, - - 0x0A, 0x48, 0x58, 0xBF, - 0x02, 0x48, 0x68, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x2A, 0x49, 0x59, 0xBF, - 0x1A, 0x49, 0x69, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x82, 0x30, 0x57, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x83, 0x38, 0x57, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x84, 0x31, 0x5E, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x85, 0x39, 0x5E, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8A, 0x36, 0x20, 0xE9, - - 0x87, 0x77, 0x57, 0xE9, - 0x8B, 0x3E, 0xBF, 0xEA, - - 0x80, 0x30, 0x57, 0xE9, - 0x81, 0x38, 0x57, 0xE9, - - 0x82, 0x31, 0x57, 0xE9, - 0x86, 0x78, 0x57, 0xE9, - - 0x83, 0x39, 0x57, 0xE9, - 0x87, 0x79, 0x57, 0xE9, - - 0x30, 0x1F, 0x5F, 0xE9, - 0x8A, 0x34, 0x20, 0xE9, - - 0x8B, 0x3C, 0x20, 0xE9, - 0x37, 0x50, 0x60, 0xBD, - - 0x57, 0x0D, 0x20, 0xE9, - 0x35, 0x51, 0x61, 0xBD, - - 0x2B, 0x50, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x0E, 0x77, - - 0x24, 0x51, 0x20, 0xE9, - 0x8D, 0xFF, 0x20, 0xEA, - - 0x16, 0x0E, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x0B, 0x46, 0xA0, 0xE8, - 0x1B, 0x56, 0xA0, 0xE8, - - 0x2B, 0x66, 0xA0, 0xE8, - 0x0C, 0x47, 0xA0, 0xE8, - - 0x1C, 0x57, 0xA0, 0xE8, - 0x2C, 0x67, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x57, 0x80, 0x57, 0xCF, - - 0x66, 0x33, 0x66, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x67, 0x3B, 0x67, 0xCF, - - 0x0B, 0x48, 0xA0, 0xE8, - 0x1B, 0x58, 0xA0, 0xE8, - - 0x2B, 0x68, 0xA0, 0xE8, - 0x0C, 0x49, 0xA0, 0xE8, - - 0x1C, 0x59, 0xA0, 0xE8, - 0x2C, 0x69, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x34, 0xD7, 0x34, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3C, 0xD7, 0x3C, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x34, 0x80, 0x34, 0xBD, - 0x3C, 0x80, 0x3C, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x48, 0x80, 0x48, 0xCF, - 0x59, 0x80, 0x59, 0xCF, - - 0x68, 0x33, 0x68, 0xCF, - 0x49, 0x3B, 0x49, 0xCF, - - 0xAD, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x6B, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_t2gzsaf[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x8E, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - - 0x61, 0x51, 0xE0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x52, 0xBF, - 0x0F, 0x52, 0xA0, 0xE8, - - 0x1A, 0x42, 0x62, 0xBF, - 0x1E, 0x51, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x0E, 0x61, 0x60, 0xEA, - - 0x32, 0x40, 0x50, 0xBD, - 0x22, 0x40, 0x60, 0xBD, - - 0x12, 0x41, 0x51, 0xBD, - 0x3A, 0x41, 0x61, 0xBD, - - 0xBF, 0x2F, 0x0E, 0xBD, - 0x97, 0xE2, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x35, 0x48, 0xB1, 0xE8, - 0x3D, 0x59, 0xB1, 0xE8, - - 0x46, 0x31, 0x46, 0xBF, - 0x56, 0x31, 0x56, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0x31, 0x66, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x57, 0x39, 0x57, 0xBF, - 0x67, 0x39, 0x67, 0xBF, - - 0x7F, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x35, 0x00, - 0x3D, 0x00, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0x8D, 0x2F, 0x1E, 0xBD, - - 0x43, 0x75, 0xF8, 0xEC, - 0x35, 0x20, - 0x3D, 0x20, - - 0x43, 0x43, 0x2D, 0xDF, - 0x53, 0x53, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x0E, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x48, 0x35, 0x48, 0xBF, - 0x58, 0x35, 0x58, 0xBF, - - 0x68, 0x35, 0x68, 0xBF, - 0x49, 0x3D, 0x49, 0xBF, - - 0x59, 0x3D, 0x59, 0xBF, - 0x69, 0x3D, 0x69, 0xBF, - - 0x63, 0x63, 0x2D, 0xDF, - 0x4D, 0x7D, 0xF8, 0xEC, - - 0x59, 0xE3, - 0x00, 0xE0, - 0xB8, 0x38, 0x33, 0xBF, - - 0x2D, 0x73, - 0x30, 0x76, - 0x18, 0x3A, 0x41, 0xE9, - - 0x3F, 0x53, 0xA0, 0xE8, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x63, 0xA0, 0xE8, - - 0x50, 0x70, 0xF8, 0xEC, - 0x2B, 0x50, 0x3C, 0xE9, - - 0x1F, 0x0F, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x59, 0x78, 0xF8, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x46, 0x37, 0x46, 0xDF, - 0x56, 0x3F, 0x56, 0xDF, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x66, 0x3D, 0x66, 0xDF, - - 0x1D, 0x32, 0x41, 0xE9, - 0x67, 0x3D, 0x67, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3F, 0x57, 0xDF, - - 0x2A, 0x40, 0x20, 0xE9, - 0x59, 0x3F, 0x59, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x69, 0x3D, 0x69, 0xDF, - - 0x48, 0x37, 0x48, 0xDF, - 0x58, 0x3F, 0x58, 0xDF, - - 0x68, 0x3D, 0x68, 0xDF, - 0x49, 0x37, 0x49, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x0F, 0xCF, 0x74, 0xC2, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x54, 0xB0, - 0x02, 0x44, 0x64, 0xB0, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x34, 0x37, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x38, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB2, - 0x1A, 0x44, 0x64, 0xB2, - - 0x3A, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x0F, 0xCF, 0x75, 0xC0, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x3D, 0xCF, 0x75, 0xC2, - 0x37, 0xCF, 0x75, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA6, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA3, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB4, - 0x1A, 0x44, 0x64, 0xB4, - - 0x0A, 0x45, 0x55, 0xB0, - 0x02, 0x45, 0x65, 0xB0, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA0, 0x37, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x45, 0x55, 0xB2, - 0x1A, 0x45, 0x65, 0xB2, - - 0x0A, 0x45, 0x55, 0xB4, - 0x02, 0x45, 0x65, 0xB4, - - 0x0F, 0xCF, 0x74, 0xC6, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA7, 0x30, 0x4F, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9C, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA8, 0x38, 0x4F, 0xE9, - - 0x2A, 0x44, 0x54, 0xB6, - 0x1A, 0x44, 0x64, 0xB6, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x0A, 0x45, 0x55, 0xB6, - 0x02, 0x45, 0x65, 0xB6, - - 0x3D, 0xCF, 0x75, 0xC6, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x56, 0xBF, - 0x1A, 0x46, 0x66, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA4, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA5, 0x39, 0x4F, 0xE9, - - 0x31, 0x3D, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x0A, 0x47, 0x57, 0xBF, - 0x02, 0x47, 0x67, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0xA1, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0xA2, 0x38, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9D, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x9E, 0x39, 0x4F, 0xE9, - - 0x2A, 0x43, 0x53, 0xBF, - 0x1A, 0x43, 0x63, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x35, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x39, 0x38, 0x4F, 0xE9, - - 0x0A, 0x48, 0x58, 0xBF, - 0x02, 0x48, 0x68, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x2A, 0x49, 0x59, 0xBF, - 0x1A, 0x49, 0x69, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x82, 0x30, 0x57, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x83, 0x38, 0x57, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x84, 0x31, 0x5E, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x85, 0x39, 0x5E, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8A, 0x36, 0x20, 0xE9, - - 0x87, 0x77, 0x57, 0xE9, - 0x8B, 0x3E, 0xBF, 0xEA, - - 0x80, 0x30, 0x57, 0xE9, - 0x81, 0x38, 0x57, 0xE9, - - 0x82, 0x31, 0x57, 0xE9, - 0x86, 0x78, 0x57, 0xE9, - - 0x83, 0x39, 0x57, 0xE9, - 0x87, 0x79, 0x57, 0xE9, - - 0x30, 0x1F, 0x5F, 0xE9, - 0x8A, 0x34, 0x20, 0xE9, - - 0x8B, 0x3C, 0x20, 0xE9, - 0x37, 0x50, 0x60, 0xBD, - - 0x57, 0x0D, 0x20, 0xE9, - 0x35, 0x51, 0x61, 0xBD, - - 0x2B, 0x50, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x0E, 0x77, - - 0x24, 0x51, 0x20, 0xE9, - 0x89, 0xFF, 0x20, 0xEA, - - 0x16, 0x0E, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x0B, 0x46, 0xA0, 0xE8, - 0x1B, 0x56, 0xA0, 0xE8, - - 0x2B, 0x66, 0xA0, 0xE8, - 0x0C, 0x47, 0xA0, 0xE8, - - 0x1C, 0x57, 0xA0, 0xE8, - 0x2C, 0x67, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x57, 0x80, 0x57, 0xCF, - - 0x66, 0x33, 0x66, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x67, 0x3B, 0x67, 0xCF, - - 0x0B, 0x48, 0xA0, 0xE8, - 0x1B, 0x58, 0xA0, 0xE8, - - 0x2B, 0x68, 0xA0, 0xE8, - 0x0C, 0x49, 0xA0, 0xE8, - - 0x1C, 0x59, 0xA0, 0xE8, - 0x2C, 0x69, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x34, 0xD7, 0x34, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3C, 0xD7, 0x3C, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x34, 0x80, 0x34, 0xBD, - 0x3C, 0x80, 0x3C, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x48, 0x80, 0x48, 0xCF, - 0x59, 0x80, 0x59, 0xCF, - - 0x68, 0x33, 0x68, 0xCF, - 0x49, 0x3B, 0x49, 0xCF, - - 0xA9, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x67, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_t2gzsf[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x8A, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - - 0x61, 0x51, 0xE0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x52, 0xBF, - 0x0F, 0x52, 0xA0, 0xE8, - - 0x1A, 0x42, 0x62, 0xBF, - 0x1E, 0x51, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x0E, 0x61, 0x60, 0xEA, - - 0x32, 0x40, 0x50, 0xBD, - 0x22, 0x40, 0x60, 0xBD, - - 0x12, 0x41, 0x51, 0xBD, - 0x3A, 0x41, 0x61, 0xBD, - - 0xBF, 0x2F, 0x0E, 0xBD, - 0x97, 0xE2, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x35, 0x48, 0xB1, 0xE8, - 0x3D, 0x59, 0xB1, 0xE8, - - 0x46, 0x31, 0x46, 0xBF, - 0x56, 0x31, 0x56, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0x31, 0x66, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x57, 0x39, 0x57, 0xBF, - 0x67, 0x39, 0x67, 0xBF, - - 0x7B, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x35, 0x00, - 0x3D, 0x00, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0x8D, 0x2F, 0x1E, 0xBD, - - 0x43, 0x75, 0xF8, 0xEC, - 0x35, 0x20, - 0x3D, 0x20, - - 0x43, 0x43, 0x2D, 0xDF, - 0x53, 0x53, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x0E, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x48, 0x35, 0x48, 0xBF, - 0x58, 0x35, 0x58, 0xBF, - - 0x68, 0x35, 0x68, 0xBF, - 0x49, 0x3D, 0x49, 0xBF, - - 0x59, 0x3D, 0x59, 0xBF, - 0x69, 0x3D, 0x69, 0xBF, - - 0x63, 0x63, 0x2D, 0xDF, - 0x4D, 0x7D, 0xF8, 0xEC, - - 0x59, 0xE3, - 0x00, 0xE0, - 0xB8, 0x38, 0x33, 0xBF, - - 0x2D, 0x73, - 0x30, 0x76, - 0x18, 0x3A, 0x41, 0xE9, - - 0x3F, 0x53, 0xA0, 0xE8, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x63, 0xA0, 0xE8, - - 0x50, 0x70, 0xF8, 0xEC, - 0x2B, 0x50, 0x3C, 0xE9, - - 0x1F, 0x0F, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x59, 0x78, 0xF8, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x46, 0x37, 0x46, 0xDF, - 0x56, 0x3F, 0x56, 0xDF, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x66, 0x3D, 0x66, 0xDF, - - 0x1D, 0x32, 0x41, 0xE9, - 0x67, 0x3D, 0x67, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3F, 0x57, 0xDF, - - 0x2A, 0x40, 0x20, 0xE9, - 0x59, 0x3F, 0x59, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x69, 0x3D, 0x69, 0xDF, - - 0x48, 0x37, 0x48, 0xDF, - 0x58, 0x3F, 0x58, 0xDF, - - 0x68, 0x3D, 0x68, 0xDF, - 0x49, 0x37, 0x49, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x0F, 0xCF, 0x74, 0xC2, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x54, 0xB0, - 0x02, 0x44, 0x64, 0xB0, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x34, 0x37, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x38, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB2, - 0x1A, 0x44, 0x64, 0xB2, - - 0x36, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x0F, 0xCF, 0x75, 0xC0, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x3D, 0xCF, 0x75, 0xC2, - 0x37, 0xCF, 0x75, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA6, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA3, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB4, - 0x1A, 0x44, 0x64, 0xB4, - - 0x0A, 0x45, 0x55, 0xB0, - 0x02, 0x45, 0x65, 0xB0, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA0, 0x37, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x45, 0x55, 0xB2, - 0x1A, 0x45, 0x65, 0xB2, - - 0x0A, 0x45, 0x55, 0xB4, - 0x02, 0x45, 0x65, 0xB4, - - 0x0F, 0xCF, 0x75, 0xC6, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA7, 0x30, 0x4F, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x31, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA8, 0x38, 0x4F, 0xE9, - - 0x2A, 0x45, 0x55, 0xB6, - 0x1A, 0x45, 0x65, 0xB6, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x56, 0xBF, - 0x1A, 0x46, 0x66, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA4, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA5, 0x39, 0x4F, 0xE9, - - 0x0A, 0x47, 0x57, 0xBF, - 0x02, 0x47, 0x67, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA1, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA2, 0x38, 0x4F, 0xE9, - - 0x2A, 0x43, 0x53, 0xBF, - 0x1A, 0x43, 0x63, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x35, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x39, 0x39, 0x4F, 0xE9, - - 0x0A, 0x48, 0x58, 0xBF, - 0x02, 0x48, 0x68, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x2A, 0x49, 0x59, 0xBF, - 0x1A, 0x49, 0x69, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x82, 0x30, 0x57, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x83, 0x38, 0x57, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x84, 0x31, 0x5E, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x85, 0x39, 0x5E, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8A, 0x36, 0x20, 0xE9, - - 0x87, 0x77, 0x57, 0xE9, - 0x8B, 0x3E, 0xBF, 0xEA, - - 0x80, 0x30, 0x57, 0xE9, - 0x81, 0x38, 0x57, 0xE9, - - 0x82, 0x31, 0x57, 0xE9, - 0x86, 0x78, 0x57, 0xE9, - - 0x83, 0x39, 0x57, 0xE9, - 0x87, 0x79, 0x57, 0xE9, - - 0x30, 0x1F, 0x5F, 0xE9, - 0x8A, 0x34, 0x20, 0xE9, - - 0x8B, 0x3C, 0x20, 0xE9, - 0x37, 0x50, 0x60, 0xBD, - - 0x57, 0x0D, 0x20, 0xE9, - 0x35, 0x51, 0x61, 0xBD, - - 0x2B, 0x50, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x0E, 0x77, - - 0x24, 0x51, 0x20, 0xE9, - 0x8D, 0xFF, 0x20, 0xEA, - - 0x16, 0x0E, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x0B, 0x46, 0xA0, 0xE8, - 0x1B, 0x56, 0xA0, 0xE8, - - 0x2B, 0x66, 0xA0, 0xE8, - 0x0C, 0x47, 0xA0, 0xE8, - - 0x1C, 0x57, 0xA0, 0xE8, - 0x2C, 0x67, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x57, 0x80, 0x57, 0xCF, - - 0x66, 0x33, 0x66, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x67, 0x3B, 0x67, 0xCF, - - 0x0B, 0x48, 0xA0, 0xE8, - 0x1B, 0x58, 0xA0, 0xE8, - - 0x2B, 0x68, 0xA0, 0xE8, - 0x0C, 0x49, 0xA0, 0xE8, - - 0x1C, 0x59, 0xA0, 0xE8, - 0x2C, 0x69, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x34, 0xD7, 0x34, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3C, 0xD7, 0x3C, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x34, 0x80, 0x34, 0xBD, - 0x3C, 0x80, 0x3C, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x48, 0x80, 0x48, 0xCF, - 0x59, 0x80, 0x59, 0xCF, - - 0x68, 0x33, 0x68, 0xCF, - 0x49, 0x3B, 0x49, 0xCF, - - 0xAD, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x6B, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_tgz[] = { - - 0x00, 0x88, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x22, 0x40, 0x48, 0xBF, - 0x2A, 0x40, 0x50, 0xBF, - - 0x32, 0x41, 0x49, 0xBF, - 0x3A, 0x41, 0x51, 0xBF, - - 0xC3, 0x6B, - 0xCB, 0x6B, - 0x00, 0x88, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x4B, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x29, 0x9F, - 0x00, 0xE0, - 0x49, 0x04, - - 0x90, 0xE2, - 0x51, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x49, 0x41, 0xC0, 0xEC, - 0x39, 0x57, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x53, 0xA0, 0xE8, - - 0x51, 0x41, 0xC0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x58, 0x80, 0x15, 0xEA, - 0x08, 0x04, - 0x10, 0x04, - - 0x51, 0x49, 0xC0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x4A, 0xBF, - 0x27, 0x4A, 0xA0, 0xE8, - - 0x1A, 0x42, 0x52, 0xBF, - 0x1E, 0x49, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x26, 0x51, 0x60, 0xEA, - - 0x32, 0x40, 0x48, 0xBD, - 0x22, 0x40, 0x50, 0xBD, - - 0x12, 0x41, 0x49, 0xBD, - 0x3A, 0x41, 0x51, 0xBD, - - 0xBF, 0x2F, 0x26, 0xBD, - 0x00, 0xE0, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x46, 0x31, 0x46, 0xBF, - 0x4E, 0x31, 0x4E, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x56, 0x31, 0x56, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x4F, 0x39, 0x4F, 0xBF, - 0x57, 0x39, 0x57, 0xBF, - - 0x4A, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x42, 0x73, 0xF8, 0xEC, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0xA5, 0x2F, 0x1E, 0xBD, - - 0x43, 0x43, 0x2D, 0xDF, - 0x4B, 0x4B, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x26, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x53, 0x53, 0x2D, 0xDF, - 0x00, 0x80, 0x00, 0xE8, - - 0xB8, 0x38, 0x33, 0xBF, - 0x00, 0xE0, - 0x59, 0xE3, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x3F, 0x4B, 0xA0, 0xE8, - - 0x2D, 0x73, - 0x30, 0x76, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x53, 0xA0, 0xE8, - - 0x48, 0x70, 0xF8, 0xEC, - 0x2B, 0x48, 0x3C, 0xE9, - - 0x1F, 0x27, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x18, 0x3A, 0x41, 0xE9, - 0x1D, 0x32, 0x41, 0xE9, - - 0x2A, 0x40, 0x20, 0xE9, - 0x56, 0x3D, 0x56, 0xDF, - - 0x46, 0x37, 0x46, 0xDF, - 0x4E, 0x3F, 0x4E, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x4F, 0x3F, 0x4F, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3D, 0x57, 0xDF, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x37, 0xCF, 0x74, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0x34, 0x80, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x0A, 0x44, 0x4C, 0xB0, - 0x02, 0x44, 0x54, 0xB0, - - 0x2A, 0x44, 0x4C, 0xB2, - 0x1A, 0x44, 0x54, 0xB2, - - 0x1D, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x3D, 0xCF, 0x74, 0xC2, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x2A, 0x44, 0x4C, 0xB4, - 0x1A, 0x44, 0x54, 0xB4, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x38, 0x3D, 0x20, 0xE9, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x4E, 0xBF, - 0x1A, 0x46, 0x56, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x0A, 0x47, 0x4F, 0xBF, - 0x02, 0x47, 0x57, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x43, 0x4B, 0xBF, - 0x1A, 0x43, 0x53, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x37, 0x48, 0x50, 0xBD, - 0x8A, 0x36, 0x20, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8B, 0x3E, 0x20, 0xE9, - - 0x82, 0x30, 0x57, 0xE9, - 0x87, 0x77, 0x57, 0xE9, - - 0x83, 0x38, 0x57, 0xE9, - 0x35, 0x49, 0x51, 0xBD, - - 0x84, 0x31, 0x5E, 0xE9, - 0x30, 0x1F, 0x5F, 0xE9, - - 0x85, 0x39, 0x5E, 0xE9, - 0x57, 0x25, 0x20, 0xE9, - - 0x2B, 0x48, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0xAF, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xD6, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x9D, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_tgza[] = { - - 0x00, 0x88, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x22, 0x40, 0x48, 0xBF, - 0x2A, 0x40, 0x50, 0xBF, - - 0x32, 0x41, 0x49, 0xBF, - 0x3A, 0x41, 0x51, 0xBF, - - 0xC3, 0x6B, - 0xCB, 0x6B, - 0x00, 0x88, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x4B, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x29, 0x9F, - 0x00, 0xE0, - 0x49, 0x04, - - 0x90, 0xE2, - 0x51, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x49, 0x41, 0xC0, 0xEC, - 0x39, 0x57, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x53, 0xA0, 0xE8, - - 0x51, 0x41, 0xC0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x5C, 0x80, 0x15, 0xEA, - 0x08, 0x04, - 0x10, 0x04, - - 0x51, 0x49, 0xC0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x4A, 0xBF, - 0x27, 0x4A, 0xA0, 0xE8, - - 0x1A, 0x42, 0x52, 0xBF, - 0x1E, 0x49, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x26, 0x51, 0x60, 0xEA, - - 0x32, 0x40, 0x48, 0xBD, - 0x22, 0x40, 0x50, 0xBD, - - 0x12, 0x41, 0x49, 0xBD, - 0x3A, 0x41, 0x51, 0xBD, - - 0xBF, 0x2F, 0x26, 0xBD, - 0x00, 0xE0, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x46, 0x31, 0x46, 0xBF, - 0x4E, 0x31, 0x4E, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x56, 0x31, 0x56, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x4F, 0x39, 0x4F, 0xBF, - 0x57, 0x39, 0x57, 0xBF, - - 0x4E, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x42, 0x73, 0xF8, 0xEC, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0xA5, 0x2F, 0x1E, 0xBD, - - 0x43, 0x43, 0x2D, 0xDF, - 0x4B, 0x4B, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x26, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x53, 0x53, 0x2D, 0xDF, - 0x00, 0x80, 0x00, 0xE8, - - 0xB8, 0x38, 0x33, 0xBF, - 0x00, 0xE0, - 0x59, 0xE3, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x3F, 0x4B, 0xA0, 0xE8, - - 0x2D, 0x73, - 0x30, 0x76, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x53, 0xA0, 0xE8, - - 0x48, 0x70, 0xF8, 0xEC, - 0x2B, 0x48, 0x3C, 0xE9, - - 0x1F, 0x27, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x18, 0x3A, 0x41, 0xE9, - 0x1D, 0x32, 0x41, 0xE9, - - 0x2A, 0x40, 0x20, 0xE9, - 0x56, 0x3D, 0x56, 0xDF, - - 0x46, 0x37, 0x46, 0xDF, - 0x4E, 0x3F, 0x4E, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x4F, 0x3F, 0x4F, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3D, 0x57, 0xDF, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x37, 0xCF, 0x74, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0x34, 0x80, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x27, 0xCF, 0x74, 0xC6, - 0x3D, 0xCF, 0x74, 0xC2, - - 0x0A, 0x44, 0x4C, 0xB0, - 0x02, 0x44, 0x54, 0xB0, - - 0x2A, 0x44, 0x4C, 0xB2, - 0x1A, 0x44, 0x54, 0xB2, - - 0x20, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9C, 0x27, 0x20, 0xE9, - - 0x0A, 0x44, 0x4C, 0xB4, - 0x02, 0x44, 0x54, 0xB4, - - 0x2A, 0x44, 0x4C, 0xB6, - 0x1A, 0x44, 0x54, 0xB6, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x38, 0x3D, 0x20, 0xE9, - - 0x0A, 0x20, - 0x02, 0x20, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x0A, 0x47, 0x4F, 0xBF, - 0x02, 0x47, 0x57, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x2A, 0x46, 0x4E, 0xBF, - 0x1A, 0x46, 0x56, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x36, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x37, 0x38, 0x4F, 0xE9, - - 0x2A, 0x43, 0x4B, 0xBF, - 0x1A, 0x43, 0x53, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x9D, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x9E, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x37, 0x48, 0x50, 0xBD, - 0x8A, 0x36, 0x20, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8B, 0x3E, 0x20, 0xE9, - - 0x82, 0x30, 0x57, 0xE9, - 0x87, 0x77, 0x57, 0xE9, - - 0x83, 0x38, 0x57, 0xE9, - 0x35, 0x49, 0x51, 0xBD, - - 0x84, 0x31, 0x5E, 0xE9, - 0x30, 0x1F, 0x5F, 0xE9, - - 0x85, 0x39, 0x5E, 0xE9, - 0x57, 0x25, 0x20, 0xE9, - - 0x2B, 0x48, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0xAB, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xD3, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x99, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_tgzaf[] = { - - 0x00, 0x88, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x22, 0x40, 0x48, 0xBF, - 0x2A, 0x40, 0x50, 0xBF, - - 0x32, 0x41, 0x49, 0xBF, - 0x3A, 0x41, 0x51, 0xBF, - - 0xC3, 0x6B, - 0xCB, 0x6B, - 0x00, 0x88, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x4B, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x29, 0x9F, - 0x00, 0xE0, - 0x49, 0x04, - - 0x90, 0xE2, - 0x51, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x49, 0x41, 0xC0, 0xEC, - 0x39, 0x57, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x53, 0xA0, 0xE8, - - 0x51, 0x41, 0xC0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x61, 0x80, 0x15, 0xEA, - 0x08, 0x04, - 0x10, 0x04, - - 0x51, 0x49, 0xC0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x4A, 0xBF, - 0x27, 0x4A, 0xA0, 0xE8, - - 0x1A, 0x42, 0x52, 0xBF, - 0x1E, 0x49, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x26, 0x51, 0x60, 0xEA, - - 0x32, 0x40, 0x48, 0xBD, - 0x22, 0x40, 0x50, 0xBD, - - 0x12, 0x41, 0x49, 0xBD, - 0x3A, 0x41, 0x51, 0xBD, - - 0xBF, 0x2F, 0x26, 0xBD, - 0x00, 0xE0, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x46, 0x31, 0x46, 0xBF, - 0x4E, 0x31, 0x4E, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x56, 0x31, 0x56, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x4F, 0x39, 0x4F, 0xBF, - 0x57, 0x39, 0x57, 0xBF, - - 0x53, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x42, 0x73, 0xF8, 0xEC, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0xA5, 0x2F, 0x1E, 0xBD, - - 0x43, 0x43, 0x2D, 0xDF, - 0x4B, 0x4B, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x26, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x53, 0x53, 0x2D, 0xDF, - 0x00, 0x80, 0x00, 0xE8, - - 0xB8, 0x38, 0x33, 0xBF, - 0x00, 0xE0, - 0x59, 0xE3, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x3F, 0x4B, 0xA0, 0xE8, - - 0x2D, 0x73, - 0x30, 0x76, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x53, 0xA0, 0xE8, - - 0x48, 0x70, 0xF8, 0xEC, - 0x2B, 0x48, 0x3C, 0xE9, - - 0x1F, 0x27, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x18, 0x3A, 0x41, 0xE9, - 0x1D, 0x32, 0x41, 0xE9, - - 0x2A, 0x40, 0x20, 0xE9, - 0x56, 0x3D, 0x56, 0xDF, - - 0x46, 0x37, 0x46, 0xDF, - 0x4E, 0x3F, 0x4E, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x4F, 0x3F, 0x4F, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3D, 0x57, 0xDF, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x4C, 0xB0, - 0x02, 0x44, 0x54, 0xB0, - - 0x31, 0x53, 0x2F, 0x9F, - 0x34, 0x37, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB2, - 0x1A, 0x44, 0x54, 0xB2, - - 0x26, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x3D, 0xCF, 0x74, 0xC2, - 0x27, 0xCF, 0x74, 0xC6, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9C, 0x27, 0x20, 0xE9, - - 0x0A, 0x44, 0x4C, 0xB4, - 0x02, 0x44, 0x54, 0xB4, - - 0x2A, 0x44, 0x4C, 0xB6, - 0x1A, 0x44, 0x54, 0xB6, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x38, 0x3D, 0x20, 0xE9, - - 0x0A, 0x20, - 0x02, 0x20, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x3D, 0xCF, 0x75, 0xC6, - 0x00, 0x80, 0x00, 0xE8, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x0A, 0x45, 0x4D, 0xB6, - 0x02, 0x45, 0x55, 0xB6, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x31, 0x3D, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x2A, 0x46, 0x4E, 0xBF, - 0x1A, 0x46, 0x56, 0xBF, - - 0x0A, 0x47, 0x4F, 0xBF, - 0x02, 0x47, 0x57, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x38, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9D, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x9E, 0x39, 0x4F, 0xE9, - - 0x2A, 0x43, 0x4B, 0xBF, - 0x1A, 0x43, 0x53, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x35, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x39, 0x38, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x37, 0x48, 0x50, 0xBD, - 0x8A, 0x36, 0x20, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8B, 0x3E, 0x20, 0xE9, - - 0x82, 0x30, 0x57, 0xE9, - 0x87, 0x77, 0x57, 0xE9, - - 0x83, 0x38, 0x57, 0xE9, - 0x35, 0x49, 0x51, 0xBD, - - 0x84, 0x31, 0x5E, 0xE9, - 0x30, 0x1F, 0x5F, 0xE9, - - 0x85, 0x39, 0x5E, 0xE9, - 0x57, 0x25, 0x20, 0xE9, - - 0x2B, 0x48, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0xA6, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xCD, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x94, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_tgzf[] = { - - 0x00, 0x88, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x22, 0x40, 0x48, 0xBF, - 0x2A, 0x40, 0x50, 0xBF, - - 0x32, 0x41, 0x49, 0xBF, - 0x3A, 0x41, 0x51, 0xBF, - - 0xC3, 0x6B, - 0xCB, 0x6B, - 0x00, 0x88, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x4B, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x29, 0x9F, - 0x00, 0xE0, - 0x49, 0x04, - - 0x90, 0xE2, - 0x51, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x49, 0x41, 0xC0, 0xEC, - 0x39, 0x57, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x53, 0xA0, 0xE8, - - 0x51, 0x41, 0xC0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x5D, 0x80, 0x15, 0xEA, - 0x08, 0x04, - 0x10, 0x04, - - 0x51, 0x49, 0xC0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x4A, 0xBF, - 0x27, 0x4A, 0xA0, 0xE8, - - 0x1A, 0x42, 0x52, 0xBF, - 0x1E, 0x49, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x26, 0x51, 0x60, 0xEA, - - 0x32, 0x40, 0x48, 0xBD, - 0x22, 0x40, 0x50, 0xBD, - - 0x12, 0x41, 0x49, 0xBD, - 0x3A, 0x41, 0x51, 0xBD, - - 0xBF, 0x2F, 0x26, 0xBD, - 0x00, 0xE0, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x46, 0x31, 0x46, 0xBF, - 0x4E, 0x31, 0x4E, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x56, 0x31, 0x56, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x4F, 0x39, 0x4F, 0xBF, - 0x57, 0x39, 0x57, 0xBF, - - 0x4F, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x42, 0x73, 0xF8, 0xEC, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0xA5, 0x2F, 0x1E, 0xBD, - - 0x43, 0x43, 0x2D, 0xDF, - 0x4B, 0x4B, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x26, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x53, 0x53, 0x2D, 0xDF, - 0x00, 0x80, 0x00, 0xE8, - - 0xB8, 0x38, 0x33, 0xBF, - 0x00, 0xE0, - 0x59, 0xE3, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x3F, 0x4B, 0xA0, 0xE8, - - 0x2D, 0x73, - 0x30, 0x76, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x53, 0xA0, 0xE8, - - 0x48, 0x70, 0xF8, 0xEC, - 0x2B, 0x48, 0x3C, 0xE9, - - 0x1F, 0x27, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x18, 0x3A, 0x41, 0xE9, - 0x1D, 0x32, 0x41, 0xE9, - - 0x2A, 0x40, 0x20, 0xE9, - 0x56, 0x3D, 0x56, 0xDF, - - 0x46, 0x37, 0x46, 0xDF, - 0x4E, 0x3F, 0x4E, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x4F, 0x3F, 0x4F, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3D, 0x57, 0xDF, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x37, 0xCF, 0x74, 0xC4, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x34, 0x80, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x88, 0x73, 0x5E, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x27, 0xCF, 0x75, 0xC6, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x0A, 0x44, 0x4C, 0xB0, - 0x02, 0x44, 0x54, 0xB0, - - 0x2A, 0x44, 0x4C, 0xB2, - 0x1A, 0x44, 0x54, 0xB2, - - 0x20, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x3D, 0xCF, 0x74, 0xC2, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x31, 0x27, 0x20, 0xE9, - - 0x0A, 0x44, 0x4C, 0xB4, - 0x02, 0x44, 0x54, 0xB4, - - 0x2A, 0x45, 0x4D, 0xB6, - 0x1A, 0x45, 0x55, 0xB6, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x38, 0x3D, 0x20, 0xE9, - - 0x0A, 0x20, - 0x02, 0x20, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x0A, 0x47, 0x4F, 0xBF, - 0x02, 0x47, 0x57, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x2A, 0x46, 0x4E, 0xBF, - 0x1A, 0x46, 0x56, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x36, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x37, 0x38, 0x4F, 0xE9, - - 0x2A, 0x43, 0x4B, 0xBF, - 0x1A, 0x43, 0x53, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x35, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x39, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x37, 0x48, 0x50, 0xBD, - 0x8A, 0x36, 0x20, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8B, 0x3E, 0x20, 0xE9, - - 0x82, 0x30, 0x57, 0xE9, - 0x87, 0x77, 0x57, 0xE9, - - 0x83, 0x38, 0x57, 0xE9, - 0x35, 0x49, 0x51, 0xBD, - - 0x84, 0x31, 0x5E, 0xE9, - 0x30, 0x1F, 0x5F, 0xE9, - - 0x85, 0x39, 0x5E, 0xE9, - 0x57, 0x25, 0x20, 0xE9, - - 0x2B, 0x48, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0xAA, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xD3, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x98, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_tgzs[] = { - - 0x00, 0x88, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x22, 0x40, 0x48, 0xBF, - 0x2A, 0x40, 0x50, 0xBF, - - 0x32, 0x41, 0x49, 0xBF, - 0x3A, 0x41, 0x51, 0xBF, - - 0xC3, 0x6B, - 0xCB, 0x6B, - 0x00, 0x88, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x4B, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x29, 0x9F, - 0x00, 0xE0, - 0x49, 0x04, - - 0x90, 0xE2, - 0x51, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x49, 0x41, 0xC0, 0xEC, - 0x39, 0x57, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x53, 0xA0, 0xE8, - - 0x51, 0x41, 0xC0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x65, 0x80, 0x15, 0xEA, - 0x08, 0x04, - 0x10, 0x04, - - 0x51, 0x49, 0xC0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x4A, 0xBF, - 0x27, 0x4A, 0xA0, 0xE8, - - 0x1A, 0x42, 0x52, 0xBF, - 0x1E, 0x49, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x26, 0x51, 0x60, 0xEA, - - 0x32, 0x40, 0x48, 0xBD, - 0x22, 0x40, 0x50, 0xBD, - - 0x12, 0x41, 0x49, 0xBD, - 0x3A, 0x41, 0x51, 0xBD, - - 0xBF, 0x2F, 0x26, 0xBD, - 0x00, 0xE0, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x46, 0x31, 0x46, 0xBF, - 0x4E, 0x31, 0x4E, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x56, 0x31, 0x56, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x4F, 0x39, 0x4F, 0xBF, - 0x57, 0x39, 0x57, 0xBF, - - 0x57, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x42, 0x73, 0xF8, 0xEC, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0xA5, 0x2F, 0x1E, 0xBD, - - 0x43, 0x43, 0x2D, 0xDF, - 0x4B, 0x4B, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x26, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x53, 0x53, 0x2D, 0xDF, - 0x00, 0x80, 0x00, 0xE8, - - 0xB8, 0x38, 0x33, 0xBF, - 0x00, 0xE0, - 0x59, 0xE3, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x3F, 0x4B, 0xA0, 0xE8, - - 0x2D, 0x73, - 0x30, 0x76, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x53, 0xA0, 0xE8, - - 0x48, 0x70, 0xF8, 0xEC, - 0x2B, 0x48, 0x3C, 0xE9, - - 0x1F, 0x27, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x18, 0x3A, 0x41, 0xE9, - 0x1D, 0x32, 0x41, 0xE9, - - 0x2A, 0x40, 0x20, 0xE9, - 0x56, 0x3D, 0x56, 0xDF, - - 0x46, 0x37, 0x46, 0xDF, - 0x4E, 0x3F, 0x4E, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x4F, 0x3F, 0x4F, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3D, 0x57, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x27, 0xCF, 0x74, 0xC2, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x4C, 0xB0, - 0x02, 0x44, 0x54, 0xB0, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x34, 0x37, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x38, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB2, - 0x1A, 0x44, 0x54, 0xB2, - - 0x29, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x27, 0xCF, 0x75, 0xC0, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x3D, 0xCF, 0x75, 0xC2, - 0x37, 0xCF, 0x75, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA6, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA3, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB4, - 0x1A, 0x44, 0x54, 0xB4, - - 0x0A, 0x45, 0x4D, 0xB0, - 0x02, 0x45, 0x55, 0xB0, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA0, 0x37, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x2A, 0x45, 0x4D, 0xB2, - 0x1A, 0x45, 0x55, 0xB2, - - 0x0A, 0x45, 0x4D, 0xB4, - 0x02, 0x45, 0x55, 0xB4, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x0A, 0x20, - 0x02, 0x20, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x4E, 0xBF, - 0x1A, 0x46, 0x56, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0xA7, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0xA8, 0x38, 0x4F, 0xE9, - - 0x0A, 0x47, 0x4F, 0xBF, - 0x02, 0x47, 0x57, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA4, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA5, 0x39, 0x4F, 0xE9, - - 0x2A, 0x43, 0x4B, 0xBF, - 0x1A, 0x43, 0x53, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0xA1, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0xA2, 0x38, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x37, 0x48, 0x50, 0xBD, - 0x8A, 0x36, 0x20, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8B, 0x3E, 0x20, 0xE9, - - 0x82, 0x30, 0x57, 0xE9, - 0x87, 0x77, 0x57, 0xE9, - - 0x83, 0x38, 0x57, 0xE9, - 0x35, 0x49, 0x51, 0xBD, - - 0x84, 0x31, 0x5E, 0xE9, - 0x30, 0x1F, 0x5F, 0xE9, - - 0x85, 0x39, 0x5E, 0xE9, - 0x57, 0x25, 0x20, 0xE9, - - 0x2B, 0x48, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0xA2, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xCA, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x90, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_tgzsa[] = { - - 0x00, 0x88, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x22, 0x40, 0x48, 0xBF, - 0x2A, 0x40, 0x50, 0xBF, - - 0x32, 0x41, 0x49, 0xBF, - 0x3A, 0x41, 0x51, 0xBF, - - 0xC3, 0x6B, - 0xCB, 0x6B, - 0x00, 0x88, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x4B, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x29, 0x9F, - 0x00, 0xE0, - 0x49, 0x04, - - 0x90, 0xE2, - 0x51, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x49, 0x41, 0xC0, 0xEC, - 0x39, 0x57, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x53, 0xA0, 0xE8, - - 0x51, 0x41, 0xC0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x6A, 0x80, 0x15, 0xEA, - 0x08, 0x04, - 0x10, 0x04, - - 0x51, 0x49, 0xC0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x4A, 0xBF, - 0x27, 0x4A, 0xA0, 0xE8, - - 0x1A, 0x42, 0x52, 0xBF, - 0x1E, 0x49, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x26, 0x51, 0x60, 0xEA, - - 0x32, 0x40, 0x48, 0xBD, - 0x22, 0x40, 0x50, 0xBD, - - 0x12, 0x41, 0x49, 0xBD, - 0x3A, 0x41, 0x51, 0xBD, - - 0xBF, 0x2F, 0x26, 0xBD, - 0x00, 0xE0, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x46, 0x31, 0x46, 0xBF, - 0x4E, 0x31, 0x4E, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x56, 0x31, 0x56, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x4F, 0x39, 0x4F, 0xBF, - 0x57, 0x39, 0x57, 0xBF, - - 0x5C, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x42, 0x73, 0xF8, 0xEC, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0xA5, 0x2F, 0x1E, 0xBD, - - 0x43, 0x43, 0x2D, 0xDF, - 0x4B, 0x4B, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x26, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x53, 0x53, 0x2D, 0xDF, - 0x00, 0x80, 0x00, 0xE8, - - 0xB8, 0x38, 0x33, 0xBF, - 0x00, 0xE0, - 0x59, 0xE3, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x3F, 0x4B, 0xA0, 0xE8, - - 0x2D, 0x73, - 0x30, 0x76, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x53, 0xA0, 0xE8, - - 0x48, 0x70, 0xF8, 0xEC, - 0x2B, 0x48, 0x3C, 0xE9, - - 0x1F, 0x27, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x18, 0x3A, 0x41, 0xE9, - 0x1D, 0x32, 0x41, 0xE9, - - 0x2A, 0x40, 0x20, 0xE9, - 0x56, 0x3D, 0x56, 0xDF, - - 0x46, 0x37, 0x46, 0xDF, - 0x4E, 0x3F, 0x4E, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x4F, 0x3F, 0x4F, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3D, 0x57, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x27, 0xCF, 0x74, 0xC2, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x4C, 0xB0, - 0x02, 0x44, 0x54, 0xB0, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x34, 0x37, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x38, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB2, - 0x1A, 0x44, 0x54, 0xB2, - - 0x2E, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x27, 0xCF, 0x75, 0xC0, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x3D, 0xCF, 0x75, 0xC2, - 0x37, 0xCF, 0x75, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA6, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA3, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB4, - 0x1A, 0x44, 0x54, 0xB4, - - 0x0A, 0x45, 0x4D, 0xB0, - 0x02, 0x45, 0x55, 0xB0, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA0, 0x37, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x45, 0x4D, 0xB2, - 0x1A, 0x45, 0x55, 0xB2, - - 0x0A, 0x45, 0x4D, 0xB4, - 0x02, 0x45, 0x55, 0xB4, - - 0x27, 0xCF, 0x74, 0xC6, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA7, 0x30, 0x4F, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9C, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA8, 0x38, 0x4F, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB6, - 0x1A, 0x44, 0x54, 0xB6, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x4E, 0xBF, - 0x1A, 0x46, 0x56, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA4, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA5, 0x39, 0x4F, 0xE9, - - 0x0A, 0x47, 0x4F, 0xBF, - 0x02, 0x47, 0x57, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA1, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA2, 0x38, 0x4F, 0xE9, - - 0x2A, 0x43, 0x4B, 0xBF, - 0x1A, 0x43, 0x53, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x9D, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x9E, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x37, 0x48, 0x50, 0xBD, - 0x8A, 0x36, 0x20, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8B, 0x3E, 0x20, 0xE9, - - 0x82, 0x30, 0x57, 0xE9, - 0x87, 0x77, 0x57, 0xE9, - - 0x83, 0x38, 0x57, 0xE9, - 0x35, 0x49, 0x51, 0xBD, - - 0x84, 0x31, 0x5E, 0xE9, - 0x30, 0x1F, 0x5F, 0xE9, - - 0x85, 0x39, 0x5E, 0xE9, - 0x57, 0x25, 0x20, 0xE9, - - 0x2B, 0x48, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0x9D, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xC5, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x8B, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_tgzsaf[] = { - - 0x00, 0x88, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x22, 0x40, 0x48, 0xBF, - 0x2A, 0x40, 0x50, 0xBF, - - 0x32, 0x41, 0x49, 0xBF, - 0x3A, 0x41, 0x51, 0xBF, - - 0xC3, 0x6B, - 0xCB, 0x6B, - 0x00, 0x88, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x4B, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x29, 0x9F, - 0x00, 0xE0, - 0x49, 0x04, - - 0x90, 0xE2, - 0x51, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x49, 0x41, 0xC0, 0xEC, - 0x39, 0x57, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x53, 0xA0, 0xE8, - - 0x51, 0x41, 0xC0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x6E, 0x80, 0x15, 0xEA, - 0x08, 0x04, - 0x10, 0x04, - - 0x51, 0x49, 0xC0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x4A, 0xBF, - 0x27, 0x4A, 0xA0, 0xE8, - - 0x1A, 0x42, 0x52, 0xBF, - 0x1E, 0x49, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x26, 0x51, 0x60, 0xEA, - - 0x32, 0x40, 0x48, 0xBD, - 0x22, 0x40, 0x50, 0xBD, - - 0x12, 0x41, 0x49, 0xBD, - 0x3A, 0x41, 0x51, 0xBD, - - 0xBF, 0x2F, 0x26, 0xBD, - 0x00, 0xE0, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x46, 0x31, 0x46, 0xBF, - 0x4E, 0x31, 0x4E, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x56, 0x31, 0x56, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x4F, 0x39, 0x4F, 0xBF, - 0x57, 0x39, 0x57, 0xBF, - - 0x60, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x42, 0x73, 0xF8, 0xEC, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0xA5, 0x2F, 0x1E, 0xBD, - - 0x43, 0x43, 0x2D, 0xDF, - 0x4B, 0x4B, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x26, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x53, 0x53, 0x2D, 0xDF, - 0x00, 0x80, 0x00, 0xE8, - - 0xB8, 0x38, 0x33, 0xBF, - 0x00, 0xE0, - 0x59, 0xE3, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x3F, 0x4B, 0xA0, 0xE8, - - 0x2D, 0x73, - 0x30, 0x76, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x53, 0xA0, 0xE8, - - 0x48, 0x70, 0xF8, 0xEC, - 0x2B, 0x48, 0x3C, 0xE9, - - 0x1F, 0x27, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x18, 0x3A, 0x41, 0xE9, - 0x1D, 0x32, 0x41, 0xE9, - - 0x2A, 0x40, 0x20, 0xE9, - 0x56, 0x3D, 0x56, 0xDF, - - 0x46, 0x37, 0x46, 0xDF, - 0x4E, 0x3F, 0x4E, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x4F, 0x3F, 0x4F, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3D, 0x57, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x27, 0xCF, 0x74, 0xC2, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x4C, 0xB0, - 0x02, 0x44, 0x54, 0xB0, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x34, 0x37, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x38, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB2, - 0x1A, 0x44, 0x54, 0xB2, - - 0x32, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x27, 0xCF, 0x75, 0xC0, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x3D, 0xCF, 0x75, 0xC2, - 0x37, 0xCF, 0x75, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA6, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA3, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB4, - 0x1A, 0x44, 0x54, 0xB4, - - 0x0A, 0x45, 0x4D, 0xB0, - 0x02, 0x45, 0x55, 0xB0, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA0, 0x37, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x45, 0x4D, 0xB2, - 0x1A, 0x45, 0x55, 0xB2, - - 0x0A, 0x45, 0x4D, 0xB4, - 0x02, 0x45, 0x55, 0xB4, - - 0x27, 0xCF, 0x74, 0xC6, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA7, 0x30, 0x4F, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9C, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA8, 0x38, 0x4F, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB6, - 0x1A, 0x44, 0x54, 0xB6, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x0A, 0x45, 0x4D, 0xB6, - 0x02, 0x45, 0x55, 0xB6, - - 0x3D, 0xCF, 0x75, 0xC6, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x4E, 0xBF, - 0x1A, 0x46, 0x56, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA4, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA5, 0x39, 0x4F, 0xE9, - - 0x31, 0x3D, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x0A, 0x47, 0x4F, 0xBF, - 0x02, 0x47, 0x57, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0xA1, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0xA2, 0x38, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9D, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x9E, 0x39, 0x4F, 0xE9, - - 0x2A, 0x43, 0x4B, 0xBF, - 0x1A, 0x43, 0x53, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x35, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x39, 0x38, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x37, 0x48, 0x50, 0xBD, - 0x8A, 0x36, 0x20, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8B, 0x3E, 0x20, 0xE9, - - 0x82, 0x30, 0x57, 0xE9, - 0x87, 0x77, 0x57, 0xE9, - - 0x83, 0x38, 0x57, 0xE9, - 0x35, 0x49, 0x51, 0xBD, - - 0x84, 0x31, 0x5E, 0xE9, - 0x30, 0x1F, 0x5F, 0xE9, - - 0x85, 0x39, 0x5E, 0xE9, - 0x57, 0x25, 0x20, 0xE9, - - 0x2B, 0x48, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0x99, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xC1, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x87, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_tgzsf[] = { - - 0x00, 0x88, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x22, 0x40, 0x48, 0xBF, - 0x2A, 0x40, 0x50, 0xBF, - - 0x32, 0x41, 0x49, 0xBF, - 0x3A, 0x41, 0x51, 0xBF, - - 0xC3, 0x6B, - 0xCB, 0x6B, - 0x00, 0x88, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x4B, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x29, 0x9F, - 0x00, 0xE0, - 0x49, 0x04, - - 0x90, 0xE2, - 0x51, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x49, 0x41, 0xC0, 0xEC, - 0x39, 0x57, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x53, 0xA0, 0xE8, - - 0x51, 0x41, 0xC0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x6A, 0x80, 0x15, 0xEA, - 0x08, 0x04, - 0x10, 0x04, - - 0x51, 0x49, 0xC0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x4A, 0xBF, - 0x27, 0x4A, 0xA0, 0xE8, - - 0x1A, 0x42, 0x52, 0xBF, - 0x1E, 0x49, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x26, 0x51, 0x60, 0xEA, - - 0x32, 0x40, 0x48, 0xBD, - 0x22, 0x40, 0x50, 0xBD, - - 0x12, 0x41, 0x49, 0xBD, - 0x3A, 0x41, 0x51, 0xBD, - - 0xBF, 0x2F, 0x26, 0xBD, - 0x00, 0xE0, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x46, 0x31, 0x46, 0xBF, - 0x4E, 0x31, 0x4E, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x56, 0x31, 0x56, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x4F, 0x39, 0x4F, 0xBF, - 0x57, 0x39, 0x57, 0xBF, - - 0x5C, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x42, 0x73, 0xF8, 0xEC, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0xA5, 0x2F, 0x1E, 0xBD, - - 0x43, 0x43, 0x2D, 0xDF, - 0x4B, 0x4B, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x26, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x53, 0x53, 0x2D, 0xDF, - 0x00, 0x80, 0x00, 0xE8, - - 0xB8, 0x38, 0x33, 0xBF, - 0x00, 0xE0, - 0x59, 0xE3, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x3F, 0x4B, 0xA0, 0xE8, - - 0x2D, 0x73, - 0x30, 0x76, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x53, 0xA0, 0xE8, - - 0x48, 0x70, 0xF8, 0xEC, - 0x2B, 0x48, 0x3C, 0xE9, - - 0x1F, 0x27, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x18, 0x3A, 0x41, 0xE9, - 0x1D, 0x32, 0x41, 0xE9, - - 0x2A, 0x40, 0x20, 0xE9, - 0x56, 0x3D, 0x56, 0xDF, - - 0x46, 0x37, 0x46, 0xDF, - 0x4E, 0x3F, 0x4E, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x4F, 0x3F, 0x4F, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3D, 0x57, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x27, 0xCF, 0x74, 0xC2, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x4C, 0xB0, - 0x02, 0x44, 0x54, 0xB0, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x34, 0x37, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x38, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB2, - 0x1A, 0x44, 0x54, 0xB2, - - 0x2E, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x27, 0xCF, 0x75, 0xC0, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x3D, 0xCF, 0x75, 0xC2, - 0x37, 0xCF, 0x75, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA6, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA3, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB4, - 0x1A, 0x44, 0x54, 0xB4, - - 0x0A, 0x45, 0x4D, 0xB0, - 0x02, 0x45, 0x55, 0xB0, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA0, 0x37, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x45, 0x4D, 0xB2, - 0x1A, 0x45, 0x55, 0xB2, - - 0x0A, 0x45, 0x4D, 0xB4, - 0x02, 0x45, 0x55, 0xB4, - - 0x27, 0xCF, 0x75, 0xC6, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA7, 0x30, 0x4F, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x31, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA8, 0x38, 0x4F, 0xE9, - - 0x2A, 0x45, 0x4D, 0xB6, - 0x1A, 0x45, 0x55, 0xB6, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x4E, 0xBF, - 0x1A, 0x46, 0x56, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA4, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA5, 0x39, 0x4F, 0xE9, - - 0x0A, 0x47, 0x4F, 0xBF, - 0x02, 0x47, 0x57, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA1, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA2, 0x38, 0x4F, 0xE9, - - 0x2A, 0x43, 0x4B, 0xBF, - 0x1A, 0x43, 0x53, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x35, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x39, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x37, 0x48, 0x50, 0xBD, - 0x8A, 0x36, 0x20, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8B, 0x3E, 0x20, 0xE9, - - 0x82, 0x30, 0x57, 0xE9, - 0x87, 0x77, 0x57, 0xE9, - - 0x83, 0x38, 0x57, 0xE9, - 0x35, 0x49, 0x51, 0xBD, - - 0x84, 0x31, 0x5E, 0xE9, - 0x30, 0x1F, 0x5F, 0xE9, - - 0x85, 0x39, 0x5E, 0xE9, - 0x57, 0x25, 0x20, 0xE9, - - 0x2B, 0x48, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0x9D, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xC5, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x8B, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; diff --git a/drivers/gpu/drm/mga/mga_warp.c b/drivers/gpu/drm/mga/mga_warp.c index 651b93c8ab5d..9aad4847afdf 100644 --- a/drivers/gpu/drm/mga/mga_warp.c +++ b/drivers/gpu/drm/mga/mga_warp.c @@ -27,132 +27,108 @@ * Gareth Hughes */ +#include +#include +#include + #include "drmP.h" #include "drm.h" #include "mga_drm.h" #include "mga_drv.h" -#include "mga_ucode.h" + +#define FIRMWARE_G200 "matrox/g200_warp.fw" +#define FIRMWARE_G400 "matrox/g400_warp.fw" + +MODULE_FIRMWARE(FIRMWARE_G200); +MODULE_FIRMWARE(FIRMWARE_G400); #define MGA_WARP_CODE_ALIGN 256 /* in bytes */ -#define WARP_UCODE_SIZE( which ) \ - ((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN) - -#define WARP_UCODE_INSTALL( which, where ) \ -do { \ - DRM_DEBUG( " pcbase = 0x%08lx vcbase = %p\n", pcbase, vcbase );\ - dev_priv->warp_pipe_phys[where] = pcbase; \ - memcpy( vcbase, which, sizeof(which) ); \ - pcbase += WARP_UCODE_SIZE( which ); \ - vcbase += WARP_UCODE_SIZE( which ); \ -} while (0) - -static const unsigned int mga_warp_g400_microcode_size = - (WARP_UCODE_SIZE(warp_g400_tgz) + - WARP_UCODE_SIZE(warp_g400_tgza) + - WARP_UCODE_SIZE(warp_g400_tgzaf) + - WARP_UCODE_SIZE(warp_g400_tgzf) + - WARP_UCODE_SIZE(warp_g400_tgzs) + - WARP_UCODE_SIZE(warp_g400_tgzsa) + - WARP_UCODE_SIZE(warp_g400_tgzsaf) + - WARP_UCODE_SIZE(warp_g400_tgzsf) + - WARP_UCODE_SIZE(warp_g400_t2gz) + - WARP_UCODE_SIZE(warp_g400_t2gza) + - WARP_UCODE_SIZE(warp_g400_t2gzaf) + - WARP_UCODE_SIZE(warp_g400_t2gzf) + - WARP_UCODE_SIZE(warp_g400_t2gzs) + - WARP_UCODE_SIZE(warp_g400_t2gzsa) + - WARP_UCODE_SIZE(warp_g400_t2gzsaf) + WARP_UCODE_SIZE(warp_g400_t2gzsf)); - -static const unsigned int mga_warp_g200_microcode_size = - (WARP_UCODE_SIZE(warp_g200_tgz) + - WARP_UCODE_SIZE(warp_g200_tgza) + - WARP_UCODE_SIZE(warp_g200_tgzaf) + - WARP_UCODE_SIZE(warp_g200_tgzf) + - WARP_UCODE_SIZE(warp_g200_tgzs) + - WARP_UCODE_SIZE(warp_g200_tgzsa) + - WARP_UCODE_SIZE(warp_g200_tgzsaf) + WARP_UCODE_SIZE(warp_g200_tgzsf)); - -unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv) +#define WARP_UCODE_SIZE(size) ALIGN(size, MGA_WARP_CODE_ALIGN) + +int mga_warp_install_microcode(drm_mga_private_t * dev_priv) { + unsigned char *vcbase = dev_priv->warp->handle; + unsigned long pcbase = dev_priv->warp->offset; + const char *firmware_name; + struct platform_device *pdev; + const struct firmware *fw = NULL; + const struct ihex_binrec *rec; + unsigned int size; + int n_pipes, where; + int rc = 0; + switch (dev_priv->chipset) { case MGA_CARD_TYPE_G400: case MGA_CARD_TYPE_G550: - return PAGE_ALIGN(mga_warp_g400_microcode_size); + firmware_name = FIRMWARE_G400; + n_pipes = MGA_MAX_G400_PIPES; + break; case MGA_CARD_TYPE_G200: - return PAGE_ALIGN(mga_warp_g200_microcode_size); + firmware_name = FIRMWARE_G200; + n_pipes = MGA_MAX_G200_PIPES; + break; default: - return 0; + return -EINVAL; } -} - -static int mga_warp_install_g400_microcode(drm_mga_private_t * dev_priv) -{ - unsigned char *vcbase = dev_priv->warp->handle; - unsigned long pcbase = dev_priv->warp->offset; - - memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); - - WARP_UCODE_INSTALL(warp_g400_tgz, MGA_WARP_TGZ); - WARP_UCODE_INSTALL(warp_g400_tgzf, MGA_WARP_TGZF); - WARP_UCODE_INSTALL(warp_g400_tgza, MGA_WARP_TGZA); - WARP_UCODE_INSTALL(warp_g400_tgzaf, MGA_WARP_TGZAF); - WARP_UCODE_INSTALL(warp_g400_tgzs, MGA_WARP_TGZS); - WARP_UCODE_INSTALL(warp_g400_tgzsf, MGA_WARP_TGZSF); - WARP_UCODE_INSTALL(warp_g400_tgzsa, MGA_WARP_TGZSA); - WARP_UCODE_INSTALL(warp_g400_tgzsaf, MGA_WARP_TGZSAF); - - WARP_UCODE_INSTALL(warp_g400_t2gz, MGA_WARP_T2GZ); - WARP_UCODE_INSTALL(warp_g400_t2gzf, MGA_WARP_T2GZF); - WARP_UCODE_INSTALL(warp_g400_t2gza, MGA_WARP_T2GZA); - WARP_UCODE_INSTALL(warp_g400_t2gzaf, MGA_WARP_T2GZAF); - WARP_UCODE_INSTALL(warp_g400_t2gzs, MGA_WARP_T2GZS); - WARP_UCODE_INSTALL(warp_g400_t2gzsf, MGA_WARP_T2GZSF); - WARP_UCODE_INSTALL(warp_g400_t2gzsa, MGA_WARP_T2GZSA); - WARP_UCODE_INSTALL(warp_g400_t2gzsaf, MGA_WARP_T2GZSAF); - - return 0; -} - -static int mga_warp_install_g200_microcode(drm_mga_private_t * dev_priv) -{ - unsigned char *vcbase = dev_priv->warp->handle; - unsigned long pcbase = dev_priv->warp->offset; - - memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); - - WARP_UCODE_INSTALL(warp_g200_tgz, MGA_WARP_TGZ); - WARP_UCODE_INSTALL(warp_g200_tgzf, MGA_WARP_TGZF); - WARP_UCODE_INSTALL(warp_g200_tgza, MGA_WARP_TGZA); - WARP_UCODE_INSTALL(warp_g200_tgzaf, MGA_WARP_TGZAF); - WARP_UCODE_INSTALL(warp_g200_tgzs, MGA_WARP_TGZS); - WARP_UCODE_INSTALL(warp_g200_tgzsf, MGA_WARP_TGZSF); - WARP_UCODE_INSTALL(warp_g200_tgzsa, MGA_WARP_TGZSA); - WARP_UCODE_INSTALL(warp_g200_tgzsaf, MGA_WARP_TGZSAF); - return 0; -} + pdev = platform_device_register_simple("mga_warp", 0, NULL, 0); + if (IS_ERR(pdev)) { + DRM_ERROR("mga: Failed to register microcode\n"); + return PTR_ERR(pdev); + } + rc = request_ihex_firmware(&fw, firmware_name, &pdev->dev); + platform_device_unregister(pdev); + if (rc) { + DRM_ERROR("mga: Failed to load microcode \"%s\"\n", + firmware_name); + return rc; + } -int mga_warp_install_microcode(drm_mga_private_t * dev_priv) -{ - const unsigned int size = mga_warp_microcode_size(dev_priv); + size = 0; + where = 0; + for (rec = (const struct ihex_binrec *)fw->data; + rec; + rec = ihex_next_binrec(rec)) { + size += WARP_UCODE_SIZE(be16_to_cpu(rec->len)); + where++; + } + if (where != n_pipes) { + DRM_ERROR("mga: Invalid microcode \"%s\"\n", firmware_name); + rc = -EINVAL; + goto out; + } + size = PAGE_ALIGN(size); DRM_DEBUG("MGA ucode size = %d bytes\n", size); if (size > dev_priv->warp->size) { DRM_ERROR("microcode too large! (%u > %lu)\n", size, dev_priv->warp->size); - return -ENOMEM; + rc = -ENOMEM; + goto out; } - switch (dev_priv->chipset) { - case MGA_CARD_TYPE_G400: - case MGA_CARD_TYPE_G550: - return mga_warp_install_g400_microcode(dev_priv); - case MGA_CARD_TYPE_G200: - return mga_warp_install_g200_microcode(dev_priv); - default: - return -EINVAL; + memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); + + where = 0; + for (rec = (const struct ihex_binrec *)fw->data; + rec; + rec = ihex_next_binrec(rec)) { + unsigned int src_size, dst_size; + + DRM_DEBUG(" pcbase = 0x%08lx vcbase = %p\n", pcbase, vcbase); + dev_priv->warp_pipe_phys[where] = pcbase; + src_size = be16_to_cpu(rec->len); + dst_size = WARP_UCODE_SIZE(src_size); + memcpy(vcbase, rec->data, src_size); + pcbase += dst_size; + vcbase += dst_size; + where++; } + +out: + release_firmware(fw); + return rc; } #define WMISC_EXPECTED (MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE) diff --git a/drivers/gpu/drm/r128/r128_cce.c b/drivers/gpu/drm/r128/r128_cce.c index c75fd3564040..4c39a407aa4a 100644 --- a/drivers/gpu/drm/r128/r128_cce.c +++ b/drivers/gpu/drm/r128/r128_cce.c @@ -29,6 +29,9 @@ * Gareth Hughes */ +#include +#include + #include "drmP.h" #include "drm.h" #include "r128_drm.h" @@ -36,50 +39,9 @@ #define R128_FIFO_DEBUG 0 -/* CCE microcode (from ATI) */ -static u32 r128_cce_microcode[] = { - 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0, - 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0, - 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1, - 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11, - 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28, - 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9, - 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656, - 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1, - 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071, - 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2, - 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1, - 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1, - 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1, - 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2, - 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1, - 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82, - 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729, - 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008, - 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0, - 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1, - 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1, - 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0, - 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370, - 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1, - 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793, - 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1, - 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1, - 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1, - 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1, - 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894, - 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14, - 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1, - 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1, - 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1, - 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; +#define FIRMWARE_NAME "r128/r128_cce.bin" + +MODULE_FIRMWARE(FIRMWARE_NAME); static int R128_READ_PLL(struct drm_device * dev, int addr) { @@ -176,20 +138,50 @@ static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv) */ /* Load the microcode for the CCE */ -static void r128_cce_load_microcode(drm_r128_private_t * dev_priv) +static int r128_cce_load_microcode(drm_r128_private_t *dev_priv) { - int i; + struct platform_device *pdev; + const struct firmware *fw; + const __be32 *fw_data; + int rc, i; DRM_DEBUG("\n"); + pdev = platform_device_register_simple("r128_cce", 0, NULL, 0); + if (IS_ERR(pdev)) { + printk(KERN_ERR "r128_cce: Failed to register firmware\n"); + return PTR_ERR(pdev); + } + rc = request_firmware(&fw, FIRMWARE_NAME, &pdev->dev); + platform_device_unregister(pdev); + if (rc) { + printk(KERN_ERR "r128_cce: Failed to load firmware \"%s\"\n", + FIRMWARE_NAME); + return rc; + } + + if (fw->size != 256 * 8) { + printk(KERN_ERR + "r128_cce: Bogus length %zu in firmware \"%s\"\n", + fw->size, FIRMWARE_NAME); + rc = -EINVAL; + goto out_release; + } + r128_do_wait_for_idle(dev_priv); + fw_data = (const __be32 *)fw->data; R128_WRITE(R128_PM4_MICROCODE_ADDR, 0); for (i = 0; i < 256; i++) { - R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]); + R128_WRITE(R128_PM4_MICROCODE_DATAH, + be32_to_cpup(&fw_data[i * 2])); R128_WRITE(R128_PM4_MICROCODE_DATAL, - r128_cce_microcode[i * 2 + 1]); + be32_to_cpup(&fw_data[i * 2 + 1])); } + +out_release: + release_firmware(fw); + return rc; } /* Flush any pending commands to the CCE. This should only be used just @@ -350,9 +342,15 @@ static void r128_cce_init_ring_buffer(struct drm_device * dev, static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) { drm_r128_private_t *dev_priv; + int rc; DRM_DEBUG("\n"); + if (dev->dev_private) { + DRM_DEBUG("called when already initialized\n"); + return -EINVAL; + } + dev_priv = kzalloc(sizeof(drm_r128_private_t), GFP_KERNEL); if (dev_priv == NULL) return -ENOMEM; @@ -575,13 +573,18 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) #endif r128_cce_init_ring_buffer(dev, dev_priv); - r128_cce_load_microcode(dev_priv); + rc = r128_cce_load_microcode(dev_priv); dev->dev_private = (void *)dev_priv; r128_do_engine_reset(dev); - return 0; + if (rc) { + DRM_ERROR("Failed to load firmware!\n"); + r128_do_cleanup_cce(dev); + } + + return rc; } int r128_do_cleanup_cce(struct drm_device * dev) @@ -649,6 +652,8 @@ int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_pri LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) { DRM_DEBUG("while CCE running\n"); return 0; @@ -671,6 +676,8 @@ int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + /* Flush any pending CCE commands. This ensures any outstanding * commands are exectuted by the engine before we turn it off. */ @@ -708,10 +715,7 @@ int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_pri LOCK_TEST_WITH_RETURN(dev, file_priv); - if (!dev_priv) { - DRM_DEBUG("called before init done\n"); - return -EINVAL; - } + DEV_INIT_TEST_WITH_RETURN(dev_priv); r128_do_cce_reset(dev_priv); @@ -728,6 +732,8 @@ int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + if (dev_priv->cce_running) { r128_do_cce_flush(dev_priv); } @@ -741,6 +747,8 @@ int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_ LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev->dev_private); + return r128_do_engine_reset(dev); } diff --git a/drivers/gpu/drm/r128/r128_drv.h b/drivers/gpu/drm/r128/r128_drv.h index 797a26c42dab..3c60829d82e9 100644 --- a/drivers/gpu/drm/r128/r128_drv.h +++ b/drivers/gpu/drm/r128/r128_drv.h @@ -422,6 +422,14 @@ static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv) * Misc helper macros */ +#define DEV_INIT_TEST_WITH_RETURN(_dev_priv) \ +do { \ + if (!_dev_priv) { \ + DRM_ERROR("called with no initialization\n"); \ + return -EINVAL; \ + } \ +} while (0) + #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ do { \ drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \ diff --git a/drivers/gpu/drm/r128/r128_state.c b/drivers/gpu/drm/r128/r128_state.c index 026a48c95c8f..af2665cf4718 100644 --- a/drivers/gpu/drm/r128/r128_state.c +++ b/drivers/gpu/drm/r128/r128_state.c @@ -1244,14 +1244,18 @@ static void r128_cce_dispatch_stipple(struct drm_device * dev, u32 * stipple) static int r128_cce_clear(struct drm_device *dev, void *data, struct drm_file *file_priv) { drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_sarea_t *sarea_priv; drm_r128_clear_t *clear = data; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + sarea_priv = dev_priv->sarea_priv; + if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; @@ -1312,6 +1316,8 @@ static int r128_cce_flip(struct drm_device *dev, void *data, struct drm_file *fi LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + RING_SPACE_TEST_WITH_RETURN(dev_priv); if (!dev_priv->page_flipping) @@ -1331,6 +1337,8 @@ static int r128_cce_swap(struct drm_device *dev, void *data, struct drm_file *fi LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + RING_SPACE_TEST_WITH_RETURN(dev_priv); if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) @@ -1354,10 +1362,7 @@ static int r128_cce_vertex(struct drm_device *dev, void *data, struct drm_file * LOCK_TEST_WITH_RETURN(dev, file_priv); - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } + DEV_INIT_TEST_WITH_RETURN(dev_priv); DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard); @@ -1410,10 +1415,7 @@ static int r128_cce_indices(struct drm_device *dev, void *data, struct drm_file LOCK_TEST_WITH_RETURN(dev, file_priv); - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } + DEV_INIT_TEST_WITH_RETURN(dev_priv); DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, elts->idx, elts->start, elts->end, elts->discard); @@ -1476,6 +1478,8 @@ static int r128_cce_blit(struct drm_device *dev, void *data, struct drm_file *fi LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit->idx); if (blit->idx < 0 || blit->idx >= dma->buf_count) { @@ -1501,6 +1505,8 @@ static int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *f LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + RING_SPACE_TEST_WITH_RETURN(dev_priv); ret = -EINVAL; @@ -1531,6 +1537,8 @@ static int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32))) return -EFAULT; @@ -1555,10 +1563,7 @@ static int r128_cce_indirect(struct drm_device *dev, void *data, struct drm_file LOCK_TEST_WITH_RETURN(dev, file_priv); - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } + DEV_INIT_TEST_WITH_RETURN(dev_priv); DRM_DEBUG("idx=%d s=%d e=%d d=%d\n", indirect->idx, indirect->start, indirect->end, @@ -1620,10 +1625,7 @@ static int r128_getparam(struct drm_device *dev, void *data, struct drm_file *fi drm_r128_getparam_t *param = data; int value; - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } + DEV_INIT_TEST_WITH_RETURN(dev_priv); DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig index 2168d67f09a6..5982321be4d5 100644 --- a/drivers/gpu/drm/radeon/Kconfig +++ b/drivers/gpu/drm/radeon/Kconfig @@ -1,7 +1,6 @@ config DRM_RADEON_KMS bool "Enable modesetting on radeon by default" depends on DRM_RADEON - select DRM_TTM help Choose this option if you want kernel modesetting enabled by default, and you have a new enough userspace to support this. Running old diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 013d38059943..09a28923f46e 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -3,18 +3,53 @@ # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. ccflags-y := -Iinclude/drm + +hostprogs-y := mkregtable + +quiet_cmd_mkregtable = MKREGTABLE $@ + cmd_mkregtable = $(obj)/mkregtable $< > $@ + +$(obj)/rn50_reg_safe.h: $(src)/reg_srcs/rn50 $(obj)/mkregtable + $(call if_changed,mkregtable) + +$(obj)/r100_reg_safe.h: $(src)/reg_srcs/r100 $(obj)/mkregtable + $(call if_changed,mkregtable) + +$(obj)/r200_reg_safe.h: $(src)/reg_srcs/r200 $(obj)/mkregtable + $(call if_changed,mkregtable) + +$(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable + $(call if_changed,mkregtable) + +$(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable + $(call if_changed,mkregtable) + +$(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable + $(call if_changed,mkregtable) + +$(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h + +$(obj)/r200.o: $(obj)/r200_reg_safe.h + +$(obj)/rv515.o: $(obj)/rv515_reg_safe.h + +$(obj)/r300.o: $(obj)/r300_reg_safe.h + +$(obj)/rs600.o: $(obj)/rs600_reg_safe.h + radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \ radeon_irq.o r300_cmdbuf.o r600_cp.o - -radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \ +# add KMS driver +radeon-y += radeon_device.o radeon_kms.o \ radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \ atom.o radeon_fence.o radeon_ttm.o radeon_object.o radeon_gart.o \ radeon_legacy_crtc.o radeon_legacy_encoders.o radeon_connectors.o \ radeon_encoders.o radeon_display.o radeon_cursor.o radeon_i2c.o \ radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \ radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ - rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o \ - radeon_test.o + rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \ + r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ + r600_blit_kms.o radeon-$(CONFIG_COMPAT) += radeon_ioc32.o diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h index cf67928abbc8..5d402086bc47 100644 --- a/drivers/gpu/drm/radeon/atombios.h +++ b/drivers/gpu/drm/radeon/atombios.h @@ -2374,6 +2374,17 @@ typedef struct _ATOM_ANALOG_TV_INFO { ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; } ATOM_ANALOG_TV_INFO; +#define MAX_SUPPORTED_TV_TIMING_V1_2 3 + +typedef struct _ATOM_ANALOG_TV_INFO_V1_2 { + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucTV_SupportedStandard; + UCHAR ucTV_BootUpDefaultStandard; + UCHAR ucExt_TV_ASIC_ID; + UCHAR ucExt_TV_ASIC_SlaveAddr; + ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; +} ATOM_ANALOG_TV_INFO_V1_2; + /**************************************************************************/ /* VRAM usage and their defintions */ diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 74d034f77c6b..6a015929deee 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -31,6 +31,10 @@ #include "atom.h" #include "atom-bits.h" +/* evil but including atombios.h is much worse */ +bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, + SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, + int32_t *pixel_clock); static void atombios_overscan_setup(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) @@ -89,17 +93,32 @@ static void atombios_scaler_setup(struct drm_crtc *crtc) struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); ENABLE_SCALER_PS_ALLOCATION args; int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); + /* fixme - fill in enc_priv for atom dac */ enum radeon_tv_std tv_std = TV_STD_NTSC; + bool is_tv = false, is_cv = false; + struct drm_encoder *encoder; if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) return; + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + /* find tv std */ + if (encoder->crtc == crtc) { + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { + struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; + tv_std = tv_dac->tv_std; + is_tv = true; + } + } + } + memset(&args, 0, sizeof(args)); args.ucScaler = radeon_crtc->crtc_id; - if (radeon_crtc->devices & (ATOM_DEVICE_TV_SUPPORT)) { + if (is_tv) { switch (tv_std) { case TV_STD_NTSC: default: @@ -128,7 +147,7 @@ static void atombios_scaler_setup(struct drm_crtc *crtc) break; } args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; - } else if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT)) { + } else if (is_cv) { args.ucTVStandard = ATOM_TV_CV; args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; } else { @@ -151,9 +170,9 @@ static void atombios_scaler_setup(struct drm_crtc *crtc) } } atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); - if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT) - && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_RV570) { - atom_rv515_force_tv_scaler(rdev); + if ((is_tv || is_cv) + && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { + atom_rv515_force_tv_scaler(rdev, radeon_crtc); } } @@ -370,6 +389,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) pll_flags |= RADEON_PLL_USE_REF_DIV; } radeon_encoder = to_radeon_encoder(encoder); + break; } } @@ -468,6 +488,11 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, } switch (crtc->fb->bits_per_pixel) { + case 8: + fb_format = + AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | + AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; + break; case 15: fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | @@ -551,42 +576,68 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, struct radeon_device *rdev = dev->dev_private; struct drm_encoder *encoder; SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing; + int need_tv_timings = 0; + bool ret; /* TODO color tiling */ memset(&crtc_timing, 0, sizeof(crtc_timing)); - /* TODO tv */ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - + /* find tv std */ + if (encoder->crtc == crtc) { + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + + if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { + struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; + if (tv_dac) { + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M) + need_tv_timings = 1; + else + need_tv_timings = 2; + break; + } + } + } } crtc_timing.ucCRTC = radeon_crtc->crtc_id; - crtc_timing.usH_Total = adjusted_mode->crtc_htotal; - crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay; - crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start; - crtc_timing.usH_SyncWidth = - adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; + if (need_tv_timings) { + ret = radeon_atom_get_tv_timings(rdev, need_tv_timings - 1, + &crtc_timing, &adjusted_mode->clock); + if (ret == false) + need_tv_timings = 0; + } - crtc_timing.usV_Total = adjusted_mode->crtc_vtotal; - crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay; - crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start; - crtc_timing.usV_SyncWidth = - adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; + if (!need_tv_timings) { + crtc_timing.usH_Total = adjusted_mode->crtc_htotal; + crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay; + crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start; + crtc_timing.usH_SyncWidth = + adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; - if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) - crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY; + crtc_timing.usV_Total = adjusted_mode->crtc_vtotal; + crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay; + crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start; + crtc_timing.usV_SyncWidth = + adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; - if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) - crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY; + if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) + crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY; - if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) - crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC; + if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) + crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY; - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) - crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE; + if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) + crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC; - if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) - crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE; + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) + crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE; + + if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) + crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE; + } atombios_crtc_set_pll(crtc, adjusted_mode); atombios_crtc_set_timing(crtc, &crtc_timing); diff --git a/drivers/gpu/drm/radeon/avivod.h b/drivers/gpu/drm/radeon/avivod.h new file mode 100644 index 000000000000..e2b92c445bab --- /dev/null +++ b/drivers/gpu/drm/radeon/avivod.h @@ -0,0 +1,69 @@ +/* + * Copyright 2009 Advanced Micro Devices, Inc. + * Copyright 2009 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef AVIVOD_H +#define AVIVOD_H + + +#define D1CRTC_CONTROL 0x6080 +#define CRTC_EN (1 << 0) +#define D1CRTC_UPDATE_LOCK 0x60E8 +#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 +#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 + +#define D2CRTC_CONTROL 0x6880 +#define D2CRTC_UPDATE_LOCK 0x68E8 +#define D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 +#define D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 + +#define D1VGA_CONTROL 0x0330 +#define DVGA_CONTROL_MODE_ENABLE (1 << 0) +#define DVGA_CONTROL_TIMING_SELECT (1 << 8) +#define DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9) +#define DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10) +#define DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16) +#define DVGA_CONTROL_ROTATE (1 << 24) +#define D2VGA_CONTROL 0x0338 + +#define VGA_HDP_CONTROL 0x328 +#define VGA_MEM_PAGE_SELECT_EN (1 << 0) +#define VGA_MEMORY_DISABLE (1 << 4) +#define VGA_RBBM_LOCK_DISABLE (1 << 8) +#define VGA_SOFT_RESET (1 << 16) +#define VGA_MEMORY_BASE_ADDRESS 0x0310 +#define VGA_RENDER_CONTROL 0x0300 +#define VGA_VSTATUS_CNTL_MASK 0x00030000 + +/* AVIVO disable VGA rendering */ +static inline void radeon_avivo_vga_render_disable(struct radeon_device *rdev) +{ + u32 vga_render; + vga_render = RREG32(VGA_RENDER_CONTROL); + vga_render &= ~VGA_VSTATUS_CNTL_MASK; + WREG32(VGA_RENDER_CONTROL, vga_render); +} + +#endif diff --git a/drivers/gpu/drm/radeon/mkregtable.c b/drivers/gpu/drm/radeon/mkregtable.c new file mode 100644 index 000000000000..fb211e585dea --- /dev/null +++ b/drivers/gpu/drm/radeon/mkregtable.c @@ -0,0 +1,720 @@ +/* utility to create the register check tables + * this includes inlined list.h safe for userspace. + * + * Copyright 2009 Jerome Glisse + * Copyright 2009 Red Hat Inc. + * + * Authors: + * Jerome Glisse + * Dave Airlie + */ + +#include +#include +#include +#include +#include +#include + +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) +/** + * container_of - cast a member of a structure out to the containing structure + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const typeof(((type *)0)->member)*__mptr = (ptr); \ + (type *)((char *)__mptr - offsetof(type, member)); }) + +/* + * Simple doubly linked list implementation. + * + * Some of the internal functions ("__xxx") are useful when + * manipulating whole lists rather than single entries, as + * sometimes we already know the next/prev entries and we can + * generate better code by using them directly rather than + * using the generic single-entry routines. + */ + +struct list_head { + struct list_head *next, *prev; +}; + +#define LIST_HEAD_INIT(name) { &(name), &(name) } + +#define LIST_HEAD(name) \ + struct list_head name = LIST_HEAD_INIT(name) + +static inline void INIT_LIST_HEAD(struct list_head *list) +{ + list->next = list; + list->prev = list; +} + +/* + * Insert a new entry between two known consecutive entries. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +#ifndef CONFIG_DEBUG_LIST +static inline void __list_add(struct list_head *new, + struct list_head *prev, struct list_head *next) +{ + next->prev = new; + new->next = next; + new->prev = prev; + prev->next = new; +} +#else +extern void __list_add(struct list_head *new, + struct list_head *prev, struct list_head *next); +#endif + +/** + * list_add - add a new entry + * @new: new entry to be added + * @head: list head to add it after + * + * Insert a new entry after the specified head. + * This is good for implementing stacks. + */ +static inline void list_add(struct list_head *new, struct list_head *head) +{ + __list_add(new, head, head->next); +} + +/** + * list_add_tail - add a new entry + * @new: new entry to be added + * @head: list head to add it before + * + * Insert a new entry before the specified head. + * This is useful for implementing queues. + */ +static inline void list_add_tail(struct list_head *new, struct list_head *head) +{ + __list_add(new, head->prev, head); +} + +/* + * Delete a list entry by making the prev/next entries + * point to each other. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_del(struct list_head *prev, struct list_head *next) +{ + next->prev = prev; + prev->next = next; +} + +/** + * list_del - deletes entry from list. + * @entry: the element to delete from the list. + * Note: list_empty() on entry does not return true after this, the entry is + * in an undefined state. + */ +#ifndef CONFIG_DEBUG_LIST +static inline void list_del(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + entry->next = (void *)0xDEADBEEF; + entry->prev = (void *)0xBEEFDEAD; +} +#else +extern void list_del(struct list_head *entry); +#endif + +/** + * list_replace - replace old entry by new one + * @old : the element to be replaced + * @new : the new element to insert + * + * If @old was empty, it will be overwritten. + */ +static inline void list_replace(struct list_head *old, struct list_head *new) +{ + new->next = old->next; + new->next->prev = new; + new->prev = old->prev; + new->prev->next = new; +} + +static inline void list_replace_init(struct list_head *old, + struct list_head *new) +{ + list_replace(old, new); + INIT_LIST_HEAD(old); +} + +/** + * list_del_init - deletes entry from list and reinitialize it. + * @entry: the element to delete from the list. + */ +static inline void list_del_init(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + INIT_LIST_HEAD(entry); +} + +/** + * list_move - delete from one list and add as another's head + * @list: the entry to move + * @head: the head that will precede our entry + */ +static inline void list_move(struct list_head *list, struct list_head *head) +{ + __list_del(list->prev, list->next); + list_add(list, head); +} + +/** + * list_move_tail - delete from one list and add as another's tail + * @list: the entry to move + * @head: the head that will follow our entry + */ +static inline void list_move_tail(struct list_head *list, + struct list_head *head) +{ + __list_del(list->prev, list->next); + list_add_tail(list, head); +} + +/** + * list_is_last - tests whether @list is the last entry in list @head + * @list: the entry to test + * @head: the head of the list + */ +static inline int list_is_last(const struct list_head *list, + const struct list_head *head) +{ + return list->next == head; +} + +/** + * list_empty - tests whether a list is empty + * @head: the list to test. + */ +static inline int list_empty(const struct list_head *head) +{ + return head->next == head; +} + +/** + * list_empty_careful - tests whether a list is empty and not being modified + * @head: the list to test + * + * Description: + * tests whether a list is empty _and_ checks that no other CPU might be + * in the process of modifying either member (next or prev) + * + * NOTE: using list_empty_careful() without synchronization + * can only be safe if the only activity that can happen + * to the list entry is list_del_init(). Eg. it cannot be used + * if another CPU could re-list_add() it. + */ +static inline int list_empty_careful(const struct list_head *head) +{ + struct list_head *next = head->next; + return (next == head) && (next == head->prev); +} + +/** + * list_is_singular - tests whether a list has just one entry. + * @head: the list to test. + */ +static inline int list_is_singular(const struct list_head *head) +{ + return !list_empty(head) && (head->next == head->prev); +} + +static inline void __list_cut_position(struct list_head *list, + struct list_head *head, + struct list_head *entry) +{ + struct list_head *new_first = entry->next; + list->next = head->next; + list->next->prev = list; + list->prev = entry; + entry->next = list; + head->next = new_first; + new_first->prev = head; +} + +/** + * list_cut_position - cut a list into two + * @list: a new list to add all removed entries + * @head: a list with entries + * @entry: an entry within head, could be the head itself + * and if so we won't cut the list + * + * This helper moves the initial part of @head, up to and + * including @entry, from @head to @list. You should + * pass on @entry an element you know is on @head. @list + * should be an empty list or a list you do not care about + * losing its data. + * + */ +static inline void list_cut_position(struct list_head *list, + struct list_head *head, + struct list_head *entry) +{ + if (list_empty(head)) + return; + if (list_is_singular(head) && (head->next != entry && head != entry)) + return; + if (entry == head) + INIT_LIST_HEAD(list); + else + __list_cut_position(list, head, entry); +} + +static inline void __list_splice(const struct list_head *list, + struct list_head *prev, struct list_head *next) +{ + struct list_head *first = list->next; + struct list_head *last = list->prev; + + first->prev = prev; + prev->next = first; + + last->next = next; + next->prev = last; +} + +/** + * list_splice - join two lists, this is designed for stacks + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static inline void list_splice(const struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) + __list_splice(list, head, head->next); +} + +/** + * list_splice_tail - join two lists, each list being a queue + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static inline void list_splice_tail(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) + __list_splice(list, head->prev, head); +} + +/** + * list_splice_init - join two lists and reinitialise the emptied list. + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * The list at @list is reinitialised + */ +static inline void list_splice_init(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) { + __list_splice(list, head, head->next); + INIT_LIST_HEAD(list); + } +} + +/** + * list_splice_tail_init - join two lists and reinitialise the emptied list + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * Each of the lists is a queue. + * The list at @list is reinitialised + */ +static inline void list_splice_tail_init(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) { + __list_splice(list, head->prev, head); + INIT_LIST_HEAD(list); + } +} + +/** + * list_entry - get the struct for this entry + * @ptr: the &struct list_head pointer. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + */ +#define list_entry(ptr, type, member) \ + container_of(ptr, type, member) + +/** + * list_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define list_first_entry(ptr, type, member) \ + list_entry((ptr)->next, type, member) + +/** + * list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + */ +#define list_for_each(pos, head) \ + for (pos = (head)->next; prefetch(pos->next), pos != (head); \ + pos = pos->next) + +/** + * __list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + * + * This variant differs from list_for_each() in that it's the + * simplest possible list iteration code, no prefetching is done. + * Use this for code that knows the list to be very short (empty + * or 1 entry) most of the time. + */ +#define __list_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * list_for_each_prev - iterate over a list backwards + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + */ +#define list_for_each_prev(pos, head) \ + for (pos = (head)->prev; prefetch(pos->prev), pos != (head); \ + pos = pos->prev) + +/** + * list_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the &struct list_head to use as a loop cursor. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +/** + * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry + * @pos: the &struct list_head to use as a loop cursor. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_prev_safe(pos, n, head) \ + for (pos = (head)->prev, n = pos->prev; \ + prefetch(pos->prev), pos != (head); \ + pos = n, n = pos->prev) + +/** + * list_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry(pos, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_reverse - iterate backwards over list of given type. + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_reverse(pos, head, member) \ + for (pos = list_entry((head)->prev, typeof(*pos), member); \ + prefetch(pos->member.prev), &pos->member != (head); \ + pos = list_entry(pos->member.prev, typeof(*pos), member)) + +/** + * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue() + * @pos: the type * to use as a start point + * @head: the head of the list + * @member: the name of the list_struct within the struct. + * + * Prepares a pos entry for use as a start point in list_for_each_entry_continue(). + */ +#define list_prepare_entry(pos, head, member) \ + ((pos) ? : list_entry(head, typeof(*pos), member)) + +/** + * list_for_each_entry_continue - continue iteration over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Continue to iterate over list of given type, continuing after + * the current position. + */ +#define list_for_each_entry_continue(pos, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member); \ + prefetch(pos->member.next), &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_continue_reverse - iterate backwards from the given point + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Start to iterate over list of given type backwards, continuing after + * the current position. + */ +#define list_for_each_entry_continue_reverse(pos, head, member) \ + for (pos = list_entry(pos->member.prev, typeof(*pos), member); \ + prefetch(pos->member.prev), &pos->member != (head); \ + pos = list_entry(pos->member.prev, typeof(*pos), member)) + +/** + * list_for_each_entry_from - iterate over list of given type from the current point + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type, continuing from current position. + */ +#define list_for_each_entry_from(pos, head, member) \ + for (; prefetch(pos->member.next), &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_safe(pos, n, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_continue + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type, continuing after current point, + * safe against removal of list entry. + */ +#define list_for_each_entry_safe_continue(pos, n, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_from + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type from current point, safe against + * removal of list entry. + */ +#define list_for_each_entry_safe_from(pos, n, head, member) \ + for (n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_reverse + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate backwards over list of given type, safe against removal + * of list entry. + */ +#define list_for_each_entry_safe_reverse(pos, n, head, member) \ + for (pos = list_entry((head)->prev, typeof(*pos), member), \ + n = list_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.prev, typeof(*n), member)) + +struct offset { + struct list_head list; + unsigned offset; +}; + +struct table { + struct list_head offsets; + unsigned offset_max; + unsigned nentry; + unsigned *table; + char *gpu_prefix; +}; + +struct offset *offset_new(unsigned o) +{ + struct offset *offset; + + offset = (struct offset *)malloc(sizeof(struct offset)); + if (offset) { + INIT_LIST_HEAD(&offset->list); + offset->offset = o; + } + return offset; +} + +void table_offset_add(struct table *t, struct offset *offset) +{ + list_add_tail(&offset->list, &t->offsets); +} + +void table_init(struct table *t) +{ + INIT_LIST_HEAD(&t->offsets); + t->offset_max = 0; + t->nentry = 0; + t->table = NULL; +} + +void table_print(struct table *t) +{ + unsigned nlloop, i, j, n, c, id; + + nlloop = (t->nentry + 3) / 4; + c = t->nentry; + printf("static const unsigned %s_reg_safe_bm[%d] = {\n", t->gpu_prefix, + t->nentry); + for (i = 0, id = 0; i < nlloop; i++) { + n = 4; + if (n > c) + n = c; + c -= n; + for (j = 0; j < n; j++) { + if (j == 0) + printf("\t"); + else + printf(" "); + printf("0x%08X,", t->table[id++]); + } + printf("\n"); + } + printf("};\n"); +} + +int table_build(struct table *t) +{ + struct offset *offset; + unsigned i, m; + + t->nentry = ((t->offset_max >> 2) + 31) / 32; + t->table = (unsigned *)malloc(sizeof(unsigned) * t->nentry); + if (t->table == NULL) + return -1; + memset(t->table, 0xff, sizeof(unsigned) * t->nentry); + list_for_each_entry(offset, &t->offsets, list) { + i = (offset->offset >> 2) / 32; + m = (offset->offset >> 2) & 31; + m = 1 << m; + t->table[i] ^= m; + } + return 0; +} + +static char gpu_name[10]; +int parser_auth(struct table *t, const char *filename) +{ + FILE *file; + regex_t mask_rex; + regmatch_t match[4]; + char buf[1024]; + size_t end; + int len; + int done = 0; + int r; + unsigned o; + struct offset *offset; + char last_reg_s[10]; + int last_reg; + + if (regcomp + (&mask_rex, "(0x[0-9a-fA-F]*) *([_a-zA-Z0-9]*)", REG_EXTENDED)) { + fprintf(stderr, "Failed to compile regular expression\n"); + return -1; + } + file = fopen(filename, "r"); + if (file == NULL) { + fprintf(stderr, "Failed to open: %s\n", filename); + return -1; + } + fseek(file, 0, SEEK_END); + end = ftell(file); + fseek(file, 0, SEEK_SET); + + /* get header */ + if (fgets(buf, 1024, file) == NULL) + return -1; + + /* first line will contain the last register + * and gpu name */ + sscanf(buf, "%s %s", gpu_name, last_reg_s); + t->gpu_prefix = gpu_name; + last_reg = strtol(last_reg_s, NULL, 16); + + do { + if (fgets(buf, 1024, file) == NULL) + return -1; + len = strlen(buf); + if (ftell(file) == end) + done = 1; + if (len) { + r = regexec(&mask_rex, buf, 4, match, 0); + if (r == REG_NOMATCH) { + } else if (r) { + fprintf(stderr, + "Error matching regular expression %d in %s\n", + r, filename); + return -1; + } else { + buf[match[0].rm_eo] = 0; + buf[match[1].rm_eo] = 0; + buf[match[2].rm_eo] = 0; + o = strtol(&buf[match[1].rm_so], NULL, 16); + offset = offset_new(o); + table_offset_add(t, offset); + if (o > t->offset_max) + t->offset_max = o; + } + } + } while (!done); + fclose(file); + if (t->offset_max < last_reg) + t->offset_max = last_reg; + return table_build(t); +} + +int main(int argc, char *argv[]) +{ + struct table t; + + if (argc != 2) { + fprintf(stderr, "Usage: %s \n", argv[0]); + exit(1); + } + table_init(&t); + if (parser_auth(&t, argv[1])) { + fprintf(stderr, "Failed to parse file %s\n", argv[1]); + return -1; + } + table_print(&t); + return 0; +} diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 68e728e8be4d..be51c5f7d0f6 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -29,15 +29,41 @@ #include "drmP.h" #include "drm.h" #include "radeon_drm.h" -#include "radeon_microcode.h" #include "radeon_reg.h" #include "radeon.h" +#include "r100d.h" + +#include +#include + +#include "r100_reg_safe.h" +#include "rn50_reg_safe.h" + +/* Firmware Names */ +#define FIRMWARE_R100 "radeon/R100_cp.bin" +#define FIRMWARE_R200 "radeon/R200_cp.bin" +#define FIRMWARE_R300 "radeon/R300_cp.bin" +#define FIRMWARE_R420 "radeon/R420_cp.bin" +#define FIRMWARE_RS690 "radeon/RS690_cp.bin" +#define FIRMWARE_RS600 "radeon/RS600_cp.bin" +#define FIRMWARE_R520 "radeon/R520_cp.bin" + +MODULE_FIRMWARE(FIRMWARE_R100); +MODULE_FIRMWARE(FIRMWARE_R200); +MODULE_FIRMWARE(FIRMWARE_R300); +MODULE_FIRMWARE(FIRMWARE_R420); +MODULE_FIRMWARE(FIRMWARE_RS690); +MODULE_FIRMWARE(FIRMWARE_RS600); +MODULE_FIRMWARE(FIRMWARE_R520); + +#include "r100_track.h" /* This files gather functions specifics to: * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 * * Some of these functions might be used by newer ASICs. */ +int r200_init(struct radeon_device *rdev); void r100_hdp_reset(struct radeon_device *rdev); void r100_gpu_init(struct radeon_device *rdev); int r100_gui_wait_for_idle(struct radeon_device *rdev); @@ -58,23 +84,28 @@ void r100_pci_gart_tlb_flush(struct radeon_device *rdev) * could end up in wrong address. */ } -int r100_pci_gart_enable(struct radeon_device *rdev) +int r100_pci_gart_init(struct radeon_device *rdev) { - uint32_t tmp; int r; + if (rdev->gart.table.ram.ptr) { + WARN(1, "R100 PCI GART already initialized.\n"); + return 0; + } /* Initialize common gart structure */ r = radeon_gart_init(rdev); - if (r) { + if (r) return r; - } - if (rdev->gart.table.ram.ptr == NULL) { - rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; - r = radeon_gart_table_ram_alloc(rdev); - if (r) { - return r; - } - } + rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; + rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; + rdev->asic->gart_set_page = &r100_pci_gart_set_page; + return radeon_gart_table_ram_alloc(rdev); +} + +int r100_pci_gart_enable(struct radeon_device *rdev) +{ + uint32_t tmp; + /* discard memory request outside of configured range */ tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; WREG32(RADEON_AIC_CNTL, tmp); @@ -114,13 +145,11 @@ int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) return 0; } -int r100_gart_enable(struct radeon_device *rdev) +void r100_pci_gart_fini(struct radeon_device *rdev) { - if (rdev->flags & RADEON_IS_AGP) { - r100_pci_gart_disable(rdev); - return 0; - } - return r100_pci_gart_enable(rdev); + r100_pci_gart_disable(rdev); + radeon_gart_table_ram_free(rdev); + radeon_gart_fini(rdev); } @@ -247,9 +276,6 @@ int r100_mc_init(struct radeon_device *rdev) void r100_mc_fini(struct radeon_device *rdev) { - r100_pci_gart_disable(rdev); - radeon_gart_table_ram_free(rdev); - radeon_gart_fini(rdev); } @@ -273,6 +299,17 @@ int r100_irq_set(struct radeon_device *rdev) return 0; } +void r100_irq_disable(struct radeon_device *rdev) +{ + u32 tmp; + + WREG32(R_000040_GEN_INT_CNTL, 0); + /* Wait and acknowledge irq */ + mdelay(1); + tmp = RREG32(R_000044_GEN_INT_STATUS); + WREG32(R_000044_GEN_INT_STATUS, tmp); +} + static inline uint32_t r100_irq_ack(struct radeon_device *rdev) { uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); @@ -293,6 +330,9 @@ int r100_irq_process(struct radeon_device *rdev) if (!status) { return IRQ_NONE; } + if (rdev->shutdown) { + return IRQ_NONE; + } while (status) { /* SW interrupt */ if (status & RADEON_SW_INT_TEST) { @@ -367,14 +407,21 @@ int r100_wb_init(struct radeon_device *rdev) return r; } } - WREG32(0x774, rdev->wb.gpu_addr); - WREG32(0x70C, rdev->wb.gpu_addr + 1024); - WREG32(0x770, 0xff); + WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr); + WREG32(R_00070C_CP_RB_RPTR_ADDR, + S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2)); + WREG32(R_000770_SCRATCH_UMSK, 0xff); return 0; } +void r100_wb_disable(struct radeon_device *rdev) +{ + WREG32(R_000770_SCRATCH_UMSK, 0); +} + void r100_wb_fini(struct radeon_device *rdev) { + r100_wb_disable(rdev); if (rdev->wb.wb_obj) { radeon_object_kunmap(rdev->wb.wb_obj); radeon_object_unpin(rdev->wb.wb_obj); @@ -461,6 +508,21 @@ int r100_copy_blit(struct radeon_device *rdev, /* * CP */ +static int r100_cp_wait_for_idle(struct radeon_device *rdev) +{ + unsigned i; + u32 tmp; + + for (i = 0; i < rdev->usec_timeout; i++) { + tmp = RREG32(R_000E40_RBBM_STATUS); + if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { + return 0; + } + udelay(1); + } + return -1; +} + void r100_ring_start(struct radeon_device *rdev) { int r; @@ -478,33 +540,33 @@ void r100_ring_start(struct radeon_device *rdev) radeon_ring_unlock_commit(rdev); } -static void r100_cp_load_microcode(struct radeon_device *rdev) + +/* Load the microcode for the CP */ +static int r100_cp_init_microcode(struct radeon_device *rdev) { - int i; + struct platform_device *pdev; + const char *fw_name = NULL; + int err; - if (r100_gui_wait_for_idle(rdev)) { - printk(KERN_WARNING "Failed to wait GUI idle while " - "programming pipes. Bad things might happen.\n"); - } + DRM_DEBUG("\n"); - WREG32(RADEON_CP_ME_RAM_ADDR, 0); + pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); + err = IS_ERR(pdev); + if (err) { + printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); + return -EINVAL; + } if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || (rdev->family == CHIP_RS200)) { DRM_INFO("Loading R100 Microcode\n"); - for (i = 0; i < 256; i++) { - WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]); - WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]); - } + fw_name = FIRMWARE_R100; } else if ((rdev->family == CHIP_R200) || (rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280) || (rdev->family == CHIP_RS300)) { DRM_INFO("Loading R200 Microcode\n"); - for (i = 0; i < 256; i++) { - WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]); - WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]); - } + fw_name = FIRMWARE_R200; } else if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350) || (rdev->family == CHIP_RV350) || @@ -512,31 +574,19 @@ static void r100_cp_load_microcode(struct radeon_device *rdev) (rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) { DRM_INFO("Loading R300 Microcode\n"); - for (i = 0; i < 256; i++) { - WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]); - WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]); - } + fw_name = FIRMWARE_R300; } else if ((rdev->family == CHIP_R420) || (rdev->family == CHIP_R423) || (rdev->family == CHIP_RV410)) { DRM_INFO("Loading R400 Microcode\n"); - for (i = 0; i < 256; i++) { - WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]); - WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]); - } + fw_name = FIRMWARE_R420; } else if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { DRM_INFO("Loading RS690/RS740 Microcode\n"); - for (i = 0; i < 256; i++) { - WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]); - WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]); - } + fw_name = FIRMWARE_RS690; } else if (rdev->family == CHIP_RS600) { DRM_INFO("Loading RS600 Microcode\n"); - for (i = 0; i < 256; i++) { - WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]); - WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]); - } + fw_name = FIRMWARE_RS600; } else if ((rdev->family == CHIP_RV515) || (rdev->family == CHIP_R520) || (rdev->family == CHIP_RV530) || @@ -544,9 +594,43 @@ static void r100_cp_load_microcode(struct radeon_device *rdev) (rdev->family == CHIP_RV560) || (rdev->family == CHIP_RV570)) { DRM_INFO("Loading R500 Microcode\n"); - for (i = 0; i < 256; i++) { - WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]); - WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]); + fw_name = FIRMWARE_R520; + } + + err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); + platform_device_unregister(pdev); + if (err) { + printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", + fw_name); + } else if (rdev->me_fw->size % 8) { + printk(KERN_ERR + "radeon_cp: Bogus length %zu in firmware \"%s\"\n", + rdev->me_fw->size, fw_name); + err = -EINVAL; + release_firmware(rdev->me_fw); + rdev->me_fw = NULL; + } + return err; +} +static void r100_cp_load_microcode(struct radeon_device *rdev) +{ + const __be32 *fw_data; + int i, size; + + if (r100_gui_wait_for_idle(rdev)) { + printk(KERN_WARNING "Failed to wait GUI idle while " + "programming pipes. Bad things might happen.\n"); + } + + if (rdev->me_fw) { + size = rdev->me_fw->size / 4; + fw_data = (const __be32 *)&rdev->me_fw->data[0]; + WREG32(RADEON_CP_ME_RAM_ADDR, 0); + for (i = 0; i < size; i += 2) { + WREG32(RADEON_CP_ME_RAM_DATAH, + be32_to_cpup(&fw_data[i])); + WREG32(RADEON_CP_ME_RAM_DATAL, + be32_to_cpup(&fw_data[i + 1])); } } } @@ -585,6 +669,15 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) } else { DRM_INFO("radeon: cp idle (0x%08X)\n", tmp); } + + if (!rdev->me_fw) { + r = r100_cp_init_microcode(rdev); + if (r) { + DRM_ERROR("Failed to load firmware!\n"); + return r; + } + } + /* Align ring size */ rb_bufsz = drm_order(ring_size / 8); ring_size = (1 << (rb_bufsz + 1)) * 4; @@ -658,9 +751,11 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) void r100_cp_fini(struct radeon_device *rdev) { + if (r100_cp_wait_for_idle(rdev)) { + DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); + } /* Disable ring */ - rdev->cp.ready = false; - WREG32(RADEON_CP_CSQ_CNTL, 0); + r100_cp_disable(rdev); radeon_ring_fini(rdev); DRM_INFO("radeon: cp finalized\n"); } @@ -710,6 +805,12 @@ int r100_cp_reset(struct radeon_device *rdev) return -1; } +void r100_cp_commit(struct radeon_device *rdev) +{ + WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); + (void)RREG32(RADEON_CP_RB_WPTR); +} + /* * CS functions @@ -968,147 +1069,356 @@ int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, return 0; } +static int r100_get_vtx_size(uint32_t vtx_fmt) +{ + int vtx_size; + vtx_size = 2; + /* ordered according to bits in spec */ + if (vtx_fmt & RADEON_SE_VTX_FMT_W0) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) + vtx_size += 3; + if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) + vtx_size += 3; + if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) + vtx_size += 2; + if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) + vtx_size += 2; + if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) + vtx_size += 2; + if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) + vtx_size += 2; + if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) + vtx_size++; + /* blend weight */ + if (vtx_fmt & (0x7 << 15)) + vtx_size += (vtx_fmt >> 15) & 0x7; + if (vtx_fmt & RADEON_SE_VTX_FMT_N0) + vtx_size += 3; + if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) + vtx_size += 2; + if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_W1) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_N1) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_Z) + vtx_size++; + return vtx_size; +} + static int r100_packet0_check(struct radeon_cs_parser *p, - struct radeon_cs_packet *pkt) + struct radeon_cs_packet *pkt, + unsigned idx, unsigned reg) { struct radeon_cs_chunk *ib_chunk; struct radeon_cs_reloc *reloc; + struct r100_cs_track *track; volatile uint32_t *ib; uint32_t tmp; - unsigned reg; - unsigned i; - unsigned idx; - bool onereg; int r; + int i, face; u32 tile_flags = 0; ib = p->ib->ptr; ib_chunk = &p->chunks[p->chunk_ib_idx]; - idx = pkt->idx + 1; - reg = pkt->reg; - onereg = false; - if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) { - onereg = true; - } - for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { - switch (reg) { - case RADEON_CRTC_GUI_TRIG_VLINE: - r = r100_cs_packet_parse_vline(p); - if (r) { - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", - idx, reg); - r100_cs_dump_packet(p, pkt); - return r; - } - break; + track = (struct r100_cs_track *)p->track; + + switch (reg) { + case RADEON_CRTC_GUI_TRIG_VLINE: + r = r100_cs_packet_parse_vline(p); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + break; /* FIXME: only allow PACKET3 blit? easier to check for out of * range access */ - case RADEON_DST_PITCH_OFFSET: - case RADEON_SRC_PITCH_OFFSET: - r = r100_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", - idx, reg); - r100_cs_dump_packet(p, pkt); - return r; - } - tmp = ib_chunk->kdata[idx] & 0x003fffff; - tmp += (((u32)reloc->lobj.gpu_offset) >> 10); - - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) - tile_flags |= RADEON_DST_TILE_MACRO; - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { - if (reg == RADEON_SRC_PITCH_OFFSET) { - DRM_ERROR("Cannot src blit from microtiled surface\n"); - r100_cs_dump_packet(p, pkt); - return -EINVAL; - } - tile_flags |= RADEON_DST_TILE_MICRO; - } + case RADEON_DST_PITCH_OFFSET: + case RADEON_SRC_PITCH_OFFSET: + r = r100_reloc_pitch_offset(p, pkt, idx, reg); + if (r) + return r; + break; + case RADEON_RB3D_DEPTHOFFSET: + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + track->zb.robj = reloc->robj; + track->zb.offset = ib_chunk->kdata[idx]; + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + break; + case RADEON_RB3D_COLOROFFSET: + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + track->cb[0].robj = reloc->robj; + track->cb[0].offset = ib_chunk->kdata[idx]; + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + break; + case RADEON_PP_TXOFFSET_0: + case RADEON_PP_TXOFFSET_1: + case RADEON_PP_TXOFFSET_2: + i = (reg - RADEON_PP_TXOFFSET_0) / 24; + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + track->textures[i].robj = reloc->robj; + break; + case RADEON_PP_CUBIC_OFFSET_T0_0: + case RADEON_PP_CUBIC_OFFSET_T0_1: + case RADEON_PP_CUBIC_OFFSET_T0_2: + case RADEON_PP_CUBIC_OFFSET_T0_3: + case RADEON_PP_CUBIC_OFFSET_T0_4: + i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + track->textures[0].cube_info[i].offset = ib_chunk->kdata[idx]; + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + track->textures[0].cube_info[i].robj = reloc->robj; + break; + case RADEON_PP_CUBIC_OFFSET_T1_0: + case RADEON_PP_CUBIC_OFFSET_T1_1: + case RADEON_PP_CUBIC_OFFSET_T1_2: + case RADEON_PP_CUBIC_OFFSET_T1_3: + case RADEON_PP_CUBIC_OFFSET_T1_4: + i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + track->textures[1].cube_info[i].offset = ib_chunk->kdata[idx]; + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + track->textures[1].cube_info[i].robj = reloc->robj; + break; + case RADEON_PP_CUBIC_OFFSET_T2_0: + case RADEON_PP_CUBIC_OFFSET_T2_1: + case RADEON_PP_CUBIC_OFFSET_T2_2: + case RADEON_PP_CUBIC_OFFSET_T2_3: + case RADEON_PP_CUBIC_OFFSET_T2_4: + i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + track->textures[2].cube_info[i].offset = ib_chunk->kdata[idx]; + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + track->textures[2].cube_info[i].robj = reloc->robj; + break; + case RADEON_RE_WIDTH_HEIGHT: + track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF); + break; + case RADEON_RB3D_COLORPITCH: + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } - tmp |= tile_flags; - ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; - break; - case RADEON_RB3D_DEPTHOFFSET: - case RADEON_RB3D_COLOROFFSET: - case R300_RB3D_COLOROFFSET0: - case R300_ZB_DEPTHOFFSET: - case R200_PP_TXOFFSET_0: - case R200_PP_TXOFFSET_1: - case R200_PP_TXOFFSET_2: - case R200_PP_TXOFFSET_3: - case R200_PP_TXOFFSET_4: - case R200_PP_TXOFFSET_5: - case RADEON_PP_TXOFFSET_0: - case RADEON_PP_TXOFFSET_1: - case RADEON_PP_TXOFFSET_2: - case R300_TX_OFFSET_0: - case R300_TX_OFFSET_0+4: - case R300_TX_OFFSET_0+8: - case R300_TX_OFFSET_0+12: - case R300_TX_OFFSET_0+16: - case R300_TX_OFFSET_0+20: - case R300_TX_OFFSET_0+24: - case R300_TX_OFFSET_0+28: - case R300_TX_OFFSET_0+32: - case R300_TX_OFFSET_0+36: - case R300_TX_OFFSET_0+40: - case R300_TX_OFFSET_0+44: - case R300_TX_OFFSET_0+48: - case R300_TX_OFFSET_0+52: - case R300_TX_OFFSET_0+56: - case R300_TX_OFFSET_0+60: - /* rn50 has no 3D engine so fail on any 3d setup */ - if (ASIC_IS_RN50(p->rdev)) { - DRM_ERROR("attempt to use RN50 3D engine failed\n"); - return -EINVAL; - } - r = r100_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", - idx, reg); - r100_cs_dump_packet(p, pkt); - return r; - } - ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); - break; - case R300_RB3D_COLORPITCH0: - case RADEON_RB3D_COLORPITCH: - r = r100_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", - idx, reg); - r100_cs_dump_packet(p, pkt); - return r; - } + if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) + tile_flags |= RADEON_COLOR_TILE_ENABLE; + if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) + tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) - tile_flags |= RADEON_COLOR_TILE_ENABLE; - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) - tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; + tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); + tmp |= tile_flags; + ib[idx] = tmp; - tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); - tmp |= tile_flags; - ib[idx] = tmp; + track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK; + break; + case RADEON_RB3D_DEPTHPITCH: + track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK; + break; + case RADEON_RB3D_CNTL: + switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { + case 7: + case 8: + case 9: + case 11: + case 12: + track->cb[0].cpp = 1; break; - case RADEON_RB3D_ZPASS_ADDR: - r = r100_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", - idx, reg); - r100_cs_dump_packet(p, pkt); - return r; - } - ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + case 3: + case 4: + case 15: + track->cb[0].cpp = 2; + break; + case 6: + track->cb[0].cpp = 4; break; default: - /* FIXME: we don't want to allow anyothers packet */ + DRM_ERROR("Invalid color buffer format (%d) !\n", + ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); + return -EINVAL; + } + track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE); + break; + case RADEON_RB3D_ZSTENCILCNTL: + switch (ib_chunk->kdata[idx] & 0xf) { + case 0: + track->zb.cpp = 2; + break; + case 2: + case 3: + case 4: + case 5: + case 9: + case 11: + track->zb.cpp = 4; break; + default: + break; + } + break; + case RADEON_RB3D_ZPASS_ADDR: + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + break; + case RADEON_PP_CNTL: + { + uint32_t temp = ib_chunk->kdata[idx] >> 4; + for (i = 0; i < track->num_texture; i++) + track->textures[i].enabled = !!(temp & (1 << i)); } - if (onereg) { - /* FIXME: forbid onereg write to register on relocate */ + break; + case RADEON_SE_VF_CNTL: + track->vap_vf_cntl = ib_chunk->kdata[idx]; + break; + case RADEON_SE_VTX_FMT: + track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx]); + break; + case RADEON_PP_TEX_SIZE_0: + case RADEON_PP_TEX_SIZE_1: + case RADEON_PP_TEX_SIZE_2: + i = (reg - RADEON_PP_TEX_SIZE_0) / 8; + track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1; + track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; + break; + case RADEON_PP_TEX_PITCH_0: + case RADEON_PP_TEX_PITCH_1: + case RADEON_PP_TEX_PITCH_2: + i = (reg - RADEON_PP_TEX_PITCH_0) / 8; + track->textures[i].pitch = ib_chunk->kdata[idx] + 32; + break; + case RADEON_PP_TXFILTER_0: + case RADEON_PP_TXFILTER_1: + case RADEON_PP_TXFILTER_2: + i = (reg - RADEON_PP_TXFILTER_0) / 24; + track->textures[i].num_levels = ((ib_chunk->kdata[idx] & RADEON_MAX_MIP_LEVEL_MASK) + >> RADEON_MAX_MIP_LEVEL_SHIFT); + tmp = (ib_chunk->kdata[idx] >> 23) & 0x7; + if (tmp == 2 || tmp == 6) + track->textures[i].roundup_w = false; + tmp = (ib_chunk->kdata[idx] >> 27) & 0x7; + if (tmp == 2 || tmp == 6) + track->textures[i].roundup_h = false; + break; + case RADEON_PP_TXFORMAT_0: + case RADEON_PP_TXFORMAT_1: + case RADEON_PP_TXFORMAT_2: + i = (reg - RADEON_PP_TXFORMAT_0) / 24; + if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_NON_POWER2) { + track->textures[i].use_pitch = 1; + } else { + track->textures[i].use_pitch = 0; + track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); + track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); + } + if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) + track->textures[i].tex_coord_type = 2; + switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) { + case RADEON_TXFORMAT_I8: + case RADEON_TXFORMAT_RGB332: + case RADEON_TXFORMAT_Y8: + track->textures[i].cpp = 1; break; + case RADEON_TXFORMAT_AI88: + case RADEON_TXFORMAT_ARGB1555: + case RADEON_TXFORMAT_RGB565: + case RADEON_TXFORMAT_ARGB4444: + case RADEON_TXFORMAT_VYUY422: + case RADEON_TXFORMAT_YVYU422: + case RADEON_TXFORMAT_DXT1: + case RADEON_TXFORMAT_SHADOW16: + case RADEON_TXFORMAT_LDUDV655: + case RADEON_TXFORMAT_DUDV88: + track->textures[i].cpp = 2; + break; + case RADEON_TXFORMAT_ARGB8888: + case RADEON_TXFORMAT_RGBA8888: + case RADEON_TXFORMAT_DXT23: + case RADEON_TXFORMAT_DXT45: + case RADEON_TXFORMAT_SHADOW32: + case RADEON_TXFORMAT_LDUDUV8888: + track->textures[i].cpp = 4; + break; + } + track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf); + track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf); + break; + case RADEON_PP_CUBIC_FACES_0: + case RADEON_PP_CUBIC_FACES_1: + case RADEON_PP_CUBIC_FACES_2: + tmp = ib_chunk->kdata[idx]; + i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; + for (face = 0; face < 4; face++) { + track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); + track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); } + break; + default: + printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", + reg, idx); + return -EINVAL; } return 0; } @@ -1137,6 +1447,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p, { struct radeon_cs_chunk *ib_chunk; struct radeon_cs_reloc *reloc; + struct r100_cs_track *track; unsigned idx; unsigned i, c; volatile uint32_t *ib; @@ -1145,9 +1456,11 @@ static int r100_packet3_check(struct radeon_cs_parser *p, ib = p->ib->ptr; ib_chunk = &p->chunks[p->chunk_ib_idx]; idx = pkt->idx + 1; + track = (struct r100_cs_track *)p->track; switch (pkt->opcode) { case PACKET3_3D_LOAD_VBPNTR: c = ib_chunk->kdata[idx++]; + track->num_arrays = c; for (i = 0; i < (c - 1); i += 2, idx += 3) { r = r100_cs_packet_next_reloc(p, &reloc); if (r) { @@ -1157,6 +1470,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p, return r; } ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); + track->arrays[i + 0].robj = reloc->robj; + track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; + track->arrays[i + 0].esize &= 0x7F; r = r100_cs_packet_next_reloc(p, &reloc); if (r) { DRM_ERROR("No reloc for packet3 %d\n", @@ -1165,6 +1481,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p, return r; } ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset); + track->arrays[i + 1].robj = reloc->robj; + track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24; + track->arrays[i + 1].esize &= 0x7F; } if (c & 1) { r = r100_cs_packet_next_reloc(p, &reloc); @@ -1175,6 +1494,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p, return r; } ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); + track->arrays[i + 0].robj = reloc->robj; + track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; + track->arrays[i + 0].esize &= 0x7F; } break; case PACKET3_INDX_BUFFER: @@ -1191,7 +1513,6 @@ static int r100_packet3_check(struct radeon_cs_parser *p, } break; case 0x23: - /* FIXME: cleanup */ /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ r = r100_cs_packet_next_reloc(p, &reloc); if (r) { @@ -1200,18 +1521,71 @@ static int r100_packet3_check(struct radeon_cs_parser *p, return r; } ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + track->num_arrays = 1; + track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx+2]); + + track->arrays[0].robj = reloc->robj; + track->arrays[0].esize = track->vtx_size; + + track->max_indx = ib_chunk->kdata[idx+1]; + + track->vap_vf_cntl = ib_chunk->kdata[idx+3]; + track->immd_dwords = pkt->count - 1; + r = r100_cs_track_check(p->rdev, track); + if (r) + return r; break; case PACKET3_3D_DRAW_IMMD: + if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) { + DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); + return -EINVAL; + } + track->vap_vf_cntl = ib_chunk->kdata[idx+1]; + track->immd_dwords = pkt->count - 1; + r = r100_cs_track_check(p->rdev, track); + if (r) + return r; + break; /* triggers drawing using in-packet vertex data */ case PACKET3_3D_DRAW_IMMD_2: + if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) { + DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); + return -EINVAL; + } + track->vap_vf_cntl = ib_chunk->kdata[idx]; + track->immd_dwords = pkt->count; + r = r100_cs_track_check(p->rdev, track); + if (r) + return r; + break; /* triggers drawing using in-packet vertex data */ case PACKET3_3D_DRAW_VBUF_2: + track->vap_vf_cntl = ib_chunk->kdata[idx]; + r = r100_cs_track_check(p->rdev, track); + if (r) + return r; + break; /* triggers drawing of vertex buffers setup elsewhere */ case PACKET3_3D_DRAW_INDX_2: + track->vap_vf_cntl = ib_chunk->kdata[idx]; + r = r100_cs_track_check(p->rdev, track); + if (r) + return r; + break; /* triggers drawing using indices to vertex buffer */ case PACKET3_3D_DRAW_VBUF: + track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; + r = r100_cs_track_check(p->rdev, track); + if (r) + return r; + break; /* triggers drawing of vertex buffers setup elsewhere */ case PACKET3_3D_DRAW_INDX: + track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; + r = r100_cs_track_check(p->rdev, track); + if (r) + return r; + break; /* triggers drawing using indices to vertex buffer */ case PACKET3_NOP: break; @@ -1225,8 +1599,12 @@ static int r100_packet3_check(struct radeon_cs_parser *p, int r100_cs_parse(struct radeon_cs_parser *p) { struct radeon_cs_packet pkt; + struct r100_cs_track *track; int r; + track = kzalloc(sizeof(*track), GFP_KERNEL); + r100_cs_track_clear(p->rdev, track); + p->track = track; do { r = r100_cs_packet_parse(p, &pkt, p->idx); if (r) { @@ -1235,7 +1613,16 @@ int r100_cs_parse(struct radeon_cs_parser *p) p->idx += pkt.count + 2; switch (pkt.type) { case PACKET_TYPE0: - r = r100_packet0_check(p, &pkt); + if (p->rdev->family >= CHIP_R200) + r = r100_cs_parse_packet0(p, &pkt, + p->rdev->config.r100.reg_safe_bm, + p->rdev->config.r100.reg_safe_bm_size, + &r200_packet0_check); + else + r = r100_cs_parse_packet0(p, &pkt, + p->rdev->config.r100.reg_safe_bm, + p->rdev->config.r100.reg_safe_bm_size, + &r100_packet0_check); break; case PACKET_TYPE2: break; @@ -1568,6 +1955,20 @@ void r100_vram_init_sizes(struct radeon_device *rdev) rdev->mc.real_vram_size = rdev->mc.aper_size; } +void r100_vga_set_state(struct radeon_device *rdev, bool state) +{ + uint32_t temp; + + temp = RREG32(RADEON_CONFIG_CNTL); + if (state == false) { + temp &= ~(1<<8); + temp |= (1<<9); + } else { + temp &= ~(1<<9); + } + WREG32(RADEON_CONFIG_CNTL, temp); +} + void r100_vram_info(struct radeon_device *rdev) { r100_vram_get_type(rdev); @@ -1634,6 +2035,15 @@ void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) int r100_init(struct radeon_device *rdev) { + if (ASIC_IS_RN50(rdev)) { + rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; + rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); + } else if (rdev->family < CHIP_R200) { + rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; + rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); + } else { + return r200_init(rdev); + } return 0; } @@ -1839,6 +2249,11 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg, flags |= R300_SURF_TILE_MICRO; } + if (tiling_flags & RADEON_TILING_SWAP_16BIT) + flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; + if (tiling_flags & RADEON_TILING_SWAP_32BIT) + flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; + DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); WREG32(RADEON_SURFACE0_INFO + surf_index, flags); WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); @@ -2334,3 +2749,460 @@ void r100_bandwidth_update(struct radeon_device *rdev) (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); } } + +static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t) +{ + DRM_ERROR("pitch %d\n", t->pitch); + DRM_ERROR("width %d\n", t->width); + DRM_ERROR("height %d\n", t->height); + DRM_ERROR("num levels %d\n", t->num_levels); + DRM_ERROR("depth %d\n", t->txdepth); + DRM_ERROR("bpp %d\n", t->cpp); + DRM_ERROR("coordinate type %d\n", t->tex_coord_type); + DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); + DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); +} + +static int r100_cs_track_cube(struct radeon_device *rdev, + struct r100_cs_track *track, unsigned idx) +{ + unsigned face, w, h; + struct radeon_object *cube_robj; + unsigned long size; + + for (face = 0; face < 5; face++) { + cube_robj = track->textures[idx].cube_info[face].robj; + w = track->textures[idx].cube_info[face].width; + h = track->textures[idx].cube_info[face].height; + + size = w * h; + size *= track->textures[idx].cpp; + + size += track->textures[idx].cube_info[face].offset; + + if (size > radeon_object_size(cube_robj)) { + DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", + size, radeon_object_size(cube_robj)); + r100_cs_track_texture_print(&track->textures[idx]); + return -1; + } + } + return 0; +} + +static int r100_cs_track_texture_check(struct radeon_device *rdev, + struct r100_cs_track *track) +{ + struct radeon_object *robj; + unsigned long size; + unsigned u, i, w, h; + int ret; + + for (u = 0; u < track->num_texture; u++) { + if (!track->textures[u].enabled) + continue; + robj = track->textures[u].robj; + if (robj == NULL) { + DRM_ERROR("No texture bound to unit %u\n", u); + return -EINVAL; + } + size = 0; + for (i = 0; i <= track->textures[u].num_levels; i++) { + if (track->textures[u].use_pitch) { + if (rdev->family < CHIP_R300) + w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); + else + w = track->textures[u].pitch / (1 << i); + } else { + w = track->textures[u].width / (1 << i); + if (rdev->family >= CHIP_RV515) + w |= track->textures[u].width_11; + if (track->textures[u].roundup_w) + w = roundup_pow_of_two(w); + } + h = track->textures[u].height / (1 << i); + if (rdev->family >= CHIP_RV515) + h |= track->textures[u].height_11; + if (track->textures[u].roundup_h) + h = roundup_pow_of_two(h); + size += w * h; + } + size *= track->textures[u].cpp; + switch (track->textures[u].tex_coord_type) { + case 0: + break; + case 1: + size *= (1 << track->textures[u].txdepth); + break; + case 2: + if (track->separate_cube) { + ret = r100_cs_track_cube(rdev, track, u); + if (ret) + return ret; + } else + size *= 6; + break; + default: + DRM_ERROR("Invalid texture coordinate type %u for unit " + "%u\n", track->textures[u].tex_coord_type, u); + return -EINVAL; + } + if (size > radeon_object_size(robj)) { + DRM_ERROR("Texture of unit %u needs %lu bytes but is " + "%lu\n", u, size, radeon_object_size(robj)); + r100_cs_track_texture_print(&track->textures[u]); + return -EINVAL; + } + } + return 0; +} + +int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) +{ + unsigned i; + unsigned long size; + unsigned prim_walk; + unsigned nverts; + + for (i = 0; i < track->num_cb; i++) { + if (track->cb[i].robj == NULL) { + DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); + return -EINVAL; + } + size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; + size += track->cb[i].offset; + if (size > radeon_object_size(track->cb[i].robj)) { + DRM_ERROR("[drm] Buffer too small for color buffer %d " + "(need %lu have %lu) !\n", i, size, + radeon_object_size(track->cb[i].robj)); + DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", + i, track->cb[i].pitch, track->cb[i].cpp, + track->cb[i].offset, track->maxy); + return -EINVAL; + } + } + if (track->z_enabled) { + if (track->zb.robj == NULL) { + DRM_ERROR("[drm] No buffer for z buffer !\n"); + return -EINVAL; + } + size = track->zb.pitch * track->zb.cpp * track->maxy; + size += track->zb.offset; + if (size > radeon_object_size(track->zb.robj)) { + DRM_ERROR("[drm] Buffer too small for z buffer " + "(need %lu have %lu) !\n", size, + radeon_object_size(track->zb.robj)); + DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", + track->zb.pitch, track->zb.cpp, + track->zb.offset, track->maxy); + return -EINVAL; + } + } + prim_walk = (track->vap_vf_cntl >> 4) & 0x3; + nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; + switch (prim_walk) { + case 1: + for (i = 0; i < track->num_arrays; i++) { + size = track->arrays[i].esize * track->max_indx * 4; + if (track->arrays[i].robj == NULL) { + DRM_ERROR("(PW %u) Vertex array %u no buffer " + "bound\n", prim_walk, i); + return -EINVAL; + } + if (size > radeon_object_size(track->arrays[i].robj)) { + DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " + "have %lu dwords\n", prim_walk, i, + size >> 2, + radeon_object_size(track->arrays[i].robj) >> 2); + DRM_ERROR("Max indices %u\n", track->max_indx); + return -EINVAL; + } + } + break; + case 2: + for (i = 0; i < track->num_arrays; i++) { + size = track->arrays[i].esize * (nverts - 1) * 4; + if (track->arrays[i].robj == NULL) { + DRM_ERROR("(PW %u) Vertex array %u no buffer " + "bound\n", prim_walk, i); + return -EINVAL; + } + if (size > radeon_object_size(track->arrays[i].robj)) { + DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " + "have %lu dwords\n", prim_walk, i, size >> 2, + radeon_object_size(track->arrays[i].robj) >> 2); + return -EINVAL; + } + } + break; + case 3: + size = track->vtx_size * nverts; + if (size != track->immd_dwords) { + DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", + track->immd_dwords, size); + DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", + nverts, track->vtx_size); + return -EINVAL; + } + break; + default: + DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", + prim_walk); + return -EINVAL; + } + return r100_cs_track_texture_check(rdev, track); +} + +void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) +{ + unsigned i, face; + + if (rdev->family < CHIP_R300) { + track->num_cb = 1; + if (rdev->family <= CHIP_RS200) + track->num_texture = 3; + else + track->num_texture = 6; + track->maxy = 2048; + track->separate_cube = 1; + } else { + track->num_cb = 4; + track->num_texture = 16; + track->maxy = 4096; + track->separate_cube = 0; + } + + for (i = 0; i < track->num_cb; i++) { + track->cb[i].robj = NULL; + track->cb[i].pitch = 8192; + track->cb[i].cpp = 16; + track->cb[i].offset = 0; + } + track->z_enabled = true; + track->zb.robj = NULL; + track->zb.pitch = 8192; + track->zb.cpp = 4; + track->zb.offset = 0; + track->vtx_size = 0x7F; + track->immd_dwords = 0xFFFFFFFFUL; + track->num_arrays = 11; + track->max_indx = 0x00FFFFFFUL; + for (i = 0; i < track->num_arrays; i++) { + track->arrays[i].robj = NULL; + track->arrays[i].esize = 0x7F; + } + for (i = 0; i < track->num_texture; i++) { + track->textures[i].pitch = 16536; + track->textures[i].width = 16536; + track->textures[i].height = 16536; + track->textures[i].width_11 = 1 << 11; + track->textures[i].height_11 = 1 << 11; + track->textures[i].num_levels = 12; + if (rdev->family <= CHIP_RS200) { + track->textures[i].tex_coord_type = 0; + track->textures[i].txdepth = 0; + } else { + track->textures[i].txdepth = 16; + track->textures[i].tex_coord_type = 1; + } + track->textures[i].cpp = 64; + track->textures[i].robj = NULL; + /* CS IB emission code makes sure texture unit are disabled */ + track->textures[i].enabled = false; + track->textures[i].roundup_w = true; + track->textures[i].roundup_h = true; + if (track->separate_cube) + for (face = 0; face < 5; face++) { + track->textures[i].cube_info[face].robj = NULL; + track->textures[i].cube_info[face].width = 16536; + track->textures[i].cube_info[face].height = 16536; + track->textures[i].cube_info[face].offset = 0; + } + } +} + +int r100_ring_test(struct radeon_device *rdev) +{ + uint32_t scratch; + uint32_t tmp = 0; + unsigned i; + int r; + + r = radeon_scratch_get(rdev, &scratch); + if (r) { + DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + r = radeon_ring_lock(rdev, 2); + if (r) { + DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); + radeon_scratch_free(rdev, scratch); + return r; + } + radeon_ring_write(rdev, PACKET0(scratch, 0)); + radeon_ring_write(rdev, 0xDEADBEEF); + radeon_ring_unlock_commit(rdev); + for (i = 0; i < rdev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) { + break; + } + DRM_UDELAY(1); + } + if (i < rdev->usec_timeout) { + DRM_INFO("ring test succeeded in %d usecs\n", i); + } else { + DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n", + scratch, tmp); + r = -EINVAL; + } + radeon_scratch_free(rdev, scratch); + return r; +} + +void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) +{ + radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); + radeon_ring_write(rdev, ib->gpu_addr); + radeon_ring_write(rdev, ib->length_dw); +} + +int r100_ib_test(struct radeon_device *rdev) +{ + struct radeon_ib *ib; + uint32_t scratch; + uint32_t tmp = 0; + unsigned i; + int r; + + r = radeon_scratch_get(rdev, &scratch); + if (r) { + DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + r = radeon_ib_get(rdev, &ib); + if (r) { + return r; + } + ib->ptr[0] = PACKET0(scratch, 0); + ib->ptr[1] = 0xDEADBEEF; + ib->ptr[2] = PACKET2(0); + ib->ptr[3] = PACKET2(0); + ib->ptr[4] = PACKET2(0); + ib->ptr[5] = PACKET2(0); + ib->ptr[6] = PACKET2(0); + ib->ptr[7] = PACKET2(0); + ib->length_dw = 8; + r = radeon_ib_schedule(rdev, ib); + if (r) { + radeon_scratch_free(rdev, scratch); + radeon_ib_free(rdev, &ib); + return r; + } + r = radeon_fence_wait(ib->fence, false); + if (r) { + return r; + } + for (i = 0; i < rdev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) { + break; + } + DRM_UDELAY(1); + } + if (i < rdev->usec_timeout) { + DRM_INFO("ib test succeeded in %u usecs\n", i); + } else { + DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", + scratch, tmp); + r = -EINVAL; + } + radeon_scratch_free(rdev, scratch); + radeon_ib_free(rdev, &ib); + return r; +} + +void r100_ib_fini(struct radeon_device *rdev) +{ + radeon_ib_pool_fini(rdev); +} + +int r100_ib_init(struct radeon_device *rdev) +{ + int r; + + r = radeon_ib_pool_init(rdev); + if (r) { + dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r); + r100_ib_fini(rdev); + return r; + } + r = r100_ib_test(rdev); + if (r) { + dev_err(rdev->dev, "failled testing IB (%d).\n", r); + r100_ib_fini(rdev); + return r; + } + return 0; +} + +void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) +{ + /* Shutdown CP we shouldn't need to do that but better be safe than + * sorry + */ + rdev->cp.ready = false; + WREG32(R_000740_CP_CSQ_CNTL, 0); + + /* Save few CRTC registers */ + save->GENMO_WT = RREG32(R_0003C0_GENMO_WT); + save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); + save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); + save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); + if (!(rdev->flags & RADEON_SINGLE_CRTC)) { + save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); + save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); + } + + /* Disable VGA aperture access */ + WREG32(R_0003C0_GENMO_WT, C_0003C0_VGA_RAM_EN & save->GENMO_WT); + /* Disable cursor, overlay, crtc */ + WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); + WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | + S_000054_CRTC_DISPLAY_DIS(1)); + WREG32(R_000050_CRTC_GEN_CNTL, + (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | + S_000050_CRTC_DISP_REQ_EN_B(1)); + WREG32(R_000420_OV0_SCALE_CNTL, + C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); + WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); + if (!(rdev->flags & RADEON_SINGLE_CRTC)) { + WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | + S_000360_CUR2_LOCK(1)); + WREG32(R_0003F8_CRTC2_GEN_CNTL, + (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | + S_0003F8_CRTC2_DISPLAY_DIS(1) | + S_0003F8_CRTC2_DISP_REQ_EN_B(1)); + WREG32(R_000360_CUR2_OFFSET, + C_000360_CUR2_LOCK & save->CUR2_OFFSET); + } +} + +void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) +{ + /* Update base address for crtc */ + WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location); + if (!(rdev->flags & RADEON_SINGLE_CRTC)) { + WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, + rdev->mc.vram_location); + } + /* Restore CRTC registers */ + WREG32(R_0003C0_GENMO_WT, save->GENMO_WT); + WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); + WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); + if (!(rdev->flags & RADEON_SINGLE_CRTC)) { + WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); + } +} diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h new file mode 100644 index 000000000000..70a82eda394a --- /dev/null +++ b/drivers/gpu/drm/radeon/r100_track.h @@ -0,0 +1,124 @@ + +#define R100_TRACK_MAX_TEXTURE 3 +#define R200_TRACK_MAX_TEXTURE 6 +#define R300_TRACK_MAX_TEXTURE 16 + +#define R100_MAX_CB 1 +#define R300_MAX_CB 4 + +/* + * CS functions + */ +struct r100_cs_track_cb { + struct radeon_object *robj; + unsigned pitch; + unsigned cpp; + unsigned offset; +}; + +struct r100_cs_track_array { + struct radeon_object *robj; + unsigned esize; +}; + +struct r100_cs_cube_info { + struct radeon_object *robj; + unsigned offset; + unsigned width; + unsigned height; +}; + +struct r100_cs_track_texture { + struct radeon_object *robj; + struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */ + unsigned pitch; + unsigned width; + unsigned height; + unsigned num_levels; + unsigned cpp; + unsigned tex_coord_type; + unsigned txdepth; + unsigned width_11; + unsigned height_11; + bool use_pitch; + bool enabled; + bool roundup_w; + bool roundup_h; +}; + +struct r100_cs_track_limits { + unsigned num_cb; + unsigned num_texture; + unsigned max_levels; +}; + +struct r100_cs_track { + struct radeon_device *rdev; + unsigned num_cb; + unsigned num_texture; + unsigned maxy; + unsigned vtx_size; + unsigned vap_vf_cntl; + unsigned immd_dwords; + unsigned num_arrays; + unsigned max_indx; + struct r100_cs_track_array arrays[11]; + struct r100_cs_track_cb cb[R300_MAX_CB]; + struct r100_cs_track_cb zb; + struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; + bool z_enabled; + bool separate_cube; + +}; + +int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); +void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track); +int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, + struct radeon_cs_reloc **cs_reloc); +void r100_cs_dump_packet(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt); + +int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); + +int r200_packet0_check(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt, + unsigned idx, unsigned reg); + +static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt, + unsigned idx, + unsigned reg) +{ + int r; + u32 tile_flags = 0; + u32 tmp; + struct radeon_cs_reloc *reloc; + struct radeon_cs_chunk *ib_chunk; + + ib_chunk = &p->chunks[p->chunk_ib_idx]; + + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + tmp = ib_chunk->kdata[idx] & 0x003fffff; + tmp += (((u32)reloc->lobj.gpu_offset) >> 10); + + if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) + tile_flags |= RADEON_DST_TILE_MACRO; + if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { + if (reg == RADEON_SRC_PITCH_OFFSET) { + DRM_ERROR("Cannot src blit from microtiled surface\n"); + r100_cs_dump_packet(p, pkt); + return -EINVAL; + } + tile_flags |= RADEON_DST_TILE_MICRO; + } + + tmp |= tile_flags; + p->ib->ptr[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; + return 0; +} diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h new file mode 100644 index 000000000000..c4b257ec920e --- /dev/null +++ b/drivers/gpu/drm/radeon/r100d.h @@ -0,0 +1,607 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef __R100D_H__ +#define __R100D_H__ + +#define CP_PACKET0 0x00000000 +#define PACKET0_BASE_INDEX_SHIFT 0 +#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) +#define PACKET0_COUNT_SHIFT 16 +#define PACKET0_COUNT_MASK (0x3fff << 16) +#define CP_PACKET1 0x40000000 +#define CP_PACKET2 0x80000000 +#define PACKET2_PAD_SHIFT 0 +#define PACKET2_PAD_MASK (0x3fffffff << 0) +#define CP_PACKET3 0xC0000000 +#define PACKET3_IT_OPCODE_SHIFT 8 +#define PACKET3_IT_OPCODE_MASK (0xff << 8) +#define PACKET3_COUNT_SHIFT 16 +#define PACKET3_COUNT_MASK (0x3fff << 16) +/* PACKET3 op code */ +#define PACKET3_NOP 0x10 +#define PACKET3_3D_DRAW_VBUF 0x28 +#define PACKET3_3D_DRAW_IMMD 0x29 +#define PACKET3_3D_DRAW_INDX 0x2A +#define PACKET3_3D_LOAD_VBPNTR 0x2F +#define PACKET3_INDX_BUFFER 0x33 +#define PACKET3_3D_DRAW_VBUF_2 0x34 +#define PACKET3_3D_DRAW_IMMD_2 0x35 +#define PACKET3_3D_DRAW_INDX_2 0x36 +#define PACKET3_BITBLT_MULTI 0x9B + +#define PACKET0(reg, n) (CP_PACKET0 | \ + REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ + REG_SET(PACKET0_COUNT, (n))) +#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) +#define PACKET3(op, n) (CP_PACKET3 | \ + REG_SET(PACKET3_IT_OPCODE, (op)) | \ + REG_SET(PACKET3_COUNT, (n))) + +#define PACKET_TYPE0 0 +#define PACKET_TYPE1 1 +#define PACKET_TYPE2 2 +#define PACKET_TYPE3 3 + +#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) +#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) +#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) +#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) +#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) + +/* Registers */ +#define R_000040_GEN_INT_CNTL 0x000040 +#define S_000040_CRTC_VBLANK(x) (((x) & 0x1) << 0) +#define G_000040_CRTC_VBLANK(x) (((x) >> 0) & 0x1) +#define C_000040_CRTC_VBLANK 0xFFFFFFFE +#define S_000040_CRTC_VLINE(x) (((x) & 0x1) << 1) +#define G_000040_CRTC_VLINE(x) (((x) >> 1) & 0x1) +#define C_000040_CRTC_VLINE 0xFFFFFFFD +#define S_000040_CRTC_VSYNC(x) (((x) & 0x1) << 2) +#define G_000040_CRTC_VSYNC(x) (((x) >> 2) & 0x1) +#define C_000040_CRTC_VSYNC 0xFFFFFFFB +#define S_000040_SNAPSHOT(x) (((x) & 0x1) << 3) +#define G_000040_SNAPSHOT(x) (((x) >> 3) & 0x1) +#define C_000040_SNAPSHOT 0xFFFFFFF7 +#define S_000040_FP_DETECT(x) (((x) & 0x1) << 4) +#define G_000040_FP_DETECT(x) (((x) >> 4) & 0x1) +#define C_000040_FP_DETECT 0xFFFFFFEF +#define S_000040_CRTC2_VLINE(x) (((x) & 0x1) << 5) +#define G_000040_CRTC2_VLINE(x) (((x) >> 5) & 0x1) +#define C_000040_CRTC2_VLINE 0xFFFFFFDF +#define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12) +#define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1) +#define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF +#define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6) +#define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1) +#define C_000040_CRTC2_VSYNC 0xFFFFFFBF +#define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7) +#define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1) +#define C_000040_SNAPSHOT2 0xFFFFFF7F +#define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9) +#define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1) +#define C_000040_CRTC2_VBLANK 0xFFFFFDFF +#define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10) +#define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1) +#define C_000040_FP2_DETECT 0xFFFFFBFF +#define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11) +#define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1) +#define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF +#define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) +#define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) +#define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF +#define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) +#define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) +#define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF +#define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) +#define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) +#define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF +#define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17) +#define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1) +#define C_000040_I2C_INT_EN 0xFFFDFFFF +#define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19) +#define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1) +#define C_000040_GUI_IDLE 0xFFF7FFFF +#define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24) +#define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1) +#define C_000040_VIPH_INT_EN 0xFEFFFFFF +#define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25) +#define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1) +#define C_000040_SW_INT_EN 0xFDFFFFFF +#define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27) +#define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1) +#define C_000040_GEYSERVILLE 0xF7FFFFFF +#define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28) +#define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1) +#define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF +#define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29) +#define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1) +#define C_000040_DVI_I2C_INT 0xDFFFFFFF +#define S_000040_GUIDMA(x) (((x) & 0x1) << 30) +#define G_000040_GUIDMA(x) (((x) >> 30) & 0x1) +#define C_000040_GUIDMA 0xBFFFFFFF +#define S_000040_VIDDMA(x) (((x) & 0x1) << 31) +#define G_000040_VIDDMA(x) (((x) >> 31) & 0x1) +#define C_000040_VIDDMA 0x7FFFFFFF +#define R_000044_GEN_INT_STATUS 0x000044 +#define S_000044_CRTC_VBLANK_STAT(x) (((x) & 0x1) << 0) +#define G_000044_CRTC_VBLANK_STAT(x) (((x) >> 0) & 0x1) +#define C_000044_CRTC_VBLANK_STAT 0xFFFFFFFE +#define S_000044_CRTC_VBLANK_STAT_AK(x) (((x) & 0x1) << 0) +#define G_000044_CRTC_VBLANK_STAT_AK(x) (((x) >> 0) & 0x1) +#define C_000044_CRTC_VBLANK_STAT_AK 0xFFFFFFFE +#define S_000044_CRTC_VLINE_STAT(x) (((x) & 0x1) << 1) +#define G_000044_CRTC_VLINE_STAT(x) (((x) >> 1) & 0x1) +#define C_000044_CRTC_VLINE_STAT 0xFFFFFFFD +#define S_000044_CRTC_VLINE_STAT_AK(x) (((x) & 0x1) << 1) +#define G_000044_CRTC_VLINE_STAT_AK(x) (((x) >> 1) & 0x1) +#define C_000044_CRTC_VLINE_STAT_AK 0xFFFFFFFD +#define S_000044_CRTC_VSYNC_STAT(x) (((x) & 0x1) << 2) +#define G_000044_CRTC_VSYNC_STAT(x) (((x) >> 2) & 0x1) +#define C_000044_CRTC_VSYNC_STAT 0xFFFFFFFB +#define S_000044_CRTC_VSYNC_STAT_AK(x) (((x) & 0x1) << 2) +#define G_000044_CRTC_VSYNC_STAT_AK(x) (((x) >> 2) & 0x1) +#define C_000044_CRTC_VSYNC_STAT_AK 0xFFFFFFFB +#define S_000044_SNAPSHOT_STAT(x) (((x) & 0x1) << 3) +#define G_000044_SNAPSHOT_STAT(x) (((x) >> 3) & 0x1) +#define C_000044_SNAPSHOT_STAT 0xFFFFFFF7 +#define S_000044_SNAPSHOT_STAT_AK(x) (((x) & 0x1) << 3) +#define G_000044_SNAPSHOT_STAT_AK(x) (((x) >> 3) & 0x1) +#define C_000044_SNAPSHOT_STAT_AK 0xFFFFFFF7 +#define S_000044_FP_DETECT_STAT(x) (((x) & 0x1) << 4) +#define G_000044_FP_DETECT_STAT(x) (((x) >> 4) & 0x1) +#define C_000044_FP_DETECT_STAT 0xFFFFFFEF +#define S_000044_FP_DETECT_STAT_AK(x) (((x) & 0x1) << 4) +#define G_000044_FP_DETECT_STAT_AK(x) (((x) >> 4) & 0x1) +#define C_000044_FP_DETECT_STAT_AK 0xFFFFFFEF +#define S_000044_CRTC2_VLINE_STAT(x) (((x) & 0x1) << 5) +#define G_000044_CRTC2_VLINE_STAT(x) (((x) >> 5) & 0x1) +#define C_000044_CRTC2_VLINE_STAT 0xFFFFFFDF +#define S_000044_CRTC2_VLINE_STAT_AK(x) (((x) & 0x1) << 5) +#define G_000044_CRTC2_VLINE_STAT_AK(x) (((x) >> 5) & 0x1) +#define C_000044_CRTC2_VLINE_STAT_AK 0xFFFFFFDF +#define S_000044_CRTC2_VSYNC_STAT(x) (((x) & 0x1) << 6) +#define G_000044_CRTC2_VSYNC_STAT(x) (((x) >> 6) & 0x1) +#define C_000044_CRTC2_VSYNC_STAT 0xFFFFFFBF +#define S_000044_CRTC2_VSYNC_STAT_AK(x) (((x) & 0x1) << 6) +#define G_000044_CRTC2_VSYNC_STAT_AK(x) (((x) >> 6) & 0x1) +#define C_000044_CRTC2_VSYNC_STAT_AK 0xFFFFFFBF +#define S_000044_SNAPSHOT2_STAT(x) (((x) & 0x1) << 7) +#define G_000044_SNAPSHOT2_STAT(x) (((x) >> 7) & 0x1) +#define C_000044_SNAPSHOT2_STAT 0xFFFFFF7F +#define S_000044_SNAPSHOT2_STAT_AK(x) (((x) & 0x1) << 7) +#define G_000044_SNAPSHOT2_STAT_AK(x) (((x) >> 7) & 0x1) +#define C_000044_SNAPSHOT2_STAT_AK 0xFFFFFF7F +#define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8) +#define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1) +#define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF +#define S_000044_CRTC2_VBLANK_STAT(x) (((x) & 0x1) << 9) +#define G_000044_CRTC2_VBLANK_STAT(x) (((x) >> 9) & 0x1) +#define C_000044_CRTC2_VBLANK_STAT 0xFFFFFDFF +#define S_000044_CRTC2_VBLANK_STAT_AK(x) (((x) & 0x1) << 9) +#define G_000044_CRTC2_VBLANK_STAT_AK(x) (((x) >> 9) & 0x1) +#define C_000044_CRTC2_VBLANK_STAT_AK 0xFFFFFDFF +#define S_000044_FP2_DETECT_STAT(x) (((x) & 0x1) << 10) +#define G_000044_FP2_DETECT_STAT(x) (((x) >> 10) & 0x1) +#define C_000044_FP2_DETECT_STAT 0xFFFFFBFF +#define S_000044_FP2_DETECT_STAT_AK(x) (((x) & 0x1) << 10) +#define G_000044_FP2_DETECT_STAT_AK(x) (((x) >> 10) & 0x1) +#define C_000044_FP2_DETECT_STAT_AK 0xFFFFFBFF +#define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) & 0x1) << 11) +#define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) >> 11) & 0x1) +#define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT 0xFFFFF7FF +#define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) & 0x1) << 11) +#define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) >> 11) & 0x1) +#define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK 0xFFFFF7FF +#define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12) +#define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1) +#define C_000044_DMA_VIPH0_INT 0xFFFFEFFF +#define S_000044_DMA_VIPH0_INT_AK(x) (((x) & 0x1) << 12) +#define G_000044_DMA_VIPH0_INT_AK(x) (((x) >> 12) & 0x1) +#define C_000044_DMA_VIPH0_INT_AK 0xFFFFEFFF +#define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13) +#define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1) +#define C_000044_DMA_VIPH1_INT 0xFFFFDFFF +#define S_000044_DMA_VIPH1_INT_AK(x) (((x) & 0x1) << 13) +#define G_000044_DMA_VIPH1_INT_AK(x) (((x) >> 13) & 0x1) +#define C_000044_DMA_VIPH1_INT_AK 0xFFFFDFFF +#define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14) +#define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1) +#define C_000044_DMA_VIPH2_INT 0xFFFFBFFF +#define S_000044_DMA_VIPH2_INT_AK(x) (((x) & 0x1) << 14) +#define G_000044_DMA_VIPH2_INT_AK(x) (((x) >> 14) & 0x1) +#define C_000044_DMA_VIPH2_INT_AK 0xFFFFBFFF +#define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15) +#define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1) +#define C_000044_DMA_VIPH3_INT 0xFFFF7FFF +#define S_000044_DMA_VIPH3_INT_AK(x) (((x) & 0x1) << 15) +#define G_000044_DMA_VIPH3_INT_AK(x) (((x) >> 15) & 0x1) +#define C_000044_DMA_VIPH3_INT_AK 0xFFFF7FFF +#define S_000044_I2C_INT(x) (((x) & 0x1) << 17) +#define G_000044_I2C_INT(x) (((x) >> 17) & 0x1) +#define C_000044_I2C_INT 0xFFFDFFFF +#define S_000044_I2C_INT_AK(x) (((x) & 0x1) << 17) +#define G_000044_I2C_INT_AK(x) (((x) >> 17) & 0x1) +#define C_000044_I2C_INT_AK 0xFFFDFFFF +#define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19) +#define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1) +#define C_000044_GUI_IDLE_STAT 0xFFF7FFFF +#define S_000044_GUI_IDLE_STAT_AK(x) (((x) & 0x1) << 19) +#define G_000044_GUI_IDLE_STAT_AK(x) (((x) >> 19) & 0x1) +#define C_000044_GUI_IDLE_STAT_AK 0xFFF7FFFF +#define S_000044_VIPH_INT(x) (((x) & 0x1) << 24) +#define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1) +#define C_000044_VIPH_INT 0xFEFFFFFF +#define S_000044_SW_INT(x) (((x) & 0x1) << 25) +#define G_000044_SW_INT(x) (((x) >> 25) & 0x1) +#define C_000044_SW_INT 0xFDFFFFFF +#define S_000044_SW_INT_AK(x) (((x) & 0x1) << 25) +#define G_000044_SW_INT_AK(x) (((x) >> 25) & 0x1) +#define C_000044_SW_INT_AK 0xFDFFFFFF +#define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26) +#define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1) +#define C_000044_SW_INT_SET 0xFBFFFFFF +#define S_000044_GEYSERVILLE_STAT(x) (((x) & 0x1) << 27) +#define G_000044_GEYSERVILLE_STAT(x) (((x) >> 27) & 0x1) +#define C_000044_GEYSERVILLE_STAT 0xF7FFFFFF +#define S_000044_GEYSERVILLE_STAT_AK(x) (((x) & 0x1) << 27) +#define G_000044_GEYSERVILLE_STAT_AK(x) (((x) >> 27) & 0x1) +#define C_000044_GEYSERVILLE_STAT_AK 0xF7FFFFFF +#define S_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) & 0x1) << 28) +#define G_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) >> 28) & 0x1) +#define C_000044_HDCP_AUTHORIZED_INT_STAT 0xEFFFFFFF +#define S_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) & 0x1) << 28) +#define G_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) >> 28) & 0x1) +#define C_000044_HDCP_AUTHORIZED_INT_AK 0xEFFFFFFF +#define S_000044_DVI_I2C_INT_STAT(x) (((x) & 0x1) << 29) +#define G_000044_DVI_I2C_INT_STAT(x) (((x) >> 29) & 0x1) +#define C_000044_DVI_I2C_INT_STAT 0xDFFFFFFF +#define S_000044_DVI_I2C_INT_AK(x) (((x) & 0x1) << 29) +#define G_000044_DVI_I2C_INT_AK(x) (((x) >> 29) & 0x1) +#define C_000044_DVI_I2C_INT_AK 0xDFFFFFFF +#define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30) +#define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1) +#define C_000044_GUIDMA_STAT 0xBFFFFFFF +#define S_000044_GUIDMA_AK(x) (((x) & 0x1) << 30) +#define G_000044_GUIDMA_AK(x) (((x) >> 30) & 0x1) +#define C_000044_GUIDMA_AK 0xBFFFFFFF +#define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31) +#define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1) +#define C_000044_VIDDMA_STAT 0x7FFFFFFF +#define S_000044_VIDDMA_AK(x) (((x) & 0x1) << 31) +#define G_000044_VIDDMA_AK(x) (((x) >> 31) & 0x1) +#define C_000044_VIDDMA_AK 0x7FFFFFFF +#define R_000050_CRTC_GEN_CNTL 0x000050 +#define S_000050_CRTC_DBL_SCAN_EN(x) (((x) & 0x1) << 0) +#define G_000050_CRTC_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) +#define C_000050_CRTC_DBL_SCAN_EN 0xFFFFFFFE +#define S_000050_CRTC_INTERLACE_EN(x) (((x) & 0x1) << 1) +#define G_000050_CRTC_INTERLACE_EN(x) (((x) >> 1) & 0x1) +#define C_000050_CRTC_INTERLACE_EN 0xFFFFFFFD +#define S_000050_CRTC_C_SYNC_EN(x) (((x) & 0x1) << 4) +#define G_000050_CRTC_C_SYNC_EN(x) (((x) >> 4) & 0x1) +#define C_000050_CRTC_C_SYNC_EN 0xFFFFFFEF +#define S_000050_CRTC_PIX_WIDTH(x) (((x) & 0xF) << 8) +#define G_000050_CRTC_PIX_WIDTH(x) (((x) >> 8) & 0xF) +#define C_000050_CRTC_PIX_WIDTH 0xFFFFF0FF +#define S_000050_CRTC_ICON_EN(x) (((x) & 0x1) << 15) +#define G_000050_CRTC_ICON_EN(x) (((x) >> 15) & 0x1) +#define C_000050_CRTC_ICON_EN 0xFFFF7FFF +#define S_000050_CRTC_CUR_EN(x) (((x) & 0x1) << 16) +#define G_000050_CRTC_CUR_EN(x) (((x) >> 16) & 0x1) +#define C_000050_CRTC_CUR_EN 0xFFFEFFFF +#define S_000050_CRTC_VSTAT_MODE(x) (((x) & 0x3) << 17) +#define G_000050_CRTC_VSTAT_MODE(x) (((x) >> 17) & 0x3) +#define C_000050_CRTC_VSTAT_MODE 0xFFF9FFFF +#define S_000050_CRTC_CUR_MODE(x) (((x) & 0x7) << 20) +#define G_000050_CRTC_CUR_MODE(x) (((x) >> 20) & 0x7) +#define C_000050_CRTC_CUR_MODE 0xFF8FFFFF +#define S_000050_CRTC_EXT_DISP_EN(x) (((x) & 0x1) << 24) +#define G_000050_CRTC_EXT_DISP_EN(x) (((x) >> 24) & 0x1) +#define C_000050_CRTC_EXT_DISP_EN 0xFEFFFFFF +#define S_000050_CRTC_EN(x) (((x) & 0x1) << 25) +#define G_000050_CRTC_EN(x) (((x) >> 25) & 0x1) +#define C_000050_CRTC_EN 0xFDFFFFFF +#define S_000050_CRTC_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) +#define G_000050_CRTC_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) +#define C_000050_CRTC_DISP_REQ_EN_B 0xFBFFFFFF +#define R_000054_CRTC_EXT_CNTL 0x000054 +#define S_000054_CRTC_VGA_XOVERSCAN(x) (((x) & 0x1) << 0) +#define G_000054_CRTC_VGA_XOVERSCAN(x) (((x) >> 0) & 0x1) +#define C_000054_CRTC_VGA_XOVERSCAN 0xFFFFFFFE +#define S_000054_VGA_BLINK_RATE(x) (((x) & 0x3) << 1) +#define G_000054_VGA_BLINK_RATE(x) (((x) >> 1) & 0x3) +#define C_000054_VGA_BLINK_RATE 0xFFFFFFF9 +#define S_000054_VGA_ATI_LINEAR(x) (((x) & 0x1) << 3) +#define G_000054_VGA_ATI_LINEAR(x) (((x) >> 3) & 0x1) +#define C_000054_VGA_ATI_LINEAR 0xFFFFFFF7 +#define S_000054_VGA_128KAP_PAGING(x) (((x) & 0x1) << 4) +#define G_000054_VGA_128KAP_PAGING(x) (((x) >> 4) & 0x1) +#define C_000054_VGA_128KAP_PAGING 0xFFFFFFEF +#define S_000054_VGA_TEXT_132(x) (((x) & 0x1) << 5) +#define G_000054_VGA_TEXT_132(x) (((x) >> 5) & 0x1) +#define C_000054_VGA_TEXT_132 0xFFFFFFDF +#define S_000054_VGA_XCRT_CNT_EN(x) (((x) & 0x1) << 6) +#define G_000054_VGA_XCRT_CNT_EN(x) (((x) >> 6) & 0x1) +#define C_000054_VGA_XCRT_CNT_EN 0xFFFFFFBF +#define S_000054_CRTC_HSYNC_DIS(x) (((x) & 0x1) << 8) +#define G_000054_CRTC_HSYNC_DIS(x) (((x) >> 8) & 0x1) +#define C_000054_CRTC_HSYNC_DIS 0xFFFFFEFF +#define S_000054_CRTC_VSYNC_DIS(x) (((x) & 0x1) << 9) +#define G_000054_CRTC_VSYNC_DIS(x) (((x) >> 9) & 0x1) +#define C_000054_CRTC_VSYNC_DIS 0xFFFFFDFF +#define S_000054_CRTC_DISPLAY_DIS(x) (((x) & 0x1) << 10) +#define G_000054_CRTC_DISPLAY_DIS(x) (((x) >> 10) & 0x1) +#define C_000054_CRTC_DISPLAY_DIS 0xFFFFFBFF +#define S_000054_CRTC_SYNC_TRISTATE(x) (((x) & 0x1) << 11) +#define G_000054_CRTC_SYNC_TRISTATE(x) (((x) >> 11) & 0x1) +#define C_000054_CRTC_SYNC_TRISTATE 0xFFFFF7FF +#define S_000054_CRTC_HSYNC_TRISTATE(x) (((x) & 0x1) << 12) +#define G_000054_CRTC_HSYNC_TRISTATE(x) (((x) >> 12) & 0x1) +#define C_000054_CRTC_HSYNC_TRISTATE 0xFFFFEFFF +#define S_000054_CRTC_VSYNC_TRISTATE(x) (((x) & 0x1) << 13) +#define G_000054_CRTC_VSYNC_TRISTATE(x) (((x) >> 13) & 0x1) +#define C_000054_CRTC_VSYNC_TRISTATE 0xFFFFDFFF +#define S_000054_CRT_ON(x) (((x) & 0x1) << 15) +#define G_000054_CRT_ON(x) (((x) >> 15) & 0x1) +#define C_000054_CRT_ON 0xFFFF7FFF +#define S_000054_VGA_CUR_B_TEST(x) (((x) & 0x1) << 17) +#define G_000054_VGA_CUR_B_TEST(x) (((x) >> 17) & 0x1) +#define C_000054_VGA_CUR_B_TEST 0xFFFDFFFF +#define S_000054_VGA_PACK_DIS(x) (((x) & 0x1) << 18) +#define G_000054_VGA_PACK_DIS(x) (((x) >> 18) & 0x1) +#define C_000054_VGA_PACK_DIS 0xFFFBFFFF +#define S_000054_VGA_MEM_PS_EN(x) (((x) & 0x1) << 19) +#define G_000054_VGA_MEM_PS_EN(x) (((x) >> 19) & 0x1) +#define C_000054_VGA_MEM_PS_EN 0xFFF7FFFF +#define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24) +#define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F) +#define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF +#define R_00023C_DISPLAY_BASE_ADDR 0x00023C +#define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00023C_DISPLAY_BASE_ADDR 0x00000000 +#define R_000260_CUR_OFFSET 0x000260 +#define S_000260_CUR_OFFSET(x) (((x) & 0x7FFFFFF) << 0) +#define G_000260_CUR_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) +#define C_000260_CUR_OFFSET 0xF8000000 +#define S_000260_CUR_LOCK(x) (((x) & 0x1) << 31) +#define G_000260_CUR_LOCK(x) (((x) >> 31) & 0x1) +#define C_000260_CUR_LOCK 0x7FFFFFFF +#define R_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00033C +#define S_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00000000 +#define R_000360_CUR2_OFFSET 0x000360 +#define S_000360_CUR2_OFFSET(x) (((x) & 0x7FFFFFF) << 0) +#define G_000360_CUR2_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) +#define C_000360_CUR2_OFFSET 0xF8000000 +#define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31) +#define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1) +#define C_000360_CUR2_LOCK 0x7FFFFFFF +#define R_0003C0_GENMO_WT 0x0003C0 +#define S_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0) +#define G_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1) +#define C_0003C0_GENMO_MONO_ADDRESS_B 0xFFFFFFFE +#define S_0003C0_VGA_RAM_EN(x) (((x) & 0x1) << 1) +#define G_0003C0_VGA_RAM_EN(x) (((x) >> 1) & 0x1) +#define C_0003C0_VGA_RAM_EN 0xFFFFFFFD +#define S_0003C0_VGA_CKSEL(x) (((x) & 0x3) << 2) +#define G_0003C0_VGA_CKSEL(x) (((x) >> 2) & 0x3) +#define C_0003C0_VGA_CKSEL 0xFFFFFFF3 +#define S_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5) +#define G_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1) +#define C_0003C0_ODD_EVEN_MD_PGSEL 0xFFFFFFDF +#define S_0003C0_VGA_HSYNC_POL(x) (((x) & 0x1) << 6) +#define G_0003C0_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1) +#define C_0003C0_VGA_HSYNC_POL 0xFFFFFFBF +#define S_0003C0_VGA_VSYNC_POL(x) (((x) & 0x1) << 7) +#define G_0003C0_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1) +#define C_0003C0_VGA_VSYNC_POL 0xFFFFFF7F +#define R_0003F8_CRTC2_GEN_CNTL 0x0003F8 +#define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0) +#define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) +#define C_0003F8_CRTC2_DBL_SCAN_EN 0xFFFFFFFE +#define S_0003F8_CRTC2_INTERLACE_EN(x) (((x) & 0x1) << 1) +#define G_0003F8_CRTC2_INTERLACE_EN(x) (((x) >> 1) & 0x1) +#define C_0003F8_CRTC2_INTERLACE_EN 0xFFFFFFFD +#define S_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) & 0x1) << 4) +#define G_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) >> 4) & 0x1) +#define C_0003F8_CRTC2_SYNC_TRISTATE 0xFFFFFFEF +#define S_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) & 0x1) << 5) +#define G_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) >> 5) & 0x1) +#define C_0003F8_CRTC2_HSYNC_TRISTATE 0xFFFFFFDF +#define S_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) & 0x1) << 6) +#define G_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) >> 6) & 0x1) +#define C_0003F8_CRTC2_VSYNC_TRISTATE 0xFFFFFFBF +#define S_0003F8_CRT2_ON(x) (((x) & 0x1) << 7) +#define G_0003F8_CRT2_ON(x) (((x) >> 7) & 0x1) +#define C_0003F8_CRT2_ON 0xFFFFFF7F +#define S_0003F8_CRTC2_PIX_WIDTH(x) (((x) & 0xF) << 8) +#define G_0003F8_CRTC2_PIX_WIDTH(x) (((x) >> 8) & 0xF) +#define C_0003F8_CRTC2_PIX_WIDTH 0xFFFFF0FF +#define S_0003F8_CRTC2_ICON_EN(x) (((x) & 0x1) << 15) +#define G_0003F8_CRTC2_ICON_EN(x) (((x) >> 15) & 0x1) +#define C_0003F8_CRTC2_ICON_EN 0xFFFF7FFF +#define S_0003F8_CRTC2_CUR_EN(x) (((x) & 0x1) << 16) +#define G_0003F8_CRTC2_CUR_EN(x) (((x) >> 16) & 0x1) +#define C_0003F8_CRTC2_CUR_EN 0xFFFEFFFF +#define S_0003F8_CRTC2_CUR_MODE(x) (((x) & 0x7) << 20) +#define G_0003F8_CRTC2_CUR_MODE(x) (((x) >> 20) & 0x7) +#define C_0003F8_CRTC2_CUR_MODE 0xFF8FFFFF +#define S_0003F8_CRTC2_DISPLAY_DIS(x) (((x) & 0x1) << 23) +#define G_0003F8_CRTC2_DISPLAY_DIS(x) (((x) >> 23) & 0x1) +#define C_0003F8_CRTC2_DISPLAY_DIS 0xFF7FFFFF +#define S_0003F8_CRTC2_EN(x) (((x) & 0x1) << 25) +#define G_0003F8_CRTC2_EN(x) (((x) >> 25) & 0x1) +#define C_0003F8_CRTC2_EN 0xFDFFFFFF +#define S_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) +#define G_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) +#define C_0003F8_CRTC2_DISP_REQ_EN_B 0xFBFFFFFF +#define S_0003F8_CRTC2_C_SYNC_EN(x) (((x) & 0x1) << 27) +#define G_0003F8_CRTC2_C_SYNC_EN(x) (((x) >> 27) & 0x1) +#define C_0003F8_CRTC2_C_SYNC_EN 0xF7FFFFFF +#define S_0003F8_CRTC2_HSYNC_DIS(x) (((x) & 0x1) << 28) +#define G_0003F8_CRTC2_HSYNC_DIS(x) (((x) >> 28) & 0x1) +#define C_0003F8_CRTC2_HSYNC_DIS 0xEFFFFFFF +#define S_0003F8_CRTC2_VSYNC_DIS(x) (((x) & 0x1) << 29) +#define G_0003F8_CRTC2_VSYNC_DIS(x) (((x) >> 29) & 0x1) +#define C_0003F8_CRTC2_VSYNC_DIS 0xDFFFFFFF +#define R_000420_OV0_SCALE_CNTL 0x000420 +#define S_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) & 0x1) << 1) +#define G_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) >> 1) & 0x1) +#define C_000420_OV0_NO_READ_BEHIND_SCAN 0xFFFFFFFD +#define S_000420_OV0_HORZ_PICK_NEAREST(x) (((x) & 0x1) << 2) +#define G_000420_OV0_HORZ_PICK_NEAREST(x) (((x) >> 2) & 0x1) +#define C_000420_OV0_HORZ_PICK_NEAREST 0xFFFFFFFB +#define S_000420_OV0_VERT_PICK_NEAREST(x) (((x) & 0x1) << 3) +#define G_000420_OV0_VERT_PICK_NEAREST(x) (((x) >> 3) & 0x1) +#define C_000420_OV0_VERT_PICK_NEAREST 0xFFFFFFF7 +#define S_000420_OV0_SIGNED_UV(x) (((x) & 0x1) << 4) +#define G_000420_OV0_SIGNED_UV(x) (((x) >> 4) & 0x1) +#define C_000420_OV0_SIGNED_UV 0xFFFFFFEF +#define S_000420_OV0_GAMMA_SEL(x) (((x) & 0x7) << 5) +#define G_000420_OV0_GAMMA_SEL(x) (((x) >> 5) & 0x7) +#define C_000420_OV0_GAMMA_SEL 0xFFFFFF1F +#define S_000420_OV0_SURFACE_FORMAT(x) (((x) & 0xF) << 8) +#define G_000420_OV0_SURFACE_FORMAT(x) (((x) >> 8) & 0xF) +#define C_000420_OV0_SURFACE_FORMAT 0xFFFFF0FF +#define S_000420_OV0_ADAPTIVE_DEINT(x) (((x) & 0x1) << 12) +#define G_000420_OV0_ADAPTIVE_DEINT(x) (((x) >> 12) & 0x1) +#define C_000420_OV0_ADAPTIVE_DEINT 0xFFFFEFFF +#define S_000420_OV0_CRTC_SEL(x) (((x) & 0x1) << 14) +#define G_000420_OV0_CRTC_SEL(x) (((x) >> 14) & 0x1) +#define C_000420_OV0_CRTC_SEL 0xFFFFBFFF +#define S_000420_OV0_BURST_PER_PLANE(x) (((x) & 0x7F) << 16) +#define G_000420_OV0_BURST_PER_PLANE(x) (((x) >> 16) & 0x7F) +#define C_000420_OV0_BURST_PER_PLANE 0xFF80FFFF +#define S_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) & 0x1) << 24) +#define G_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) >> 24) & 0x1) +#define C_000420_OV0_DOUBLE_BUFFER_REGS 0xFEFFFFFF +#define S_000420_OV0_BANDWIDTH(x) (((x) & 0x1) << 26) +#define G_000420_OV0_BANDWIDTH(x) (((x) >> 26) & 0x1) +#define C_000420_OV0_BANDWIDTH 0xFBFFFFFF +#define S_000420_OV0_LIN_TRANS_BYPASS(x) (((x) & 0x1) << 28) +#define G_000420_OV0_LIN_TRANS_BYPASS(x) (((x) >> 28) & 0x1) +#define C_000420_OV0_LIN_TRANS_BYPASS 0xEFFFFFFF +#define S_000420_OV0_INT_EMU(x) (((x) & 0x1) << 29) +#define G_000420_OV0_INT_EMU(x) (((x) >> 29) & 0x1) +#define C_000420_OV0_INT_EMU 0xDFFFFFFF +#define S_000420_OV0_OVERLAY_EN(x) (((x) & 0x1) << 30) +#define G_000420_OV0_OVERLAY_EN(x) (((x) >> 30) & 0x1) +#define C_000420_OV0_OVERLAY_EN 0xBFFFFFFF +#define S_000420_OV0_SOFT_RESET(x) (((x) & 0x1) << 31) +#define G_000420_OV0_SOFT_RESET(x) (((x) >> 31) & 0x1) +#define C_000420_OV0_SOFT_RESET 0x7FFFFFFF +#define R_00070C_CP_RB_RPTR_ADDR 0x00070C +#define S_00070C_RB_RPTR_SWAP(x) (((x) & 0x3) << 0) +#define G_00070C_RB_RPTR_SWAP(x) (((x) >> 0) & 0x3) +#define C_00070C_RB_RPTR_SWAP 0xFFFFFFFC +#define S_00070C_RB_RPTR_ADDR(x) (((x) & 0x3FFFFFFF) << 2) +#define G_00070C_RB_RPTR_ADDR(x) (((x) >> 2) & 0x3FFFFFFF) +#define C_00070C_RB_RPTR_ADDR 0x00000003 +#define R_000740_CP_CSQ_CNTL 0x000740 +#define S_000740_CSQ_CNT_PRIMARY(x) (((x) & 0xFF) << 0) +#define G_000740_CSQ_CNT_PRIMARY(x) (((x) >> 0) & 0xFF) +#define C_000740_CSQ_CNT_PRIMARY 0xFFFFFF00 +#define S_000740_CSQ_CNT_INDIRECT(x) (((x) & 0xFF) << 8) +#define G_000740_CSQ_CNT_INDIRECT(x) (((x) >> 8) & 0xFF) +#define C_000740_CSQ_CNT_INDIRECT 0xFFFF00FF +#define S_000740_CSQ_MODE(x) (((x) & 0xF) << 28) +#define G_000740_CSQ_MODE(x) (((x) >> 28) & 0xF) +#define C_000740_CSQ_MODE 0x0FFFFFFF +#define R_000770_SCRATCH_UMSK 0x000770 +#define S_000770_SCRATCH_UMSK(x) (((x) & 0x3F) << 0) +#define G_000770_SCRATCH_UMSK(x) (((x) >> 0) & 0x3F) +#define C_000770_SCRATCH_UMSK 0xFFFFFFC0 +#define S_000770_SCRATCH_SWAP(x) (((x) & 0x3) << 16) +#define G_000770_SCRATCH_SWAP(x) (((x) >> 16) & 0x3) +#define C_000770_SCRATCH_SWAP 0xFFFCFFFF +#define R_000774_SCRATCH_ADDR 0x000774 +#define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5) +#define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF) +#define C_000774_SCRATCH_ADDR 0x0000001F +#define R_000E40_RBBM_STATUS 0x000E40 +#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) +#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) +#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 +#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) +#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) +#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF +#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) +#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) +#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF +#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) +#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) +#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF +#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) +#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) +#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF +#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) +#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) +#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF +#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) +#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) +#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF +#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) +#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) +#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF +#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) +#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) +#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF +#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) +#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) +#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF +#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) +#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) +#define C_000E40_E2_BUSY 0xFFFDFFFF +#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) +#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) +#define C_000E40_RB2D_BUSY 0xFFFBFFFF +#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) +#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) +#define C_000E40_RB3D_BUSY 0xFFF7FFFF +#define S_000E40_SE_BUSY(x) (((x) & 0x1) << 20) +#define G_000E40_SE_BUSY(x) (((x) >> 20) & 0x1) +#define C_000E40_SE_BUSY 0xFFEFFFFF +#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) +#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) +#define C_000E40_RE_BUSY 0xFFDFFFFF +#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) +#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) +#define C_000E40_TAM_BUSY 0xFFBFFFFF +#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) +#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) +#define C_000E40_TDM_BUSY 0xFF7FFFFF +#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) +#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) +#define C_000E40_PB_BUSY 0xFEFFFFFF +#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) +#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) +#define C_000E40_GUI_ACTIVE 0x7FFFFFFF + +#endif diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c new file mode 100644 index 000000000000..568c74bfba3d --- /dev/null +++ b/drivers/gpu/drm/radeon/r200.c @@ -0,0 +1,456 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#include "drmP.h" +#include "drm.h" +#include "radeon_drm.h" +#include "radeon_reg.h" +#include "radeon.h" + +#include "r200_reg_safe.h" + +#include "r100_track.h" + +static int r200_get_vtx_size_0(uint32_t vtx_fmt_0) +{ + int vtx_size, i; + vtx_size = 2; + + if (vtx_fmt_0 & R200_VTX_Z0) + vtx_size++; + if (vtx_fmt_0 & R200_VTX_W0) + vtx_size++; + /* blend weight */ + if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT)) + vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7; + if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL) + vtx_size++; + if (vtx_fmt_0 & R200_VTX_N0) + vtx_size += 3; + if (vtx_fmt_0 & R200_VTX_POINT_SIZE) + vtx_size++; + if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG) + vtx_size++; + if (vtx_fmt_0 & R200_VTX_SHININESS_0) + vtx_size++; + if (vtx_fmt_0 & R200_VTX_SHININESS_1) + vtx_size++; + for (i = 0; i < 8; i++) { + int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3; + switch (color_size) { + case 0: break; + case 1: vtx_size++; break; + case 2: vtx_size += 3; break; + case 3: vtx_size += 4; break; + } + } + if (vtx_fmt_0 & R200_VTX_XY1) + vtx_size += 2; + if (vtx_fmt_0 & R200_VTX_Z1) + vtx_size++; + if (vtx_fmt_0 & R200_VTX_W1) + vtx_size++; + if (vtx_fmt_0 & R200_VTX_N1) + vtx_size += 3; + return vtx_size; +} + +static int r200_get_vtx_size_1(uint32_t vtx_fmt_1) +{ + int vtx_size, i, tex_size; + vtx_size = 0; + for (i = 0; i < 6; i++) { + tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7; + if (tex_size > 4) + continue; + vtx_size += tex_size; + } + return vtx_size; +} + +int r200_packet0_check(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt, + unsigned idx, unsigned reg) +{ + struct radeon_cs_chunk *ib_chunk; + struct radeon_cs_reloc *reloc; + struct r100_cs_track *track; + volatile uint32_t *ib; + uint32_t tmp; + int r; + int i; + int face; + u32 tile_flags = 0; + + ib = p->ib->ptr; + ib_chunk = &p->chunks[p->chunk_ib_idx]; + track = (struct r100_cs_track *)p->track; + + switch (reg) { + case RADEON_CRTC_GUI_TRIG_VLINE: + r = r100_cs_packet_parse_vline(p); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + break; + /* FIXME: only allow PACKET3 blit? easier to check for out of + * range access */ + case RADEON_DST_PITCH_OFFSET: + case RADEON_SRC_PITCH_OFFSET: + r = r100_reloc_pitch_offset(p, pkt, idx, reg); + if (r) + return r; + break; + case RADEON_RB3D_DEPTHOFFSET: + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + track->zb.robj = reloc->robj; + track->zb.offset = ib_chunk->kdata[idx]; + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + break; + case RADEON_RB3D_COLOROFFSET: + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + track->cb[0].robj = reloc->robj; + track->cb[0].offset = ib_chunk->kdata[idx]; + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + break; + case R200_PP_TXOFFSET_0: + case R200_PP_TXOFFSET_1: + case R200_PP_TXOFFSET_2: + case R200_PP_TXOFFSET_3: + case R200_PP_TXOFFSET_4: + case R200_PP_TXOFFSET_5: + i = (reg - R200_PP_TXOFFSET_0) / 24; + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + track->textures[i].robj = reloc->robj; + break; + case R200_PP_CUBIC_OFFSET_F1_0: + case R200_PP_CUBIC_OFFSET_F2_0: + case R200_PP_CUBIC_OFFSET_F3_0: + case R200_PP_CUBIC_OFFSET_F4_0: + case R200_PP_CUBIC_OFFSET_F5_0: + case R200_PP_CUBIC_OFFSET_F1_1: + case R200_PP_CUBIC_OFFSET_F2_1: + case R200_PP_CUBIC_OFFSET_F3_1: + case R200_PP_CUBIC_OFFSET_F4_1: + case R200_PP_CUBIC_OFFSET_F5_1: + case R200_PP_CUBIC_OFFSET_F1_2: + case R200_PP_CUBIC_OFFSET_F2_2: + case R200_PP_CUBIC_OFFSET_F3_2: + case R200_PP_CUBIC_OFFSET_F4_2: + case R200_PP_CUBIC_OFFSET_F5_2: + case R200_PP_CUBIC_OFFSET_F1_3: + case R200_PP_CUBIC_OFFSET_F2_3: + case R200_PP_CUBIC_OFFSET_F3_3: + case R200_PP_CUBIC_OFFSET_F4_3: + case R200_PP_CUBIC_OFFSET_F5_3: + case R200_PP_CUBIC_OFFSET_F1_4: + case R200_PP_CUBIC_OFFSET_F2_4: + case R200_PP_CUBIC_OFFSET_F3_4: + case R200_PP_CUBIC_OFFSET_F4_4: + case R200_PP_CUBIC_OFFSET_F5_4: + case R200_PP_CUBIC_OFFSET_F1_5: + case R200_PP_CUBIC_OFFSET_F2_5: + case R200_PP_CUBIC_OFFSET_F3_5: + case R200_PP_CUBIC_OFFSET_F4_5: + case R200_PP_CUBIC_OFFSET_F5_5: + i = (reg - R200_PP_TXOFFSET_0) / 24; + face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4; + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + track->textures[i].cube_info[face - 1].offset = ib_chunk->kdata[idx]; + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + track->textures[i].cube_info[face - 1].robj = reloc->robj; + break; + case RADEON_RE_WIDTH_HEIGHT: + track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF); + break; + case RADEON_RB3D_COLORPITCH: + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + + if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) + tile_flags |= RADEON_COLOR_TILE_ENABLE; + if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) + tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; + + tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); + tmp |= tile_flags; + ib[idx] = tmp; + + track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK; + break; + case RADEON_RB3D_DEPTHPITCH: + track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK; + break; + case RADEON_RB3D_CNTL: + switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { + case 7: + case 8: + case 9: + case 11: + case 12: + track->cb[0].cpp = 1; + break; + case 3: + case 4: + case 15: + track->cb[0].cpp = 2; + break; + case 6: + track->cb[0].cpp = 4; + break; + default: + DRM_ERROR("Invalid color buffer format (%d) !\n", + ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); + return -EINVAL; + } + if (ib_chunk->kdata[idx] & RADEON_DEPTHXY_OFFSET_ENABLE) { + DRM_ERROR("No support for depth xy offset in kms\n"); + return -EINVAL; + } + + track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE); + break; + case RADEON_RB3D_ZSTENCILCNTL: + switch (ib_chunk->kdata[idx] & 0xf) { + case 0: + track->zb.cpp = 2; + break; + case 2: + case 3: + case 4: + case 5: + case 9: + case 11: + track->zb.cpp = 4; + break; + default: + break; + } + break; + case RADEON_RB3D_ZPASS_ADDR: + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + break; + case RADEON_PP_CNTL: + { + uint32_t temp = ib_chunk->kdata[idx] >> 4; + for (i = 0; i < track->num_texture; i++) + track->textures[i].enabled = !!(temp & (1 << i)); + } + break; + case RADEON_SE_VF_CNTL: + track->vap_vf_cntl = ib_chunk->kdata[idx]; + break; + case 0x210c: + /* VAP_VF_MAX_VTX_INDX */ + track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL; + break; + case R200_SE_VTX_FMT_0: + track->vtx_size = r200_get_vtx_size_0(ib_chunk->kdata[idx]); + break; + case R200_SE_VTX_FMT_1: + track->vtx_size += r200_get_vtx_size_1(ib_chunk->kdata[idx]); + break; + case R200_PP_TXSIZE_0: + case R200_PP_TXSIZE_1: + case R200_PP_TXSIZE_2: + case R200_PP_TXSIZE_3: + case R200_PP_TXSIZE_4: + case R200_PP_TXSIZE_5: + i = (reg - R200_PP_TXSIZE_0) / 32; + track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1; + track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; + break; + case R200_PP_TXPITCH_0: + case R200_PP_TXPITCH_1: + case R200_PP_TXPITCH_2: + case R200_PP_TXPITCH_3: + case R200_PP_TXPITCH_4: + case R200_PP_TXPITCH_5: + i = (reg - R200_PP_TXPITCH_0) / 32; + track->textures[i].pitch = ib_chunk->kdata[idx] + 32; + break; + case R200_PP_TXFILTER_0: + case R200_PP_TXFILTER_1: + case R200_PP_TXFILTER_2: + case R200_PP_TXFILTER_3: + case R200_PP_TXFILTER_4: + case R200_PP_TXFILTER_5: + i = (reg - R200_PP_TXFILTER_0) / 32; + track->textures[i].num_levels = ((ib_chunk->kdata[idx] & R200_MAX_MIP_LEVEL_MASK) + >> R200_MAX_MIP_LEVEL_SHIFT); + tmp = (ib_chunk->kdata[idx] >> 23) & 0x7; + if (tmp == 2 || tmp == 6) + track->textures[i].roundup_w = false; + tmp = (ib_chunk->kdata[idx] >> 27) & 0x7; + if (tmp == 2 || tmp == 6) + track->textures[i].roundup_h = false; + break; + case R200_PP_TXMULTI_CTL_0: + case R200_PP_TXMULTI_CTL_1: + case R200_PP_TXMULTI_CTL_2: + case R200_PP_TXMULTI_CTL_3: + case R200_PP_TXMULTI_CTL_4: + case R200_PP_TXMULTI_CTL_5: + i = (reg - R200_PP_TXMULTI_CTL_0) / 32; + break; + case R200_PP_TXFORMAT_X_0: + case R200_PP_TXFORMAT_X_1: + case R200_PP_TXFORMAT_X_2: + case R200_PP_TXFORMAT_X_3: + case R200_PP_TXFORMAT_X_4: + case R200_PP_TXFORMAT_X_5: + i = (reg - R200_PP_TXFORMAT_X_0) / 32; + track->textures[i].txdepth = ib_chunk->kdata[idx] & 0x7; + tmp = (ib_chunk->kdata[idx] >> 16) & 0x3; + /* 2D, 3D, CUBE */ + switch (tmp) { + case 0: + case 5: + case 6: + case 7: + track->textures[i].tex_coord_type = 0; + break; + case 1: + track->textures[i].tex_coord_type = 1; + break; + case 2: + track->textures[i].tex_coord_type = 2; + break; + } + break; + case R200_PP_TXFORMAT_0: + case R200_PP_TXFORMAT_1: + case R200_PP_TXFORMAT_2: + case R200_PP_TXFORMAT_3: + case R200_PP_TXFORMAT_4: + case R200_PP_TXFORMAT_5: + i = (reg - R200_PP_TXFORMAT_0) / 32; + if (ib_chunk->kdata[idx] & R200_TXFORMAT_NON_POWER2) { + track->textures[i].use_pitch = 1; + } else { + track->textures[i].use_pitch = 0; + track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); + track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); + } + switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) { + case R200_TXFORMAT_I8: + case R200_TXFORMAT_RGB332: + case R200_TXFORMAT_Y8: + track->textures[i].cpp = 1; + break; + case R200_TXFORMAT_DXT1: + case R200_TXFORMAT_AI88: + case R200_TXFORMAT_ARGB1555: + case R200_TXFORMAT_RGB565: + case R200_TXFORMAT_ARGB4444: + case R200_TXFORMAT_VYUY422: + case R200_TXFORMAT_YVYU422: + case R200_TXFORMAT_LDVDU655: + case R200_TXFORMAT_DVDU88: + case R200_TXFORMAT_AVYU4444: + track->textures[i].cpp = 2; + break; + case R200_TXFORMAT_ARGB8888: + case R200_TXFORMAT_RGBA8888: + case R200_TXFORMAT_ABGR8888: + case R200_TXFORMAT_BGR111110: + case R200_TXFORMAT_LDVDU8888: + case R200_TXFORMAT_DXT23: + case R200_TXFORMAT_DXT45: + track->textures[i].cpp = 4; + break; + } + track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf); + track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf); + break; + case R200_PP_CUBIC_FACES_0: + case R200_PP_CUBIC_FACES_1: + case R200_PP_CUBIC_FACES_2: + case R200_PP_CUBIC_FACES_3: + case R200_PP_CUBIC_FACES_4: + case R200_PP_CUBIC_FACES_5: + tmp = ib_chunk->kdata[idx]; + i = (reg - R200_PP_CUBIC_FACES_0) / 32; + for (face = 0; face < 4; face++) { + track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); + track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); + } + break; + default: + printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", + reg, idx); + return -EINVAL; + } + return 0; +} + +int r200_init(struct radeon_device *rdev) +{ + rdev->config.r100.reg_safe_bm = r200_reg_safe_bm; + rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm); + return 0; +} diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 051bca6e3a4f..bb151ecdf8fc 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c @@ -31,7 +31,10 @@ #include "radeon_reg.h" #include "radeon.h" #include "radeon_drm.h" -#include "radeon_share.h" +#include "r100_track.h" +#include "r300d.h" + +#include "r300_reg_safe.h" /* r300,r350,rv350,rv370,rv380 depends on : */ void r100_hdp_reset(struct radeon_device *rdev); @@ -39,7 +42,6 @@ int r100_cp_reset(struct radeon_device *rdev); int r100_rb2d_reset(struct radeon_device *rdev); int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); int r100_pci_gart_enable(struct radeon_device *rdev); -void r100_pci_gart_disable(struct radeon_device *rdev); void r100_mc_setup(struct radeon_device *rdev); void r100_mc_disable_clients(struct radeon_device *rdev); int r100_gui_wait_for_idle(struct radeon_device *rdev); @@ -47,14 +49,10 @@ int r100_cs_packet_parse(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt, unsigned idx); int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); -int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, - struct radeon_cs_reloc **cs_reloc); int r100_cs_parse_packet0(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt, const unsigned *auth, unsigned n, radeon_packet0_check_t check); -void r100_cs_dump_packet(struct radeon_cs_parser *p, - struct radeon_cs_packet *pkt); int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt, struct radeon_object *robj); @@ -87,26 +85,57 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) mb(); } -int rv370_pcie_gart_enable(struct radeon_device *rdev) +int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) +{ + void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; + + if (i < 0 || i > rdev->gart.num_gpu_pages) { + return -EINVAL; + } + addr = (lower_32_bits(addr) >> 8) | + ((upper_32_bits(addr) & 0xff) << 24) | + 0xc; + /* on x86 we want this to be CPU endian, on powerpc + * on powerpc without HW swappers, it'll get swapped on way + * into VRAM - so no need for cpu_to_le32 on VRAM tables */ + writel(addr, ((void __iomem *)ptr) + (i * 4)); + return 0; +} + +int rv370_pcie_gart_init(struct radeon_device *rdev) { - uint32_t table_addr; - uint32_t tmp; int r; + if (rdev->gart.table.vram.robj) { + WARN(1, "RV370 PCIE GART already initialized.\n"); + return 0; + } /* Initialize common gart structure */ r = radeon_gart_init(rdev); - if (r) { + if (r) return r; - } r = rv370_debugfs_pcie_gart_info_init(rdev); - if (r) { + if (r) DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); - } rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; - r = radeon_gart_table_vram_alloc(rdev); - if (r) { - return r; + rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; + rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; + return radeon_gart_table_vram_alloc(rdev); +} + +int rv370_pcie_gart_enable(struct radeon_device *rdev) +{ + uint32_t table_addr; + uint32_t tmp; + int r; + + if (rdev->gart.table.vram.robj == NULL) { + dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); + return -EINVAL; } + r = radeon_gart_table_vram_pin(rdev); + if (r) + return r; /* discard memory request outside of configured range */ tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); @@ -128,7 +157,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev) WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); rv370_pcie_gart_tlb_flush(rdev); DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n", - rdev->mc.gtt_size >> 20, table_addr); + (unsigned)(rdev->mc.gtt_size >> 20), table_addr); rdev->gart.ready = true; return 0; } @@ -146,45 +175,13 @@ void rv370_pcie_gart_disable(struct radeon_device *rdev) } } -int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) +void rv370_pcie_gart_fini(struct radeon_device *rdev) { - void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; - - if (i < 0 || i > rdev->gart.num_gpu_pages) { - return -EINVAL; - } - addr = (lower_32_bits(addr) >> 8) | - ((upper_32_bits(addr) & 0xff) << 24) | - 0xc; - /* on x86 we want this to be CPU endian, on powerpc - * on powerpc without HW swappers, it'll get swapped on way - * into VRAM - so no need for cpu_to_le32 on VRAM tables */ - writel(addr, ((void __iomem *)ptr) + (i * 4)); - return 0; -} - -int r300_gart_enable(struct radeon_device *rdev) -{ -#if __OS_HAS_AGP - if (rdev->flags & RADEON_IS_AGP) { - if (rdev->family > CHIP_RV350) { - rv370_pcie_gart_disable(rdev); - } else { - r100_pci_gart_disable(rdev); - } - return 0; - } -#endif - if (rdev->flags & RADEON_IS_PCIE) { - rdev->asic->gart_disable = &rv370_pcie_gart_disable; - rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; - rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; - return rv370_pcie_gart_enable(rdev); - } - return r100_pci_gart_enable(rdev); + rv370_pcie_gart_disable(rdev); + radeon_gart_table_vram_free(rdev); + radeon_gart_fini(rdev); } - /* * MC */ @@ -232,14 +229,6 @@ int r300_mc_init(struct radeon_device *rdev) void r300_mc_fini(struct radeon_device *rdev) { - if (rdev->flags & RADEON_IS_PCIE) { - rv370_pcie_gart_disable(rdev); - radeon_gart_table_vram_free(rdev); - } else { - r100_pci_gart_disable(rdev); - radeon_gart_table_ram_free(rdev); - } - radeon_gart_fini(rdev); } @@ -704,307 +693,13 @@ int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) /* * CS functions */ -struct r300_cs_track_cb { - struct radeon_object *robj; - unsigned pitch; - unsigned cpp; - unsigned offset; -}; - -struct r300_cs_track_array { - struct radeon_object *robj; - unsigned esize; -}; - -struct r300_cs_track_texture { - struct radeon_object *robj; - unsigned pitch; - unsigned width; - unsigned height; - unsigned num_levels; - unsigned cpp; - unsigned tex_coord_type; - unsigned txdepth; - unsigned width_11; - unsigned height_11; - bool use_pitch; - bool enabled; - bool roundup_w; - bool roundup_h; -}; - -struct r300_cs_track { - unsigned num_cb; - unsigned maxy; - unsigned vtx_size; - unsigned vap_vf_cntl; - unsigned immd_dwords; - unsigned num_arrays; - unsigned max_indx; - struct r300_cs_track_array arrays[11]; - struct r300_cs_track_cb cb[4]; - struct r300_cs_track_cb zb; - struct r300_cs_track_texture textures[16]; - bool z_enabled; -}; - -static inline void r300_cs_track_texture_print(struct r300_cs_track_texture *t) -{ - DRM_ERROR("pitch %d\n", t->pitch); - DRM_ERROR("width %d\n", t->width); - DRM_ERROR("height %d\n", t->height); - DRM_ERROR("num levels %d\n", t->num_levels); - DRM_ERROR("depth %d\n", t->txdepth); - DRM_ERROR("bpp %d\n", t->cpp); - DRM_ERROR("coordinate type %d\n", t->tex_coord_type); - DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); - DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); -} - -static inline int r300_cs_track_texture_check(struct radeon_device *rdev, - struct r300_cs_track *track) -{ - struct radeon_object *robj; - unsigned long size; - unsigned u, i, w, h; - - for (u = 0; u < 16; u++) { - if (!track->textures[u].enabled) - continue; - robj = track->textures[u].robj; - if (robj == NULL) { - DRM_ERROR("No texture bound to unit %u\n", u); - return -EINVAL; - } - size = 0; - for (i = 0; i <= track->textures[u].num_levels; i++) { - if (track->textures[u].use_pitch) { - w = track->textures[u].pitch / (1 << i); - } else { - w = track->textures[u].width / (1 << i); - if (rdev->family >= CHIP_RV515) - w |= track->textures[u].width_11; - if (track->textures[u].roundup_w) - w = roundup_pow_of_two(w); - } - h = track->textures[u].height / (1 << i); - if (rdev->family >= CHIP_RV515) - h |= track->textures[u].height_11; - if (track->textures[u].roundup_h) - h = roundup_pow_of_two(h); - size += w * h; - } - size *= track->textures[u].cpp; - switch (track->textures[u].tex_coord_type) { - case 0: - break; - case 1: - size *= (1 << track->textures[u].txdepth); - break; - case 2: - size *= 6; - break; - default: - DRM_ERROR("Invalid texture coordinate type %u for unit " - "%u\n", track->textures[u].tex_coord_type, u); - return -EINVAL; - } - if (size > radeon_object_size(robj)) { - DRM_ERROR("Texture of unit %u needs %lu bytes but is " - "%lu\n", u, size, radeon_object_size(robj)); - r300_cs_track_texture_print(&track->textures[u]); - return -EINVAL; - } - } - return 0; -} - -int r300_cs_track_check(struct radeon_device *rdev, struct r300_cs_track *track) -{ - unsigned i; - unsigned long size; - unsigned prim_walk; - unsigned nverts; - - for (i = 0; i < track->num_cb; i++) { - if (track->cb[i].robj == NULL) { - DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); - return -EINVAL; - } - size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; - size += track->cb[i].offset; - if (size > radeon_object_size(track->cb[i].robj)) { - DRM_ERROR("[drm] Buffer too small for color buffer %d " - "(need %lu have %lu) !\n", i, size, - radeon_object_size(track->cb[i].robj)); - DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", - i, track->cb[i].pitch, track->cb[i].cpp, - track->cb[i].offset, track->maxy); - return -EINVAL; - } - } - if (track->z_enabled) { - if (track->zb.robj == NULL) { - DRM_ERROR("[drm] No buffer for z buffer !\n"); - return -EINVAL; - } - size = track->zb.pitch * track->zb.cpp * track->maxy; - size += track->zb.offset; - if (size > radeon_object_size(track->zb.robj)) { - DRM_ERROR("[drm] Buffer too small for z buffer " - "(need %lu have %lu) !\n", size, - radeon_object_size(track->zb.robj)); - return -EINVAL; - } - } - prim_walk = (track->vap_vf_cntl >> 4) & 0x3; - nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; - switch (prim_walk) { - case 1: - for (i = 0; i < track->num_arrays; i++) { - size = track->arrays[i].esize * track->max_indx * 4; - if (track->arrays[i].robj == NULL) { - DRM_ERROR("(PW %u) Vertex array %u no buffer " - "bound\n", prim_walk, i); - return -EINVAL; - } - if (size > radeon_object_size(track->arrays[i].robj)) { - DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " - "have %lu dwords\n", prim_walk, i, - size >> 2, - radeon_object_size(track->arrays[i].robj) >> 2); - DRM_ERROR("Max indices %u\n", track->max_indx); - return -EINVAL; - } - } - break; - case 2: - for (i = 0; i < track->num_arrays; i++) { - size = track->arrays[i].esize * (nverts - 1) * 4; - if (track->arrays[i].robj == NULL) { - DRM_ERROR("(PW %u) Vertex array %u no buffer " - "bound\n", prim_walk, i); - return -EINVAL; - } - if (size > radeon_object_size(track->arrays[i].robj)) { - DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " - "have %lu dwords\n", prim_walk, i, size >> 2, - radeon_object_size(track->arrays[i].robj) >> 2); - return -EINVAL; - } - } - break; - case 3: - size = track->vtx_size * nverts; - if (size != track->immd_dwords) { - DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", - track->immd_dwords, size); - DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", - nverts, track->vtx_size); - return -EINVAL; - } - break; - default: - DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", - prim_walk); - return -EINVAL; - } - return r300_cs_track_texture_check(rdev, track); -} - -static inline void r300_cs_track_clear(struct r300_cs_track *track) -{ - unsigned i; - - track->num_cb = 4; - track->maxy = 4096; - for (i = 0; i < track->num_cb; i++) { - track->cb[i].robj = NULL; - track->cb[i].pitch = 8192; - track->cb[i].cpp = 16; - track->cb[i].offset = 0; - } - track->z_enabled = true; - track->zb.robj = NULL; - track->zb.pitch = 8192; - track->zb.cpp = 4; - track->zb.offset = 0; - track->vtx_size = 0x7F; - track->immd_dwords = 0xFFFFFFFFUL; - track->num_arrays = 11; - track->max_indx = 0x00FFFFFFUL; - for (i = 0; i < track->num_arrays; i++) { - track->arrays[i].robj = NULL; - track->arrays[i].esize = 0x7F; - } - for (i = 0; i < 16; i++) { - track->textures[i].pitch = 16536; - track->textures[i].width = 16536; - track->textures[i].height = 16536; - track->textures[i].width_11 = 1 << 11; - track->textures[i].height_11 = 1 << 11; - track->textures[i].num_levels = 12; - track->textures[i].txdepth = 16; - track->textures[i].cpp = 64; - track->textures[i].tex_coord_type = 1; - track->textures[i].robj = NULL; - /* CS IB emission code makes sure texture unit are disabled */ - track->textures[i].enabled = false; - track->textures[i].roundup_w = true; - track->textures[i].roundup_h = true; - } -} - -static const unsigned r300_reg_safe_bm[159] = { - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF, - 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000, - 0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFF, - 0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF, - 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, - 0x00000000, 0x0000C100, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x0003FC01, 0xFFFFFCF8, 0xFF800B19, -}; - static int r300_packet0_check(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt, unsigned idx, unsigned reg) { struct radeon_cs_chunk *ib_chunk; struct radeon_cs_reloc *reloc; - struct r300_cs_track *track; + struct r100_cs_track *track; volatile uint32_t *ib; uint32_t tmp, tile_flags = 0; unsigned i; @@ -1012,7 +707,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, ib = p->ib->ptr; ib_chunk = &p->chunks[p->chunk_ib_idx]; - track = (struct r300_cs_track*)p->track; + track = (struct r100_cs_track *)p->track; switch(reg) { case AVIVO_D1MODE_VLINE_START_END: case RADEON_CRTC_GUI_TRIG_VLINE: @@ -1026,28 +721,9 @@ static int r300_packet0_check(struct radeon_cs_parser *p, break; case RADEON_DST_PITCH_OFFSET: case RADEON_SRC_PITCH_OFFSET: - r = r100_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", - idx, reg); - r100_cs_dump_packet(p, pkt); + r = r100_reloc_pitch_offset(p, pkt, idx, reg); + if (r) return r; - } - tmp = ib_chunk->kdata[idx] & 0x003fffff; - tmp += (((u32)reloc->lobj.gpu_offset) >> 10); - - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) - tile_flags |= RADEON_DST_TILE_MACRO; - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { - if (reg == RADEON_SRC_PITCH_OFFSET) { - DRM_ERROR("Cannot src blit from microtiled surface\n"); - r100_cs_dump_packet(p, pkt); - return -EINVAL; - } - tile_flags |= RADEON_DST_TILE_MICRO; - } - tmp |= tile_flags; - ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; break; case R300_RB3D_COLOROFFSET0: case R300_RB3D_COLOROFFSET1: @@ -1256,42 +932,41 @@ static int r300_packet0_check(struct radeon_cs_parser *p, tmp = (ib_chunk->kdata[idx] >> 25) & 0x3; track->textures[i].tex_coord_type = tmp; switch ((ib_chunk->kdata[idx] & 0x1F)) { - case 0: - case 2: - case 5: - case 18: - case 20: - case 21: + case R300_TX_FORMAT_X8: + case R300_TX_FORMAT_Y4X4: + case R300_TX_FORMAT_Z3Y3X2: track->textures[i].cpp = 1; break; - case 1: - case 3: - case 6: - case 7: - case 10: - case 11: - case 19: - case 22: - case 24: + case R300_TX_FORMAT_X16: + case R300_TX_FORMAT_Y8X8: + case R300_TX_FORMAT_Z5Y6X5: + case R300_TX_FORMAT_Z6Y5X5: + case R300_TX_FORMAT_W4Z4Y4X4: + case R300_TX_FORMAT_W1Z5Y5X5: + case R300_TX_FORMAT_DXT1: + case R300_TX_FORMAT_D3DMFT_CxV8U8: + case R300_TX_FORMAT_B8G8_B8G8: + case R300_TX_FORMAT_G8R8_G8B8: track->textures[i].cpp = 2; break; - case 4: - case 8: - case 9: - case 12: - case 13: - case 23: - case 25: - case 27: - case 30: + case R300_TX_FORMAT_Y16X16: + case R300_TX_FORMAT_Z11Y11X10: + case R300_TX_FORMAT_Z10Y11X11: + case R300_TX_FORMAT_W8Z8Y8X8: + case R300_TX_FORMAT_W2Z10Y10X10: + case 0x17: + case R300_TX_FORMAT_FL_I32: + case 0x1e: + case R300_TX_FORMAT_DXT3: + case R300_TX_FORMAT_DXT5: track->textures[i].cpp = 4; break; - case 14: - case 26: - case 28: + case R300_TX_FORMAT_W16Z16Y16X16: + case R300_TX_FORMAT_FL_R16G16B16A16: + case R300_TX_FORMAT_FL_I32A32: track->textures[i].cpp = 8; break; - case 29: + case R300_TX_FORMAT_FL_R32G32B32A32: track->textures[i].cpp = 16; break; default: @@ -1319,11 +994,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p, case 0x443C: /* TX_FILTER0_[0-15] */ i = (reg - 0x4400) >> 2; - tmp = ib_chunk->kdata[idx] & 0x7;; + tmp = ib_chunk->kdata[idx] & 0x7; if (tmp == 2 || tmp == 4 || tmp == 6) { track->textures[i].roundup_w = false; } - tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;; + tmp = (ib_chunk->kdata[idx] >> 3) & 0x7; if (tmp == 2 || tmp == 4 || tmp == 6) { track->textures[i].roundup_h = false; } @@ -1411,8 +1086,9 @@ static int r300_packet3_check(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt) { struct radeon_cs_chunk *ib_chunk; + struct radeon_cs_reloc *reloc; - struct r300_cs_track *track; + struct r100_cs_track *track; volatile uint32_t *ib; unsigned idx; unsigned i, c; @@ -1421,7 +1097,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p, ib = p->ib->ptr; ib_chunk = &p->chunks[p->chunk_ib_idx]; idx = pkt->idx + 1; - track = (struct r300_cs_track*)p->track; + track = (struct r100_cs_track *)p->track; switch(pkt->opcode) { case PACKET3_3D_LOAD_VBPNTR: c = ib_chunk->kdata[idx++] & 0x1F; @@ -1488,7 +1164,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p, } track->vap_vf_cntl = ib_chunk->kdata[idx+1]; track->immd_dwords = pkt->count - 1; - r = r300_cs_track_check(p->rdev, track); + r = r100_cs_track_check(p->rdev, track); if (r) { return r; } @@ -1503,35 +1179,35 @@ static int r300_packet3_check(struct radeon_cs_parser *p, } track->vap_vf_cntl = ib_chunk->kdata[idx]; track->immd_dwords = pkt->count; - r = r300_cs_track_check(p->rdev, track); + r = r100_cs_track_check(p->rdev, track); if (r) { return r; } break; case PACKET3_3D_DRAW_VBUF: track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; - r = r300_cs_track_check(p->rdev, track); + r = r100_cs_track_check(p->rdev, track); if (r) { return r; } break; case PACKET3_3D_DRAW_VBUF_2: track->vap_vf_cntl = ib_chunk->kdata[idx]; - r = r300_cs_track_check(p->rdev, track); + r = r100_cs_track_check(p->rdev, track); if (r) { return r; } break; case PACKET3_3D_DRAW_INDX: track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; - r = r300_cs_track_check(p->rdev, track); + r = r100_cs_track_check(p->rdev, track); if (r) { return r; } break; case PACKET3_3D_DRAW_INDX_2: track->vap_vf_cntl = ib_chunk->kdata[idx]; - r = r300_cs_track_check(p->rdev, track); + r = r100_cs_track_check(p->rdev, track); if (r) { return r; } @@ -1548,11 +1224,12 @@ static int r300_packet3_check(struct radeon_cs_parser *p, int r300_cs_parse(struct radeon_cs_parser *p) { struct radeon_cs_packet pkt; - struct r300_cs_track track; + struct r100_cs_track *track; int r; - r300_cs_track_clear(&track); - p->track = &track; + track = kzalloc(sizeof(*track), GFP_KERNEL); + r100_cs_track_clear(p->rdev, track); + p->track = track; do { r = r100_cs_packet_parse(p, &pkt, p->idx); if (r) { @@ -1582,9 +1259,48 @@ int r300_cs_parse(struct radeon_cs_parser *p) return 0; } -int r300_init(struct radeon_device *rdev) +void r300_set_reg_safe(struct radeon_device *rdev) { rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); +} + +int r300_init(struct radeon_device *rdev) +{ + r300_set_reg_safe(rdev); return 0; } + +void r300_mc_program(struct radeon_device *rdev) +{ + struct r100_mc_save save; + int r; + + r = r100_debugfs_mc_info_init(rdev); + if (r) { + dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); + } + + /* Stops all mc clients */ + r100_mc_stop(rdev, &save); + if (rdev->flags & RADEON_IS_AGP) { + WREG32(R_00014C_MC_AGP_LOCATION, + S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | + S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); + WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); + WREG32(R_00015C_AGP_BASE_2, + upper_32_bits(rdev->mc.agp_base) & 0xff); + } else { + WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); + WREG32(R_000170_AGP_BASE, 0); + WREG32(R_00015C_AGP_BASE_2, 0); + } + /* Wait for mc idle */ + if (r300_mc_wait_for_idle(rdev)) + DRM_INFO("Failed to wait MC idle before programming MC.\n"); + /* Program MC, should be a 32bits limited address space */ + WREG32(R_000148_MC_FB_LOCATION, + S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | + S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); + r100_mc_resume(rdev, &save); +} diff --git a/drivers/gpu/drm/radeon/r300.h b/drivers/gpu/drm/radeon/r300.h deleted file mode 100644 index 8486b4da9d69..000000000000 --- a/drivers/gpu/drm/radeon/r300.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright 2008 Advanced Micro Devices, Inc. - * Copyright 2008 Red Hat Inc. - * Copyright 2009 Jerome Glisse. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Dave Airlie - * Alex Deucher - * Jerome Glisse - */ -#ifndef R300_H -#define R300_H - -struct r300_asic { - const unsigned *reg_safe_bm; - unsigned reg_safe_bm_size; -}; - -#endif diff --git a/drivers/gpu/drm/radeon/r300d.h b/drivers/gpu/drm/radeon/r300d.h new file mode 100644 index 000000000000..d4fa3eb1074f --- /dev/null +++ b/drivers/gpu/drm/radeon/r300d.h @@ -0,0 +1,101 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef __R300D_H__ +#define __R300D_H__ + +#define CP_PACKET0 0x00000000 +#define PACKET0_BASE_INDEX_SHIFT 0 +#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) +#define PACKET0_COUNT_SHIFT 16 +#define PACKET0_COUNT_MASK (0x3fff << 16) +#define CP_PACKET1 0x40000000 +#define CP_PACKET2 0x80000000 +#define PACKET2_PAD_SHIFT 0 +#define PACKET2_PAD_MASK (0x3fffffff << 0) +#define CP_PACKET3 0xC0000000 +#define PACKET3_IT_OPCODE_SHIFT 8 +#define PACKET3_IT_OPCODE_MASK (0xff << 8) +#define PACKET3_COUNT_SHIFT 16 +#define PACKET3_COUNT_MASK (0x3fff << 16) +/* PACKET3 op code */ +#define PACKET3_NOP 0x10 +#define PACKET3_3D_DRAW_VBUF 0x28 +#define PACKET3_3D_DRAW_IMMD 0x29 +#define PACKET3_3D_DRAW_INDX 0x2A +#define PACKET3_3D_LOAD_VBPNTR 0x2F +#define PACKET3_INDX_BUFFER 0x33 +#define PACKET3_3D_DRAW_VBUF_2 0x34 +#define PACKET3_3D_DRAW_IMMD_2 0x35 +#define PACKET3_3D_DRAW_INDX_2 0x36 +#define PACKET3_BITBLT_MULTI 0x9B + +#define PACKET0(reg, n) (CP_PACKET0 | \ + REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ + REG_SET(PACKET0_COUNT, (n))) +#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) +#define PACKET3(op, n) (CP_PACKET3 | \ + REG_SET(PACKET3_IT_OPCODE, (op)) | \ + REG_SET(PACKET3_COUNT, (n))) + +#define PACKET_TYPE0 0 +#define PACKET_TYPE1 1 +#define PACKET_TYPE2 2 +#define PACKET_TYPE3 3 + +#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) +#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) +#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) +#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) +#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) + +/* Registers */ +#define R_000148_MC_FB_LOCATION 0x000148 +#define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) +#define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) +#define C_000148_MC_FB_START 0xFFFF0000 +#define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) +#define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) +#define C_000148_MC_FB_TOP 0x0000FFFF +#define R_00014C_MC_AGP_LOCATION 0x00014C +#define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) +#define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) +#define C_00014C_MC_AGP_START 0xFFFF0000 +#define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) +#define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) +#define C_00014C_MC_AGP_TOP 0x0000FFFF +#define R_00015C_AGP_BASE_2 0x00015C +#define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) +#define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) +#define C_00015C_AGP_BASE_ADDR_2 0xFFFFFFF0 +#define R_000170_AGP_BASE 0x000170 +#define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) +#define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_000170_AGP_BASE_ADDR 0x00000000 + + +#endif diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c index 97426a6f370f..49a2fdc57d27 100644 --- a/drivers/gpu/drm/radeon/r420.c +++ b/drivers/gpu/drm/radeon/r420.c @@ -29,47 +29,13 @@ #include "drmP.h" #include "radeon_reg.h" #include "radeon.h" +#include "atom.h" +#include "r420d.h" -/* r420,r423,rv410 depends on : */ -void r100_pci_gart_disable(struct radeon_device *rdev); -void r100_hdp_reset(struct radeon_device *rdev); -void r100_mc_setup(struct radeon_device *rdev); -int r100_gui_wait_for_idle(struct radeon_device *rdev); -void r100_mc_disable_clients(struct radeon_device *rdev); -void r300_vram_info(struct radeon_device *rdev); -int r300_mc_wait_for_idle(struct radeon_device *rdev); -int rv370_pcie_gart_enable(struct radeon_device *rdev); -void rv370_pcie_gart_disable(struct radeon_device *rdev); - -/* This files gather functions specifics to : - * r420,r423,rv410 - * - * Some of these functions might be used by newer ASICs. - */ -void r420_gpu_init(struct radeon_device *rdev); -int r420_debugfs_pipes_info_init(struct radeon_device *rdev); - - -/* - * MC - */ int r420_mc_init(struct radeon_device *rdev) { int r; - if (r100_debugfs_rbbm_init(rdev)) { - DRM_ERROR("Failed to register debugfs file for RBBM !\n"); - } - if (r420_debugfs_pipes_info_init(rdev)) { - DRM_ERROR("Failed to register debugfs file for pipes !\n"); - } - - r420_gpu_init(rdev); - r100_pci_gart_disable(rdev); - if (rdev->flags & RADEON_IS_PCIE) { - rv370_pcie_gart_disable(rdev); - } - /* Setup GPU memory space */ rdev->mc.vram_location = 0xFFFFFFFFUL; rdev->mc.gtt_location = 0xFFFFFFFFUL; @@ -87,33 +53,9 @@ int r420_mc_init(struct radeon_device *rdev) if (r) { return r; } - - /* Program GPU memory space */ - r100_mc_disable_clients(rdev); - if (r300_mc_wait_for_idle(rdev)) { - printk(KERN_WARNING "Failed to wait MC idle while " - "programming pipes. Bad things might happen.\n"); - } - r100_mc_setup(rdev); return 0; } -void r420_mc_fini(struct radeon_device *rdev) -{ - rv370_pcie_gart_disable(rdev); - radeon_gart_table_vram_free(rdev); - radeon_gart_fini(rdev); -} - - -/* - * Global GPU functions - */ -void r420_errata(struct radeon_device *rdev) -{ - rdev->pll_errata = 0; -} - void r420_pipes_init(struct radeon_device *rdev) { unsigned tmp; @@ -122,6 +64,11 @@ void r420_pipes_init(struct radeon_device *rdev) /* GA_ENHANCE workaround TCL deadlock issue */ WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)); + /* add idle wait as per freedesktop.org bug 24041 */ + if (r100_gui_wait_for_idle(rdev)) { + printk(KERN_WARNING "Failed to wait GUI idle while " + "programming pipes. Bad things might happen.\n"); + } /* get max number of pipes */ gb_pipe_select = RREG32(0x402C); num_pipes = ((gb_pipe_select >> 12) & 3) + 1; @@ -179,25 +126,239 @@ void r420_pipes_init(struct radeon_device *rdev) rdev->num_gb_pipes, rdev->num_z_pipes); } -void r420_gpu_init(struct radeon_device *rdev) +u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) +{ + u32 r; + + WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); + r = RREG32(R_0001FC_MC_IND_DATA); + return r; +} + +void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) +{ + WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | + S_0001F8_MC_IND_WR_EN(1)); + WREG32(R_0001FC_MC_IND_DATA, v); +} + +static void r420_debugfs(struct radeon_device *rdev) +{ + if (r100_debugfs_rbbm_init(rdev)) { + DRM_ERROR("Failed to register debugfs file for RBBM !\n"); + } + if (r420_debugfs_pipes_info_init(rdev)) { + DRM_ERROR("Failed to register debugfs file for pipes !\n"); + } +} + +static void r420_clock_resume(struct radeon_device *rdev) +{ + u32 sclk_cntl; + sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); + sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); + if (rdev->family == CHIP_R420) + sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); + WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); +} + +static int r420_startup(struct radeon_device *rdev) { - r100_hdp_reset(rdev); + int r; + + r300_mc_program(rdev); + /* Initialize GART (initialize after TTM so we can allocate + * memory through TTM but finalize after TTM) */ + if (rdev->flags & RADEON_IS_PCIE) { + r = rv370_pcie_gart_enable(rdev); + if (r) + return r; + } + if (rdev->flags & RADEON_IS_PCI) { + r = r100_pci_gart_enable(rdev); + if (r) + return r; + } r420_pipes_init(rdev); - if (r300_mc_wait_for_idle(rdev)) { - printk(KERN_WARNING "Failed to wait MC idle while " - "programming pipes. Bad things might happen.\n"); + /* Enable IRQ */ + rdev->irq.sw_int = true; + r100_irq_set(rdev); + /* 1M ring buffer */ + r = r100_cp_init(rdev, 1024 * 1024); + if (r) { + dev_err(rdev->dev, "failled initializing CP (%d).\n", r); + return r; + } + r = r100_wb_init(rdev); + if (r) { + dev_err(rdev->dev, "failled initializing WB (%d).\n", r); + } + r = r100_ib_init(rdev); + if (r) { + dev_err(rdev->dev, "failled initializing IB (%d).\n", r); + return r; } + return 0; } +int r420_resume(struct radeon_device *rdev) +{ + /* Make sur GART are not working */ + if (rdev->flags & RADEON_IS_PCIE) + rv370_pcie_gart_disable(rdev); + if (rdev->flags & RADEON_IS_PCI) + r100_pci_gart_disable(rdev); + /* Resume clock before doing reset */ + r420_clock_resume(rdev); + /* Reset gpu before posting otherwise ATOM will enter infinite loop */ + if (radeon_gpu_reset(rdev)) { + dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", + RREG32(R_000E40_RBBM_STATUS), + RREG32(R_0007C0_CP_STAT)); + } + /* check if cards are posted or not */ + if (rdev->is_atom_bios) { + atom_asic_init(rdev->mode_info.atom_context); + } else { + radeon_combios_asic_init(rdev->ddev); + } + /* Resume clock after posting */ + r420_clock_resume(rdev); -/* - * r420,r423,rv410 VRAM info - */ -void r420_vram_info(struct radeon_device *rdev) + return r420_startup(rdev); +} + +int r420_suspend(struct radeon_device *rdev) { - r300_vram_info(rdev); + r100_cp_disable(rdev); + r100_wb_disable(rdev); + r100_irq_disable(rdev); + if (rdev->flags & RADEON_IS_PCIE) + rv370_pcie_gart_disable(rdev); + if (rdev->flags & RADEON_IS_PCI) + r100_pci_gart_disable(rdev); + return 0; +} + +void r420_fini(struct radeon_device *rdev) +{ + r100_cp_fini(rdev); + r100_wb_fini(rdev); + r100_ib_fini(rdev); + radeon_gem_fini(rdev); + if (rdev->flags & RADEON_IS_PCIE) + rv370_pcie_gart_fini(rdev); + if (rdev->flags & RADEON_IS_PCI) + r100_pci_gart_fini(rdev); + radeon_agp_fini(rdev); + radeon_irq_kms_fini(rdev); + radeon_fence_driver_fini(rdev); + radeon_object_fini(rdev); + if (rdev->is_atom_bios) { + radeon_atombios_fini(rdev); + } else { + radeon_combios_fini(rdev); + } + kfree(rdev->bios); + rdev->bios = NULL; } +int r420_init(struct radeon_device *rdev) +{ + int r; + + rdev->new_init_path = true; + /* Initialize scratch registers */ + radeon_scratch_init(rdev); + /* Initialize surface registers */ + radeon_surface_init(rdev); + /* TODO: disable VGA need to use VGA request */ + /* BIOS*/ + if (!radeon_get_bios(rdev)) { + if (ASIC_IS_AVIVO(rdev)) + return -EINVAL; + } + if (rdev->is_atom_bios) { + r = radeon_atombios_init(rdev); + if (r) { + return r; + } + } else { + r = radeon_combios_init(rdev); + if (r) { + return r; + } + } + /* Reset gpu before posting otherwise ATOM will enter infinite loop */ + if (radeon_gpu_reset(rdev)) { + dev_warn(rdev->dev, + "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", + RREG32(R_000E40_RBBM_STATUS), + RREG32(R_0007C0_CP_STAT)); + } + /* check if cards are posted or not */ + if (!radeon_card_posted(rdev) && rdev->bios) { + DRM_INFO("GPU not posted. posting now...\n"); + if (rdev->is_atom_bios) { + atom_asic_init(rdev->mode_info.atom_context); + } else { + radeon_combios_asic_init(rdev->ddev); + } + } + /* Initialize clocks */ + radeon_get_clock_info(rdev->ddev); + /* Get vram informations */ + r300_vram_info(rdev); + /* Initialize memory controller (also test AGP) */ + r = r420_mc_init(rdev); + if (r) { + return r; + } + r420_debugfs(rdev); + /* Fence driver */ + r = radeon_fence_driver_init(rdev); + if (r) { + return r; + } + r = radeon_irq_kms_init(rdev); + if (r) { + return r; + } + /* Memory manager */ + r = radeon_object_init(rdev); + if (r) { + return r; + } + if (rdev->flags & RADEON_IS_PCIE) { + r = rv370_pcie_gart_init(rdev); + if (r) + return r; + } + if (rdev->flags & RADEON_IS_PCI) { + r = r100_pci_gart_init(rdev); + if (r) + return r; + } + r300_set_reg_safe(rdev); + rdev->accel_working = true; + r = r420_startup(rdev); + if (r) { + /* Somethings want wront with the accel init stop accel */ + dev_err(rdev->dev, "Disabling GPU acceleration\n"); + r420_suspend(rdev); + r100_cp_fini(rdev); + r100_wb_fini(rdev); + r100_ib_fini(rdev); + if (rdev->flags & RADEON_IS_PCIE) + rv370_pcie_gart_fini(rdev); + if (rdev->flags & RADEON_IS_PCI) + r100_pci_gart_fini(rdev); + radeon_agp_fini(rdev); + radeon_irq_kms_fini(rdev); + rdev->accel_working = false; + } + return 0; +} /* * Debugfs info diff --git a/drivers/gpu/drm/radeon/r420d.h b/drivers/gpu/drm/radeon/r420d.h new file mode 100644 index 000000000000..a48a7db1e2aa --- /dev/null +++ b/drivers/gpu/drm/radeon/r420d.h @@ -0,0 +1,249 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef R420D_H +#define R420D_H + +#define R_0001F8_MC_IND_INDEX 0x0001F8 +#define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) +#define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) +#define C_0001F8_MC_IND_ADDR 0xFFFFFF80 +#define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) +#define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) +#define C_0001F8_MC_IND_WR_EN 0xFFFFFEFF +#define R_0001FC_MC_IND_DATA 0x0001FC +#define S_0001FC_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) +#define G_0001FC_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_0001FC_MC_IND_DATA 0x00000000 +#define R_0007C0_CP_STAT 0x0007C0 +#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) +#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) +#define C_0007C0_MRU_BUSY 0xFFFFFFFE +#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) +#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) +#define C_0007C0_MWU_BUSY 0xFFFFFFFD +#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) +#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) +#define C_0007C0_RSIU_BUSY 0xFFFFFFFB +#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) +#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) +#define C_0007C0_RCIU_BUSY 0xFFFFFFF7 +#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) +#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) +#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF +#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) +#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) +#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF +#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) +#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) +#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF +#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) +#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) +#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF +#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) +#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) +#define C_0007C0_CSI_BUSY 0xFFFFDFFF +#define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) +#define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) +#define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF +#define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) +#define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) +#define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF +#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) +#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) +#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF +#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) +#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) +#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF +#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) +#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) +#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF +#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) +#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) +#define C_0007C0_CP_BUSY 0x7FFFFFFF +#define R_000E40_RBBM_STATUS 0x000E40 +#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) +#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) +#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 +#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) +#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) +#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF +#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) +#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) +#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF +#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) +#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) +#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF +#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) +#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) +#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF +#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) +#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) +#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF +#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) +#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) +#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF +#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) +#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) +#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF +#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) +#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) +#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF +#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) +#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) +#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF +#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) +#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) +#define C_000E40_E2_BUSY 0xFFFDFFFF +#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) +#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) +#define C_000E40_RB2D_BUSY 0xFFFBFFFF +#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) +#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) +#define C_000E40_RB3D_BUSY 0xFFF7FFFF +#define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) +#define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) +#define C_000E40_VAP_BUSY 0xFFEFFFFF +#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) +#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) +#define C_000E40_RE_BUSY 0xFFDFFFFF +#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) +#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) +#define C_000E40_TAM_BUSY 0xFFBFFFFF +#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) +#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) +#define C_000E40_TDM_BUSY 0xFF7FFFFF +#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) +#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) +#define C_000E40_PB_BUSY 0xFEFFFFFF +#define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) +#define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) +#define C_000E40_TIM_BUSY 0xFDFFFFFF +#define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) +#define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) +#define C_000E40_GA_BUSY 0xFBFFFFFF +#define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) +#define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) +#define C_000E40_CBA2D_BUSY 0xF7FFFFFF +#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) +#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) +#define C_000E40_GUI_ACTIVE 0x7FFFFFFF + +/* CLK registers */ +#define R_00000D_SCLK_CNTL 0x00000D +#define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) +#define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) +#define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8 +#define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) +#define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) +#define C_00000D_CP_MAX_DYN_STOP_LAT 0xFFFFFFF7 +#define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) +#define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) +#define C_00000D_HDP_MAX_DYN_STOP_LAT 0xFFFFFFEF +#define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) +#define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) +#define C_00000D_TV_MAX_DYN_STOP_LAT 0xFFFFFFDF +#define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) +#define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) +#define C_00000D_E2_MAX_DYN_STOP_LAT 0xFFFFFFBF +#define S_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 7) +#define G_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) >> 7) & 0x1) +#define C_00000D_SE_MAX_DYN_STOP_LAT 0xFFFFFF7F +#define S_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 8) +#define G_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 8) & 0x1) +#define C_00000D_IDCT_MAX_DYN_STOP_LAT 0xFFFFFEFF +#define S_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 9) +#define G_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) >> 9) & 0x1) +#define C_00000D_VIP_MAX_DYN_STOP_LAT 0xFFFFFDFF +#define S_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 10) +#define G_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) >> 10) & 0x1) +#define C_00000D_RE_MAX_DYN_STOP_LAT 0xFFFFFBFF +#define S_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 11) +#define G_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) >> 11) & 0x1) +#define C_00000D_PB_MAX_DYN_STOP_LAT 0xFFFFF7FF +#define S_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 12) +#define G_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) >> 12) & 0x1) +#define C_00000D_TAM_MAX_DYN_STOP_LAT 0xFFFFEFFF +#define S_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 13) +#define G_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) >> 13) & 0x1) +#define C_00000D_TDM_MAX_DYN_STOP_LAT 0xFFFFDFFF +#define S_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 14) +#define G_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) >> 14) & 0x1) +#define C_00000D_RB_MAX_DYN_STOP_LAT 0xFFFFBFFF +#define S_00000D_FORCE_DISP2(x) (((x) & 0x1) << 15) +#define G_00000D_FORCE_DISP2(x) (((x) >> 15) & 0x1) +#define C_00000D_FORCE_DISP2 0xFFFF7FFF +#define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16) +#define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1) +#define C_00000D_FORCE_CP 0xFFFEFFFF +#define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17) +#define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1) +#define C_00000D_FORCE_HDP 0xFFFDFFFF +#define S_00000D_FORCE_DISP1(x) (((x) & 0x1) << 18) +#define G_00000D_FORCE_DISP1(x) (((x) >> 18) & 0x1) +#define C_00000D_FORCE_DISP1 0xFFFBFFFF +#define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19) +#define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1) +#define C_00000D_FORCE_TOP 0xFFF7FFFF +#define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20) +#define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1) +#define C_00000D_FORCE_E2 0xFFEFFFFF +#define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21) +#define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1) +#define C_00000D_FORCE_SE 0xFFDFFFFF +#define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22) +#define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1) +#define C_00000D_FORCE_IDCT 0xFFBFFFFF +#define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23) +#define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1) +#define C_00000D_FORCE_VIP 0xFF7FFFFF +#define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24) +#define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1) +#define C_00000D_FORCE_RE 0xFEFFFFFF +#define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25) +#define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1) +#define C_00000D_FORCE_PB 0xFDFFFFFF +#define S_00000D_FORCE_PX(x) (((x) & 0x1) << 26) +#define G_00000D_FORCE_PX(x) (((x) >> 26) & 0x1) +#define C_00000D_FORCE_PX 0xFBFFFFFF +#define S_00000D_FORCE_TX(x) (((x) & 0x1) << 27) +#define G_00000D_FORCE_TX(x) (((x) >> 27) & 0x1) +#define C_00000D_FORCE_TX 0xF7FFFFFF +#define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28) +#define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1) +#define C_00000D_FORCE_RB 0xEFFFFFFF +#define S_00000D_FORCE_TV_SCLK(x) (((x) & 0x1) << 29) +#define G_00000D_FORCE_TV_SCLK(x) (((x) >> 29) & 0x1) +#define C_00000D_FORCE_TV_SCLK 0xDFFFFFFF +#define S_00000D_FORCE_SUBPIC(x) (((x) & 0x1) << 30) +#define G_00000D_FORCE_SUBPIC(x) (((x) >> 30) & 0x1) +#define C_00000D_FORCE_SUBPIC 0xBFFFFFFF +#define S_00000D_FORCE_OV0(x) (((x) & 0x1) << 31) +#define G_00000D_FORCE_OV0(x) (((x) >> 31) & 0x1) +#define C_00000D_FORCE_OV0 0x7FFFFFFF + +#endif diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c index ebd6b0f7bdff..d4b0b9d2e39b 100644 --- a/drivers/gpu/drm/radeon/r520.c +++ b/drivers/gpu/drm/radeon/r520.c @@ -28,12 +28,9 @@ #include "drmP.h" #include "radeon_reg.h" #include "radeon.h" -#include "radeon_share.h" /* r520,rv530,rv560,rv570,r580 depends on : */ void r100_hdp_reset(struct radeon_device *rdev); -int rv370_pcie_gart_enable(struct radeon_device *rdev); -void rv370_pcie_gart_disable(struct radeon_device *rdev); void r420_pipes_init(struct radeon_device *rdev); void rs600_mc_disable_clients(struct radeon_device *rdev); void rs600_disable_vga(struct radeon_device *rdev); @@ -119,9 +116,6 @@ int r520_mc_init(struct radeon_device *rdev) void r520_mc_fini(struct radeon_device *rdev) { - rv370_pcie_gart_disable(rdev); - radeon_gart_table_vram_free(rdev); - radeon_gart_fini(rdev); } diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 538cd907df69..eab31c1d6df1 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -25,12 +25,45 @@ * Alex Deucher * Jerome Glisse */ +#include +#include +#include #include "drmP.h" -#include "radeon_reg.h" +#include "radeon_drm.h" #include "radeon.h" +#include "radeon_mode.h" +#include "r600d.h" +#include "avivod.h" +#include "atom.h" -/* r600,rv610,rv630,rv620,rv635,rv670 depends on : */ -void rs600_mc_disable_clients(struct radeon_device *rdev); +#define PFP_UCODE_SIZE 576 +#define PM4_UCODE_SIZE 1792 +#define R700_PFP_UCODE_SIZE 848 +#define R700_PM4_UCODE_SIZE 1360 + +/* Firmware Names */ +MODULE_FIRMWARE("radeon/R600_pfp.bin"); +MODULE_FIRMWARE("radeon/R600_me.bin"); +MODULE_FIRMWARE("radeon/RV610_pfp.bin"); +MODULE_FIRMWARE("radeon/RV610_me.bin"); +MODULE_FIRMWARE("radeon/RV630_pfp.bin"); +MODULE_FIRMWARE("radeon/RV630_me.bin"); +MODULE_FIRMWARE("radeon/RV620_pfp.bin"); +MODULE_FIRMWARE("radeon/RV620_me.bin"); +MODULE_FIRMWARE("radeon/RV635_pfp.bin"); +MODULE_FIRMWARE("radeon/RV635_me.bin"); +MODULE_FIRMWARE("radeon/RV670_pfp.bin"); +MODULE_FIRMWARE("radeon/RV670_me.bin"); +MODULE_FIRMWARE("radeon/RS780_pfp.bin"); +MODULE_FIRMWARE("radeon/RS780_me.bin"); +MODULE_FIRMWARE("radeon/RV770_pfp.bin"); +MODULE_FIRMWARE("radeon/RV770_me.bin"); +MODULE_FIRMWARE("radeon/RV730_pfp.bin"); +MODULE_FIRMWARE("radeon/RV730_me.bin"); +MODULE_FIRMWARE("radeon/RV710_pfp.bin"); +MODULE_FIRMWARE("radeon/RV710_me.bin"); + +int r600_debugfs_mc_info_init(struct radeon_device *rdev); /* This files gather functions specifics to: * r600,rv610,rv630,rv620,rv635,rv670 @@ -39,87 +72,293 @@ void rs600_mc_disable_clients(struct radeon_device *rdev); */ int r600_mc_wait_for_idle(struct radeon_device *rdev); void r600_gpu_init(struct radeon_device *rdev); +void r600_fini(struct radeon_device *rdev); /* - * MC + * R600 PCIE GART */ -int r600_mc_init(struct radeon_device *rdev) +int r600_gart_clear_page(struct radeon_device *rdev, int i) { - uint32_t tmp; + void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; + u64 pte; - r600_gpu_init(rdev); + if (i < 0 || i > rdev->gart.num_gpu_pages) + return -EINVAL; + pte = 0; + writeq(pte, ((void __iomem *)ptr) + (i * 8)); + return 0; +} - /* setup the gart before changing location so we can ask to - * discard unmapped mc request - */ - /* FIXME: disable out of gart access */ - tmp = rdev->mc.gtt_location / 4096; - tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp); - WREG32(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp); - tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096; - tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp); - WREG32(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp); - - rs600_mc_disable_clients(rdev); - if (r600_mc_wait_for_idle(rdev)) { - printk(KERN_WARNING "Failed to wait MC idle while " - "programming pipes. Bad things might happen.\n"); +void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) +{ + unsigned i; + u32 tmp; + + WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); + WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); + WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); + for (i = 0; i < rdev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); + tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; + if (tmp == 2) { + printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); + return; + } + if (tmp) { + return; + } + udelay(1); } +} - tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; - tmp = REG_SET(R600_MC_FB_TOP, tmp >> 24); - tmp |= REG_SET(R600_MC_FB_BASE, rdev->mc.vram_location >> 24); - WREG32(R600_MC_VM_FB_LOCATION, tmp); - tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; - tmp = REG_SET(R600_MC_AGP_TOP, tmp >> 22); - WREG32(R600_MC_VM_AGP_TOP, tmp); - tmp = REG_SET(R600_MC_AGP_BOT, rdev->mc.gtt_location >> 22); - WREG32(R600_MC_VM_AGP_BOT, tmp); - return 0; +int r600_pcie_gart_init(struct radeon_device *rdev) +{ + int r; + + if (rdev->gart.table.vram.robj) { + WARN(1, "R600 PCIE GART already initialized.\n"); + return 0; + } + /* Initialize common gart structure */ + r = radeon_gart_init(rdev); + if (r) + return r; + rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; + return radeon_gart_table_vram_alloc(rdev); } -void r600_mc_fini(struct radeon_device *rdev) +int r600_pcie_gart_enable(struct radeon_device *rdev) { - /* FIXME: implement */ + u32 tmp; + int r, i; + + if (rdev->gart.table.vram.robj == NULL) { + dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); + return -EINVAL; + } + r = radeon_gart_table_vram_pin(rdev); + if (r) + return r; + + /* Setup L2 cache */ + WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | + ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | + EFFECTIVE_L2_QUEUE_SIZE(7)); + WREG32(VM_L2_CNTL2, 0); + WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); + /* Setup TLB control */ + tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | + SYSTEM_ACCESS_MODE_NOT_IN_SYS | + EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | + ENABLE_WAIT_L2_QUERY; + WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); + WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); + WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); + WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12); + WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); + WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); + WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, + (u32)(rdev->dummy_page.addr >> 12)); + for (i = 1; i < 7; i++) + WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); + + r600_pcie_gart_tlb_flush(rdev); + rdev->gart.ready = true; + return 0; } +void r600_pcie_gart_disable(struct radeon_device *rdev) +{ + u32 tmp; + int i; -/* - * Global GPU functions - */ -void r600_errata(struct radeon_device *rdev) + /* Disable all tables */ + for (i = 0; i < 7; i++) + WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); + + /* Disable L2 cache */ + WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | + EFFECTIVE_L2_QUEUE_SIZE(7)); + WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); + /* Setup L1 TLB control */ + tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | + ENABLE_WAIT_L2_QUERY; + WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); + if (rdev->gart.table.vram.robj) { + radeon_object_kunmap(rdev->gart.table.vram.robj); + radeon_object_unpin(rdev->gart.table.vram.robj); + } +} + +void r600_pcie_gart_fini(struct radeon_device *rdev) { - rdev->pll_errata = 0; + r600_pcie_gart_disable(rdev); + radeon_gart_table_vram_free(rdev); + radeon_gart_fini(rdev); } int r600_mc_wait_for_idle(struct radeon_device *rdev) { - /* FIXME: implement */ - return 0; + unsigned i; + u32 tmp; + + for (i = 0; i < rdev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; + if (!tmp) + return 0; + udelay(1); + } + return -1; } -void r600_gpu_init(struct radeon_device *rdev) +static void r600_mc_resume(struct radeon_device *rdev) { - /* FIXME: implement */ -} + u32 d1vga_control, d2vga_control; + u32 vga_render_control, vga_hdp_control; + u32 d1crtc_control, d2crtc_control; + u32 new_d1grph_primary, new_d1grph_secondary; + u32 new_d2grph_primary, new_d2grph_secondary; + u64 old_vram_start; + u32 tmp; + int i, j; + /* Initialize HDP */ + for (i = 0, j = 0; i < 32; i++, j += 0x18) { + WREG32((0x2c14 + j), 0x00000000); + WREG32((0x2c18 + j), 0x00000000); + WREG32((0x2c1c + j), 0x00000000); + WREG32((0x2c20 + j), 0x00000000); + WREG32((0x2c24 + j), 0x00000000); + } + WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); -/* - * VRAM info - */ -void r600_vram_get_type(struct radeon_device *rdev) + d1vga_control = RREG32(D1VGA_CONTROL); + d2vga_control = RREG32(D2VGA_CONTROL); + vga_render_control = RREG32(VGA_RENDER_CONTROL); + vga_hdp_control = RREG32(VGA_HDP_CONTROL); + d1crtc_control = RREG32(D1CRTC_CONTROL); + d2crtc_control = RREG32(D2CRTC_CONTROL); + old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; + new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS); + new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS); + new_d1grph_primary += rdev->mc.vram_start - old_vram_start; + new_d1grph_secondary += rdev->mc.vram_start - old_vram_start; + new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS); + new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS); + new_d2grph_primary += rdev->mc.vram_start - old_vram_start; + new_d2grph_secondary += rdev->mc.vram_start - old_vram_start; + + /* Stop all video */ + WREG32(D1VGA_CONTROL, 0); + WREG32(D2VGA_CONTROL, 0); + WREG32(VGA_RENDER_CONTROL, 0); + WREG32(D1CRTC_UPDATE_LOCK, 1); + WREG32(D2CRTC_UPDATE_LOCK, 1); + WREG32(D1CRTC_CONTROL, 0); + WREG32(D2CRTC_CONTROL, 0); + WREG32(D1CRTC_UPDATE_LOCK, 0); + WREG32(D2CRTC_UPDATE_LOCK, 0); + + mdelay(1); + if (r600_mc_wait_for_idle(rdev)) { + printk(KERN_WARNING "[drm] MC not idle !\n"); + } + + /* Lockout access through VGA aperture*/ + WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); + + /* Update configuration */ + WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); + WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12); + WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); + tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16; + tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); + WREG32(MC_VM_FB_LOCATION, tmp); + WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); + WREG32(HDP_NONSURFACE_INFO, (2 << 7)); + WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF); + if (rdev->flags & RADEON_IS_AGP) { + WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16); + WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); + WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); + } else { + WREG32(MC_VM_AGP_BASE, 0); + WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); + WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); + } + WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary); + WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary); + WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary); + WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary); + WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); + + /* Unlock host access */ + WREG32(VGA_HDP_CONTROL, vga_hdp_control); + + mdelay(1); + if (r600_mc_wait_for_idle(rdev)) { + printk(KERN_WARNING "[drm] MC not idle !\n"); + } + + /* Restore video state */ + WREG32(D1CRTC_UPDATE_LOCK, 1); + WREG32(D2CRTC_UPDATE_LOCK, 1); + WREG32(D1CRTC_CONTROL, d1crtc_control); + WREG32(D2CRTC_CONTROL, d2crtc_control); + WREG32(D1CRTC_UPDATE_LOCK, 0); + WREG32(D2CRTC_UPDATE_LOCK, 0); + WREG32(D1VGA_CONTROL, d1vga_control); + WREG32(D2VGA_CONTROL, d2vga_control); + WREG32(VGA_RENDER_CONTROL, vga_render_control); + + /* we need to own VRAM, so turn off the VGA renderer here + * to stop it overwriting our objects */ + radeon_avivo_vga_render_disable(rdev); +} + +int r600_mc_init(struct radeon_device *rdev) { - uint32_t tmp; + fixed20_12 a; + u32 tmp; int chansize; + int r; + /* Get VRAM informations */ rdev->mc.vram_width = 128; rdev->mc.vram_is_ddr = true; - - tmp = RREG32(R600_RAMCFG); - if (tmp & R600_CHANSIZE_OVERRIDE) { + tmp = RREG32(RAMCFG); + if (tmp & CHANSIZE_OVERRIDE) { chansize = 16; - } else if (tmp & R600_CHANSIZE) { + } else if (tmp & CHANSIZE_MASK) { chansize = 64; } else { chansize = 32; @@ -135,36 +374,1459 @@ void r600_vram_get_type(struct radeon_device *rdev) (rdev->family == CHIP_RV635)) { rdev->mc.vram_width = 2 * chansize; } + /* Could aper size report 0 ? */ + rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); + rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); + /* Setup GPU memory space */ + rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); + rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); + if (rdev->flags & RADEON_IS_AGP) { + r = radeon_agp_init(rdev); + if (r) + return r; + /* gtt_size is setup by radeon_agp_init */ + rdev->mc.gtt_location = rdev->mc.agp_base; + tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; + /* Try to put vram before or after AGP because we + * we want SYSTEM_APERTURE to cover both VRAM and + * AGP so that GPU can catch out of VRAM/AGP access + */ + if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { + /* Enought place before */ + rdev->mc.vram_location = rdev->mc.gtt_location - + rdev->mc.mc_vram_size; + } else if (tmp > rdev->mc.mc_vram_size) { + /* Enought place after */ + rdev->mc.vram_location = rdev->mc.gtt_location + + rdev->mc.gtt_size; + } else { + /* Try to setup VRAM then AGP might not + * not work on some card + */ + rdev->mc.vram_location = 0x00000000UL; + rdev->mc.gtt_location = rdev->mc.mc_vram_size; + } + } else { + if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { + rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) & + 0xFFFF) << 24; + rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; + tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; + if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { + /* Enough place after vram */ + rdev->mc.gtt_location = tmp; + } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) { + /* Enough place before vram */ + rdev->mc.gtt_location = 0; + } else { + /* Not enough place after or before shrink + * gart size + */ + if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) { + rdev->mc.gtt_location = 0; + rdev->mc.gtt_size = rdev->mc.vram_location; + } else { + rdev->mc.gtt_location = tmp; + rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp; + } + } + rdev->mc.gtt_location = rdev->mc.mc_vram_size; + } else { + rdev->mc.vram_location = 0x00000000UL; + rdev->mc.gtt_location = rdev->mc.mc_vram_size; + rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; + } + } + rdev->mc.vram_start = rdev->mc.vram_location; + rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size; + rdev->mc.gtt_start = rdev->mc.gtt_location; + rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size; + /* FIXME: we should enforce default clock in case GPU is not in + * default setup + */ + a.full = rfixed_const(100); + rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); + rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); + return 0; } -void r600_vram_info(struct radeon_device *rdev) +/* We doesn't check that the GPU really needs a reset we simply do the + * reset, it's up to the caller to determine if the GPU needs one. We + * might add an helper function to check that. + */ +int r600_gpu_soft_reset(struct radeon_device *rdev) { - r600_vram_get_type(rdev); - rdev->mc.real_vram_size = RREG32(R600_CONFIG_MEMSIZE); - rdev->mc.mc_vram_size = rdev->mc.real_vram_size; + u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | + S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | + S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | + S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | + S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | + S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | + S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | + S_008010_GUI_ACTIVE(1); + u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | + S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | + S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | + S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | + S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | + S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | + S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | + S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); + u32 srbm_reset = 0; - /* Could aper size report 0 ? */ - rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); - rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); + /* Disable CP parsing/prefetching */ + WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff)); + /* Check if any of the rendering block is busy and reset it */ + if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || + (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { + WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CR(1) | + S_008020_SOFT_RESET_DB(1) | + S_008020_SOFT_RESET_CB(1) | + S_008020_SOFT_RESET_PA(1) | + S_008020_SOFT_RESET_SC(1) | + S_008020_SOFT_RESET_SMX(1) | + S_008020_SOFT_RESET_SPI(1) | + S_008020_SOFT_RESET_SX(1) | + S_008020_SOFT_RESET_SH(1) | + S_008020_SOFT_RESET_TC(1) | + S_008020_SOFT_RESET_TA(1) | + S_008020_SOFT_RESET_VC(1) | + S_008020_SOFT_RESET_VGT(1)); + (void)RREG32(R_008020_GRBM_SOFT_RESET); + udelay(50); + WREG32(R_008020_GRBM_SOFT_RESET, 0); + (void)RREG32(R_008020_GRBM_SOFT_RESET); + } + /* Reset CP (we always reset CP) */ + WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CP(1)); + (void)RREG32(R_008020_GRBM_SOFT_RESET); + udelay(50); + WREG32(R_008020_GRBM_SOFT_RESET, 0); + (void)RREG32(R_008020_GRBM_SOFT_RESET); + /* Reset others GPU block if necessary */ + if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_RLC(1); + if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_GRBM(1); + if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_IH(1); + if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_VMC(1); + if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_MC(1); + if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_MC(1); + if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_MC(1); + if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_MC(1); + if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_MC(1); + if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_RLC(1); + if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_SEM(1); + WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset); + (void)RREG32(R_000E60_SRBM_SOFT_RESET); + udelay(50); + WREG32(R_000E60_SRBM_SOFT_RESET, 0); + (void)RREG32(R_000E60_SRBM_SOFT_RESET); + /* Wait a little for things to settle down */ + udelay(50); + return 0; } +int r600_gpu_reset(struct radeon_device *rdev) +{ + return r600_gpu_soft_reset(rdev); +} + +static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, + u32 num_backends, + u32 backend_disable_mask) +{ + u32 backend_map = 0; + u32 enabled_backends_mask; + u32 enabled_backends_count; + u32 cur_pipe; + u32 swizzle_pipe[R6XX_MAX_PIPES]; + u32 cur_backend; + u32 i; + + if (num_tile_pipes > R6XX_MAX_PIPES) + num_tile_pipes = R6XX_MAX_PIPES; + if (num_tile_pipes < 1) + num_tile_pipes = 1; + if (num_backends > R6XX_MAX_BACKENDS) + num_backends = R6XX_MAX_BACKENDS; + if (num_backends < 1) + num_backends = 1; + + enabled_backends_mask = 0; + enabled_backends_count = 0; + for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { + if (((backend_disable_mask >> i) & 1) == 0) { + enabled_backends_mask |= (1 << i); + ++enabled_backends_count; + } + if (enabled_backends_count == num_backends) + break; + } + + if (enabled_backends_count == 0) { + enabled_backends_mask = 1; + enabled_backends_count = 1; + } + + if (enabled_backends_count != num_backends) + num_backends = enabled_backends_count; + + memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); + switch (num_tile_pipes) { + case 1: + swizzle_pipe[0] = 0; + break; + case 2: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + break; + case 3: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + break; + case 4: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + swizzle_pipe[3] = 3; + break; + case 5: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + swizzle_pipe[3] = 3; + swizzle_pipe[4] = 4; + break; + case 6: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 5; + swizzle_pipe[4] = 1; + swizzle_pipe[5] = 3; + break; + case 7: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 6; + swizzle_pipe[4] = 1; + swizzle_pipe[5] = 3; + swizzle_pipe[6] = 5; + break; + case 8: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 6; + swizzle_pipe[4] = 1; + swizzle_pipe[5] = 3; + swizzle_pipe[6] = 5; + swizzle_pipe[7] = 7; + break; + } + + cur_backend = 0; + for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { + while (((1 << cur_backend) & enabled_backends_mask) == 0) + cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; + + backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); + + cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; + } + + return backend_map; +} + +int r600_count_pipe_bits(uint32_t val) +{ + int i, ret = 0; + + for (i = 0; i < 32; i++) { + ret += val & 1; + val >>= 1; + } + return ret; +} + +void r600_gpu_init(struct radeon_device *rdev) +{ + u32 tiling_config; + u32 ramcfg; + u32 tmp; + int i, j; + u32 sq_config; + u32 sq_gpr_resource_mgmt_1 = 0; + u32 sq_gpr_resource_mgmt_2 = 0; + u32 sq_thread_resource_mgmt = 0; + u32 sq_stack_resource_mgmt_1 = 0; + u32 sq_stack_resource_mgmt_2 = 0; + + /* FIXME: implement */ + switch (rdev->family) { + case CHIP_R600: + rdev->config.r600.max_pipes = 4; + rdev->config.r600.max_tile_pipes = 8; + rdev->config.r600.max_simds = 4; + rdev->config.r600.max_backends = 4; + rdev->config.r600.max_gprs = 256; + rdev->config.r600.max_threads = 192; + rdev->config.r600.max_stack_entries = 256; + rdev->config.r600.max_hw_contexts = 8; + rdev->config.r600.max_gs_threads = 16; + rdev->config.r600.sx_max_export_size = 128; + rdev->config.r600.sx_max_export_pos_size = 16; + rdev->config.r600.sx_max_export_smx_size = 128; + rdev->config.r600.sq_num_cf_insts = 2; + break; + case CHIP_RV630: + case CHIP_RV635: + rdev->config.r600.max_pipes = 2; + rdev->config.r600.max_tile_pipes = 2; + rdev->config.r600.max_simds = 3; + rdev->config.r600.max_backends = 1; + rdev->config.r600.max_gprs = 128; + rdev->config.r600.max_threads = 192; + rdev->config.r600.max_stack_entries = 128; + rdev->config.r600.max_hw_contexts = 8; + rdev->config.r600.max_gs_threads = 4; + rdev->config.r600.sx_max_export_size = 128; + rdev->config.r600.sx_max_export_pos_size = 16; + rdev->config.r600.sx_max_export_smx_size = 128; + rdev->config.r600.sq_num_cf_insts = 2; + break; + case CHIP_RV610: + case CHIP_RV620: + case CHIP_RS780: + case CHIP_RS880: + rdev->config.r600.max_pipes = 1; + rdev->config.r600.max_tile_pipes = 1; + rdev->config.r600.max_simds = 2; + rdev->config.r600.max_backends = 1; + rdev->config.r600.max_gprs = 128; + rdev->config.r600.max_threads = 192; + rdev->config.r600.max_stack_entries = 128; + rdev->config.r600.max_hw_contexts = 4; + rdev->config.r600.max_gs_threads = 4; + rdev->config.r600.sx_max_export_size = 128; + rdev->config.r600.sx_max_export_pos_size = 16; + rdev->config.r600.sx_max_export_smx_size = 128; + rdev->config.r600.sq_num_cf_insts = 1; + break; + case CHIP_RV670: + rdev->config.r600.max_pipes = 4; + rdev->config.r600.max_tile_pipes = 4; + rdev->config.r600.max_simds = 4; + rdev->config.r600.max_backends = 4; + rdev->config.r600.max_gprs = 192; + rdev->config.r600.max_threads = 192; + rdev->config.r600.max_stack_entries = 256; + rdev->config.r600.max_hw_contexts = 8; + rdev->config.r600.max_gs_threads = 16; + rdev->config.r600.sx_max_export_size = 128; + rdev->config.r600.sx_max_export_pos_size = 16; + rdev->config.r600.sx_max_export_smx_size = 128; + rdev->config.r600.sq_num_cf_insts = 2; + break; + default: + break; + } + + /* Initialize HDP */ + for (i = 0, j = 0; i < 32; i++, j += 0x18) { + WREG32((0x2c14 + j), 0x00000000); + WREG32((0x2c18 + j), 0x00000000); + WREG32((0x2c1c + j), 0x00000000); + WREG32((0x2c20 + j), 0x00000000); + WREG32((0x2c24 + j), 0x00000000); + } + + WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); + + /* Setup tiling */ + tiling_config = 0; + ramcfg = RREG32(RAMCFG); + switch (rdev->config.r600.max_tile_pipes) { + case 1: + tiling_config |= PIPE_TILING(0); + break; + case 2: + tiling_config |= PIPE_TILING(1); + break; + case 4: + tiling_config |= PIPE_TILING(2); + break; + case 8: + tiling_config |= PIPE_TILING(3); + break; + default: + break; + } + tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); + tiling_config |= GROUP_SIZE(0); + tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; + if (tmp > 3) { + tiling_config |= ROW_TILING(3); + tiling_config |= SAMPLE_SPLIT(3); + } else { + tiling_config |= ROW_TILING(tmp); + tiling_config |= SAMPLE_SPLIT(tmp); + } + tiling_config |= BANK_SWAPS(1); + tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, + rdev->config.r600.max_backends, + (0xff << rdev->config.r600.max_backends) & 0xff); + tiling_config |= BACKEND_MAP(tmp); + WREG32(GB_TILING_CONFIG, tiling_config); + WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); + WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); + + tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); + WREG32(CC_RB_BACKEND_DISABLE, tmp); + + /* Setup pipes */ + tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); + tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); + WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp); + WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp); + + tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK); + WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); + WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); + + /* Setup some CP states */ + WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); + WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); + + WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | + SYNC_WALKER | SYNC_ALIGNER)); + /* Setup various GPU states */ + if (rdev->family == CHIP_RV670) + WREG32(ARB_GDEC_RD_CNTL, 0x00000021); + + tmp = RREG32(SX_DEBUG_1); + tmp |= SMX_EVENT_RELEASE; + if ((rdev->family > CHIP_R600)) + tmp |= ENABLE_NEW_SMX_ADDRESS; + WREG32(SX_DEBUG_1, tmp); + + if (((rdev->family) == CHIP_R600) || + ((rdev->family) == CHIP_RV630) || + ((rdev->family) == CHIP_RV610) || + ((rdev->family) == CHIP_RV620) || + ((rdev->family) == CHIP_RS780)) { + WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); + } else { + WREG32(DB_DEBUG, 0); + } + WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | + DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); + + WREG32(PA_SC_MULTI_CHIP_CNTL, 0); + WREG32(VGT_NUM_INSTANCES, 0); + + WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); + WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); + + tmp = RREG32(SQ_MS_FIFO_SIZES); + if (((rdev->family) == CHIP_RV610) || + ((rdev->family) == CHIP_RV620) || + ((rdev->family) == CHIP_RS780)) { + tmp = (CACHE_FIFO_SIZE(0xa) | + FETCH_FIFO_HIWATER(0xa) | + DONE_FIFO_HIWATER(0xe0) | + ALU_UPDATE_FIFO_HIWATER(0x8)); + } else if (((rdev->family) == CHIP_R600) || + ((rdev->family) == CHIP_RV630)) { + tmp &= ~DONE_FIFO_HIWATER(0xff); + tmp |= DONE_FIFO_HIWATER(0x4); + } + WREG32(SQ_MS_FIFO_SIZES, tmp); + + /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT + * should be adjusted as needed by the 2D/3D drivers. This just sets default values + */ + sq_config = RREG32(SQ_CONFIG); + sq_config &= ~(PS_PRIO(3) | + VS_PRIO(3) | + GS_PRIO(3) | + ES_PRIO(3)); + sq_config |= (DX9_CONSTS | + VC_ENABLE | + PS_PRIO(0) | + VS_PRIO(1) | + GS_PRIO(2) | + ES_PRIO(3)); + + if ((rdev->family) == CHIP_R600) { + sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | + NUM_VS_GPRS(124) | + NUM_CLAUSE_TEMP_GPRS(4)); + sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | + NUM_ES_GPRS(0)); + sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | + NUM_VS_THREADS(48) | + NUM_GS_THREADS(4) | + NUM_ES_THREADS(4)); + sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | + NUM_VS_STACK_ENTRIES(128)); + sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | + NUM_ES_STACK_ENTRIES(0)); + } else if (((rdev->family) == CHIP_RV610) || + ((rdev->family) == CHIP_RV620) || + ((rdev->family) == CHIP_RS780)) { + /* no vertex cache */ + sq_config &= ~VC_ENABLE; + + sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | + NUM_VS_GPRS(44) | + NUM_CLAUSE_TEMP_GPRS(2)); + sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | + NUM_ES_GPRS(17)); + sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | + NUM_VS_THREADS(78) | + NUM_GS_THREADS(4) | + NUM_ES_THREADS(31)); + sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | + NUM_VS_STACK_ENTRIES(40)); + sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | + NUM_ES_STACK_ENTRIES(16)); + } else if (((rdev->family) == CHIP_RV630) || + ((rdev->family) == CHIP_RV635)) { + sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | + NUM_VS_GPRS(44) | + NUM_CLAUSE_TEMP_GPRS(2)); + sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | + NUM_ES_GPRS(18)); + sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | + NUM_VS_THREADS(78) | + NUM_GS_THREADS(4) | + NUM_ES_THREADS(31)); + sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | + NUM_VS_STACK_ENTRIES(40)); + sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | + NUM_ES_STACK_ENTRIES(16)); + } else if ((rdev->family) == CHIP_RV670) { + sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | + NUM_VS_GPRS(44) | + NUM_CLAUSE_TEMP_GPRS(2)); + sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | + NUM_ES_GPRS(17)); + sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | + NUM_VS_THREADS(78) | + NUM_GS_THREADS(4) | + NUM_ES_THREADS(31)); + sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | + NUM_VS_STACK_ENTRIES(64)); + sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | + NUM_ES_STACK_ENTRIES(64)); + } + + WREG32(SQ_CONFIG, sq_config); + WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); + WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); + WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); + WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); + WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); + + if (((rdev->family) == CHIP_RV610) || + ((rdev->family) == CHIP_RV620) || + ((rdev->family) == CHIP_RS780)) { + WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); + } else { + WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); + } + + /* More default values. 2D/3D driver should adjust as needed */ + WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | + S1_X(0x4) | S1_Y(0xc))); + WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | + S1_X(0x2) | S1_Y(0x2) | + S2_X(0xa) | S2_Y(0x6) | + S3_X(0x6) | S3_Y(0xa))); + WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | + S1_X(0x4) | S1_Y(0xc) | + S2_X(0x1) | S2_Y(0x6) | + S3_X(0xa) | S3_Y(0xe))); + WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | + S5_X(0x0) | S5_Y(0x0) | + S6_X(0xb) | S6_Y(0x4) | + S7_X(0x7) | S7_Y(0x8))); + + WREG32(VGT_STRMOUT_EN, 0); + tmp = rdev->config.r600.max_pipes * 16; + switch (rdev->family) { + case CHIP_RV610: + case CHIP_RS780: + case CHIP_RV620: + tmp += 32; + break; + case CHIP_RV670: + tmp += 128; + break; + default: + break; + } + if (tmp > 256) { + tmp = 256; + } + WREG32(VGT_ES_PER_GS, 128); + WREG32(VGT_GS_PER_ES, tmp); + WREG32(VGT_GS_PER_VS, 2); + WREG32(VGT_GS_VERTEX_REUSE, 16); + + /* more default values. 2D/3D driver should adjust as needed */ + WREG32(PA_SC_LINE_STIPPLE_STATE, 0); + WREG32(VGT_STRMOUT_EN, 0); + WREG32(SX_MISC, 0); + WREG32(PA_SC_MODE_CNTL, 0); + WREG32(PA_SC_AA_CONFIG, 0); + WREG32(PA_SC_LINE_STIPPLE, 0); + WREG32(SPI_INPUT_Z, 0); + WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); + WREG32(CB_COLOR7_FRAG, 0); + + /* Clear render buffer base addresses */ + WREG32(CB_COLOR0_BASE, 0); + WREG32(CB_COLOR1_BASE, 0); + WREG32(CB_COLOR2_BASE, 0); + WREG32(CB_COLOR3_BASE, 0); + WREG32(CB_COLOR4_BASE, 0); + WREG32(CB_COLOR5_BASE, 0); + WREG32(CB_COLOR6_BASE, 0); + WREG32(CB_COLOR7_BASE, 0); + WREG32(CB_COLOR7_FRAG, 0); + + switch (rdev->family) { + case CHIP_RV610: + case CHIP_RS780: + case CHIP_RV620: + tmp = TC_L2_SIZE(8); + break; + case CHIP_RV630: + case CHIP_RV635: + tmp = TC_L2_SIZE(4); + break; + case CHIP_R600: + tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; + break; + default: + tmp = TC_L2_SIZE(0); + break; + } + WREG32(TC_CNTL, tmp); + + tmp = RREG32(HDP_HOST_PATH_CNTL); + WREG32(HDP_HOST_PATH_CNTL, tmp); + + tmp = RREG32(ARB_POP); + tmp |= ENABLE_TC128; + WREG32(ARB_POP, tmp); + + WREG32(PA_SC_MULTI_CHIP_CNTL, 0); + WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | + NUM_CLIP_SEQ(3))); + WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); +} + + /* * Indirect registers accessor */ -uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg) +u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) { - uint32_t r; + u32 r; - WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff)); - (void)RREG32(R600_PCIE_PORT_INDEX); - r = RREG32(R600_PCIE_PORT_DATA); + WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); + (void)RREG32(PCIE_PORT_INDEX); + r = RREG32(PCIE_PORT_DATA); return r; } -void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) +void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) { - WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff)); - (void)RREG32(R600_PCIE_PORT_INDEX); - WREG32(R600_PCIE_PORT_DATA, (v)); - (void)RREG32(R600_PCIE_PORT_DATA); + WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); + (void)RREG32(PCIE_PORT_INDEX); + WREG32(PCIE_PORT_DATA, (v)); + (void)RREG32(PCIE_PORT_DATA); +} + + +/* + * CP & Ring + */ +void r600_cp_stop(struct radeon_device *rdev) +{ + WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); +} + +int r600_cp_init_microcode(struct radeon_device *rdev) +{ + struct platform_device *pdev; + const char *chip_name; + size_t pfp_req_size, me_req_size; + char fw_name[30]; + int err; + + DRM_DEBUG("\n"); + + pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); + err = IS_ERR(pdev); + if (err) { + printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); + return -EINVAL; + } + + switch (rdev->family) { + case CHIP_R600: chip_name = "R600"; break; + case CHIP_RV610: chip_name = "RV610"; break; + case CHIP_RV630: chip_name = "RV630"; break; + case CHIP_RV620: chip_name = "RV620"; break; + case CHIP_RV635: chip_name = "RV635"; break; + case CHIP_RV670: chip_name = "RV670"; break; + case CHIP_RS780: + case CHIP_RS880: chip_name = "RS780"; break; + case CHIP_RV770: chip_name = "RV770"; break; + case CHIP_RV730: + case CHIP_RV740: chip_name = "RV730"; break; + case CHIP_RV710: chip_name = "RV710"; break; + default: BUG(); + } + + if (rdev->family >= CHIP_RV770) { + pfp_req_size = R700_PFP_UCODE_SIZE * 4; + me_req_size = R700_PM4_UCODE_SIZE * 4; + } else { + pfp_req_size = PFP_UCODE_SIZE * 4; + me_req_size = PM4_UCODE_SIZE * 12; + } + + DRM_INFO("Loading %s CP Microcode\n", chip_name); + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); + err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); + if (err) + goto out; + if (rdev->pfp_fw->size != pfp_req_size) { + printk(KERN_ERR + "r600_cp: Bogus length %zu in firmware \"%s\"\n", + rdev->pfp_fw->size, fw_name); + err = -EINVAL; + goto out; + } + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); + err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); + if (err) + goto out; + if (rdev->me_fw->size != me_req_size) { + printk(KERN_ERR + "r600_cp: Bogus length %zu in firmware \"%s\"\n", + rdev->me_fw->size, fw_name); + err = -EINVAL; + } +out: + platform_device_unregister(pdev); + + if (err) { + if (err != -EINVAL) + printk(KERN_ERR + "r600_cp: Failed to load firmware \"%s\"\n", + fw_name); + release_firmware(rdev->pfp_fw); + rdev->pfp_fw = NULL; + release_firmware(rdev->me_fw); + rdev->me_fw = NULL; + } + return err; +} + +static int r600_cp_load_microcode(struct radeon_device *rdev) +{ + const __be32 *fw_data; + int i; + + if (!rdev->me_fw || !rdev->pfp_fw) + return -EINVAL; + + r600_cp_stop(rdev); + + WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); + + /* Reset cp */ + WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); + RREG32(GRBM_SOFT_RESET); + mdelay(15); + WREG32(GRBM_SOFT_RESET, 0); + + WREG32(CP_ME_RAM_WADDR, 0); + + fw_data = (const __be32 *)rdev->me_fw->data; + WREG32(CP_ME_RAM_WADDR, 0); + for (i = 0; i < PM4_UCODE_SIZE * 3; i++) + WREG32(CP_ME_RAM_DATA, + be32_to_cpup(fw_data++)); + + fw_data = (const __be32 *)rdev->pfp_fw->data; + WREG32(CP_PFP_UCODE_ADDR, 0); + for (i = 0; i < PFP_UCODE_SIZE; i++) + WREG32(CP_PFP_UCODE_DATA, + be32_to_cpup(fw_data++)); + + WREG32(CP_PFP_UCODE_ADDR, 0); + WREG32(CP_ME_RAM_WADDR, 0); + WREG32(CP_ME_RAM_RADDR, 0); + return 0; +} + +int r600_cp_start(struct radeon_device *rdev) +{ + int r; + uint32_t cp_me; + + r = radeon_ring_lock(rdev, 7); + if (r) { + DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); + return r; + } + radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); + radeon_ring_write(rdev, 0x1); + if (rdev->family < CHIP_RV770) { + radeon_ring_write(rdev, 0x3); + radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1); + } else { + radeon_ring_write(rdev, 0x0); + radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); + } + radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); + radeon_ring_write(rdev, 0); + radeon_ring_write(rdev, 0); + radeon_ring_unlock_commit(rdev); + + cp_me = 0xff; + WREG32(R_0086D8_CP_ME_CNTL, cp_me); + return 0; +} + +int r600_cp_resume(struct radeon_device *rdev) +{ + u32 tmp; + u32 rb_bufsz; + int r; + + /* Reset cp */ + WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); + RREG32(GRBM_SOFT_RESET); + mdelay(15); + WREG32(GRBM_SOFT_RESET, 0); + + /* Set ring buffer size */ + rb_bufsz = drm_order(rdev->cp.ring_size / 8); +#ifdef __BIG_ENDIAN + WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE | + (drm_order(4096/8) << 8) | rb_bufsz); +#else + WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(4096/8) << 8) | rb_bufsz); +#endif + WREG32(CP_SEM_WAIT_TIMER, 0x4); + + /* Set the write pointer delay */ + WREG32(CP_RB_WPTR_DELAY, 0); + + /* Initialize the ring buffer's read and write pointers */ + tmp = RREG32(CP_RB_CNTL); + WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); + WREG32(CP_RB_RPTR_WR, 0); + WREG32(CP_RB_WPTR, 0); + WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF); + WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr)); + mdelay(1); + WREG32(CP_RB_CNTL, tmp); + + WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); + WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); + + rdev->cp.rptr = RREG32(CP_RB_RPTR); + rdev->cp.wptr = RREG32(CP_RB_WPTR); + + r600_cp_start(rdev); + rdev->cp.ready = true; + r = radeon_ring_test(rdev); + if (r) { + rdev->cp.ready = false; + return r; + } + return 0; +} + +void r600_cp_commit(struct radeon_device *rdev) +{ + WREG32(CP_RB_WPTR, rdev->cp.wptr); + (void)RREG32(CP_RB_WPTR); +} + +void r600_ring_init(struct radeon_device *rdev, unsigned ring_size) +{ + u32 rb_bufsz; + + /* Align ring size */ + rb_bufsz = drm_order(ring_size / 8); + ring_size = (1 << (rb_bufsz + 1)) * 4; + rdev->cp.ring_size = ring_size; + rdev->cp.align_mask = 16 - 1; +} + + +/* + * GPU scratch registers helpers function. + */ +void r600_scratch_init(struct radeon_device *rdev) +{ + int i; + + rdev->scratch.num_reg = 7; + for (i = 0; i < rdev->scratch.num_reg; i++) { + rdev->scratch.free[i] = true; + rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4); + } +} + +int r600_ring_test(struct radeon_device *rdev) +{ + uint32_t scratch; + uint32_t tmp = 0; + unsigned i; + int r; + + r = radeon_scratch_get(rdev, &scratch); + if (r) { + DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + r = radeon_ring_lock(rdev, 3); + if (r) { + DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); + radeon_scratch_free(rdev, scratch); + return r; + } + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); + radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); + radeon_ring_write(rdev, 0xDEADBEEF); + radeon_ring_unlock_commit(rdev); + for (i = 0; i < rdev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + if (i < rdev->usec_timeout) { + DRM_INFO("ring test succeeded in %d usecs\n", i); + } else { + DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", + scratch, tmp); + r = -EINVAL; + } + radeon_scratch_free(rdev, scratch); + return r; +} + +/* + * Writeback + */ +int r600_wb_init(struct radeon_device *rdev) +{ + int r; + + if (rdev->wb.wb_obj == NULL) { + r = radeon_object_create(rdev, NULL, 4096, + true, + RADEON_GEM_DOMAIN_GTT, + false, &rdev->wb.wb_obj); + if (r) { + DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r); + return r; + } + r = radeon_object_pin(rdev->wb.wb_obj, + RADEON_GEM_DOMAIN_GTT, + &rdev->wb.gpu_addr); + if (r) { + DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r); + return r; + } + r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); + if (r) { + DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r); + return r; + } + } + WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF); + WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC); + WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF); + WREG32(SCRATCH_UMSK, 0xff); + return 0; +} + +void r600_wb_fini(struct radeon_device *rdev) +{ + if (rdev->wb.wb_obj) { + radeon_object_kunmap(rdev->wb.wb_obj); + radeon_object_unpin(rdev->wb.wb_obj); + radeon_object_unref(&rdev->wb.wb_obj); + rdev->wb.wb = NULL; + rdev->wb.wb_obj = NULL; + } +} + + +/* + * CS + */ +void r600_fence_ring_emit(struct radeon_device *rdev, + struct radeon_fence *fence) +{ + /* Emit fence sequence & fire IRQ */ + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); + radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); + radeon_ring_write(rdev, fence->seq); +} + +int r600_copy_dma(struct radeon_device *rdev, + uint64_t src_offset, + uint64_t dst_offset, + unsigned num_pages, + struct radeon_fence *fence) +{ + /* FIXME: implement */ + return 0; +} + +int r600_copy_blit(struct radeon_device *rdev, + uint64_t src_offset, uint64_t dst_offset, + unsigned num_pages, struct radeon_fence *fence) +{ + r600_blit_prepare_copy(rdev, num_pages * 4096); + r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * 4096); + r600_blit_done_copy(rdev, fence); + return 0; +} + +int r600_irq_process(struct radeon_device *rdev) +{ + /* FIXME: implement */ + return 0; +} + +int r600_irq_set(struct radeon_device *rdev) +{ + /* FIXME: implement */ + return 0; +} + +int r600_set_surface_reg(struct radeon_device *rdev, int reg, + uint32_t tiling_flags, uint32_t pitch, + uint32_t offset, uint32_t obj_size) +{ + /* FIXME: implement */ + return 0; +} + +void r600_clear_surface_reg(struct radeon_device *rdev, int reg) +{ + /* FIXME: implement */ +} + + +bool r600_card_posted(struct radeon_device *rdev) +{ + uint32_t reg; + + /* first check CRTCs */ + reg = RREG32(D1CRTC_CONTROL) | + RREG32(D2CRTC_CONTROL); + if (reg & CRTC_EN) + return true; + + /* then check MEM_SIZE, in case the crtcs are off */ + if (RREG32(CONFIG_MEMSIZE)) + return true; + + return false; +} + +int r600_startup(struct radeon_device *rdev) +{ + int r; + + r600_gpu_reset(rdev); + r600_mc_resume(rdev); + r = r600_pcie_gart_enable(rdev); + if (r) + return r; + r600_gpu_init(rdev); + + r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, + &rdev->r600_blit.shader_gpu_addr); + if (r) { + DRM_ERROR("failed to pin blit object %d\n", r); + return r; + } + + r = radeon_ring_init(rdev, rdev->cp.ring_size); + if (r) + return r; + r = r600_cp_load_microcode(rdev); + if (r) + return r; + r = r600_cp_resume(rdev); + if (r) + return r; + r = r600_wb_init(rdev); + if (r) + return r; + return 0; +} + +void r600_vga_set_state(struct radeon_device *rdev, bool state) +{ + uint32_t temp; + + temp = RREG32(CONFIG_CNTL); + if (state == false) { + temp &= ~(1<<0); + temp |= (1<<1); + } else { + temp &= ~(1<<1); + } + WREG32(CONFIG_CNTL, temp); +} + +int r600_resume(struct radeon_device *rdev) +{ + int r; + + if (radeon_gpu_reset(rdev)) { + /* FIXME: what do we want to do here ? */ + } + /* post card */ + if (rdev->is_atom_bios) { + atom_asic_init(rdev->mode_info.atom_context); + } else { + radeon_combios_asic_init(rdev->ddev); + } + /* Initialize clocks */ + r = radeon_clocks_init(rdev); + if (r) { + return r; + } + + r = r600_startup(rdev); + if (r) { + DRM_ERROR("r600 startup failed on resume\n"); + return r; + } + + r = radeon_ib_test(rdev); + if (r) { + DRM_ERROR("radeon: failled testing IB (%d).\n", r); + return r; + } + return r; +} + + +int r600_suspend(struct radeon_device *rdev) +{ + /* FIXME: we should wait for ring to be empty */ + r600_cp_stop(rdev); + rdev->cp.ready = false; + + r600_pcie_gart_disable(rdev); + /* unpin shaders bo */ + radeon_object_unpin(rdev->r600_blit.shader_obj); + return 0; +} + +/* Plan is to move initialization in that function and use + * helper function so that radeon_device_init pretty much + * do nothing more than calling asic specific function. This + * should also allow to remove a bunch of callback function + * like vram_info. + */ +int r600_init(struct radeon_device *rdev) +{ + int r; + + rdev->new_init_path = true; + r = radeon_dummy_page_init(rdev); + if (r) + return r; + if (r600_debugfs_mc_info_init(rdev)) { + DRM_ERROR("Failed to register debugfs file for mc !\n"); + } + /* This don't do much */ + r = radeon_gem_init(rdev); + if (r) + return r; + /* Read BIOS */ + if (!radeon_get_bios(rdev)) { + if (ASIC_IS_AVIVO(rdev)) + return -EINVAL; + } + /* Must be an ATOMBIOS */ + if (!rdev->is_atom_bios) + return -EINVAL; + r = radeon_atombios_init(rdev); + if (r) + return r; + /* Post card if necessary */ + if (!r600_card_posted(rdev) && rdev->bios) { + DRM_INFO("GPU not posted. posting now...\n"); + atom_asic_init(rdev->mode_info.atom_context); + } + /* Initialize scratch registers */ + r600_scratch_init(rdev); + /* Initialize surface registers */ + radeon_surface_init(rdev); + radeon_get_clock_info(rdev->ddev); + r = radeon_clocks_init(rdev); + if (r) + return r; + /* Fence driver */ + r = radeon_fence_driver_init(rdev); + if (r) + return r; + r = r600_mc_init(rdev); + if (r) { + if (rdev->flags & RADEON_IS_AGP) { + /* Retry with disabling AGP */ + r600_fini(rdev); + rdev->flags &= ~RADEON_IS_AGP; + return r600_init(rdev); + } + return r; + } + /* Memory manager */ + r = radeon_object_init(rdev); + if (r) + return r; + rdev->cp.ring_obj = NULL; + r600_ring_init(rdev, 1024 * 1024); + + if (!rdev->me_fw || !rdev->pfp_fw) { + r = r600_cp_init_microcode(rdev); + if (r) { + DRM_ERROR("Failed to load firmware!\n"); + return r; + } + } + + r = r600_pcie_gart_init(rdev); + if (r) + return r; + + rdev->accel_working = true; + r = r600_blit_init(rdev); + if (r) { + DRM_ERROR("radeon: failled blitter (%d).\n", r); + return r; + } + + r = r600_startup(rdev); + if (r) { + if (rdev->flags & RADEON_IS_AGP) { + /* Retry with disabling AGP */ + r600_fini(rdev); + rdev->flags &= ~RADEON_IS_AGP; + return r600_init(rdev); + } + rdev->accel_working = false; + } + if (rdev->accel_working) { + r = radeon_ib_pool_init(rdev); + if (r) { + DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); + rdev->accel_working = false; + } + r = radeon_ib_test(rdev); + if (r) { + DRM_ERROR("radeon: failled testing IB (%d).\n", r); + rdev->accel_working = false; + } + } + return 0; +} + +void r600_fini(struct radeon_device *rdev) +{ + /* Suspend operations */ + r600_suspend(rdev); + + r600_blit_fini(rdev); + radeon_ring_fini(rdev); + r600_pcie_gart_fini(rdev); + radeon_gem_fini(rdev); + radeon_fence_driver_fini(rdev); + radeon_clocks_fini(rdev); +#if __OS_HAS_AGP + if (rdev->flags & RADEON_IS_AGP) + radeon_agp_fini(rdev); +#endif + radeon_object_fini(rdev); + if (rdev->is_atom_bios) + radeon_atombios_fini(rdev); + else + radeon_combios_fini(rdev); + kfree(rdev->bios); + rdev->bios = NULL; + radeon_dummy_page_fini(rdev); +} + + +/* + * CS stuff + */ +void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) +{ + /* FIXME: implement */ + radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); + radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC); + radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); + radeon_ring_write(rdev, ib->length_dw); +} + +int r600_ib_test(struct radeon_device *rdev) +{ + struct radeon_ib *ib; + uint32_t scratch; + uint32_t tmp = 0; + unsigned i; + int r; + + r = radeon_scratch_get(rdev, &scratch); + if (r) { + DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + r = radeon_ib_get(rdev, &ib); + if (r) { + DRM_ERROR("radeon: failed to get ib (%d).\n", r); + return r; + } + ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); + ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); + ib->ptr[2] = 0xDEADBEEF; + ib->ptr[3] = PACKET2(0); + ib->ptr[4] = PACKET2(0); + ib->ptr[5] = PACKET2(0); + ib->ptr[6] = PACKET2(0); + ib->ptr[7] = PACKET2(0); + ib->ptr[8] = PACKET2(0); + ib->ptr[9] = PACKET2(0); + ib->ptr[10] = PACKET2(0); + ib->ptr[11] = PACKET2(0); + ib->ptr[12] = PACKET2(0); + ib->ptr[13] = PACKET2(0); + ib->ptr[14] = PACKET2(0); + ib->ptr[15] = PACKET2(0); + ib->length_dw = 16; + r = radeon_ib_schedule(rdev, ib); + if (r) { + radeon_scratch_free(rdev, scratch); + radeon_ib_free(rdev, &ib); + DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); + return r; + } + r = radeon_fence_wait(ib->fence, false); + if (r) { + DRM_ERROR("radeon: fence wait failed (%d).\n", r); + return r; + } + for (i = 0; i < rdev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + if (i < rdev->usec_timeout) { + DRM_INFO("ib test succeeded in %u usecs\n", i); + } else { + DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", + scratch, tmp); + r = -EINVAL; + } + radeon_scratch_free(rdev, scratch); + radeon_ib_free(rdev, &ib); + return r; +} + + + + +/* + * Debugfs info + */ +#if defined(CONFIG_DEBUG_FS) + +static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + struct radeon_device *rdev = dev->dev_private; + uint32_t rdp, wdp; + unsigned count, i, j; + + radeon_ring_free_size(rdev); + rdp = RREG32(CP_RB_RPTR); + wdp = RREG32(CP_RB_WPTR); + count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask; + seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); + seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); + seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); + seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); + seq_printf(m, "%u dwords in ring\n", count); + for (j = 0; j <= count; j++) { + i = (rdp + j) & rdev->cp.ptr_mask; + seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); + } + return 0; +} + +static int r600_debugfs_mc_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + struct radeon_device *rdev = dev->dev_private; + + DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); + DREG32_SYS(m, rdev, VM_L2_STATUS); + return 0; +} + +static struct drm_info_list r600_mc_info_list[] = { + {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, + {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL}, +}; +#endif + +int r600_debugfs_mc_info_init(struct radeon_device *rdev) +{ +#if defined(CONFIG_DEBUG_FS) + return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); +#else + return 0; +#endif } diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c new file mode 100644 index 000000000000..dde2ccbf1d15 --- /dev/null +++ b/drivers/gpu/drm/radeon/r600_blit.c @@ -0,0 +1,850 @@ +/* + * Copyright 2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Alex Deucher + */ +#include "drmP.h" +#include "drm.h" +#include "radeon_drm.h" +#include "radeon_drv.h" + +#include "r600_blit_shaders.h" + +#define DI_PT_RECTLIST 0x11 +#define DI_INDEX_SIZE_16_BIT 0x0 +#define DI_SRC_SEL_AUTO_INDEX 0x2 + +#define FMT_8 0x1 +#define FMT_5_6_5 0x8 +#define FMT_8_8_8_8 0x1a +#define COLOR_8 0x1 +#define COLOR_5_6_5 0x8 +#define COLOR_8_8_8_8 0x1a + +static inline void +set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr) +{ + u32 cb_color_info; + int pitch, slice; + RING_LOCALS; + DRM_DEBUG("\n"); + + h = (h + 7) & ~7; + if (h < 8) + h = 8; + + cb_color_info = ((format << 2) | (1 << 27)); + pitch = (w / 8) - 1; + slice = ((w * h) / 64) - 1; + + if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600) && + ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) { + BEGIN_RING(21 + 2); + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(gpu_addr >> 8); + OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0)); + OUT_RING(2 << 0); + } else { + BEGIN_RING(21); + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(gpu_addr >> 8); + } + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING((pitch << 0) | (slice << 10)); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_CB_COLOR0_VIEW - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(0); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_CB_COLOR0_INFO - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(cb_color_info); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_CB_COLOR0_TILE - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(0); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_CB_COLOR0_FRAG - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(0); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_CB_COLOR0_MASK - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(0); + + ADVANCE_RING(); +} + +static inline void +cp_set_surface_sync(drm_radeon_private_t *dev_priv, + u32 sync_type, u32 size, u64 mc_addr) +{ + u32 cp_coher_size; + RING_LOCALS; + DRM_DEBUG("\n"); + + if (size == 0xffffffff) + cp_coher_size = 0xffffffff; + else + cp_coher_size = ((size + 255) >> 8); + + BEGIN_RING(5); + OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYNC, 3)); + OUT_RING(sync_type); + OUT_RING(cp_coher_size); + OUT_RING((mc_addr >> 8)); + OUT_RING(10); /* poll interval */ + ADVANCE_RING(); +} + +static inline void +set_shaders(struct drm_device *dev) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + u64 gpu_addr; + int i; + u32 *vs, *ps; + uint32_t sq_pgm_resources; + RING_LOCALS; + DRM_DEBUG("\n"); + + /* load shaders */ + vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset); + ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256); + + for (i = 0; i < r6xx_vs_size; i++) + vs[i] = r6xx_vs[i]; + for (i = 0; i < r6xx_ps_size; i++) + ps[i] = r6xx_ps[i]; + + dev_priv->blit_vb->used = 512; + + gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset; + + /* setup shader regs */ + sq_pgm_resources = (1 << 0); + + BEGIN_RING(9 + 12); + /* VS */ + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_SQ_PGM_START_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(gpu_addr >> 8); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_SQ_PGM_RESOURCES_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(sq_pgm_resources); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_SQ_PGM_CF_OFFSET_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(0); + + /* PS */ + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_SQ_PGM_START_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING((gpu_addr + 256) >> 8); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_SQ_PGM_RESOURCES_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(sq_pgm_resources | (1 << 28)); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_SQ_PGM_EXPORTS_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(2); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_SQ_PGM_CF_OFFSET_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(0); + ADVANCE_RING(); + + cp_set_surface_sync(dev_priv, + R600_SH_ACTION_ENA, 512, gpu_addr); +} + +static inline void +set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr) +{ + uint32_t sq_vtx_constant_word2; + RING_LOCALS; + DRM_DEBUG("\n"); + + sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8)); + + BEGIN_RING(9); + OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + OUT_RING(0x460); + OUT_RING(gpu_addr & 0xffffffff); + OUT_RING(48 - 1); + OUT_RING(sq_vtx_constant_word2); + OUT_RING(1 << 0); + OUT_RING(0); + OUT_RING(0); + OUT_RING(R600_SQ_TEX_VTX_VALID_BUFFER << 30); + ADVANCE_RING(); + + if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) + cp_set_surface_sync(dev_priv, + R600_TC_ACTION_ENA, 48, gpu_addr); + else + cp_set_surface_sync(dev_priv, + R600_VC_ACTION_ENA, 48, gpu_addr); +} + +static inline void +set_tex_resource(drm_radeon_private_t *dev_priv, + int format, int w, int h, int pitch, u64 gpu_addr) +{ + uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; + RING_LOCALS; + DRM_DEBUG("\n"); + + if (h < 1) + h = 1; + + sq_tex_resource_word0 = (1 << 0); + sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) | + ((w - 1) << 19)); + + sq_tex_resource_word1 = (format << 26); + sq_tex_resource_word1 |= ((h - 1) << 0); + + sq_tex_resource_word4 = ((1 << 14) | + (0 << 16) | + (1 << 19) | + (2 << 22) | + (3 << 25)); + + BEGIN_RING(9); + OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + OUT_RING(0); + OUT_RING(sq_tex_resource_word0); + OUT_RING(sq_tex_resource_word1); + OUT_RING(gpu_addr >> 8); + OUT_RING(gpu_addr >> 8); + OUT_RING(sq_tex_resource_word4); + OUT_RING(0); + OUT_RING(R600_SQ_TEX_VTX_VALID_TEXTURE << 30); + ADVANCE_RING(); + +} + +static inline void +set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2) +{ + RING_LOCALS; + DRM_DEBUG("\n"); + + BEGIN_RING(12); + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); + OUT_RING((R600_PA_SC_SCREEN_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING((x1 << 0) | (y1 << 16)); + OUT_RING((x2 << 0) | (y2 << 16)); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); + OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); + OUT_RING((x2 << 0) | (y2 << 16)); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); + OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); + OUT_RING((x2 << 0) | (y2 << 16)); + ADVANCE_RING(); +} + +static inline void +draw_auto(drm_radeon_private_t *dev_priv) +{ + RING_LOCALS; + DRM_DEBUG("\n"); + + BEGIN_RING(10); + OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + OUT_RING((R600_VGT_PRIMITIVE_TYPE - R600_SET_CONFIG_REG_OFFSET) >> 2); + OUT_RING(DI_PT_RECTLIST); + + OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); + OUT_RING(DI_INDEX_SIZE_16_BIT); + + OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0)); + OUT_RING(1); + + OUT_RING(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1)); + OUT_RING(3); + OUT_RING(DI_SRC_SEL_AUTO_INDEX); + + ADVANCE_RING(); + COMMIT_RING(); +} + +static inline void +set_default_state(drm_radeon_private_t *dev_priv) +{ + int i; + u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; + u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; + int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; + int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; + int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; + RING_LOCALS; + + switch ((dev_priv->flags & RADEON_FAMILY_MASK)) { + case CHIP_R600: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_RV630: + case CHIP_RV635: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 144; + num_vs_threads = 40; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_RV610: + case CHIP_RV620: + case CHIP_RS780: + case CHIP_RS880: + default: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_RV670: + num_ps_gprs = 144; + num_vs_gprs = 40; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_RV770: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 188; + num_vs_threads = 60; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 256; + num_vs_stack_entries = 256; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_RV730: + case CHIP_RV740: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 188; + num_vs_threads = 60; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_RV710: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 144; + num_vs_threads = 48; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + } + + if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) + sq_config = 0; + else + sq_config = R600_VC_ENABLE; + + sq_config |= (R600_DX9_CONSTS | + R600_ALU_INST_PREFER_VECTOR | + R600_PS_PRIO(0) | + R600_VS_PRIO(1) | + R600_GS_PRIO(2) | + R600_ES_PRIO(3)); + + sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(num_ps_gprs) | + R600_NUM_VS_GPRS(num_vs_gprs) | + R600_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); + sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(num_gs_gprs) | + R600_NUM_ES_GPRS(num_es_gprs)); + sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(num_ps_threads) | + R600_NUM_VS_THREADS(num_vs_threads) | + R600_NUM_GS_THREADS(num_gs_threads) | + R600_NUM_ES_THREADS(num_es_threads)); + sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | + R600_NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); + sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | + R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries)); + + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { + BEGIN_RING(r7xx_default_size + 10); + for (i = 0; i < r7xx_default_size; i++) + OUT_RING(r7xx_default_state[i]); + } else { + BEGIN_RING(r6xx_default_size + 10); + for (i = 0; i < r6xx_default_size; i++) + OUT_RING(r6xx_default_state[i]); + } + OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); + OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); + /* SQ config */ + OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 6)); + OUT_RING((R600_SQ_CONFIG - R600_SET_CONFIG_REG_OFFSET) >> 2); + OUT_RING(sq_config); + OUT_RING(sq_gpr_resource_mgmt_1); + OUT_RING(sq_gpr_resource_mgmt_2); + OUT_RING(sq_thread_resource_mgmt); + OUT_RING(sq_stack_resource_mgmt_1); + OUT_RING(sq_stack_resource_mgmt_2); + ADVANCE_RING(); +} + +static inline uint32_t i2f(uint32_t input) +{ + u32 result, i, exponent, fraction; + + if ((input & 0x3fff) == 0) + result = 0; /* 0 is a special case */ + else { + exponent = 140; /* exponent biased by 127; */ + fraction = (input & 0x3fff) << 10; /* cheat and only + handle numbers below 2^^15 */ + for (i = 0; i < 14; i++) { + if (fraction & 0x800000) + break; + else { + fraction = fraction << 1; /* keep + shifting left until top bit = 1 */ + exponent = exponent - 1; + } + } + result = exponent << 23 | (fraction & 0x7fffff); /* mask + off top bit; assumed 1 */ + } + return result; +} + + +static inline int r600_nomm_get_vb(struct drm_device *dev) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + dev_priv->blit_vb = radeon_freelist_get(dev); + if (!dev_priv->blit_vb) { + DRM_ERROR("Unable to allocate vertex buffer for blit\n"); + return -EAGAIN; + } + return 0; +} + +static inline void r600_nomm_put_vb(struct drm_device *dev) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + + dev_priv->blit_vb->used = 0; + radeon_cp_discard_buffer(dev, dev_priv->blit_vb->file_priv->master, dev_priv->blit_vb); +} + +static inline void *r600_nomm_get_vb_ptr(struct drm_device *dev) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + return (((char *)dev->agp_buffer_map->handle + + dev_priv->blit_vb->offset + dev_priv->blit_vb->used)); +} + +int +r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + DRM_DEBUG("\n"); + + r600_nomm_get_vb(dev); + + dev_priv->blit_vb->file_priv = file_priv; + + set_default_state(dev_priv); + set_shaders(dev); + + return 0; +} + + +void +r600_done_blit_copy(struct drm_device *dev) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + DRM_DEBUG("\n"); + + BEGIN_RING(5); + OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); + OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); + /* wait for 3D idle clean */ + OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); + OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); + + ADVANCE_RING(); + COMMIT_RING(); + + r600_nomm_put_vb(dev); +} + +void +r600_blit_copy(struct drm_device *dev, + uint64_t src_gpu_addr, uint64_t dst_gpu_addr, + int size_bytes) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + int max_bytes; + u64 vb_addr; + u32 *vb; + + vb = r600_nomm_get_vb_ptr(dev); + + if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) { + max_bytes = 8192; + + while (size_bytes) { + int cur_size = size_bytes; + int src_x = src_gpu_addr & 255; + int dst_x = dst_gpu_addr & 255; + int h = 1; + src_gpu_addr = src_gpu_addr & ~255; + dst_gpu_addr = dst_gpu_addr & ~255; + + if (!src_x && !dst_x) { + h = (cur_size / max_bytes); + if (h > 8192) + h = 8192; + if (h == 0) + h = 1; + else + cur_size = max_bytes; + } else { + if (cur_size > max_bytes) + cur_size = max_bytes; + if (cur_size > (max_bytes - dst_x)) + cur_size = (max_bytes - dst_x); + if (cur_size > (max_bytes - src_x)) + cur_size = (max_bytes - src_x); + } + + if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) { + + r600_nomm_put_vb(dev); + r600_nomm_get_vb(dev); + if (!dev_priv->blit_vb) + return; + set_shaders(dev); + vb = r600_nomm_get_vb_ptr(dev); + } + + vb[0] = i2f(dst_x); + vb[1] = 0; + vb[2] = i2f(src_x); + vb[3] = 0; + + vb[4] = i2f(dst_x); + vb[5] = i2f(h); + vb[6] = i2f(src_x); + vb[7] = i2f(h); + + vb[8] = i2f(dst_x + cur_size); + vb[9] = i2f(h); + vb[10] = i2f(src_x + cur_size); + vb[11] = i2f(h); + + /* src */ + set_tex_resource(dev_priv, FMT_8, + src_x + cur_size, h, src_x + cur_size, + src_gpu_addr); + + cp_set_surface_sync(dev_priv, + R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); + + /* dst */ + set_render_target(dev_priv, COLOR_8, + dst_x + cur_size, h, + dst_gpu_addr); + + /* scissors */ + set_scissors(dev_priv, dst_x, 0, dst_x + cur_size, h); + + /* Vertex buffer setup */ + vb_addr = dev_priv->gart_buffers_offset + + dev_priv->blit_vb->offset + + dev_priv->blit_vb->used; + set_vtx_resource(dev_priv, vb_addr); + + /* draw */ + draw_auto(dev_priv); + + cp_set_surface_sync(dev_priv, + R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA, + cur_size * h, dst_gpu_addr); + + vb += 12; + dev_priv->blit_vb->used += 12 * 4; + + src_gpu_addr += cur_size * h; + dst_gpu_addr += cur_size * h; + size_bytes -= cur_size * h; + } + } else { + max_bytes = 8192 * 4; + + while (size_bytes) { + int cur_size = size_bytes; + int src_x = (src_gpu_addr & 255); + int dst_x = (dst_gpu_addr & 255); + int h = 1; + src_gpu_addr = src_gpu_addr & ~255; + dst_gpu_addr = dst_gpu_addr & ~255; + + if (!src_x && !dst_x) { + h = (cur_size / max_bytes); + if (h > 8192) + h = 8192; + if (h == 0) + h = 1; + else + cur_size = max_bytes; + } else { + if (cur_size > max_bytes) + cur_size = max_bytes; + if (cur_size > (max_bytes - dst_x)) + cur_size = (max_bytes - dst_x); + if (cur_size > (max_bytes - src_x)) + cur_size = (max_bytes - src_x); + } + + if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) { + r600_nomm_put_vb(dev); + r600_nomm_get_vb(dev); + if (!dev_priv->blit_vb) + return; + + set_shaders(dev); + vb = r600_nomm_get_vb_ptr(dev); + } + + vb[0] = i2f(dst_x / 4); + vb[1] = 0; + vb[2] = i2f(src_x / 4); + vb[3] = 0; + + vb[4] = i2f(dst_x / 4); + vb[5] = i2f(h); + vb[6] = i2f(src_x / 4); + vb[7] = i2f(h); + + vb[8] = i2f((dst_x + cur_size) / 4); + vb[9] = i2f(h); + vb[10] = i2f((src_x + cur_size) / 4); + vb[11] = i2f(h); + + /* src */ + set_tex_resource(dev_priv, FMT_8_8_8_8, + (src_x + cur_size) / 4, + h, (src_x + cur_size) / 4, + src_gpu_addr); + + cp_set_surface_sync(dev_priv, + R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); + + /* dst */ + set_render_target(dev_priv, COLOR_8_8_8_8, + dst_x + cur_size, h, + dst_gpu_addr); + + /* scissors */ + set_scissors(dev_priv, (dst_x / 4), 0, (dst_x + cur_size / 4), h); + + /* Vertex buffer setup */ + vb_addr = dev_priv->gart_buffers_offset + + dev_priv->blit_vb->offset + + dev_priv->blit_vb->used; + set_vtx_resource(dev_priv, vb_addr); + + /* draw */ + draw_auto(dev_priv); + + cp_set_surface_sync(dev_priv, + R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA, + cur_size * h, dst_gpu_addr); + + vb += 12; + dev_priv->blit_vb->used += 12 * 4; + + src_gpu_addr += cur_size * h; + dst_gpu_addr += cur_size * h; + size_bytes -= cur_size * h; + } + } +} + +void +r600_blit_swap(struct drm_device *dev, + uint64_t src_gpu_addr, uint64_t dst_gpu_addr, + int sx, int sy, int dx, int dy, + int w, int h, int src_pitch, int dst_pitch, int cpp) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + int cb_format, tex_format; + u64 vb_addr; + u32 *vb; + + vb = r600_nomm_get_vb_ptr(dev); + + if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) { + + r600_nomm_put_vb(dev); + r600_nomm_get_vb(dev); + if (!dev_priv->blit_vb) + return; + + set_shaders(dev); + vb = r600_nomm_get_vb_ptr(dev); + } + + if (cpp == 4) { + cb_format = COLOR_8_8_8_8; + tex_format = FMT_8_8_8_8; + } else if (cpp == 2) { + cb_format = COLOR_5_6_5; + tex_format = FMT_5_6_5; + } else { + cb_format = COLOR_8; + tex_format = FMT_8; + } + + vb[0] = i2f(dx); + vb[1] = i2f(dy); + vb[2] = i2f(sx); + vb[3] = i2f(sy); + + vb[4] = i2f(dx); + vb[5] = i2f(dy + h); + vb[6] = i2f(sx); + vb[7] = i2f(sy + h); + + vb[8] = i2f(dx + w); + vb[9] = i2f(dy + h); + vb[10] = i2f(sx + w); + vb[11] = i2f(sy + h); + + /* src */ + set_tex_resource(dev_priv, tex_format, + src_pitch / cpp, + sy + h, src_pitch / cpp, + src_gpu_addr); + + cp_set_surface_sync(dev_priv, + R600_TC_ACTION_ENA, (src_pitch * (sy + h)), src_gpu_addr); + + /* dst */ + set_render_target(dev_priv, cb_format, + dst_pitch / cpp, dy + h, + dst_gpu_addr); + + /* scissors */ + set_scissors(dev_priv, dx, dy, dx + w, dy + h); + + /* Vertex buffer setup */ + vb_addr = dev_priv->gart_buffers_offset + + dev_priv->blit_vb->offset + + dev_priv->blit_vb->used; + set_vtx_resource(dev_priv, vb_addr); + + /* draw */ + draw_auto(dev_priv); + + cp_set_surface_sync(dev_priv, + R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA, + dst_pitch * (dy + h), dst_gpu_addr); + + dev_priv->blit_vb->used += 12 * 4; +} diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c new file mode 100644 index 000000000000..0a6f4681f468 --- /dev/null +++ b/drivers/gpu/drm/radeon/r600_blit_kms.c @@ -0,0 +1,805 @@ +#include "drmP.h" +#include "drm.h" +#include "radeon_drm.h" +#include "radeon.h" + +#include "r600d.h" +#include "r600_blit_shaders.h" + +#define DI_PT_RECTLIST 0x11 +#define DI_INDEX_SIZE_16_BIT 0x0 +#define DI_SRC_SEL_AUTO_INDEX 0x2 + +#define FMT_8 0x1 +#define FMT_5_6_5 0x8 +#define FMT_8_8_8_8 0x1a +#define COLOR_8 0x1 +#define COLOR_5_6_5 0x8 +#define COLOR_8_8_8_8 0x1a + +/* emits 21 on rv770+, 23 on r600 */ +static void +set_render_target(struct radeon_device *rdev, int format, + int w, int h, u64 gpu_addr) +{ + u32 cb_color_info; + int pitch, slice; + + h = (h + 7) & ~7; + if (h < 8) + h = 8; + + cb_color_info = ((format << 2) | (1 << 27)); + pitch = (w / 8) - 1; + slice = ((w * h) / 64) - 1; + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, gpu_addr >> 8); + + if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) { + radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); + radeon_ring_write(rdev, 2 << 0); + } + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, (pitch << 0) | (slice << 10)); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, 0); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, cb_color_info); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, 0); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, 0); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, 0); +} + +/* emits 5dw */ +static void +cp_set_surface_sync(struct radeon_device *rdev, + u32 sync_type, u32 size, + u64 mc_addr) +{ + u32 cp_coher_size; + + if (size == 0xffffffff) + cp_coher_size = 0xffffffff; + else + cp_coher_size = ((size + 255) >> 8); + + radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); + radeon_ring_write(rdev, sync_type); + radeon_ring_write(rdev, cp_coher_size); + radeon_ring_write(rdev, mc_addr >> 8); + radeon_ring_write(rdev, 10); /* poll interval */ +} + +/* emits 21dw + 1 surface sync = 26dw */ +static void +set_shaders(struct radeon_device *rdev) +{ + u64 gpu_addr; + u32 sq_pgm_resources; + + /* setup shader regs */ + sq_pgm_resources = (1 << 0); + + /* VS */ + gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, gpu_addr >> 8); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, sq_pgm_resources); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, 0); + + /* PS */ + gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, gpu_addr >> 8); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, sq_pgm_resources | (1 << 28)); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, 2); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, 0); + + gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; + cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); +} + +/* emits 9 + 1 sync (5) = 14*/ +static void +set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) +{ + u32 sq_vtx_constant_word2; + + sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8)); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); + radeon_ring_write(rdev, 0x460); + radeon_ring_write(rdev, gpu_addr & 0xffffffff); + radeon_ring_write(rdev, 48 - 1); + radeon_ring_write(rdev, sq_vtx_constant_word2); + radeon_ring_write(rdev, 1 << 0); + radeon_ring_write(rdev, 0); + radeon_ring_write(rdev, 0); + radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); + + if ((rdev->family == CHIP_RV610) || + (rdev->family == CHIP_RV620) || + (rdev->family == CHIP_RS780) || + (rdev->family == CHIP_RS880) || + (rdev->family == CHIP_RV710)) + cp_set_surface_sync(rdev, + PACKET3_TC_ACTION_ENA, 48, gpu_addr); + else + cp_set_surface_sync(rdev, + PACKET3_VC_ACTION_ENA, 48, gpu_addr); +} + +/* emits 9 */ +static void +set_tex_resource(struct radeon_device *rdev, + int format, int w, int h, int pitch, + u64 gpu_addr) +{ + uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; + + if (h < 1) + h = 1; + + sq_tex_resource_word0 = (1 << 0); + sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) | + ((w - 1) << 19)); + + sq_tex_resource_word1 = (format << 26); + sq_tex_resource_word1 |= ((h - 1) << 0); + + sq_tex_resource_word4 = ((1 << 14) | + (0 << 16) | + (1 << 19) | + (2 << 22) | + (3 << 25)); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); + radeon_ring_write(rdev, 0); + radeon_ring_write(rdev, sq_tex_resource_word0); + radeon_ring_write(rdev, sq_tex_resource_word1); + radeon_ring_write(rdev, gpu_addr >> 8); + radeon_ring_write(rdev, gpu_addr >> 8); + radeon_ring_write(rdev, sq_tex_resource_word4); + radeon_ring_write(rdev, 0); + radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30); +} + +/* emits 12 */ +static void +set_scissors(struct radeon_device *rdev, int x1, int y1, + int x2, int y2) +{ + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); + radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); + radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); + radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); + radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); + radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); + radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); +} + +/* emits 10 */ +static void +draw_auto(struct radeon_device *rdev) +{ + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); + radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); + radeon_ring_write(rdev, DI_PT_RECTLIST); + + radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); + radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT); + + radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); + radeon_ring_write(rdev, 1); + + radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); + radeon_ring_write(rdev, 3); + radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); + +} + +/* emits 14 */ +static void +set_default_state(struct radeon_device *rdev) +{ + u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; + u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; + int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; + int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; + int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; + u64 gpu_addr; + int dwords; + + switch (rdev->family) { + case CHIP_R600: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_RV630: + case CHIP_RV635: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 144; + num_vs_threads = 40; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_RV610: + case CHIP_RV620: + case CHIP_RS780: + case CHIP_RS880: + default: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_RV670: + num_ps_gprs = 144; + num_vs_gprs = 40; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_RV770: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 188; + num_vs_threads = 60; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 256; + num_vs_stack_entries = 256; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_RV730: + case CHIP_RV740: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 188; + num_vs_threads = 60; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_RV710: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 144; + num_vs_threads = 48; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + } + + if ((rdev->family == CHIP_RV610) || + (rdev->family == CHIP_RV620) || + (rdev->family == CHIP_RS780) || + (rdev->family == CHIP_RS780) || + (rdev->family == CHIP_RV710)) + sq_config = 0; + else + sq_config = VC_ENABLE; + + sq_config |= (DX9_CONSTS | + ALU_INST_PREFER_VECTOR | + PS_PRIO(0) | + VS_PRIO(1) | + GS_PRIO(2) | + ES_PRIO(3)); + + sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) | + NUM_VS_GPRS(num_vs_gprs) | + NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); + sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) | + NUM_ES_GPRS(num_es_gprs)); + sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) | + NUM_VS_THREADS(num_vs_threads) | + NUM_GS_THREADS(num_gs_threads) | + NUM_ES_THREADS(num_es_threads)); + sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | + NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); + sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | + NUM_ES_STACK_ENTRIES(num_es_stack_entries)); + + /* emit an IB pointing at default state */ + dwords = (rdev->r600_blit.state_len + 0xf) & ~0xf; + gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; + radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); + radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); + radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); + radeon_ring_write(rdev, dwords); + + radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); + radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); + /* SQ config */ + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); + radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); + radeon_ring_write(rdev, sq_config); + radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); + radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); + radeon_ring_write(rdev, sq_thread_resource_mgmt); + radeon_ring_write(rdev, sq_stack_resource_mgmt_1); + radeon_ring_write(rdev, sq_stack_resource_mgmt_2); +} + +static inline uint32_t i2f(uint32_t input) +{ + u32 result, i, exponent, fraction; + + if ((input & 0x3fff) == 0) + result = 0; /* 0 is a special case */ + else { + exponent = 140; /* exponent biased by 127; */ + fraction = (input & 0x3fff) << 10; /* cheat and only + handle numbers below 2^^15 */ + for (i = 0; i < 14; i++) { + if (fraction & 0x800000) + break; + else { + fraction = fraction << 1; /* keep + shifting left until top bit = 1 */ + exponent = exponent - 1; + } + } + result = exponent << 23 | (fraction & 0x7fffff); /* mask + off top bit; assumed 1 */ + } + return result; +} + +int r600_blit_init(struct radeon_device *rdev) +{ + u32 obj_size; + int r, dwords; + void *ptr; + u32 packet2s[16]; + int num_packet2s = 0; + + rdev->r600_blit.state_offset = 0; + + if (rdev->family >= CHIP_RV770) + rdev->r600_blit.state_len = r7xx_default_size; + else + rdev->r600_blit.state_len = r6xx_default_size; + + dwords = rdev->r600_blit.state_len; + while (dwords & 0xf) { + packet2s[num_packet2s++] = PACKET2(0); + dwords++; + } + + obj_size = dwords * 4; + obj_size = ALIGN(obj_size, 256); + + rdev->r600_blit.vs_offset = obj_size; + obj_size += r6xx_vs_size * 4; + obj_size = ALIGN(obj_size, 256); + + rdev->r600_blit.ps_offset = obj_size; + obj_size += r6xx_ps_size * 4; + obj_size = ALIGN(obj_size, 256); + + r = radeon_object_create(rdev, NULL, obj_size, + true, RADEON_GEM_DOMAIN_VRAM, + false, &rdev->r600_blit.shader_obj); + if (r) { + DRM_ERROR("r600 failed to allocate shader\n"); + return r; + } + + DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n", + obj_size, + rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset); + + r = radeon_object_kmap(rdev->r600_blit.shader_obj, &ptr); + if (r) { + DRM_ERROR("failed to map blit object %d\n", r); + return r; + } + + if (rdev->family >= CHIP_RV770) + memcpy_toio(ptr + rdev->r600_blit.state_offset, + r7xx_default_state, rdev->r600_blit.state_len * 4); + else + memcpy_toio(ptr + rdev->r600_blit.state_offset, + r6xx_default_state, rdev->r600_blit.state_len * 4); + if (num_packet2s) + memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), + packet2s, num_packet2s * 4); + + + memcpy(ptr + rdev->r600_blit.vs_offset, r6xx_vs, r6xx_vs_size * 4); + memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4); + + radeon_object_kunmap(rdev->r600_blit.shader_obj); + return 0; +} + +void r600_blit_fini(struct radeon_device *rdev) +{ + radeon_object_unpin(rdev->r600_blit.shader_obj); + radeon_object_unref(&rdev->r600_blit.shader_obj); +} + +int r600_vb_ib_get(struct radeon_device *rdev) +{ + int r; + r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib); + if (r) { + DRM_ERROR("failed to get IB for vertex buffer\n"); + return r; + } + + rdev->r600_blit.vb_total = 64*1024; + rdev->r600_blit.vb_used = 0; + return 0; +} + +void r600_vb_ib_put(struct radeon_device *rdev) +{ + radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence); + mutex_lock(&rdev->ib_pool.mutex); + list_add_tail(&rdev->r600_blit.vb_ib->list, &rdev->ib_pool.scheduled_ibs); + mutex_unlock(&rdev->ib_pool.mutex); + radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); +} + +int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) +{ + int r; + int ring_size, line_size; + int max_size; + /* loops of emits 64 + fence emit possible */ + int dwords_per_loop = 76, num_loops; + + r = r600_vb_ib_get(rdev); + WARN_ON(r); + + /* set_render_target emits 2 extra dwords on rv6xx */ + if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) + dwords_per_loop += 2; + + /* 8 bpp vs 32 bpp for xfer unit */ + if (size_bytes & 3) + line_size = 8192; + else + line_size = 8192*4; + + max_size = 8192 * line_size; + + /* major loops cover the max size transfer */ + num_loops = ((size_bytes + max_size) / max_size); + /* minor loops cover the extra non aligned bits */ + num_loops += ((size_bytes % line_size) ? 1 : 0); + /* calculate number of loops correctly */ + ring_size = num_loops * dwords_per_loop; + /* set default + shaders */ + ring_size += 40; /* shaders + def state */ + ring_size += 3; /* fence emit for VB IB */ + ring_size += 5; /* done copy */ + ring_size += 3; /* fence emit for done copy */ + r = radeon_ring_lock(rdev, ring_size); + WARN_ON(r); + + set_default_state(rdev); /* 14 */ + set_shaders(rdev); /* 26 */ + return 0; +} + +void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence) +{ + int r; + + radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); + radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); + /* wait for 3D idle clean */ + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); + radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); + radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); + + if (rdev->r600_blit.vb_ib) + r600_vb_ib_put(rdev); + + if (fence) + r = radeon_fence_emit(rdev, fence); + + radeon_ring_unlock_commit(rdev); +} + +void r600_kms_blit_copy(struct radeon_device *rdev, + u64 src_gpu_addr, u64 dst_gpu_addr, + int size_bytes) +{ + int max_bytes; + u64 vb_gpu_addr; + u32 *vb; + + DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr, + size_bytes, rdev->r600_blit.vb_used); + vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used); + if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) { + max_bytes = 8192; + + while (size_bytes) { + int cur_size = size_bytes; + int src_x = src_gpu_addr & 255; + int dst_x = dst_gpu_addr & 255; + int h = 1; + src_gpu_addr = src_gpu_addr & ~255; + dst_gpu_addr = dst_gpu_addr & ~255; + + if (!src_x && !dst_x) { + h = (cur_size / max_bytes); + if (h > 8192) + h = 8192; + if (h == 0) + h = 1; + else + cur_size = max_bytes; + } else { + if (cur_size > max_bytes) + cur_size = max_bytes; + if (cur_size > (max_bytes - dst_x)) + cur_size = (max_bytes - dst_x); + if (cur_size > (max_bytes - src_x)) + cur_size = (max_bytes - src_x); + } + + if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { + WARN_ON(1); + +#if 0 + r600_vb_ib_put(rdev); + + r600_nomm_put_vb(dev); + r600_nomm_get_vb(dev); + if (!dev_priv->blit_vb) + return; + set_shaders(dev); + vb = r600_nomm_get_vb_ptr(dev); +#endif + } + + vb[0] = i2f(dst_x); + vb[1] = 0; + vb[2] = i2f(src_x); + vb[3] = 0; + + vb[4] = i2f(dst_x); + vb[5] = i2f(h); + vb[6] = i2f(src_x); + vb[7] = i2f(h); + + vb[8] = i2f(dst_x + cur_size); + vb[9] = i2f(h); + vb[10] = i2f(src_x + cur_size); + vb[11] = i2f(h); + + /* src 9 */ + set_tex_resource(rdev, FMT_8, + src_x + cur_size, h, src_x + cur_size, + src_gpu_addr); + + /* 5 */ + cp_set_surface_sync(rdev, + PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); + + /* dst 23 */ + set_render_target(rdev, COLOR_8, + dst_x + cur_size, h, + dst_gpu_addr); + + /* scissors 12 */ + set_scissors(rdev, dst_x, 0, dst_x + cur_size, h); + + /* 14 */ + vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; + set_vtx_resource(rdev, vb_gpu_addr); + + /* draw 10 */ + draw_auto(rdev); + + /* 5 */ + cp_set_surface_sync(rdev, + PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, + cur_size * h, dst_gpu_addr); + + vb += 12; + rdev->r600_blit.vb_used += 12 * 4; + + src_gpu_addr += cur_size * h; + dst_gpu_addr += cur_size * h; + size_bytes -= cur_size * h; + } + } else { + max_bytes = 8192 * 4; + + while (size_bytes) { + int cur_size = size_bytes; + int src_x = (src_gpu_addr & 255); + int dst_x = (dst_gpu_addr & 255); + int h = 1; + src_gpu_addr = src_gpu_addr & ~255; + dst_gpu_addr = dst_gpu_addr & ~255; + + if (!src_x && !dst_x) { + h = (cur_size / max_bytes); + if (h > 8192) + h = 8192; + if (h == 0) + h = 1; + else + cur_size = max_bytes; + } else { + if (cur_size > max_bytes) + cur_size = max_bytes; + if (cur_size > (max_bytes - dst_x)) + cur_size = (max_bytes - dst_x); + if (cur_size > (max_bytes - src_x)) + cur_size = (max_bytes - src_x); + } + + if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { + WARN_ON(1); + } +#if 0 + if ((rdev->blit_vb->used + 48) > rdev->blit_vb->total) { + r600_nomm_put_vb(dev); + r600_nomm_get_vb(dev); + if (!rdev->blit_vb) + return; + + set_shaders(dev); + vb = r600_nomm_get_vb_ptr(dev); + } +#endif + + vb[0] = i2f(dst_x / 4); + vb[1] = 0; + vb[2] = i2f(src_x / 4); + vb[3] = 0; + + vb[4] = i2f(dst_x / 4); + vb[5] = i2f(h); + vb[6] = i2f(src_x / 4); + vb[7] = i2f(h); + + vb[8] = i2f((dst_x + cur_size) / 4); + vb[9] = i2f(h); + vb[10] = i2f((src_x + cur_size) / 4); + vb[11] = i2f(h); + + /* src 9 */ + set_tex_resource(rdev, FMT_8_8_8_8, + (src_x + cur_size) / 4, + h, (src_x + cur_size) / 4, + src_gpu_addr); + /* 5 */ + cp_set_surface_sync(rdev, + PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); + + /* dst 23 */ + set_render_target(rdev, COLOR_8_8_8_8, + dst_x + cur_size, h, + dst_gpu_addr); + + /* scissors 12 */ + set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h); + + /* Vertex buffer setup 14 */ + vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; + set_vtx_resource(rdev, vb_gpu_addr); + + /* draw 10 */ + draw_auto(rdev); + + /* 5 */ + cp_set_surface_sync(rdev, + PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, + cur_size * h, dst_gpu_addr); + + /* 78 ring dwords per loop */ + vb += 12; + rdev->r600_blit.vb_used += 12 * 4; + + src_gpu_addr += cur_size * h; + dst_gpu_addr += cur_size * h; + size_bytes -= cur_size * h; + } + } +} + diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c new file mode 100644 index 000000000000..d745e815c2e8 --- /dev/null +++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c @@ -0,0 +1,1072 @@ + +#include +#include + +const u32 r6xx_default_state[] = +{ + 0xc0002400, + 0x00000000, + 0xc0012800, + 0x80000000, + 0x80000000, + 0xc0004600, + 0x00000016, + 0xc0016800, + 0x00000010, + 0x00028000, + 0xc0016800, + 0x00000010, + 0x00008000, + 0xc0016800, + 0x00000542, + 0x07000003, + 0xc0016800, + 0x000005c5, + 0x00000000, + 0xc0016800, + 0x00000363, + 0x00000000, + 0xc0016800, + 0x0000060c, + 0x82000000, + 0xc0016800, + 0x0000060e, + 0x01020204, + 0xc0016f00, + 0x00000000, + 0x00000000, + 0xc0016f00, + 0x00000001, + 0x00000000, + 0xc0096900, + 0x0000022a, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0016900, + 0x00000004, + 0x00000000, + 0xc0016900, + 0x0000000a, + 0x00000000, + 0xc0016900, + 0x0000000b, + 0x00000000, + 0xc0016900, + 0x0000010c, + 0x00000000, + 0xc0016900, + 0x0000010d, + 0x00000000, + 0xc0016900, + 0x00000200, + 0x00000000, + 0xc0016900, + 0x00000343, + 0x00000060, + 0xc0016900, + 0x00000344, + 0x00000040, + 0xc0016900, + 0x00000351, + 0x0000aa00, + 0xc0016900, + 0x00000104, + 0x00000000, + 0xc0016900, + 0x0000010e, + 0x00000000, + 0xc0046900, + 0x00000105, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0036900, + 0x00000109, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0046900, + 0x0000030c, + 0x01000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0046900, + 0x00000048, + 0x3f800000, + 0x00000000, + 0x3f800000, + 0x3f800000, + 0xc0016900, + 0x0000008e, + 0x0000000f, + 0xc0016900, + 0x00000080, + 0x00000000, + 0xc0016900, + 0x00000083, + 0x0000ffff, + 0xc0016900, + 0x00000084, + 0x00000000, + 0xc0016900, + 0x00000085, + 0x20002000, + 0xc0016900, + 0x00000086, + 0x00000000, + 0xc0016900, + 0x00000087, + 0x20002000, + 0xc0016900, + 0x00000088, + 0x00000000, + 0xc0016900, + 0x00000089, + 0x20002000, + 0xc0016900, + 0x0000008a, + 0x00000000, + 0xc0016900, + 0x0000008b, + 0x20002000, + 0xc0016900, + 0x0000008c, + 0x00000000, + 0xc0016900, + 0x00000094, + 0x80000000, + 0xc0016900, + 0x00000095, + 0x20002000, + 0xc0026900, + 0x000000b4, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x00000096, + 0x80000000, + 0xc0016900, + 0x00000097, + 0x20002000, + 0xc0026900, + 0x000000b6, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x00000098, + 0x80000000, + 0xc0016900, + 0x00000099, + 0x20002000, + 0xc0026900, + 0x000000b8, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x0000009a, + 0x80000000, + 0xc0016900, + 0x0000009b, + 0x20002000, + 0xc0026900, + 0x000000ba, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x0000009c, + 0x80000000, + 0xc0016900, + 0x0000009d, + 0x20002000, + 0xc0026900, + 0x000000bc, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x0000009e, + 0x80000000, + 0xc0016900, + 0x0000009f, + 0x20002000, + 0xc0026900, + 0x000000be, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a0, + 0x80000000, + 0xc0016900, + 0x000000a1, + 0x20002000, + 0xc0026900, + 0x000000c0, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a2, + 0x80000000, + 0xc0016900, + 0x000000a3, + 0x20002000, + 0xc0026900, + 0x000000c2, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a4, + 0x80000000, + 0xc0016900, + 0x000000a5, + 0x20002000, + 0xc0026900, + 0x000000c4, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a6, + 0x80000000, + 0xc0016900, + 0x000000a7, + 0x20002000, + 0xc0026900, + 0x000000c6, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a8, + 0x80000000, + 0xc0016900, + 0x000000a9, + 0x20002000, + 0xc0026900, + 0x000000c8, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000aa, + 0x80000000, + 0xc0016900, + 0x000000ab, + 0x20002000, + 0xc0026900, + 0x000000ca, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000ac, + 0x80000000, + 0xc0016900, + 0x000000ad, + 0x20002000, + 0xc0026900, + 0x000000cc, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000ae, + 0x80000000, + 0xc0016900, + 0x000000af, + 0x20002000, + 0xc0026900, + 0x000000ce, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000b0, + 0x80000000, + 0xc0016900, + 0x000000b1, + 0x20002000, + 0xc0026900, + 0x000000d0, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000b2, + 0x80000000, + 0xc0016900, + 0x000000b3, + 0x20002000, + 0xc0026900, + 0x000000d2, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x00000293, + 0x00004010, + 0xc0016900, + 0x00000300, + 0x00000000, + 0xc0016900, + 0x00000301, + 0x00000000, + 0xc0016900, + 0x00000312, + 0xffffffff, + 0xc0016900, + 0x00000307, + 0x00000000, + 0xc0016900, + 0x00000308, + 0x00000000, + 0xc0016900, + 0x00000283, + 0x00000000, + 0xc0016900, + 0x00000292, + 0x00000000, + 0xc0066900, + 0x0000010f, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0016900, + 0x00000206, + 0x00000000, + 0xc0016900, + 0x00000207, + 0x00000000, + 0xc0016900, + 0x00000208, + 0x00000000, + 0xc0046900, + 0x00000303, + 0x3f800000, + 0x3f800000, + 0x3f800000, + 0x3f800000, + 0xc0016900, + 0x00000205, + 0x00000004, + 0xc0016900, + 0x00000280, + 0x00000000, + 0xc0016900, + 0x00000281, + 0x00000000, + 0xc0016900, + 0x0000037e, + 0x00000000, + 0xc0016900, + 0x00000382, + 0x00000000, + 0xc0016900, + 0x00000380, + 0x00000000, + 0xc0016900, + 0x00000383, + 0x00000000, + 0xc0016900, + 0x00000381, + 0x00000000, + 0xc0016900, + 0x00000282, + 0x00000008, + 0xc0016900, + 0x00000302, + 0x0000002d, + 0xc0016900, + 0x0000037f, + 0x00000000, + 0xc0016900, + 0x000001b2, + 0x00000000, + 0xc0016900, + 0x000001b6, + 0x00000000, + 0xc0016900, + 0x000001b7, + 0x00000000, + 0xc0016900, + 0x000001b8, + 0x00000000, + 0xc0016900, + 0x000001b9, + 0x00000000, + 0xc0016900, + 0x00000225, + 0x00000000, + 0xc0016900, + 0x00000229, + 0x00000000, + 0xc0016900, + 0x00000237, + 0x00000000, + 0xc0016900, + 0x00000100, + 0x00000800, + 0xc0016900, + 0x00000101, + 0x00000000, + 0xc0016900, + 0x00000102, + 0x00000000, + 0xc0016900, + 0x000002a8, + 0x00000000, + 0xc0016900, + 0x000002a9, + 0x00000000, + 0xc0016900, + 0x00000103, + 0x00000000, + 0xc0016900, + 0x00000284, + 0x00000000, + 0xc0016900, + 0x00000290, + 0x00000000, + 0xc0016900, + 0x00000285, + 0x00000000, + 0xc0016900, + 0x00000286, + 0x00000000, + 0xc0016900, + 0x00000287, + 0x00000000, + 0xc0016900, + 0x00000288, + 0x00000000, + 0xc0016900, + 0x00000289, + 0x00000000, + 0xc0016900, + 0x0000028a, + 0x00000000, + 0xc0016900, + 0x0000028b, + 0x00000000, + 0xc0016900, + 0x0000028c, + 0x00000000, + 0xc0016900, + 0x0000028d, + 0x00000000, + 0xc0016900, + 0x0000028e, + 0x00000000, + 0xc0016900, + 0x0000028f, + 0x00000000, + 0xc0016900, + 0x000002a1, + 0x00000000, + 0xc0016900, + 0x000002a5, + 0x00000000, + 0xc0016900, + 0x000002ac, + 0x00000000, + 0xc0016900, + 0x000002ad, + 0x00000000, + 0xc0016900, + 0x000002ae, + 0x00000000, + 0xc0016900, + 0x000002c8, + 0x00000000, + 0xc0016900, + 0x00000206, + 0x00000100, + 0xc0016900, + 0x00000204, + 0x00010000, + 0xc0036e00, + 0x00000000, + 0x00000012, + 0x00000000, + 0x00000000, + 0xc0016900, + 0x0000008f, + 0x0000000f, + 0xc0016900, + 0x000001e8, + 0x00000001, + 0xc0016900, + 0x00000202, + 0x00cc0000, + 0xc0016900, + 0x00000205, + 0x00000244, + 0xc0016900, + 0x00000203, + 0x00000210, + 0xc0016900, + 0x000001b1, + 0x00000000, + 0xc0016900, + 0x00000185, + 0x00000000, + 0xc0016900, + 0x000001b3, + 0x00000001, + 0xc0016900, + 0x000001b4, + 0x00000000, + 0xc0016900, + 0x00000191, + 0x00000b00, + 0xc0016900, + 0x000001b5, + 0x00000000, +}; + +const u32 r7xx_default_state[] = +{ + 0xc0012800, + 0x80000000, + 0x80000000, + 0xc0004600, + 0x00000016, + 0xc0016800, + 0x00000010, + 0x00028000, + 0xc0016800, + 0x00000010, + 0x00008000, + 0xc0016800, + 0x00000542, + 0x07000002, + 0xc0016800, + 0x000005c5, + 0x00000000, + 0xc0016800, + 0x00000363, + 0x00004000, + 0xc0016800, + 0x0000060c, + 0x00000000, + 0xc0016800, + 0x0000060e, + 0x00420204, + 0xc0016f00, + 0x00000000, + 0x00000000, + 0xc0016f00, + 0x00000001, + 0x00000000, + 0xc0096900, + 0x0000022a, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0016900, + 0x00000004, + 0x00000000, + 0xc0016900, + 0x0000000a, + 0x00000000, + 0xc0016900, + 0x0000000b, + 0x00000000, + 0xc0016900, + 0x0000010c, + 0x00000000, + 0xc0016900, + 0x0000010d, + 0x00000000, + 0xc0016900, + 0x00000200, + 0x00000000, + 0xc0016900, + 0x00000343, + 0x00000060, + 0xc0016900, + 0x00000344, + 0x00000000, + 0xc0016900, + 0x00000351, + 0x0000aa00, + 0xc0016900, + 0x00000104, + 0x00000000, + 0xc0016900, + 0x0000010e, + 0x00000000, + 0xc0046900, + 0x00000105, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0046900, + 0x0000030c, + 0x01000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0016900, + 0x0000008e, + 0x0000000f, + 0xc0016900, + 0x00000080, + 0x00000000, + 0xc0016900, + 0x00000083, + 0x0000ffff, + 0xc0016900, + 0x00000084, + 0x00000000, + 0xc0016900, + 0x00000085, + 0x20002000, + 0xc0016900, + 0x00000086, + 0x00000000, + 0xc0016900, + 0x00000087, + 0x20002000, + 0xc0016900, + 0x00000088, + 0x00000000, + 0xc0016900, + 0x00000089, + 0x20002000, + 0xc0016900, + 0x0000008a, + 0x00000000, + 0xc0016900, + 0x0000008b, + 0x20002000, + 0xc0016900, + 0x0000008c, + 0xaaaaaaaa, + 0xc0016900, + 0x00000094, + 0x80000000, + 0xc0016900, + 0x00000095, + 0x20002000, + 0xc0026900, + 0x000000b4, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x00000096, + 0x80000000, + 0xc0016900, + 0x00000097, + 0x20002000, + 0xc0026900, + 0x000000b6, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x00000098, + 0x80000000, + 0xc0016900, + 0x00000099, + 0x20002000, + 0xc0026900, + 0x000000b8, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x0000009a, + 0x80000000, + 0xc0016900, + 0x0000009b, + 0x20002000, + 0xc0026900, + 0x000000ba, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x0000009c, + 0x80000000, + 0xc0016900, + 0x0000009d, + 0x20002000, + 0xc0026900, + 0x000000bc, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x0000009e, + 0x80000000, + 0xc0016900, + 0x0000009f, + 0x20002000, + 0xc0026900, + 0x000000be, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a0, + 0x80000000, + 0xc0016900, + 0x000000a1, + 0x20002000, + 0xc0026900, + 0x000000c0, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a2, + 0x80000000, + 0xc0016900, + 0x000000a3, + 0x20002000, + 0xc0026900, + 0x000000c2, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a4, + 0x80000000, + 0xc0016900, + 0x000000a5, + 0x20002000, + 0xc0026900, + 0x000000c4, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a6, + 0x80000000, + 0xc0016900, + 0x000000a7, + 0x20002000, + 0xc0026900, + 0x000000c6, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a8, + 0x80000000, + 0xc0016900, + 0x000000a9, + 0x20002000, + 0xc0026900, + 0x000000c8, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000aa, + 0x80000000, + 0xc0016900, + 0x000000ab, + 0x20002000, + 0xc0026900, + 0x000000ca, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000ac, + 0x80000000, + 0xc0016900, + 0x000000ad, + 0x20002000, + 0xc0026900, + 0x000000cc, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000ae, + 0x80000000, + 0xc0016900, + 0x000000af, + 0x20002000, + 0xc0026900, + 0x000000ce, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000b0, + 0x80000000, + 0xc0016900, + 0x000000b1, + 0x20002000, + 0xc0026900, + 0x000000d0, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000b2, + 0x80000000, + 0xc0016900, + 0x000000b3, + 0x20002000, + 0xc0026900, + 0x000000d2, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x00000293, + 0x00514000, + 0xc0016900, + 0x00000300, + 0x00000000, + 0xc0016900, + 0x00000301, + 0x00000000, + 0xc0016900, + 0x00000312, + 0xffffffff, + 0xc0016900, + 0x00000307, + 0x00000000, + 0xc0016900, + 0x00000308, + 0x00000000, + 0xc0016900, + 0x00000283, + 0x00000000, + 0xc0016900, + 0x00000292, + 0x00000000, + 0xc0066900, + 0x0000010f, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0016900, + 0x00000206, + 0x00000000, + 0xc0016900, + 0x00000207, + 0x00000000, + 0xc0016900, + 0x00000208, + 0x00000000, + 0xc0046900, + 0x00000303, + 0x3f800000, + 0x3f800000, + 0x3f800000, + 0x3f800000, + 0xc0016900, + 0x00000205, + 0x00000004, + 0xc0016900, + 0x00000280, + 0x00000000, + 0xc0016900, + 0x00000281, + 0x00000000, + 0xc0016900, + 0x0000037e, + 0x00000000, + 0xc0016900, + 0x00000382, + 0x00000000, + 0xc0016900, + 0x00000380, + 0x00000000, + 0xc0016900, + 0x00000383, + 0x00000000, + 0xc0016900, + 0x00000381, + 0x00000000, + 0xc0016900, + 0x00000282, + 0x00000008, + 0xc0016900, + 0x00000302, + 0x0000002d, + 0xc0016900, + 0x0000037f, + 0x00000000, + 0xc0016900, + 0x000001b2, + 0x00000001, + 0xc0016900, + 0x000001b6, + 0x00000000, + 0xc0016900, + 0x000001b7, + 0x00000000, + 0xc0016900, + 0x000001b8, + 0x00000000, + 0xc0016900, + 0x000001b9, + 0x00000000, + 0xc0016900, + 0x00000225, + 0x00000000, + 0xc0016900, + 0x00000229, + 0x00000000, + 0xc0016900, + 0x00000237, + 0x00000000, + 0xc0016900, + 0x00000100, + 0x00000800, + 0xc0016900, + 0x00000101, + 0x00000000, + 0xc0016900, + 0x00000102, + 0x00000000, + 0xc0016900, + 0x000002a8, + 0x00000000, + 0xc0016900, + 0x000002a9, + 0x00000000, + 0xc0016900, + 0x00000103, + 0x00000000, + 0xc0016900, + 0x00000284, + 0x00000000, + 0xc0016900, + 0x00000290, + 0x00000000, + 0xc0016900, + 0x00000285, + 0x00000000, + 0xc0016900, + 0x00000286, + 0x00000000, + 0xc0016900, + 0x00000287, + 0x00000000, + 0xc0016900, + 0x00000288, + 0x00000000, + 0xc0016900, + 0x00000289, + 0x00000000, + 0xc0016900, + 0x0000028a, + 0x00000000, + 0xc0016900, + 0x0000028b, + 0x00000000, + 0xc0016900, + 0x0000028c, + 0x00000000, + 0xc0016900, + 0x0000028d, + 0x00000000, + 0xc0016900, + 0x0000028e, + 0x00000000, + 0xc0016900, + 0x0000028f, + 0x00000000, + 0xc0016900, + 0x000002a1, + 0x00000000, + 0xc0016900, + 0x000002a5, + 0x00000000, + 0xc0016900, + 0x000002ac, + 0x00000000, + 0xc0016900, + 0x000002ad, + 0x00000000, + 0xc0016900, + 0x000002ae, + 0x00000000, + 0xc0016900, + 0x000002c8, + 0x00000000, + 0xc0016900, + 0x00000206, + 0x00000100, + 0xc0016900, + 0x00000204, + 0x00010000, + 0xc0036e00, + 0x00000000, + 0x00000012, + 0x00000000, + 0x00000000, + 0xc0016900, + 0x0000008f, + 0x0000000f, + 0xc0016900, + 0x000001e8, + 0x00000001, + 0xc0016900, + 0x00000202, + 0x00cc0000, + 0xc0016900, + 0x00000205, + 0x00000244, + 0xc0016900, + 0x00000203, + 0x00000210, + 0xc0016900, + 0x000001b1, + 0x00000000, + 0xc0016900, + 0x00000185, + 0x00000000, + 0xc0016900, + 0x000001b3, + 0x00000001, + 0xc0016900, + 0x000001b4, + 0x00000000, + 0xc0016900, + 0x00000191, + 0x00000b00, + 0xc0016900, + 0x000001b5, + 0x00000000, +}; + +/* same for r6xx/r7xx */ +const u32 r6xx_vs[] = +{ + 0x00000004, + 0x81000000, + 0x0000203c, + 0x94000b08, + 0x00004000, + 0x14200b1a, + 0x00000000, + 0x00000000, + 0x3c000000, + 0x68cd1000, + 0x00080000, + 0x00000000, +}; + +const u32 r6xx_ps[] = +{ + 0x00000002, + 0x80800000, + 0x00000000, + 0x94200688, + 0x00000010, + 0x000d1000, + 0xb0800000, + 0x00000000, +}; + +const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps); +const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs); +const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state); +const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state); diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.h b/drivers/gpu/drm/radeon/r600_blit_shaders.h new file mode 100644 index 000000000000..fdc3b378cbb0 --- /dev/null +++ b/drivers/gpu/drm/radeon/r600_blit_shaders.h @@ -0,0 +1,14 @@ + +#ifndef R600_BLIT_SHADERS_H +#define R600_BLIT_SHADERS_H + +extern const u32 r6xx_ps[]; +extern const u32 r6xx_vs[]; +extern const u32 r7xx_default_state[]; +extern const u32 r6xx_default_state[]; + + +extern const u32 r6xx_ps_size, r6xx_vs_size; +extern const u32 r6xx_default_size, r7xx_default_size; + +#endif diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c index 20f17908b036..6d5a711c2e91 100644 --- a/drivers/gpu/drm/radeon/r600_cp.c +++ b/drivers/gpu/drm/radeon/r600_cp.c @@ -31,7 +31,38 @@ #include "radeon_drm.h" #include "radeon_drv.h" -#include "r600_microcode.h" +#define PFP_UCODE_SIZE 576 +#define PM4_UCODE_SIZE 1792 +#define R700_PFP_UCODE_SIZE 848 +#define R700_PM4_UCODE_SIZE 1360 + +/* Firmware Names */ +MODULE_FIRMWARE("radeon/R600_pfp.bin"); +MODULE_FIRMWARE("radeon/R600_me.bin"); +MODULE_FIRMWARE("radeon/RV610_pfp.bin"); +MODULE_FIRMWARE("radeon/RV610_me.bin"); +MODULE_FIRMWARE("radeon/RV630_pfp.bin"); +MODULE_FIRMWARE("radeon/RV630_me.bin"); +MODULE_FIRMWARE("radeon/RV620_pfp.bin"); +MODULE_FIRMWARE("radeon/RV620_me.bin"); +MODULE_FIRMWARE("radeon/RV635_pfp.bin"); +MODULE_FIRMWARE("radeon/RV635_me.bin"); +MODULE_FIRMWARE("radeon/RV670_pfp.bin"); +MODULE_FIRMWARE("radeon/RV670_me.bin"); +MODULE_FIRMWARE("radeon/RS780_pfp.bin"); +MODULE_FIRMWARE("radeon/RS780_me.bin"); +MODULE_FIRMWARE("radeon/RV770_pfp.bin"); +MODULE_FIRMWARE("radeon/RV770_me.bin"); +MODULE_FIRMWARE("radeon/RV730_pfp.bin"); +MODULE_FIRMWARE("radeon/RV730_me.bin"); +MODULE_FIRMWARE("radeon/RV710_pfp.bin"); +MODULE_FIRMWARE("radeon/RV710_me.bin"); + + +int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, + unsigned family, u32 *ib, int *l); +void r600_cs_legacy_init(void); + # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) @@ -275,11 +306,93 @@ static void r600_vm_init(struct drm_device *dev) r600_vm_flush_gart_range(dev); } -/* load r600 microcode */ +static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv) +{ + struct platform_device *pdev; + const char *chip_name; + size_t pfp_req_size, me_req_size; + char fw_name[30]; + int err; + + pdev = platform_device_register_simple("r600_cp", 0, NULL, 0); + err = IS_ERR(pdev); + if (err) { + printk(KERN_ERR "r600_cp: Failed to register firmware\n"); + return -EINVAL; + } + + switch (dev_priv->flags & RADEON_FAMILY_MASK) { + case CHIP_R600: chip_name = "R600"; break; + case CHIP_RV610: chip_name = "RV610"; break; + case CHIP_RV630: chip_name = "RV630"; break; + case CHIP_RV620: chip_name = "RV620"; break; + case CHIP_RV635: chip_name = "RV635"; break; + case CHIP_RV670: chip_name = "RV670"; break; + case CHIP_RS780: + case CHIP_RS880: chip_name = "RS780"; break; + case CHIP_RV770: chip_name = "RV770"; break; + case CHIP_RV730: + case CHIP_RV740: chip_name = "RV730"; break; + case CHIP_RV710: chip_name = "RV710"; break; + default: BUG(); + } + + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { + pfp_req_size = R700_PFP_UCODE_SIZE * 4; + me_req_size = R700_PM4_UCODE_SIZE * 4; + } else { + pfp_req_size = PFP_UCODE_SIZE * 4; + me_req_size = PM4_UCODE_SIZE * 12; + } + + DRM_INFO("Loading %s CP Microcode\n", chip_name); + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); + err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev); + if (err) + goto out; + if (dev_priv->pfp_fw->size != pfp_req_size) { + printk(KERN_ERR + "r600_cp: Bogus length %zu in firmware \"%s\"\n", + dev_priv->pfp_fw->size, fw_name); + err = -EINVAL; + goto out; + } + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); + err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev); + if (err) + goto out; + if (dev_priv->me_fw->size != me_req_size) { + printk(KERN_ERR + "r600_cp: Bogus length %zu in firmware \"%s\"\n", + dev_priv->me_fw->size, fw_name); + err = -EINVAL; + } +out: + platform_device_unregister(pdev); + + if (err) { + if (err != -EINVAL) + printk(KERN_ERR + "r600_cp: Failed to load firmware \"%s\"\n", + fw_name); + release_firmware(dev_priv->pfp_fw); + dev_priv->pfp_fw = NULL; + release_firmware(dev_priv->me_fw); + dev_priv->me_fw = NULL; + } + return err; +} + static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) { + const __be32 *fw_data; int i; + if (!dev_priv->me_fw || !dev_priv->pfp_fw) + return; + r600_do_cp_stop(dev_priv); RADEON_WRITE(R600_CP_RB_CNTL, @@ -292,115 +405,18 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) DRM_UDELAY(15000); RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); + fw_data = (const __be32 *)dev_priv->me_fw->data; RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); + for (i = 0; i < PM4_UCODE_SIZE * 3; i++) + RADEON_WRITE(R600_CP_ME_RAM_DATA, + be32_to_cpup(fw_data++)); - if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600)) { - DRM_INFO("Loading R600 CP Microcode\n"); - for (i = 0; i < PM4_UCODE_SIZE; i++) { - RADEON_WRITE(R600_CP_ME_RAM_DATA, - R600_cp_microcode[i][0]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - R600_cp_microcode[i][1]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - R600_cp_microcode[i][2]); - } - - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading R600 PFP Microcode\n"); - for (i = 0; i < PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, R600_pfp_microcode[i]); - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610)) { - DRM_INFO("Loading RV610 CP Microcode\n"); - for (i = 0; i < PM4_UCODE_SIZE; i++) { - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV610_cp_microcode[i][0]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV610_cp_microcode[i][1]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV610_cp_microcode[i][2]); - } - - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV610 PFP Microcode\n"); - for (i = 0; i < PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV610_pfp_microcode[i]); - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { - DRM_INFO("Loading RV630 CP Microcode\n"); - for (i = 0; i < PM4_UCODE_SIZE; i++) { - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV630_cp_microcode[i][0]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV630_cp_microcode[i][1]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV630_cp_microcode[i][2]); - } - - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV630 PFP Microcode\n"); - for (i = 0; i < PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV630_pfp_microcode[i]); - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620)) { - DRM_INFO("Loading RV620 CP Microcode\n"); - for (i = 0; i < PM4_UCODE_SIZE; i++) { - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV620_cp_microcode[i][0]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV620_cp_microcode[i][1]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV620_cp_microcode[i][2]); - } - - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV620 PFP Microcode\n"); - for (i = 0; i < PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV620_pfp_microcode[i]); - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { - DRM_INFO("Loading RV635 CP Microcode\n"); - for (i = 0; i < PM4_UCODE_SIZE; i++) { - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV635_cp_microcode[i][0]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV635_cp_microcode[i][1]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV635_cp_microcode[i][2]); - } - - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV635 PFP Microcode\n"); - for (i = 0; i < PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV635_pfp_microcode[i]); - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)) { - DRM_INFO("Loading RV670 CP Microcode\n"); - for (i = 0; i < PM4_UCODE_SIZE; i++) { - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV670_cp_microcode[i][0]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV670_cp_microcode[i][1]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV670_cp_microcode[i][2]); - } - - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV670 PFP Microcode\n"); - for (i = 0; i < PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]); - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { - DRM_INFO("Loading RS780/RS880 CP Microcode\n"); - for (i = 0; i < PM4_UCODE_SIZE; i++) { - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RS780_cp_microcode[i][0]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RS780_cp_microcode[i][1]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RS780_cp_microcode[i][2]); - } + fw_data = (const __be32 *)dev_priv->pfp_fw->data; + RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); + for (i = 0; i < PFP_UCODE_SIZE; i++) + RADEON_WRITE(R600_CP_PFP_UCODE_DATA, + be32_to_cpup(fw_data++)); - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RS780/RS880 PFP Microcode\n"); - for (i = 0; i < PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RS780_pfp_microcode[i]); - } RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); @@ -459,11 +475,14 @@ static void r700_vm_init(struct drm_device *dev) r600_vm_flush_gart_range(dev); } -/* load r600 microcode */ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) { + const __be32 *fw_data; int i; + if (!dev_priv->me_fw || !dev_priv->pfp_fw) + return; + r600_do_cp_stop(dev_priv); RADEON_WRITE(R600_CP_RB_CNTL, @@ -476,48 +495,18 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) DRM_UDELAY(15000); RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); + fw_data = (const __be32 *)dev_priv->pfp_fw->data; + RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); + for (i = 0; i < R700_PFP_UCODE_SIZE; i++) + RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); + RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) { - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV770/RV790 PFP Microcode\n"); - for (i = 0; i < R700_PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]); - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - - RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - DRM_INFO("Loading RV770/RV790 CP Microcode\n"); - for (i = 0; i < R700_PM4_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]); - RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)) { - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV730/RV740 PFP Microcode\n"); - for (i = 0; i < R700_PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]); - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - - RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - DRM_INFO("Loading RV730/RV740 CP Microcode\n"); - for (i = 0; i < R700_PM4_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]); - RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) { - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV710 PFP Microcode\n"); - for (i = 0; i < R700_PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV710_pfp_microcode[i]); - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - - RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - DRM_INFO("Loading RV710 CP Microcode\n"); - for (i = 0; i < R700_PM4_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_ME_RAM_DATA, RV710_cp_microcode[i]); - RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); + fw_data = (const __be32 *)dev_priv->me_fw->data; + RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); + for (i = 0; i < R700_PM4_UCODE_SIZE; i++) + RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); + RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - } RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); @@ -1874,6 +1863,8 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, DRM_DEBUG("\n"); + mutex_init(&dev_priv->cs_mutex); + r600_cs_legacy_init(); /* if we require new memory map but we don't have it fail */ if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); @@ -1905,7 +1896,7 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, /* Enable vblank on CRTC1 for older X servers */ dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; - + dev_priv->do_boxes = 0; dev_priv->cp_mode = init->cp_mode; /* We don't support anything other than bus-mastering ring mode, @@ -1991,11 +1982,11 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, } else #endif { - dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; + dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset; dev_priv->ring_rptr->handle = - (void *)dev_priv->ring_rptr->offset; + (void *)(unsigned long)dev_priv->ring_rptr->offset; dev->agp_buffer_map->handle = - (void *)dev->agp_buffer_map->offset; + (void *)(unsigned long)dev->agp_buffer_map->offset; DRM_DEBUG("dev_priv->cp_ring->handle %p\n", dev_priv->cp_ring->handle); @@ -2147,6 +2138,14 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, r600_vm_init(dev); } + if (!dev_priv->me_fw || !dev_priv->pfp_fw) { + int err = r600_cp_init_microcode(dev_priv); + if (err) { + DRM_ERROR("Failed to load firmware!\n"); + r600_do_cleanup_cp(dev); + return err; + } + } if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) r700_cp_load_microcode(dev_priv); else @@ -2291,3 +2290,239 @@ int r600_cp_dispatch_indirect(struct drm_device *dev, return 0; } + +void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + struct drm_master *master = file_priv->master; + struct drm_radeon_master_private *master_priv = master->driver_priv; + drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; + int nbox = sarea_priv->nbox; + struct drm_clip_rect *pbox = sarea_priv->boxes; + int i, cpp, src_pitch, dst_pitch; + uint64_t src, dst; + RING_LOCALS; + DRM_DEBUG("\n"); + + if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888) + cpp = 4; + else + cpp = 2; + + if (sarea_priv->pfCurrentPage == 0) { + src_pitch = dev_priv->back_pitch; + dst_pitch = dev_priv->front_pitch; + src = dev_priv->back_offset + dev_priv->fb_location; + dst = dev_priv->front_offset + dev_priv->fb_location; + } else { + src_pitch = dev_priv->front_pitch; + dst_pitch = dev_priv->back_pitch; + src = dev_priv->front_offset + dev_priv->fb_location; + dst = dev_priv->back_offset + dev_priv->fb_location; + } + + if (r600_prepare_blit_copy(dev, file_priv)) { + DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); + return; + } + for (i = 0; i < nbox; i++) { + int x = pbox[i].x1; + int y = pbox[i].y1; + int w = pbox[i].x2 - x; + int h = pbox[i].y2 - y; + + DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h); + + r600_blit_swap(dev, + src, dst, + x, y, x, y, w, h, + src_pitch, dst_pitch, cpp); + } + r600_done_blit_copy(dev); + + /* Increment the frame counter. The client-side 3D driver must + * throttle the framerate by waiting for this value before + * performing the swapbuffer ioctl. + */ + sarea_priv->last_frame++; + + BEGIN_RING(3); + R600_FRAME_AGE(sarea_priv->last_frame); + ADVANCE_RING(); +} + +int r600_cp_dispatch_texture(struct drm_device *dev, + struct drm_file *file_priv, + drm_radeon_texture_t *tex, + drm_radeon_tex_image_t *image) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + struct drm_buf *buf; + u32 *buffer; + const u8 __user *data; + int size, pass_size; + u64 src_offset, dst_offset; + + if (!radeon_check_offset(dev_priv, tex->offset)) { + DRM_ERROR("Invalid destination offset\n"); + return -EINVAL; + } + + /* this might fail for zero-sized uploads - are those illegal? */ + if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) { + DRM_ERROR("Invalid final destination offset\n"); + return -EINVAL; + } + + size = tex->height * tex->pitch; + + if (size == 0) + return 0; + + dst_offset = tex->offset; + + if (r600_prepare_blit_copy(dev, file_priv)) { + DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); + return -EAGAIN; + } + do { + data = (const u8 __user *)image->data; + pass_size = size; + + buf = radeon_freelist_get(dev); + if (!buf) { + DRM_DEBUG("EAGAIN\n"); + if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) + return -EFAULT; + return -EAGAIN; + } + + if (pass_size > buf->total) + pass_size = buf->total; + + /* Dispatch the indirect buffer. + */ + buffer = + (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); + + if (DRM_COPY_FROM_USER(buffer, data, pass_size)) { + DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size); + return -EFAULT; + } + + buf->file_priv = file_priv; + buf->used = pass_size; + src_offset = dev_priv->gart_buffers_offset + buf->offset; + + r600_blit_copy(dev, src_offset, dst_offset, pass_size); + + radeon_cp_discard_buffer(dev, file_priv->master, buf); + + /* Update the input parameters for next time */ + image->data = (const u8 __user *)image->data + pass_size; + dst_offset += pass_size; + size -= pass_size; + } while (size > 0); + r600_done_blit_copy(dev); + + return 0; +} + +/* + * Legacy cs ioctl + */ +static u32 radeon_cs_id_get(struct drm_radeon_private *radeon) +{ + /* FIXME: check if wrap affect last reported wrap & sequence */ + radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF; + if (!radeon->cs_id_scnt) { + /* increment wrap counter */ + radeon->cs_id_wcnt += 0x01000000; + /* valid sequence counter start at 1 */ + radeon->cs_id_scnt = 1; + } + return (radeon->cs_id_scnt | radeon->cs_id_wcnt); +} + +static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id) +{ + RING_LOCALS; + + *id = radeon_cs_id_get(dev_priv); + + /* SCRATCH 2 */ + BEGIN_RING(3); + R600_CLEAR_AGE(*id); + ADVANCE_RING(); + COMMIT_RING(); +} + +static int r600_ib_get(struct drm_device *dev, + struct drm_file *fpriv, + struct drm_buf **buffer) +{ + struct drm_buf *buf; + + *buffer = NULL; + buf = radeon_freelist_get(dev); + if (!buf) { + return -EBUSY; + } + buf->file_priv = fpriv; + *buffer = buf; + return 0; +} + +static void r600_ib_free(struct drm_device *dev, struct drm_buf *buf, + struct drm_file *fpriv, int l, int r) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + + if (buf) { + if (!r) + r600_cp_dispatch_indirect(dev, buf, 0, l * 4); + radeon_cp_discard_buffer(dev, fpriv->master, buf); + COMMIT_RING(); + } +} + +int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv) +{ + struct drm_radeon_private *dev_priv = dev->dev_private; + struct drm_radeon_cs *cs = data; + struct drm_buf *buf; + unsigned family; + int l, r = 0; + u32 *ib, cs_id = 0; + + if (dev_priv == NULL) { + DRM_ERROR("called with no initialization\n"); + return -EINVAL; + } + family = dev_priv->flags & RADEON_FAMILY_MASK; + if (family < CHIP_R600) { + DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n"); + return -EINVAL; + } + mutex_lock(&dev_priv->cs_mutex); + /* get ib */ + r = r600_ib_get(dev, fpriv, &buf); + if (r) { + DRM_ERROR("ib_get failed\n"); + goto out; + } + ib = dev->agp_buffer_map->handle + buf->offset; + /* now parse command stream */ + r = r600_cs_legacy(dev, data, fpriv, family, ib, &l); + if (r) { + goto out; + } + +out: + r600_ib_free(dev, buf, fpriv, l, r); + /* emit cs id sequence */ + r600_cs_id_emit(dev_priv, &cs_id); + cs->cs_id = cs_id; + mutex_unlock(&dev_priv->cs_mutex); + return r; +} diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c new file mode 100644 index 000000000000..33b89cd8743e --- /dev/null +++ b/drivers/gpu/drm/radeon/r600_cs.c @@ -0,0 +1,657 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#include "drmP.h" +#include "radeon.h" +#include "r600d.h" +#include "avivod.h" + +static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, + struct radeon_cs_reloc **cs_reloc); +static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, + struct radeon_cs_reloc **cs_reloc); +typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**); +static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm; + +/** + * r600_cs_packet_parse() - parse cp packet and point ib index to next packet + * @parser: parser structure holding parsing context. + * @pkt: where to store packet informations + * + * Assume that chunk_ib_index is properly set. Will return -EINVAL + * if packet is bigger than remaining ib size. or if packets is unknown. + **/ +int r600_cs_packet_parse(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt, + unsigned idx) +{ + struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; + uint32_t header; + + if (idx >= ib_chunk->length_dw) { + DRM_ERROR("Can not parse packet at %d after CS end %d !\n", + idx, ib_chunk->length_dw); + return -EINVAL; + } + header = ib_chunk->kdata[idx]; + pkt->idx = idx; + pkt->type = CP_PACKET_GET_TYPE(header); + pkt->count = CP_PACKET_GET_COUNT(header); + pkt->one_reg_wr = 0; + switch (pkt->type) { + case PACKET_TYPE0: + pkt->reg = CP_PACKET0_GET_REG(header); + break; + case PACKET_TYPE3: + pkt->opcode = CP_PACKET3_GET_OPCODE(header); + break; + case PACKET_TYPE2: + pkt->count = -1; + break; + default: + DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); + return -EINVAL; + } + if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { + DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", + pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); + return -EINVAL; + } + return 0; +} + +/** + * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3 + * @parser: parser structure holding parsing context. + * @data: pointer to relocation data + * @offset_start: starting offset + * @offset_mask: offset mask (to align start offset on) + * @reloc: reloc informations + * + * Check next packet is relocation packet3, do bo validation and compute + * GPU offset using the provided start. + **/ +static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, + struct radeon_cs_reloc **cs_reloc) +{ + struct radeon_cs_chunk *ib_chunk; + struct radeon_cs_chunk *relocs_chunk; + struct radeon_cs_packet p3reloc; + unsigned idx; + int r; + + if (p->chunk_relocs_idx == -1) { + DRM_ERROR("No relocation chunk !\n"); + return -EINVAL; + } + *cs_reloc = NULL; + ib_chunk = &p->chunks[p->chunk_ib_idx]; + relocs_chunk = &p->chunks[p->chunk_relocs_idx]; + r = r600_cs_packet_parse(p, &p3reloc, p->idx); + if (r) { + return r; + } + p->idx += p3reloc.count + 2; + if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { + DRM_ERROR("No packet3 for relocation for packet at %d.\n", + p3reloc.idx); + return -EINVAL; + } + idx = ib_chunk->kdata[p3reloc.idx + 1]; + if (idx >= relocs_chunk->length_dw) { + DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", + idx, relocs_chunk->length_dw); + return -EINVAL; + } + /* FIXME: we assume reloc size is 4 dwords */ + *cs_reloc = p->relocs_ptr[(idx / 4)]; + return 0; +} + +/** + * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3 + * @parser: parser structure holding parsing context. + * @data: pointer to relocation data + * @offset_start: starting offset + * @offset_mask: offset mask (to align start offset on) + * @reloc: reloc informations + * + * Check next packet is relocation packet3, do bo validation and compute + * GPU offset using the provided start. + **/ +static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, + struct radeon_cs_reloc **cs_reloc) +{ + struct radeon_cs_chunk *ib_chunk; + struct radeon_cs_chunk *relocs_chunk; + struct radeon_cs_packet p3reloc; + unsigned idx; + int r; + + if (p->chunk_relocs_idx == -1) { + DRM_ERROR("No relocation chunk !\n"); + return -EINVAL; + } + *cs_reloc = NULL; + ib_chunk = &p->chunks[p->chunk_ib_idx]; + relocs_chunk = &p->chunks[p->chunk_relocs_idx]; + r = r600_cs_packet_parse(p, &p3reloc, p->idx); + if (r) { + return r; + } + p->idx += p3reloc.count + 2; + if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { + DRM_ERROR("No packet3 for relocation for packet at %d.\n", + p3reloc.idx); + return -EINVAL; + } + idx = ib_chunk->kdata[p3reloc.idx + 1]; + if (idx >= relocs_chunk->length_dw) { + DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", + idx, relocs_chunk->length_dw); + return -EINVAL; + } + *cs_reloc = &p->relocs[0]; + (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32; + (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0]; + return 0; +} + +static int r600_packet0_check(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt, + unsigned idx, unsigned reg) +{ + switch (reg) { + case AVIVO_D1MODE_VLINE_START_END: + case AVIVO_D2MODE_VLINE_START_END: + break; + default: + printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", + reg, idx); + return -EINVAL; + } + return 0; +} + +static int r600_cs_parse_packet0(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt) +{ + unsigned reg, i; + unsigned idx; + int r; + + idx = pkt->idx + 1; + reg = pkt->reg; + for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { + r = r600_packet0_check(p, pkt, idx, reg); + if (r) { + return r; + } + } + return 0; +} + +static int r600_packet3_check(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt) +{ + struct radeon_cs_chunk *ib_chunk; + struct radeon_cs_reloc *reloc; + volatile u32 *ib; + unsigned idx; + unsigned i; + unsigned start_reg, end_reg, reg; + int r; + + ib = p->ib->ptr; + ib_chunk = &p->chunks[p->chunk_ib_idx]; + idx = pkt->idx + 1; + switch (pkt->opcode) { + case PACKET3_START_3D_CMDBUF: + if (p->family >= CHIP_RV770 || pkt->count) { + DRM_ERROR("bad START_3D\n"); + return -EINVAL; + } + break; + case PACKET3_CONTEXT_CONTROL: + if (pkt->count != 1) { + DRM_ERROR("bad CONTEXT_CONTROL\n"); + return -EINVAL; + } + break; + case PACKET3_INDEX_TYPE: + case PACKET3_NUM_INSTANCES: + if (pkt->count) { + DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n"); + return -EINVAL; + } + break; + case PACKET3_DRAW_INDEX: + if (pkt->count != 3) { + DRM_ERROR("bad DRAW_INDEX\n"); + return -EINVAL; + } + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad DRAW_INDEX\n"); + return -EINVAL; + } + ib[idx+0] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); + ib[idx+1] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff; + break; + case PACKET3_DRAW_INDEX_AUTO: + if (pkt->count != 1) { + DRM_ERROR("bad DRAW_INDEX_AUTO\n"); + return -EINVAL; + } + break; + case PACKET3_DRAW_INDEX_IMMD_BE: + case PACKET3_DRAW_INDEX_IMMD: + if (pkt->count < 2) { + DRM_ERROR("bad DRAW_INDEX_IMMD\n"); + return -EINVAL; + } + break; + case PACKET3_WAIT_REG_MEM: + if (pkt->count != 5) { + DRM_ERROR("bad WAIT_REG_MEM\n"); + return -EINVAL; + } + /* bit 4 is reg (0) or mem (1) */ + if (ib_chunk->kdata[idx+0] & 0x10) { + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad WAIT_REG_MEM\n"); + return -EINVAL; + } + ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); + ib[idx+2] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff; + } + break; + case PACKET3_SURFACE_SYNC: + if (pkt->count != 3) { + DRM_ERROR("bad SURFACE_SYNC\n"); + return -EINVAL; + } + /* 0xffffffff/0x0 is flush all cache flag */ + if (ib_chunk->kdata[idx+1] != 0xffffffff || + ib_chunk->kdata[idx+2] != 0) { + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad SURFACE_SYNC\n"); + return -EINVAL; + } + ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + } + break; + case PACKET3_EVENT_WRITE: + if (pkt->count != 2 && pkt->count != 0) { + DRM_ERROR("bad EVENT_WRITE\n"); + return -EINVAL; + } + if (pkt->count) { + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad EVENT_WRITE\n"); + return -EINVAL; + } + ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); + ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff; + } + break; + case PACKET3_EVENT_WRITE_EOP: + if (pkt->count != 4) { + DRM_ERROR("bad EVENT_WRITE_EOP\n"); + return -EINVAL; + } + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad EVENT_WRITE\n"); + return -EINVAL; + } + ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); + ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff; + break; + case PACKET3_SET_CONFIG_REG: + start_reg = (ib[idx+0] << 2) + PACKET3_SET_CONFIG_REG_OFFSET; + end_reg = 4 * pkt->count + start_reg - 4; + if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) || + (start_reg >= PACKET3_SET_CONFIG_REG_END) || + (end_reg >= PACKET3_SET_CONFIG_REG_END)) { + DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); + return -EINVAL; + } + for (i = 0; i < pkt->count; i++) { + reg = start_reg + (4 * i); + switch (reg) { + case CP_COHER_BASE: + /* use PACKET3_SURFACE_SYNC */ + return -EINVAL; + default: + break; + } + } + break; + case PACKET3_SET_CONTEXT_REG: + start_reg = (ib[idx+0] << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; + end_reg = 4 * pkt->count + start_reg - 4; + if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) || + (start_reg >= PACKET3_SET_CONTEXT_REG_END) || + (end_reg >= PACKET3_SET_CONTEXT_REG_END)) { + DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n"); + return -EINVAL; + } + for (i = 0; i < pkt->count; i++) { + reg = start_reg + (4 * i); + switch (reg) { + case DB_DEPTH_BASE: + case CB_COLOR0_BASE: + case CB_COLOR1_BASE: + case CB_COLOR2_BASE: + case CB_COLOR3_BASE: + case CB_COLOR4_BASE: + case CB_COLOR5_BASE: + case CB_COLOR6_BASE: + case CB_COLOR7_BASE: + case SQ_PGM_START_FS: + case SQ_PGM_START_ES: + case SQ_PGM_START_VS: + case SQ_PGM_START_GS: + case SQ_PGM_START_PS: + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad SET_CONTEXT_REG " + "0x%04X\n", reg); + return -EINVAL; + } + ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + break; + case VGT_DMA_BASE: + case VGT_DMA_BASE_HI: + /* These should be handled by DRAW_INDEX packet 3 */ + case VGT_STRMOUT_BASE_OFFSET_0: + case VGT_STRMOUT_BASE_OFFSET_1: + case VGT_STRMOUT_BASE_OFFSET_2: + case VGT_STRMOUT_BASE_OFFSET_3: + case VGT_STRMOUT_BASE_OFFSET_HI_0: + case VGT_STRMOUT_BASE_OFFSET_HI_1: + case VGT_STRMOUT_BASE_OFFSET_HI_2: + case VGT_STRMOUT_BASE_OFFSET_HI_3: + case VGT_STRMOUT_BUFFER_BASE_0: + case VGT_STRMOUT_BUFFER_BASE_1: + case VGT_STRMOUT_BUFFER_BASE_2: + case VGT_STRMOUT_BUFFER_BASE_3: + case VGT_STRMOUT_BUFFER_OFFSET_0: + case VGT_STRMOUT_BUFFER_OFFSET_1: + case VGT_STRMOUT_BUFFER_OFFSET_2: + case VGT_STRMOUT_BUFFER_OFFSET_3: + /* These should be handled by STRMOUT_BUFFER packet 3 */ + DRM_ERROR("bad context reg: 0x%08x\n", reg); + return -EINVAL; + default: + break; + } + } + break; + case PACKET3_SET_RESOURCE: + if (pkt->count % 7) { + DRM_ERROR("bad SET_RESOURCE\n"); + return -EINVAL; + } + start_reg = (ib[idx+0] << 2) + PACKET3_SET_RESOURCE_OFFSET; + end_reg = 4 * pkt->count + start_reg - 4; + if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) || + (start_reg >= PACKET3_SET_RESOURCE_END) || + (end_reg >= PACKET3_SET_RESOURCE_END)) { + DRM_ERROR("bad SET_RESOURCE\n"); + return -EINVAL; + } + for (i = 0; i < (pkt->count / 7); i++) { + switch (G__SQ_VTX_CONSTANT_TYPE(ib[idx+(i*7)+6+1])) { + case SQ_TEX_VTX_VALID_TEXTURE: + /* tex base */ + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad SET_RESOURCE\n"); + return -EINVAL; + } + ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + /* tex mip base */ + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad SET_RESOURCE\n"); + return -EINVAL; + } + ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + break; + case SQ_TEX_VTX_VALID_BUFFER: + /* vtx base */ + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad SET_RESOURCE\n"); + return -EINVAL; + } + ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff); + ib[idx+1+(i*7)+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff; + break; + case SQ_TEX_VTX_INVALID_TEXTURE: + case SQ_TEX_VTX_INVALID_BUFFER: + default: + DRM_ERROR("bad SET_RESOURCE\n"); + return -EINVAL; + } + } + break; + case PACKET3_SET_ALU_CONST: + start_reg = (ib[idx+0] << 2) + PACKET3_SET_ALU_CONST_OFFSET; + end_reg = 4 * pkt->count + start_reg - 4; + if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) || + (start_reg >= PACKET3_SET_ALU_CONST_END) || + (end_reg >= PACKET3_SET_ALU_CONST_END)) { + DRM_ERROR("bad SET_ALU_CONST\n"); + return -EINVAL; + } + break; + case PACKET3_SET_BOOL_CONST: + start_reg = (ib[idx+0] << 2) + PACKET3_SET_BOOL_CONST_OFFSET; + end_reg = 4 * pkt->count + start_reg - 4; + if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) || + (start_reg >= PACKET3_SET_BOOL_CONST_END) || + (end_reg >= PACKET3_SET_BOOL_CONST_END)) { + DRM_ERROR("bad SET_BOOL_CONST\n"); + return -EINVAL; + } + break; + case PACKET3_SET_LOOP_CONST: + start_reg = (ib[idx+0] << 2) + PACKET3_SET_LOOP_CONST_OFFSET; + end_reg = 4 * pkt->count + start_reg - 4; + if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) || + (start_reg >= PACKET3_SET_LOOP_CONST_END) || + (end_reg >= PACKET3_SET_LOOP_CONST_END)) { + DRM_ERROR("bad SET_LOOP_CONST\n"); + return -EINVAL; + } + break; + case PACKET3_SET_CTL_CONST: + start_reg = (ib[idx+0] << 2) + PACKET3_SET_CTL_CONST_OFFSET; + end_reg = 4 * pkt->count + start_reg - 4; + if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) || + (start_reg >= PACKET3_SET_CTL_CONST_END) || + (end_reg >= PACKET3_SET_CTL_CONST_END)) { + DRM_ERROR("bad SET_CTL_CONST\n"); + return -EINVAL; + } + break; + case PACKET3_SET_SAMPLER: + if (pkt->count % 3) { + DRM_ERROR("bad SET_SAMPLER\n"); + return -EINVAL; + } + start_reg = (ib[idx+0] << 2) + PACKET3_SET_SAMPLER_OFFSET; + end_reg = 4 * pkt->count + start_reg - 4; + if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) || + (start_reg >= PACKET3_SET_SAMPLER_END) || + (end_reg >= PACKET3_SET_SAMPLER_END)) { + DRM_ERROR("bad SET_SAMPLER\n"); + return -EINVAL; + } + break; + case PACKET3_SURFACE_BASE_UPDATE: + if (p->family >= CHIP_RV770 || p->family == CHIP_R600) { + DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); + return -EINVAL; + } + if (pkt->count) { + DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); + return -EINVAL; + } + break; + case PACKET3_NOP: + break; + default: + DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); + return -EINVAL; + } + return 0; +} + +int r600_cs_parse(struct radeon_cs_parser *p) +{ + struct radeon_cs_packet pkt; + int r; + + do { + r = r600_cs_packet_parse(p, &pkt, p->idx); + if (r) { + return r; + } + p->idx += pkt.count + 2; + switch (pkt.type) { + case PACKET_TYPE0: + r = r600_cs_parse_packet0(p, &pkt); + break; + case PACKET_TYPE2: + break; + case PACKET_TYPE3: + r = r600_packet3_check(p, &pkt); + break; + default: + DRM_ERROR("Unknown packet type %d !\n", pkt.type); + return -EINVAL; + } + if (r) { + return r; + } + } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); +#if 0 + for (r = 0; r < p->ib->length_dw; r++) { + printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]); + mdelay(1); + } +#endif + return 0; +} + +static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p) +{ + if (p->chunk_relocs_idx == -1) { + return 0; + } + p->relocs = kcalloc(1, sizeof(struct radeon_cs_reloc), GFP_KERNEL); + if (p->relocs == NULL) { + return -ENOMEM; + } + return 0; +} + +/** + * cs_parser_fini() - clean parser states + * @parser: parser structure holding parsing context. + * @error: error number + * + * If error is set than unvalidate buffer, otherwise just free memory + * used by parsing context. + **/ +static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error) +{ + unsigned i; + + kfree(parser->relocs); + for (i = 0; i < parser->nchunks; i++) { + kfree(parser->chunks[i].kdata); + } + kfree(parser->chunks); + kfree(parser->chunks_array); +} + +int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, + unsigned family, u32 *ib, int *l) +{ + struct radeon_cs_parser parser; + struct radeon_cs_chunk *ib_chunk; + struct radeon_ib fake_ib; + int r; + + /* initialize parser */ + memset(&parser, 0, sizeof(struct radeon_cs_parser)); + parser.filp = filp; + parser.rdev = NULL; + parser.family = family; + parser.ib = &fake_ib; + fake_ib.ptr = ib; + r = radeon_cs_parser_init(&parser, data); + if (r) { + DRM_ERROR("Failed to initialize parser !\n"); + r600_cs_parser_fini(&parser, r); + return r; + } + r = r600_cs_parser_relocs_legacy(&parser); + if (r) { + DRM_ERROR("Failed to parse relocation !\n"); + r600_cs_parser_fini(&parser, r); + return r; + } + /* Copy the packet into the IB, the parser will read from the + * input memory (cached) and write to the IB (which can be + * uncached). */ + ib_chunk = &parser.chunks[parser.chunk_ib_idx]; + parser.ib->length_dw = ib_chunk->length_dw; + memcpy((void *)parser.ib->ptr, ib_chunk->kdata, ib_chunk->length_dw*4); + *l = parser.ib->length_dw; + r = r600_cs_parse(&parser); + if (r) { + DRM_ERROR("Invalid command stream !\n"); + r600_cs_parser_fini(&parser, r); + return r; + } + r600_cs_parser_fini(&parser, r); + return r; +} + +void r600_cs_legacy_init(void) +{ + r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm; +} diff --git a/drivers/gpu/drm/radeon/r600_microcode.h b/drivers/gpu/drm/radeon/r600_microcode.h deleted file mode 100644 index 778c8b4b2fd9..000000000000 --- a/drivers/gpu/drm/radeon/r600_microcode.h +++ /dev/null @@ -1,23297 +0,0 @@ -/* - * Copyright 2008-2009 Advanced Micro Devices, Inc. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef R600_MICROCODE_H -#define R600_MICROCODE_H - -static const int ME_JUMP_TABLE_START = 1764; -static const int ME_JUMP_TABLE_END = 1792; - -#define PFP_UCODE_SIZE 576 -#define PM4_UCODE_SIZE 1792 -#define R700_PFP_UCODE_SIZE 848 -#define R700_PM4_UCODE_SIZE 1360 - -static const u32 R600_cp_microcode[][3] = { - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x614 }, - { 0x00000000, 0x00600000, 0x5b2 }, - { 0x00000000, 0x00600000, 0x5c5 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000020, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000021, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x0000001d, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x0000001d, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000030, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x00000010, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000030, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000032, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x0000002d, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x080 }, - { 0x0000002e, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x081 }, - { 0x00000000, 0x00400000, 0x087 }, - { 0x0000002d, 0x00203623, 0x000 }, - { 0x0000002e, 0x00203624, 0x000 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x087 }, - { 0x00000000, 0x00600000, 0x5ed }, - { 0x00000000, 0x00600000, 0x5e1 }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08a }, - { 0x00000018, 0xc0403620, 0x090 }, - { 0x00000000, 0x2ee00000, 0x08e }, - { 0x00000000, 0x2ce00000, 0x08d }, - { 0x00000002, 0x00400e2d, 0x08f }, - { 0x00000003, 0x00400e2d, 0x08f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000018, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x095 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x09d }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09b }, - { 0x00000000, 0x2ce00000, 0x09a }, - { 0x00000002, 0x00400e2d, 0x09c }, - { 0x00000003, 0x00400e2d, 0x09c }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a4 }, - { 0x0000001c, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x0000001b, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0db }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x28c }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x128 }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0c5 }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0d6 }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0d4 }, - { 0x00000013, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0cf }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0ce }, - { 0x00003f00, 0x00400c11, 0x0d0 }, - { 0x00001f00, 0x00400c11, 0x0d0 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0d6 }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00284a22, 0x000 }, - { 0x00000030, 0x00200e2d, 0x000 }, - { 0x0000002e, 0x0020122d, 0x000 }, - { 0x00000000, 0x002f0083, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e3 }, - { 0x00000000, 0x00600000, 0x5e7 }, - { 0x00000000, 0x00400000, 0x0e4 }, - { 0x00000000, 0x00600000, 0x5ea }, - { 0x00000007, 0x0020222d, 0x000 }, - { 0x00000005, 0x00220e22, 0x000 }, - { 0x00100000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x000000ef, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x0000001d, 0x00200e2d, 0x000 }, - { 0x00000003, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x0f1 }, - { 0x0000000b, 0x00210228, 0x000 }, - { 0x00000000, 0x14c00000, 0x0f1 }, - { 0x00000400, 0x00292228, 0x000 }, - { 0x0000001a, 0x00203628, 0x000 }, - { 0x0000001c, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x0f6 }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000001e, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x104 }, - { 0x0000a30f, 0x00204411, 0x000 }, - { 0x00000013, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0fd }, - { 0xffffffff, 0x00404811, 0x104 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x100 }, - { 0x0000ffff, 0x00404811, 0x104 }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x103 }, - { 0x000000ff, 0x00404811, 0x104 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0002c400, 0x00204411, 0x000 }, - { 0x0000001f, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x10b }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000019, 0x00203623, 0x000 }, - { 0x00000018, 0x40224a20, 0x000 }, - { 0x00000010, 0xc0424a20, 0x10d }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000019, 0x00203623, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000000a, 0x00201011, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x114 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00531224, 0x110 }, - { 0xffbfffff, 0x00283a2e, 0x000 }, - { 0x0000001b, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x127 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0x00000018, 0x00220e30, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e00e, 0x00204411, 0x000 }, - { 0x07f8ff08, 0x00204811, 0x000 }, - { 0x00000000, 0x00294a23, 0x000 }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00800000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204806, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x614 }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x613 }, - { 0x00000004, 0x00404c11, 0x12e }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x2fe }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x19f }, - { 0x00000000, 0x00600000, 0x151 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40280620, 0x000 }, - { 0x00000010, 0xc0210a20, 0x000 }, - { 0x00000000, 0x00341461, 0x000 }, - { 0x00000000, 0x00741882, 0x2a4 }, - { 0x0001a1fd, 0x00604411, 0x2c9 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x138 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x2fe }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x19f }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x151 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0681a20, 0x2a4 }, - { 0x0001a1fd, 0x00604411, 0x2c9 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x149 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000001, 0x00300a2f, 0x000 }, - { 0x00000001, 0x00210a22, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600000, 0x17c }, - { 0x00000000, 0x00600000, 0x18d }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00202c08, 0x000 }, - { 0x00000000, 0x00202411, 0x000 }, - { 0x00000000, 0x00202811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000002, 0x00221e29, 0x000 }, - { 0x00000000, 0x007048eb, 0x189 }, - { 0x00000000, 0x00600000, 0x2a4 }, - { 0x00000001, 0x40330620, 0x000 }, - { 0x00000000, 0xc0302409, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x28c }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x173 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000001, 0x00530621, 0x16f }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0604800, 0x184 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000013, 0x0020062d, 0x000 }, - { 0x00000000, 0x0078042a, 0x2e4 }, - { 0x00000000, 0x00202809, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x165 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000210, 0x00600411, 0x2fe }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x181 }, - { 0x0000001b, 0xc0203620, 0x000 }, - { 0x0000001c, 0xc0203620, 0x000 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x46000000, 0x00600811, 0x19f }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x188 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00804811, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40281620, 0x000 }, - { 0x00000010, 0xc0811a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000008, 0x00221e30, 0x000 }, - { 0x00000032, 0x00201a2d, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfffbff09, 0x00204811, 0x000 }, - { 0x00000011, 0x0020222d, 0x000 }, - { 0x00001fff, 0x00294a28, 0x000 }, - { 0x00000006, 0x0020222d, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000100, 0x00201811, 0x000 }, - { 0x00000008, 0x00621e28, 0x128 }, - { 0x00000008, 0x00822228, 0x000 }, - { 0x0002c000, 0x00204411, 0x000 }, - { 0x0000001b, 0x00600e2d, 0x1aa }, - { 0x0000001c, 0x00600e2d, 0x1aa }, - { 0x0000c008, 0x00204411, 0x000 }, - { 0x0000001d, 0x00200e2d, 0x000 }, - { 0x00000000, 0x14c00000, 0x1a6 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x39000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00804802, 0x000 }, - { 0x00000020, 0x00202e2d, 0x000 }, - { 0x00000000, 0x003b0d63, 0x000 }, - { 0x00000008, 0x00224a23, 0x000 }, - { 0x00000010, 0x00224a23, 0x000 }, - { 0x00000018, 0x00224a23, 0x000 }, - { 0x00000000, 0x00804803, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x2fe }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x19f }, - { 0x00000007, 0x0021062f, 0x000 }, - { 0x00000019, 0x00200a2d, 0x000 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000ffff, 0x40282220, 0x000 }, - { 0x0000000f, 0x00262228, 0x000 }, - { 0x00000010, 0x40212620, 0x000 }, - { 0x0000000f, 0x00262629, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1cd }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000081, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000080, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1c9 }, - { 0x00000000, 0x00600000, 0x1d6 }, - { 0x00000001, 0x00531e27, 0x1c5 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000001f, 0x00280a22, 0x000 }, - { 0x0000001f, 0x00282a2a, 0x000 }, - { 0x00000001, 0x00530621, 0x1be }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000002, 0x00304a2f, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000001, 0x00301e2f, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x1d6 }, - { 0x00000001, 0x00531e27, 0x1d2 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x0000000f, 0x00260e23, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000000f, 0x00261224, 0x000 }, - { 0x00000000, 0x00201411, 0x000 }, - { 0x00000000, 0x00601811, 0x2a4 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022b, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1e5 }, - { 0x00000010, 0x00221628, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a29, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x0020480a, 0x000 }, - { 0x00000000, 0x00202c11, 0x000 }, - { 0x00000010, 0x00221623, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a24, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x00731503, 0x1f2 }, - { 0x00000000, 0x00201805, 0x000 }, - { 0x00000000, 0x00731524, 0x1f2 }, - { 0x00000000, 0x002d14c5, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00000000, 0x00202003, 0x000 }, - { 0x00000000, 0x00802404, 0x000 }, - { 0x0000000f, 0x00210225, 0x000 }, - { 0x00000000, 0x14c00000, 0x613 }, - { 0x00000000, 0x002b1405, 0x000 }, - { 0x00000001, 0x00901625, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x2fe }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x19f }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00294a22, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a21, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000ffff, 0x40281220, 0x000 }, - { 0x00000010, 0xc0211a20, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211620, 0x000 }, - { 0x00000000, 0x00741465, 0x2a4 }, - { 0x0001a1fd, 0x00604411, 0x2c9 }, - { 0x00000001, 0x00330621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0cc00000, 0x206 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x1ff }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x5c5 }, - { 0x00000000, 0x0040040f, 0x200 }, - { 0x00000000, 0x00600000, 0x5b2 }, - { 0x00000000, 0x00600000, 0x5c5 }, - { 0x00000210, 0x00600411, 0x2fe }, - { 0x00000000, 0x00600000, 0x18d }, - { 0x00000000, 0x00600000, 0x189 }, - { 0x00000000, 0x00600000, 0x2a4 }, - { 0x00000000, 0x00600000, 0x28c }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x21f }, - { 0x00000000, 0xc0404800, 0x21c }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x00600411, 0x2e4 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x5b2 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000018, 0x40210a20, 0x000 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x235 }, - { 0x0000001a, 0x0020222d, 0x000 }, - { 0x00080101, 0x00292228, 0x000 }, - { 0x0000001a, 0x00203628, 0x000 }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x23a }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000010, 0x00600411, 0x2fe }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x19f }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00000000, 0x00600000, 0x265 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0x00000001, 0x00211e27, 0x000 }, - { 0x00000000, 0x14e00000, 0x253 }, - { 0x00000018, 0x00201e2d, 0x000 }, - { 0x0000ffff, 0x00281e27, 0x000 }, - { 0x00000000, 0x00341c27, 0x000 }, - { 0x00000000, 0x12c00000, 0x248 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e5, 0x000 }, - { 0x00000000, 0x08c00000, 0x24b }, - { 0x00000000, 0x00201407, 0x000 }, - { 0x00000018, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00211e27, 0x000 }, - { 0x00000000, 0x00341c47, 0x000 }, - { 0x00000000, 0x12c00000, 0x250 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x08c00000, 0x253 }, - { 0x00000000, 0x00201807, 0x000 }, - { 0x00000000, 0x00600000, 0x2aa }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000000, 0x00342023, 0x000 }, - { 0x00000000, 0x12c00000, 0x25b }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x25a }, - { 0x00000016, 0x00404811, 0x25f }, - { 0x00000018, 0x00404811, 0x25f }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x25e }, - { 0x00000017, 0x00404811, 0x25f }, - { 0x00000019, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00604411, 0x2d2 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x23f }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000010, 0x40210620, 0x000 }, - { 0x0000ffff, 0xc0280a20, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0881a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x614 }, - { 0x00000000, 0x00600000, 0x5b2 }, - { 0x00000000, 0xc0600000, 0x28c }, - { 0x00000005, 0x00200a2d, 0x000 }, - { 0x00000008, 0x00220a22, 0x000 }, - { 0x00000034, 0x00201a2d, 0x000 }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00007000, 0x00281e27, 0x000 }, - { 0x00000000, 0x00311ce6, 0x000 }, - { 0x00000033, 0x00201a2d, 0x000 }, - { 0x0000000c, 0x00221a26, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x06e00000, 0x27b }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000034, 0x00203623, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00691ce2, 0x128 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x286 }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000024, 0x00403627, 0x000 }, - { 0x0000000c, 0xc0220a20, 0x000 }, - { 0x00000032, 0x00203622, 0x000 }, - { 0x00000031, 0xc0403620, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000009, 0x00204811, 0x000 }, - { 0xa1000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000029, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce3, 0x000 }, - { 0x00000029, 0x00203627, 0x000 }, - { 0x0000002a, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce4, 0x000 }, - { 0x0000002a, 0x00203627, 0x000 }, - { 0x0000002b, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a3, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x0000002b, 0x00203627, 0x000 }, - { 0x0000002c, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x0000002c, 0x00803627, 0x000 }, - { 0x00000029, 0x00203623, 0x000 }, - { 0x0000002a, 0x00203624, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x0000002b, 0x00203627, 0x000 }, - { 0x00000000, 0x00311cc4, 0x000 }, - { 0x0000002c, 0x00803627, 0x000 }, - { 0x00000022, 0x00203627, 0x000 }, - { 0x00000023, 0x00203628, 0x000 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14c00000, 0x2c5 }, - { 0x00000000, 0x00400000, 0x2c2 }, - { 0x00000022, 0x00203627, 0x000 }, - { 0x00000023, 0x00203628, 0x000 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2c2 }, - { 0x00000003, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2c5 }, - { 0x0000002b, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e1, 0x000 }, - { 0x00000000, 0x02c00000, 0x2c5 }, - { 0x00000029, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a1, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2c5 }, - { 0x0000002c, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e2, 0x000 }, - { 0x00000000, 0x02c00000, 0x2c5 }, - { 0x0000002a, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2c5 }, - { 0x00000000, 0x00600000, 0x5ed }, - { 0x00000000, 0x00600000, 0x29e }, - { 0x00000000, 0x00400000, 0x2c7 }, - { 0x00000000, 0x00600000, 0x29e }, - { 0x00000000, 0x00600000, 0x5e4 }, - { 0x00000000, 0x00400000, 0x2c7 }, - { 0x00000000, 0x00600000, 0x290 }, - { 0x00000000, 0x00400000, 0x2c7 }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000023, 0x0080222d, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca1, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x003808c5, 0x000 }, - { 0x00000000, 0x00300841, 0x000 }, - { 0x00000001, 0x00220a22, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x0000001d, 0x0020222d, 0x000 }, - { 0x00000000, 0x14c00000, 0x301 }, - { 0xffffffef, 0x00280621, 0x000 }, - { 0x0000001a, 0x0020222d, 0x000 }, - { 0x0000f8e0, 0x00204411, 0x000 }, - { 0x00000000, 0x00294901, 0x000 }, - { 0x00000000, 0x00894901, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00804811, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x97000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00002257, 0x00204411, 0x000 }, - { 0x00000003, 0xc0484a20, 0x000 }, - { 0x0000225d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x5c5 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x00000001, 0x40304a20, 0x000 }, - { 0x00000002, 0xc0304a20, 0x000 }, - { 0x00000001, 0x00530a22, 0x334 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000017, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x614 }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x33d }, - { 0x00000014, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x351 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000016, 0x00604811, 0x35e }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x355 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00404811, 0x349 }, - { 0x00000028, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x349 }, - { 0x00002104, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x00000035, 0x00203626, 0x000 }, - { 0x00000049, 0x00201811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0cc00000, 0x360 }, - { 0x00000035, 0x00801a2d, 0x000 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x00000015, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x376 }, - { 0x0000001e, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x380 }, - { 0x00000020, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x38c }, - { 0x0000000f, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x398 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x398 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x39a }, - { 0x00000016, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x39f }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x08000000, 0x00290a22, 0x000 }, - { 0x00000003, 0x40210e20, 0x000 }, - { 0x0000000c, 0xc0211220, 0x000 }, - { 0x00080000, 0x00281224, 0x000 }, - { 0x00000014, 0xc0221620, 0x000 }, - { 0x00000000, 0x002914a4, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x002948a2, 0x000 }, - { 0x0000a1fe, 0x00204411, 0x000 }, - { 0x00000000, 0x00404803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000015, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x614 }, - { 0x00000015, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x382 }, - { 0x0000210e, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x614 }, - { 0x00000003, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x38e }, - { 0x00002108, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00404811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000006, 0x00404811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000016, 0x00604811, 0x35e }, - { 0x00000016, 0x00404811, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x0000001d, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x3b9 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000017, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x614 }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x3ab }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0xbabecafe, 0x00204811, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000004, 0x00404811, 0x000 }, - { 0x00002170, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000a, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3be }, - { 0x8c000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00003fff, 0x40280a20, 0x000 }, - { 0x80000000, 0x40280e20, 0x000 }, - { 0x40000000, 0xc0281220, 0x000 }, - { 0x00040000, 0x00694622, 0x614 }, - { 0x00000000, 0x00201410, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3cc }, - { 0x00000000, 0xc0401800, 0x3cf }, - { 0x00003fff, 0xc0281a20, 0x000 }, - { 0x00040000, 0x00694626, 0x614 }, - { 0x00000000, 0x00201810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3d2 }, - { 0x00000000, 0xc0401c00, 0x3d5 }, - { 0x00003fff, 0xc0281e20, 0x000 }, - { 0x00040000, 0x00694627, 0x614 }, - { 0x00000000, 0x00201c10, 0x000 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0x002820c5, 0x000 }, - { 0x00000000, 0x004948e8, 0x000 }, - { 0xa5800000, 0x00200811, 0x000 }, - { 0x00002000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x3fd }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x0000001f, 0xc0210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x3e2 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000ffff, 0xc0481220, 0x3ea }, - { 0xa7800000, 0x00200811, 0x000 }, - { 0x0000a000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x3fd }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00304883, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x83000000, 0x00604411, 0x3fd }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xa9800000, 0x00200811, 0x000 }, - { 0x0000c000, 0x00400c11, 0x3e5 }, - { 0xab800000, 0x00200811, 0x000 }, - { 0x0000f8e0, 0x00400c11, 0x3e5 }, - { 0xad800000, 0x00200811, 0x000 }, - { 0x0000f880, 0x00400c11, 0x3e5 }, - { 0xb3800000, 0x00200811, 0x000 }, - { 0x0000f3fc, 0x00400c11, 0x3e5 }, - { 0xaf800000, 0x00200811, 0x000 }, - { 0x0000e000, 0x00400c11, 0x3e5 }, - { 0xb1800000, 0x00200811, 0x000 }, - { 0x0000f000, 0x00400c11, 0x3e5 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00002148, 0x00204811, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00182000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0018a000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0018c000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0018f8e0, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0018f880, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0018e000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0018f000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0018f3fc, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x86000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x614 }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00404c02, 0x42e }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x00000000, 0xc0201400, 0x000 }, - { 0x00000000, 0xc0201800, 0x000 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x43c }, - { 0x00000000, 0xc0202000, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x00000010, 0x00280a23, 0x000 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x444 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x614 }, - { 0x00000000, 0x00400000, 0x44d }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x1ac00000, 0x449 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x44c }, - { 0x00000000, 0x002824f0, 0x000 }, - { 0x00000007, 0x00280a23, 0x000 }, - { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x454 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x04e00000, 0x46d }, - { 0x00000000, 0x00400000, 0x47a }, - { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x459 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x02e00000, 0x46d }, - { 0x00000000, 0x00400000, 0x47a }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x45e }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ce00000, 0x46d }, - { 0x00000000, 0x00400000, 0x47a }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x463 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46d }, - { 0x00000000, 0x00400000, 0x47a }, - { 0x00000005, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x468 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x06e00000, 0x46d }, - { 0x00000000, 0x00400000, 0x47a }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46d }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x08e00000, 0x46d }, - { 0x00000000, 0x00400000, 0x47a }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x000 }, - { 0x00000008, 0x00210a23, 0x000 }, - { 0x00000000, 0x14c00000, 0x477 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x480 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x00404c08, 0x43c }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000011, 0x40211220, 0x000 }, - { 0x00000012, 0x40211620, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00210225, 0x000 }, - { 0x00000000, 0x14e00000, 0x48a }, - { 0x00040000, 0xc0494a20, 0x48b }, - { 0xfffbffff, 0xc0284a20, 0x000 }, - { 0x00000000, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x497 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000c, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x493 }, - { 0xa0000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000004, 0x00204811, 0x000 }, - { 0x0000216b, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000216c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00400000, 0x491 }, - { 0x00000000, 0xc0210a20, 0x000 }, - { 0x00000000, 0x14c00000, 0x4ae }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1ac00000, 0x4a9 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x4ac }, - { 0x00000000, 0x00400000, 0x4b2 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0xc0294620, 0x000 }, - { 0x00000000, 0xc0600000, 0x614 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x4b9 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0404810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x614 }, - { 0x00000000, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x4bb }, - { 0x00002180, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000003, 0x00333e2f, 0x000 }, - { 0x00000001, 0x00210221, 0x000 }, - { 0x00000000, 0x14e00000, 0x4eb }, - { 0x00000035, 0x00200a2d, 0x000 }, - { 0x00040000, 0x18e00c11, 0x4da }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xd8c04800, 0x4ce }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000036, 0x0020122d, 0x000 }, - { 0x00000000, 0x00290c83, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000011, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00400000, 0x491 }, - { 0x00000035, 0xc0203620, 0x000 }, - { 0x00000036, 0xc0403620, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0xe0000000, 0xc0484a20, 0x000 }, - { 0x0000000f, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x4f2 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0xd9000000, 0x000 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000002, 0x00204811, 0x000 }, - { 0x000000ff, 0x00280e30, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x4f6 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x14c00000, 0x50b }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000024, 0x00203623, 0x000 }, - { 0x00000034, 0x00203623, 0x000 }, - { 0x00000032, 0x00203623, 0x000 }, - { 0x00000031, 0x00203623, 0x000 }, - { 0x0000001d, 0x00203623, 0x000 }, - { 0x0000002d, 0x00203623, 0x000 }, - { 0x0000002e, 0x00203623, 0x000 }, - { 0x0000001b, 0x00203623, 0x000 }, - { 0x0000001c, 0x00203623, 0x000 }, - { 0xffffe000, 0x00200c11, 0x000 }, - { 0x00000029, 0x00203623, 0x000 }, - { 0x0000002a, 0x00203623, 0x000 }, - { 0x00001fff, 0x00200c11, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x0000002c, 0x00203623, 0x000 }, - { 0xf1ffffff, 0x00283a2e, 0x000 }, - { 0x0000001a, 0xc0220e20, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000033, 0x40203620, 0x000 }, - { 0x87000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x9d000000, 0x00204411, 0x000 }, - { 0x0000001f, 0x40214a20, 0x000 }, - { 0x96000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x0000001f, 0x00211624, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000003, 0x00281e23, 0x000 }, - { 0x00000008, 0x00222223, 0x000 }, - { 0xfffff000, 0x00282228, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x00000027, 0x00203628, 0x000 }, - { 0x00000018, 0x00211e23, 0x000 }, - { 0x00000028, 0x00203627, 0x000 }, - { 0x00000002, 0x00221624, 0x000 }, - { 0x00000000, 0x003014a8, 0x000 }, - { 0x00000026, 0x00203625, 0x000 }, - { 0x00000003, 0x00211a24, 0x000 }, - { 0x10000000, 0x00281a26, 0x000 }, - { 0xefffffff, 0x00283a2e, 0x000 }, - { 0x00000000, 0x004938ce, 0x602 }, - { 0x00000001, 0x40280a20, 0x000 }, - { 0x00000006, 0x40280e20, 0x000 }, - { 0x00000300, 0xc0281220, 0x000 }, - { 0x00000008, 0x00211224, 0x000 }, - { 0x00000000, 0xc0201620, 0x000 }, - { 0x00000000, 0xc0201a20, 0x000 }, - { 0x00000000, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x541 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x614 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00020000, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x549 }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x55b }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x549 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x614 }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x55b }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x54d }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x55b }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x559 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1ac00000, 0x554 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x557 }, - { 0x00000000, 0x00401c10, 0x55b }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x55d }, - { 0x00000000, 0x00600000, 0x5a4 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56d }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x614 }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x56b }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x57d }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x614 }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x57b }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x58d }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x614 }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x58b }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x614 }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x599 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x59f }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5a4 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x5b7 }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x00000034, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x5bb }, - { 0x00000000, 0x00600000, 0x5a4 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x5bb }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x0000217a, 0xc0204411, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x5e1 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000016, 0x00604811, 0x35e }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x614 }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x5dc }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x0000001d, 0x00803627, 0x000 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x0000001d, 0x00803627, 0x000 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x0000001d, 0x00803627, 0x000 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x0000001d, 0x00803627, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000016, 0x00604811, 0x35e }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0x00ffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x614 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x613 }, - { 0x00000010, 0x00404c11, 0x5f9 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x00000025, 0x00200a2d, 0x000 }, - { 0x00000026, 0x00200e2d, 0x000 }, - { 0x00000027, 0x0020122d, 0x000 }, - { 0x00000028, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x612 }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x00000027, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x614 }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x617 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x2fe }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x19f }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000029, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x0000002c, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000002a, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000002b, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x013304ef, 0x059b0239, 0x000 }, - { 0x01b00159, 0x0425059b, 0x000 }, - { 0x021201f6, 0x02390142, 0x000 }, - { 0x0210022e, 0x0289022a, 0x000 }, - { 0x03c2059b, 0x059b059b, 0x000 }, - { 0x05cd05ce, 0x0308059b, 0x000 }, - { 0x059b05a0, 0x03090329, 0x000 }, - { 0x0313026b, 0x032b031d, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b052c, 0x059b059b, 0x000 }, - { 0x03a5059b, 0x04a2032d, 0x000 }, - { 0x04810433, 0x0423059b, 0x000 }, - { 0x04bb04ed, 0x042704c8, 0x000 }, - { 0x043304f4, 0x033a0365, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b059b, 0x05b905a2, 0x000 }, - { 0x059b059b, 0x0007059b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x03e303d8, 0x03f303f1, 0x000 }, - { 0x03f903f5, 0x03f703fb, 0x000 }, - { 0x04070403, 0x040f040b, 0x000 }, - { 0x04170413, 0x041f041b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x00020600, 0x06190006, 0x000 }, -}; - -static const u32 R600_pfp_microcode[] = { -0xd40071, -0xd40072, -0xca0400, -0xa00000, -0x7e828b, -0x800003, -0xca0400, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d4, -0xd5c01e, -0xca0800, -0x80001b, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000d, -0xc41838, -0xe4013e, -0xd4001e, -0x80000d, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800054, -0xd40073, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800002, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800002, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b9, -0xd4c01e, -0xc6083e, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800002, -0x062001, -0xc6083e, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x80007a, -0xd42013, -0xc6083e, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008e, -0x000000, -0xc41432, -0xc6183e, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800002, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xd40073, -0xe4015e, -0xd4001e, -0x8001b9, -0x062001, -0x0a2001, -0xd60074, -0xc40836, -0xc61040, -0x988007, -0xcc3835, -0x95010f, -0xd4001f, -0xd46062, -0x800002, -0xd42062, -0xcc1433, -0x8401bc, -0xd40070, -0xd5401e, -0x800002, -0xee001e, -0xca0c00, -0xca1000, -0xd4c01a, -0x8401bc, -0xd5001a, -0xcc0443, -0x35101f, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b9, -0xd4006d, -0x344401, -0xcc0c44, -0x98403a, -0xcc2c46, -0x958004, -0xcc0445, -0x8001b9, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f3, -0xcc1003, -0x98801b, -0x04380c, -0x8400f3, -0xcc1003, -0x988017, -0x043808, -0x8400f3, -0xcc1003, -0x988013, -0x043804, -0x8400f3, -0xcc1003, -0x988014, -0xcc1047, -0x9a8009, -0xcc1448, -0x9840da, -0xd4006d, -0xcc1844, -0xd5001a, -0xd5401a, -0x8000cc, -0xd5801a, -0x96c0d3, -0xd4006d, -0x8001b9, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800002, -0xec007f, -0x9ac0ca, -0xd4006d, -0x8001b9, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b9, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809c, -0xd4006d, -0x98409a, -0xd4006e, -0xcc0847, -0xcc0c48, -0xcc1044, -0xd4801a, -0xd4c01a, -0x800104, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d8, -0xca0c00, -0xd4401e, -0x800002, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800002, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bc, -0x000000, -0x8401bc, -0xd7806f, -0x800002, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902af, -0x7c738b, -0x8401bc, -0xd7806f, -0x800002, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984296, -0x000000, -0x800164, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800002, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc1049, -0x990004, -0xd40071, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800002, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x95001f, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x7d8380, -0xd5806f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0x8001b9, -0xd60074, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800002, -0xee001e, -0x800002, -0xee001f, -0xd4001f, -0x800002, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010174, -0x02017b, -0x030090, -0x040080, -0x050005, -0x060040, -0x070033, -0x08012f, -0x090047, -0x0a0037, -0x1001b7, -0x1700a4, -0x22013d, -0x23014c, -0x2000b5, -0x240128, -0x27004e, -0x28006b, -0x2a0061, -0x2b0053, -0x2f0066, -0x320088, -0x340182, -0x3c0159, -0x3f0073, -0x41018f, -0x440131, -0x550176, -0x56017d, -0x60000c, -0x610035, -0x620039, -0x630039, -0x640039, -0x650039, -0x660039, -0x670039, -0x68003b, -0x690042, -0x6a0049, -0x6b0049, -0x6c0049, -0x6d0049, -0x6e0049, -0x6f0049, -0x7301b7, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -}; - -static const u32 RV610_cp_microcode[][3] = { - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x668 }, - { 0x00000000, 0x00600000, 0x65c }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 0x00400c11, 0x0d6 }, - { 0x00001f00, 0x00400c11, 0x0d6 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0dc }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00280e22, 0x000 }, - { 0x00000080, 0x00294a23, 0x000 }, - { 0x00000027, 0x00200e2d, 0x000 }, - { 0x00000026, 0x0020122d, 0x000 }, - { 0x00000000, 0x002f0083, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0ea }, - { 0x00000000, 0x00600000, 0x662 }, - { 0x00000000, 0x00400000, 0x0eb }, - { 0x00000000, 0x00600000, 0x665 }, - { 0x00000007, 0x0020222d, 0x000 }, - { 0x00000005, 0x00220e22, 0x000 }, - { 0x00100000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x000000ef, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000003, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x0f8 }, - { 0x0000000b, 0x00210228, 0x000 }, - { 0x00000000, 0x14c00000, 0x0f8 }, - { 0x00000400, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000001c, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x0fd }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000001e, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x10b }, - { 0x0000a30f, 0x00204411, 0x000 }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x104 }, - { 0xffffffff, 0x00404811, 0x10b }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x107 }, - { 0x0000ffff, 0x00404811, 0x10b }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x10a }, - { 0x000000ff, 0x00404811, 0x10b }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0002c400, 0x00204411, 0x000 }, - { 0x0000001f, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x112 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000018, 0x40224a20, 0x000 }, - { 0x00000010, 0xc0424a20, 0x114 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000000a, 0x00201011, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x11b }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00531224, 0x117 }, - { 0xffbfffff, 0x00283a2e, 0x000 }, - { 0x0000001b, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x12e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0x00000018, 0x00220e30, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e00e, 0x00204411, 0x000 }, - { 0x07f8ff08, 0x00204811, 0x000 }, - { 0x00000000, 0x00294a23, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00800000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204806, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x68c }, - { 0x00000004, 0x00404c11, 0x135 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000001c, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x13c }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40280620, 0x000 }, - { 0x00000010, 0xc0210a20, 0x000 }, - { 0x00000000, 0x00341461, 0x000 }, - { 0x00000000, 0x00741882, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x147 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0681a20, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x158 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000001, 0x00300a2f, 0x000 }, - { 0x00000001, 0x00210a22, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600000, 0x18f }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00202c08, 0x000 }, - { 0x00000000, 0x00202411, 0x000 }, - { 0x00000000, 0x00202811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000002, 0x00221e29, 0x000 }, - { 0x00000000, 0x007048eb, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000001, 0x40330620, 0x000 }, - { 0x00000000, 0xc0302409, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ae00000, 0x181 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x186 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x186 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000001, 0x00530621, 0x182 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0604800, 0x197 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000011, 0x0020062d, 0x000 }, - { 0x00000000, 0x0078042a, 0x2fb }, - { 0x00000000, 0x00202809, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x174 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x194 }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x46000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x19b }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00804811, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40281620, 0x000 }, - { 0x00000010, 0xc0811a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000008, 0x00221e30, 0x000 }, - { 0x00000029, 0x00201a2d, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfffbff09, 0x00204811, 0x000 }, - { 0x0000000f, 0x0020222d, 0x000 }, - { 0x00001fff, 0x00294a28, 0x000 }, - { 0x00000006, 0x0020222d, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000100, 0x00201811, 0x000 }, - { 0x00000008, 0x00621e28, 0x12f }, - { 0x00000008, 0x00822228, 0x000 }, - { 0x0002c000, 0x00204411, 0x000 }, - { 0x00000015, 0x00600e2d, 0x1bd }, - { 0x00000016, 0x00600e2d, 0x1bd }, - { 0x0000c008, 0x00204411, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000000, 0x14c00000, 0x1b9 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x39000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00804802, 0x000 }, - { 0x00000018, 0x00202e2d, 0x000 }, - { 0x00000000, 0x003b0d63, 0x000 }, - { 0x00000008, 0x00224a23, 0x000 }, - { 0x00000010, 0x00224a23, 0x000 }, - { 0x00000018, 0x00224a23, 0x000 }, - { 0x00000000, 0x00804803, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000007, 0x0021062f, 0x000 }, - { 0x00000013, 0x00200a2d, 0x000 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000ffff, 0x40282220, 0x000 }, - { 0x0000000f, 0x00262228, 0x000 }, - { 0x00000010, 0x40212620, 0x000 }, - { 0x0000000f, 0x00262629, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1e0 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000081, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000080, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1dc }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1d8 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000001f, 0x00280a22, 0x000 }, - { 0x0000001f, 0x00282a2a, 0x000 }, - { 0x00000001, 0x00530621, 0x1d1 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000002, 0x00304a2f, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000001, 0x00301e2f, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1e5 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x0000000f, 0x00260e23, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000000f, 0x00261224, 0x000 }, - { 0x00000000, 0x00201411, 0x000 }, - { 0x00000000, 0x00601811, 0x2bb }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022b, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1f8 }, - { 0x00000010, 0x00221628, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a29, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x0020480a, 0x000 }, - { 0x00000000, 0x00202c11, 0x000 }, - { 0x00000010, 0x00221623, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a24, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x00731503, 0x205 }, - { 0x00000000, 0x00201805, 0x000 }, - { 0x00000000, 0x00731524, 0x205 }, - { 0x00000000, 0x002d14c5, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00000000, 0x00202003, 0x000 }, - { 0x00000000, 0x00802404, 0x000 }, - { 0x0000000f, 0x00210225, 0x000 }, - { 0x00000000, 0x14c00000, 0x68c }, - { 0x00000000, 0x002b1405, 0x000 }, - { 0x00000001, 0x00901625, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00294a22, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a21, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000ffff, 0x40281220, 0x000 }, - { 0x00000010, 0xc0211a20, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211620, 0x000 }, - { 0x00000000, 0x00741465, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00000001, 0x00330621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0cc00000, 0x219 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x212 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000000, 0x0040040f, 0x213 }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00000000, 0x00600000, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ae00000, 0x232 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x236 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x236 }, - { 0x00000000, 0xc0404800, 0x233 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x00600411, 0x2fb }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000018, 0x40210a20, 0x000 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x24c }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x00080101, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x251 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000010, 0x00600411, 0x315 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00000000, 0x00600000, 0x27c }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000001, 0x00211e27, 0x000 }, - { 0x00000000, 0x14e00000, 0x26a }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x0000ffff, 0x00281e27, 0x000 }, - { 0x00000000, 0x00341c27, 0x000 }, - { 0x00000000, 0x12c00000, 0x25f }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e5, 0x000 }, - { 0x00000000, 0x08c00000, 0x262 }, - { 0x00000000, 0x00201407, 0x000 }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00211e27, 0x000 }, - { 0x00000000, 0x00341c47, 0x000 }, - { 0x00000000, 0x12c00000, 0x267 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x08c00000, 0x26a }, - { 0x00000000, 0x00201807, 0x000 }, - { 0x00000000, 0x00600000, 0x2c1 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000000, 0x00342023, 0x000 }, - { 0x00000000, 0x12c00000, 0x272 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x271 }, - { 0x00000016, 0x00404811, 0x276 }, - { 0x00000018, 0x00404811, 0x276 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x275 }, - { 0x00000017, 0x00404811, 0x276 }, - { 0x00000019, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00604411, 0x2e9 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x256 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000010, 0x40210620, 0x000 }, - { 0x0000ffff, 0xc0280a20, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0881a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x00000000, 0xc0600000, 0x2a3 }, - { 0x00000005, 0x00200a2d, 0x000 }, - { 0x00000008, 0x00220a22, 0x000 }, - { 0x0000002b, 0x00201a2d, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00007000, 0x00281e27, 0x000 }, - { 0x00000000, 0x00311ce6, 0x000 }, - { 0x0000002a, 0x00201a2d, 0x000 }, - { 0x0000000c, 0x00221a26, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x06e00000, 0x292 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00691ce2, 0x12f }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x29d }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000001c, 0x00403627, 0x000 }, - { 0x0000000c, 0xc0220a20, 0x000 }, - { 0x00000029, 0x00203622, 0x000 }, - { 0x00000028, 0xc0403620, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000009, 0x00204811, 0x000 }, - { 0xa1000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce3, 0x000 }, - { 0x00000021, 0x00203627, 0x000 }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce4, 0x000 }, - { 0x00000022, 0x00203627, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a3, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203624, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000000, 0x00311cc4, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14c00000, 0x2dc }, - { 0x00000000, 0x00400000, 0x2d9 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2d9 }, - { 0x00000003, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2dc }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e1, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a1, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e2, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000000, 0x00600000, 0x668 }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00600000, 0x65f }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2a7 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x0000001a, 0x00201e2d, 0x000 }, - { 0x0000001b, 0x0080222d, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca1, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x003808c5, 0x000 }, - { 0x00000000, 0x00300841, 0x000 }, - { 0x00000001, 0x00220a22, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000017, 0x0020222d, 0x000 }, - { 0x00000000, 0x14c00000, 0x318 }, - { 0xffffffef, 0x00280621, 0x000 }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x0000f8e0, 0x00204411, 0x000 }, - { 0x00000000, 0x00294901, 0x000 }, - { 0x00000000, 0x00894901, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00804811, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x97000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00002257, 0x00204411, 0x000 }, - { 0x00000003, 0xc0484a20, 0x000 }, - { 0x0000225d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x00000001, 0x40304a20, 0x000 }, - { 0x00000002, 0xc0304a20, 0x000 }, - { 0x00000001, 0x00530a22, 0x34b }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x354 }, - { 0x00000014, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x364 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00604802, 0x36e }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x36a }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35f }, - { 0x00000028, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5c0 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35f }, - { 0x0000002c, 0x00203626, 0x000 }, - { 0x00000049, 0x00201811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0cc00000, 0x370 }, - { 0x0000002c, 0x00801a2d, 0x000 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x00000015, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x386 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b1 }, - { 0x00000016, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b5 }, - { 0x00000020, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x39c }, - { 0x0000000f, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a8 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a8 }, - { 0x0000001e, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x390 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x08000000, 0x00290a22, 0x000 }, - { 0x00000003, 0x40210e20, 0x000 }, - { 0x0000000c, 0xc0211220, 0x000 }, - { 0x00080000, 0x00281224, 0x000 }, - { 0x00000014, 0xc0221620, 0x000 }, - { 0x00000000, 0x002914a4, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x002948a2, 0x000 }, - { 0x0000a1fe, 0x00204411, 0x000 }, - { 0x00000000, 0x00404803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000015, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x392 }, - { 0x0000210e, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000017, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000003, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x39e }, - { 0x00002108, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x80000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000010, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3ae }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000006, 0x00404811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x0000001d, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x3ce }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x3c0 }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0xbabecafe, 0x00204811, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000004, 0x00404811, 0x000 }, - { 0x00002170, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000a, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3d3 }, - { 0x8c000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00003fff, 0x40280a20, 0x000 }, - { 0x80000000, 0x40280e20, 0x000 }, - { 0x40000000, 0xc0281220, 0x000 }, - { 0x00040000, 0x00694622, 0x68d }, - { 0x00000000, 0x00201410, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e1 }, - { 0x00000000, 0xc0401800, 0x3e4 }, - { 0x00003fff, 0xc0281a20, 0x000 }, - { 0x00040000, 0x00694626, 0x68d }, - { 0x00000000, 0x00201810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e7 }, - { 0x00000000, 0xc0401c00, 0x3ea }, - { 0x00003fff, 0xc0281e20, 0x000 }, - { 0x00040000, 0x00694627, 0x68d }, - { 0x00000000, 0x00201c10, 0x000 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0x002820c5, 0x000 }, - { 0x00000000, 0x004948e8, 0x000 }, - { 0xa5800000, 0x00200811, 0x000 }, - { 0x00002000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x0000001f, 0xc0210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x3f7 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000ffff, 0xc0481220, 0x3ff }, - { 0xa7800000, 0x00200811, 0x000 }, - { 0x0000a000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00304883, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xa9800000, 0x00200811, 0x000 }, - { 0x0000c000, 0x00400c11, 0x3fa }, - { 0xab800000, 0x00200811, 0x000 }, - { 0x0000f8e0, 0x00400c11, 0x3fa }, - { 0xad800000, 0x00200811, 0x000 }, - { 0x0000f880, 0x00400c11, 0x3fa }, - { 0xb3800000, 0x00200811, 0x000 }, - { 0x0000f3fc, 0x00400c11, 0x3fa }, - { 0xaf800000, 0x00200811, 0x000 }, - { 0x0000e000, 0x00400c11, 0x3fa }, - { 0xb1800000, 0x00200811, 0x000 }, - { 0x0000f000, 0x00400c11, 0x3fa }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00002148, 0x00204811, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x01182000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0218a000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0318c000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0418f8e0, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0518f880, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0618e000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0718f000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0818f3fc, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000030, 0x00200a2d, 0x000 }, - { 0x00000000, 0xc0290c40, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x86000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x85000000, 0xc0204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00000018, 0x40210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x445 }, - { 0x00800000, 0xc0494a20, 0x446 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00404c02, 0x44b }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x00000000, 0xc0201400, 0x000 }, - { 0x00000000, 0xc0201800, 0x000 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x459 }, - { 0x00000000, 0xc0202000, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x00000010, 0x00280a23, 0x000 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x461 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x68d }, - { 0x00000000, 0x00400000, 0x466 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00604805, 0x692 }, - { 0x00000000, 0x002824f0, 0x000 }, - { 0x00000007, 0x00280a23, 0x000 }, - { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46d }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x04e00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x472 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x02e00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x477 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ce00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x47c }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ae00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000005, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x481 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x06e00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x486 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x08e00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x000 }, - { 0x00000008, 0x00210a23, 0x000 }, - { 0x00000000, 0x14c00000, 0x490 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x499 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x00404c08, 0x459 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000011, 0x40211220, 0x000 }, - { 0x00000012, 0x40211620, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00210225, 0x000 }, - { 0x00000000, 0x14e00000, 0x4a3 }, - { 0x00040000, 0xc0494a20, 0x4a4 }, - { 0xfffbffff, 0xc0284a20, 0x000 }, - { 0x00000000, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x4b0 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000c, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x4ac }, - { 0xa0000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000004, 0x00204811, 0x000 }, - { 0x0000216b, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000216c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4aa }, - { 0x00000000, 0xc0210a20, 0x000 }, - { 0x00000000, 0x14c00000, 0x4c3 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x692 }, - { 0x00000000, 0x00400000, 0x4c7 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0xc0294620, 0x000 }, - { 0x00000000, 0xc0600000, 0x68d }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x4ce }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0404810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000000, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x4d0 }, - { 0x00002180, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000003, 0x00333e2f, 0x000 }, - { 0x00000001, 0x00210221, 0x000 }, - { 0x00000000, 0x14e00000, 0x500 }, - { 0x0000002c, 0x00200a2d, 0x000 }, - { 0x00040000, 0x18e00c11, 0x4ef }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xd8c04800, 0x4e3 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000002d, 0x0020122d, 0x000 }, - { 0x00000000, 0x00290c83, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000011, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4aa }, - { 0x0000002c, 0xc0203620, 0x000 }, - { 0x0000002d, 0xc0403620, 0x000 }, - { 0x0000000f, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x505 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0xd9000000, 0x000 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xb5000000, 0x00204411, 0x000 }, - { 0x00002000, 0x00204811, 0x000 }, - { 0xb6000000, 0x00204411, 0x000 }, - { 0x0000a000, 0x00204811, 0x000 }, - { 0xb7000000, 0x00204411, 0x000 }, - { 0x0000c000, 0x00204811, 0x000 }, - { 0xb8000000, 0x00204411, 0x000 }, - { 0x0000f8e0, 0x00204811, 0x000 }, - { 0xb9000000, 0x00204411, 0x000 }, - { 0x0000f880, 0x00204811, 0x000 }, - { 0xba000000, 0x00204411, 0x000 }, - { 0x0000e000, 0x00204811, 0x000 }, - { 0xbb000000, 0x00204411, 0x000 }, - { 0x0000f000, 0x00204811, 0x000 }, - { 0xbc000000, 0x00204411, 0x000 }, - { 0x0000f3fc, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000002, 0x00204811, 0x000 }, - { 0x000000ff, 0x00280e30, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x519 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x14c00000, 0x52e }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000001c, 0x00203623, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000029, 0x00203623, 0x000 }, - { 0x00000028, 0x00203623, 0x000 }, - { 0x00000017, 0x00203623, 0x000 }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203623, 0x000 }, - { 0x00000015, 0x00203623, 0x000 }, - { 0x00000016, 0x00203623, 0x000 }, - { 0xffffe000, 0x00200c11, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203623, 0x000 }, - { 0x00001fff, 0x00200c11, 0x000 }, - { 0x00000023, 0x00203623, 0x000 }, - { 0x00000024, 0x00203623, 0x000 }, - { 0xf1ffffff, 0x00283a2e, 0x000 }, - { 0x0000001a, 0xc0220e20, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000002a, 0x40203620, 0x000 }, - { 0x87000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x9d000000, 0x00204411, 0x000 }, - { 0x0000001f, 0x40214a20, 0x000 }, - { 0x96000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x0000001f, 0x00211624, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x0000001d, 0x00203623, 0x000 }, - { 0x00000003, 0x00281e23, 0x000 }, - { 0x00000008, 0x00222223, 0x000 }, - { 0xfffff000, 0x00282228, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x0000001f, 0x00203628, 0x000 }, - { 0x00000018, 0x00211e23, 0x000 }, - { 0x00000020, 0x00203627, 0x000 }, - { 0x00000002, 0x00221624, 0x000 }, - { 0x00000000, 0x003014a8, 0x000 }, - { 0x0000001e, 0x00203625, 0x000 }, - { 0x00000003, 0x00211a24, 0x000 }, - { 0x10000000, 0x00281a26, 0x000 }, - { 0xefffffff, 0x00283a2e, 0x000 }, - { 0x00000000, 0x004938ce, 0x67b }, - { 0x00000001, 0x40280a20, 0x000 }, - { 0x00000006, 0x40280e20, 0x000 }, - { 0x00000300, 0xc0281220, 0x000 }, - { 0x00000008, 0x00211224, 0x000 }, - { 0x00000000, 0xc0201620, 0x000 }, - { 0x00000000, 0xc0201a20, 0x000 }, - { 0x00000000, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x566 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68d }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00020000, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56e }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x57c }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68d }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x57c }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x572 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x57c }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x57a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x692 }, - { 0x00000000, 0x00401c10, 0x57c }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x57e }, - { 0x00000000, 0x00600000, 0x5c9 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x58f }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x58d }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5a0 }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x59e }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5b1 }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5af }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5be }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5c4 }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5c9 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000002c, 0x00203621, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0230, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5d0 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000030, 0x00403621, 0x5e3 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5e3 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a092, 0x00604411, 0x68d }, - { 0x00000031, 0x00203630, 0x000 }, - { 0x0004a093, 0x00604411, 0x68d }, - { 0x00000032, 0x00203630, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68d }, - { 0x00000033, 0x00203630, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68d }, - { 0x00000034, 0x00203630, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68d }, - { 0x00000035, 0x00203630, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68d }, - { 0x00000036, 0x00203630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000001, 0x002f0230, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62c }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62c }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x605 }, - { 0x0000a092, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x0000a093, 0x00204411, 0x000 }, - { 0x00000032, 0x00204a2d, 0x000 }, - { 0x0000a2b6, 0x00204411, 0x000 }, - { 0x00000033, 0x00204a2d, 0x000 }, - { 0x0000a2ba, 0x00204411, 0x000 }, - { 0x00000034, 0x00204a2d, 0x000 }, - { 0x0000a2be, 0x00204411, 0x000 }, - { 0x00000035, 0x00204a2d, 0x000 }, - { 0x0000a2c2, 0x00204411, 0x000 }, - { 0x00000036, 0x00204a2d, 0x000 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x000001ff, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62b }, - { 0x00000000, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x60e }, - { 0x0004a003, 0x00604411, 0x68d }, - { 0x0000a003, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x14c00000, 0x613 }, - { 0x0004a010, 0x00604411, 0x68d }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62b }, - { 0x0004a011, 0x00604411, 0x68d }, - { 0x0000a011, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a012, 0x00604411, 0x68d }, - { 0x0000a012, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a013, 0x00604411, 0x68d }, - { 0x0000a013, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a014, 0x00604411, 0x68d }, - { 0x0000a014, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a015, 0x00604411, 0x68d }, - { 0x0000a015, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a016, 0x00604411, 0x68d }, - { 0x0000a016, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a017, 0x00604411, 0x68d }, - { 0x0000a017, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000002c, 0x0080062d, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x63d }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000002, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x63b }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x641 }, - { 0x00000000, 0x00600000, 0x5c9 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x641 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x62d }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x62d }, - { 0x00000000, 0x00600000, 0x65c }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x656 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x68c }, - { 0x00000010, 0x00404c11, 0x672 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x68b }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68d }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x690 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x692 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x695 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x01420502, 0x05c00250, 0x000 }, - { 0x01c30168, 0x043f05c0, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03d705c0, 0x05c005c0, 0x000 }, - { 0x0649064a, 0x031f05c0, 0x000 }, - { 0x05c005c5, 0x03200340, 0x000 }, - { 0x032a0282, 0x03420334, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c00551, 0x05c005c0, 0x000 }, - { 0x03ba05c0, 0x04bb0344, 0x000 }, - { 0x049a0450, 0x043d05c0, 0x000 }, - { 0x04d005c0, 0x044104dd, 0x000 }, - { 0x04500507, 0x03510375, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x063f05c7, 0x000 }, - { 0x05c005c0, 0x000705c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x03f803ed, 0x04080406, 0x000 }, - { 0x040e040a, 0x040c0410, 0x000 }, - { 0x041c0418, 0x04240420, 0x000 }, - { 0x042c0428, 0x04340430, 0x000 }, - { 0x05c005c0, 0x043805c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x00020679, 0x06970006, 0x000 }, -}; - -static const u32 RV610_pfp_microcode[] = { -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001b8, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800053, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b8, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x800079, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008d, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401bb, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401bb, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b8, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001b8, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f0, -0xcc1003, -0x98801b, -0x04380c, -0x8400f0, -0xcc1003, -0x988017, -0x043808, -0x8400f0, -0xcc1003, -0x988013, -0x043804, -0x8400f0, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000c9, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001b8, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001b8, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b8, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800101, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d9, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bd, -0x000000, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902b0, -0x7c738b, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984297, -0x000000, -0x800161, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001b8, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010171, -0x020178, -0x03008f, -0x04007f, -0x050003, -0x06003f, -0x070032, -0x08012c, -0x090046, -0x0a0036, -0x1001b6, -0x1700a2, -0x22013a, -0x230149, -0x2000b4, -0x240125, -0x27004d, -0x28006a, -0x2a0060, -0x2b0052, -0x2f0065, -0x320087, -0x34017f, -0x3c0156, -0x3f0072, -0x41018c, -0x44012e, -0x550173, -0x56017a, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; - -static const u32 RV620_cp_microcode[][3] = { - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x668 }, - { 0x00000000, 0x00600000, 0x65c }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 0x00400c11, 0x0d6 }, - { 0x00001f00, 0x00400c11, 0x0d6 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0dc }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00280e22, 0x000 }, - { 0x00000080, 0x00294a23, 0x000 }, - { 0x00000027, 0x00200e2d, 0x000 }, - { 0x00000026, 0x0020122d, 0x000 }, - { 0x00000000, 0x002f0083, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0ea }, - { 0x00000000, 0x00600000, 0x662 }, - { 0x00000000, 0x00400000, 0x0eb }, - { 0x00000000, 0x00600000, 0x665 }, - { 0x00000007, 0x0020222d, 0x000 }, - { 0x00000005, 0x00220e22, 0x000 }, - { 0x00100000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x000000ef, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000003, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x0f8 }, - { 0x0000000b, 0x00210228, 0x000 }, - { 0x00000000, 0x14c00000, 0x0f8 }, - { 0x00000400, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000001c, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x0fd }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000001e, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x10b }, - { 0x0000a30f, 0x00204411, 0x000 }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x104 }, - { 0xffffffff, 0x00404811, 0x10b }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x107 }, - { 0x0000ffff, 0x00404811, 0x10b }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x10a }, - { 0x000000ff, 0x00404811, 0x10b }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0002c400, 0x00204411, 0x000 }, - { 0x0000001f, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x112 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000018, 0x40224a20, 0x000 }, - { 0x00000010, 0xc0424a20, 0x114 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000000a, 0x00201011, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x11b }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00531224, 0x117 }, - { 0xffbfffff, 0x00283a2e, 0x000 }, - { 0x0000001b, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x12e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0x00000018, 0x00220e30, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e00e, 0x00204411, 0x000 }, - { 0x07f8ff08, 0x00204811, 0x000 }, - { 0x00000000, 0x00294a23, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00800000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204806, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x68c }, - { 0x00000004, 0x00404c11, 0x135 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000001c, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x13c }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40280620, 0x000 }, - { 0x00000010, 0xc0210a20, 0x000 }, - { 0x00000000, 0x00341461, 0x000 }, - { 0x00000000, 0x00741882, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x147 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0681a20, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x158 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000001, 0x00300a2f, 0x000 }, - { 0x00000001, 0x00210a22, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600000, 0x18f }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00202c08, 0x000 }, - { 0x00000000, 0x00202411, 0x000 }, - { 0x00000000, 0x00202811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000002, 0x00221e29, 0x000 }, - { 0x00000000, 0x007048eb, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000001, 0x40330620, 0x000 }, - { 0x00000000, 0xc0302409, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ae00000, 0x181 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x186 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x186 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000001, 0x00530621, 0x182 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0604800, 0x197 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000011, 0x0020062d, 0x000 }, - { 0x00000000, 0x0078042a, 0x2fb }, - { 0x00000000, 0x00202809, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x174 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x194 }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x46000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x19b }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00804811, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40281620, 0x000 }, - { 0x00000010, 0xc0811a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000008, 0x00221e30, 0x000 }, - { 0x00000029, 0x00201a2d, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfffbff09, 0x00204811, 0x000 }, - { 0x0000000f, 0x0020222d, 0x000 }, - { 0x00001fff, 0x00294a28, 0x000 }, - { 0x00000006, 0x0020222d, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000100, 0x00201811, 0x000 }, - { 0x00000008, 0x00621e28, 0x12f }, - { 0x00000008, 0x00822228, 0x000 }, - { 0x0002c000, 0x00204411, 0x000 }, - { 0x00000015, 0x00600e2d, 0x1bd }, - { 0x00000016, 0x00600e2d, 0x1bd }, - { 0x0000c008, 0x00204411, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000000, 0x14c00000, 0x1b9 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x39000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00804802, 0x000 }, - { 0x00000018, 0x00202e2d, 0x000 }, - { 0x00000000, 0x003b0d63, 0x000 }, - { 0x00000008, 0x00224a23, 0x000 }, - { 0x00000010, 0x00224a23, 0x000 }, - { 0x00000018, 0x00224a23, 0x000 }, - { 0x00000000, 0x00804803, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000007, 0x0021062f, 0x000 }, - { 0x00000013, 0x00200a2d, 0x000 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000ffff, 0x40282220, 0x000 }, - { 0x0000000f, 0x00262228, 0x000 }, - { 0x00000010, 0x40212620, 0x000 }, - { 0x0000000f, 0x00262629, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1e0 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000081, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000080, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1dc }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1d8 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000001f, 0x00280a22, 0x000 }, - { 0x0000001f, 0x00282a2a, 0x000 }, - { 0x00000001, 0x00530621, 0x1d1 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000002, 0x00304a2f, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000001, 0x00301e2f, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1e5 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x0000000f, 0x00260e23, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000000f, 0x00261224, 0x000 }, - { 0x00000000, 0x00201411, 0x000 }, - { 0x00000000, 0x00601811, 0x2bb }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022b, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1f8 }, - { 0x00000010, 0x00221628, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a29, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x0020480a, 0x000 }, - { 0x00000000, 0x00202c11, 0x000 }, - { 0x00000010, 0x00221623, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a24, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x00731503, 0x205 }, - { 0x00000000, 0x00201805, 0x000 }, - { 0x00000000, 0x00731524, 0x205 }, - { 0x00000000, 0x002d14c5, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00000000, 0x00202003, 0x000 }, - { 0x00000000, 0x00802404, 0x000 }, - { 0x0000000f, 0x00210225, 0x000 }, - { 0x00000000, 0x14c00000, 0x68c }, - { 0x00000000, 0x002b1405, 0x000 }, - { 0x00000001, 0x00901625, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00294a22, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a21, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000ffff, 0x40281220, 0x000 }, - { 0x00000010, 0xc0211a20, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211620, 0x000 }, - { 0x00000000, 0x00741465, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00000001, 0x00330621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0cc00000, 0x219 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x212 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000000, 0x0040040f, 0x213 }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00000000, 0x00600000, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ae00000, 0x232 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x236 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x236 }, - { 0x00000000, 0xc0404800, 0x233 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x00600411, 0x2fb }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000018, 0x40210a20, 0x000 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x24c }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x00080101, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x251 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000010, 0x00600411, 0x315 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00000000, 0x00600000, 0x27c }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000001, 0x00211e27, 0x000 }, - { 0x00000000, 0x14e00000, 0x26a }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x0000ffff, 0x00281e27, 0x000 }, - { 0x00000000, 0x00341c27, 0x000 }, - { 0x00000000, 0x12c00000, 0x25f }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e5, 0x000 }, - { 0x00000000, 0x08c00000, 0x262 }, - { 0x00000000, 0x00201407, 0x000 }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00211e27, 0x000 }, - { 0x00000000, 0x00341c47, 0x000 }, - { 0x00000000, 0x12c00000, 0x267 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x08c00000, 0x26a }, - { 0x00000000, 0x00201807, 0x000 }, - { 0x00000000, 0x00600000, 0x2c1 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000000, 0x00342023, 0x000 }, - { 0x00000000, 0x12c00000, 0x272 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x271 }, - { 0x00000016, 0x00404811, 0x276 }, - { 0x00000018, 0x00404811, 0x276 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x275 }, - { 0x00000017, 0x00404811, 0x276 }, - { 0x00000019, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00604411, 0x2e9 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x256 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000010, 0x40210620, 0x000 }, - { 0x0000ffff, 0xc0280a20, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0881a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x00000000, 0xc0600000, 0x2a3 }, - { 0x00000005, 0x00200a2d, 0x000 }, - { 0x00000008, 0x00220a22, 0x000 }, - { 0x0000002b, 0x00201a2d, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00007000, 0x00281e27, 0x000 }, - { 0x00000000, 0x00311ce6, 0x000 }, - { 0x0000002a, 0x00201a2d, 0x000 }, - { 0x0000000c, 0x00221a26, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x06e00000, 0x292 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00691ce2, 0x12f }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x29d }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000001c, 0x00403627, 0x000 }, - { 0x0000000c, 0xc0220a20, 0x000 }, - { 0x00000029, 0x00203622, 0x000 }, - { 0x00000028, 0xc0403620, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000009, 0x00204811, 0x000 }, - { 0xa1000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce3, 0x000 }, - { 0x00000021, 0x00203627, 0x000 }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce4, 0x000 }, - { 0x00000022, 0x00203627, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a3, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203624, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000000, 0x00311cc4, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14c00000, 0x2dc }, - { 0x00000000, 0x00400000, 0x2d9 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2d9 }, - { 0x00000003, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2dc }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e1, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a1, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e2, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000000, 0x00600000, 0x668 }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00600000, 0x65f }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2a7 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x0000001a, 0x00201e2d, 0x000 }, - { 0x0000001b, 0x0080222d, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca1, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x003808c5, 0x000 }, - { 0x00000000, 0x00300841, 0x000 }, - { 0x00000001, 0x00220a22, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000017, 0x0020222d, 0x000 }, - { 0x00000000, 0x14c00000, 0x318 }, - { 0xffffffef, 0x00280621, 0x000 }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x0000f8e0, 0x00204411, 0x000 }, - { 0x00000000, 0x00294901, 0x000 }, - { 0x00000000, 0x00894901, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00804811, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x97000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00002257, 0x00204411, 0x000 }, - { 0x00000003, 0xc0484a20, 0x000 }, - { 0x0000225d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x00000001, 0x40304a20, 0x000 }, - { 0x00000002, 0xc0304a20, 0x000 }, - { 0x00000001, 0x00530a22, 0x34b }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x354 }, - { 0x00000014, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x364 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00604802, 0x36e }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x36a }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35f }, - { 0x00000028, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5c0 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35f }, - { 0x0000002c, 0x00203626, 0x000 }, - { 0x00000049, 0x00201811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0cc00000, 0x370 }, - { 0x0000002c, 0x00801a2d, 0x000 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x00000015, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x386 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b1 }, - { 0x00000016, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b5 }, - { 0x00000020, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x39c }, - { 0x0000000f, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a8 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a8 }, - { 0x0000001e, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x390 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x08000000, 0x00290a22, 0x000 }, - { 0x00000003, 0x40210e20, 0x000 }, - { 0x0000000c, 0xc0211220, 0x000 }, - { 0x00080000, 0x00281224, 0x000 }, - { 0x00000014, 0xc0221620, 0x000 }, - { 0x00000000, 0x002914a4, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x002948a2, 0x000 }, - { 0x0000a1fe, 0x00204411, 0x000 }, - { 0x00000000, 0x00404803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000015, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x392 }, - { 0x0000210e, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000017, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000003, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x39e }, - { 0x00002108, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x80000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000010, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3ae }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000006, 0x00404811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x0000001d, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x3ce }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x3c0 }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0xbabecafe, 0x00204811, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000004, 0x00404811, 0x000 }, - { 0x00002170, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000a, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3d3 }, - { 0x8c000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00003fff, 0x40280a20, 0x000 }, - { 0x80000000, 0x40280e20, 0x000 }, - { 0x40000000, 0xc0281220, 0x000 }, - { 0x00040000, 0x00694622, 0x68d }, - { 0x00000000, 0x00201410, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e1 }, - { 0x00000000, 0xc0401800, 0x3e4 }, - { 0x00003fff, 0xc0281a20, 0x000 }, - { 0x00040000, 0x00694626, 0x68d }, - { 0x00000000, 0x00201810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e7 }, - { 0x00000000, 0xc0401c00, 0x3ea }, - { 0x00003fff, 0xc0281e20, 0x000 }, - { 0x00040000, 0x00694627, 0x68d }, - { 0x00000000, 0x00201c10, 0x000 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0x002820c5, 0x000 }, - { 0x00000000, 0x004948e8, 0x000 }, - { 0xa5800000, 0x00200811, 0x000 }, - { 0x00002000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x0000001f, 0xc0210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x3f7 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000ffff, 0xc0481220, 0x3ff }, - { 0xa7800000, 0x00200811, 0x000 }, - { 0x0000a000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00304883, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xa9800000, 0x00200811, 0x000 }, - { 0x0000c000, 0x00400c11, 0x3fa }, - { 0xab800000, 0x00200811, 0x000 }, - { 0x0000f8e0, 0x00400c11, 0x3fa }, - { 0xad800000, 0x00200811, 0x000 }, - { 0x0000f880, 0x00400c11, 0x3fa }, - { 0xb3800000, 0x00200811, 0x000 }, - { 0x0000f3fc, 0x00400c11, 0x3fa }, - { 0xaf800000, 0x00200811, 0x000 }, - { 0x0000e000, 0x00400c11, 0x3fa }, - { 0xb1800000, 0x00200811, 0x000 }, - { 0x0000f000, 0x00400c11, 0x3fa }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00002148, 0x00204811, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x01182000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0218a000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0318c000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0418f8e0, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0518f880, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0618e000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0718f000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0818f3fc, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000030, 0x00200a2d, 0x000 }, - { 0x00000000, 0xc0290c40, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x86000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x85000000, 0xc0204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00000018, 0x40210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x445 }, - { 0x00800000, 0xc0494a20, 0x446 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00404c02, 0x44b }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x00000000, 0xc0201400, 0x000 }, - { 0x00000000, 0xc0201800, 0x000 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x459 }, - { 0x00000000, 0xc0202000, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x00000010, 0x00280a23, 0x000 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x461 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x68d }, - { 0x00000000, 0x00400000, 0x466 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00604805, 0x692 }, - { 0x00000000, 0x002824f0, 0x000 }, - { 0x00000007, 0x00280a23, 0x000 }, - { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46d }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x04e00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x472 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x02e00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x477 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ce00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x47c }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ae00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000005, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x481 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x06e00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x486 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x08e00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x000 }, - { 0x00000008, 0x00210a23, 0x000 }, - { 0x00000000, 0x14c00000, 0x490 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x499 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x00404c08, 0x459 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000011, 0x40211220, 0x000 }, - { 0x00000012, 0x40211620, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00210225, 0x000 }, - { 0x00000000, 0x14e00000, 0x4a3 }, - { 0x00040000, 0xc0494a20, 0x4a4 }, - { 0xfffbffff, 0xc0284a20, 0x000 }, - { 0x00000000, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x4b0 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000c, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x4ac }, - { 0xa0000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000004, 0x00204811, 0x000 }, - { 0x0000216b, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000216c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4aa }, - { 0x00000000, 0xc0210a20, 0x000 }, - { 0x00000000, 0x14c00000, 0x4c3 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x692 }, - { 0x00000000, 0x00400000, 0x4c7 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0xc0294620, 0x000 }, - { 0x00000000, 0xc0600000, 0x68d }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x4ce }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0404810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000000, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x4d0 }, - { 0x00002180, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000003, 0x00333e2f, 0x000 }, - { 0x00000001, 0x00210221, 0x000 }, - { 0x00000000, 0x14e00000, 0x500 }, - { 0x0000002c, 0x00200a2d, 0x000 }, - { 0x00040000, 0x18e00c11, 0x4ef }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xd8c04800, 0x4e3 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000002d, 0x0020122d, 0x000 }, - { 0x00000000, 0x00290c83, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000011, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4aa }, - { 0x0000002c, 0xc0203620, 0x000 }, - { 0x0000002d, 0xc0403620, 0x000 }, - { 0x0000000f, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x505 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0xd9000000, 0x000 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xb5000000, 0x00204411, 0x000 }, - { 0x00002000, 0x00204811, 0x000 }, - { 0xb6000000, 0x00204411, 0x000 }, - { 0x0000a000, 0x00204811, 0x000 }, - { 0xb7000000, 0x00204411, 0x000 }, - { 0x0000c000, 0x00204811, 0x000 }, - { 0xb8000000, 0x00204411, 0x000 }, - { 0x0000f8e0, 0x00204811, 0x000 }, - { 0xb9000000, 0x00204411, 0x000 }, - { 0x0000f880, 0x00204811, 0x000 }, - { 0xba000000, 0x00204411, 0x000 }, - { 0x0000e000, 0x00204811, 0x000 }, - { 0xbb000000, 0x00204411, 0x000 }, - { 0x0000f000, 0x00204811, 0x000 }, - { 0xbc000000, 0x00204411, 0x000 }, - { 0x0000f3fc, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000002, 0x00204811, 0x000 }, - { 0x000000ff, 0x00280e30, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x519 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x14c00000, 0x52e }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000001c, 0x00203623, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000029, 0x00203623, 0x000 }, - { 0x00000028, 0x00203623, 0x000 }, - { 0x00000017, 0x00203623, 0x000 }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203623, 0x000 }, - { 0x00000015, 0x00203623, 0x000 }, - { 0x00000016, 0x00203623, 0x000 }, - { 0xffffe000, 0x00200c11, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203623, 0x000 }, - { 0x00001fff, 0x00200c11, 0x000 }, - { 0x00000023, 0x00203623, 0x000 }, - { 0x00000024, 0x00203623, 0x000 }, - { 0xf1ffffff, 0x00283a2e, 0x000 }, - { 0x0000001a, 0xc0220e20, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000002a, 0x40203620, 0x000 }, - { 0x87000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x9d000000, 0x00204411, 0x000 }, - { 0x0000001f, 0x40214a20, 0x000 }, - { 0x96000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x0000001f, 0x00211624, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x0000001d, 0x00203623, 0x000 }, - { 0x00000003, 0x00281e23, 0x000 }, - { 0x00000008, 0x00222223, 0x000 }, - { 0xfffff000, 0x00282228, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x0000001f, 0x00203628, 0x000 }, - { 0x00000018, 0x00211e23, 0x000 }, - { 0x00000020, 0x00203627, 0x000 }, - { 0x00000002, 0x00221624, 0x000 }, - { 0x00000000, 0x003014a8, 0x000 }, - { 0x0000001e, 0x00203625, 0x000 }, - { 0x00000003, 0x00211a24, 0x000 }, - { 0x10000000, 0x00281a26, 0x000 }, - { 0xefffffff, 0x00283a2e, 0x000 }, - { 0x00000000, 0x004938ce, 0x67b }, - { 0x00000001, 0x40280a20, 0x000 }, - { 0x00000006, 0x40280e20, 0x000 }, - { 0x00000300, 0xc0281220, 0x000 }, - { 0x00000008, 0x00211224, 0x000 }, - { 0x00000000, 0xc0201620, 0x000 }, - { 0x00000000, 0xc0201a20, 0x000 }, - { 0x00000000, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x566 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68d }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00020000, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56e }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x57c }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68d }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x57c }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x572 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x57c }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x57a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x692 }, - { 0x00000000, 0x00401c10, 0x57c }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x57e }, - { 0x00000000, 0x00600000, 0x5c9 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x58f }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x58d }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5a0 }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x59e }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5b1 }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5af }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5be }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5c4 }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5c9 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000002c, 0x00203621, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0230, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5d0 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000030, 0x00403621, 0x5e3 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5e3 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a092, 0x00604411, 0x68d }, - { 0x00000031, 0x00203630, 0x000 }, - { 0x0004a093, 0x00604411, 0x68d }, - { 0x00000032, 0x00203630, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68d }, - { 0x00000033, 0x00203630, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68d }, - { 0x00000034, 0x00203630, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68d }, - { 0x00000035, 0x00203630, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68d }, - { 0x00000036, 0x00203630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000001, 0x002f0230, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62c }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62c }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x605 }, - { 0x0000a092, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x0000a093, 0x00204411, 0x000 }, - { 0x00000032, 0x00204a2d, 0x000 }, - { 0x0000a2b6, 0x00204411, 0x000 }, - { 0x00000033, 0x00204a2d, 0x000 }, - { 0x0000a2ba, 0x00204411, 0x000 }, - { 0x00000034, 0x00204a2d, 0x000 }, - { 0x0000a2be, 0x00204411, 0x000 }, - { 0x00000035, 0x00204a2d, 0x000 }, - { 0x0000a2c2, 0x00204411, 0x000 }, - { 0x00000036, 0x00204a2d, 0x000 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x000001ff, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62b }, - { 0x00000000, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x60e }, - { 0x0004a003, 0x00604411, 0x68d }, - { 0x0000a003, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x14c00000, 0x613 }, - { 0x0004a010, 0x00604411, 0x68d }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62b }, - { 0x0004a011, 0x00604411, 0x68d }, - { 0x0000a011, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a012, 0x00604411, 0x68d }, - { 0x0000a012, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a013, 0x00604411, 0x68d }, - { 0x0000a013, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a014, 0x00604411, 0x68d }, - { 0x0000a014, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a015, 0x00604411, 0x68d }, - { 0x0000a015, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a016, 0x00604411, 0x68d }, - { 0x0000a016, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a017, 0x00604411, 0x68d }, - { 0x0000a017, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000002c, 0x0080062d, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x63d }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000002, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x63b }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x641 }, - { 0x00000000, 0x00600000, 0x5c9 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x641 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x62d }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x62d }, - { 0x00000000, 0x00600000, 0x65c }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x656 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x68c }, - { 0x00000010, 0x00404c11, 0x672 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x68b }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68d }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x690 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x692 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x695 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x01420502, 0x05c00250, 0x000 }, - { 0x01c30168, 0x043f05c0, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03d705c0, 0x05c005c0, 0x000 }, - { 0x0649064a, 0x031f05c0, 0x000 }, - { 0x05c005c5, 0x03200340, 0x000 }, - { 0x032a0282, 0x03420334, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c00551, 0x05c005c0, 0x000 }, - { 0x03ba05c0, 0x04bb0344, 0x000 }, - { 0x049a0450, 0x043d05c0, 0x000 }, - { 0x04d005c0, 0x044104dd, 0x000 }, - { 0x04500507, 0x03510375, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x063f05c7, 0x000 }, - { 0x05c005c0, 0x000705c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x03f803ed, 0x04080406, 0x000 }, - { 0x040e040a, 0x040c0410, 0x000 }, - { 0x041c0418, 0x04240420, 0x000 }, - { 0x042c0428, 0x04340430, 0x000 }, - { 0x05c005c0, 0x043805c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x00020679, 0x06970006, 0x000 }, -}; - -static const u32 RV620_pfp_microcode[] = { -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001b8, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800053, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b8, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x800079, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008d, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401bb, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401bb, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b8, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001b8, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f0, -0xcc1003, -0x98801b, -0x04380c, -0x8400f0, -0xcc1003, -0x988017, -0x043808, -0x8400f0, -0xcc1003, -0x988013, -0x043804, -0x8400f0, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000c9, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001b8, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001b8, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b8, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800101, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d9, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bd, -0x000000, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902b0, -0x7c738b, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984297, -0x000000, -0x800161, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001b8, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010171, -0x020178, -0x03008f, -0x04007f, -0x050003, -0x06003f, -0x070032, -0x08012c, -0x090046, -0x0a0036, -0x1001b6, -0x1700a2, -0x22013a, -0x230149, -0x2000b4, -0x240125, -0x27004d, -0x28006a, -0x2a0060, -0x2b0052, -0x2f0065, -0x320087, -0x34017f, -0x3c0156, -0x3f0072, -0x41018c, -0x44012e, -0x550173, -0x56017a, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; - -static const u32 RV630_cp_microcode[][3] = { - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x665 }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 0x00400c11, 0x0d6 }, - { 0x00001f00, 0x00400c11, 0x0d6 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0dc }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00280e22, 0x000 }, - { 0x00000080, 0x00294a23, 0x000 }, - { 0x00000027, 0x00200e2d, 0x000 }, - { 0x00000026, 0x0020122d, 0x000 }, - { 0x00000000, 0x002f0083, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0ea }, - { 0x00000000, 0x00600000, 0x65f }, - { 0x00000000, 0x00400000, 0x0eb }, - { 0x00000000, 0x00600000, 0x662 }, - { 0x00000007, 0x0020222d, 0x000 }, - { 0x00000005, 0x00220e22, 0x000 }, - { 0x00100000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x000000ef, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000003, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x0f8 }, - { 0x0000000b, 0x00210228, 0x000 }, - { 0x00000000, 0x14c00000, 0x0f8 }, - { 0x00000400, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000001c, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x0fd }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000001e, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x10b }, - { 0x0000a30f, 0x00204411, 0x000 }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x104 }, - { 0xffffffff, 0x00404811, 0x10b }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x107 }, - { 0x0000ffff, 0x00404811, 0x10b }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x10a }, - { 0x000000ff, 0x00404811, 0x10b }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0002c400, 0x00204411, 0x000 }, - { 0x0000001f, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x112 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000018, 0x40224a20, 0x000 }, - { 0x00000010, 0xc0424a20, 0x114 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000000a, 0x00201011, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x11b }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00531224, 0x117 }, - { 0xffbfffff, 0x00283a2e, 0x000 }, - { 0x0000001b, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x12e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0x00000018, 0x00220e30, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e00e, 0x00204411, 0x000 }, - { 0x07f8ff08, 0x00204811, 0x000 }, - { 0x00000000, 0x00294a23, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00800000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204806, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x689 }, - { 0x00000004, 0x00404c11, 0x135 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000001c, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x13c }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40280620, 0x000 }, - { 0x00000010, 0xc0210a20, 0x000 }, - { 0x00000000, 0x00341461, 0x000 }, - { 0x00000000, 0x00741882, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x147 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0681a20, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x158 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000001, 0x00300a2f, 0x000 }, - { 0x00000001, 0x00210a22, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600000, 0x18f }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00202c08, 0x000 }, - { 0x00000000, 0x00202411, 0x000 }, - { 0x00000000, 0x00202811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000002, 0x00221e29, 0x000 }, - { 0x00000000, 0x007048eb, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000001, 0x40330620, 0x000 }, - { 0x00000000, 0xc0302409, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ae00000, 0x181 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x186 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x186 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000001, 0x00530621, 0x182 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0604800, 0x197 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000011, 0x0020062d, 0x000 }, - { 0x00000000, 0x0078042a, 0x2fb }, - { 0x00000000, 0x00202809, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x174 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x194 }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x46000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x19b }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00804811, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40281620, 0x000 }, - { 0x00000010, 0xc0811a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000008, 0x00221e30, 0x000 }, - { 0x00000029, 0x00201a2d, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfffbff09, 0x00204811, 0x000 }, - { 0x0000000f, 0x0020222d, 0x000 }, - { 0x00001fff, 0x00294a28, 0x000 }, - { 0x00000006, 0x0020222d, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000100, 0x00201811, 0x000 }, - { 0x00000008, 0x00621e28, 0x12f }, - { 0x00000008, 0x00822228, 0x000 }, - { 0x0002c000, 0x00204411, 0x000 }, - { 0x00000015, 0x00600e2d, 0x1bd }, - { 0x00000016, 0x00600e2d, 0x1bd }, - { 0x0000c008, 0x00204411, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000000, 0x14c00000, 0x1b9 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x39000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00804802, 0x000 }, - { 0x00000018, 0x00202e2d, 0x000 }, - { 0x00000000, 0x003b0d63, 0x000 }, - { 0x00000008, 0x00224a23, 0x000 }, - { 0x00000010, 0x00224a23, 0x000 }, - { 0x00000018, 0x00224a23, 0x000 }, - { 0x00000000, 0x00804803, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000007, 0x0021062f, 0x000 }, - { 0x00000013, 0x00200a2d, 0x000 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000ffff, 0x40282220, 0x000 }, - { 0x0000000f, 0x00262228, 0x000 }, - { 0x00000010, 0x40212620, 0x000 }, - { 0x0000000f, 0x00262629, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1e0 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000081, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000080, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1dc }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1d8 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000001f, 0x00280a22, 0x000 }, - { 0x0000001f, 0x00282a2a, 0x000 }, - { 0x00000001, 0x00530621, 0x1d1 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000002, 0x00304a2f, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000001, 0x00301e2f, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1e5 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x0000000f, 0x00260e23, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000000f, 0x00261224, 0x000 }, - { 0x00000000, 0x00201411, 0x000 }, - { 0x00000000, 0x00601811, 0x2bb }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022b, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1f8 }, - { 0x00000010, 0x00221628, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a29, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x0020480a, 0x000 }, - { 0x00000000, 0x00202c11, 0x000 }, - { 0x00000010, 0x00221623, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a24, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x00731503, 0x205 }, - { 0x00000000, 0x00201805, 0x000 }, - { 0x00000000, 0x00731524, 0x205 }, - { 0x00000000, 0x002d14c5, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00000000, 0x00202003, 0x000 }, - { 0x00000000, 0x00802404, 0x000 }, - { 0x0000000f, 0x00210225, 0x000 }, - { 0x00000000, 0x14c00000, 0x689 }, - { 0x00000000, 0x002b1405, 0x000 }, - { 0x00000001, 0x00901625, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00294a22, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a21, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000ffff, 0x40281220, 0x000 }, - { 0x00000010, 0xc0211a20, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211620, 0x000 }, - { 0x00000000, 0x00741465, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00000001, 0x00330621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0cc00000, 0x219 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x212 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000000, 0x0040040f, 0x213 }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00000000, 0x00600000, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ae00000, 0x232 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x236 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x236 }, - { 0x00000000, 0xc0404800, 0x233 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x00600411, 0x2fb }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000018, 0x40210a20, 0x000 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x24c }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x00080101, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x251 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000010, 0x00600411, 0x315 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00000000, 0x00600000, 0x27c }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000001, 0x00211e27, 0x000 }, - { 0x00000000, 0x14e00000, 0x26a }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x0000ffff, 0x00281e27, 0x000 }, - { 0x00000000, 0x00341c27, 0x000 }, - { 0x00000000, 0x12c00000, 0x25f }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e5, 0x000 }, - { 0x00000000, 0x08c00000, 0x262 }, - { 0x00000000, 0x00201407, 0x000 }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00211e27, 0x000 }, - { 0x00000000, 0x00341c47, 0x000 }, - { 0x00000000, 0x12c00000, 0x267 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x08c00000, 0x26a }, - { 0x00000000, 0x00201807, 0x000 }, - { 0x00000000, 0x00600000, 0x2c1 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000000, 0x00342023, 0x000 }, - { 0x00000000, 0x12c00000, 0x272 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x271 }, - { 0x00000016, 0x00404811, 0x276 }, - { 0x00000018, 0x00404811, 0x276 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x275 }, - { 0x00000017, 0x00404811, 0x276 }, - { 0x00000019, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00604411, 0x2e9 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x256 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000010, 0x40210620, 0x000 }, - { 0x0000ffff, 0xc0280a20, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0881a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x00000000, 0xc0600000, 0x2a3 }, - { 0x00000005, 0x00200a2d, 0x000 }, - { 0x00000008, 0x00220a22, 0x000 }, - { 0x0000002b, 0x00201a2d, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00007000, 0x00281e27, 0x000 }, - { 0x00000000, 0x00311ce6, 0x000 }, - { 0x0000002a, 0x00201a2d, 0x000 }, - { 0x0000000c, 0x00221a26, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x06e00000, 0x292 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00691ce2, 0x12f }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x29d }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000001c, 0x00403627, 0x000 }, - { 0x0000000c, 0xc0220a20, 0x000 }, - { 0x00000029, 0x00203622, 0x000 }, - { 0x00000028, 0xc0403620, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000009, 0x00204811, 0x000 }, - { 0xa1000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce3, 0x000 }, - { 0x00000021, 0x00203627, 0x000 }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce4, 0x000 }, - { 0x00000022, 0x00203627, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a3, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203624, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000000, 0x00311cc4, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14c00000, 0x2dc }, - { 0x00000000, 0x00400000, 0x2d9 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2d9 }, - { 0x00000003, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2dc }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e1, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a1, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e2, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000000, 0x00600000, 0x665 }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00600000, 0x65c }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2a7 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x0000001a, 0x00201e2d, 0x000 }, - { 0x0000001b, 0x0080222d, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca1, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x003808c5, 0x000 }, - { 0x00000000, 0x00300841, 0x000 }, - { 0x00000001, 0x00220a22, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000017, 0x0020222d, 0x000 }, - { 0x00000000, 0x14c00000, 0x318 }, - { 0xffffffef, 0x00280621, 0x000 }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x0000f8e0, 0x00204411, 0x000 }, - { 0x00000000, 0x00294901, 0x000 }, - { 0x00000000, 0x00894901, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00804811, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x97000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00002257, 0x00204411, 0x000 }, - { 0x00000003, 0xc0484a20, 0x000 }, - { 0x0000225d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x00000001, 0x40304a20, 0x000 }, - { 0x00000002, 0xc0304a20, 0x000 }, - { 0x00000001, 0x00530a22, 0x34b }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x354 }, - { 0x00000014, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x364 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00604802, 0x36e }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x36a }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35f }, - { 0x00000028, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5bd }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35f }, - { 0x0000002c, 0x00203626, 0x000 }, - { 0x00000049, 0x00201811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0cc00000, 0x370 }, - { 0x0000002c, 0x00801a2d, 0x000 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x00000015, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x386 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b1 }, - { 0x00000016, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b5 }, - { 0x00000020, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x39c }, - { 0x0000000f, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a8 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a8 }, - { 0x0000001e, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x390 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x08000000, 0x00290a22, 0x000 }, - { 0x00000003, 0x40210e20, 0x000 }, - { 0x0000000c, 0xc0211220, 0x000 }, - { 0x00080000, 0x00281224, 0x000 }, - { 0x00000014, 0xc0221620, 0x000 }, - { 0x00000000, 0x002914a4, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x002948a2, 0x000 }, - { 0x0000a1fe, 0x00204411, 0x000 }, - { 0x00000000, 0x00404803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000015, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x392 }, - { 0x0000210e, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000017, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000003, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x39e }, - { 0x00002108, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x80000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000010, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3ae }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000006, 0x00404811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x0000001d, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x3ce }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x3c0 }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0xbabecafe, 0x00204811, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000004, 0x00404811, 0x000 }, - { 0x00002170, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000a, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3d3 }, - { 0x8c000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00003fff, 0x40280a20, 0x000 }, - { 0x80000000, 0x40280e20, 0x000 }, - { 0x40000000, 0xc0281220, 0x000 }, - { 0x00040000, 0x00694622, 0x68a }, - { 0x00000000, 0x00201410, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e1 }, - { 0x00000000, 0xc0401800, 0x3e4 }, - { 0x00003fff, 0xc0281a20, 0x000 }, - { 0x00040000, 0x00694626, 0x68a }, - { 0x00000000, 0x00201810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e7 }, - { 0x00000000, 0xc0401c00, 0x3ea }, - { 0x00003fff, 0xc0281e20, 0x000 }, - { 0x00040000, 0x00694627, 0x68a }, - { 0x00000000, 0x00201c10, 0x000 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0x002820c5, 0x000 }, - { 0x00000000, 0x004948e8, 0x000 }, - { 0xa5800000, 0x00200811, 0x000 }, - { 0x00002000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x0000001f, 0xc0210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x3f7 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000ffff, 0xc0481220, 0x3ff }, - { 0xa7800000, 0x00200811, 0x000 }, - { 0x0000a000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00304883, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xa9800000, 0x00200811, 0x000 }, - { 0x0000c000, 0x00400c11, 0x3fa }, - { 0xab800000, 0x00200811, 0x000 }, - { 0x0000f8e0, 0x00400c11, 0x3fa }, - { 0xad800000, 0x00200811, 0x000 }, - { 0x0000f880, 0x00400c11, 0x3fa }, - { 0xb3800000, 0x00200811, 0x000 }, - { 0x0000f3fc, 0x00400c11, 0x3fa }, - { 0xaf800000, 0x00200811, 0x000 }, - { 0x0000e000, 0x00400c11, 0x3fa }, - { 0xb1800000, 0x00200811, 0x000 }, - { 0x0000f000, 0x00400c11, 0x3fa }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00002148, 0x00204811, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x01182000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0218a000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0318c000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0418f8e0, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0518f880, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0618e000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0718f000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0818f3fc, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000030, 0x00200a2d, 0x000 }, - { 0x00000000, 0xc0290c40, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x86000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x85000000, 0xc0204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00404c02, 0x448 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x00000000, 0xc0201400, 0x000 }, - { 0x00000000, 0xc0201800, 0x000 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x456 }, - { 0x00000000, 0xc0202000, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x00000010, 0x00280a23, 0x000 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x45e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x68a }, - { 0x00000000, 0x00400000, 0x463 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00604805, 0x68f }, - { 0x00000000, 0x002824f0, 0x000 }, - { 0x00000007, 0x00280a23, 0x000 }, - { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46a }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x04e00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46f }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x02e00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x474 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ce00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x479 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ae00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000005, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x47e }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x06e00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x483 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x08e00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x000 }, - { 0x00000008, 0x00210a23, 0x000 }, - { 0x00000000, 0x14c00000, 0x48d }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x496 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x00404c08, 0x456 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000011, 0x40211220, 0x000 }, - { 0x00000012, 0x40211620, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00210225, 0x000 }, - { 0x00000000, 0x14e00000, 0x4a0 }, - { 0x00040000, 0xc0494a20, 0x4a1 }, - { 0xfffbffff, 0xc0284a20, 0x000 }, - { 0x00000000, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x4ad }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000c, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x4a9 }, - { 0xa0000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000004, 0x00204811, 0x000 }, - { 0x0000216b, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000216c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4a7 }, - { 0x00000000, 0xc0210a20, 0x000 }, - { 0x00000000, 0x14c00000, 0x4c0 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x68f }, - { 0x00000000, 0x00400000, 0x4c4 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0xc0294620, 0x000 }, - { 0x00000000, 0xc0600000, 0x68a }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x4cb }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0404810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000000, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x4cd }, - { 0x00002180, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000003, 0x00333e2f, 0x000 }, - { 0x00000001, 0x00210221, 0x000 }, - { 0x00000000, 0x14e00000, 0x4fd }, - { 0x0000002c, 0x00200a2d, 0x000 }, - { 0x00040000, 0x18e00c11, 0x4ec }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xd8c04800, 0x4e0 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000002d, 0x0020122d, 0x000 }, - { 0x00000000, 0x00290c83, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000011, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4a7 }, - { 0x0000002c, 0xc0203620, 0x000 }, - { 0x0000002d, 0xc0403620, 0x000 }, - { 0x0000000f, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x502 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0xd9000000, 0x000 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xb5000000, 0x00204411, 0x000 }, - { 0x00002000, 0x00204811, 0x000 }, - { 0xb6000000, 0x00204411, 0x000 }, - { 0x0000a000, 0x00204811, 0x000 }, - { 0xb7000000, 0x00204411, 0x000 }, - { 0x0000c000, 0x00204811, 0x000 }, - { 0xb8000000, 0x00204411, 0x000 }, - { 0x0000f8e0, 0x00204811, 0x000 }, - { 0xb9000000, 0x00204411, 0x000 }, - { 0x0000f880, 0x00204811, 0x000 }, - { 0xba000000, 0x00204411, 0x000 }, - { 0x0000e000, 0x00204811, 0x000 }, - { 0xbb000000, 0x00204411, 0x000 }, - { 0x0000f000, 0x00204811, 0x000 }, - { 0xbc000000, 0x00204411, 0x000 }, - { 0x0000f3fc, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000002, 0x00204811, 0x000 }, - { 0x000000ff, 0x00280e30, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x516 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x14c00000, 0x52b }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000001c, 0x00203623, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000029, 0x00203623, 0x000 }, - { 0x00000028, 0x00203623, 0x000 }, - { 0x00000017, 0x00203623, 0x000 }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203623, 0x000 }, - { 0x00000015, 0x00203623, 0x000 }, - { 0x00000016, 0x00203623, 0x000 }, - { 0xffffe000, 0x00200c11, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203623, 0x000 }, - { 0x00001fff, 0x00200c11, 0x000 }, - { 0x00000023, 0x00203623, 0x000 }, - { 0x00000024, 0x00203623, 0x000 }, - { 0xf1ffffff, 0x00283a2e, 0x000 }, - { 0x0000001a, 0xc0220e20, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000002a, 0x40203620, 0x000 }, - { 0x87000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x9d000000, 0x00204411, 0x000 }, - { 0x0000001f, 0x40214a20, 0x000 }, - { 0x96000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x0000001f, 0x00211624, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x0000001d, 0x00203623, 0x000 }, - { 0x00000003, 0x00281e23, 0x000 }, - { 0x00000008, 0x00222223, 0x000 }, - { 0xfffff000, 0x00282228, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x0000001f, 0x00203628, 0x000 }, - { 0x00000018, 0x00211e23, 0x000 }, - { 0x00000020, 0x00203627, 0x000 }, - { 0x00000002, 0x00221624, 0x000 }, - { 0x00000000, 0x003014a8, 0x000 }, - { 0x0000001e, 0x00203625, 0x000 }, - { 0x00000003, 0x00211a24, 0x000 }, - { 0x10000000, 0x00281a26, 0x000 }, - { 0xefffffff, 0x00283a2e, 0x000 }, - { 0x00000000, 0x004938ce, 0x678 }, - { 0x00000001, 0x40280a20, 0x000 }, - { 0x00000006, 0x40280e20, 0x000 }, - { 0x00000300, 0xc0281220, 0x000 }, - { 0x00000008, 0x00211224, 0x000 }, - { 0x00000000, 0xc0201620, 0x000 }, - { 0x00000000, 0xc0201a20, 0x000 }, - { 0x00000000, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x563 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68a }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00020000, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56b }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56b }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68a }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56f }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x577 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x68f }, - { 0x00000000, 0x00401c10, 0x579 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x57b }, - { 0x00000000, 0x00600000, 0x5c6 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x58c }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x58a }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x59d }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x59b }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5ae }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5ac }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5bb }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5c1 }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5c6 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000002c, 0x00203621, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0230, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5cd }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000030, 0x00403621, 0x5e0 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5e0 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a092, 0x00604411, 0x68a }, - { 0x00000031, 0x00203630, 0x000 }, - { 0x0004a093, 0x00604411, 0x68a }, - { 0x00000032, 0x00203630, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68a }, - { 0x00000033, 0x00203630, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68a }, - { 0x00000034, 0x00203630, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68a }, - { 0x00000035, 0x00203630, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68a }, - { 0x00000036, 0x00203630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000001, 0x002f0230, 0x000 }, - { 0x00000000, 0x0ce00000, 0x629 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x629 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x602 }, - { 0x0000a092, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x0000a093, 0x00204411, 0x000 }, - { 0x00000032, 0x00204a2d, 0x000 }, - { 0x0000a2b6, 0x00204411, 0x000 }, - { 0x00000033, 0x00204a2d, 0x000 }, - { 0x0000a2ba, 0x00204411, 0x000 }, - { 0x00000034, 0x00204a2d, 0x000 }, - { 0x0000a2be, 0x00204411, 0x000 }, - { 0x00000035, 0x00204a2d, 0x000 }, - { 0x0000a2c2, 0x00204411, 0x000 }, - { 0x00000036, 0x00204a2d, 0x000 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x000001ff, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x628 }, - { 0x00000000, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x60b }, - { 0x0004a003, 0x00604411, 0x68a }, - { 0x0000a003, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x14c00000, 0x610 }, - { 0x0004a010, 0x00604411, 0x68a }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x628 }, - { 0x0004a011, 0x00604411, 0x68a }, - { 0x0000a011, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a012, 0x00604411, 0x68a }, - { 0x0000a012, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a013, 0x00604411, 0x68a }, - { 0x0000a013, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a014, 0x00604411, 0x68a }, - { 0x0000a014, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a015, 0x00604411, 0x68a }, - { 0x0000a015, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a016, 0x00604411, 0x68a }, - { 0x0000a016, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a017, 0x00604411, 0x68a }, - { 0x0000a017, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000002c, 0x0080062d, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x63a }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000002, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x638 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x63e }, - { 0x00000000, 0x00600000, 0x5c6 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x63e }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x62a }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x62a }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x653 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x689 }, - { 0x00000010, 0x00404c11, 0x66f }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x688 }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68a }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x68d }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68f }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x692 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x014204ff, 0x05bd0250, 0x000 }, - { 0x01c30168, 0x043f05bd, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03d705bd, 0x05bd05bd, 0x000 }, - { 0x06460647, 0x031f05bd, 0x000 }, - { 0x05bd05c2, 0x03200340, 0x000 }, - { 0x032a0282, 0x03420334, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd054e, 0x05bd05bd, 0x000 }, - { 0x03ba05bd, 0x04b80344, 0x000 }, - { 0x0497044d, 0x043d05bd, 0x000 }, - { 0x04cd05bd, 0x044104da, 0x000 }, - { 0x044d0504, 0x03510375, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x063c05c4, 0x000 }, - { 0x05bd05bd, 0x000705bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x03f803ed, 0x04080406, 0x000 }, - { 0x040e040a, 0x040c0410, 0x000 }, - { 0x041c0418, 0x04240420, 0x000 }, - { 0x042c0428, 0x04340430, 0x000 }, - { 0x05bd05bd, 0x043805bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x00020676, 0x06940006, 0x000 }, -}; - -static const u32 RV630_pfp_microcode[] = { -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001b8, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800053, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b8, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x800079, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008d, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401bb, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401bb, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b8, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001b8, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f0, -0xcc1003, -0x98801b, -0x04380c, -0x8400f0, -0xcc1003, -0x988017, -0x043808, -0x8400f0, -0xcc1003, -0x988013, -0x043804, -0x8400f0, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000c9, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001b8, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001b8, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b8, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800101, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d9, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bd, -0x000000, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902b0, -0x7c738b, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984297, -0x000000, -0x800161, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001b8, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010171, -0x020178, -0x03008f, -0x04007f, -0x050003, -0x06003f, -0x070032, -0x08012c, -0x090046, -0x0a0036, -0x1001b6, -0x1700a2, -0x22013a, -0x230149, -0x2000b4, -0x240125, -0x27004d, -0x28006a, -0x2a0060, -0x2b0052, -0x2f0065, -0x320087, -0x34017f, -0x3c0156, -0x3f0072, -0x41018c, -0x44012e, -0x550173, -0x56017a, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; - -static const u32 RV635_cp_microcode[][3] = { - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x665 }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 0x00400c11, 0x0d6 }, - { 0x00001f00, 0x00400c11, 0x0d6 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0dc }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00280e22, 0x000 }, - { 0x00000080, 0x00294a23, 0x000 }, - { 0x00000027, 0x00200e2d, 0x000 }, - { 0x00000026, 0x0020122d, 0x000 }, - { 0x00000000, 0x002f0083, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0ea }, - { 0x00000000, 0x00600000, 0x65f }, - { 0x00000000, 0x00400000, 0x0eb }, - { 0x00000000, 0x00600000, 0x662 }, - { 0x00000007, 0x0020222d, 0x000 }, - { 0x00000005, 0x00220e22, 0x000 }, - { 0x00100000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x000000ef, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000003, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x0f8 }, - { 0x0000000b, 0x00210228, 0x000 }, - { 0x00000000, 0x14c00000, 0x0f8 }, - { 0x00000400, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000001c, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x0fd }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000001e, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x10b }, - { 0x0000a30f, 0x00204411, 0x000 }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x104 }, - { 0xffffffff, 0x00404811, 0x10b }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x107 }, - { 0x0000ffff, 0x00404811, 0x10b }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x10a }, - { 0x000000ff, 0x00404811, 0x10b }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0002c400, 0x00204411, 0x000 }, - { 0x0000001f, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x112 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000018, 0x40224a20, 0x000 }, - { 0x00000010, 0xc0424a20, 0x114 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000000a, 0x00201011, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x11b }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00531224, 0x117 }, - { 0xffbfffff, 0x00283a2e, 0x000 }, - { 0x0000001b, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x12e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0x00000018, 0x00220e30, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e00e, 0x00204411, 0x000 }, - { 0x07f8ff08, 0x00204811, 0x000 }, - { 0x00000000, 0x00294a23, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00800000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204806, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x689 }, - { 0x00000004, 0x00404c11, 0x135 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000001c, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x13c }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40280620, 0x000 }, - { 0x00000010, 0xc0210a20, 0x000 }, - { 0x00000000, 0x00341461, 0x000 }, - { 0x00000000, 0x00741882, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x147 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0681a20, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x158 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000001, 0x00300a2f, 0x000 }, - { 0x00000001, 0x00210a22, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600000, 0x18f }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00202c08, 0x000 }, - { 0x00000000, 0x00202411, 0x000 }, - { 0x00000000, 0x00202811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000002, 0x00221e29, 0x000 }, - { 0x00000000, 0x007048eb, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000001, 0x40330620, 0x000 }, - { 0x00000000, 0xc0302409, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ae00000, 0x181 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x186 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x186 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000001, 0x00530621, 0x182 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0604800, 0x197 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000011, 0x0020062d, 0x000 }, - { 0x00000000, 0x0078042a, 0x2fb }, - { 0x00000000, 0x00202809, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x174 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x194 }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x46000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x19b }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00804811, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40281620, 0x000 }, - { 0x00000010, 0xc0811a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000008, 0x00221e30, 0x000 }, - { 0x00000029, 0x00201a2d, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfffbff09, 0x00204811, 0x000 }, - { 0x0000000f, 0x0020222d, 0x000 }, - { 0x00001fff, 0x00294a28, 0x000 }, - { 0x00000006, 0x0020222d, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000100, 0x00201811, 0x000 }, - { 0x00000008, 0x00621e28, 0x12f }, - { 0x00000008, 0x00822228, 0x000 }, - { 0x0002c000, 0x00204411, 0x000 }, - { 0x00000015, 0x00600e2d, 0x1bd }, - { 0x00000016, 0x00600e2d, 0x1bd }, - { 0x0000c008, 0x00204411, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000000, 0x14c00000, 0x1b9 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x39000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00804802, 0x000 }, - { 0x00000018, 0x00202e2d, 0x000 }, - { 0x00000000, 0x003b0d63, 0x000 }, - { 0x00000008, 0x00224a23, 0x000 }, - { 0x00000010, 0x00224a23, 0x000 }, - { 0x00000018, 0x00224a23, 0x000 }, - { 0x00000000, 0x00804803, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000007, 0x0021062f, 0x000 }, - { 0x00000013, 0x00200a2d, 0x000 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000ffff, 0x40282220, 0x000 }, - { 0x0000000f, 0x00262228, 0x000 }, - { 0x00000010, 0x40212620, 0x000 }, - { 0x0000000f, 0x00262629, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1e0 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000081, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000080, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1dc }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1d8 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000001f, 0x00280a22, 0x000 }, - { 0x0000001f, 0x00282a2a, 0x000 }, - { 0x00000001, 0x00530621, 0x1d1 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000002, 0x00304a2f, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000001, 0x00301e2f, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1e5 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x0000000f, 0x00260e23, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000000f, 0x00261224, 0x000 }, - { 0x00000000, 0x00201411, 0x000 }, - { 0x00000000, 0x00601811, 0x2bb }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022b, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1f8 }, - { 0x00000010, 0x00221628, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a29, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x0020480a, 0x000 }, - { 0x00000000, 0x00202c11, 0x000 }, - { 0x00000010, 0x00221623, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a24, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x00731503, 0x205 }, - { 0x00000000, 0x00201805, 0x000 }, - { 0x00000000, 0x00731524, 0x205 }, - { 0x00000000, 0x002d14c5, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00000000, 0x00202003, 0x000 }, - { 0x00000000, 0x00802404, 0x000 }, - { 0x0000000f, 0x00210225, 0x000 }, - { 0x00000000, 0x14c00000, 0x689 }, - { 0x00000000, 0x002b1405, 0x000 }, - { 0x00000001, 0x00901625, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00294a22, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a21, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000ffff, 0x40281220, 0x000 }, - { 0x00000010, 0xc0211a20, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211620, 0x000 }, - { 0x00000000, 0x00741465, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00000001, 0x00330621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0cc00000, 0x219 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x212 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000000, 0x0040040f, 0x213 }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00000000, 0x00600000, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ae00000, 0x232 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x236 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x236 }, - { 0x00000000, 0xc0404800, 0x233 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x00600411, 0x2fb }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000018, 0x40210a20, 0x000 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x24c }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x00080101, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x251 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000010, 0x00600411, 0x315 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00000000, 0x00600000, 0x27c }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000001, 0x00211e27, 0x000 }, - { 0x00000000, 0x14e00000, 0x26a }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x0000ffff, 0x00281e27, 0x000 }, - { 0x00000000, 0x00341c27, 0x000 }, - { 0x00000000, 0x12c00000, 0x25f }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e5, 0x000 }, - { 0x00000000, 0x08c00000, 0x262 }, - { 0x00000000, 0x00201407, 0x000 }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00211e27, 0x000 }, - { 0x00000000, 0x00341c47, 0x000 }, - { 0x00000000, 0x12c00000, 0x267 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x08c00000, 0x26a }, - { 0x00000000, 0x00201807, 0x000 }, - { 0x00000000, 0x00600000, 0x2c1 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000000, 0x00342023, 0x000 }, - { 0x00000000, 0x12c00000, 0x272 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x271 }, - { 0x00000016, 0x00404811, 0x276 }, - { 0x00000018, 0x00404811, 0x276 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x275 }, - { 0x00000017, 0x00404811, 0x276 }, - { 0x00000019, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00604411, 0x2e9 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x256 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000010, 0x40210620, 0x000 }, - { 0x0000ffff, 0xc0280a20, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0881a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x00000000, 0xc0600000, 0x2a3 }, - { 0x00000005, 0x00200a2d, 0x000 }, - { 0x00000008, 0x00220a22, 0x000 }, - { 0x0000002b, 0x00201a2d, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00007000, 0x00281e27, 0x000 }, - { 0x00000000, 0x00311ce6, 0x000 }, - { 0x0000002a, 0x00201a2d, 0x000 }, - { 0x0000000c, 0x00221a26, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x06e00000, 0x292 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00691ce2, 0x12f }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x29d }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000001c, 0x00403627, 0x000 }, - { 0x0000000c, 0xc0220a20, 0x000 }, - { 0x00000029, 0x00203622, 0x000 }, - { 0x00000028, 0xc0403620, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000009, 0x00204811, 0x000 }, - { 0xa1000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce3, 0x000 }, - { 0x00000021, 0x00203627, 0x000 }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce4, 0x000 }, - { 0x00000022, 0x00203627, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a3, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203624, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000000, 0x00311cc4, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14c00000, 0x2dc }, - { 0x00000000, 0x00400000, 0x2d9 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2d9 }, - { 0x00000003, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2dc }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e1, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a1, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e2, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000000, 0x00600000, 0x665 }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00600000, 0x65c }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2a7 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x0000001a, 0x00201e2d, 0x000 }, - { 0x0000001b, 0x0080222d, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca1, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x003808c5, 0x000 }, - { 0x00000000, 0x00300841, 0x000 }, - { 0x00000001, 0x00220a22, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000017, 0x0020222d, 0x000 }, - { 0x00000000, 0x14c00000, 0x318 }, - { 0xffffffef, 0x00280621, 0x000 }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x0000f8e0, 0x00204411, 0x000 }, - { 0x00000000, 0x00294901, 0x000 }, - { 0x00000000, 0x00894901, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00804811, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x97000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00002257, 0x00204411, 0x000 }, - { 0x00000003, 0xc0484a20, 0x000 }, - { 0x0000225d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x00000001, 0x40304a20, 0x000 }, - { 0x00000002, 0xc0304a20, 0x000 }, - { 0x00000001, 0x00530a22, 0x34b }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x354 }, - { 0x00000014, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x364 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00604802, 0x36e }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x36a }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35f }, - { 0x00000028, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5bd }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35f }, - { 0x0000002c, 0x00203626, 0x000 }, - { 0x00000049, 0x00201811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0cc00000, 0x370 }, - { 0x0000002c, 0x00801a2d, 0x000 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x00000015, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x386 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b1 }, - { 0x00000016, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b5 }, - { 0x00000020, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x39c }, - { 0x0000000f, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a8 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a8 }, - { 0x0000001e, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x390 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x08000000, 0x00290a22, 0x000 }, - { 0x00000003, 0x40210e20, 0x000 }, - { 0x0000000c, 0xc0211220, 0x000 }, - { 0x00080000, 0x00281224, 0x000 }, - { 0x00000014, 0xc0221620, 0x000 }, - { 0x00000000, 0x002914a4, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x002948a2, 0x000 }, - { 0x0000a1fe, 0x00204411, 0x000 }, - { 0x00000000, 0x00404803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000015, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x392 }, - { 0x0000210e, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000017, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000003, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x39e }, - { 0x00002108, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x80000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000010, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3ae }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000006, 0x00404811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x0000001d, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x3ce }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x3c0 }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0xbabecafe, 0x00204811, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000004, 0x00404811, 0x000 }, - { 0x00002170, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000a, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3d3 }, - { 0x8c000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00003fff, 0x40280a20, 0x000 }, - { 0x80000000, 0x40280e20, 0x000 }, - { 0x40000000, 0xc0281220, 0x000 }, - { 0x00040000, 0x00694622, 0x68a }, - { 0x00000000, 0x00201410, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e1 }, - { 0x00000000, 0xc0401800, 0x3e4 }, - { 0x00003fff, 0xc0281a20, 0x000 }, - { 0x00040000, 0x00694626, 0x68a }, - { 0x00000000, 0x00201810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e7 }, - { 0x00000000, 0xc0401c00, 0x3ea }, - { 0x00003fff, 0xc0281e20, 0x000 }, - { 0x00040000, 0x00694627, 0x68a }, - { 0x00000000, 0x00201c10, 0x000 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0x002820c5, 0x000 }, - { 0x00000000, 0x004948e8, 0x000 }, - { 0xa5800000, 0x00200811, 0x000 }, - { 0x00002000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x0000001f, 0xc0210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x3f7 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000ffff, 0xc0481220, 0x3ff }, - { 0xa7800000, 0x00200811, 0x000 }, - { 0x0000a000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00304883, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xa9800000, 0x00200811, 0x000 }, - { 0x0000c000, 0x00400c11, 0x3fa }, - { 0xab800000, 0x00200811, 0x000 }, - { 0x0000f8e0, 0x00400c11, 0x3fa }, - { 0xad800000, 0x00200811, 0x000 }, - { 0x0000f880, 0x00400c11, 0x3fa }, - { 0xb3800000, 0x00200811, 0x000 }, - { 0x0000f3fc, 0x00400c11, 0x3fa }, - { 0xaf800000, 0x00200811, 0x000 }, - { 0x0000e000, 0x00400c11, 0x3fa }, - { 0xb1800000, 0x00200811, 0x000 }, - { 0x0000f000, 0x00400c11, 0x3fa }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00002148, 0x00204811, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x01182000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0218a000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0318c000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0418f8e0, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0518f880, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0618e000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0718f000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0818f3fc, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000030, 0x00200a2d, 0x000 }, - { 0x00000000, 0xc0290c40, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x86000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x85000000, 0xc0204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00404c02, 0x448 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x00000000, 0xc0201400, 0x000 }, - { 0x00000000, 0xc0201800, 0x000 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x456 }, - { 0x00000000, 0xc0202000, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x00000010, 0x00280a23, 0x000 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x45e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x68a }, - { 0x00000000, 0x00400000, 0x463 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00604805, 0x68f }, - { 0x00000000, 0x002824f0, 0x000 }, - { 0x00000007, 0x00280a23, 0x000 }, - { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46a }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x04e00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46f }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x02e00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x474 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ce00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x479 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ae00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000005, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x47e }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x06e00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x483 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x08e00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x000 }, - { 0x00000008, 0x00210a23, 0x000 }, - { 0x00000000, 0x14c00000, 0x48d }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x496 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x00404c08, 0x456 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000011, 0x40211220, 0x000 }, - { 0x00000012, 0x40211620, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00210225, 0x000 }, - { 0x00000000, 0x14e00000, 0x4a0 }, - { 0x00040000, 0xc0494a20, 0x4a1 }, - { 0xfffbffff, 0xc0284a20, 0x000 }, - { 0x00000000, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x4ad }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000c, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x4a9 }, - { 0xa0000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000004, 0x00204811, 0x000 }, - { 0x0000216b, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000216c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4a7 }, - { 0x00000000, 0xc0210a20, 0x000 }, - { 0x00000000, 0x14c00000, 0x4c0 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x68f }, - { 0x00000000, 0x00400000, 0x4c4 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0xc0294620, 0x000 }, - { 0x00000000, 0xc0600000, 0x68a }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x4cb }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0404810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000000, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x4cd }, - { 0x00002180, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000003, 0x00333e2f, 0x000 }, - { 0x00000001, 0x00210221, 0x000 }, - { 0x00000000, 0x14e00000, 0x4fd }, - { 0x0000002c, 0x00200a2d, 0x000 }, - { 0x00040000, 0x18e00c11, 0x4ec }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xd8c04800, 0x4e0 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000002d, 0x0020122d, 0x000 }, - { 0x00000000, 0x00290c83, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000011, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4a7 }, - { 0x0000002c, 0xc0203620, 0x000 }, - { 0x0000002d, 0xc0403620, 0x000 }, - { 0x0000000f, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x502 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0xd9000000, 0x000 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xb5000000, 0x00204411, 0x000 }, - { 0x00002000, 0x00204811, 0x000 }, - { 0xb6000000, 0x00204411, 0x000 }, - { 0x0000a000, 0x00204811, 0x000 }, - { 0xb7000000, 0x00204411, 0x000 }, - { 0x0000c000, 0x00204811, 0x000 }, - { 0xb8000000, 0x00204411, 0x000 }, - { 0x0000f8e0, 0x00204811, 0x000 }, - { 0xb9000000, 0x00204411, 0x000 }, - { 0x0000f880, 0x00204811, 0x000 }, - { 0xba000000, 0x00204411, 0x000 }, - { 0x0000e000, 0x00204811, 0x000 }, - { 0xbb000000, 0x00204411, 0x000 }, - { 0x0000f000, 0x00204811, 0x000 }, - { 0xbc000000, 0x00204411, 0x000 }, - { 0x0000f3fc, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000002, 0x00204811, 0x000 }, - { 0x000000ff, 0x00280e30, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x516 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x14c00000, 0x52b }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000001c, 0x00203623, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000029, 0x00203623, 0x000 }, - { 0x00000028, 0x00203623, 0x000 }, - { 0x00000017, 0x00203623, 0x000 }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203623, 0x000 }, - { 0x00000015, 0x00203623, 0x000 }, - { 0x00000016, 0x00203623, 0x000 }, - { 0xffffe000, 0x00200c11, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203623, 0x000 }, - { 0x00001fff, 0x00200c11, 0x000 }, - { 0x00000023, 0x00203623, 0x000 }, - { 0x00000024, 0x00203623, 0x000 }, - { 0xf1ffffff, 0x00283a2e, 0x000 }, - { 0x0000001a, 0xc0220e20, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000002a, 0x40203620, 0x000 }, - { 0x87000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x9d000000, 0x00204411, 0x000 }, - { 0x0000001f, 0x40214a20, 0x000 }, - { 0x96000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x0000001f, 0x00211624, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x0000001d, 0x00203623, 0x000 }, - { 0x00000003, 0x00281e23, 0x000 }, - { 0x00000008, 0x00222223, 0x000 }, - { 0xfffff000, 0x00282228, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x0000001f, 0x00203628, 0x000 }, - { 0x00000018, 0x00211e23, 0x000 }, - { 0x00000020, 0x00203627, 0x000 }, - { 0x00000002, 0x00221624, 0x000 }, - { 0x00000000, 0x003014a8, 0x000 }, - { 0x0000001e, 0x00203625, 0x000 }, - { 0x00000003, 0x00211a24, 0x000 }, - { 0x10000000, 0x00281a26, 0x000 }, - { 0xefffffff, 0x00283a2e, 0x000 }, - { 0x00000000, 0x004938ce, 0x678 }, - { 0x00000001, 0x40280a20, 0x000 }, - { 0x00000006, 0x40280e20, 0x000 }, - { 0x00000300, 0xc0281220, 0x000 }, - { 0x00000008, 0x00211224, 0x000 }, - { 0x00000000, 0xc0201620, 0x000 }, - { 0x00000000, 0xc0201a20, 0x000 }, - { 0x00000000, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x563 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68a }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00020000, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56b }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56b }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68a }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56f }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x577 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x68f }, - { 0x00000000, 0x00401c10, 0x579 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x57b }, - { 0x00000000, 0x00600000, 0x5c6 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x58c }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x58a }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x59d }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x59b }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5ae }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5ac }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5bb }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5c1 }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5c6 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000002c, 0x00203621, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0230, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5cd }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000030, 0x00403621, 0x5e0 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5e0 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a092, 0x00604411, 0x68a }, - { 0x00000031, 0x00203630, 0x000 }, - { 0x0004a093, 0x00604411, 0x68a }, - { 0x00000032, 0x00203630, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68a }, - { 0x00000033, 0x00203630, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68a }, - { 0x00000034, 0x00203630, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68a }, - { 0x00000035, 0x00203630, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68a }, - { 0x00000036, 0x00203630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000001, 0x002f0230, 0x000 }, - { 0x00000000, 0x0ce00000, 0x629 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x629 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x602 }, - { 0x0000a092, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x0000a093, 0x00204411, 0x000 }, - { 0x00000032, 0x00204a2d, 0x000 }, - { 0x0000a2b6, 0x00204411, 0x000 }, - { 0x00000033, 0x00204a2d, 0x000 }, - { 0x0000a2ba, 0x00204411, 0x000 }, - { 0x00000034, 0x00204a2d, 0x000 }, - { 0x0000a2be, 0x00204411, 0x000 }, - { 0x00000035, 0x00204a2d, 0x000 }, - { 0x0000a2c2, 0x00204411, 0x000 }, - { 0x00000036, 0x00204a2d, 0x000 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x000001ff, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x628 }, - { 0x00000000, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x60b }, - { 0x0004a003, 0x00604411, 0x68a }, - { 0x0000a003, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x14c00000, 0x610 }, - { 0x0004a010, 0x00604411, 0x68a }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x628 }, - { 0x0004a011, 0x00604411, 0x68a }, - { 0x0000a011, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a012, 0x00604411, 0x68a }, - { 0x0000a012, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a013, 0x00604411, 0x68a }, - { 0x0000a013, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a014, 0x00604411, 0x68a }, - { 0x0000a014, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a015, 0x00604411, 0x68a }, - { 0x0000a015, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a016, 0x00604411, 0x68a }, - { 0x0000a016, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a017, 0x00604411, 0x68a }, - { 0x0000a017, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000002c, 0x0080062d, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x63a }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000002, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x638 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x63e }, - { 0x00000000, 0x00600000, 0x5c6 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x63e }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x62a }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x62a }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x653 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x689 }, - { 0x00000010, 0x00404c11, 0x66f }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x688 }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68a }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x68d }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68f }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x692 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x014204ff, 0x05bd0250, 0x000 }, - { 0x01c30168, 0x043f05bd, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03d705bd, 0x05bd05bd, 0x000 }, - { 0x06460647, 0x031f05bd, 0x000 }, - { 0x05bd05c2, 0x03200340, 0x000 }, - { 0x032a0282, 0x03420334, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd054e, 0x05bd05bd, 0x000 }, - { 0x03ba05bd, 0x04b80344, 0x000 }, - { 0x0497044d, 0x043d05bd, 0x000 }, - { 0x04cd05bd, 0x044104da, 0x000 }, - { 0x044d0504, 0x03510375, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x063c05c4, 0x000 }, - { 0x05bd05bd, 0x000705bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x03f803ed, 0x04080406, 0x000 }, - { 0x040e040a, 0x040c0410, 0x000 }, - { 0x041c0418, 0x04240420, 0x000 }, - { 0x042c0428, 0x04340430, 0x000 }, - { 0x05bd05bd, 0x043805bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x00020676, 0x06940006, 0x000 }, -}; - -static const u32 RV635_pfp_microcode[] = { -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001b8, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800053, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b8, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x800079, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008d, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401bb, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401bb, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b8, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001b8, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f0, -0xcc1003, -0x98801b, -0x04380c, -0x8400f0, -0xcc1003, -0x988017, -0x043808, -0x8400f0, -0xcc1003, -0x988013, -0x043804, -0x8400f0, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000c9, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001b8, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001b8, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b8, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800101, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d9, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bd, -0x000000, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902b0, -0x7c738b, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984297, -0x000000, -0x800161, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001b8, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010171, -0x020178, -0x03008f, -0x04007f, -0x050003, -0x06003f, -0x070032, -0x08012c, -0x090046, -0x0a0036, -0x1001b6, -0x1700a2, -0x22013a, -0x230149, -0x2000b4, -0x240125, -0x27004d, -0x28006a, -0x2a0060, -0x2b0052, -0x2f0065, -0x320087, -0x34017f, -0x3c0156, -0x3f0072, -0x41018c, -0x44012e, -0x550173, -0x56017a, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; - -static const u32 RV670_cp_microcode[][3] = { - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x00000000, 0x00600000, 0x624 }, - { 0x00000000, 0x00600000, 0x638 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00000000, 0x00600000, 0x64d }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 0x00400c11, 0x0d6 }, - { 0x00001f00, 0x00400c11, 0x0d6 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0dc }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00280e22, 0x000 }, - { 0x00000080, 0x00294a23, 0x000 }, - { 0x00000027, 0x00200e2d, 0x000 }, - { 0x00000026, 0x0020122d, 0x000 }, - { 0x00000000, 0x002f0083, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0ea }, - { 0x00000000, 0x00600000, 0x653 }, - { 0x00000000, 0x00400000, 0x0eb }, - { 0x00000000, 0x00600000, 0x656 }, - { 0x00000007, 0x0020222d, 0x000 }, - { 0x00000005, 0x00220e22, 0x000 }, - { 0x00100000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x000000ef, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000003, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x0f8 }, - { 0x0000000b, 0x00210228, 0x000 }, - { 0x00000000, 0x14c00000, 0x0f8 }, - { 0x00000400, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000001c, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x0fd }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000001e, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x10b }, - { 0x0000a30f, 0x00204411, 0x000 }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x104 }, - { 0xffffffff, 0x00404811, 0x10b }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x107 }, - { 0x0000ffff, 0x00404811, 0x10b }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x10a }, - { 0x000000ff, 0x00404811, 0x10b }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0002c400, 0x00204411, 0x000 }, - { 0x0000001f, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x112 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000018, 0x40224a20, 0x000 }, - { 0x00000010, 0xc0424a20, 0x114 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000000a, 0x00201011, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x11b }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00531224, 0x117 }, - { 0xffbfffff, 0x00283a2e, 0x000 }, - { 0x0000001b, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x12e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0x00000018, 0x00220e30, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e00e, 0x00204411, 0x000 }, - { 0x07f8ff08, 0x00204811, 0x000 }, - { 0x00000000, 0x00294a23, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00800000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204806, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x67c }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x67b }, - { 0x00000004, 0x00404c11, 0x135 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000001c, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x67c }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x13c }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40280620, 0x000 }, - { 0x00000010, 0xc0210a20, 0x000 }, - { 0x00000000, 0x00341461, 0x000 }, - { 0x00000000, 0x00741882, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x147 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0681a20, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x158 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000001, 0x00300a2f, 0x000 }, - { 0x00000001, 0x00210a22, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600000, 0x18f }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00202c08, 0x000 }, - { 0x00000000, 0x00202411, 0x000 }, - { 0x00000000, 0x00202811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000002, 0x00221e29, 0x000 }, - { 0x00000000, 0x007048eb, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000001, 0x40330620, 0x000 }, - { 0x00000000, 0xc0302409, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ae00000, 0x181 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x186 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x186 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000001, 0x00530621, 0x182 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0604800, 0x197 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000011, 0x0020062d, 0x000 }, - { 0x00000000, 0x0078042a, 0x2fb }, - { 0x00000000, 0x00202809, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x174 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x194 }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x46000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x19b }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00804811, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40281620, 0x000 }, - { 0x00000010, 0xc0811a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000008, 0x00221e30, 0x000 }, - { 0x00000029, 0x00201a2d, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfffbff09, 0x00204811, 0x000 }, - { 0x0000000f, 0x0020222d, 0x000 }, - { 0x00001fff, 0x00294a28, 0x000 }, - { 0x00000006, 0x0020222d, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000100, 0x00201811, 0x000 }, - { 0x00000008, 0x00621e28, 0x12f }, - { 0x00000008, 0x00822228, 0x000 }, - { 0x0002c000, 0x00204411, 0x000 }, - { 0x00000015, 0x00600e2d, 0x1bd }, - { 0x00000016, 0x00600e2d, 0x1bd }, - { 0x0000c008, 0x00204411, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000000, 0x14c00000, 0x1b9 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x39000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00804802, 0x000 }, - { 0x00000018, 0x00202e2d, 0x000 }, - { 0x00000000, 0x003b0d63, 0x000 }, - { 0x00000008, 0x00224a23, 0x000 }, - { 0x00000010, 0x00224a23, 0x000 }, - { 0x00000018, 0x00224a23, 0x000 }, - { 0x00000000, 0x00804803, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000007, 0x0021062f, 0x000 }, - { 0x00000013, 0x00200a2d, 0x000 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000ffff, 0x40282220, 0x000 }, - { 0x0000000f, 0x00262228, 0x000 }, - { 0x00000010, 0x40212620, 0x000 }, - { 0x0000000f, 0x00262629, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1e0 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000081, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000080, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1dc }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1d8 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000001f, 0x00280a22, 0x000 }, - { 0x0000001f, 0x00282a2a, 0x000 }, - { 0x00000001, 0x00530621, 0x1d1 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000002, 0x00304a2f, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000001, 0x00301e2f, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1e5 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x0000000f, 0x00260e23, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000000f, 0x00261224, 0x000 }, - { 0x00000000, 0x00201411, 0x000 }, - { 0x00000000, 0x00601811, 0x2bb }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022b, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1f8 }, - { 0x00000010, 0x00221628, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a29, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x0020480a, 0x000 }, - { 0x00000000, 0x00202c11, 0x000 }, - { 0x00000010, 0x00221623, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a24, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x00731503, 0x205 }, - { 0x00000000, 0x00201805, 0x000 }, - { 0x00000000, 0x00731524, 0x205 }, - { 0x00000000, 0x002d14c5, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00000000, 0x00202003, 0x000 }, - { 0x00000000, 0x00802404, 0x000 }, - { 0x0000000f, 0x00210225, 0x000 }, - { 0x00000000, 0x14c00000, 0x67b }, - { 0x00000000, 0x002b1405, 0x000 }, - { 0x00000001, 0x00901625, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00294a22, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a21, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000ffff, 0x40281220, 0x000 }, - { 0x00000010, 0xc0211a20, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211620, 0x000 }, - { 0x00000000, 0x00741465, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00000001, 0x00330621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0cc00000, 0x219 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x212 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x638 }, - { 0x00000000, 0x0040040f, 0x213 }, - { 0x00000000, 0x00600000, 0x624 }, - { 0x00000000, 0x00600000, 0x638 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00000000, 0x00600000, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ae00000, 0x232 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x236 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x236 }, - { 0x00000000, 0xc0404800, 0x233 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x00600411, 0x2fb }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x624 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000018, 0x40210a20, 0x000 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x24c }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x00080101, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x251 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000010, 0x00600411, 0x315 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00000000, 0x00600000, 0x27c }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000001, 0x00211e27, 0x000 }, - { 0x00000000, 0x14e00000, 0x26a }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x0000ffff, 0x00281e27, 0x000 }, - { 0x00000000, 0x00341c27, 0x000 }, - { 0x00000000, 0x12c00000, 0x25f }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e5, 0x000 }, - { 0x00000000, 0x08c00000, 0x262 }, - { 0x00000000, 0x00201407, 0x000 }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00211e27, 0x000 }, - { 0x00000000, 0x00341c47, 0x000 }, - { 0x00000000, 0x12c00000, 0x267 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x08c00000, 0x26a }, - { 0x00000000, 0x00201807, 0x000 }, - { 0x00000000, 0x00600000, 0x2c1 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000000, 0x00342023, 0x000 }, - { 0x00000000, 0x12c00000, 0x272 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x271 }, - { 0x00000016, 0x00404811, 0x276 }, - { 0x00000018, 0x00404811, 0x276 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x275 }, - { 0x00000017, 0x00404811, 0x276 }, - { 0x00000019, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00604411, 0x2e9 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x256 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000010, 0x40210620, 0x000 }, - { 0x0000ffff, 0xc0280a20, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0881a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x00000000, 0x00600000, 0x624 }, - { 0x00000000, 0xc0600000, 0x2a3 }, - { 0x00000005, 0x00200a2d, 0x000 }, - { 0x00000008, 0x00220a22, 0x000 }, - { 0x0000002b, 0x00201a2d, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00007000, 0x00281e27, 0x000 }, - { 0x00000000, 0x00311ce6, 0x000 }, - { 0x0000002a, 0x00201a2d, 0x000 }, - { 0x0000000c, 0x00221a26, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x06e00000, 0x292 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00691ce2, 0x12f }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x29d }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000001c, 0x00403627, 0x000 }, - { 0x0000000c, 0xc0220a20, 0x000 }, - { 0x00000029, 0x00203622, 0x000 }, - { 0x00000028, 0xc0403620, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000009, 0x00204811, 0x000 }, - { 0xa1000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce3, 0x000 }, - { 0x00000021, 0x00203627, 0x000 }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce4, 0x000 }, - { 0x00000022, 0x00203627, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a3, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203624, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000000, 0x00311cc4, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14c00000, 0x2dc }, - { 0x00000000, 0x00400000, 0x2d9 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2d9 }, - { 0x00000003, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2dc }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e1, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a1, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e2, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00600000, 0x650 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2a7 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x0000001a, 0x00201e2d, 0x000 }, - { 0x0000001b, 0x0080222d, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca1, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x003808c5, 0x000 }, - { 0x00000000, 0x00300841, 0x000 }, - { 0x00000001, 0x00220a22, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000017, 0x0020222d, 0x000 }, - { 0x00000000, 0x14c00000, 0x318 }, - { 0xffffffef, 0x00280621, 0x000 }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x0000f8e0, 0x00204411, 0x000 }, - { 0x00000000, 0x00294901, 0x000 }, - { 0x00000000, 0x00894901, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00804811, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x97000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00002257, 0x00204411, 0x000 }, - { 0x00000003, 0xc0484a20, 0x000 }, - { 0x0000225d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x638 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x00000001, 0x40304a20, 0x000 }, - { 0x00000002, 0xc0304a20, 0x000 }, - { 0x00000001, 0x00530a22, 0x34b }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x67c }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x354 }, - { 0x00000014, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x362 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00604802, 0x36a }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x366 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35d }, - { 0x00000028, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5b3 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35d }, - { 0x0000002c, 0x00203626, 0x000 }, - { 0x00000049, 0x00201811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0cc00000, 0x36c }, - { 0x0000002c, 0x00801a2d, 0x000 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x00000015, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x382 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3ad }, - { 0x00000016, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3af }, - { 0x00000020, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x398 }, - { 0x0000000f, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a4 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a4 }, - { 0x0000001e, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x38c }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x08000000, 0x00290a22, 0x000 }, - { 0x00000003, 0x40210e20, 0x000 }, - { 0x0000000c, 0xc0211220, 0x000 }, - { 0x00080000, 0x00281224, 0x000 }, - { 0x00000014, 0xc0221620, 0x000 }, - { 0x00000000, 0x002914a4, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x002948a2, 0x000 }, - { 0x0000a1fe, 0x00204411, 0x000 }, - { 0x00000000, 0x00404803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x67c }, - { 0x00000015, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x38e }, - { 0x0000210e, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000017, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x67c }, - { 0x00000003, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x39a }, - { 0x00002108, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x80000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000010, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3aa }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000006, 0x00404811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36a }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x0000001d, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x3c4 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x67c }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x3b8 }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0xbabecafe, 0x00204811, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000004, 0x00404811, 0x000 }, - { 0x00002170, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000a, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3c9 }, - { 0x8c000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00003fff, 0x40280a20, 0x000 }, - { 0x80000000, 0x40280e20, 0x000 }, - { 0x40000000, 0xc0281220, 0x000 }, - { 0x00040000, 0x00694622, 0x67c }, - { 0x00000000, 0x00201410, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3d7 }, - { 0x00000000, 0xc0401800, 0x3da }, - { 0x00003fff, 0xc0281a20, 0x000 }, - { 0x00040000, 0x00694626, 0x67c }, - { 0x00000000, 0x00201810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3dd }, - { 0x00000000, 0xc0401c00, 0x3e0 }, - { 0x00003fff, 0xc0281e20, 0x000 }, - { 0x00040000, 0x00694627, 0x67c }, - { 0x00000000, 0x00201c10, 0x000 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0x002820c5, 0x000 }, - { 0x00000000, 0x004948e8, 0x000 }, - { 0xa5800000, 0x00200811, 0x000 }, - { 0x00002000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x408 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x0000001f, 0xc0210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x3ed }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000ffff, 0xc0481220, 0x3f5 }, - { 0xa7800000, 0x00200811, 0x000 }, - { 0x0000a000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x408 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00304883, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x83000000, 0x00604411, 0x408 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xa9800000, 0x00200811, 0x000 }, - { 0x0000c000, 0x00400c11, 0x3f0 }, - { 0xab800000, 0x00200811, 0x000 }, - { 0x0000f8e0, 0x00400c11, 0x3f0 }, - { 0xad800000, 0x00200811, 0x000 }, - { 0x0000f880, 0x00400c11, 0x3f0 }, - { 0xb3800000, 0x00200811, 0x000 }, - { 0x0000f3fc, 0x00400c11, 0x3f0 }, - { 0xaf800000, 0x00200811, 0x000 }, - { 0x0000e000, 0x00400c11, 0x3f0 }, - { 0xb1800000, 0x00200811, 0x000 }, - { 0x0000f000, 0x00400c11, 0x3f0 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00002148, 0x00204811, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x01182000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0218a000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0318c000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0418f8e0, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0518f880, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0618e000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0718f000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0818f3fc, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000030, 0x00200a2d, 0x000 }, - { 0x00000000, 0xc0290c40, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x86000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x85000000, 0xc0204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x67c }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00404c02, 0x43e }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x00000000, 0xc0201400, 0x000 }, - { 0x00000000, 0xc0201800, 0x000 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x44c }, - { 0x00000000, 0xc0202000, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x00000010, 0x00280a23, 0x000 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x454 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x67c }, - { 0x00000000, 0x00400000, 0x459 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00604805, 0x681 }, - { 0x00000000, 0x002824f0, 0x000 }, - { 0x00000007, 0x00280a23, 0x000 }, - { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x460 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x04e00000, 0x479 }, - { 0x00000000, 0x00400000, 0x486 }, - { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x465 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x02e00000, 0x479 }, - { 0x00000000, 0x00400000, 0x486 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46a }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ce00000, 0x479 }, - { 0x00000000, 0x00400000, 0x486 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46f }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ae00000, 0x479 }, - { 0x00000000, 0x00400000, 0x486 }, - { 0x00000005, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x474 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x06e00000, 0x479 }, - { 0x00000000, 0x00400000, 0x486 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x479 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x08e00000, 0x479 }, - { 0x00000000, 0x00400000, 0x486 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x000 }, - { 0x00000008, 0x00210a23, 0x000 }, - { 0x00000000, 0x14c00000, 0x483 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x48c }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x00404c08, 0x44c }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000011, 0x40211220, 0x000 }, - { 0x00000012, 0x40211620, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00210225, 0x000 }, - { 0x00000000, 0x14e00000, 0x496 }, - { 0x00040000, 0xc0494a20, 0x497 }, - { 0xfffbffff, 0xc0284a20, 0x000 }, - { 0x00000000, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x4a3 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000c, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x49f }, - { 0xa0000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000004, 0x00204811, 0x000 }, - { 0x0000216b, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000216c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00400000, 0x49d }, - { 0x00000000, 0xc0210a20, 0x000 }, - { 0x00000000, 0x14c00000, 0x4b6 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x681 }, - { 0x00000000, 0x00400000, 0x4ba }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0xc0294620, 0x000 }, - { 0x00000000, 0xc0600000, 0x67c }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x4c1 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0404810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x67c }, - { 0x00000000, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x4c3 }, - { 0x00002180, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000003, 0x00333e2f, 0x000 }, - { 0x00000001, 0x00210221, 0x000 }, - { 0x00000000, 0x14e00000, 0x4f3 }, - { 0x0000002c, 0x00200a2d, 0x000 }, - { 0x00040000, 0x18e00c11, 0x4e2 }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xd8c04800, 0x4d6 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000002d, 0x0020122d, 0x000 }, - { 0x00000000, 0x00290c83, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000011, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00400000, 0x49d }, - { 0x0000002c, 0xc0203620, 0x000 }, - { 0x0000002d, 0xc0403620, 0x000 }, - { 0x0000000f, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x4f8 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0xd9000000, 0x000 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xb5000000, 0x00204411, 0x000 }, - { 0x00002000, 0x00204811, 0x000 }, - { 0xb6000000, 0x00204411, 0x000 }, - { 0x0000a000, 0x00204811, 0x000 }, - { 0xb7000000, 0x00204411, 0x000 }, - { 0x0000c000, 0x00204811, 0x000 }, - { 0xb8000000, 0x00204411, 0x000 }, - { 0x0000f8e0, 0x00204811, 0x000 }, - { 0xb9000000, 0x00204411, 0x000 }, - { 0x0000f880, 0x00204811, 0x000 }, - { 0xba000000, 0x00204411, 0x000 }, - { 0x0000e000, 0x00204811, 0x000 }, - { 0xbb000000, 0x00204411, 0x000 }, - { 0x0000f000, 0x00204811, 0x000 }, - { 0xbc000000, 0x00204411, 0x000 }, - { 0x0000f3fc, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000002, 0x00204811, 0x000 }, - { 0x000000ff, 0x00280e30, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x50c }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x14c00000, 0x521 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000001c, 0x00203623, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000029, 0x00203623, 0x000 }, - { 0x00000028, 0x00203623, 0x000 }, - { 0x00000017, 0x00203623, 0x000 }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203623, 0x000 }, - { 0x00000015, 0x00203623, 0x000 }, - { 0x00000016, 0x00203623, 0x000 }, - { 0xffffe000, 0x00200c11, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203623, 0x000 }, - { 0x00001fff, 0x00200c11, 0x000 }, - { 0x00000023, 0x00203623, 0x000 }, - { 0x00000024, 0x00203623, 0x000 }, - { 0xf1ffffff, 0x00283a2e, 0x000 }, - { 0x0000001a, 0xc0220e20, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000002a, 0x40203620, 0x000 }, - { 0x87000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x9d000000, 0x00204411, 0x000 }, - { 0x0000001f, 0x40214a20, 0x000 }, - { 0x96000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x0000001f, 0x00211624, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x0000001d, 0x00203623, 0x000 }, - { 0x00000003, 0x00281e23, 0x000 }, - { 0x00000008, 0x00222223, 0x000 }, - { 0xfffff000, 0x00282228, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x0000001f, 0x00203628, 0x000 }, - { 0x00000018, 0x00211e23, 0x000 }, - { 0x00000020, 0x00203627, 0x000 }, - { 0x00000002, 0x00221624, 0x000 }, - { 0x00000000, 0x003014a8, 0x000 }, - { 0x0000001e, 0x00203625, 0x000 }, - { 0x00000003, 0x00211a24, 0x000 }, - { 0x10000000, 0x00281a26, 0x000 }, - { 0xefffffff, 0x00283a2e, 0x000 }, - { 0x00000000, 0x004938ce, 0x66a }, - { 0x00000001, 0x40280a20, 0x000 }, - { 0x00000006, 0x40280e20, 0x000 }, - { 0x00000300, 0xc0281220, 0x000 }, - { 0x00000008, 0x00211224, 0x000 }, - { 0x00000000, 0xc0201620, 0x000 }, - { 0x00000000, 0xc0201a20, 0x000 }, - { 0x00000000, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x559 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x67c }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00020000, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x561 }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x56f }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x561 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x67c }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x56f }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x565 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x56f }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56d }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x681 }, - { 0x00000000, 0x00401c10, 0x56f }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x571 }, - { 0x00000000, 0x00600000, 0x5bc }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x582 }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x67c }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x580 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x593 }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x67c }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x591 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5a4 }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x67c }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5a2 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x67c }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5b1 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5b7 }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5bc }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000002c, 0x00203621, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0230, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5c3 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000030, 0x00403621, 0x5d6 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5d6 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a092, 0x00604411, 0x67c }, - { 0x00000031, 0x00203630, 0x000 }, - { 0x0004a093, 0x00604411, 0x67c }, - { 0x00000032, 0x00203630, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x67c }, - { 0x00000033, 0x00203630, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x67c }, - { 0x00000034, 0x00203630, 0x000 }, - { 0x0004a2be, 0x00604411, 0x67c }, - { 0x00000035, 0x00203630, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x67c }, - { 0x00000036, 0x00203630, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000001, 0x002f0230, 0x000 }, - { 0x00000000, 0x0ce00000, 0x61f }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x61f }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5f8 }, - { 0x0000a092, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x0000a093, 0x00204411, 0x000 }, - { 0x00000032, 0x00204a2d, 0x000 }, - { 0x0000a2b6, 0x00204411, 0x000 }, - { 0x00000033, 0x00204a2d, 0x000 }, - { 0x0000a2ba, 0x00204411, 0x000 }, - { 0x00000034, 0x00204a2d, 0x000 }, - { 0x0000a2be, 0x00204411, 0x000 }, - { 0x00000035, 0x00204a2d, 0x000 }, - { 0x0000a2c2, 0x00204411, 0x000 }, - { 0x00000036, 0x00204a2d, 0x000 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x000001ff, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x61e }, - { 0x00000000, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x601 }, - { 0x0004a003, 0x00604411, 0x67c }, - { 0x0000a003, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x14c00000, 0x606 }, - { 0x0004a010, 0x00604411, 0x67c }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x61e }, - { 0x0004a011, 0x00604411, 0x67c }, - { 0x0000a011, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a012, 0x00604411, 0x67c }, - { 0x0000a012, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a013, 0x00604411, 0x67c }, - { 0x0000a013, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a014, 0x00604411, 0x67c }, - { 0x0000a014, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a015, 0x00604411, 0x67c }, - { 0x0000a015, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a016, 0x00604411, 0x67c }, - { 0x0000a016, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a017, 0x00604411, 0x67c }, - { 0x0000a017, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0000002c, 0x0080062d, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x630 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000002, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x634 }, - { 0x00000000, 0x00600000, 0x5bc }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x634 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x620 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x620 }, - { 0x00000000, 0x00600000, 0x64d }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36a }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x67c }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x647 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36a }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x67c }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x67b }, - { 0x00000010, 0x00404c11, 0x661 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x67a }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x67c }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x67f }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x681 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x684 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x014204f5, 0x05b30250, 0x000 }, - { 0x01c30168, 0x043505b3, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03cd05b3, 0x05b305b3, 0x000 }, - { 0x063c063d, 0x031f05b3, 0x000 }, - { 0x05b305b8, 0x03200340, 0x000 }, - { 0x032a0282, 0x03420334, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x05b30544, 0x05b305b3, 0x000 }, - { 0x03b205b3, 0x04ae0344, 0x000 }, - { 0x048d0443, 0x043305b3, 0x000 }, - { 0x04c305b3, 0x043704d0, 0x000 }, - { 0x044304fa, 0x03510371, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x05b305b3, 0x063205ba, 0x000 }, - { 0x05b305b3, 0x000705b3, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x03ee03e3, 0x03fe03fc, 0x000 }, - { 0x04040400, 0x04020406, 0x000 }, - { 0x0412040e, 0x041a0416, 0x000 }, - { 0x0422041e, 0x042a0426, 0x000 }, - { 0x05b305b3, 0x042e05b3, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x00020668, 0x06860006, 0x000 }, -}; - -static const u32 RV670_pfp_microcode[] = { -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001b8, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800053, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b8, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x800079, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008d, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401bb, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401bb, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b8, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001b8, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f0, -0xcc1003, -0x98801b, -0x04380c, -0x8400f0, -0xcc1003, -0x988017, -0x043808, -0x8400f0, -0xcc1003, -0x988013, -0x043804, -0x8400f0, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000c9, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001b8, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001b8, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b8, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800101, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d9, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bd, -0x000000, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902b0, -0x7c738b, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984297, -0x000000, -0x800161, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001b8, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010171, -0x020178, -0x03008f, -0x04007f, -0x050003, -0x06003f, -0x070032, -0x08012c, -0x090046, -0x0a0036, -0x1001b6, -0x1700a2, -0x22013a, -0x230149, -0x2000b4, -0x240125, -0x27004d, -0x28006a, -0x2a0060, -0x2b0052, -0x2f0065, -0x320087, -0x34017f, -0x3c0156, -0x3f0072, -0x41018c, -0x44012e, -0x550173, -0x56017a, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; - -static const u32 RS780_cp_microcode[][3] = { - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x622 }, - { 0x00000000, 0x00600000, 0x5d1 }, - { 0x00000000, 0x00600000, 0x5de }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x5ff }, - { 0x00000000, 0x00600000, 0x5f3 }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 0x00400c11, 0x0d6 }, - { 0x00001f00, 0x00400c11, 0x0d6 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0dc }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00280e22, 0x000 }, - { 0x00000080, 0x00294a23, 0x000 }, - { 0x00000027, 0x00200e2d, 0x000 }, - { 0x00000026, 0x0020122d, 0x000 }, - { 0x00000000, 0x002f0083, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0ea }, - { 0x00000000, 0x00600000, 0x5f9 }, - { 0x00000000, 0x00400000, 0x0eb }, - { 0x00000000, 0x00600000, 0x5fc }, - { 0x00000007, 0x0020222d, 0x000 }, - { 0x00000005, 0x00220e22, 0x000 }, - { 0x00100000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x000000ef, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000003, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x0f8 }, - { 0x0000000b, 0x00210228, 0x000 }, - { 0x00000000, 0x14c00000, 0x0f8 }, - { 0x00000400, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000001c, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x0fd }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000001e, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x10b }, - { 0x0000a30f, 0x00204411, 0x000 }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x104 }, - { 0xffffffff, 0x00404811, 0x10b }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x107 }, - { 0x0000ffff, 0x00404811, 0x10b }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x10a }, - { 0x000000ff, 0x00404811, 0x10b }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0002c400, 0x00204411, 0x000 }, - { 0x0000001f, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x112 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000018, 0x40224a20, 0x000 }, - { 0x00000010, 0xc0424a20, 0x114 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000000a, 0x00201011, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x11b }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00531224, 0x117 }, - { 0xffbfffff, 0x00283a2e, 0x000 }, - { 0x0000001b, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x12e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0x00000018, 0x00220e30, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e00e, 0x00204411, 0x000 }, - { 0x07f8ff08, 0x00204811, 0x000 }, - { 0x00000000, 0x00294a23, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00800000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204806, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x622 }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x621 }, - { 0x00000004, 0x00404c11, 0x135 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000001c, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x622 }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x13c }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40280620, 0x000 }, - { 0x00000010, 0xc0210a20, 0x000 }, - { 0x00000000, 0x00341461, 0x000 }, - { 0x00000000, 0x00741882, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x147 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0681a20, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x158 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000001, 0x00300a2f, 0x000 }, - { 0x00000001, 0x00210a22, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600000, 0x18f }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00202c08, 0x000 }, - { 0x00000000, 0x00202411, 0x000 }, - { 0x00000000, 0x00202811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000002, 0x00221e29, 0x000 }, - { 0x00000000, 0x007048eb, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000001, 0x40330620, 0x000 }, - { 0x00000000, 0xc0302409, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ae00000, 0x181 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x186 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x186 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000001, 0x00530621, 0x182 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0604800, 0x197 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000011, 0x0020062d, 0x000 }, - { 0x00000000, 0x0078042a, 0x2fb }, - { 0x00000000, 0x00202809, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x174 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x194 }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x46000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x19b }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00804811, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40281620, 0x000 }, - { 0x00000010, 0xc0811a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000008, 0x00221e30, 0x000 }, - { 0x00000029, 0x00201a2d, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfffbff09, 0x00204811, 0x000 }, - { 0x0000000f, 0x0020222d, 0x000 }, - { 0x00001fff, 0x00294a28, 0x000 }, - { 0x00000006, 0x0020222d, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000100, 0x00201811, 0x000 }, - { 0x00000008, 0x00621e28, 0x12f }, - { 0x00000008, 0x00822228, 0x000 }, - { 0x0002c000, 0x00204411, 0x000 }, - { 0x00000015, 0x00600e2d, 0x1bd }, - { 0x00000016, 0x00600e2d, 0x1bd }, - { 0x0000c008, 0x00204411, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000000, 0x14c00000, 0x1b9 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x39000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00804802, 0x000 }, - { 0x00000018, 0x00202e2d, 0x000 }, - { 0x00000000, 0x003b0d63, 0x000 }, - { 0x00000008, 0x00224a23, 0x000 }, - { 0x00000010, 0x00224a23, 0x000 }, - { 0x00000018, 0x00224a23, 0x000 }, - { 0x00000000, 0x00804803, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000007, 0x0021062f, 0x000 }, - { 0x00000013, 0x00200a2d, 0x000 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000ffff, 0x40282220, 0x000 }, - { 0x0000000f, 0x00262228, 0x000 }, - { 0x00000010, 0x40212620, 0x000 }, - { 0x0000000f, 0x00262629, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1e0 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000081, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000080, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1dc }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1d8 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000001f, 0x00280a22, 0x000 }, - { 0x0000001f, 0x00282a2a, 0x000 }, - { 0x00000001, 0x00530621, 0x1d1 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000002, 0x00304a2f, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000001, 0x00301e2f, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1e5 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x0000000f, 0x00260e23, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000000f, 0x00261224, 0x000 }, - { 0x00000000, 0x00201411, 0x000 }, - { 0x00000000, 0x00601811, 0x2bb }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022b, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1f8 }, - { 0x00000010, 0x00221628, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a29, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x0020480a, 0x000 }, - { 0x00000000, 0x00202c11, 0x000 }, - { 0x00000010, 0x00221623, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a24, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x00731503, 0x205 }, - { 0x00000000, 0x00201805, 0x000 }, - { 0x00000000, 0x00731524, 0x205 }, - { 0x00000000, 0x002d14c5, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00000000, 0x00202003, 0x000 }, - { 0x00000000, 0x00802404, 0x000 }, - { 0x0000000f, 0x00210225, 0x000 }, - { 0x00000000, 0x14c00000, 0x621 }, - { 0x00000000, 0x002b1405, 0x000 }, - { 0x00000001, 0x00901625, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00294a22, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a21, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000ffff, 0x40281220, 0x000 }, - { 0x00000010, 0xc0211a20, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211620, 0x000 }, - { 0x00000000, 0x00741465, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00000001, 0x00330621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0cc00000, 0x219 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x212 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x5de }, - { 0x00000000, 0x0040040f, 0x213 }, - { 0x00000000, 0x00600000, 0x5d1 }, - { 0x00000000, 0x00600000, 0x5de }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00000000, 0x00600000, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ae00000, 0x232 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x236 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x236 }, - { 0x00000000, 0xc0404800, 0x233 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x00600411, 0x2fb }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x5d1 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000018, 0x40210a20, 0x000 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x24c }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x00080101, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x251 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000010, 0x00600411, 0x315 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00000000, 0x00600000, 0x27c }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000001, 0x00211e27, 0x000 }, - { 0x00000000, 0x14e00000, 0x26a }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x0000ffff, 0x00281e27, 0x000 }, - { 0x00000000, 0x00341c27, 0x000 }, - { 0x00000000, 0x12c00000, 0x25f }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e5, 0x000 }, - { 0x00000000, 0x08c00000, 0x262 }, - { 0x00000000, 0x00201407, 0x000 }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00211e27, 0x000 }, - { 0x00000000, 0x00341c47, 0x000 }, - { 0x00000000, 0x12c00000, 0x267 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x08c00000, 0x26a }, - { 0x00000000, 0x00201807, 0x000 }, - { 0x00000000, 0x00600000, 0x2c1 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000000, 0x00342023, 0x000 }, - { 0x00000000, 0x12c00000, 0x272 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x271 }, - { 0x00000016, 0x00404811, 0x276 }, - { 0x00000018, 0x00404811, 0x276 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x275 }, - { 0x00000017, 0x00404811, 0x276 }, - { 0x00000019, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00604411, 0x2e9 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x256 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000010, 0x40210620, 0x000 }, - { 0x0000ffff, 0xc0280a20, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0881a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x622 }, - { 0x00000000, 0x00600000, 0x5d1 }, - { 0x00000000, 0xc0600000, 0x2a3 }, - { 0x00000005, 0x00200a2d, 0x000 }, - { 0x00000008, 0x00220a22, 0x000 }, - { 0x0000002b, 0x00201a2d, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00007000, 0x00281e27, 0x000 }, - { 0x00000000, 0x00311ce6, 0x000 }, - { 0x0000002a, 0x00201a2d, 0x000 }, - { 0x0000000c, 0x00221a26, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x06e00000, 0x292 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00691ce2, 0x12f }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x29d }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000001c, 0x00403627, 0x000 }, - { 0x0000000c, 0xc0220a20, 0x000 }, - { 0x00000029, 0x00203622, 0x000 }, - { 0x00000028, 0xc0403620, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000009, 0x00204811, 0x000 }, - { 0xa1000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce3, 0x000 }, - { 0x00000021, 0x00203627, 0x000 }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce4, 0x000 }, - { 0x00000022, 0x00203627, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a3, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203624, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000000, 0x00311cc4, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14c00000, 0x2dc }, - { 0x00000000, 0x00400000, 0x2d9 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2d9 }, - { 0x00000003, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2dc }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e1, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a1, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e2, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000000, 0x00600000, 0x5ff }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00600000, 0x5f6 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2a7 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x0000001a, 0x00201e2d, 0x000 }, - { 0x0000001b, 0x0080222d, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca1, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x003808c5, 0x000 }, - { 0x00000000, 0x00300841, 0x000 }, - { 0x00000001, 0x00220a22, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000017, 0x0020222d, 0x000 }, - { 0x00000000, 0x14c00000, 0x318 }, - { 0xffffffef, 0x00280621, 0x000 }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x0000f8e0, 0x00204411, 0x000 }, - { 0x00000000, 0x00294901, 0x000 }, - { 0x00000000, 0x00894901, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00804811, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x97000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0204811, 0x000 }, - { 0x8a000000, 0xc0204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00002257, 0x00204411, 0x000 }, - { 0x00000003, 0xc0484a20, 0x000 }, - { 0x0000225d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x5de }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x00000001, 0x40304a20, 0x000 }, - { 0x00000002, 0xc0304a20, 0x000 }, - { 0x00000001, 0x00530a22, 0x355 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x622 }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x35e }, - { 0x00000014, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x36c }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00604802, 0x374 }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x370 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x367 }, - { 0x00000028, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5ba }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x367 }, - { 0x0000002c, 0x00203626, 0x000 }, - { 0x00000049, 0x00201811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0cc00000, 0x376 }, - { 0x0000002c, 0x00801a2d, 0x000 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x00000015, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x38c }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b7 }, - { 0x00000016, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b9 }, - { 0x00000020, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a2 }, - { 0x0000000f, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3ae }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3ae }, - { 0x0000001e, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x396 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x08000000, 0x00290a22, 0x000 }, - { 0x00000003, 0x40210e20, 0x000 }, - { 0x0000000c, 0xc0211220, 0x000 }, - { 0x00080000, 0x00281224, 0x000 }, - { 0x00000014, 0xc0221620, 0x000 }, - { 0x00000000, 0x002914a4, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x002948a2, 0x000 }, - { 0x0000a1fe, 0x00204411, 0x000 }, - { 0x00000000, 0x00404803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x622 }, - { 0x00000015, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x398 }, - { 0x0000210e, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000017, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x622 }, - { 0x00000003, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x3a4 }, - { 0x00002108, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x80000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000010, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3b4 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000006, 0x00404811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x374 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x0000001d, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x3ce }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x622 }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x3c2 }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0xbabecafe, 0x00204811, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000004, 0x00404811, 0x000 }, - { 0x00002170, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000a, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3d3 }, - { 0x8c000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00003fff, 0x40280a20, 0x000 }, - { 0x80000000, 0x40280e20, 0x000 }, - { 0x40000000, 0xc0281220, 0x000 }, - { 0x00040000, 0x00694622, 0x622 }, - { 0x00000000, 0x00201410, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e1 }, - { 0x00000000, 0xc0401800, 0x3e4 }, - { 0x00003fff, 0xc0281a20, 0x000 }, - { 0x00040000, 0x00694626, 0x622 }, - { 0x00000000, 0x00201810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e7 }, - { 0x00000000, 0xc0401c00, 0x3ea }, - { 0x00003fff, 0xc0281e20, 0x000 }, - { 0x00040000, 0x00694627, 0x622 }, - { 0x00000000, 0x00201c10, 0x000 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0x002820c5, 0x000 }, - { 0x00000000, 0x004948e8, 0x000 }, - { 0xa5800000, 0x00200811, 0x000 }, - { 0x00002000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x0000001f, 0xc0210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x3f7 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000ffff, 0xc0481220, 0x3ff }, - { 0xa7800000, 0x00200811, 0x000 }, - { 0x0000a000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00304883, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xa9800000, 0x00200811, 0x000 }, - { 0x0000c000, 0x00400c11, 0x3fa }, - { 0xab800000, 0x00200811, 0x000 }, - { 0x0000f8e0, 0x00400c11, 0x3fa }, - { 0xad800000, 0x00200811, 0x000 }, - { 0x0000f880, 0x00400c11, 0x3fa }, - { 0xb3800000, 0x00200811, 0x000 }, - { 0x0000f3fc, 0x00400c11, 0x3fa }, - { 0xaf800000, 0x00200811, 0x000 }, - { 0x0000e000, 0x00400c11, 0x3fa }, - { 0xb1800000, 0x00200811, 0x000 }, - { 0x0000f000, 0x00400c11, 0x3fa }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00002148, 0x00204811, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x01182000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0218a000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0318c000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0418f8e0, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0518f880, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0618e000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0718f000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0818f3fc, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000033, 0xc0300a20, 0x000 }, - { 0x00000000, 0xc0403440, 0x000 }, - { 0x00000030, 0x00200a2d, 0x000 }, - { 0x00000000, 0xc0290c40, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x86000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x85000000, 0xc0204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00000018, 0x40210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x447 }, - { 0x00800000, 0xc0494a20, 0x448 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x06e00000, 0x450 }, - { 0x00000004, 0x00200811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x622 }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00404c02, 0x450 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x00000000, 0xc0201400, 0x000 }, - { 0x00000000, 0xc0201800, 0x000 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x461 }, - { 0x00000000, 0xc0202000, 0x000 }, - { 0x00000004, 0x002f0228, 0x000 }, - { 0x00000000, 0x06e00000, 0x461 }, - { 0x00000004, 0x00202011, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x00000010, 0x00280a23, 0x000 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x469 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x622 }, - { 0x00000000, 0x00400000, 0x46e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00604805, 0x627 }, - { 0x00000000, 0x002824f0, 0x000 }, - { 0x00000007, 0x00280a23, 0x000 }, - { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x475 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x04e00000, 0x48e }, - { 0x00000000, 0x00400000, 0x49b }, - { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x47a }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x02e00000, 0x48e }, - { 0x00000000, 0x00400000, 0x49b }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x47f }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ce00000, 0x48e }, - { 0x00000000, 0x00400000, 0x49b }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x484 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ae00000, 0x48e }, - { 0x00000000, 0x00400000, 0x49b }, - { 0x00000005, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x489 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x06e00000, 0x48e }, - { 0x00000000, 0x00400000, 0x49b }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x48e }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x08e00000, 0x48e }, - { 0x00000000, 0x00400000, 0x49b }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x000 }, - { 0x00000008, 0x00210a23, 0x000 }, - { 0x00000000, 0x14c00000, 0x498 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x4a1 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x00404c08, 0x461 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000011, 0x40211220, 0x000 }, - { 0x00000012, 0x40211620, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00210225, 0x000 }, - { 0x00000000, 0x14e00000, 0x4ab }, - { 0x00040000, 0xc0494a20, 0x4ac }, - { 0xfffbffff, 0xc0284a20, 0x000 }, - { 0x00000000, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x4b8 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000c, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x4b4 }, - { 0xa0000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000004, 0x00204811, 0x000 }, - { 0x0000216b, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000216c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4b2 }, - { 0x00000000, 0xc0210a20, 0x000 }, - { 0x00000000, 0x14c00000, 0x4cb }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x627 }, - { 0x00000000, 0x00400000, 0x4cf }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0xc0294620, 0x000 }, - { 0x00000000, 0xc0600000, 0x622 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x4d6 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0404810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x622 }, - { 0x00000000, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x4d8 }, - { 0x00002180, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000003, 0x00333e2f, 0x000 }, - { 0x00000001, 0x00210221, 0x000 }, - { 0x00000000, 0x14e00000, 0x508 }, - { 0x0000002c, 0x00200a2d, 0x000 }, - { 0x00040000, 0x18e00c11, 0x4f7 }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xd8c04800, 0x4eb }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000002d, 0x0020122d, 0x000 }, - { 0x00000000, 0x00290c83, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000011, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4b2 }, - { 0x0000002c, 0xc0203620, 0x000 }, - { 0x0000002d, 0xc0403620, 0x000 }, - { 0x0000000f, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x50d }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0xd9000000, 0x000 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xb5000000, 0x00204411, 0x000 }, - { 0x00002000, 0x00204811, 0x000 }, - { 0xb6000000, 0x00204411, 0x000 }, - { 0x0000a000, 0x00204811, 0x000 }, - { 0xb7000000, 0x00204411, 0x000 }, - { 0x0000c000, 0x00204811, 0x000 }, - { 0xb8000000, 0x00204411, 0x000 }, - { 0x0000f8e0, 0x00204811, 0x000 }, - { 0xb9000000, 0x00204411, 0x000 }, - { 0x0000f880, 0x00204811, 0x000 }, - { 0xba000000, 0x00204411, 0x000 }, - { 0x0000e000, 0x00204811, 0x000 }, - { 0xbb000000, 0x00204411, 0x000 }, - { 0x0000f000, 0x00204811, 0x000 }, - { 0xbc000000, 0x00204411, 0x000 }, - { 0x0000f3fc, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000002, 0x00204811, 0x000 }, - { 0x000000ff, 0x00280e30, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x521 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x14c00000, 0x536 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000001c, 0x00203623, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000029, 0x00203623, 0x000 }, - { 0x00000028, 0x00203623, 0x000 }, - { 0x00000017, 0x00203623, 0x000 }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203623, 0x000 }, - { 0x00000015, 0x00203623, 0x000 }, - { 0x00000016, 0x00203623, 0x000 }, - { 0xffffe000, 0x00200c11, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203623, 0x000 }, - { 0x00001fff, 0x00200c11, 0x000 }, - { 0x00000023, 0x00203623, 0x000 }, - { 0x00000024, 0x00203623, 0x000 }, - { 0xf1ffffff, 0x00283a2e, 0x000 }, - { 0x0000001a, 0xc0220e20, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000002a, 0x40203620, 0x000 }, - { 0x87000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x9d000000, 0x00204411, 0x000 }, - { 0x0000001f, 0x40214a20, 0x000 }, - { 0x96000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x0000001f, 0x00211624, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x0000001d, 0x00203623, 0x000 }, - { 0x00000003, 0x00281e23, 0x000 }, - { 0x00000008, 0x00222223, 0x000 }, - { 0xfffff000, 0x00282228, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x0000001f, 0x00203628, 0x000 }, - { 0x00000018, 0x00211e23, 0x000 }, - { 0x00000020, 0x00203627, 0x000 }, - { 0x00000002, 0x00221624, 0x000 }, - { 0x00000000, 0x003014a8, 0x000 }, - { 0x0000001e, 0x00203625, 0x000 }, - { 0x00000003, 0x00211a24, 0x000 }, - { 0x10000000, 0x00281a26, 0x000 }, - { 0xefffffff, 0x00283a2e, 0x000 }, - { 0x00000000, 0x004938ce, 0x610 }, - { 0x00000001, 0x40280a20, 0x000 }, - { 0x00000006, 0x40280e20, 0x000 }, - { 0x00000300, 0xc0281220, 0x000 }, - { 0x00000008, 0x00211224, 0x000 }, - { 0x00000000, 0xc0201620, 0x000 }, - { 0x00000000, 0xc0201a20, 0x000 }, - { 0x00000000, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x56c }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x622 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00020000, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x574 }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x582 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x574 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x622 }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x582 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x578 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x582 }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x580 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x627 }, - { 0x00000000, 0x00401c10, 0x582 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x584 }, - { 0x00000000, 0x00600000, 0x5c3 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x592 }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x00000033, 0x0020262d, 0x000 }, - { 0x0000001a, 0x00212229, 0x000 }, - { 0x00000006, 0x00222629, 0x000 }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x590 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5a0 }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x00000034, 0x0020262d, 0x000 }, - { 0x0000001a, 0x00212229, 0x000 }, - { 0x00000006, 0x00222629, 0x000 }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x59e }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5ae }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x00000035, 0x0020262d, 0x000 }, - { 0x0000001a, 0x00212229, 0x000 }, - { 0x00000006, 0x00222629, 0x000 }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5ac }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x00000036, 0x0020262d, 0x000 }, - { 0x0000001a, 0x00212229, 0x000 }, - { 0x00000006, 0x00222629, 0x000 }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5b8 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5be }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5c3 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x5d6 }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x5da }, - { 0x00000000, 0x00600000, 0x5c3 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x5da }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x5cd }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x5cd }, - { 0x00000000, 0x00600000, 0x5f3 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x374 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x622 }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x5ed }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x374 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x622 }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x621 }, - { 0x00000010, 0x00404c11, 0x607 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x620 }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x622 }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x625 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x627 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x62a }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x0142050a, 0x05ba0250, 0x000 }, - { 0x01c30168, 0x044105ba, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03d705ba, 0x05ba05ba, 0x000 }, - { 0x05e205e3, 0x031f05ba, 0x000 }, - { 0x032005bf, 0x0320034a, 0x000 }, - { 0x03340282, 0x034c033e, 0x000 }, - { 0x05ba05ba, 0x05ba05ba, 0x000 }, - { 0x05ba0557, 0x05ba032a, 0x000 }, - { 0x03bc05ba, 0x04c3034e, 0x000 }, - { 0x04a20455, 0x043f05ba, 0x000 }, - { 0x04d805ba, 0x044304e5, 0x000 }, - { 0x0455050f, 0x035b037b, 0x000 }, - { 0x05ba05ba, 0x05ba05ba, 0x000 }, - { 0x05ba05ba, 0x05ba05ba, 0x000 }, - { 0x05ba05ba, 0x05d805c1, 0x000 }, - { 0x05ba05ba, 0x000705ba, 0x000 }, - { 0x05ba05ba, 0x05ba05ba, 0x000 }, - { 0x05ba05ba, 0x05ba05ba, 0x000 }, - { 0x03f803ed, 0x04080406, 0x000 }, - { 0x040e040a, 0x040c0410, 0x000 }, - { 0x041c0418, 0x04240420, 0x000 }, - { 0x042c0428, 0x04340430, 0x000 }, - { 0x05ba05ba, 0x043a0438, 0x000 }, - { 0x05ba05ba, 0x05ba05ba, 0x000 }, - { 0x05ba05ba, 0x05ba05ba, 0x000 }, - { 0x0002060e, 0x062c0006, 0x000 }, -}; - -static const u32 RS780_pfp_microcode[] = { -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001db, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581cb, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0ffe0, -0x042c08, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255407, -0x7cd580, -0x259c07, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xca0c00, -0x8001db, -0xd48024, -0xca0800, -0x7c00c0, -0xc81425, -0xc81824, -0x7c9488, -0x7c9880, -0xc20003, -0xd40075, -0x7c744c, -0x800064, -0xd4401e, -0xca1800, -0xd4401e, -0xd5801e, -0x800062, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c01, -0xd48060, -0x94c003, -0x041001, -0x041002, -0xd50025, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001db, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x80009c, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x8000b0, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401de, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401de, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001db, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001db, -0xd4001a, -0xd4c01a, -0x282801, -0x840113, -0xcc1003, -0x98801b, -0x04380c, -0x840113, -0xcc1003, -0x988017, -0x043808, -0x840113, -0xcc1003, -0x988013, -0x043804, -0x840113, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000ec, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001db, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001db, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001db, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800124, -0xd5001a, -0xcc0832, -0xd40032, -0x9482b6, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x98829a, -0x000000, -0x8401de, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x99028d, -0x7c738b, -0x8401de, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984274, -0x000000, -0x800184, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001db, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010194, -0x02019b, -0x0300b2, -0x0400a2, -0x050003, -0x06003f, -0x070032, -0x08014f, -0x090046, -0x0a0036, -0x1001d9, -0x1700c5, -0x22015d, -0x23016c, -0x2000d7, -0x240148, -0x26004d, -0x27005c, -0x28008d, -0x290051, -0x2a007e, -0x2b0061, -0x2f0088, -0x3200aa, -0x3401a2, -0x36006f, -0x3c0179, -0x3f0095, -0x4101af, -0x440151, -0x550196, -0x56019d, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x7301d9, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; - -static const u32 RV770_cp_microcode[] = { -0xcc0003ea, -0x7c408000, -0xa0000000, -0xcc800062, -0x80000001, -0xd040007f, -0x80000001, -0xcc400041, -0x7c40c000, -0xc0160004, -0x30d03fff, -0x7d15000c, -0xcc110000, -0x28d8001e, -0x31980001, -0x28dc001f, -0xc8200004, -0x95c00006, -0x7c424000, -0xcc000062, -0x7e56800c, -0xcc290000, -0xc8240004, -0x7e26000b, -0x95800006, -0x7c42c000, -0xcc000062, -0x7ed7000c, -0xcc310000, -0xc82c0004, -0x7e2e000c, -0xcc000062, -0x31103fff, -0x80000001, -0xce110000, -0x7c40c000, -0x80000001, -0xcc400040, -0x80000001, -0xcc412257, -0x7c418000, -0xcc400045, -0xcc400048, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xcc400045, -0xcc400048, -0x7c40c000, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xcc000045, -0xcc000048, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0x040ca1fd, -0xc0120001, -0xcc000045, -0xcc000048, -0x7cd0c00c, -0xcc41225c, -0xcc41a1fc, -0xd04d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0x80000001, -0xcc41225d, -0x7c408000, -0x7c40c000, -0xc02a0002, -0x7c410000, -0x7d29000c, -0x30940001, -0x30980006, -0x309c0300, -0x29dc0008, -0x7c420000, -0x7c424000, -0x9540000f, -0xc02e0004, -0x05f02258, -0x7f2f000c, -0xcc310000, -0xc8280004, -0xccc12169, -0xcd01216a, -0xce81216b, -0x0db40002, -0xcc01216c, -0x9740000e, -0x0db40000, -0x8000007b, -0xc834000a, -0x0db40002, -0x97400009, -0x0db40000, -0xc02e0004, -0x05f02258, -0x7f2f000c, -0xcc310000, -0xc8280004, -0x8000007b, -0xc834000a, -0x97400004, -0x7e028000, -0x8000007b, -0xc834000a, -0x0db40004, -0x9740ff8c, -0x00000000, -0xce01216d, -0xce41216e, -0xc8280003, -0xc834000a, -0x9b400004, -0x043c0005, -0x8400026d, -0xcc000062, -0x0df40000, -0x9740000b, -0xc82c03e6, -0xce81a2b7, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c4, -0x80000001, -0xcfc1a2d1, -0x0df40001, -0x9740000b, -0xc82c03e7, -0xce81a2bb, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c5, -0x80000001, -0xcfc1a2d2, -0x0df40002, -0x9740000b, -0xc82c03e8, -0xce81a2bf, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c6, -0x80000001, -0xcfc1a2d3, -0xc82c03e9, -0xce81a2c3, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c7, -0x80000001, -0xcfc1a2d4, -0x80000001, -0xcc400042, -0x7c40c000, -0x7c410000, -0x2914001d, -0x31540001, -0x9940000d, -0x31181000, -0xc81c0011, -0x09dc0001, -0x95c0ffff, -0xc81c0011, -0xccc12100, -0xcd012101, -0xccc12102, -0xcd012103, -0x04180004, -0x8000039f, -0xcd81a2a4, -0xc02a0004, -0x95800008, -0x36a821a3, -0xcc290000, -0xc8280004, -0xc81c0011, -0x0de40040, -0x9640ffff, -0xc81c0011, -0xccc12170, -0xcd012171, -0xc8200012, -0x96000000, -0xc8200012, -0x8000039f, -0xcc000064, -0x7c40c000, -0x7c410000, -0xcc000045, -0xcc000048, -0x40d40003, -0xcd41225c, -0xcd01a1fc, -0xc01a0001, -0x041ca1fd, -0x7dd9c00c, -0x7c420000, -0x08cc0001, -0x06240001, -0x06280002, -0xce1d0000, -0xce5d0000, -0x98c0fffa, -0xce9d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0x7c40c000, -0x30d00001, -0x28cc0001, -0x7c414000, -0x95000006, -0x7c418000, -0xcd41216d, -0xcd81216e, -0x800000f3, -0xc81c0003, -0xc0220004, -0x7e16000c, -0xcc210000, -0xc81c0004, -0x7c424000, -0x98c00004, -0x7c428000, -0x80000001, -0xcde50000, -0xce412169, -0xce81216a, -0xcdc1216b, -0x80000001, -0xcc01216c, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0x7c41c000, -0x28a40008, -0x326400ff, -0x0e68003c, -0x9680000a, -0x7c020000, -0x7c420000, -0x1e300003, -0xcc00006a, -0x9b000003, -0x42200005, -0x04200040, -0x80000110, -0x7c024000, -0x7e024000, -0x9a400000, -0x0a640001, -0x30ec0010, -0x9ac0000a, -0xcc000062, -0xc02a0004, -0xc82c0021, -0x7e92800c, -0xcc000041, -0xcc290000, -0xcec00021, -0x80000120, -0xc8300004, -0xcd01216d, -0xcd41216e, -0xc8300003, -0x7f1f000b, -0x30f40007, -0x27780001, -0x9740002a, -0x07b80125, -0x9f800000, -0x00000000, -0x80000135, -0x7f1b8004, -0x80000139, -0x7f1b8005, -0x8000013d, -0x7f1b8002, -0x80000141, -0x7f1b8003, -0x80000145, -0x7f1b8007, -0x80000149, -0x7f1b8006, -0x8000014e, -0x28a40008, -0x9b800019, -0x28a40008, -0x8000015e, -0x326400ff, -0x9b800015, -0x28a40008, -0x8000015e, -0x326400ff, -0x9b800011, -0x28a40008, -0x8000015e, -0x326400ff, -0x9b80000d, -0x28a40008, -0x8000015e, -0x326400ff, -0x9b800009, -0x28a40008, -0x8000015e, -0x326400ff, -0x9b800005, -0x28a40008, -0x8000015e, -0x326400ff, -0x28a40008, -0x326400ff, -0x0e68003c, -0x9a80feb1, -0x28ec0008, -0x7c434000, -0x7c438000, -0x7c43c000, -0x96c00007, -0xcc000062, -0xcf412169, -0xcf81216a, -0xcfc1216b, -0x80000001, -0xcc01216c, -0x80000001, -0xcff50000, -0xcc00006b, -0x840003a2, -0x0e68003c, -0x9a800004, -0xc8280015, -0x80000001, -0xd040007f, -0x9680ffab, -0x7e024000, -0x8400023b, -0xc00e0002, -0xcc000041, -0x80000239, -0xccc1304a, -0x7c40c000, -0x7c410000, -0xc01e0001, -0x29240012, -0xc0220002, -0x96400005, -0xc0260004, -0xc027fffb, -0x7d25000b, -0xc0260000, -0x7dd2800b, -0x7e12c00b, -0x7d25000c, -0x7c414000, -0x7c418000, -0xccc12169, -0x9a80000a, -0xcd01216a, -0xcd41216b, -0x96c0fe82, -0xcd81216c, -0xc8300018, -0x97000000, -0xc8300018, -0x80000001, -0xcc000018, -0x840003a2, -0xcc00007f, -0xc8140013, -0xc8180014, -0xcd41216b, -0x96c0fe76, -0xcd81216c, -0x80000182, -0xc8300018, -0xc80c0008, -0x98c00000, -0xc80c0008, -0x7c410000, -0x95000002, -0x00000000, -0x7c414000, -0xc8200009, -0xcc400043, -0xce01a1f4, -0xcc400044, -0xc00e8000, -0x7c424000, -0x7c428000, -0x2aac001f, -0x96c0fe63, -0xc035f000, -0xce4003e2, -0x32780003, -0x267c0008, -0x7ff7c00b, -0x7ffbc00c, -0x2a780018, -0xcfc003e3, -0xcf8003e4, -0x26b00002, -0x7f3f0000, -0xcf0003e5, -0x8000031f, -0x7c80c000, -0x7c40c000, -0x28d00008, -0x3110000f, -0x9500000f, -0x25280001, -0x06a801b3, -0x9e800000, -0x00000000, -0x800001d4, -0xc0120800, -0x800001e2, -0xc814000f, -0x800001e9, -0xc8140010, -0x800001f0, -0xccc1a2a4, -0x800001f9, -0xc8140011, -0x30d0003f, -0x0d280015, -0x9a800012, -0x0d28001e, -0x9a80001e, -0x0d280020, -0x9a800023, -0x0d24000f, -0x0d280010, -0x7e6a800c, -0x9a800026, -0x0d200004, -0x0d240014, -0x0d280028, -0x7e62400c, -0x7ea6800c, -0x9a80002a, -0xc8140011, -0x80000001, -0xccc1a2a4, -0xc0120800, -0x7c414000, -0x7d0cc00c, -0xc0120008, -0x29580003, -0x295c000c, -0x7c420000, -0x7dd1c00b, -0x26200014, -0x7e1e400c, -0x7e4e800c, -0xce81a2a4, -0x80000001, -0xcd81a1fe, -0xc814000f, -0x0410210e, -0x95400000, -0xc814000f, -0xd0510000, -0x80000001, -0xccc1a2a4, -0xc8140010, -0x04102108, -0x95400000, -0xc8140010, -0xd0510000, -0x80000001, -0xccc1a2a4, -0xccc1a2a4, -0x04100001, -0xcd000019, -0x840003a2, -0xcc00007f, -0xc8100019, -0x99000000, -0xc8100019, -0x80000002, -0x7c408000, -0x04102100, -0x09540001, -0x9540ffff, -0xc8140011, -0xd0510000, -0x8000039f, -0xccc1a2a4, -0x7c40c000, -0xcc40000d, -0x94c0fdff, -0xcc40000e, -0x7c410000, -0x95000005, -0x08cc0001, -0xc8140005, -0x99400014, -0x00000000, -0x98c0fffb, -0x7c410000, -0x80000002, -0x7d008000, -0xc8140005, -0x7c40c000, -0x9940000c, -0xc818000c, -0x7c410000, -0x9580fdee, -0xc820000e, -0xc81c000d, -0x66200020, -0x7e1e002c, -0x25240002, -0x7e624020, -0x80000001, -0xcce60000, -0x7c410000, -0xcc00006c, -0xcc00006d, -0xc818001f, -0xc81c001e, -0x65980020, -0x7dd9c02c, -0x7cd4c00c, -0xccde0000, -0x45dc0004, -0xc8280017, -0x9680000f, -0xc00e0001, -0x28680008, -0x2aac0016, -0x32a800ff, -0x0eb00049, -0x7f2f000b, -0x97000006, -0x00000000, -0xc8140005, -0x7c40c000, -0x80000223, -0x7c410000, -0x80000226, -0xd040007f, -0x8400023b, -0xcc000041, -0xccc1304a, -0x94000000, -0xc83c001a, -0x043c0005, -0xcfc1a2a4, -0xc0361f90, -0xc0387fff, -0x7c03c010, -0x7f7b400c, -0xcf41217c, -0xcfc1217d, -0xcc01217e, -0xc03a0004, -0x0434217f, -0x7f7b400c, -0xcc350000, -0xc83c0004, -0x2bfc001f, -0x04380020, -0x97c00005, -0xcc000062, -0x9b800000, -0x0bb80001, -0x80000247, -0xcc000071, -0xcc01a1f4, -0x04380016, -0xc0360002, -0xcf81a2a4, -0x88000000, -0xcf412010, -0x7c40c000, -0x28d0001c, -0x95000005, -0x04d40001, -0xcd400065, -0x80000001, -0xcd400068, -0x09540002, -0x80000001, -0xcd400066, -0x8400026c, -0xc81803ea, -0x7c40c000, -0x9980fd9d, -0xc8140016, -0x08d00001, -0x9940002b, -0xcd000068, -0x7c408000, -0xa0000000, -0xcc800062, -0x043c0005, -0xcfc1a2a4, -0xcc01a1f4, -0x840003a2, -0xcc000046, -0x88000000, -0xcc00007f, -0x8400027e, -0xc81803ea, -0x7c40c000, -0x9980fd8b, -0xc8140016, -0x08d00001, -0x99400019, -0xcd000068, -0x7c408000, -0xa0000000, -0xcc800062, -0x043c0022, -0xcfc1a2a4, -0x840003a2, -0xcc000047, -0x88000000, -0xcc00007f, -0xc8100016, -0x9900000d, -0xcc400067, -0x80000002, -0x7c408000, -0xc81803ea, -0x9980fd77, -0x7c40c000, -0x94c00003, -0xc8100016, -0x99000004, -0xccc00068, -0x80000002, -0x7c408000, -0x8400023b, -0xc0148000, -0xcc000041, -0xcd41304a, -0xc0148000, -0x99000000, -0xc8100016, -0x80000002, -0x7c408000, -0xc0120001, -0x7c51400c, -0x80000001, -0xd0550000, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0x291c001f, -0xccc0004a, -0xcd00004b, -0x95c00003, -0xc01c8000, -0xcdc12010, -0xdd830000, -0x055c2000, -0xcc000062, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc0004c, -0xcd00004d, -0xdd830000, -0x055ca000, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc0004e, -0xcd00004f, -0xdd830000, -0x055cc000, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00050, -0xcd000051, -0xdd830000, -0x055cf8e0, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00052, -0xcd000053, -0xdd830000, -0x055cf880, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00054, -0xcd000055, -0xdd830000, -0x055ce000, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00056, -0xcd000057, -0xdd830000, -0x055cf000, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00058, -0xcd000059, -0xdd830000, -0x055cf3fc, -0x80000001, -0xd81f4100, -0xd0432000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043a000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043c000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f8e0, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f880, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043e000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f3fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xc81403e0, -0xcc430000, -0xcc430000, -0xcc430000, -0x7d45c000, -0xcdc30000, -0xd0430000, -0x7c408000, -0xa0000000, -0xcc800062, -0x7c40c000, -0xc81003e2, -0xc81403e5, -0xc81803e3, -0xc81c03e4, -0xcd812169, -0xcdc1216a, -0xccc1216b, -0xcc01216c, -0x04200004, -0x7da18000, -0x7d964002, -0x9640fcd7, -0xcd8003e3, -0x31280003, -0xc02df000, -0x25180008, -0x7dad800b, -0x7da9800c, -0x80000001, -0xcd8003e3, -0x308cffff, -0xd04d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0x7c40c000, -0x7c410000, -0x29240018, -0x32640001, -0x9a400013, -0xc8140020, -0x15580002, -0x9580ffff, -0xc8140020, -0xcc00006e, -0xccc12180, -0xcd01218d, -0xcc412181, -0x2914001f, -0x34588000, -0xcd81218c, -0x9540fcb9, -0xcc412182, -0xc8140020, -0x9940ffff, -0xc8140020, -0x80000002, -0x7c408000, -0x7c414000, -0x7c418000, -0x7c41c000, -0x65b40020, -0x7f57402c, -0xd4378100, -0x47740004, -0xd4378100, -0x47740004, -0xd4378100, -0x47740004, -0x09dc0004, -0xd4378100, -0x99c0fff8, -0x47740004, -0x2924001f, -0xc0380019, -0x9640fca1, -0xc03e0004, -0xcf8121f8, -0x37e021f9, -0xcc210000, -0xc8200004, -0x2a200018, -0x32200001, -0x9a00fffb, -0xcf8121f8, -0x80000002, -0x7c408000, -0x7c40c000, -0x28d00018, -0x31100001, -0xc0160080, -0x95000003, -0xc02a0004, -0x7cd4c00c, -0xccc1217c, -0xcc41217d, -0xcc41217e, -0x7c418000, -0x1db00003, -0x36a0217f, -0x9b000003, -0x419c0005, -0x041c0040, -0x99c00000, -0x09dc0001, -0xcc210000, -0xc8240004, -0x2a6c001f, -0x419c0005, -0x9ac0fffa, -0xcc800062, -0x80000002, -0x7c408000, -0x7c40c000, -0x04d403e6, -0x80000001, -0xcc540000, -0x8000039f, -0xcc4003ea, -0xc01c8000, -0x044ca000, -0xcdc12010, -0x7c410000, -0xc8140009, -0x04180000, -0x041c0008, -0xcd800071, -0x09dc0001, -0x05980001, -0xcd0d0000, -0x99c0fffc, -0xcc800062, -0x8000039f, -0xcd400071, -0xc00e0100, -0xcc000041, -0xccc1304a, -0xc83c007f, -0xcc00007f, -0x80000001, -0xcc00007f, -0xcc00007f, -0x88000000, -0xcc00007f, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00010333, -0x00100004, -0x00170006, -0x00210008, -0x00270028, -0x00280023, -0x00290029, -0x002a0026, -0x002b0029, -0x002d0038, -0x002e003f, -0x002f004a, -0x0034004c, -0x00360030, -0x003900af, -0x003a00d0, -0x003b00e5, -0x003c00fd, -0x003d016c, -0x003f00ad, -0x00410338, -0x0043036c, -0x0044018f, -0x004500fd, -0x004601ad, -0x004701ad, -0x00480200, -0x0049020e, -0x004a0257, -0x004b0284, -0x00520261, -0x00530273, -0x00540289, -0x0057029b, -0x0060029f, -0x006102ae, -0x006202b8, -0x006302c2, -0x006402cc, -0x006502d6, -0x006602e0, -0x006702ea, -0x006802f4, -0x006902f8, -0x006a02fc, -0x006b0300, -0x006c0304, -0x006d0308, -0x006e030c, -0x006f0310, -0x00700314, -0x00720386, -0x0074038c, -0x0079038a, -0x007c031e, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -}; - -static const u32 RV770_pfp_microcode[] = { -0x7c408000, -0xa0000000, -0x7e82800b, -0x80000000, -0xdc030000, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xc818000e, -0x31980001, -0x7c424000, -0x95800252, -0x7c428000, -0xc81c001c, -0xc037c000, -0x7c40c000, -0x7c410000, -0x7cb4800b, -0xc0360003, -0x99c00000, -0xc81c001c, -0x7cb4800c, -0x24d40002, -0x7d654000, -0xcd400043, -0xce800043, -0xcd000043, -0xcc800040, -0xce400040, -0xce800040, -0xccc00040, -0xdc3a0000, -0x9780ffde, -0xcd000040, -0x7c40c000, -0x80000018, -0x7c410000, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xc818000e, -0x8000000c, -0x31980002, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xc818000e, -0x288c0008, -0x30cc000f, -0x34100001, -0x7d0d0008, -0x8000000c, -0x7d91800b, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xcc4003f9, -0x80000261, -0xcc4003f8, -0xc82003f8, -0xc81c03f9, -0xc81803fb, -0xc037ffff, -0x7c414000, -0xcf41a29e, -0x66200020, -0x7de1c02c, -0x7d58c008, -0x7cdcc020, -0x68d00020, -0xc0360003, -0xcc000054, -0x7cb4800c, -0x8000006a, -0xcc800040, -0x7c418000, -0xcd81a29e, -0xcc800040, -0xcd800040, -0x80000068, -0xcc000054, -0xc019ffff, -0xcc800040, -0xcd81a29e, -0x7c40c000, -0x7c410000, -0x7c414000, -0xccc1a1fa, -0xcd01a1f9, -0xcd41a29d, -0xccc00040, -0xcd000040, -0xcd400040, -0xcc400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xcc000054, -0xcc800040, -0x7c40c000, -0x7c410000, -0x7c414000, -0xccc1a1fa, -0xcd01a1f9, -0xcd41a29d, -0xccc00040, -0xcd000040, -0xcd400040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0x7c40c000, -0x30d00001, -0xccc1a29f, -0x95000003, -0x04140001, -0x04140002, -0xcd4003fb, -0xcc800040, -0x80000000, -0xccc00040, -0x7c40c000, -0xcc800040, -0xccc1a2a2, -0x80000000, -0xccc00040, -0x7c40c000, -0x28d4001f, -0xcc800040, -0x95400003, -0x7c410000, -0xccc00057, -0x2918001f, -0xccc00040, -0x95800003, -0xcd000040, -0xcd000058, -0x80000261, -0xcc00007f, -0xc8200017, -0xc8300022, -0x9a000006, -0x0e280001, -0xc824001e, -0x0a640001, -0xd4001240, -0xce400040, -0xc036c000, -0x96800007, -0x37747900, -0x041c0001, -0xcf400040, -0xcdc00040, -0xcf0003fa, -0x7c030000, -0xca0c0010, -0x7c410000, -0x94c00004, -0x7c414000, -0xd42002c4, -0xcde00044, -0x9b00000b, -0x7c418000, -0xcc00004b, -0xcda00049, -0xcd200041, -0xcd600041, -0xcda00041, -0x06200001, -0xce000056, -0x80000261, -0xcc00007f, -0xc8280020, -0xc82c0021, -0xcc000063, -0x7eea4001, -0x65740020, -0x7f53402c, -0x269c0002, -0x7df5c020, -0x69f80020, -0xce80004b, -0xce600049, -0xcde00041, -0xcfa00041, -0xce600041, -0x271c0002, -0x7df5c020, -0x69f80020, -0x7db24001, -0xcf00004b, -0xce600049, -0xcde00041, -0xcfa00041, -0x800000bd, -0xce600041, -0xc8200017, -0xc8300022, -0x9a000006, -0x0e280001, -0xc824001e, -0x0a640001, -0xd4001240, -0xce400040, -0xca0c0010, -0x7c410000, -0x94c0000b, -0xc036c000, -0x96800007, -0x37747900, -0x041c0001, -0xcf400040, -0xcdc00040, -0xcf0003fa, -0x7c030000, -0x800000b6, -0x7c414000, -0xcc000048, -0x800000ef, -0x00000000, -0xc8200017, -0xc81c0023, -0x0e240002, -0x99c00015, -0x7c418000, -0x0a200001, -0xce000056, -0xd4000440, -0xcc000040, -0xc036c000, -0xca140013, -0x96400007, -0x37747900, -0xcf400040, -0xcc000040, -0xc83003fa, -0x80000104, -0xcf000022, -0xcc000022, -0x9540015d, -0xcc00007f, -0xcca00046, -0x80000000, -0xcc200046, -0x80000261, -0xcc000064, -0xc8200017, -0xc810001f, -0x96000005, -0x09100001, -0xd4000440, -0xcd000040, -0xcd000022, -0xcc800040, -0xd0400040, -0xc80c0025, -0x94c0feeb, -0xc8100008, -0xcd000040, -0xd4000fc0, -0x80000000, -0xd4000fa2, -0x7c40c000, -0x7c410000, -0xccc003fd, -0xcd0003fc, -0xccc00042, -0xcd000042, -0x2914001f, -0x29180010, -0x31980007, -0x3b5c0001, -0x7d76000b, -0x99800005, -0x7d5e400b, -0xcc000042, -0x80000261, -0xcc00004d, -0x29980001, -0x292c0008, -0x9980003d, -0x32ec0001, -0x96000004, -0x2930000c, -0x80000261, -0xcc000042, -0x04140010, -0xcd400042, -0x33300001, -0x34280001, -0x8400015e, -0xc8140003, -0x9b40001b, -0x0438000c, -0x8400015e, -0xc8140003, -0x9b400017, -0x04380008, -0x8400015e, -0xc8140003, -0x9b400013, -0x04380004, -0x8400015e, -0xc8140003, -0x9b400015, -0xc80c03fd, -0x9a800009, -0xc81003fc, -0x9b000118, -0xcc00004d, -0x04140010, -0xccc00042, -0xcd000042, -0x80000136, -0xcd400042, -0x96c00111, -0xcc00004d, -0x80000261, -0xcc00004e, -0x9ac00003, -0xcc00004d, -0xcc00004e, -0xdf830000, -0x80000000, -0xd80301ff, -0x9ac00107, -0xcc00004d, -0x80000261, -0xcc00004e, -0xc8180003, -0xc81c0003, -0xc8200003, -0x7d5d4003, -0x7da1c003, -0x7d5d400c, -0x2a10001f, -0x299c001f, -0x7d1d000b, -0x7d17400b, -0x88000000, -0x7e92800b, -0x96400004, -0xcc00004e, -0x80000261, -0xcc000042, -0x04380008, -0xcf800042, -0xc8080003, -0xc80c0003, -0xc8100003, -0xc8140003, -0xc8180003, -0xc81c0003, -0xc8240003, -0xc8280003, -0x29fc001f, -0x2ab0001f, -0x7ff3c00b, -0x28f0001f, -0x7ff3c00b, -0x2970001f, -0x7ff3c00b, -0x7d888001, -0x7dccc001, -0x7e510001, -0x7e954001, -0x7c908002, -0x7cd4c002, -0x7cbc800b, -0x9ac00003, -0x7c8f400b, -0x38b40001, -0x9b4000d8, -0xcc00004d, -0x9bc000d6, -0xcc00004e, -0xc80c03fd, -0xc81003fc, -0xccc00042, -0x8000016f, -0xcd000042, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xcc400040, -0xcc400040, -0xcc400040, -0x7c40c000, -0xccc00040, -0xccc0000d, -0x80000000, -0xd0400040, -0x7c40c000, -0x7c410000, -0x65140020, -0x7d4d402c, -0x24580002, -0x7d598020, -0x7c41c000, -0xcd800042, -0x69980020, -0xcd800042, -0xcdc00042, -0xc023c000, -0x05e40002, -0x7ca0800b, -0x26640010, -0x7ca4800c, -0xcc800040, -0xcdc00040, -0xccc00040, -0x95c0000e, -0xcd000040, -0x09dc0001, -0xc8280003, -0x96800008, -0xce800040, -0xc834001d, -0x97400000, -0xc834001d, -0x26a80008, -0x84000264, -0xcc2b0000, -0x99c0fff7, -0x09dc0001, -0xdc3a0000, -0x97800004, -0x7c418000, -0x800001a3, -0x25980002, -0xa0000000, -0x7d808000, -0xc818001d, -0x7c40c000, -0x64d00008, -0x95800000, -0xc818001d, -0xcc130000, -0xcc800040, -0xccc00040, -0x80000000, -0xcc400040, -0xc810001f, -0x7c40c000, -0xcc800040, -0x7cd1400c, -0xcd400040, -0x05180001, -0x80000000, -0xcd800022, -0x7c40c000, -0x64500020, -0x84000264, -0xcc000061, -0x7cd0c02c, -0xc8200017, -0xc8d60000, -0x99400008, -0x7c438000, -0xdf830000, -0xcfa0004f, -0x84000264, -0xcc000062, -0x80000000, -0xd040007f, -0x80000261, -0xcc000062, -0x84000264, -0xcc000061, -0xc8200017, -0x7c40c000, -0xc036ff00, -0xc810000d, -0xc0303fff, -0x7cf5400b, -0x7d51800b, -0x7d81800f, -0x99800008, -0x7cf3800b, -0xdf830000, -0xcfa0004f, -0x84000264, -0xcc000062, -0x80000000, -0xd040007f, -0x80000261, -0xcc000062, -0x84000264, -0x7c40c000, -0x28dc0008, -0x95c00019, -0x30dc0010, -0x7c410000, -0x99c00004, -0x64540020, -0x80000209, -0xc91d0000, -0x7d15002c, -0xc91e0000, -0x7c420000, -0x7c424000, -0x7c418000, -0x7de5c00b, -0x7de28007, -0x9a80000e, -0x41ac0005, -0x9ac00000, -0x0aec0001, -0x30dc0010, -0x99c00004, -0x00000000, -0x8000020c, -0xc91d0000, -0x8000020c, -0xc91e0000, -0xcc800040, -0xccc00040, -0xd0400040, -0xc80c0025, -0x94c0fde3, -0xc8100008, -0xcd000040, -0xd4000fc0, -0x80000000, -0xd4000fa2, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0x7c40c000, -0x30d00006, -0x0d100006, -0x99000007, -0xc8140015, -0x99400005, -0xcc000052, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xccc00040, -0x80000000, -0xd0400040, -0x7c40c000, -0xcc4d0000, -0xdc3a0000, -0x9780fdbc, -0x04cc0001, -0x80000243, -0xcc4d0000, -0x7c40c000, -0x7c410000, -0x29240018, -0x32640001, -0x9640000f, -0xcc800040, -0x7c414000, -0x7c418000, -0x7c41c000, -0xccc00043, -0xcd000043, -0x31dc7fff, -0xcdc00043, -0xccc00040, -0xcd000040, -0xcd400040, -0xcd800040, -0x80000000, -0xcdc00040, -0xccc00040, -0xcd000040, -0x80000000, -0xd0400040, -0x80000000, -0xd040007f, -0xcc00007f, -0x80000000, -0xcc00007f, -0xcc00007f, -0x88000000, -0xcc00007f, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00030223, -0x0004022b, -0x000500a0, -0x00020003, -0x0006003c, -0x00070027, -0x00080192, -0x00090044, -0x000a002d, -0x0010025f, -0x001700f1, -0x002201d8, -0x002301e9, -0x0026004c, -0x0027005f, -0x0020011b, -0x00280093, -0x0029004f, -0x002a0084, -0x002b0065, -0x002f008e, -0x003200d9, -0x00340233, -0x00360075, -0x0039010b, -0x003c01fd, -0x003f00a0, -0x00410248, -0x00440195, -0x0048019e, -0x004901c6, -0x004a01d0, -0x00550226, -0x0056022e, -0x0060000a, -0x0061002a, -0x00620030, -0x00630030, -0x00640030, -0x00650030, -0x00660030, -0x00670030, -0x00680037, -0x0069003f, -0x006a0047, -0x006b0047, -0x006c0047, -0x006d0047, -0x006e0047, -0x006f0047, -0x00700047, -0x0073025f, -0x007b0241, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -}; - -static const u32 RV730_pfp_microcode[] = { -0x7c408000, -0xa0000000, -0x7e82800b, -0x80000000, -0xdc030000, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xc818000e, -0x31980001, -0x7c424000, -0x9580023a, -0x7c428000, -0xc81c001c, -0xc037c000, -0x7c40c000, -0x7c410000, -0x7cb4800b, -0xc0360003, -0x99c00000, -0xc81c001c, -0x7cb4800c, -0x24d40002, -0x7d654000, -0xcd400043, -0xce800043, -0xcd000043, -0xcc800040, -0xce400040, -0xce800040, -0xccc00040, -0xdc3a0000, -0x9780ffde, -0xcd000040, -0x7c40c000, -0x80000018, -0x7c410000, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xc818000e, -0x8000000c, -0x31980002, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xc818000e, -0x288c0008, -0x30cc000f, -0x34100001, -0x7d0d0008, -0x8000000c, -0x7d91800b, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xcc4003f9, -0x80000249, -0xcc4003f8, -0xc037ffff, -0x7c414000, -0xcf41a29e, -0xc82003f8, -0xc81c03f9, -0x66200020, -0xc81803fb, -0x7de1c02c, -0x7d58c008, -0x7cdcc020, -0x69100020, -0xc0360003, -0xcc000054, -0x7cb4800c, -0x80000069, -0xcc800040, -0x7c418000, -0xcd81a29e, -0xcc800040, -0x80000067, -0xcd800040, -0xc019ffff, -0xcc800040, -0xcd81a29e, -0x7c40c000, -0x7c410000, -0x7c414000, -0xccc1a1fa, -0xcd01a1f9, -0xcd41a29d, -0xccc00040, -0xcd000040, -0xcd400040, -0xcc400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xcc000054, -0xcc800040, -0x7c40c000, -0x7c410000, -0x7c414000, -0xccc1a1fa, -0xcd01a1f9, -0xcd41a29d, -0xccc00040, -0xcd000040, -0xcd400040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0x7c40c000, -0x30d00001, -0xccc1a29f, -0x95000003, -0x04140001, -0x04140002, -0xcd4003fb, -0xcc800040, -0x80000000, -0xccc00040, -0x7c40c000, -0xcc800040, -0xccc1a2a2, -0x80000000, -0xccc00040, -0x7c40c000, -0x28d4001f, -0xcc800040, -0x95400003, -0x7c410000, -0xccc00057, -0x2918001f, -0xccc00040, -0x95800003, -0xcd000040, -0xcd000058, -0x80000249, -0xcc00007f, -0xc8200017, -0xc8300022, -0x9a000006, -0x0e280001, -0xc824001e, -0x0a640001, -0xd4001240, -0xce400040, -0xc036c000, -0x96800007, -0x37747900, -0x041c0001, -0xcf400040, -0xcdc00040, -0xcf0003fa, -0x7c030000, -0xca0c0010, -0x7c410000, -0x94c00004, -0x7c414000, -0xd42002c4, -0xcde00044, -0x9b00000b, -0x7c418000, -0xcc00004b, -0xcda00049, -0xcd200041, -0xcd600041, -0xcda00041, -0x06200001, -0xce000056, -0x80000249, -0xcc00007f, -0xc8280020, -0xc82c0021, -0xcc000063, -0x7eea4001, -0x65740020, -0x7f53402c, -0x269c0002, -0x7df5c020, -0x69f80020, -0xce80004b, -0xce600049, -0xcde00041, -0xcfa00041, -0xce600041, -0x271c0002, -0x7df5c020, -0x69f80020, -0x7db24001, -0xcf00004b, -0xce600049, -0xcde00041, -0xcfa00041, -0x800000bc, -0xce600041, -0xc8200017, -0xc8300022, -0x9a000006, -0x0e280001, -0xc824001e, -0x0a640001, -0xd4001240, -0xce400040, -0xca0c0010, -0x7c410000, -0x94c0000b, -0xc036c000, -0x96800007, -0x37747900, -0x041c0001, -0xcf400040, -0xcdc00040, -0xcf0003fa, -0x7c030000, -0x800000b5, -0x7c414000, -0xcc000048, -0x800000ee, -0x00000000, -0xc8200017, -0xc81c0023, -0x0e240002, -0x99c00015, -0x7c418000, -0x0a200001, -0xce000056, -0xd4000440, -0xcc000040, -0xc036c000, -0xca140013, -0x96400007, -0x37747900, -0xcf400040, -0xcc000040, -0xc83003fa, -0x80000103, -0xcf000022, -0xcc000022, -0x95400146, -0xcc00007f, -0xcca00046, -0x80000000, -0xcc200046, -0x80000249, -0xcc000064, -0xc8200017, -0xc810001f, -0x96000005, -0x09100001, -0xd4000440, -0xcd000040, -0xcd000022, -0xcc800040, -0xd0400040, -0xc80c0025, -0x94c0feec, -0xc8100008, -0xcd000040, -0xd4000fc0, -0x80000000, -0xd4000fa2, -0x7c40c000, -0x7c410000, -0xccc003fd, -0xcd0003fc, -0xccc00042, -0xcd000042, -0x2914001f, -0x29180010, -0x31980007, -0x3b5c0001, -0x7d76000b, -0x99800005, -0x7d5e400b, -0xcc000042, -0x80000249, -0xcc00004d, -0x29980001, -0x292c0008, -0x9980003d, -0x32ec0001, -0x96000004, -0x2930000c, -0x80000249, -0xcc000042, -0x04140010, -0xcd400042, -0x33300001, -0x34280001, -0x8400015d, -0xc8140003, -0x9b40001b, -0x0438000c, -0x8400015d, -0xc8140003, -0x9b400017, -0x04380008, -0x8400015d, -0xc8140003, -0x9b400013, -0x04380004, -0x8400015d, -0xc8140003, -0x9b400015, -0xc80c03fd, -0x9a800009, -0xc81003fc, -0x9b000101, -0xcc00004d, -0x04140010, -0xccc00042, -0xcd000042, -0x80000135, -0xcd400042, -0x96c000fa, -0xcc00004d, -0x80000249, -0xcc00004e, -0x9ac00003, -0xcc00004d, -0xcc00004e, -0xdf830000, -0x80000000, -0xd80301ff, -0x9ac000f0, -0xcc00004d, -0x80000249, -0xcc00004e, -0xc8180003, -0xc81c0003, -0xc8200003, -0x7d5d4003, -0x7da1c003, -0x7d5d400c, -0x2a10001f, -0x299c001f, -0x7d1d000b, -0x7d17400b, -0x88000000, -0x7e92800b, -0x96400004, -0xcc00004e, -0x80000249, -0xcc000042, -0x04380008, -0xcf800042, -0xc8080003, -0xc80c0003, -0xc8100003, -0xc8140003, -0xc8180003, -0xc81c0003, -0xc8240003, -0xc8280003, -0x29fc001f, -0x2ab0001f, -0x7ff3c00b, -0x28f0001f, -0x7ff3c00b, -0x2970001f, -0x7ff3c00b, -0x7d888001, -0x7dccc001, -0x7e510001, -0x7e954001, -0x7c908002, -0x7cd4c002, -0x7cbc800b, -0x9ac00003, -0x7c8f400b, -0x38b40001, -0x9b4000c1, -0xcc00004d, -0x9bc000bf, -0xcc00004e, -0xc80c03fd, -0xc81003fc, -0xccc00042, -0x8000016e, -0xcd000042, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xcc400040, -0xcc400040, -0xcc400040, -0x7c40c000, -0xccc00040, -0xccc0000d, -0x80000000, -0xd0400040, -0x7c40c000, -0x7c410000, -0x65140020, -0x7d4d402c, -0x24580002, -0x7d598020, -0x7c41c000, -0xcd800042, -0x69980020, -0xcd800042, -0xcdc00042, -0xc023c000, -0x05e40002, -0x7ca0800b, -0x26640010, -0x7ca4800c, -0xcc800040, -0xcdc00040, -0xccc00040, -0x95c0000e, -0xcd000040, -0x09dc0001, -0xc8280003, -0x96800008, -0xce800040, -0xc834001d, -0x97400000, -0xc834001d, -0x26a80008, -0x8400024c, -0xcc2b0000, -0x99c0fff7, -0x09dc0001, -0xdc3a0000, -0x97800004, -0x7c418000, -0x800001a2, -0x25980002, -0xa0000000, -0x7d808000, -0xc818001d, -0x7c40c000, -0x64d00008, -0x95800000, -0xc818001d, -0xcc130000, -0xcc800040, -0xccc00040, -0x80000000, -0xcc400040, -0xc810001f, -0x7c40c000, -0xcc800040, -0x7cd1400c, -0xcd400040, -0x05180001, -0x80000000, -0xcd800022, -0x7c40c000, -0x64500020, -0x8400024c, -0xcc000061, -0x7cd0c02c, -0xc8200017, -0xc8d60000, -0x99400008, -0x7c438000, -0xdf830000, -0xcfa0004f, -0x8400024c, -0xcc000062, -0x80000000, -0xd040007f, -0x80000249, -0xcc000062, -0x8400024c, -0xcc000061, -0xc8200017, -0x7c40c000, -0xc036ff00, -0xc810000d, -0xc0303fff, -0x7cf5400b, -0x7d51800b, -0x7d81800f, -0x99800008, -0x7cf3800b, -0xdf830000, -0xcfa0004f, -0x8400024c, -0xcc000062, -0x80000000, -0xd040007f, -0x80000249, -0xcc000062, -0x8400024c, -0x7c40c000, -0x28dc0008, -0x95c00019, -0x30dc0010, -0x7c410000, -0x99c00004, -0x64540020, -0x80000208, -0xc91d0000, -0x7d15002c, -0xc91e0000, -0x7c420000, -0x7c424000, -0x7c418000, -0x7de5c00b, -0x7de28007, -0x9a80000e, -0x41ac0005, -0x9ac00000, -0x0aec0001, -0x30dc0010, -0x99c00004, -0x00000000, -0x8000020b, -0xc91d0000, -0x8000020b, -0xc91e0000, -0xcc800040, -0xccc00040, -0xd0400040, -0xc80c0025, -0x94c0fde4, -0xc8100008, -0xcd000040, -0xd4000fc0, -0x80000000, -0xd4000fa2, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0x7c40c000, -0x30d00006, -0x0d100006, -0x99000007, -0xc8140015, -0x99400005, -0xcc000052, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xccc00040, -0x80000000, -0xd0400040, -0x7c40c000, -0xcc4d0000, -0xdc3a0000, -0x9780fdbd, -0x04cc0001, -0x80000242, -0xcc4d0000, -0x80000000, -0xd040007f, -0xcc00007f, -0x80000000, -0xcc00007f, -0xcc00007f, -0x88000000, -0xcc00007f, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00030222, -0x0004022a, -0x0005009f, -0x00020003, -0x0006003c, -0x00070027, -0x00080191, -0x00090044, -0x000a002d, -0x00100247, -0x001700f0, -0x002201d7, -0x002301e8, -0x0026004c, -0x0027005f, -0x0020011a, -0x00280092, -0x0029004f, -0x002a0083, -0x002b0064, -0x002f008d, -0x003200d8, -0x00340232, -0x00360074, -0x0039010a, -0x003c01fc, -0x003f009f, -0x00410005, -0x00440194, -0x0048019d, -0x004901c5, -0x004a01cf, -0x00550225, -0x0056022d, -0x0060000a, -0x0061002a, -0x00620030, -0x00630030, -0x00640030, -0x00650030, -0x00660030, -0x00670030, -0x00680037, -0x0069003f, -0x006a0047, -0x006b0047, -0x006c0047, -0x006d0047, -0x006e0047, -0x006f0047, -0x00700047, -0x00730247, -0x007b0240, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -}; - -static const u32 RV730_cp_microcode[] = { -0xcc0003ea, -0x7c408000, -0xa0000000, -0xcc800062, -0x80000001, -0xd040007f, -0x80000001, -0xcc400041, -0x7c40c000, -0xc0160004, -0x30d03fff, -0x7d15000c, -0xcc110000, -0x28d8001e, -0x31980001, -0x28dc001f, -0xc8200004, -0x95c00006, -0x7c424000, -0xcc000062, -0x7e56800c, -0xcc290000, -0xc8240004, -0x7e26000b, -0x95800006, -0x7c42c000, -0xcc000062, -0x7ed7000c, -0xcc310000, -0xc82c0004, -0x7e2e000c, -0xcc000062, -0x31103fff, -0x80000001, -0xce110000, -0x7c40c000, -0x80000001, -0xcc400040, -0x80000001, -0xcc412257, -0x7c418000, -0xcc400045, -0xcc400048, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xcc400045, -0xcc400048, -0x7c40c000, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xcc000045, -0xcc000048, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0x040ca1fd, -0xc0120001, -0xcc000045, -0xcc000048, -0x7cd0c00c, -0xcc41225c, -0xcc41a1fc, -0xd04d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0x80000001, -0xcc41225d, -0x7c408000, -0x7c40c000, -0xc02a0002, -0x7c410000, -0x7d29000c, -0x30940001, -0x30980006, -0x309c0300, -0x29dc0008, -0x7c420000, -0x7c424000, -0x9540000f, -0xc02e0004, -0x05f02258, -0x7f2f000c, -0xcc310000, -0xc8280004, -0xccc12169, -0xcd01216a, -0xce81216b, -0x0db40002, -0xcc01216c, -0x9740000e, -0x0db40000, -0x8000007b, -0xc834000a, -0x0db40002, -0x97400009, -0x0db40000, -0xc02e0004, -0x05f02258, -0x7f2f000c, -0xcc310000, -0xc8280004, -0x8000007b, -0xc834000a, -0x97400004, -0x7e028000, -0x8000007b, -0xc834000a, -0x0db40004, -0x9740ff8c, -0x00000000, -0xce01216d, -0xce41216e, -0xc8280003, -0xc834000a, -0x9b400004, -0x043c0005, -0x8400026b, -0xcc000062, -0x0df40000, -0x9740000b, -0xc82c03e6, -0xce81a2b7, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c4, -0x80000001, -0xcfc1a2d1, -0x0df40001, -0x9740000b, -0xc82c03e7, -0xce81a2bb, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c5, -0x80000001, -0xcfc1a2d2, -0x0df40002, -0x9740000b, -0xc82c03e8, -0xce81a2bf, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c6, -0x80000001, -0xcfc1a2d3, -0xc82c03e9, -0xce81a2c3, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c7, -0x80000001, -0xcfc1a2d4, -0x80000001, -0xcc400042, -0x7c40c000, -0x7c410000, -0x2914001d, -0x31540001, -0x9940000c, -0x31181000, -0xc81c0011, -0x95c00000, -0xc81c0011, -0xccc12100, -0xcd012101, -0xccc12102, -0xcd012103, -0x04180004, -0x8000037c, -0xcd81a2a4, -0xc02a0004, -0x95800008, -0x36a821a3, -0xcc290000, -0xc8280004, -0xc81c0011, -0x0de40040, -0x9640ffff, -0xc81c0011, -0xccc12170, -0xcd012171, -0xc8200012, -0x96000000, -0xc8200012, -0x8000037c, -0xcc000064, -0x7c40c000, -0x7c410000, -0xcc000045, -0xcc000048, -0x40d40003, -0xcd41225c, -0xcd01a1fc, -0xc01a0001, -0x041ca1fd, -0x7dd9c00c, -0x7c420000, -0x08cc0001, -0x06240001, -0x06280002, -0xce1d0000, -0xce5d0000, -0x98c0fffa, -0xce9d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0x7c40c000, -0x30d00001, -0x28cc0001, -0x7c414000, -0x95000006, -0x7c418000, -0xcd41216d, -0xcd81216e, -0x800000f2, -0xc81c0003, -0xc0220004, -0x7e16000c, -0xcc210000, -0xc81c0004, -0x7c424000, -0x98c00004, -0x7c428000, -0x80000001, -0xcde50000, -0xce412169, -0xce81216a, -0xcdc1216b, -0x80000001, -0xcc01216c, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0x7c41c000, -0x28a40008, -0x326400ff, -0x0e68003c, -0x9680000a, -0x7c020000, -0x7c420000, -0x1e300003, -0xcc00006a, -0x9b000003, -0x42200005, -0x04200040, -0x8000010f, -0x7c024000, -0x7e024000, -0x9a400000, -0x0a640001, -0x30ec0010, -0x9ac0000a, -0xcc000062, -0xc02a0004, -0xc82c0021, -0x7e92800c, -0xcc000041, -0xcc290000, -0xcec00021, -0x8000011f, -0xc8300004, -0xcd01216d, -0xcd41216e, -0xc8300003, -0x7f1f000b, -0x30f40007, -0x27780001, -0x9740002a, -0x07b80124, -0x9f800000, -0x00000000, -0x80000134, -0x7f1b8004, -0x80000138, -0x7f1b8005, -0x8000013c, -0x7f1b8002, -0x80000140, -0x7f1b8003, -0x80000144, -0x7f1b8007, -0x80000148, -0x7f1b8006, -0x8000014d, -0x28a40008, -0x9b800019, -0x28a40008, -0x8000015d, -0x326400ff, -0x9b800015, -0x28a40008, -0x8000015d, -0x326400ff, -0x9b800011, -0x28a40008, -0x8000015d, -0x326400ff, -0x9b80000d, -0x28a40008, -0x8000015d, -0x326400ff, -0x9b800009, -0x28a40008, -0x8000015d, -0x326400ff, -0x9b800005, -0x28a40008, -0x8000015d, -0x326400ff, -0x28a40008, -0x326400ff, -0x0e68003c, -0x9a80feb2, -0x28ec0008, -0x7c434000, -0x7c438000, -0x7c43c000, -0x96c00007, -0xcc000062, -0xcf412169, -0xcf81216a, -0xcfc1216b, -0x80000001, -0xcc01216c, -0x80000001, -0xcff50000, -0xcc00006b, -0x8400037f, -0x0e68003c, -0x9a800004, -0xc8280015, -0x80000001, -0xd040007f, -0x9680ffab, -0x7e024000, -0x84000239, -0xc00e0002, -0xcc000041, -0x80000237, -0xccc1304a, -0x7c40c000, -0x7c410000, -0xc01e0001, -0x29240012, -0xc0220002, -0x96400005, -0xc0260004, -0xc027fffb, -0x7d25000b, -0xc0260000, -0x7dd2800b, -0x7e12c00b, -0x7d25000c, -0x7c414000, -0x7c418000, -0xccc12169, -0x9a80000a, -0xcd01216a, -0xcd41216b, -0x96c0fe83, -0xcd81216c, -0xc8300018, -0x97000000, -0xc8300018, -0x80000001, -0xcc000018, -0x8400037f, -0xcc00007f, -0xc8140013, -0xc8180014, -0xcd41216b, -0x96c0fe77, -0xcd81216c, -0x80000181, -0xc8300018, -0xc80c0008, -0x98c00000, -0xc80c0008, -0x7c410000, -0x95000002, -0x00000000, -0x7c414000, -0xc8200009, -0xcc400043, -0xce01a1f4, -0xcc400044, -0xc00e8000, -0x7c424000, -0x7c428000, -0x2aac001f, -0x96c0fe64, -0xc035f000, -0xce4003e2, -0x32780003, -0x267c0008, -0x7ff7c00b, -0x7ffbc00c, -0x2a780018, -0xcfc003e3, -0xcf8003e4, -0x26b00002, -0x7f3f0000, -0xcf0003e5, -0x8000031d, -0x7c80c000, -0x7c40c000, -0x28d00008, -0x3110000f, -0x9500000f, -0x25280001, -0x06a801b2, -0x9e800000, -0x00000000, -0x800001d3, -0xc0120800, -0x800001e1, -0xc814000f, -0x800001e8, -0xc8140010, -0x800001ef, -0xccc1a2a4, -0x800001f8, -0xc8140011, -0x30d0003f, -0x0d280015, -0x9a800012, -0x0d28001e, -0x9a80001e, -0x0d280020, -0x9a800023, -0x0d24000f, -0x0d280010, -0x7e6a800c, -0x9a800026, -0x0d200004, -0x0d240014, -0x0d280028, -0x7e62400c, -0x7ea6800c, -0x9a80002a, -0xc8140011, -0x80000001, -0xccc1a2a4, -0xc0120800, -0x7c414000, -0x7d0cc00c, -0xc0120008, -0x29580003, -0x295c000c, -0x7c420000, -0x7dd1c00b, -0x26200014, -0x7e1e400c, -0x7e4e800c, -0xce81a2a4, -0x80000001, -0xcd81a1fe, -0xc814000f, -0x0410210e, -0x95400000, -0xc814000f, -0xd0510000, -0x80000001, -0xccc1a2a4, -0xc8140010, -0x04102108, -0x95400000, -0xc8140010, -0xd0510000, -0x80000001, -0xccc1a2a4, -0xccc1a2a4, -0x04100001, -0xcd000019, -0x8400037f, -0xcc00007f, -0xc8100019, -0x99000000, -0xc8100019, -0x80000002, -0x7c408000, -0x04102100, -0x95400000, -0xc8140011, -0xd0510000, -0x8000037c, -0xccc1a2a4, -0x7c40c000, -0xcc40000d, -0x94c0fe01, -0xcc40000e, -0x7c410000, -0x95000005, -0x08cc0001, -0xc8140005, -0x99400014, -0x00000000, -0x98c0fffb, -0x7c410000, -0x80000002, -0x7d008000, -0xc8140005, -0x7c40c000, -0x9940000c, -0xc818000c, -0x7c410000, -0x9580fdf0, -0xc820000e, -0xc81c000d, -0x66200020, -0x7e1e002c, -0x25240002, -0x7e624020, -0x80000001, -0xcce60000, -0x7c410000, -0xcc00006c, -0xcc00006d, -0xc818001f, -0xc81c001e, -0x65980020, -0x7dd9c02c, -0x7cd4c00c, -0xccde0000, -0x45dc0004, -0xc8280017, -0x9680000f, -0xc00e0001, -0x28680008, -0x2aac0016, -0x32a800ff, -0x0eb00049, -0x7f2f000b, -0x97000006, -0x00000000, -0xc8140005, -0x7c40c000, -0x80000221, -0x7c410000, -0x80000224, -0xd040007f, -0x84000239, -0xcc000041, -0xccc1304a, -0x94000000, -0xc83c001a, -0x043c0005, -0xcfc1a2a4, -0xc0361f90, -0xc0387fff, -0x7c03c010, -0x7f7b400c, -0xcf41217c, -0xcfc1217d, -0xcc01217e, -0xc03a0004, -0x0434217f, -0x7f7b400c, -0xcc350000, -0xc83c0004, -0x2bfc001f, -0x04380020, -0x97c00005, -0xcc000062, -0x9b800000, -0x0bb80001, -0x80000245, -0xcc000071, -0xcc01a1f4, -0x04380016, -0xc0360002, -0xcf81a2a4, -0x88000000, -0xcf412010, -0x7c40c000, -0x28d0001c, -0x95000005, -0x04d40001, -0xcd400065, -0x80000001, -0xcd400068, -0x09540002, -0x80000001, -0xcd400066, -0x8400026a, -0xc81803ea, -0x7c40c000, -0x9980fd9f, -0xc8140016, -0x08d00001, -0x9940002b, -0xcd000068, -0x7c408000, -0xa0000000, -0xcc800062, -0x043c0005, -0xcfc1a2a4, -0xcc01a1f4, -0x8400037f, -0xcc000046, -0x88000000, -0xcc00007f, -0x8400027c, -0xc81803ea, -0x7c40c000, -0x9980fd8d, -0xc8140016, -0x08d00001, -0x99400019, -0xcd000068, -0x7c408000, -0xa0000000, -0xcc800062, -0x043c0022, -0xcfc1a2a4, -0x8400037f, -0xcc000047, -0x88000000, -0xcc00007f, -0xc8100016, -0x9900000d, -0xcc400067, -0x80000002, -0x7c408000, -0xc81803ea, -0x9980fd79, -0x7c40c000, -0x94c00003, -0xc8100016, -0x99000004, -0xccc00068, -0x80000002, -0x7c408000, -0x84000239, -0xc0148000, -0xcc000041, -0xcd41304a, -0xc0148000, -0x99000000, -0xc8100016, -0x80000002, -0x7c408000, -0xc0120001, -0x7c51400c, -0x80000001, -0xd0550000, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0x291c001f, -0xccc0004a, -0xcd00004b, -0x95c00003, -0xc01c8000, -0xcdc12010, -0xdd830000, -0x055c2000, -0xcc000062, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc0004c, -0xcd00004d, -0xdd830000, -0x055ca000, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc0004e, -0xcd00004f, -0xdd830000, -0x055cc000, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00050, -0xcd000051, -0xdd830000, -0x055cf8e0, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00052, -0xcd000053, -0xdd830000, -0x055cf880, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00054, -0xcd000055, -0xdd830000, -0x055ce000, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00056, -0xcd000057, -0xdd830000, -0x055cf000, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00058, -0xcd000059, -0xdd830000, -0x055cf3fc, -0x80000001, -0xd81f4100, -0xd0432000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043a000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043c000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f8e0, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f880, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043e000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f3fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xc81403e0, -0xcc430000, -0xcc430000, -0xcc430000, -0x7d45c000, -0xcdc30000, -0xd0430000, -0x7c408000, -0xa0000000, -0xcc800062, -0x7c40c000, -0xc81003e2, -0xc81403e5, -0xc81803e3, -0xc81c03e4, -0xcd812169, -0xcdc1216a, -0xccc1216b, -0xcc01216c, -0x04200004, -0x7da18000, -0x7d964002, -0x9640fcd9, -0xcd8003e3, -0x31280003, -0xc02df000, -0x25180008, -0x7dad800b, -0x7da9800c, -0x80000001, -0xcd8003e3, -0x308cffff, -0xd04d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0xc8140020, -0x15580002, -0x9580ffff, -0xc8140020, -0xcc00006e, -0xcc412180, -0x7c40c000, -0xccc1218d, -0xcc412181, -0x28d0001f, -0x34588000, -0xcd81218c, -0x9500fcbf, -0xcc412182, -0xc8140020, -0x9940ffff, -0xc8140020, -0x80000002, -0x7c408000, -0x7c40c000, -0x28d00018, -0x31100001, -0xc0160080, -0x95000003, -0xc02a0004, -0x7cd4c00c, -0xccc1217c, -0xcc41217d, -0xcc41217e, -0x7c418000, -0x1db00003, -0x36a0217f, -0x9b000003, -0x419c0005, -0x041c0040, -0x99c00000, -0x09dc0001, -0xcc210000, -0xc8240004, -0x2a6c001f, -0x419c0005, -0x9ac0fffa, -0xcc800062, -0x80000002, -0x7c408000, -0x7c40c000, -0x04d403e6, -0x80000001, -0xcc540000, -0x8000037c, -0xcc4003ea, -0xc01c8000, -0x044ca000, -0xcdc12010, -0x7c410000, -0xc8140009, -0x04180000, -0x041c0008, -0xcd800071, -0x09dc0001, -0x05980001, -0xcd0d0000, -0x99c0fffc, -0xcc800062, -0x8000037c, -0xcd400071, -0xc00e0100, -0xcc000041, -0xccc1304a, -0xc83c007f, -0xcc00007f, -0x80000001, -0xcc00007f, -0xcc00007f, -0x88000000, -0xcc00007f, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00010331, -0x00100004, -0x00170006, -0x00210008, -0x00270028, -0x00280023, -0x00290029, -0x002a0026, -0x002b0029, -0x002d0038, -0x002e003f, -0x002f004a, -0x0034004c, -0x00360030, -0x003900af, -0x003a00cf, -0x003b00e4, -0x003c00fc, -0x003d016b, -0x003f00ad, -0x00410336, -0x00430349, -0x0044018e, -0x004500fc, -0x004601ac, -0x004701ac, -0x004801fe, -0x0049020c, -0x004a0255, -0x004b0282, -0x0052025f, -0x00530271, -0x00540287, -0x00570299, -0x0060029d, -0x006102ac, -0x006202b6, -0x006302c0, -0x006402ca, -0x006502d4, -0x006602de, -0x006702e8, -0x006802f2, -0x006902f6, -0x006a02fa, -0x006b02fe, -0x006c0302, -0x006d0306, -0x006e030a, -0x006f030e, -0x00700312, -0x00720363, -0x00740369, -0x00790367, -0x007c031c, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -}; - -static const u32 RV710_pfp_microcode[] = { -0x7c408000, -0xa0000000, -0x7e82800b, -0x80000000, -0xdc030000, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xc818000e, -0x31980001, -0x7c424000, -0x9580023a, -0x7c428000, -0xc81c001c, -0xc037c000, -0x7c40c000, -0x7c410000, -0x7cb4800b, -0xc0360003, -0x99c00000, -0xc81c001c, -0x7cb4800c, -0x24d40002, -0x7d654000, -0xcd400043, -0xce800043, -0xcd000043, -0xcc800040, -0xce400040, -0xce800040, -0xccc00040, -0xdc3a0000, -0x9780ffde, -0xcd000040, -0x7c40c000, -0x80000018, -0x7c410000, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xc818000e, -0x8000000c, -0x31980002, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xc818000e, -0x288c0008, -0x30cc000f, -0x34100001, -0x7d0d0008, -0x8000000c, -0x7d91800b, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xcc4003f9, -0x80000249, -0xcc4003f8, -0xc037ffff, -0x7c414000, -0xcf41a29e, -0xc82003f8, -0xc81c03f9, -0x66200020, -0xc81803fb, -0x7de1c02c, -0x7d58c008, -0x7cdcc020, -0x69100020, -0xc0360003, -0xcc000054, -0x7cb4800c, -0x80000069, -0xcc800040, -0x7c418000, -0xcd81a29e, -0xcc800040, -0x80000067, -0xcd800040, -0xc019ffff, -0xcc800040, -0xcd81a29e, -0x7c40c000, -0x7c410000, -0x7c414000, -0xccc1a1fa, -0xcd01a1f9, -0xcd41a29d, -0xccc00040, -0xcd000040, -0xcd400040, -0xcc400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xcc000054, -0xcc800040, -0x7c40c000, -0x7c410000, -0x7c414000, -0xccc1a1fa, -0xcd01a1f9, -0xcd41a29d, -0xccc00040, -0xcd000040, -0xcd400040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0x7c40c000, -0x30d00001, -0xccc1a29f, -0x95000003, -0x04140001, -0x04140002, -0xcd4003fb, -0xcc800040, -0x80000000, -0xccc00040, -0x7c40c000, -0xcc800040, -0xccc1a2a2, -0x80000000, -0xccc00040, -0x7c40c000, -0x28d4001f, -0xcc800040, -0x95400003, -0x7c410000, -0xccc00057, -0x2918001f, -0xccc00040, -0x95800003, -0xcd000040, -0xcd000058, -0x80000249, -0xcc00007f, -0xc8200017, -0xc8300022, -0x9a000006, -0x0e280001, -0xc824001e, -0x0a640001, -0xd4001240, -0xce400040, -0xc036c000, -0x96800007, -0x37747900, -0x041c0001, -0xcf400040, -0xcdc00040, -0xcf0003fa, -0x7c030000, -0xca0c0010, -0x7c410000, -0x94c00004, -0x7c414000, -0xd42002c4, -0xcde00044, -0x9b00000b, -0x7c418000, -0xcc00004b, -0xcda00049, -0xcd200041, -0xcd600041, -0xcda00041, -0x06200001, -0xce000056, -0x80000249, -0xcc00007f, -0xc8280020, -0xc82c0021, -0xcc000063, -0x7eea4001, -0x65740020, -0x7f53402c, -0x269c0002, -0x7df5c020, -0x69f80020, -0xce80004b, -0xce600049, -0xcde00041, -0xcfa00041, -0xce600041, -0x271c0002, -0x7df5c020, -0x69f80020, -0x7db24001, -0xcf00004b, -0xce600049, -0xcde00041, -0xcfa00041, -0x800000bc, -0xce600041, -0xc8200017, -0xc8300022, -0x9a000006, -0x0e280001, -0xc824001e, -0x0a640001, -0xd4001240, -0xce400040, -0xca0c0010, -0x7c410000, -0x94c0000b, -0xc036c000, -0x96800007, -0x37747900, -0x041c0001, -0xcf400040, -0xcdc00040, -0xcf0003fa, -0x7c030000, -0x800000b5, -0x7c414000, -0xcc000048, -0x800000ee, -0x00000000, -0xc8200017, -0xc81c0023, -0x0e240002, -0x99c00015, -0x7c418000, -0x0a200001, -0xce000056, -0xd4000440, -0xcc000040, -0xc036c000, -0xca140013, -0x96400007, -0x37747900, -0xcf400040, -0xcc000040, -0xc83003fa, -0x80000103, -0xcf000022, -0xcc000022, -0x95400146, -0xcc00007f, -0xcca00046, -0x80000000, -0xcc200046, -0x80000249, -0xcc000064, -0xc8200017, -0xc810001f, -0x96000005, -0x09100001, -0xd4000440, -0xcd000040, -0xcd000022, -0xcc800040, -0xd0400040, -0xc80c0025, -0x94c0feec, -0xc8100008, -0xcd000040, -0xd4000fc0, -0x80000000, -0xd4000fa2, -0x7c40c000, -0x7c410000, -0xccc003fd, -0xcd0003fc, -0xccc00042, -0xcd000042, -0x2914001f, -0x29180010, -0x31980007, -0x3b5c0001, -0x7d76000b, -0x99800005, -0x7d5e400b, -0xcc000042, -0x80000249, -0xcc00004d, -0x29980001, -0x292c0008, -0x9980003d, -0x32ec0001, -0x96000004, -0x2930000c, -0x80000249, -0xcc000042, -0x04140010, -0xcd400042, -0x33300001, -0x34280001, -0x8400015d, -0xc8140003, -0x9b40001b, -0x0438000c, -0x8400015d, -0xc8140003, -0x9b400017, -0x04380008, -0x8400015d, -0xc8140003, -0x9b400013, -0x04380004, -0x8400015d, -0xc8140003, -0x9b400015, -0xc80c03fd, -0x9a800009, -0xc81003fc, -0x9b000101, -0xcc00004d, -0x04140010, -0xccc00042, -0xcd000042, -0x80000135, -0xcd400042, -0x96c000fa, -0xcc00004d, -0x80000249, -0xcc00004e, -0x9ac00003, -0xcc00004d, -0xcc00004e, -0xdf830000, -0x80000000, -0xd80301ff, -0x9ac000f0, -0xcc00004d, -0x80000249, -0xcc00004e, -0xc8180003, -0xc81c0003, -0xc8200003, -0x7d5d4003, -0x7da1c003, -0x7d5d400c, -0x2a10001f, -0x299c001f, -0x7d1d000b, -0x7d17400b, -0x88000000, -0x7e92800b, -0x96400004, -0xcc00004e, -0x80000249, -0xcc000042, -0x04380008, -0xcf800042, -0xc8080003, -0xc80c0003, -0xc8100003, -0xc8140003, -0xc8180003, -0xc81c0003, -0xc8240003, -0xc8280003, -0x29fc001f, -0x2ab0001f, -0x7ff3c00b, -0x28f0001f, -0x7ff3c00b, -0x2970001f, -0x7ff3c00b, -0x7d888001, -0x7dccc001, -0x7e510001, -0x7e954001, -0x7c908002, -0x7cd4c002, -0x7cbc800b, -0x9ac00003, -0x7c8f400b, -0x38b40001, -0x9b4000c1, -0xcc00004d, -0x9bc000bf, -0xcc00004e, -0xc80c03fd, -0xc81003fc, -0xccc00042, -0x8000016e, -0xcd000042, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xcc400040, -0xcc400040, -0xcc400040, -0x7c40c000, -0xccc00040, -0xccc0000d, -0x80000000, -0xd0400040, -0x7c40c000, -0x7c410000, -0x65140020, -0x7d4d402c, -0x24580002, -0x7d598020, -0x7c41c000, -0xcd800042, -0x69980020, -0xcd800042, -0xcdc00042, -0xc023c000, -0x05e40002, -0x7ca0800b, -0x26640010, -0x7ca4800c, -0xcc800040, -0xcdc00040, -0xccc00040, -0x95c0000e, -0xcd000040, -0x09dc0001, -0xc8280003, -0x96800008, -0xce800040, -0xc834001d, -0x97400000, -0xc834001d, -0x26a80008, -0x8400024c, -0xcc2b0000, -0x99c0fff7, -0x09dc0001, -0xdc3a0000, -0x97800004, -0x7c418000, -0x800001a2, -0x25980002, -0xa0000000, -0x7d808000, -0xc818001d, -0x7c40c000, -0x64d00008, -0x95800000, -0xc818001d, -0xcc130000, -0xcc800040, -0xccc00040, -0x80000000, -0xcc400040, -0xc810001f, -0x7c40c000, -0xcc800040, -0x7cd1400c, -0xcd400040, -0x05180001, -0x80000000, -0xcd800022, -0x7c40c000, -0x64500020, -0x8400024c, -0xcc000061, -0x7cd0c02c, -0xc8200017, -0xc8d60000, -0x99400008, -0x7c438000, -0xdf830000, -0xcfa0004f, -0x8400024c, -0xcc000062, -0x80000000, -0xd040007f, -0x80000249, -0xcc000062, -0x8400024c, -0xcc000061, -0xc8200017, -0x7c40c000, -0xc036ff00, -0xc810000d, -0xc0303fff, -0x7cf5400b, -0x7d51800b, -0x7d81800f, -0x99800008, -0x7cf3800b, -0xdf830000, -0xcfa0004f, -0x8400024c, -0xcc000062, -0x80000000, -0xd040007f, -0x80000249, -0xcc000062, -0x8400024c, -0x7c40c000, -0x28dc0008, -0x95c00019, -0x30dc0010, -0x7c410000, -0x99c00004, -0x64540020, -0x80000208, -0xc91d0000, -0x7d15002c, -0xc91e0000, -0x7c420000, -0x7c424000, -0x7c418000, -0x7de5c00b, -0x7de28007, -0x9a80000e, -0x41ac0005, -0x9ac00000, -0x0aec0001, -0x30dc0010, -0x99c00004, -0x00000000, -0x8000020b, -0xc91d0000, -0x8000020b, -0xc91e0000, -0xcc800040, -0xccc00040, -0xd0400040, -0xc80c0025, -0x94c0fde4, -0xc8100008, -0xcd000040, -0xd4000fc0, -0x80000000, -0xd4000fa2, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0x7c40c000, -0x30d00006, -0x0d100006, -0x99000007, -0xc8140015, -0x99400005, -0xcc000052, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xccc00040, -0x80000000, -0xd0400040, -0x7c40c000, -0xcc4d0000, -0xdc3a0000, -0x9780fdbd, -0x04cc0001, -0x80000242, -0xcc4d0000, -0x80000000, -0xd040007f, -0xcc00007f, -0x80000000, -0xcc00007f, -0xcc00007f, -0x88000000, -0xcc00007f, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00030222, -0x0004022a, -0x0005009f, -0x00020003, -0x0006003c, -0x00070027, -0x00080191, -0x00090044, -0x000a002d, -0x00100247, -0x001700f0, -0x002201d7, -0x002301e8, -0x0026004c, -0x0027005f, -0x0020011a, -0x00280092, -0x0029004f, -0x002a0083, -0x002b0064, -0x002f008d, -0x003200d8, -0x00340232, -0x00360074, -0x0039010a, -0x003c01fc, -0x003f009f, -0x00410005, -0x00440194, -0x0048019d, -0x004901c5, -0x004a01cf, -0x00550225, -0x0056022d, -0x0060000a, -0x0061002a, -0x00620030, -0x00630030, -0x00640030, -0x00650030, -0x00660030, -0x00670030, -0x00680037, -0x0069003f, -0x006a0047, -0x006b0047, -0x006c0047, -0x006d0047, -0x006e0047, -0x006f0047, -0x00700047, -0x00730247, -0x007b0240, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -}; - -static const u32 RV710_cp_microcode[] = { -0xcc0003ea, -0x04080003, -0xcc800043, -0x7c408000, -0xa0000000, -0xcc800062, -0x80000003, -0xd040007f, -0x80000003, -0xcc400041, -0x7c40c000, -0xc0160004, -0x30d03fff, -0x7d15000c, -0xcc110000, -0x28d8001e, -0x31980001, -0x28dc001f, -0xc8200004, -0x95c00006, -0x7c424000, -0xcc000062, -0x7e56800c, -0xcc290000, -0xc8240004, -0x7e26000b, -0x95800006, -0x7c42c000, -0xcc000062, -0x7ed7000c, -0xcc310000, -0xc82c0004, -0x7e2e000c, -0xcc000062, -0x31103fff, -0x80000003, -0xce110000, -0x7c40c000, -0x80000003, -0xcc400040, -0x80000003, -0xcc412257, -0x7c418000, -0xcc400045, -0xcc400048, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xcc400045, -0xcc400048, -0x7c40c000, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xcc000045, -0xcc000048, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0x040ca1fd, -0xc0120001, -0xcc000045, -0xcc000048, -0x7cd0c00c, -0xcc41225c, -0xcc41a1fc, -0xd04d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0x80000003, -0xcc41225d, -0x7c408000, -0x7c40c000, -0xc02a0002, -0x7c410000, -0x7d29000c, -0x30940001, -0x30980006, -0x309c0300, -0x29dc0008, -0x7c420000, -0x7c424000, -0x9540000f, -0xc02e0004, -0x05f02258, -0x7f2f000c, -0xcc310000, -0xc8280004, -0xccc12169, -0xcd01216a, -0xce81216b, -0x0db40002, -0xcc01216c, -0x9740000e, -0x0db40000, -0x8000007d, -0xc834000a, -0x0db40002, -0x97400009, -0x0db40000, -0xc02e0004, -0x05f02258, -0x7f2f000c, -0xcc310000, -0xc8280004, -0x8000007d, -0xc834000a, -0x97400004, -0x7e028000, -0x8000007d, -0xc834000a, -0x0db40004, -0x9740ff8c, -0x00000000, -0xce01216d, -0xce41216e, -0xc8280003, -0xc834000a, -0x9b400004, -0x043c0005, -0x8400026d, -0xcc000062, -0x0df40000, -0x9740000b, -0xc82c03e6, -0xce81a2b7, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c4, -0x80000003, -0xcfc1a2d1, -0x0df40001, -0x9740000b, -0xc82c03e7, -0xce81a2bb, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c5, -0x80000003, -0xcfc1a2d2, -0x0df40002, -0x9740000b, -0xc82c03e8, -0xce81a2bf, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c6, -0x80000003, -0xcfc1a2d3, -0xc82c03e9, -0xce81a2c3, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c7, -0x80000003, -0xcfc1a2d4, -0x80000003, -0xcc400042, -0x7c40c000, -0x7c410000, -0x2914001d, -0x31540001, -0x9940000c, -0x31181000, -0xc81c0011, -0x95c00000, -0xc81c0011, -0xccc12100, -0xcd012101, -0xccc12102, -0xcd012103, -0x04180004, -0x8000037e, -0xcd81a2a4, -0xc02a0004, -0x95800008, -0x36a821a3, -0xcc290000, -0xc8280004, -0xc81c0011, -0x0de40040, -0x9640ffff, -0xc81c0011, -0xccc12170, -0xcd012171, -0xc8200012, -0x96000000, -0xc8200012, -0x8000037e, -0xcc000064, -0x7c40c000, -0x7c410000, -0xcc000045, -0xcc000048, -0x40d40003, -0xcd41225c, -0xcd01a1fc, -0xc01a0001, -0x041ca1fd, -0x7dd9c00c, -0x7c420000, -0x08cc0001, -0x06240001, -0x06280002, -0xce1d0000, -0xce5d0000, -0x98c0fffa, -0xce9d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0x7c40c000, -0x30d00001, -0x28cc0001, -0x7c414000, -0x95000006, -0x7c418000, -0xcd41216d, -0xcd81216e, -0x800000f4, -0xc81c0003, -0xc0220004, -0x7e16000c, -0xcc210000, -0xc81c0004, -0x7c424000, -0x98c00004, -0x7c428000, -0x80000003, -0xcde50000, -0xce412169, -0xce81216a, -0xcdc1216b, -0x80000003, -0xcc01216c, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0x7c41c000, -0x28a40008, -0x326400ff, -0x0e68003c, -0x9680000a, -0x7c020000, -0x7c420000, -0x1e300003, -0xcc00006a, -0x9b000003, -0x42200005, -0x04200040, -0x80000111, -0x7c024000, -0x7e024000, -0x9a400000, -0x0a640001, -0x30ec0010, -0x9ac0000a, -0xcc000062, -0xc02a0004, -0xc82c0021, -0x7e92800c, -0xcc000041, -0xcc290000, -0xcec00021, -0x80000121, -0xc8300004, -0xcd01216d, -0xcd41216e, -0xc8300003, -0x7f1f000b, -0x30f40007, -0x27780001, -0x9740002a, -0x07b80126, -0x9f800000, -0x00000000, -0x80000136, -0x7f1b8004, -0x8000013a, -0x7f1b8005, -0x8000013e, -0x7f1b8002, -0x80000142, -0x7f1b8003, -0x80000146, -0x7f1b8007, -0x8000014a, -0x7f1b8006, -0x8000014f, -0x28a40008, -0x9b800019, -0x28a40008, -0x8000015f, -0x326400ff, -0x9b800015, -0x28a40008, -0x8000015f, -0x326400ff, -0x9b800011, -0x28a40008, -0x8000015f, -0x326400ff, -0x9b80000d, -0x28a40008, -0x8000015f, -0x326400ff, -0x9b800009, -0x28a40008, -0x8000015f, -0x326400ff, -0x9b800005, -0x28a40008, -0x8000015f, -0x326400ff, -0x28a40008, -0x326400ff, -0x0e68003c, -0x9a80feb2, -0x28ec0008, -0x7c434000, -0x7c438000, -0x7c43c000, -0x96c00007, -0xcc000062, -0xcf412169, -0xcf81216a, -0xcfc1216b, -0x80000003, -0xcc01216c, -0x80000003, -0xcff50000, -0xcc00006b, -0x84000381, -0x0e68003c, -0x9a800004, -0xc8280015, -0x80000003, -0xd040007f, -0x9680ffab, -0x7e024000, -0x8400023b, -0xc00e0002, -0xcc000041, -0x80000239, -0xccc1304a, -0x7c40c000, -0x7c410000, -0xc01e0001, -0x29240012, -0xc0220002, -0x96400005, -0xc0260004, -0xc027fffb, -0x7d25000b, -0xc0260000, -0x7dd2800b, -0x7e12c00b, -0x7d25000c, -0x7c414000, -0x7c418000, -0xccc12169, -0x9a80000a, -0xcd01216a, -0xcd41216b, -0x96c0fe83, -0xcd81216c, -0xc8300018, -0x97000000, -0xc8300018, -0x80000003, -0xcc000018, -0x84000381, -0xcc00007f, -0xc8140013, -0xc8180014, -0xcd41216b, -0x96c0fe77, -0xcd81216c, -0x80000183, -0xc8300018, -0xc80c0008, -0x98c00000, -0xc80c0008, -0x7c410000, -0x95000002, -0x00000000, -0x7c414000, -0xc8200009, -0xcc400043, -0xce01a1f4, -0xcc400044, -0xc00e8000, -0x7c424000, -0x7c428000, -0x2aac001f, -0x96c0fe64, -0xc035f000, -0xce4003e2, -0x32780003, -0x267c0008, -0x7ff7c00b, -0x7ffbc00c, -0x2a780018, -0xcfc003e3, -0xcf8003e4, -0x26b00002, -0x7f3f0000, -0xcf0003e5, -0x8000031f, -0x7c80c000, -0x7c40c000, -0x28d00008, -0x3110000f, -0x9500000f, -0x25280001, -0x06a801b4, -0x9e800000, -0x00000000, -0x800001d5, -0xc0120800, -0x800001e3, -0xc814000f, -0x800001ea, -0xc8140010, -0x800001f1, -0xccc1a2a4, -0x800001fa, -0xc8140011, -0x30d0003f, -0x0d280015, -0x9a800012, -0x0d28001e, -0x9a80001e, -0x0d280020, -0x9a800023, -0x0d24000f, -0x0d280010, -0x7e6a800c, -0x9a800026, -0x0d200004, -0x0d240014, -0x0d280028, -0x7e62400c, -0x7ea6800c, -0x9a80002a, -0xc8140011, -0x80000003, -0xccc1a2a4, -0xc0120800, -0x7c414000, -0x7d0cc00c, -0xc0120008, -0x29580003, -0x295c000c, -0x7c420000, -0x7dd1c00b, -0x26200014, -0x7e1e400c, -0x7e4e800c, -0xce81a2a4, -0x80000003, -0xcd81a1fe, -0xc814000f, -0x0410210e, -0x95400000, -0xc814000f, -0xd0510000, -0x80000003, -0xccc1a2a4, -0xc8140010, -0x04102108, -0x95400000, -0xc8140010, -0xd0510000, -0x80000003, -0xccc1a2a4, -0xccc1a2a4, -0x04100001, -0xcd000019, -0x84000381, -0xcc00007f, -0xc8100019, -0x99000000, -0xc8100019, -0x80000004, -0x7c408000, -0x04102100, -0x95400000, -0xc8140011, -0xd0510000, -0x8000037e, -0xccc1a2a4, -0x7c40c000, -0xcc40000d, -0x94c0fe01, -0xcc40000e, -0x7c410000, -0x95000005, -0x08cc0001, -0xc8140005, -0x99400014, -0x00000000, -0x98c0fffb, -0x7c410000, -0x80000004, -0x7d008000, -0xc8140005, -0x7c40c000, -0x9940000c, -0xc818000c, -0x7c410000, -0x9580fdf0, -0xc820000e, -0xc81c000d, -0x66200020, -0x7e1e002c, -0x25240002, -0x7e624020, -0x80000003, -0xcce60000, -0x7c410000, -0xcc00006c, -0xcc00006d, -0xc818001f, -0xc81c001e, -0x65980020, -0x7dd9c02c, -0x7cd4c00c, -0xccde0000, -0x45dc0004, -0xc8280017, -0x9680000f, -0xc00e0001, -0x28680008, -0x2aac0016, -0x32a800ff, -0x0eb00049, -0x7f2f000b, -0x97000006, -0x00000000, -0xc8140005, -0x7c40c000, -0x80000223, -0x7c410000, -0x80000226, -0xd040007f, -0x8400023b, -0xcc000041, -0xccc1304a, -0x94000000, -0xc83c001a, -0x043c0005, -0xcfc1a2a4, -0xc0361f90, -0xc0387fff, -0x7c03c010, -0x7f7b400c, -0xcf41217c, -0xcfc1217d, -0xcc01217e, -0xc03a0004, -0x0434217f, -0x7f7b400c, -0xcc350000, -0xc83c0004, -0x2bfc001f, -0x04380020, -0x97c00005, -0xcc000062, -0x9b800000, -0x0bb80001, -0x80000247, -0xcc000071, -0xcc01a1f4, -0x04380016, -0xc0360002, -0xcf81a2a4, -0x88000000, -0xcf412010, -0x7c40c000, -0x28d0001c, -0x95000005, -0x04d40001, -0xcd400065, -0x80000003, -0xcd400068, -0x09540002, -0x80000003, -0xcd400066, -0x8400026c, -0xc81803ea, -0x7c40c000, -0x9980fd9f, -0xc8140016, -0x08d00001, -0x9940002b, -0xcd000068, -0x7c408000, -0xa0000000, -0xcc800062, -0x043c0005, -0xcfc1a2a4, -0xcc01a1f4, -0x84000381, -0xcc000046, -0x88000000, -0xcc00007f, -0x8400027e, -0xc81803ea, -0x7c40c000, -0x9980fd8d, -0xc8140016, -0x08d00001, -0x99400019, -0xcd000068, -0x7c408000, -0xa0000000, -0xcc800062, -0x043c0022, -0xcfc1a2a4, -0x84000381, -0xcc000047, -0x88000000, -0xcc00007f, -0xc8100016, -0x9900000d, -0xcc400067, -0x80000004, -0x7c408000, -0xc81803ea, -0x9980fd79, -0x7c40c000, -0x94c00003, -0xc8100016, -0x99000004, -0xccc00068, -0x80000004, -0x7c408000, -0x8400023b, -0xc0148000, -0xcc000041, -0xcd41304a, -0xc0148000, -0x99000000, -0xc8100016, -0x80000004, -0x7c408000, -0xc0120001, -0x7c51400c, -0x80000003, -0xd0550000, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0x291c001f, -0xccc0004a, -0xcd00004b, -0x95c00003, -0xc01c8000, -0xcdc12010, -0xdd830000, -0x055c2000, -0xcc000062, -0x80000003, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc0004c, -0xcd00004d, -0xdd830000, -0x055ca000, -0x80000003, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc0004e, -0xcd00004f, -0xdd830000, -0x055cc000, -0x80000003, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00050, -0xcd000051, -0xdd830000, -0x055cf8e0, -0x80000003, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00052, -0xcd000053, -0xdd830000, -0x055cf880, -0x80000003, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00054, -0xcd000055, -0xdd830000, -0x055ce000, -0x80000003, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00056, -0xcd000057, -0xdd830000, -0x055cf000, -0x80000003, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00058, -0xcd000059, -0xdd830000, -0x055cf3fc, -0x80000003, -0xd81f4100, -0xd0432000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043a000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043c000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f8e0, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f880, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043e000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f3fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xc81403e0, -0xcc430000, -0xcc430000, -0xcc430000, -0x7d45c000, -0xcdc30000, -0xd0430000, -0x7c408000, -0xa0000000, -0xcc800062, -0x7c40c000, -0xc81003e2, -0xc81403e5, -0xc81803e3, -0xc81c03e4, -0xcd812169, -0xcdc1216a, -0xccc1216b, -0xcc01216c, -0x04200004, -0x7da18000, -0x7d964002, -0x9640fcd9, -0xcd8003e3, -0x31280003, -0xc02df000, -0x25180008, -0x7dad800b, -0x7da9800c, -0x80000003, -0xcd8003e3, -0x308cffff, -0xd04d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0xc8140020, -0x15580002, -0x9580ffff, -0xc8140020, -0xcc00006e, -0xcc412180, -0x7c40c000, -0xccc1218d, -0xcc412181, -0x28d0001f, -0x34588000, -0xcd81218c, -0x9500fcbf, -0xcc412182, -0xc8140020, -0x9940ffff, -0xc8140020, -0x80000004, -0x7c408000, -0x7c40c000, -0x28d00018, -0x31100001, -0xc0160080, -0x95000003, -0xc02a0004, -0x7cd4c00c, -0xccc1217c, -0xcc41217d, -0xcc41217e, -0x7c418000, -0x1db00003, -0x36a0217f, -0x9b000003, -0x419c0005, -0x041c0040, -0x99c00000, -0x09dc0001, -0xcc210000, -0xc8240004, -0x2a6c001f, -0x419c0005, -0x9ac0fffa, -0xcc800062, -0x80000004, -0x7c408000, -0x7c40c000, -0x04d403e6, -0x80000003, -0xcc540000, -0x8000037e, -0xcc4003ea, -0xc01c8000, -0x044ca000, -0xcdc12010, -0x7c410000, -0xc8140009, -0x04180000, -0x041c0008, -0xcd800071, -0x09dc0001, -0x05980001, -0xcd0d0000, -0x99c0fffc, -0xcc800062, -0x8000037e, -0xcd400071, -0xc00e0100, -0xcc000041, -0xccc1304a, -0xc83c007f, -0xcc00007f, -0x80000003, -0xcc00007f, -0xcc00007f, -0x88000000, -0xcc00007f, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00010333, -0x00100006, -0x00170008, -0x0021000a, -0x0027002a, -0x00280025, -0x0029002b, -0x002a0028, -0x002b002b, -0x002d003a, -0x002e0041, -0x002f004c, -0x0034004e, -0x00360032, -0x003900b1, -0x003a00d1, -0x003b00e6, -0x003c00fe, -0x003d016d, -0x003f00af, -0x00410338, -0x0043034b, -0x00440190, -0x004500fe, -0x004601ae, -0x004701ae, -0x00480200, -0x0049020e, -0x004a0257, -0x004b0284, -0x00520261, -0x00530273, -0x00540289, -0x0057029b, -0x0060029f, -0x006102ae, -0x006202b8, -0x006302c2, -0x006402cc, -0x006502d6, -0x006602e0, -0x006702ea, -0x006802f4, -0x006902f8, -0x006a02fc, -0x006b0300, -0x006c0304, -0x006d0308, -0x006e030c, -0x006f0310, -0x00700314, -0x00720365, -0x0074036b, -0x00790369, -0x007c031e, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -}; - -#endif diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h new file mode 100644 index 000000000000..4a9028a85c9b --- /dev/null +++ b/drivers/gpu/drm/radeon/r600d.h @@ -0,0 +1,662 @@ +/* + * Copyright 2009 Advanced Micro Devices, Inc. + * Copyright 2009 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef R600D_H +#define R600D_H + +#define CP_PACKET2 0x80000000 +#define PACKET2_PAD_SHIFT 0 +#define PACKET2_PAD_MASK (0x3fffffff << 0) + +#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) + +#define R6XX_MAX_SH_GPRS 256 +#define R6XX_MAX_TEMP_GPRS 16 +#define R6XX_MAX_SH_THREADS 256 +#define R6XX_MAX_SH_STACK_ENTRIES 4096 +#define R6XX_MAX_BACKENDS 8 +#define R6XX_MAX_BACKENDS_MASK 0xff +#define R6XX_MAX_SIMDS 8 +#define R6XX_MAX_SIMDS_MASK 0xff +#define R6XX_MAX_PIPES 8 +#define R6XX_MAX_PIPES_MASK 0xff + +/* PTE flags */ +#define PTE_VALID (1 << 0) +#define PTE_SYSTEM (1 << 1) +#define PTE_SNOOPED (1 << 2) +#define PTE_READABLE (1 << 5) +#define PTE_WRITEABLE (1 << 6) + +/* Registers */ +#define ARB_POP 0x2418 +#define ENABLE_TC128 (1 << 30) +#define ARB_GDEC_RD_CNTL 0x246C + +#define CC_GC_SHADER_PIPE_CONFIG 0x8950 +#define CC_RB_BACKEND_DISABLE 0x98F4 +#define BACKEND_DISABLE(x) ((x) << 16) + +#define CB_COLOR0_BASE 0x28040 +#define CB_COLOR1_BASE 0x28044 +#define CB_COLOR2_BASE 0x28048 +#define CB_COLOR3_BASE 0x2804C +#define CB_COLOR4_BASE 0x28050 +#define CB_COLOR5_BASE 0x28054 +#define CB_COLOR6_BASE 0x28058 +#define CB_COLOR7_BASE 0x2805C +#define CB_COLOR7_FRAG 0x280FC + +#define CB_COLOR0_SIZE 0x28060 +#define CB_COLOR0_VIEW 0x28080 +#define CB_COLOR0_INFO 0x280a0 +#define CB_COLOR0_TILE 0x280c0 +#define CB_COLOR0_FRAG 0x280e0 +#define CB_COLOR0_MASK 0x28100 + +#define CONFIG_MEMSIZE 0x5428 +#define CONFIG_CNTL 0x5424 +#define CP_STAT 0x8680 +#define CP_COHER_BASE 0x85F8 +#define CP_DEBUG 0xC1FC +#define R_0086D8_CP_ME_CNTL 0x86D8 +#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) +#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) +#define CP_ME_RAM_DATA 0xC160 +#define CP_ME_RAM_RADDR 0xC158 +#define CP_ME_RAM_WADDR 0xC15C +#define CP_MEQ_THRESHOLDS 0x8764 +#define MEQ_END(x) ((x) << 16) +#define ROQ_END(x) ((x) << 24) +#define CP_PERFMON_CNTL 0x87FC +#define CP_PFP_UCODE_ADDR 0xC150 +#define CP_PFP_UCODE_DATA 0xC154 +#define CP_QUEUE_THRESHOLDS 0x8760 +#define ROQ_IB1_START(x) ((x) << 0) +#define ROQ_IB2_START(x) ((x) << 8) +#define CP_RB_BASE 0xC100 +#define CP_RB_CNTL 0xC104 +#define RB_BUFSZ(x) ((x)<<0) +#define RB_BLKSZ(x) ((x)<<8) +#define RB_NO_UPDATE (1<<27) +#define RB_RPTR_WR_ENA (1<<31) +#define BUF_SWAP_32BIT (2 << 16) +#define CP_RB_RPTR 0x8700 +#define CP_RB_RPTR_ADDR 0xC10C +#define CP_RB_RPTR_ADDR_HI 0xC110 +#define CP_RB_RPTR_WR 0xC108 +#define CP_RB_WPTR 0xC114 +#define CP_RB_WPTR_ADDR 0xC118 +#define CP_RB_WPTR_ADDR_HI 0xC11C +#define CP_RB_WPTR_DELAY 0x8704 +#define CP_ROQ_IB1_STAT 0x8784 +#define CP_ROQ_IB2_STAT 0x8788 +#define CP_SEM_WAIT_TIMER 0x85BC + +#define DB_DEBUG 0x9830 +#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) +#define DB_DEPTH_BASE 0x2800C +#define DB_WATERMARKS 0x9838 +#define DEPTH_FREE(x) ((x) << 0) +#define DEPTH_FLUSH(x) ((x) << 5) +#define DEPTH_PENDING_FREE(x) ((x) << 15) +#define DEPTH_CACHELINE_FREE(x) ((x) << 20) + +#define DCP_TILING_CONFIG 0x6CA0 +#define PIPE_TILING(x) ((x) << 1) +#define BANK_TILING(x) ((x) << 4) +#define GROUP_SIZE(x) ((x) << 6) +#define ROW_TILING(x) ((x) << 8) +#define BANK_SWAPS(x) ((x) << 11) +#define SAMPLE_SPLIT(x) ((x) << 14) +#define BACKEND_MAP(x) ((x) << 16) + +#define GB_TILING_CONFIG 0x98F0 + +#define GC_USER_SHADER_PIPE_CONFIG 0x8954 +#define INACTIVE_QD_PIPES(x) ((x) << 8) +#define INACTIVE_QD_PIPES_MASK 0x0000FF00 +#define INACTIVE_SIMDS(x) ((x) << 16) +#define INACTIVE_SIMDS_MASK 0x00FF0000 + +#define SQ_CONFIG 0x8c00 +# define VC_ENABLE (1 << 0) +# define EXPORT_SRC_C (1 << 1) +# define DX9_CONSTS (1 << 2) +# define ALU_INST_PREFER_VECTOR (1 << 3) +# define DX10_CLAMP (1 << 4) +# define CLAUSE_SEQ_PRIO(x) ((x) << 8) +# define PS_PRIO(x) ((x) << 24) +# define VS_PRIO(x) ((x) << 26) +# define GS_PRIO(x) ((x) << 28) +# define ES_PRIO(x) ((x) << 30) +#define SQ_GPR_RESOURCE_MGMT_1 0x8c04 +# define NUM_PS_GPRS(x) ((x) << 0) +# define NUM_VS_GPRS(x) ((x) << 16) +# define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) +#define SQ_GPR_RESOURCE_MGMT_2 0x8c08 +# define NUM_GS_GPRS(x) ((x) << 0) +# define NUM_ES_GPRS(x) ((x) << 16) +#define SQ_THREAD_RESOURCE_MGMT 0x8c0c +# define NUM_PS_THREADS(x) ((x) << 0) +# define NUM_VS_THREADS(x) ((x) << 8) +# define NUM_GS_THREADS(x) ((x) << 16) +# define NUM_ES_THREADS(x) ((x) << 24) +#define SQ_STACK_RESOURCE_MGMT_1 0x8c10 +# define NUM_PS_STACK_ENTRIES(x) ((x) << 0) +# define NUM_VS_STACK_ENTRIES(x) ((x) << 16) +#define SQ_STACK_RESOURCE_MGMT_2 0x8c14 +# define NUM_GS_STACK_ENTRIES(x) ((x) << 0) +# define NUM_ES_STACK_ENTRIES(x) ((x) << 16) + +#define GRBM_CNTL 0x8000 +# define GRBM_READ_TIMEOUT(x) ((x) << 0) +#define GRBM_STATUS 0x8010 +#define CMDFIFO_AVAIL_MASK 0x0000001F +#define GUI_ACTIVE (1<<31) +#define GRBM_STATUS2 0x8014 +#define GRBM_SOFT_RESET 0x8020 +#define SOFT_RESET_CP (1<<0) + +#define HDP_HOST_PATH_CNTL 0x2C00 +#define HDP_NONSURFACE_BASE 0x2C04 +#define HDP_NONSURFACE_INFO 0x2C08 +#define HDP_NONSURFACE_SIZE 0x2C0C +#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 +#define HDP_TILING_CONFIG 0x2F3C + +#define MC_VM_AGP_TOP 0x2184 +#define MC_VM_AGP_BOT 0x2188 +#define MC_VM_AGP_BASE 0x218C +#define MC_VM_FB_LOCATION 0x2180 +#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C +#define ENABLE_L1_TLB (1 << 0) +#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) +#define ENABLE_L1_STRICT_ORDERING (1 << 2) +#define SYSTEM_ACCESS_MODE_MASK 0x000000C0 +#define SYSTEM_ACCESS_MODE_SHIFT 6 +#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) +#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) +#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) +#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) +#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) +#define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) +#define ENABLE_SEMAPHORE_MODE (1 << 10) +#define ENABLE_WAIT_L2_QUERY (1 << 11) +#define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) +#define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 +#define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 +#define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) +#define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 +#define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 +#define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 +#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC +#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 +#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 +#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C +#define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 +#define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 +#define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 +#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 +#define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 +#define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C +#define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 +#define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 +#define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF +#define LOGICAL_PAGE_NUMBER_SHIFT 0 +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 + +#define PA_CL_ENHANCE 0x8A14 +#define CLIP_VTX_REORDER_ENA (1 << 0) +#define NUM_CLIP_SEQ(x) ((x) << 1) +#define PA_SC_AA_CONFIG 0x28C04 +#define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 +#define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 +#define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C +#define S0_X(x) ((x) << 0) +#define S0_Y(x) ((x) << 4) +#define S1_X(x) ((x) << 8) +#define S1_Y(x) ((x) << 12) +#define S2_X(x) ((x) << 16) +#define S2_Y(x) ((x) << 20) +#define S3_X(x) ((x) << 24) +#define S3_Y(x) ((x) << 28) +#define S4_X(x) ((x) << 0) +#define S4_Y(x) ((x) << 4) +#define S5_X(x) ((x) << 8) +#define S5_Y(x) ((x) << 12) +#define S6_X(x) ((x) << 16) +#define S6_Y(x) ((x) << 20) +#define S7_X(x) ((x) << 24) +#define S7_Y(x) ((x) << 28) +#define PA_SC_CLIPRECT_RULE 0x2820c +#define PA_SC_ENHANCE 0x8BF0 +#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) +#define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) +#define PA_SC_LINE_STIPPLE 0x28A0C +#define PA_SC_LINE_STIPPLE_STATE 0x8B10 +#define PA_SC_MODE_CNTL 0x28A4C +#define PA_SC_MULTI_CHIP_CNTL 0x8B20 + +#define PA_SC_SCREEN_SCISSOR_TL 0x28030 +#define PA_SC_GENERIC_SCISSOR_TL 0x28240 +#define PA_SC_WINDOW_SCISSOR_TL 0x28204 + +#define PCIE_PORT_INDEX 0x0038 +#define PCIE_PORT_DATA 0x003C + +#define RAMCFG 0x2408 +#define NOOFBANK_SHIFT 0 +#define NOOFBANK_MASK 0x00000001 +#define NOOFRANK_SHIFT 1 +#define NOOFRANK_MASK 0x00000002 +#define NOOFROWS_SHIFT 2 +#define NOOFROWS_MASK 0x0000001C +#define NOOFCOLS_SHIFT 5 +#define NOOFCOLS_MASK 0x00000060 +#define CHANSIZE_SHIFT 7 +#define CHANSIZE_MASK 0x00000080 +#define BURSTLENGTH_SHIFT 8 +#define BURSTLENGTH_MASK 0x00000100 +#define CHANSIZE_OVERRIDE (1 << 10) + +#define SCRATCH_REG0 0x8500 +#define SCRATCH_REG1 0x8504 +#define SCRATCH_REG2 0x8508 +#define SCRATCH_REG3 0x850C +#define SCRATCH_REG4 0x8510 +#define SCRATCH_REG5 0x8514 +#define SCRATCH_REG6 0x8518 +#define SCRATCH_REG7 0x851C +#define SCRATCH_UMSK 0x8540 +#define SCRATCH_ADDR 0x8544 + +#define SPI_CONFIG_CNTL 0x9100 +#define GPR_WRITE_PRIORITY(x) ((x) << 0) +#define DISABLE_INTERP_1 (1 << 5) +#define SPI_CONFIG_CNTL_1 0x913C +#define VTX_DONE_DELAY(x) ((x) << 0) +#define INTERP_ONE_PRIM_PER_ROW (1 << 4) +#define SPI_INPUT_Z 0x286D8 +#define SPI_PS_IN_CONTROL_0 0x286CC +#define NUM_INTERP(x) ((x)<<0) +#define POSITION_ENA (1<<8) +#define POSITION_CENTROID (1<<9) +#define POSITION_ADDR(x) ((x)<<10) +#define PARAM_GEN(x) ((x)<<15) +#define PARAM_GEN_ADDR(x) ((x)<<19) +#define BARYC_SAMPLE_CNTL(x) ((x)<<26) +#define PERSP_GRADIENT_ENA (1<<28) +#define LINEAR_GRADIENT_ENA (1<<29) +#define POSITION_SAMPLE (1<<30) +#define BARYC_AT_SAMPLE_ENA (1<<31) +#define SPI_PS_IN_CONTROL_1 0x286D0 +#define GEN_INDEX_PIX (1<<0) +#define GEN_INDEX_PIX_ADDR(x) ((x)<<1) +#define FRONT_FACE_ENA (1<<8) +#define FRONT_FACE_CHAN(x) ((x)<<9) +#define FRONT_FACE_ALL_BITS (1<<11) +#define FRONT_FACE_ADDR(x) ((x)<<12) +#define FOG_ADDR(x) ((x)<<17) +#define FIXED_PT_POSITION_ENA (1<<24) +#define FIXED_PT_POSITION_ADDR(x) ((x)<<25) + +#define SQ_MS_FIFO_SIZES 0x8CF0 +#define CACHE_FIFO_SIZE(x) ((x) << 0) +#define FETCH_FIFO_HIWATER(x) ((x) << 8) +#define DONE_FIFO_HIWATER(x) ((x) << 16) +#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) +#define SQ_PGM_START_ES 0x28880 +#define SQ_PGM_START_FS 0x28894 +#define SQ_PGM_START_GS 0x2886C +#define SQ_PGM_START_PS 0x28840 +#define SQ_PGM_RESOURCES_PS 0x28850 +#define SQ_PGM_EXPORTS_PS 0x28854 +#define SQ_PGM_CF_OFFSET_PS 0x288cc +#define SQ_PGM_START_VS 0x28858 +#define SQ_PGM_RESOURCES_VS 0x28868 +#define SQ_PGM_CF_OFFSET_VS 0x288d0 +#define SQ_VTX_CONSTANT_WORD6_0 0x38018 +#define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) +#define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) +#define SQ_TEX_VTX_INVALID_TEXTURE 0x0 +#define SQ_TEX_VTX_INVALID_BUFFER 0x1 +#define SQ_TEX_VTX_VALID_TEXTURE 0x2 +#define SQ_TEX_VTX_VALID_BUFFER 0x3 + + +#define SX_MISC 0x28350 +#define SX_DEBUG_1 0x9054 +#define SMX_EVENT_RELEASE (1 << 0) +#define ENABLE_NEW_SMX_ADDRESS (1 << 16) + +#define TA_CNTL_AUX 0x9508 +#define DISABLE_CUBE_WRAP (1 << 0) +#define DISABLE_CUBE_ANISO (1 << 1) +#define SYNC_GRADIENT (1 << 24) +#define SYNC_WALKER (1 << 25) +#define SYNC_ALIGNER (1 << 26) +#define BILINEAR_PRECISION_6_BIT (0 << 31) +#define BILINEAR_PRECISION_8_BIT (1 << 31) + +#define TC_CNTL 0x9608 +#define TC_L2_SIZE(x) ((x)<<5) +#define L2_DISABLE_LATE_HIT (1<<9) + + +#define VGT_CACHE_INVALIDATION 0x88C4 +#define CACHE_INVALIDATION(x) ((x)<<0) +#define VC_ONLY 0 +#define TC_ONLY 1 +#define VC_AND_TC 2 +#define VGT_DMA_BASE 0x287E8 +#define VGT_DMA_BASE_HI 0x287E4 +#define VGT_ES_PER_GS 0x88CC +#define VGT_GS_PER_ES 0x88C8 +#define VGT_GS_PER_VS 0x88E8 +#define VGT_GS_VERTEX_REUSE 0x88D4 +#define VGT_PRIMITIVE_TYPE 0x8958 +#define VGT_NUM_INSTANCES 0x8974 +#define VGT_OUT_DEALLOC_CNTL 0x28C5C +#define DEALLOC_DIST_MASK 0x0000007F +#define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 +#define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 +#define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 +#define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c +#define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 +#define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 +#define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c +#define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 +#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 +#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 +#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 +#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 +#define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC +#define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC +#define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC +#define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C +#define VGT_STRMOUT_EN 0x28AB0 +#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 +#define VTX_REUSE_DEPTH_MASK 0x000000FF +#define VGT_EVENT_INITIATOR 0x28a90 +# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) + +#define VM_CONTEXT0_CNTL 0x1410 +#define ENABLE_CONTEXT (1 << 0) +#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) +#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) +#define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 +#define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 +#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 +#define REQUEST_TYPE(x) (((x) & 0xf) << 0) +#define RESPONSE_TYPE_MASK 0x000000F0 +#define RESPONSE_TYPE_SHIFT 4 +#define VM_L2_CNTL 0x1400 +#define ENABLE_L2_CACHE (1 << 0) +#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) +#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) +#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) +#define VM_L2_CNTL2 0x1404 +#define INVALIDATE_ALL_L1_TLBS (1 << 0) +#define INVALIDATE_L2_CACHE (1 << 1) +#define VM_L2_CNTL3 0x1408 +#define BANK_SELECT_0(x) (((x) & 0x1f) << 0) +#define BANK_SELECT_1(x) (((x) & 0x1f) << 5) +#define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) +#define VM_L2_STATUS 0x140C +#define L2_BUSY (1 << 0) + +#define WAIT_UNTIL 0x8040 +#define WAIT_2D_IDLE_bit (1 << 14) +#define WAIT_3D_IDLE_bit (1 << 15) +#define WAIT_2D_IDLECLEAN_bit (1 << 16) +#define WAIT_3D_IDLECLEAN_bit (1 << 17) + + + +/* + * PM4 + */ +#define PACKET_TYPE0 0 +#define PACKET_TYPE1 1 +#define PACKET_TYPE2 2 +#define PACKET_TYPE3 3 + +#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) +#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) +#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) +#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) +#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ + (((reg) >> 2) & 0xFFFF) | \ + ((n) & 0x3FFF) << 16) +#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ + (((op) & 0xFF) << 8) | \ + ((n) & 0x3FFF) << 16) + +/* Packet 3 types */ +#define PACKET3_NOP 0x10 +#define PACKET3_INDIRECT_BUFFER_END 0x17 +#define PACKET3_SET_PREDICATION 0x20 +#define PACKET3_REG_RMW 0x21 +#define PACKET3_COND_EXEC 0x22 +#define PACKET3_PRED_EXEC 0x23 +#define PACKET3_START_3D_CMDBUF 0x24 +#define PACKET3_DRAW_INDEX_2 0x27 +#define PACKET3_CONTEXT_CONTROL 0x28 +#define PACKET3_DRAW_INDEX_IMMD_BE 0x29 +#define PACKET3_INDEX_TYPE 0x2A +#define PACKET3_DRAW_INDEX 0x2B +#define PACKET3_DRAW_INDEX_AUTO 0x2D +#define PACKET3_DRAW_INDEX_IMMD 0x2E +#define PACKET3_NUM_INSTANCES 0x2F +#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 +#define PACKET3_INDIRECT_BUFFER_MP 0x38 +#define PACKET3_MEM_SEMAPHORE 0x39 +#define PACKET3_MPEG_INDEX 0x3A +#define PACKET3_WAIT_REG_MEM 0x3C +#define PACKET3_MEM_WRITE 0x3D +#define PACKET3_INDIRECT_BUFFER 0x32 +#define PACKET3_CP_INTERRUPT 0x40 +#define PACKET3_SURFACE_SYNC 0x43 +# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) +# define PACKET3_TC_ACTION_ENA (1 << 23) +# define PACKET3_VC_ACTION_ENA (1 << 24) +# define PACKET3_CB_ACTION_ENA (1 << 25) +# define PACKET3_DB_ACTION_ENA (1 << 26) +# define PACKET3_SH_ACTION_ENA (1 << 27) +# define PACKET3_SMX_ACTION_ENA (1 << 28) +#define PACKET3_ME_INITIALIZE 0x44 +#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) +#define PACKET3_COND_WRITE 0x45 +#define PACKET3_EVENT_WRITE 0x46 +#define PACKET3_EVENT_WRITE_EOP 0x47 +#define PACKET3_ONE_REG_WRITE 0x57 +#define PACKET3_SET_CONFIG_REG 0x68 +#define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 +#define PACKET3_SET_CONFIG_REG_END 0x0000ac00 +#define PACKET3_SET_CONTEXT_REG 0x69 +#define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 +#define PACKET3_SET_CONTEXT_REG_END 0x00029000 +#define PACKET3_SET_ALU_CONST 0x6A +#define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 +#define PACKET3_SET_ALU_CONST_END 0x00032000 +#define PACKET3_SET_BOOL_CONST 0x6B +#define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 +#define PACKET3_SET_BOOL_CONST_END 0x00040000 +#define PACKET3_SET_LOOP_CONST 0x6C +#define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 +#define PACKET3_SET_LOOP_CONST_END 0x0003e380 +#define PACKET3_SET_RESOURCE 0x6D +#define PACKET3_SET_RESOURCE_OFFSET 0x00038000 +#define PACKET3_SET_RESOURCE_END 0x0003c000 +#define PACKET3_SET_SAMPLER 0x6E +#define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 +#define PACKET3_SET_SAMPLER_END 0x0003cff0 +#define PACKET3_SET_CTL_CONST 0x6F +#define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 +#define PACKET3_SET_CTL_CONST_END 0x0003e200 +#define PACKET3_SURFACE_BASE_UPDATE 0x73 + + +#define R_008020_GRBM_SOFT_RESET 0x8020 +#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) +#define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) +#define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) +#define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) +#define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) +#define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) +#define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) +#define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) +#define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) +#define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) +#define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) +#define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) +#define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) +#define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) +#define R_008010_GRBM_STATUS 0x8010 +#define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) +#define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) +#define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) +#define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) +#define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) +#define S_008010_VC_BUSY(x) (((x) & 1) << 11) +#define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) +#define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) +#define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) +#define S_008010_VGT_BUSY(x) (((x) & 1) << 17) +#define S_008010_TA03_BUSY(x) (((x) & 1) << 18) +#define S_008010_TC_BUSY(x) (((x) & 1) << 19) +#define S_008010_SX_BUSY(x) (((x) & 1) << 20) +#define S_008010_SH_BUSY(x) (((x) & 1) << 21) +#define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) +#define S_008010_SMX_BUSY(x) (((x) & 1) << 23) +#define S_008010_SC_BUSY(x) (((x) & 1) << 24) +#define S_008010_PA_BUSY(x) (((x) & 1) << 25) +#define S_008010_DB03_BUSY(x) (((x) & 1) << 26) +#define S_008010_CR_BUSY(x) (((x) & 1) << 27) +#define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) +#define S_008010_CP_BUSY(x) (((x) & 1) << 29) +#define S_008010_CB03_BUSY(x) (((x) & 1) << 30) +#define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) +#define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) +#define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) +#define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) +#define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) +#define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) +#define G_008010_VC_BUSY(x) (((x) >> 11) & 1) +#define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) +#define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) +#define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) +#define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) +#define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) +#define G_008010_TC_BUSY(x) (((x) >> 19) & 1) +#define G_008010_SX_BUSY(x) (((x) >> 20) & 1) +#define G_008010_SH_BUSY(x) (((x) >> 21) & 1) +#define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) +#define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) +#define G_008010_SC_BUSY(x) (((x) >> 24) & 1) +#define G_008010_PA_BUSY(x) (((x) >> 25) & 1) +#define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) +#define G_008010_CR_BUSY(x) (((x) >> 27) & 1) +#define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) +#define G_008010_CP_BUSY(x) (((x) >> 29) & 1) +#define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) +#define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) +#define R_008014_GRBM_STATUS2 0x8014 +#define S_008014_CR_CLEAN(x) (((x) & 1) << 0) +#define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) +#define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) +#define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) +#define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) +#define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) +#define S_008014_TA0_BUSY(x) (((x) & 1) << 12) +#define S_008014_TA1_BUSY(x) (((x) & 1) << 13) +#define S_008014_TA2_BUSY(x) (((x) & 1) << 14) +#define S_008014_TA3_BUSY(x) (((x) & 1) << 15) +#define S_008014_DB0_BUSY(x) (((x) & 1) << 16) +#define S_008014_DB1_BUSY(x) (((x) & 1) << 17) +#define S_008014_DB2_BUSY(x) (((x) & 1) << 18) +#define S_008014_DB3_BUSY(x) (((x) & 1) << 19) +#define S_008014_CB0_BUSY(x) (((x) & 1) << 20) +#define S_008014_CB1_BUSY(x) (((x) & 1) << 21) +#define S_008014_CB2_BUSY(x) (((x) & 1) << 22) +#define S_008014_CB3_BUSY(x) (((x) & 1) << 23) +#define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) +#define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) +#define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) +#define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) +#define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) +#define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) +#define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) +#define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) +#define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) +#define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) +#define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) +#define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) +#define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) +#define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) +#define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) +#define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) +#define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) +#define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) +#define R_000E50_SRBM_STATUS 0x0E50 +#define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) +#define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) +#define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) +#define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) +#define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) +#define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) +#define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) +#define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) +#define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) +#define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) +#define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) +#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) +#define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) +#define R_000E60_SRBM_SOFT_RESET 0x0E60 +#define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) +#define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) +#define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) +#define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) +#define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) +#define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) +#define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) +#define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) +#define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) +#define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) +#define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) +#define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) +#define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) +#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) + +#endif diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index b519fb2fecbb..c839b608970f 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -51,7 +51,6 @@ #include "radeon_mode.h" #include "radeon_reg.h" -#include "r300.h" /* * Modules parameters. @@ -66,6 +65,7 @@ extern int radeon_gart_size; extern int radeon_benchmarking; extern int radeon_testing; extern int radeon_connector_table; +extern int radeon_tv; /* * Copy from radeon_drv.h so we don't have to include both and have conflicting @@ -75,6 +75,7 @@ extern int radeon_connector_table; #define RADEON_IB_POOL_SIZE 16 #define RADEON_DEBUGFS_MAX_NUM_FILES 32 #define RADEONFB_CONN_LIMIT 4 +#define RADEON_BIOS_NUM_SCRATCH 8 enum radeon_family { CHIP_R100, @@ -107,14 +108,15 @@ enum radeon_family { CHIP_R600, CHIP_RV610, CHIP_RV630, + CHIP_RV670, CHIP_RV620, CHIP_RV635, - CHIP_RV670, CHIP_RS780, + CHIP_RS880, CHIP_RV770, CHIP_RV730, CHIP_RV710, - CHIP_RS880, + CHIP_RV740, CHIP_LAST, }; @@ -151,10 +153,21 @@ struct radeon_device; */ bool radeon_get_bios(struct radeon_device *rdev); + /* - * Clocks + * Dummy page */ +struct radeon_dummy_page { + struct page *page; + dma_addr_t addr; +}; +int radeon_dummy_page_init(struct radeon_device *rdev); +void radeon_dummy_page_fini(struct radeon_device *rdev); + +/* + * Clocks + */ struct radeon_clock { struct radeon_pll p1pll; struct radeon_pll p2pll; @@ -165,6 +178,7 @@ struct radeon_clock { uint32_t default_sclk; }; + /* * Fences. */ @@ -331,14 +345,18 @@ struct radeon_mc { resource_size_t aper_size; resource_size_t aper_base; resource_size_t agp_base; - unsigned gtt_location; - unsigned gtt_size; - unsigned vram_location; /* for some chips with <= 32MB we need to lie * about vram size near mc fb location */ - unsigned mc_vram_size; + u64 mc_vram_size; + u64 gtt_location; + u64 gtt_size; + u64 gtt_start; + u64 gtt_end; + u64 vram_location; + u64 vram_start; + u64 vram_end; unsigned vram_width; - unsigned real_vram_size; + u64 real_vram_size; int vram_mtrr; bool vram_is_ddr; }; @@ -385,6 +403,10 @@ struct radeon_ib { uint32_t length_dw; }; +/* + * locking - + * mutex protects scheduled_ibs, ready, alloc_bm + */ struct radeon_ib_pool { struct mutex mutex; struct radeon_object *robj; @@ -410,6 +432,16 @@ struct radeon_cp { bool ready; }; +struct r600_blit { + struct radeon_object *shader_obj; + u64 shader_gpu_addr; + u32 vs_offset, ps_offset; + u32 state_offset; + u32 state_len; + u32 vb_used, vb_total; + struct radeon_ib *vb_ib; +}; + int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); @@ -462,6 +494,7 @@ struct radeon_cs_parser { int chunk_relocs_idx; struct radeon_ib *ib; void *track; + unsigned family; }; struct radeon_cs_packet { @@ -558,13 +591,19 @@ int r100_debugfs_cp_init(struct radeon_device *rdev); */ struct radeon_asic { int (*init)(struct radeon_device *rdev); + void (*fini)(struct radeon_device *rdev); + int (*resume)(struct radeon_device *rdev); + int (*suspend)(struct radeon_device *rdev); void (*errata)(struct radeon_device *rdev); void (*vram_info)(struct radeon_device *rdev); + void (*vga_set_state)(struct radeon_device *rdev, bool state); int (*gpu_reset)(struct radeon_device *rdev); int (*mc_init)(struct radeon_device *rdev); void (*mc_fini)(struct radeon_device *rdev); int (*wb_init)(struct radeon_device *rdev); void (*wb_fini)(struct radeon_device *rdev); + int (*gart_init)(struct radeon_device *rdev); + void (*gart_fini)(struct radeon_device *rdev); int (*gart_enable)(struct radeon_device *rdev); void (*gart_disable)(struct radeon_device *rdev); void (*gart_tlb_flush)(struct radeon_device *rdev); @@ -572,7 +611,11 @@ struct radeon_asic { int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); void (*cp_fini)(struct radeon_device *rdev); void (*cp_disable)(struct radeon_device *rdev); + void (*cp_commit)(struct radeon_device *rdev); void (*ring_start)(struct radeon_device *rdev); + int (*ring_test)(struct radeon_device *rdev); + void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); + int (*ib_test)(struct radeon_device *rdev); int (*irq_set)(struct radeon_device *rdev); int (*irq_process)(struct radeon_device *rdev); u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); @@ -604,8 +647,60 @@ struct radeon_asic { void (*bandwidth_update)(struct radeon_device *rdev); }; +/* + * Asic structures + */ +struct r100_asic { + const unsigned *reg_safe_bm; + unsigned reg_safe_bm_size; +}; + +struct r300_asic { + const unsigned *reg_safe_bm; + unsigned reg_safe_bm_size; +}; + +struct r600_asic { + unsigned max_pipes; + unsigned max_tile_pipes; + unsigned max_simds; + unsigned max_backends; + unsigned max_gprs; + unsigned max_threads; + unsigned max_stack_entries; + unsigned max_hw_contexts; + unsigned max_gs_threads; + unsigned sx_max_export_size; + unsigned sx_max_export_pos_size; + unsigned sx_max_export_smx_size; + unsigned sq_num_cf_insts; +}; + +struct rv770_asic { + unsigned max_pipes; + unsigned max_tile_pipes; + unsigned max_simds; + unsigned max_backends; + unsigned max_gprs; + unsigned max_threads; + unsigned max_stack_entries; + unsigned max_hw_contexts; + unsigned max_gs_threads; + unsigned sx_max_export_size; + unsigned sx_max_export_pos_size; + unsigned sx_max_export_smx_size; + unsigned sq_num_cf_insts; + unsigned sx_num_of_sets; + unsigned sc_prim_fifo_size; + unsigned sc_hiz_tile_fifo_size; + unsigned sc_earlyz_tile_fifo_fize; +}; + union radeon_asic_config { struct r300_asic r300; + struct r100_asic r100; + struct r600_asic r600; + struct rv770_asic rv770; }; @@ -646,6 +741,7 @@ typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); struct radeon_device { + struct device *dev; struct drm_device *ddev; struct pci_dev *pdev; /* ASIC */ @@ -689,13 +785,20 @@ struct radeon_device { struct radeon_asic *asic; struct radeon_gem gem; struct radeon_pm pm; + uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; struct mutex cs_mutex; struct radeon_wb wb; + struct radeon_dummy_page dummy_page; bool gpu_lockup; bool shutdown; bool suspend; bool need_dma32; + bool new_init_path; + bool accel_working; struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; + const struct firmware *me_fw; /* all family ME firmware */ + const struct firmware *pfp_fw; /* r6/700 PFP firmware */ + struct r600_blit r600_blit; }; int radeon_device_init(struct radeon_device *rdev, @@ -705,6 +808,13 @@ int radeon_device_init(struct radeon_device *rdev, void radeon_device_fini(struct radeon_device *rdev); int radeon_gpu_wait_for_idle(struct radeon_device *rdev); +/* r600 blit */ +int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); +void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); +void r600_kms_blit_copy(struct radeon_device *rdev, + u64 src_gpu_addr, u64 dst_gpu_addr, + int size_bytes); + static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) { if (reg < 0x10000) @@ -732,6 +842,7 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) #define RREG32(reg) r100_mm_rreg(rdev, (reg)) +#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) @@ -755,6 +866,7 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32 tmp_ |= ((val) & ~(mask)); \ WREG32_PLL(reg, tmp_); \ } while (0) +#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) /* * Indirect registers accessor @@ -819,51 +931,6 @@ void radeon_atombios_fini(struct radeon_device *rdev); /* * RING helpers. */ -#define CP_PACKET0 0x00000000 -#define PACKET0_BASE_INDEX_SHIFT 0 -#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) -#define PACKET0_COUNT_SHIFT 16 -#define PACKET0_COUNT_MASK (0x3fff << 16) -#define CP_PACKET1 0x40000000 -#define CP_PACKET2 0x80000000 -#define PACKET2_PAD_SHIFT 0 -#define PACKET2_PAD_MASK (0x3fffffff << 0) -#define CP_PACKET3 0xC0000000 -#define PACKET3_IT_OPCODE_SHIFT 8 -#define PACKET3_IT_OPCODE_MASK (0xff << 8) -#define PACKET3_COUNT_SHIFT 16 -#define PACKET3_COUNT_MASK (0x3fff << 16) -/* PACKET3 op code */ -#define PACKET3_NOP 0x10 -#define PACKET3_3D_DRAW_VBUF 0x28 -#define PACKET3_3D_DRAW_IMMD 0x29 -#define PACKET3_3D_DRAW_INDX 0x2A -#define PACKET3_3D_LOAD_VBPNTR 0x2F -#define PACKET3_INDX_BUFFER 0x33 -#define PACKET3_3D_DRAW_VBUF_2 0x34 -#define PACKET3_3D_DRAW_IMMD_2 0x35 -#define PACKET3_3D_DRAW_INDX_2 0x36 -#define PACKET3_BITBLT_MULTI 0x9B - -#define PACKET0(reg, n) (CP_PACKET0 | \ - REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ - REG_SET(PACKET0_COUNT, (n))) -#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) -#define PACKET3(op, n) (CP_PACKET3 | \ - REG_SET(PACKET3_IT_OPCODE, (op)) | \ - REG_SET(PACKET3_COUNT, (n))) - -#define PACKET_TYPE0 0 -#define PACKET_TYPE1 1 -#define PACKET_TYPE2 2 -#define PACKET_TYPE3 3 - -#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) -#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) -#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) -#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) -#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) - static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) { #if DRM_DEBUG_CODE @@ -882,14 +949,20 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) * ASICs macro. */ #define radeon_init(rdev) (rdev)->asic->init((rdev)) +#define radeon_fini(rdev) (rdev)->asic->fini((rdev)) +#define radeon_resume(rdev) (rdev)->asic->resume((rdev)) +#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev)) +#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev)) #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev)) #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev)) #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev)) +#define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev)) +#define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev)) #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev)) #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev)) #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) @@ -897,7 +970,11 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize)) #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev)) #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev)) +#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) +#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) +#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) +#define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev)) #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) @@ -913,4 +990,88 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) +/* Common functions */ +extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); +extern int radeon_modeset_init(struct radeon_device *rdev); +extern void radeon_modeset_fini(struct radeon_device *rdev); +extern bool radeon_card_posted(struct radeon_device *rdev); +extern int radeon_clocks_init(struct radeon_device *rdev); +extern void radeon_clocks_fini(struct radeon_device *rdev); +extern void radeon_scratch_init(struct radeon_device *rdev); +extern void radeon_surface_init(struct radeon_device *rdev); +extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); + +/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ +struct r100_mc_save { + u32 GENMO_WT; + u32 CRTC_EXT_CNTL; + u32 CRTC_GEN_CNTL; + u32 CRTC2_GEN_CNTL; + u32 CUR_OFFSET; + u32 CUR2_OFFSET; +}; +extern void r100_cp_disable(struct radeon_device *rdev); +extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); +extern void r100_cp_fini(struct radeon_device *rdev); +extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); +extern int r100_pci_gart_init(struct radeon_device *rdev); +extern void r100_pci_gart_fini(struct radeon_device *rdev); +extern int r100_pci_gart_enable(struct radeon_device *rdev); +extern void r100_pci_gart_disable(struct radeon_device *rdev); +extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); +extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); +extern int r100_gui_wait_for_idle(struct radeon_device *rdev); +extern void r100_ib_fini(struct radeon_device *rdev); +extern int r100_ib_init(struct radeon_device *rdev); +extern void r100_irq_disable(struct radeon_device *rdev); +extern int r100_irq_set(struct radeon_device *rdev); +extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); +extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); +extern void r100_vram_init_sizes(struct radeon_device *rdev); +extern void r100_wb_disable(struct radeon_device *rdev); +extern void r100_wb_fini(struct radeon_device *rdev); +extern int r100_wb_init(struct radeon_device *rdev); + +/* r300,r350,rv350,rv370,rv380 */ +extern void r300_set_reg_safe(struct radeon_device *rdev); +extern void r300_mc_program(struct radeon_device *rdev); +extern void r300_vram_info(struct radeon_device *rdev); +extern int rv370_pcie_gart_init(struct radeon_device *rdev); +extern void rv370_pcie_gart_fini(struct radeon_device *rdev); +extern int rv370_pcie_gart_enable(struct radeon_device *rdev); +extern void rv370_pcie_gart_disable(struct radeon_device *rdev); + +/* r420,r423,rv410 */ +extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); +extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); +extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); + +/* rv515 */ +extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); + +/* rs690, rs740 */ +extern void rs690_line_buffer_adjust(struct radeon_device *rdev, + struct drm_display_mode *mode1, + struct drm_display_mode *mode2); + +/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ +extern bool r600_card_posted(struct radeon_device *rdev); +extern void r600_cp_stop(struct radeon_device *rdev); +extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); +extern int r600_cp_resume(struct radeon_device *rdev); +extern int r600_count_pipe_bits(uint32_t val); +extern int r600_gart_clear_page(struct radeon_device *rdev, int i); +extern int r600_mc_wait_for_idle(struct radeon_device *rdev); +extern int r600_pcie_gart_init(struct radeon_device *rdev); +extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); +extern int r600_ib_test(struct radeon_device *rdev); +extern int r600_ring_test(struct radeon_device *rdev); +extern int r600_wb_init(struct radeon_device *rdev); +extern void r600_wb_fini(struct radeon_device *rdev); +extern void r600_scratch_init(struct radeon_device *rdev); +extern int r600_blit_init(struct radeon_device *rdev); +extern void r600_blit_fini(struct radeon_device *rdev); +extern int r600_cp_init_microcode(struct radeon_device *rdev); +extern int r600_gpu_reset(struct radeon_device *rdev); + #endif diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 93d8f8889302..8968f78fa1e3 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -42,23 +42,28 @@ void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ int r100_init(struct radeon_device *rdev); +int r200_init(struct radeon_device *rdev); uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); void r100_errata(struct radeon_device *rdev); void r100_vram_info(struct radeon_device *rdev); +void r100_vga_set_state(struct radeon_device *rdev, bool state); int r100_gpu_reset(struct radeon_device *rdev); int r100_mc_init(struct radeon_device *rdev); void r100_mc_fini(struct radeon_device *rdev); u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); int r100_wb_init(struct radeon_device *rdev); void r100_wb_fini(struct radeon_device *rdev); -int r100_gart_enable(struct radeon_device *rdev); +int r100_pci_gart_init(struct radeon_device *rdev); +void r100_pci_gart_fini(struct radeon_device *rdev); +int r100_pci_gart_enable(struct radeon_device *rdev); void r100_pci_gart_disable(struct radeon_device *rdev); void r100_pci_gart_tlb_flush(struct radeon_device *rdev); int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); void r100_cp_fini(struct radeon_device *rdev); void r100_cp_disable(struct radeon_device *rdev); +void r100_cp_commit(struct radeon_device *rdev); void r100_ring_start(struct radeon_device *rdev); int r100_irq_set(struct radeon_device *rdev); int r100_irq_process(struct radeon_device *rdev); @@ -77,24 +82,34 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg, uint32_t offset, uint32_t obj_size); int r100_clear_surface_reg(struct radeon_device *rdev, int reg); void r100_bandwidth_update(struct radeon_device *rdev); +void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); +int r100_ib_test(struct radeon_device *rdev); +int r100_ring_test(struct radeon_device *rdev); static struct radeon_asic r100_asic = { .init = &r100_init, .errata = &r100_errata, .vram_info = &r100_vram_info, + .vga_set_state = &r100_vga_set_state, .gpu_reset = &r100_gpu_reset, .mc_init = &r100_mc_init, .mc_fini = &r100_mc_fini, .wb_init = &r100_wb_init, .wb_fini = &r100_wb_fini, - .gart_enable = &r100_gart_enable, + .gart_init = &r100_pci_gart_init, + .gart_fini = &r100_pci_gart_fini, + .gart_enable = &r100_pci_gart_enable, .gart_disable = &r100_pci_gart_disable, .gart_tlb_flush = &r100_pci_gart_tlb_flush, .gart_set_page = &r100_pci_gart_set_page, .cp_init = &r100_cp_init, .cp_fini = &r100_cp_fini, .cp_disable = &r100_cp_disable, + .cp_commit = &r100_cp_commit, .ring_start = &r100_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .ib_test = &r100_ib_test, .irq_set = &r100_irq_set, .irq_process = &r100_irq_process, .get_vblank_counter = &r100_get_vblank_counter, @@ -126,7 +141,9 @@ void r300_ring_start(struct radeon_device *rdev); void r300_fence_ring_emit(struct radeon_device *rdev, struct radeon_fence *fence); int r300_cs_parse(struct radeon_cs_parser *p); -int r300_gart_enable(struct radeon_device *rdev); +int rv370_pcie_gart_init(struct radeon_device *rdev); +void rv370_pcie_gart_fini(struct radeon_device *rdev); +int rv370_pcie_gart_enable(struct radeon_device *rdev); void rv370_pcie_gart_disable(struct radeon_device *rdev); void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); @@ -143,19 +160,26 @@ static struct radeon_asic r300_asic = { .init = &r300_init, .errata = &r300_errata, .vram_info = &r300_vram_info, + .vga_set_state = &r100_vga_set_state, .gpu_reset = &r300_gpu_reset, .mc_init = &r300_mc_init, .mc_fini = &r300_mc_fini, .wb_init = &r100_wb_init, .wb_fini = &r100_wb_fini, - .gart_enable = &r300_gart_enable, + .gart_init = &r100_pci_gart_init, + .gart_fini = &r100_pci_gart_fini, + .gart_enable = &r100_pci_gart_enable, .gart_disable = &r100_pci_gart_disable, .gart_tlb_flush = &r100_pci_gart_tlb_flush, .gart_set_page = &r100_pci_gart_set_page, .cp_init = &r100_cp_init, .cp_fini = &r100_cp_fini, .cp_disable = &r100_cp_disable, + .cp_commit = &r100_cp_commit, .ring_start = &r300_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .ib_test = &r100_ib_test, .irq_set = &r100_irq_set, .irq_process = &r100_irq_process, .get_vblank_counter = &r100_get_vblank_counter, @@ -176,27 +200,35 @@ static struct radeon_asic r300_asic = { /* * r420,r423,rv410 */ -void r420_errata(struct radeon_device *rdev); -void r420_vram_info(struct radeon_device *rdev); -int r420_mc_init(struct radeon_device *rdev); -void r420_mc_fini(struct radeon_device *rdev); +extern int r420_init(struct radeon_device *rdev); +extern void r420_fini(struct radeon_device *rdev); +extern int r420_suspend(struct radeon_device *rdev); +extern int r420_resume(struct radeon_device *rdev); static struct radeon_asic r420_asic = { - .init = &r300_init, - .errata = &r420_errata, - .vram_info = &r420_vram_info, + .init = &r420_init, + .fini = &r420_fini, + .suspend = &r420_suspend, + .resume = &r420_resume, + .errata = NULL, + .vram_info = NULL, + .vga_set_state = &r100_vga_set_state, .gpu_reset = &r300_gpu_reset, - .mc_init = &r420_mc_init, - .mc_fini = &r420_mc_fini, - .wb_init = &r100_wb_init, - .wb_fini = &r100_wb_fini, - .gart_enable = &r300_gart_enable, - .gart_disable = &rv370_pcie_gart_disable, + .mc_init = NULL, + .mc_fini = NULL, + .wb_init = NULL, + .wb_fini = NULL, + .gart_enable = NULL, + .gart_disable = NULL, .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, .gart_set_page = &rv370_pcie_gart_set_page, - .cp_init = &r100_cp_init, - .cp_fini = &r100_cp_fini, - .cp_disable = &r100_cp_disable, + .cp_init = NULL, + .cp_fini = NULL, + .cp_disable = NULL, + .cp_commit = &r100_cp_commit, .ring_start = &r300_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .ib_test = NULL, .irq_set = &r100_irq_set, .irq_process = &r100_irq_process, .get_vblank_counter = &r100_get_vblank_counter, @@ -222,6 +254,8 @@ void rs400_errata(struct radeon_device *rdev); void rs400_vram_info(struct radeon_device *rdev); int rs400_mc_init(struct radeon_device *rdev); void rs400_mc_fini(struct radeon_device *rdev); +int rs400_gart_init(struct radeon_device *rdev); +void rs400_gart_fini(struct radeon_device *rdev); int rs400_gart_enable(struct radeon_device *rdev); void rs400_gart_disable(struct radeon_device *rdev); void rs400_gart_tlb_flush(struct radeon_device *rdev); @@ -232,11 +266,14 @@ static struct radeon_asic rs400_asic = { .init = &r300_init, .errata = &rs400_errata, .vram_info = &rs400_vram_info, + .vga_set_state = &r100_vga_set_state, .gpu_reset = &r300_gpu_reset, .mc_init = &rs400_mc_init, .mc_fini = &rs400_mc_fini, .wb_init = &r100_wb_init, .wb_fini = &r100_wb_fini, + .gart_init = &rs400_gart_init, + .gart_fini = &rs400_gart_fini, .gart_enable = &rs400_gart_enable, .gart_disable = &rs400_gart_disable, .gart_tlb_flush = &rs400_gart_tlb_flush, @@ -244,7 +281,11 @@ static struct radeon_asic rs400_asic = { .cp_init = &r100_cp_init, .cp_fini = &r100_cp_fini, .cp_disable = &r100_cp_disable, + .cp_commit = &r100_cp_commit, .ring_start = &r300_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .ib_test = &r100_ib_test, .irq_set = &r100_irq_set, .irq_process = &r100_irq_process, .get_vblank_counter = &r100_get_vblank_counter, @@ -266,7 +307,7 @@ static struct radeon_asic rs400_asic = { /* * rs600. */ -int rs600_init(struct radeon_device *dev); +int rs600_init(struct radeon_device *rdev); void rs600_errata(struct radeon_device *rdev); void rs600_vram_info(struct radeon_device *rdev); int rs600_mc_init(struct radeon_device *rdev); @@ -274,6 +315,8 @@ void rs600_mc_fini(struct radeon_device *rdev); int rs600_irq_set(struct radeon_device *rdev); int rs600_irq_process(struct radeon_device *rdev); u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); +int rs600_gart_init(struct radeon_device *rdev); +void rs600_gart_fini(struct radeon_device *rdev); int rs600_gart_enable(struct radeon_device *rdev); void rs600_gart_disable(struct radeon_device *rdev); void rs600_gart_tlb_flush(struct radeon_device *rdev); @@ -285,11 +328,14 @@ static struct radeon_asic rs600_asic = { .init = &rs600_init, .errata = &rs600_errata, .vram_info = &rs600_vram_info, + .vga_set_state = &r100_vga_set_state, .gpu_reset = &r300_gpu_reset, .mc_init = &rs600_mc_init, .mc_fini = &rs600_mc_fini, .wb_init = &r100_wb_init, .wb_fini = &r100_wb_fini, + .gart_init = &rs600_gart_init, + .gart_fini = &rs600_gart_fini, .gart_enable = &rs600_gart_enable, .gart_disable = &rs600_gart_disable, .gart_tlb_flush = &rs600_gart_tlb_flush, @@ -297,7 +343,11 @@ static struct radeon_asic rs600_asic = { .cp_init = &r100_cp_init, .cp_fini = &r100_cp_fini, .cp_disable = &r100_cp_disable, + .cp_commit = &r100_cp_commit, .ring_start = &r300_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .ib_test = &r100_ib_test, .irq_set = &rs600_irq_set, .irq_process = &rs600_irq_process, .get_vblank_counter = &rs600_get_vblank_counter, @@ -328,11 +378,14 @@ static struct radeon_asic rs690_asic = { .init = &rs600_init, .errata = &rs690_errata, .vram_info = &rs690_vram_info, + .vga_set_state = &r100_vga_set_state, .gpu_reset = &r300_gpu_reset, .mc_init = &rs690_mc_init, .mc_fini = &rs690_mc_fini, .wb_init = &r100_wb_init, .wb_fini = &r100_wb_fini, + .gart_init = &rs400_gart_init, + .gart_fini = &rs400_gart_fini, .gart_enable = &rs400_gart_enable, .gart_disable = &rs400_gart_disable, .gart_tlb_flush = &rs400_gart_tlb_flush, @@ -340,7 +393,11 @@ static struct radeon_asic rs690_asic = { .cp_init = &r100_cp_init, .cp_fini = &r100_cp_fini, .cp_disable = &r100_cp_disable, + .cp_commit = &r100_cp_commit, .ring_start = &r300_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .ib_test = &r100_ib_test, .irq_set = &rs600_irq_set, .irq_process = &rs600_irq_process, .get_vblank_counter = &rs600_get_vblank_counter, @@ -378,19 +435,26 @@ static struct radeon_asic rv515_asic = { .init = &rv515_init, .errata = &rv515_errata, .vram_info = &rv515_vram_info, + .vga_set_state = &r100_vga_set_state, .gpu_reset = &rv515_gpu_reset, .mc_init = &rv515_mc_init, .mc_fini = &rv515_mc_fini, .wb_init = &r100_wb_init, .wb_fini = &r100_wb_fini, - .gart_enable = &r300_gart_enable, + .gart_init = &rv370_pcie_gart_init, + .gart_fini = &rv370_pcie_gart_fini, + .gart_enable = &rv370_pcie_gart_enable, .gart_disable = &rv370_pcie_gart_disable, .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, .gart_set_page = &rv370_pcie_gart_set_page, .cp_init = &r100_cp_init, .cp_fini = &r100_cp_fini, .cp_disable = &r100_cp_disable, + .cp_commit = &r100_cp_commit, .ring_start = &rv515_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .ib_test = &r100_ib_test, .irq_set = &rs600_irq_set, .irq_process = &rs600_irq_process, .get_vblank_counter = &rs600_get_vblank_counter, @@ -421,19 +485,26 @@ static struct radeon_asic r520_asic = { .init = &rv515_init, .errata = &r520_errata, .vram_info = &r520_vram_info, + .vga_set_state = &r100_vga_set_state, .gpu_reset = &rv515_gpu_reset, .mc_init = &r520_mc_init, .mc_fini = &r520_mc_fini, .wb_init = &r100_wb_init, .wb_fini = &r100_wb_fini, - .gart_enable = &r300_gart_enable, + .gart_init = &rv370_pcie_gart_init, + .gart_fini = &rv370_pcie_gart_fini, + .gart_enable = &rv370_pcie_gart_enable, .gart_disable = &rv370_pcie_gart_disable, .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, .gart_set_page = &rv370_pcie_gart_set_page, .cp_init = &r100_cp_init, .cp_fini = &r100_cp_fini, .cp_disable = &r100_cp_disable, + .cp_commit = &r100_cp_commit, .ring_start = &rv515_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .ib_test = &r100_ib_test, .irq_set = &rs600_irq_set, .irq_process = &rs600_irq_process, .get_vblank_counter = &rs600_get_vblank_counter, @@ -452,9 +523,130 @@ static struct radeon_asic r520_asic = { }; /* - * r600,rv610,rv630,rv620,rv635,rv670,rs780,rv770,rv730,rv710 + * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 */ +int r600_init(struct radeon_device *rdev); +void r600_fini(struct radeon_device *rdev); +int r600_suspend(struct radeon_device *rdev); +int r600_resume(struct radeon_device *rdev); +void r600_vga_set_state(struct radeon_device *rdev, bool state); +int r600_wb_init(struct radeon_device *rdev); +void r600_wb_fini(struct radeon_device *rdev); +void r600_cp_commit(struct radeon_device *rdev); +void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); +int r600_cs_parse(struct radeon_cs_parser *p); +void r600_fence_ring_emit(struct radeon_device *rdev, + struct radeon_fence *fence); +int r600_copy_dma(struct radeon_device *rdev, + uint64_t src_offset, + uint64_t dst_offset, + unsigned num_pages, + struct radeon_fence *fence); +int r600_irq_process(struct radeon_device *rdev); +int r600_irq_set(struct radeon_device *rdev); +int r600_gpu_reset(struct radeon_device *rdev); +int r600_set_surface_reg(struct radeon_device *rdev, int reg, + uint32_t tiling_flags, uint32_t pitch, + uint32_t offset, uint32_t obj_size); +int r600_clear_surface_reg(struct radeon_device *rdev, int reg); +void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); +int r600_ib_test(struct radeon_device *rdev); +int r600_ring_test(struct radeon_device *rdev); +int r600_copy_blit(struct radeon_device *rdev, + uint64_t src_offset, uint64_t dst_offset, + unsigned num_pages, struct radeon_fence *fence); + +static struct radeon_asic r600_asic = { + .errata = NULL, + .init = &r600_init, + .fini = &r600_fini, + .suspend = &r600_suspend, + .resume = &r600_resume, + .cp_commit = &r600_cp_commit, + .vram_info = NULL, + .vga_set_state = &r600_vga_set_state, + .gpu_reset = &r600_gpu_reset, + .mc_init = NULL, + .mc_fini = NULL, + .wb_init = &r600_wb_init, + .wb_fini = &r600_wb_fini, + .gart_enable = NULL, + .gart_disable = NULL, + .gart_tlb_flush = &r600_pcie_gart_tlb_flush, + .gart_set_page = &rs600_gart_set_page, + .cp_init = NULL, + .cp_fini = NULL, + .cp_disable = NULL, + .ring_start = NULL, + .ring_test = &r600_ring_test, + .ring_ib_execute = &r600_ring_ib_execute, + .ib_test = &r600_ib_test, + .irq_set = &r600_irq_set, + .irq_process = &r600_irq_process, + .fence_ring_emit = &r600_fence_ring_emit, + .cs_parse = &r600_cs_parse, + .copy_blit = &r600_copy_blit, + .copy_dma = &r600_copy_blit, + .copy = &r600_copy_blit, + .set_engine_clock = &radeon_atom_set_engine_clock, + .set_memory_clock = &radeon_atom_set_memory_clock, + .set_pcie_lanes = NULL, + .set_clock_gating = &radeon_atom_set_clock_gating, + .set_surface_reg = r600_set_surface_reg, + .clear_surface_reg = r600_clear_surface_reg, + .bandwidth_update = &r520_bandwidth_update, +}; + +/* + * rv770,rv730,rv710,rv740 + */ +int rv770_init(struct radeon_device *rdev); +void rv770_fini(struct radeon_device *rdev); +int rv770_suspend(struct radeon_device *rdev); +int rv770_resume(struct radeon_device *rdev); +int rv770_gpu_reset(struct radeon_device *rdev); + +static struct radeon_asic rv770_asic = { + .errata = NULL, + .init = &rv770_init, + .fini = &rv770_fini, + .suspend = &rv770_suspend, + .resume = &rv770_resume, + .cp_commit = &r600_cp_commit, + .vram_info = NULL, + .gpu_reset = &rv770_gpu_reset, + .vga_set_state = &r600_vga_set_state, + .mc_init = NULL, + .mc_fini = NULL, + .wb_init = &r600_wb_init, + .wb_fini = &r600_wb_fini, + .gart_enable = NULL, + .gart_disable = NULL, + .gart_tlb_flush = &r600_pcie_gart_tlb_flush, + .gart_set_page = &rs600_gart_set_page, + .cp_init = NULL, + .cp_fini = NULL, + .cp_disable = NULL, + .ring_start = NULL, + .ring_test = &r600_ring_test, + .ring_ib_execute = &r600_ring_ib_execute, + .ib_test = &r600_ib_test, + .irq_set = &r600_irq_set, + .irq_process = &r600_irq_process, + .fence_ring_emit = &r600_fence_ring_emit, + .cs_parse = &r600_cs_parse, + .copy_blit = &r600_copy_blit, + .copy_dma = &r600_copy_blit, + .copy = &r600_copy_blit, + .set_engine_clock = &radeon_atom_set_engine_clock, + .set_memory_clock = &radeon_atom_set_memory_clock, + .set_pcie_lanes = NULL, + .set_clock_gating = &radeon_atom_set_clock_gating, + .set_surface_reg = r600_set_surface_reg, + .clear_surface_reg = r600_clear_surface_reg, + .bandwidth_update = &r520_bandwidth_update, +}; #endif diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index fcfe5c02d744..743742128307 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -104,7 +104,7 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev, uint32_t supported_device, int *connector_type, struct radeon_i2c_bus_rec *i2c_bus, - uint8_t *line_mux) + uint16_t *line_mux) { /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ @@ -143,20 +143,31 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev, return false; } - /* some BIOSes seem to report DAC on HDMI - they hurt me with their lies */ - if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) || - (*connector_type == DRM_MODE_CONNECTOR_HDMIB)) { - if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { - return false; - } - } - /* ASUS HD 3600 XT board lists the DVI port as HDMI */ if ((dev->pdev->device == 0x9598) && (dev->pdev->subsystem_vendor == 0x1043) && (dev->pdev->subsystem_device == 0x01da)) { - if (*connector_type == DRM_MODE_CONNECTOR_HDMIB) { - *connector_type = DRM_MODE_CONNECTOR_DVID; + if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { + *connector_type = DRM_MODE_CONNECTOR_DVII; + } + } + + /* ASUS HD 3450 board lists the DVI port as HDMI */ + if ((dev->pdev->device == 0x95C5) && + (dev->pdev->subsystem_vendor == 0x1043) && + (dev->pdev->subsystem_device == 0x01e2)) { + if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { + *connector_type = DRM_MODE_CONNECTOR_DVII; + } + } + + /* some BIOSes seem to report DAC on HDMI - usually this is a board with + * HDMI + VGA reporting as HDMI + */ + if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { + if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { + *connector_type = DRM_MODE_CONNECTOR_VGA; + *line_mux = 0; } } @@ -192,11 +203,11 @@ const int object_connector_convert[] = { DRM_MODE_CONNECTOR_Composite, DRM_MODE_CONNECTOR_SVIDEO, DRM_MODE_CONNECTOR_Unknown, + DRM_MODE_CONNECTOR_Unknown, DRM_MODE_CONNECTOR_9PinDIN, DRM_MODE_CONNECTOR_Unknown, DRM_MODE_CONNECTOR_HDMIA, DRM_MODE_CONNECTOR_HDMIB, - DRM_MODE_CONNECTOR_HDMIB, DRM_MODE_CONNECTOR_LVDS, DRM_MODE_CONNECTOR_9PinDIN, DRM_MODE_CONNECTOR_Unknown, @@ -218,7 +229,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) ATOM_OBJECT_HEADER *obj_header; int i, j, path_size, device_support; int connector_type; - uint16_t igp_lane_info; + uint16_t igp_lane_info, conn_id; bool linkb; struct radeon_i2c_bus_rec ddc_bus; @@ -370,10 +381,6 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) && record-> ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { - DRM_ERROR - ("record type %d\n", - record-> - ucRecordType); switch (record-> ucRecordType) { case ATOM_I2C_RECORD_TYPE: @@ -409,9 +416,15 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) else ddc_bus = radeon_lookup_gpio(dev, line_mux); + conn_id = le16_to_cpu(path->usConnObjectId); + + if (!radeon_atom_apply_quirks + (dev, le16_to_cpu(path->usDeviceTag), &connector_type, + &ddc_bus, &conn_id)) + continue; + radeon_add_atom_connector(dev, - le16_to_cpu(path-> - usConnObjectId), + conn_id, le16_to_cpu(path-> usDeviceTag), connector_type, &ddc_bus, @@ -427,7 +440,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) struct bios_connector { bool valid; - uint8_t line_mux; + uint16_t line_mux; uint16_t devices; int connector_type; struct radeon_i2c_bus_rec ddc_bus; @@ -471,11 +484,6 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct continue; } - if (i == ATOM_DEVICE_TV1_INDEX) { - DRM_DEBUG("Skipping TV Out\n"); - continue; - } - bios_connectors[i].connector_type = supported_devices_connector_convert[ci.sucConnectorInfo. sbfAccess. @@ -711,9 +719,8 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) return false; } -struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct - radeon_encoder - *encoder) +bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, + struct radeon_encoder_int_tmds *tmds) { struct drm_device *dev = encoder->base.dev; struct radeon_device *rdev = dev->dev_private; @@ -724,7 +731,6 @@ struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct uint8_t frev, crev; uint16_t maxfreq; int i; - struct radeon_encoder_int_tmds *tmds = NULL; atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); @@ -734,12 +740,6 @@ struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct data_offset); if (tmds_info) { - tmds = - kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); - - if (!tmds) - return NULL; - maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); for (i = 0; i < 4; i++) { tmds->tmds_pll[i].freq = @@ -765,8 +765,9 @@ struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct break; } } + return true; } - return tmds; + return false; } union lvds_info { @@ -858,6 +859,72 @@ radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) return p_dac; } +bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, + SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, + int32_t *pixel_clock) +{ + struct radeon_mode_info *mode_info = &rdev->mode_info; + ATOM_ANALOG_TV_INFO *tv_info; + ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; + ATOM_DTD_FORMAT *dtd_timings; + int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); + u8 frev, crev; + uint16_t data_offset; + + atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset); + + switch (crev) { + case 1: + tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); + if (index > MAX_SUPPORTED_TV_TIMING) + return false; + + crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); + crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); + crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); + crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); + + crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); + crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); + crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); + crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); + + crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo; + + crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight); + crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft); + crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom); + crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop); + *pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; + + if (index == 1) { + /* PAL timings appear to have wrong values for totals */ + crtc_timing->usH_Total -= 1; + crtc_timing->usV_Total -= 1; + } + break; + case 2: + tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); + if (index > MAX_SUPPORTED_TV_TIMING_V1_2) + return false; + + dtd_timings = &tv_info_v1_2->aModeTimings[index]; + crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time); + crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive); + crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset); + crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth); + crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time); + crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive); + crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset); + crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth); + + crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); + *pixel_clock = le16_to_cpu(dtd_timings->usPixClk) * 10; + break; + } + return true; +} + struct radeon_encoder_tv_dac * radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) { @@ -948,10 +1015,10 @@ void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) uint32_t bios_2_scratch, bios_6_scratch; if (rdev->family >= CHIP_R600) { - bios_2_scratch = RREG32(R600_BIOS_0_SCRATCH); + bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); } else { - bios_2_scratch = RREG32(RADEON_BIOS_0_SCRATCH); + bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); } @@ -971,6 +1038,34 @@ void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) } +void radeon_save_bios_scratch_regs(struct radeon_device *rdev) +{ + uint32_t scratch_reg; + int i; + + if (rdev->family >= CHIP_R600) + scratch_reg = R600_BIOS_0_SCRATCH; + else + scratch_reg = RADEON_BIOS_0_SCRATCH; + + for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) + rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); +} + +void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) +{ + uint32_t scratch_reg; + int i; + + if (rdev->family >= CHIP_R600) + scratch_reg = R600_BIOS_0_SCRATCH; + else + scratch_reg = RADEON_BIOS_0_SCRATCH; + + for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) + WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); +} + void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) { struct drm_device *dev = encoder->dev; diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c index a37cbce53181..152eef13197a 100644 --- a/drivers/gpu/drm/radeon/radeon_clocks.c +++ b/drivers/gpu/drm/radeon/radeon_clocks.c @@ -102,10 +102,12 @@ void radeon_get_clock_info(struct drm_device *dev) p1pll->reference_div = 12; if (p2pll->reference_div < 2) p2pll->reference_div = 12; - if (spll->reference_div < 2) - spll->reference_div = - RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & - RADEON_M_SPLL_REF_DIV_MASK; + if (rdev->family < CHIP_RS600) { + if (spll->reference_div < 2) + spll->reference_div = + RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & + RADEON_M_SPLL_REF_DIV_MASK; + } if (mpll->reference_div < 2) mpll->reference_div = spll->reference_div; } else { diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index 2a027e00762a..748265a105b3 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c @@ -863,8 +863,10 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder int tmp, i; struct radeon_encoder_lvds *lvds = NULL; - if (rdev->bios == NULL) - return radeon_legacy_get_lvds_info_from_regs(rdev); + if (rdev->bios == NULL) { + lvds = radeon_legacy_get_lvds_info_from_regs(rdev); + goto out; + } lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); @@ -965,11 +967,13 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder lvds->native_mode.flags = 0; } } - encoder->native_mode = lvds->native_mode; } else { DRM_INFO("No panel info found in BIOS\n"); - return radeon_legacy_get_lvds_info_from_regs(rdev); + lvds = radeon_legacy_get_lvds_info_from_regs(rdev); } +out: + if (lvds) + encoder->native_mode = lvds->native_mode; return lvds; } @@ -994,48 +998,37 @@ static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RS480 */ }; -static struct radeon_encoder_int_tmds - *radeon_legacy_get_tmds_info_from_table(struct radeon_device *rdev) +bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, + struct radeon_encoder_int_tmds *tmds) { + struct drm_device *dev = encoder->base.dev; + struct radeon_device *rdev = dev->dev_private; int i; - struct radeon_encoder_int_tmds *tmds = NULL; - - tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); - - if (!tmds) - return NULL; for (i = 0; i < 4; i++) { tmds->tmds_pll[i].value = - default_tmds_pll[rdev->family][i].value; + default_tmds_pll[rdev->family][i].value; tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; } - return tmds; + return true; } -struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct - radeon_encoder - *encoder) +bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, + struct radeon_encoder_int_tmds *tmds) { struct drm_device *dev = encoder->base.dev; struct radeon_device *rdev = dev->dev_private; uint16_t tmds_info; int i, n; uint8_t ver; - struct radeon_encoder_int_tmds *tmds = NULL; if (rdev->bios == NULL) - return radeon_legacy_get_tmds_info_from_table(rdev); + return false; tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); if (tmds_info) { - tmds = - kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); - - if (!tmds) - return NULL; ver = RBIOS8(tmds_info); DRM_INFO("DFP table revision: %d\n", ver); @@ -1073,6 +1066,23 @@ struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct } } else DRM_INFO("No TMDS info found in BIOS\n"); + return true; +} + +struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct radeon_encoder *encoder) +{ + struct radeon_encoder_int_tmds *tmds = NULL; + bool ret; + + tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); + + if (!tmds) + return NULL; + + ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds); + if (ret == false) + radeon_legacy_get_tmds_info_from_table(encoder, tmds); + return tmds; } diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index 70ede6a52d4e..af1d551f1a8f 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c @@ -28,6 +28,7 @@ #include "drm_crtc_helper.h" #include "radeon_drm.h" #include "radeon.h" +#include "atom.h" extern void radeon_combios_connected_scratch_regs(struct drm_connector *connector, @@ -38,6 +39,15 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector, struct drm_encoder *encoder, bool connected); +static void radeon_property_change_mode(struct drm_encoder *encoder) +{ + struct drm_crtc *crtc = encoder->crtc; + + if (crtc && crtc->enabled) { + drm_crtc_helper_set_mode(crtc, &crtc->mode, + crtc->x, crtc->y, crtc->fb); + } +} static void radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_connector_status status) { @@ -77,6 +87,27 @@ radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_c } } +struct drm_encoder *radeon_find_encoder(struct drm_connector *connector, int encoder_type) +{ + struct drm_mode_object *obj; + struct drm_encoder *encoder; + int i; + + for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { + if (connector->encoder_ids[i] == 0) + break; + + obj = drm_mode_object_find(connector->dev, connector->encoder_ids[i], DRM_MODE_OBJECT_ENCODER); + if (!obj) + continue; + + encoder = obj_to_encoder(obj); + if (encoder->encoder_type == encoder_type) + return encoder; + } + return NULL; +} + struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector) { int enc_id = connector->encoder_ids[0]; @@ -94,6 +125,53 @@ struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector) return NULL; } +/* + * radeon_connector_analog_encoder_conflict_solve + * - search for other connectors sharing this encoder + * if priority is true, then set them disconnected if this is connected + * if priority is false, set us disconnected if they are connected + */ +static enum drm_connector_status +radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector, + struct drm_encoder *encoder, + enum drm_connector_status current_status, + bool priority) +{ + struct drm_device *dev = connector->dev; + struct drm_connector *conflict; + int i; + + list_for_each_entry(conflict, &dev->mode_config.connector_list, head) { + if (conflict == connector) + continue; + + for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { + if (conflict->encoder_ids[i] == 0) + break; + + /* if the IDs match */ + if (conflict->encoder_ids[i] == encoder->base.id) { + if (conflict->status != connector_status_connected) + continue; + + if (priority == true) { + DRM_INFO("1: conflicting encoders switching off %s\n", drm_get_connector_name(conflict)); + DRM_INFO("in favor of %s\n", drm_get_connector_name(connector)); + conflict->status = connector_status_disconnected; + radeon_connector_update_scratch_regs(conflict, connector_status_disconnected); + } else { + DRM_INFO("2: conflicting encoders switching off %s\n", drm_get_connector_name(connector)); + DRM_INFO("in favor of %s\n", drm_get_connector_name(conflict)); + current_status = connector_status_disconnected; + } + break; + } + } + } + return current_status; + +} + static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encoder) { struct drm_device *dev = encoder->dev; @@ -126,12 +204,171 @@ static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encode return mode; } +static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_connector *connector) +{ + struct drm_device *dev = encoder->dev; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct drm_display_mode *mode = NULL; + struct radeon_native_mode *native_mode = &radeon_encoder->native_mode; + int i; + struct mode_size { + int w; + int h; + } common_modes[17] = { + { 640, 480}, + { 720, 480}, + { 800, 600}, + { 848, 480}, + {1024, 768}, + {1152, 768}, + {1280, 720}, + {1280, 800}, + {1280, 854}, + {1280, 960}, + {1280, 1024}, + {1440, 900}, + {1400, 1050}, + {1680, 1050}, + {1600, 1200}, + {1920, 1080}, + {1920, 1200} + }; + + for (i = 0; i < 17; i++) { + if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { + if (common_modes[i].w > native_mode->panel_xres || + common_modes[i].h > native_mode->panel_yres || + (common_modes[i].w == native_mode->panel_xres && + common_modes[i].h == native_mode->panel_yres)) + continue; + } + if (common_modes[i].w < 320 || common_modes[i].h < 200) + continue; + + mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false); + drm_mode_probed_add(connector, mode); + } +} + int radeon_connector_set_property(struct drm_connector *connector, struct drm_property *property, uint64_t val) { + struct drm_device *dev = connector->dev; + struct radeon_device *rdev = dev->dev_private; + struct drm_encoder *encoder; + struct radeon_encoder *radeon_encoder; + + if (property == rdev->mode_info.coherent_mode_property) { + struct radeon_encoder_atom_dig *dig; + + /* need to find digital encoder on connector */ + encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); + if (!encoder) + return 0; + + radeon_encoder = to_radeon_encoder(encoder); + + if (!radeon_encoder->enc_priv) + return 0; + + dig = radeon_encoder->enc_priv; + dig->coherent_mode = val ? true : false; + radeon_property_change_mode(&radeon_encoder->base); + } + + if (property == rdev->mode_info.tv_std_property) { + encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TVDAC); + if (!encoder) { + encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_DAC); + } + + if (!encoder) + return 0; + + radeon_encoder = to_radeon_encoder(encoder); + if (!radeon_encoder->enc_priv) + return 0; + if (rdev->is_atom_bios) { + struct radeon_encoder_atom_dac *dac_int; + dac_int = radeon_encoder->enc_priv; + dac_int->tv_std = val; + } else { + struct radeon_encoder_tv_dac *dac_int; + dac_int = radeon_encoder->enc_priv; + dac_int->tv_std = val; + } + radeon_property_change_mode(&radeon_encoder->base); + } + + if (property == rdev->mode_info.load_detect_property) { + struct radeon_connector *radeon_connector = + to_radeon_connector(connector); + + if (val == 0) + radeon_connector->dac_load_detect = false; + else + radeon_connector->dac_load_detect = true; + } + + if (property == rdev->mode_info.tmds_pll_property) { + struct radeon_encoder_int_tmds *tmds = NULL; + bool ret = false; + /* need to find digital encoder on connector */ + encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); + if (!encoder) + return 0; + + radeon_encoder = to_radeon_encoder(encoder); + + tmds = radeon_encoder->enc_priv; + if (!tmds) + return 0; + + if (val == 0) { + if (rdev->is_atom_bios) + ret = radeon_atombios_get_tmds_info(radeon_encoder, tmds); + else + ret = radeon_legacy_get_tmds_info_from_combios(radeon_encoder, tmds); + } + if (val == 1 || ret == false) { + radeon_legacy_get_tmds_info_from_table(radeon_encoder, tmds); + } + radeon_property_change_mode(&radeon_encoder->base); + } + return 0; } +static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_native_mode *native_mode = &radeon_encoder->native_mode; + + /* Try to get native mode details from EDID if necessary */ + if (!native_mode->dotclock) { + struct drm_display_mode *t, *mode; + + list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { + if (mode->hdisplay == native_mode->panel_xres && + mode->vdisplay == native_mode->panel_yres) { + native_mode->hblank = mode->htotal - mode->hdisplay; + native_mode->hoverplus = mode->hsync_start - mode->hdisplay; + native_mode->hsync_width = mode->hsync_end - mode->hsync_start; + native_mode->vblank = mode->vtotal - mode->vdisplay; + native_mode->voverplus = mode->vsync_start - mode->vdisplay; + native_mode->vsync_width = mode->vsync_end - mode->vsync_start; + native_mode->dotclock = mode->clock; + DRM_INFO("Determined LVDS native mode details from EDID\n"); + break; + } + } + } + if (!native_mode->dotclock) { + DRM_INFO("No LVDS native mode details, disabling RMX\n"); + radeon_encoder->rmx_type = RMX_OFF; + } +} static int radeon_lvds_get_modes(struct drm_connector *connector) { @@ -143,6 +380,12 @@ static int radeon_lvds_get_modes(struct drm_connector *connector) if (radeon_connector->ddc_bus) { ret = radeon_ddc_get_modes(radeon_connector); if (ret > 0) { + encoder = radeon_best_single_encoder(connector); + if (encoder) { + radeon_fixup_lvds_native_mode(encoder, connector); + /* add scaled modes */ + radeon_add_common_modes(encoder, connector); + } return ret; } } @@ -156,7 +399,10 @@ static int radeon_lvds_get_modes(struct drm_connector *connector) if (mode) { ret = 1; drm_mode_probed_add(connector, mode); + /* add scaled modes */ + radeon_add_common_modes(encoder, connector); } + return ret; } @@ -186,6 +432,42 @@ static void radeon_connector_destroy(struct drm_connector *connector) kfree(connector); } +static int radeon_lvds_set_property(struct drm_connector *connector, + struct drm_property *property, + uint64_t value) +{ + struct drm_device *dev = connector->dev; + struct radeon_encoder *radeon_encoder; + enum radeon_rmx_type rmx_type; + + DRM_DEBUG("\n"); + if (property != dev->mode_config.scaling_mode_property) + return 0; + + if (connector->encoder) + radeon_encoder = to_radeon_encoder(connector->encoder); + else { + struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; + radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector)); + } + + switch (value) { + case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; + case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; + case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; + default: + case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; + } + if (radeon_encoder->rmx_type == rmx_type) + return 0; + + radeon_encoder->rmx_type = rmx_type; + + radeon_property_change_mode(&radeon_encoder->base); + return 0; +} + + struct drm_connector_helper_funcs radeon_lvds_connector_helper_funcs = { .get_modes = radeon_lvds_get_modes, .mode_valid = radeon_lvds_mode_valid, @@ -197,7 +479,7 @@ struct drm_connector_funcs radeon_lvds_connector_funcs = { .detect = radeon_lvds_detect, .fill_modes = drm_helper_probe_single_connector_modes, .destroy = radeon_connector_destroy, - .set_property = radeon_connector_set_property, + .set_property = radeon_lvds_set_property, }; static int radeon_vga_get_modes(struct drm_connector *connector) @@ -213,7 +495,6 @@ static int radeon_vga_get_modes(struct drm_connector *connector) static int radeon_vga_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { - return MODE_OK; } @@ -225,22 +506,24 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect bool dret; enum drm_connector_status ret = connector_status_disconnected; + encoder = radeon_best_single_encoder(connector); + if (!encoder) + ret = connector_status_disconnected; + radeon_i2c_do_lock(radeon_connector, 1); dret = radeon_ddc_probe(radeon_connector); radeon_i2c_do_lock(radeon_connector, 0); if (dret) ret = connector_status_connected; else { - /* if EDID fails to a load detect */ - encoder = radeon_best_single_encoder(connector); - if (!encoder) - ret = connector_status_disconnected; - else { + if (radeon_connector->dac_load_detect) { encoder_funcs = encoder->helper_private; ret = encoder_funcs->detect(encoder, connector); } } + if (ret == connector_status_connected) + ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true); radeon_connector_update_scratch_regs(connector, ret); return ret; } @@ -259,21 +542,97 @@ struct drm_connector_funcs radeon_vga_connector_funcs = { .set_property = radeon_connector_set_property, }; +static int radeon_tv_get_modes(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct radeon_device *rdev = dev->dev_private; + struct drm_display_mode *tv_mode; + struct drm_encoder *encoder; + + encoder = radeon_best_single_encoder(connector); + if (!encoder) + return 0; + + /* avivo chips can scale any mode */ + if (rdev->family >= CHIP_RS600) + /* add scaled modes */ + radeon_add_common_modes(encoder, connector); + else { + /* only 800x600 is supported right now on pre-avivo chips */ + tv_mode = drm_cvt_mode(dev, 800, 600, 60, false, false); + tv_mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; + drm_mode_probed_add(connector, tv_mode); + } + return 1; +} + +static int radeon_tv_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + return MODE_OK; +} + +static enum drm_connector_status radeon_tv_detect(struct drm_connector *connector) +{ + struct drm_encoder *encoder; + struct drm_encoder_helper_funcs *encoder_funcs; + struct radeon_connector *radeon_connector = to_radeon_connector(connector); + enum drm_connector_status ret = connector_status_disconnected; + + if (!radeon_connector->dac_load_detect) + return ret; + + encoder = radeon_best_single_encoder(connector); + if (!encoder) + ret = connector_status_disconnected; + else { + encoder_funcs = encoder->helper_private; + ret = encoder_funcs->detect(encoder, connector); + } + if (ret == connector_status_connected) + ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, false); + radeon_connector_update_scratch_regs(connector, ret); + return ret; +} + +struct drm_connector_helper_funcs radeon_tv_connector_helper_funcs = { + .get_modes = radeon_tv_get_modes, + .mode_valid = radeon_tv_mode_valid, + .best_encoder = radeon_best_single_encoder, +}; + +struct drm_connector_funcs radeon_tv_connector_funcs = { + .dpms = drm_helper_connector_dpms, + .detect = radeon_tv_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = radeon_connector_destroy, + .set_property = radeon_connector_set_property, +}; + static int radeon_dvi_get_modes(struct drm_connector *connector) { struct radeon_connector *radeon_connector = to_radeon_connector(connector); int ret; ret = radeon_ddc_get_modes(radeon_connector); - /* reset scratch regs here since radeon_dvi_detect doesn't check digital bit */ - radeon_connector_update_scratch_regs(connector, connector_status_connected); return ret; } +/* + * DVI is complicated + * Do a DDC probe, if DDC probe passes, get the full EDID so + * we can do analog/digital monitor detection at this point. + * If the monitor is an analog monitor or we got no DDC, + * we need to find the DAC encoder object for this connector. + * If we got no DDC, we do load detection on the DAC encoder object. + * If we got analog DDC or load detection passes on the DAC encoder + * we have to check if this analog encoder is shared with anyone else (TV) + * if its shared we have to set the other connector to disconnected. + */ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connector) { struct radeon_connector *radeon_connector = to_radeon_connector(connector); - struct drm_encoder *encoder; + struct drm_encoder *encoder = NULL; struct drm_encoder_helper_funcs *encoder_funcs; struct drm_mode_object *obj; int i; @@ -283,9 +642,29 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect radeon_i2c_do_lock(radeon_connector, 1); dret = radeon_ddc_probe(radeon_connector); radeon_i2c_do_lock(radeon_connector, 0); - if (dret) - ret = connector_status_connected; - else { + if (dret) { + radeon_i2c_do_lock(radeon_connector, 1); + radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); + radeon_i2c_do_lock(radeon_connector, 0); + + if (!radeon_connector->edid) { + DRM_ERROR("DDC responded but not EDID found for %s\n", + drm_get_connector_name(connector)); + } else { + radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); + + /* if this isn't a digital monitor + then we need to make sure we don't have any + TV conflicts */ + ret = connector_status_connected; + } + } + + if ((ret == connector_status_connected) && (radeon_connector->use_digital == true)) + goto out; + + /* find analog encoder */ + if (radeon_connector->dac_load_detect) { for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { if (connector->encoder_ids[i] == 0) break; @@ -300,15 +679,23 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect encoder_funcs = encoder->helper_private; if (encoder_funcs->detect) { - ret = encoder_funcs->detect(encoder, connector); - if (ret == connector_status_connected) { - radeon_connector->use_digital = 0; - break; + if (ret != connector_status_connected) { + ret = encoder_funcs->detect(encoder, connector); + if (ret == connector_status_connected) { + radeon_connector->use_digital = false; + } } + break; } } } + if ((ret == connector_status_connected) && (radeon_connector->use_digital == false) && + encoder) { + ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true); + } + +out: /* updated in get modes as well since we need to know if it's analog or digital */ radeon_connector_update_scratch_regs(connector, ret); return ret; @@ -332,7 +719,7 @@ struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector) encoder = obj_to_encoder(obj); - if (radeon_connector->use_digital) { + if (radeon_connector->use_digital == true) { if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) return encoder; } else { @@ -379,16 +766,14 @@ radeon_add_atom_connector(struct drm_device *dev, bool linkb, uint32_t igp_lane_info) { + struct radeon_device *rdev = dev->dev_private; struct drm_connector *connector; struct radeon_connector *radeon_connector; struct radeon_connector_atom_dig *radeon_dig_connector; uint32_t subpixel_order = SubPixelNone; /* fixme - tv/cv/din */ - if ((connector_type == DRM_MODE_CONNECTOR_Unknown) || - (connector_type == DRM_MODE_CONNECTOR_SVIDEO) || - (connector_type == DRM_MODE_CONNECTOR_Composite) || - (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) + if (connector_type == DRM_MODE_CONNECTOR_Unknown) return; /* see if we already added it */ @@ -417,6 +802,9 @@ radeon_add_atom_connector(struct drm_device *dev, if (!radeon_connector->ddc_bus) goto failed; } + drm_connector_attach_property(&radeon_connector->base, + rdev->mode_info.load_detect_property, + 1); break; case DRM_MODE_CONNECTOR_DVIA: drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); @@ -426,6 +814,9 @@ radeon_add_atom_connector(struct drm_device *dev, if (!radeon_connector->ddc_bus) goto failed; } + drm_connector_attach_property(&radeon_connector->base, + rdev->mode_info.load_detect_property, + 1); break; case DRM_MODE_CONNECTOR_DVII: case DRM_MODE_CONNECTOR_DVID: @@ -443,6 +834,12 @@ radeon_add_atom_connector(struct drm_device *dev, goto failed; } subpixel_order = SubPixelHorizontalRGB; + drm_connector_attach_property(&radeon_connector->base, + rdev->mode_info.coherent_mode_property, + 1); + drm_connector_attach_property(&radeon_connector->base, + rdev->mode_info.load_detect_property, + 1); break; case DRM_MODE_CONNECTOR_HDMIA: case DRM_MODE_CONNECTOR_HDMIB: @@ -459,6 +856,9 @@ radeon_add_atom_connector(struct drm_device *dev, if (!radeon_connector->ddc_bus) goto failed; } + drm_connector_attach_property(&radeon_connector->base, + rdev->mode_info.coherent_mode_property, + 1); subpixel_order = SubPixelHorizontalRGB; break; case DRM_MODE_CONNECTOR_DisplayPort: @@ -480,6 +880,13 @@ radeon_add_atom_connector(struct drm_device *dev, case DRM_MODE_CONNECTOR_SVIDEO: case DRM_MODE_CONNECTOR_Composite: case DRM_MODE_CONNECTOR_9PinDIN: + if (radeon_tv == 1) { + drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); + drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); + } + drm_connector_attach_property(&radeon_connector->base, + rdev->mode_info.load_detect_property, + 1); break; case DRM_MODE_CONNECTOR_LVDS: radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); @@ -495,6 +902,10 @@ radeon_add_atom_connector(struct drm_device *dev, if (!radeon_connector->ddc_bus) goto failed; } + drm_mode_create_scaling_mode_property(dev); + drm_connector_attach_property(&radeon_connector->base, + dev->mode_config.scaling_mode_property, + DRM_MODE_SCALE_FULLSCREEN); subpixel_order = SubPixelHorizontalRGB; break; } @@ -517,15 +928,13 @@ radeon_add_legacy_connector(struct drm_device *dev, int connector_type, struct radeon_i2c_bus_rec *i2c_bus) { + struct radeon_device *rdev = dev->dev_private; struct drm_connector *connector; struct radeon_connector *radeon_connector; uint32_t subpixel_order = SubPixelNone; /* fixme - tv/cv/din */ - if ((connector_type == DRM_MODE_CONNECTOR_Unknown) || - (connector_type == DRM_MODE_CONNECTOR_SVIDEO) || - (connector_type == DRM_MODE_CONNECTOR_Composite) || - (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) + if (connector_type == DRM_MODE_CONNECTOR_Unknown) return; /* see if we already added it */ @@ -554,6 +963,9 @@ radeon_add_legacy_connector(struct drm_device *dev, if (!radeon_connector->ddc_bus) goto failed; } + drm_connector_attach_property(&radeon_connector->base, + rdev->mode_info.load_detect_property, + 1); break; case DRM_MODE_CONNECTOR_DVIA: drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); @@ -563,6 +975,9 @@ radeon_add_legacy_connector(struct drm_device *dev, if (!radeon_connector->ddc_bus) goto failed; } + drm_connector_attach_property(&radeon_connector->base, + rdev->mode_info.load_detect_property, + 1); break; case DRM_MODE_CONNECTOR_DVII: case DRM_MODE_CONNECTOR_DVID: @@ -572,12 +987,22 @@ radeon_add_legacy_connector(struct drm_device *dev, radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); if (!radeon_connector->ddc_bus) goto failed; + drm_connector_attach_property(&radeon_connector->base, + rdev->mode_info.load_detect_property, + 1); } subpixel_order = SubPixelHorizontalRGB; break; case DRM_MODE_CONNECTOR_SVIDEO: case DRM_MODE_CONNECTOR_Composite: case DRM_MODE_CONNECTOR_9PinDIN: + if (radeon_tv == 1) { + drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); + drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); + drm_connector_attach_property(&radeon_connector->base, + rdev->mode_info.load_detect_property, + 1); + } break; case DRM_MODE_CONNECTOR_LVDS: drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); @@ -587,6 +1012,9 @@ radeon_add_legacy_connector(struct drm_device *dev, if (!radeon_connector->ddc_bus) goto failed; } + drm_connector_attach_property(&radeon_connector->base, + dev->mode_config.scaling_mode_property, + DRM_MODE_SCALE_FULLSCREEN); subpixel_order = SubPixelHorizontalRGB; break; } diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c index 7a52c461145c..4f7afc79dd82 100644 --- a/drivers/gpu/drm/radeon/radeon_cp.c +++ b/drivers/gpu/drm/radeon/radeon_cp.c @@ -36,10 +36,25 @@ #include "radeon_drv.h" #include "r300_reg.h" -#include "radeon_microcode.h" - #define RADEON_FIFO_DEBUG 0 +/* Firmware Names */ +#define FIRMWARE_R100 "radeon/R100_cp.bin" +#define FIRMWARE_R200 "radeon/R200_cp.bin" +#define FIRMWARE_R300 "radeon/R300_cp.bin" +#define FIRMWARE_R420 "radeon/R420_cp.bin" +#define FIRMWARE_RS690 "radeon/RS690_cp.bin" +#define FIRMWARE_RS600 "radeon/RS600_cp.bin" +#define FIRMWARE_R520 "radeon/R520_cp.bin" + +MODULE_FIRMWARE(FIRMWARE_R100); +MODULE_FIRMWARE(FIRMWARE_R200); +MODULE_FIRMWARE(FIRMWARE_R300); +MODULE_FIRMWARE(FIRMWARE_R420); +MODULE_FIRMWARE(FIRMWARE_RS690); +MODULE_FIRMWARE(FIRMWARE_RS600); +MODULE_FIRMWARE(FIRMWARE_R520); + static int radeon_do_cleanup_cp(struct drm_device * dev); static void radeon_do_cp_start(drm_radeon_private_t * dev_priv); @@ -460,37 +475,34 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv) */ /* Load the microcode for the CP */ -static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) +static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv) { - int i; + struct platform_device *pdev; + const char *fw_name = NULL; + int err; + DRM_DEBUG("\n"); - radeon_do_wait_for_idle(dev_priv); + pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); + err = IS_ERR(pdev); + if (err) { + printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); + return -EINVAL; + } - RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) { DRM_INFO("Loading R100 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - R100_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - R100_cp_microcode[i][0]); - } + fw_name = FIRMWARE_R100; } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) { DRM_INFO("Loading R200 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - R200_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - R200_cp_microcode[i][0]); - } + fw_name = FIRMWARE_R200; } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || @@ -498,39 +510,19 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { DRM_INFO("Loading R300 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - R300_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - R300_cp_microcode[i][0]); - } + fw_name = FIRMWARE_R300; } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { DRM_INFO("Loading R400 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - R420_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - R420_cp_microcode[i][0]); - } + fw_name = FIRMWARE_R420; } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { DRM_INFO("Loading RS690/RS740 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - RS690_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - RS690_cp_microcode[i][0]); - } + fw_name = FIRMWARE_RS690; } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { DRM_INFO("Loading RS600 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - RS600_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - RS600_cp_microcode[i][0]); - } + fw_name = FIRMWARE_RS600; } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || @@ -538,11 +530,41 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) { DRM_INFO("Loading R500 Microcode\n"); - for (i = 0; i < 256; i++) { + fw_name = FIRMWARE_R520; + } + + err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev); + platform_device_unregister(pdev); + if (err) { + printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", + fw_name); + } else if (dev_priv->me_fw->size % 8) { + printk(KERN_ERR + "radeon_cp: Bogus length %zu in firmware \"%s\"\n", + dev_priv->me_fw->size, fw_name); + err = -EINVAL; + release_firmware(dev_priv->me_fw); + dev_priv->me_fw = NULL; + } + return err; +} + +static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv) +{ + const __be32 *fw_data; + int i, size; + + radeon_do_wait_for_idle(dev_priv); + + if (dev_priv->me_fw) { + size = dev_priv->me_fw->size / 4; + fw_data = (const __be32 *)&dev_priv->me_fw->data[0]; + RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); + for (i = 0; i < size; i += 2) { RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - R520_cp_microcode[i][1]); + be32_to_cpup(&fw_data[i])); RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - R520_cp_microcode[i][0]); + be32_to_cpup(&fw_data[i + 1])); } } } @@ -594,6 +616,18 @@ static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) dev_priv->cp_running = 1; + /* on r420, any DMA from CP to system memory while 2D is active + * can cause a hang. workaround is to queue a CP RESYNC token + */ + if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) { + BEGIN_RING(3); + OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1)); + OUT_RING(5); /* scratch reg 5 */ + OUT_RING(0xdeadbeef); + ADVANCE_RING(); + COMMIT_RING(); + } + BEGIN_RING(8); /* isync can only be written through cp on r5xx write it here */ OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); @@ -631,8 +665,19 @@ static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) */ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) { + RING_LOCALS; DRM_DEBUG("\n"); + /* finish the pending CP_RESYNC token */ + if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) { + BEGIN_RING(2); + OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); + OUT_RING(R300_RB3D_DC_FINISH); + ADVANCE_RING(); + COMMIT_RING(); + radeon_do_wait_for_idle(dev_priv); + } + RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); dev_priv->cp_running = 0; @@ -1495,6 +1540,14 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, radeon_set_pcigart(dev_priv, 1); } + if (!dev_priv->me_fw) { + int err = radeon_cp_init_microcode(dev_priv); + if (err) { + DRM_ERROR("Failed to load firmware!\n"); + radeon_do_cleanup_cp(dev); + return err; + } + } radeon_cp_load_microcode(dev_priv); radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); @@ -1764,6 +1817,14 @@ void radeon_do_release(struct drm_device * dev) r600_do_cleanup_cp(dev); else radeon_do_cleanup_cp(dev); + if (dev_priv->me_fw) { + release_firmware(dev_priv->me_fw); + dev_priv->me_fw = NULL; + } + if (dev_priv->pfp_fw) { + release_firmware(dev_priv->pfp_fw); + dev_priv->pfp_fw = NULL; + } } } diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index a169067efc4e..12f5990c2d2a 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c @@ -145,7 +145,7 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; size = p->chunks[i].length_dw * sizeof(uint32_t); - p->chunks[i].kdata = kzalloc(size, GFP_KERNEL); + p->chunks[i].kdata = kmalloc(size, GFP_KERNEL); if (p->chunks[i].kdata == NULL) { return -ENOMEM; } @@ -185,6 +185,7 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error) mutex_unlock(&parser->rdev->ddev->struct_mutex); } } + kfree(parser->track); kfree(parser->relocs); kfree(parser->relocs_ptr); for (i = 0; i < parser->nchunks; i++) { diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 7693f7c67bd3..daf5db780956 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -29,6 +29,7 @@ #include #include #include +#include #include "radeon_reg.h" #include "radeon.h" #include "radeon_asic.h" @@ -37,7 +38,7 @@ /* * Clear GPU surface registers. */ -static void radeon_surface_init(struct radeon_device *rdev) +void radeon_surface_init(struct radeon_device *rdev) { /* FIXME: check this out */ if (rdev->family < CHIP_R600) { @@ -56,7 +57,7 @@ static void radeon_surface_init(struct radeon_device *rdev) /* * GPU scratch registers helpers function. */ -static void radeon_scratch_init(struct radeon_device *rdev) +void radeon_scratch_init(struct radeon_device *rdev) { int i; @@ -156,16 +157,18 @@ int radeon_mc_setup(struct radeon_device *rdev) tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); rdev->mc.gtt_location = tmp; } - DRM_INFO("radeon: VRAM %uM\n", rdev->mc.real_vram_size >> 20); + rdev->mc.vram_start = rdev->mc.vram_location; + rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; + rdev->mc.gtt_start = rdev->mc.gtt_location; + rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; + DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20)); DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", - rdev->mc.vram_location, - rdev->mc.vram_location + rdev->mc.mc_vram_size - 1); - if (rdev->mc.real_vram_size != rdev->mc.mc_vram_size) - DRM_INFO("radeon: VRAM less than aperture workaround enabled\n"); - DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20); + (unsigned)rdev->mc.vram_location, + (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1)); + DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20)); DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", - rdev->mc.gtt_location, - rdev->mc.gtt_location + rdev->mc.gtt_size - 1); + (unsigned)rdev->mc.gtt_location, + (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1)); return 0; } @@ -173,7 +176,7 @@ int radeon_mc_setup(struct radeon_device *rdev) /* * GPU helpers function. */ -static bool radeon_card_posted(struct radeon_device *rdev) +bool radeon_card_posted(struct radeon_device *rdev) { uint32_t reg; @@ -205,6 +208,31 @@ static bool radeon_card_posted(struct radeon_device *rdev) } +int radeon_dummy_page_init(struct radeon_device *rdev) +{ + rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); + if (rdev->dummy_page.page == NULL) + return -ENOMEM; + rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, + 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); + if (!rdev->dummy_page.addr) { + __free_page(rdev->dummy_page.page); + rdev->dummy_page.page = NULL; + return -ENOMEM; + } + return 0; +} + +void radeon_dummy_page_fini(struct radeon_device *rdev) +{ + if (rdev->dummy_page.page == NULL) + return; + pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, + PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); + __free_page(rdev->dummy_page.page); + rdev->dummy_page.page = NULL; +} + /* * Registers accessors functions. @@ -243,6 +271,10 @@ void radeon_register_accessor_init(struct radeon_device *rdev) rdev->pll_rreg = &r100_pll_rreg; rdev->pll_wreg = &r100_pll_wreg; } + if (rdev->family >= CHIP_R420) { + rdev->mc_rreg = &r420_mc_rreg; + rdev->mc_wreg = &r420_mc_wreg; + } if (rdev->family >= CHIP_RV515) { rdev->mc_rreg = &rv515_mc_rreg; rdev->mc_wreg = &rv515_mc_wreg; @@ -289,6 +321,14 @@ int radeon_asic_init(struct radeon_device *rdev) case CHIP_RV350: case CHIP_RV380: rdev->asic = &r300_asic; + if (rdev->flags & RADEON_IS_PCIE) { + rdev->asic->gart_init = &rv370_pcie_gart_init; + rdev->asic->gart_fini = &rv370_pcie_gart_fini; + rdev->asic->gart_enable = &rv370_pcie_gart_enable; + rdev->asic->gart_disable = &rv370_pcie_gart_disable; + rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; + rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; + } break; case CHIP_R420: case CHIP_R423: @@ -323,9 +363,15 @@ int radeon_asic_init(struct radeon_device *rdev) case CHIP_RV635: case CHIP_RV670: case CHIP_RS780: + case CHIP_RS880: + rdev->asic = &r600_asic; + break; case CHIP_RV770: case CHIP_RV730: case CHIP_RV710: + case CHIP_RV740: + rdev->asic = &rv770_asic; + break; default: /* FIXME: not supported yet */ return -EINVAL; @@ -341,7 +387,6 @@ int radeon_clocks_init(struct radeon_device *rdev) { int r; - radeon_get_clock_info(rdev->ddev); r = radeon_static_clocks_init(rdev->ddev); if (r) { return r; @@ -436,10 +481,18 @@ void radeon_combios_fini(struct radeon_device *rdev) { } -int radeon_modeset_init(struct radeon_device *rdev); -void radeon_modeset_fini(struct radeon_device *rdev); - +/* if we get transitioned to only one device, tak VGA back */ +static unsigned int radeon_vga_set_decode(void *cookie, bool state) +{ + struct radeon_device *rdev = cookie; + radeon_vga_set_state(rdev, state); + if (state) + return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | + VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; + else + return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; +} /* * Radeon device. */ @@ -448,11 +501,12 @@ int radeon_device_init(struct radeon_device *rdev, struct pci_dev *pdev, uint32_t flags) { - int r, ret; + int r; int dma_bits; DRM_INFO("radeon: Initializing kernel modesetting.\n"); rdev->shutdown = false; + rdev->dev = &pdev->dev; rdev->ddev = ddev; rdev->pdev = pdev; rdev->flags = flags; @@ -461,37 +515,47 @@ int radeon_device_init(struct radeon_device *rdev, rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; rdev->gpu_lockup = false; + rdev->accel_working = false; /* mutex initialization are all done here so we * can recall function without having locking issues */ mutex_init(&rdev->cs_mutex); mutex_init(&rdev->ib_pool.mutex); mutex_init(&rdev->cp.mutex); rwlock_init(&rdev->fence_drv.lock); + INIT_LIST_HEAD(&rdev->gem.objects); + + /* Set asic functions */ + r = radeon_asic_init(rdev); + if (r) { + return r; + } if (radeon_agpmode == -1) { rdev->flags &= ~RADEON_IS_AGP; - if (rdev->family > CHIP_RV515 || + if (rdev->family >= CHIP_RV515 || rdev->family == CHIP_RV380 || rdev->family == CHIP_RV410 || rdev->family == CHIP_R423) { DRM_INFO("Forcing AGP to PCIE mode\n"); rdev->flags |= RADEON_IS_PCIE; + rdev->asic->gart_init = &rv370_pcie_gart_init; + rdev->asic->gart_fini = &rv370_pcie_gart_fini; + rdev->asic->gart_enable = &rv370_pcie_gart_enable; + rdev->asic->gart_disable = &rv370_pcie_gart_disable; + rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; + rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; } else { DRM_INFO("Forcing AGP to PCI mode\n"); rdev->flags |= RADEON_IS_PCI; + rdev->asic->gart_init = &r100_pci_gart_init; + rdev->asic->gart_fini = &r100_pci_gart_fini; + rdev->asic->gart_enable = &r100_pci_gart_enable; + rdev->asic->gart_disable = &r100_pci_gart_disable; + rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; + rdev->asic->gart_set_page = &r100_pci_gart_set_page; } } - /* Set asic functions */ - r = radeon_asic_init(rdev); - if (r) { - return r; - } - r = radeon_init(rdev); - if (r) { - return r; - } - /* set DMA mask + need_dma32 flags. * PCIE - can handle 40-bits. * IGP - can handle 40-bits (in theory) @@ -521,156 +585,150 @@ int radeon_device_init(struct radeon_device *rdev, DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); - /* Setup errata flags */ - radeon_errata(rdev); - /* Initialize scratch registers */ - radeon_scratch_init(rdev); - /* Initialize surface registers */ - radeon_surface_init(rdev); - - /* TODO: disable VGA need to use VGA request */ - /* BIOS*/ - if (!radeon_get_bios(rdev)) { - if (ASIC_IS_AVIVO(rdev)) - return -EINVAL; - } - if (rdev->is_atom_bios) { - r = radeon_atombios_init(rdev); - if (r) { - return r; - } - } else { - r = radeon_combios_init(rdev); - if (r) { - return r; - } - } - /* Reset gpu before posting otherwise ATOM will enter infinite loop */ - if (radeon_gpu_reset(rdev)) { - /* FIXME: what do we want to do here ? */ - } - /* check if cards are posted or not */ - if (!radeon_card_posted(rdev) && rdev->bios) { - DRM_INFO("GPU not posted. posting now...\n"); - if (rdev->is_atom_bios) { - atom_asic_init(rdev->mode_info.atom_context); - } else { - radeon_combios_asic_init(rdev->ddev); - } - } - /* Initialize clocks */ - r = radeon_clocks_init(rdev); - if (r) { - return r; - } - /* Get vram informations */ - radeon_vram_info(rdev); - - /* Add an MTRR for the VRAM */ - rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, - MTRR_TYPE_WRCOMB, 1); - DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n", - rdev->mc.real_vram_size >> 20, - (unsigned)rdev->mc.aper_size >> 20); - DRM_INFO("RAM width %dbits %cDR\n", - rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); - /* Initialize memory controller (also test AGP) */ - r = radeon_mc_init(rdev); - if (r) { - return r; - } - /* Fence driver */ - r = radeon_fence_driver_init(rdev); - if (r) { - return r; - } - r = radeon_irq_kms_init(rdev); + rdev->new_init_path = false; + r = radeon_init(rdev); if (r) { return r; } - /* Memory manager */ - r = radeon_object_init(rdev); + + /* if we have > 1 VGA cards, then disable the radeon VGA resources */ + r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); if (r) { - return r; - } - /* Initialize GART (initialize after TTM so we can allocate - * memory through TTM but finalize after TTM) */ - r = radeon_gart_enable(rdev); - if (!r) { - r = radeon_gem_init(rdev); + return -EINVAL; } - /* 1M ring buffer */ - if (!r) { - r = radeon_cp_init(rdev, 1024 * 1024); - } - if (!r) { - r = radeon_wb_init(rdev); + if (!rdev->new_init_path) { + /* Setup errata flags */ + radeon_errata(rdev); + /* Initialize scratch registers */ + radeon_scratch_init(rdev); + /* Initialize surface registers */ + radeon_surface_init(rdev); + + /* BIOS*/ + if (!radeon_get_bios(rdev)) { + if (ASIC_IS_AVIVO(rdev)) + return -EINVAL; + } + if (rdev->is_atom_bios) { + r = radeon_atombios_init(rdev); + if (r) { + return r; + } + } else { + r = radeon_combios_init(rdev); + if (r) { + return r; + } + } + /* Reset gpu before posting otherwise ATOM will enter infinite loop */ + if (radeon_gpu_reset(rdev)) { + /* FIXME: what do we want to do here ? */ + } + /* check if cards are posted or not */ + if (!radeon_card_posted(rdev) && rdev->bios) { + DRM_INFO("GPU not posted. posting now...\n"); + if (rdev->is_atom_bios) { + atom_asic_init(rdev->mode_info.atom_context); + } else { + radeon_combios_asic_init(rdev->ddev); + } + } + /* Get clock & vram information */ + radeon_get_clock_info(rdev->ddev); + radeon_vram_info(rdev); + /* Initialize clocks */ + r = radeon_clocks_init(rdev); if (r) { - DRM_ERROR("radeon: failled initializing WB (%d).\n", r); return r; } - } - if (!r) { - r = radeon_ib_pool_init(rdev); + + /* Initialize memory controller (also test AGP) */ + r = radeon_mc_init(rdev); if (r) { - DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); return r; } - } - if (!r) { - r = radeon_ib_test(rdev); + /* Fence driver */ + r = radeon_fence_driver_init(rdev); if (r) { - DRM_ERROR("radeon: failled testing IB (%d).\n", r); return r; } + r = radeon_irq_kms_init(rdev); + if (r) { + return r; + } + /* Memory manager */ + r = radeon_object_init(rdev); + if (r) { + return r; + } + r = radeon_gpu_gart_init(rdev); + if (r) + return r; + /* Initialize GART (initialize after TTM so we can allocate + * memory through TTM but finalize after TTM) */ + r = radeon_gart_enable(rdev); + if (r) + return 0; + r = radeon_gem_init(rdev); + if (r) + return 0; + + /* 1M ring buffer */ + r = radeon_cp_init(rdev, 1024 * 1024); + if (r) + return 0; + r = radeon_wb_init(rdev); + if (r) + DRM_ERROR("radeon: failled initializing WB (%d).\n", r); + r = radeon_ib_pool_init(rdev); + if (r) + return 0; + r = radeon_ib_test(rdev); + if (r) + return 0; + rdev->accel_working = true; } - ret = r; - r = radeon_modeset_init(rdev); - if (r) { - return r; - } - if (!ret) { - DRM_INFO("radeon: kernel modesetting successfully initialized.\n"); - } + DRM_INFO("radeon: kernel modesetting successfully initialized.\n"); if (radeon_testing) { radeon_test_moves(rdev); } if (radeon_benchmarking) { radeon_benchmark(rdev); } - return ret; + return 0; } void radeon_device_fini(struct radeon_device *rdev) { - if (rdev == NULL || rdev->rmmio == NULL) { - return; - } DRM_INFO("radeon: finishing device.\n"); rdev->shutdown = true; /* Order matter so becarefull if you rearrange anythings */ - radeon_modeset_fini(rdev); - radeon_ib_pool_fini(rdev); - radeon_cp_fini(rdev); - radeon_wb_fini(rdev); - radeon_gem_fini(rdev); - radeon_object_fini(rdev); - /* mc_fini must be after object_fini */ - radeon_mc_fini(rdev); + if (!rdev->new_init_path) { + radeon_ib_pool_fini(rdev); + radeon_cp_fini(rdev); + radeon_wb_fini(rdev); + radeon_gpu_gart_fini(rdev); + radeon_gem_fini(rdev); + radeon_mc_fini(rdev); #if __OS_HAS_AGP - radeon_agp_fini(rdev); + radeon_agp_fini(rdev); #endif - radeon_irq_kms_fini(rdev); - radeon_fence_driver_fini(rdev); - radeon_clocks_fini(rdev); - if (rdev->is_atom_bios) { - radeon_atombios_fini(rdev); + radeon_irq_kms_fini(rdev); + vga_client_register(rdev->pdev, NULL, NULL, NULL); + radeon_fence_driver_fini(rdev); + radeon_clocks_fini(rdev); + radeon_object_fini(rdev); + if (rdev->is_atom_bios) { + radeon_atombios_fini(rdev); + } else { + radeon_combios_fini(rdev); + } + kfree(rdev->bios); + rdev->bios = NULL; } else { - radeon_combios_fini(rdev); + radeon_fini(rdev); } - kfree(rdev->bios); - rdev->bios = NULL; iounmap(rdev->rmmio); rdev->rmmio = NULL; } @@ -708,15 +766,19 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) /* wait for gpu to finish processing current batch */ radeon_fence_wait_last(rdev); - radeon_cp_disable(rdev); - radeon_gart_disable(rdev); + radeon_save_bios_scratch_regs(rdev); + if (!rdev->new_init_path) { + radeon_cp_disable(rdev); + radeon_gart_disable(rdev); + rdev->irq.sw_int = false; + radeon_irq_set(rdev); + } else { + radeon_suspend(rdev); + } /* evict remaining vram memory */ radeon_object_evict_vram(rdev); - rdev->irq.sw_int = false; - radeon_irq_set(rdev); - pci_save_state(dev->pdev); if (state.event == PM_EVENT_SUSPEND) { /* Shut down the device */ @@ -743,38 +805,43 @@ int radeon_resume_kms(struct drm_device *dev) } pci_set_master(dev->pdev); /* Reset gpu before posting otherwise ATOM will enter infinite loop */ - if (radeon_gpu_reset(rdev)) { - /* FIXME: what do we want to do here ? */ - } - /* post card */ - if (rdev->is_atom_bios) { - atom_asic_init(rdev->mode_info.atom_context); + if (!rdev->new_init_path) { + if (radeon_gpu_reset(rdev)) { + /* FIXME: what do we want to do here ? */ + } + /* post card */ + if (rdev->is_atom_bios) { + atom_asic_init(rdev->mode_info.atom_context); + } else { + radeon_combios_asic_init(rdev->ddev); + } + /* Initialize clocks */ + r = radeon_clocks_init(rdev); + if (r) { + release_console_sem(); + return r; + } + /* Enable IRQ */ + rdev->irq.sw_int = true; + radeon_irq_set(rdev); + /* Initialize GPU Memory Controller */ + r = radeon_mc_init(rdev); + if (r) { + goto out; + } + r = radeon_gart_enable(rdev); + if (r) { + goto out; + } + r = radeon_cp_init(rdev, rdev->cp.ring_size); + if (r) { + goto out; + } } else { - radeon_combios_asic_init(rdev->ddev); - } - /* Initialize clocks */ - r = radeon_clocks_init(rdev); - if (r) { - release_console_sem(); - return r; - } - /* Enable IRQ */ - rdev->irq.sw_int = true; - radeon_irq_set(rdev); - /* Initialize GPU Memory Controller */ - r = radeon_mc_init(rdev); - if (r) { - goto out; - } - r = radeon_gart_enable(rdev); - if (r) { - goto out; - } - r = radeon_cp_init(rdev, rdev->cp.ring_size); - if (r) { - goto out; + radeon_resume(rdev); } out: + radeon_restore_bios_scratch_regs(rdev); fb_set_suspend(rdev->fbdev_info, 0); release_console_sem(); diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index a8fa1bb84cf7..5d8141b13765 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -158,9 +158,6 @@ static void radeon_crtc_destroy(struct drm_crtc *crtc) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); - if (radeon_crtc->mode_set.mode) { - drm_mode_destroy(crtc->dev, radeon_crtc->mode_set.mode); - } drm_crtc_cleanup(crtc); kfree(radeon_crtc); } @@ -189,9 +186,11 @@ static void radeon_crtc_init(struct drm_device *dev, int index) radeon_crtc->crtc_id = index; rdev->mode_info.crtcs[index] = radeon_crtc; +#if 0 radeon_crtc->mode_set.crtc = &radeon_crtc->base; radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); radeon_crtc->mode_set.num_connectors = 0; +#endif for (i = 0; i < 256; i++) { radeon_crtc->lut_r[i] = i << 2; @@ -313,7 +312,7 @@ static void radeon_print_display_setup(struct drm_device *dev) } } -bool radeon_setup_enc_conn(struct drm_device *dev) +static bool radeon_setup_enc_conn(struct drm_device *dev) { struct radeon_device *rdev = dev->dev_private; struct drm_connector *drm_connector; @@ -347,9 +346,13 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) if (!radeon_connector->ddc_bus) return -1; - radeon_i2c_do_lock(radeon_connector, 1); - edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); - radeon_i2c_do_lock(radeon_connector, 0); + if (!radeon_connector->edid) { + radeon_i2c_do_lock(radeon_connector, 1); + edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); + radeon_i2c_do_lock(radeon_connector, 0); + } else + edid = radeon_connector->edid; + if (edid) { /* update digital bits here */ if (edid->input & DRM_EDID_INPUT_DIGITAL) @@ -362,7 +365,7 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) return ret; } drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); - return -1; + return 0; } static int radeon_ddc_dump(struct drm_connector *connector) @@ -620,6 +623,83 @@ static const struct drm_mode_config_funcs radeon_mode_funcs = { .fb_changed = radeonfb_probe, }; +struct drm_prop_enum_list { + int type; + char *name; +}; + +static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = +{ { 0, "driver" }, + { 1, "bios" }, +}; + +static struct drm_prop_enum_list radeon_tv_std_enum_list[] = +{ { TV_STD_NTSC, "ntsc" }, + { TV_STD_PAL, "pal" }, + { TV_STD_PAL_M, "pal-m" }, + { TV_STD_PAL_60, "pal-60" }, + { TV_STD_NTSC_J, "ntsc-j" }, + { TV_STD_SCART_PAL, "scart-pal" }, + { TV_STD_PAL_CN, "pal-cn" }, + { TV_STD_SECAM, "secam" }, +}; + +int radeon_modeset_create_props(struct radeon_device *rdev) +{ + int i, sz; + + if (rdev->is_atom_bios) { + rdev->mode_info.coherent_mode_property = + drm_property_create(rdev->ddev, + DRM_MODE_PROP_RANGE, + "coherent", 2); + if (!rdev->mode_info.coherent_mode_property) + return -ENOMEM; + + rdev->mode_info.coherent_mode_property->values[0] = 0; + rdev->mode_info.coherent_mode_property->values[0] = 1; + } + + if (!ASIC_IS_AVIVO(rdev)) { + sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); + rdev->mode_info.tmds_pll_property = + drm_property_create(rdev->ddev, + DRM_MODE_PROP_ENUM, + "tmds_pll", sz); + for (i = 0; i < sz; i++) { + drm_property_add_enum(rdev->mode_info.tmds_pll_property, + i, + radeon_tmds_pll_enum_list[i].type, + radeon_tmds_pll_enum_list[i].name); + } + } + + rdev->mode_info.load_detect_property = + drm_property_create(rdev->ddev, + DRM_MODE_PROP_RANGE, + "load detection", 2); + if (!rdev->mode_info.load_detect_property) + return -ENOMEM; + rdev->mode_info.load_detect_property->values[0] = 0; + rdev->mode_info.load_detect_property->values[0] = 1; + + drm_mode_create_scaling_mode_property(rdev->ddev); + + sz = ARRAY_SIZE(radeon_tv_std_enum_list); + rdev->mode_info.tv_std_property = + drm_property_create(rdev->ddev, + DRM_MODE_PROP_ENUM, + "tv standard", sz); + for (i = 0; i < sz; i++) { + drm_property_add_enum(rdev->mode_info.tv_std_property, + i, + radeon_tv_std_enum_list[i].type, + radeon_tv_std_enum_list[i].name); + } + + return 0; +} + int radeon_modeset_init(struct radeon_device *rdev) { int num_crtc = 2, i; @@ -640,6 +720,10 @@ int radeon_modeset_init(struct radeon_device *rdev) rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; + ret = radeon_modeset_create_props(rdev); + if (ret) { + return ret; + } /* allocate crtcs - TODO single crtc */ for (i = 0; i < num_crtc; i++) { radeon_crtc_init(rdev->ddev, i); @@ -678,7 +762,6 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, continue; if (first) { radeon_crtc->rmx_type = radeon_encoder->rmx_type; - radeon_crtc->devices = radeon_encoder->devices; memcpy(&radeon_crtc->native_mode, &radeon_encoder->native_mode, sizeof(struct radeon_native_mode)); diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 0bd5879a4957..50fce498910c 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -38,7 +38,6 @@ #include -#if defined(CONFIG_DRM_RADEON_KMS) /* * KMS wrapper. */ @@ -77,11 +76,9 @@ int radeon_mmap(struct file *filp, struct vm_area_struct *vma); int radeon_debugfs_init(struct drm_minor *minor); void radeon_debugfs_cleanup(struct drm_minor *minor); #endif -#endif int radeon_no_wb; -#if defined(CONFIG_DRM_RADEON_KMS) int radeon_modeset = -1; int radeon_dynclks = -1; int radeon_r4xx_atom = 0; @@ -91,12 +88,11 @@ int radeon_gart_size = 512; /* default gart size */ int radeon_benchmarking = 0; int radeon_testing = 0; int radeon_connector_table = 0; -#endif +int radeon_tv = 1; MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); module_param_named(no_wb, radeon_no_wb, int, 0444); -#if defined(CONFIG_DRM_RADEON_KMS) MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); module_param_named(modeset, radeon_modeset, int, 0400); @@ -123,7 +119,9 @@ module_param_named(test, radeon_testing, int, 0444); MODULE_PARM_DESC(connector_table, "Force connector table"); module_param_named(connector_table, radeon_connector_table, int, 0444); -#endif + +MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); +module_param_named(tv, radeon_tv, int, 0444); static int radeon_suspend(struct drm_device *dev, pm_message_t state) { @@ -215,7 +213,6 @@ static struct drm_driver driver_old = { .patchlevel = DRIVER_PATCHLEVEL, }; -#if defined(CONFIG_DRM_RADEON_KMS) static struct drm_driver kms_driver; static int __devinit @@ -289,7 +286,7 @@ static struct drm_driver kms_driver = { .poll = drm_poll, .fasync = drm_fasync, #ifdef CONFIG_COMPAT - .compat_ioctl = NULL, + .compat_ioctl = radeon_kms_compat_ioctl, #endif }, @@ -309,7 +306,6 @@ static struct drm_driver kms_driver = { .minor = KMS_DRIVER_MINOR, .patchlevel = KMS_DRIVER_PATCHLEVEL, }; -#endif static struct drm_driver *driver; @@ -317,7 +313,6 @@ static int __init radeon_init(void) { driver = &driver_old; driver->num_ioctls = radeon_max_ioctl; -#if defined(CONFIG_DRM_RADEON_KMS) #ifdef CONFIG_VGA_CONSOLE if (vgacon_text_force() && radeon_modeset == -1) { DRM_INFO("VGACON disable radeon kernel modesetting.\n"); @@ -328,8 +323,13 @@ static int __init radeon_init(void) #endif /* if enabled by default */ if (radeon_modeset == -1) { - DRM_INFO("radeon default to kernel modesetting.\n"); +#ifdef CONFIG_DRM_RADEON_KMS + DRM_INFO("radeon defaulting to kernel modesetting.\n"); radeon_modeset = 1; +#else + DRM_INFO("radeon defaulting to userspace modesetting.\n"); + radeon_modeset = 0; +#endif } if (radeon_modeset == 1) { DRM_INFO("radeon kernel modesetting enabled.\n"); @@ -339,7 +339,6 @@ static int __init radeon_init(void) } /* if the vga console setting is enabled still * let modprobe override it */ -#endif return drm_init(driver); } diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h index 6fa32dac4e97..cb0cfe4b3082 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.h +++ b/drivers/gpu/drm/radeon/radeon_drv.h @@ -31,6 +31,9 @@ #ifndef __RADEON_DRV_H__ #define __RADEON_DRV_H__ +#include +#include + /* General customization: */ @@ -353,6 +356,14 @@ typedef struct drm_radeon_private { int r700_sc_hiz_tile_fifo_size; int r700_sc_earlyz_tile_fifo_fize; + struct mutex cs_mutex; + u32 cs_id_scnt; + u32 cs_id_wcnt; + /* r6xx/r7xx drm blit vertex buffer */ + struct drm_buf *blit_vb; + + /* firmware */ + const struct firmware *me_fw, *pfp_fw; } drm_radeon_private_t; typedef struct drm_radeon_buf_priv { @@ -391,6 +402,9 @@ static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, (off >= gart_start && off <= gart_end)); } +/* radeon_state.c */ +extern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf); + /* radeon_cp.c */ extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); @@ -457,6 +471,8 @@ extern int radeon_driver_open(struct drm_device *dev, struct drm_file *file_priv); extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); +extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg); extern int radeon_master_create(struct drm_device *dev, struct drm_master *master); extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master); @@ -482,6 +498,22 @@ extern int r600_cp_dispatch_indirect(struct drm_device *dev, struct drm_buf *buf, int start, int end); extern int r600_page_table_init(struct drm_device *dev); extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info); +extern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv); +extern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv); +extern int r600_cp_dispatch_texture(struct drm_device *dev, + struct drm_file *file_priv, + drm_radeon_texture_t *tex, + drm_radeon_tex_image_t *image); +/* r600_blit.c */ +extern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv); +extern void r600_done_blit_copy(struct drm_device *dev); +extern void r600_blit_copy(struct drm_device *dev, + uint64_t src_gpu_addr, uint64_t dst_gpu_addr, + int size_bytes); +extern void r600_blit_swap(struct drm_device *dev, + uint64_t src_gpu_addr, uint64_t dst_gpu_addr, + int sx, int sy, int dx, int dy, + int w, int h, int src_pitch, int dst_pitch, int cpp); /* Flags for stats.boxes */ @@ -1067,6 +1099,9 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define RADEON_CSQ_PRIBM_INDBM (4 << 28) # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) +#define R300_CP_RESYNC_ADDR 0x0778 +#define R300_CP_RESYNC_DATA 0x077c + #define RADEON_AIC_CNTL 0x01d0 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) # define RS400_MSI_REARM (1 << 3) @@ -1109,13 +1144,71 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00 -# define R600_IT_INDIRECT_BUFFER 0x00003200 -# define R600_IT_ME_INITIALIZE 0x00004400 +# define R600_IT_INDIRECT_BUFFER_END 0x00001700 +# define R600_IT_SET_PREDICATION 0x00002000 +# define R600_IT_REG_RMW 0x00002100 +# define R600_IT_COND_EXEC 0x00002200 +# define R600_IT_PRED_EXEC 0x00002300 +# define R600_IT_START_3D_CMDBUF 0x00002400 +# define R600_IT_DRAW_INDEX_2 0x00002700 +# define R600_IT_CONTEXT_CONTROL 0x00002800 +# define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900 +# define R600_IT_INDEX_TYPE 0x00002A00 +# define R600_IT_DRAW_INDEX 0x00002B00 +# define R600_IT_DRAW_INDEX_AUTO 0x00002D00 +# define R600_IT_DRAW_INDEX_IMMD 0x00002E00 +# define R600_IT_NUM_INSTANCES 0x00002F00 +# define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400 +# define R600_IT_INDIRECT_BUFFER_MP 0x00003800 +# define R600_IT_MEM_SEMAPHORE 0x00003900 +# define R600_IT_MPEG_INDEX 0x00003A00 +# define R600_IT_WAIT_REG_MEM 0x00003C00 +# define R600_IT_MEM_WRITE 0x00003D00 +# define R600_IT_INDIRECT_BUFFER 0x00003200 +# define R600_IT_CP_INTERRUPT 0x00004000 +# define R600_IT_SURFACE_SYNC 0x00004300 +# define R600_CB0_DEST_BASE_ENA (1 << 6) +# define R600_TC_ACTION_ENA (1 << 23) +# define R600_VC_ACTION_ENA (1 << 24) +# define R600_CB_ACTION_ENA (1 << 25) +# define R600_DB_ACTION_ENA (1 << 26) +# define R600_SH_ACTION_ENA (1 << 27) +# define R600_SMX_ACTION_ENA (1 << 28) +# define R600_IT_ME_INITIALIZE 0x00004400 # define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) -# define R600_IT_EVENT_WRITE 0x00004600 -# define R600_IT_SET_CONFIG_REG 0x00006800 -# define R600_SET_CONFIG_REG_OFFSET 0x00008000 -# define R600_SET_CONFIG_REG_END 0x0000ac00 +# define R600_IT_COND_WRITE 0x00004500 +# define R600_IT_EVENT_WRITE 0x00004600 +# define R600_IT_EVENT_WRITE_EOP 0x00004700 +# define R600_IT_ONE_REG_WRITE 0x00005700 +# define R600_IT_SET_CONFIG_REG 0x00006800 +# define R600_SET_CONFIG_REG_OFFSET 0x00008000 +# define R600_SET_CONFIG_REG_END 0x0000ac00 +# define R600_IT_SET_CONTEXT_REG 0x00006900 +# define R600_SET_CONTEXT_REG_OFFSET 0x00028000 +# define R600_SET_CONTEXT_REG_END 0x00029000 +# define R600_IT_SET_ALU_CONST 0x00006A00 +# define R600_SET_ALU_CONST_OFFSET 0x00030000 +# define R600_SET_ALU_CONST_END 0x00032000 +# define R600_IT_SET_BOOL_CONST 0x00006B00 +# define R600_SET_BOOL_CONST_OFFSET 0x0003e380 +# define R600_SET_BOOL_CONST_END 0x00040000 +# define R600_IT_SET_LOOP_CONST 0x00006C00 +# define R600_SET_LOOP_CONST_OFFSET 0x0003e200 +# define R600_SET_LOOP_CONST_END 0x0003e380 +# define R600_IT_SET_RESOURCE 0x00006D00 +# define R600_SET_RESOURCE_OFFSET 0x00038000 +# define R600_SET_RESOURCE_END 0x0003c000 +# define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0 +# define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1 +# define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2 +# define R600_SQ_TEX_VTX_VALID_BUFFER 0x3 +# define R600_IT_SET_SAMPLER 0x00006E00 +# define R600_SET_SAMPLER_OFFSET 0x0003c000 +# define R600_SET_SAMPLER_END 0x0003cff0 +# define R600_IT_SET_CTL_CONST 0x00006F00 +# define R600_SET_CTL_CONST_OFFSET 0x0003cff0 +# define R600_SET_CTL_CONST_END 0x0003e200 +# define R600_IT_SURFACE_BASE_UPDATE 0x00007300 #define RADEON_CP_PACKET_MASK 0xC0000000 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 @@ -1593,6 +1686,52 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); #define R600_CB_COLOR7_BASE 0x2805c #define R600_CB_COLOR7_FRAG 0x280fc +#define R600_CB_COLOR0_SIZE 0x28060 +#define R600_CB_COLOR0_VIEW 0x28080 +#define R600_CB_COLOR0_INFO 0x280a0 +#define R600_CB_COLOR0_TILE 0x280c0 +#define R600_CB_COLOR0_FRAG 0x280e0 +#define R600_CB_COLOR0_MASK 0x28100 + +#define AVIVO_D1MODE_VLINE_START_END 0x6538 +#define AVIVO_D2MODE_VLINE_START_END 0x6d38 +#define R600_CP_COHER_BASE 0x85f8 +#define R600_DB_DEPTH_BASE 0x2800c +#define R600_SQ_PGM_START_FS 0x28894 +#define R600_SQ_PGM_START_ES 0x28880 +#define R600_SQ_PGM_START_VS 0x28858 +#define R600_SQ_PGM_RESOURCES_VS 0x28868 +#define R600_SQ_PGM_CF_OFFSET_VS 0x288d0 +#define R600_SQ_PGM_START_GS 0x2886c +#define R600_SQ_PGM_START_PS 0x28840 +#define R600_SQ_PGM_RESOURCES_PS 0x28850 +#define R600_SQ_PGM_EXPORTS_PS 0x28854 +#define R600_SQ_PGM_CF_OFFSET_PS 0x288cc +#define R600_VGT_DMA_BASE 0x287e8 +#define R600_VGT_DMA_BASE_HI 0x287e4 +#define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10 +#define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14 +#define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18 +#define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c +#define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44 +#define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48 +#define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c +#define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50 +#define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8 +#define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8 +#define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8 +#define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08 +#define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc +#define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec +#define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc +#define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c + +#define R600_VGT_PRIMITIVE_TYPE 0x8958 + +#define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030 +#define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240 +#define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204 + #define R600_TC_CNTL 0x9608 # define R600_TC_L2_SIZE(x) ((x) << 5) # define R600_L2_DISABLE_LATE_HIT (1 << 9) diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index 0a92706eac19..621646752cd2 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c @@ -126,6 +126,23 @@ radeon_link_encoder_connector(struct drm_device *dev) } } +void radeon_encoder_set_active_device(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct drm_connector *connector; + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + struct radeon_connector *radeon_connector = to_radeon_connector(connector); + radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; + DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n", + radeon_encoder->active_device, radeon_encoder->devices, + radeon_connector->devices, encoder->encoder_type); + } + } +} + static struct drm_connector * radeon_get_connector_for_encoder(struct drm_encoder *encoder) { @@ -224,9 +241,12 @@ atombios_dac_setup(struct drm_encoder *encoder, int action) struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); DAC_ENCODER_CONTROL_PS_ALLOCATION args; int index = 0, num = 0; - /* fixme - fill in enc_priv for atom dac */ + struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; enum radeon_tv_std tv_std = TV_STD_NTSC; + if (dac_info->tv_std) + tv_std = dac_info->tv_std; + memset(&args, 0, sizeof(args)); switch (radeon_encoder->encoder_id) { @@ -244,9 +264,9 @@ atombios_dac_setup(struct drm_encoder *encoder, int action) args.ucAction = action; - if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) args.ucDacStandard = ATOM_DAC1_PS2; - else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) args.ucDacStandard = ATOM_DAC1_CV; else { switch (tv_std) { @@ -279,16 +299,19 @@ atombios_tv_setup(struct drm_encoder *encoder, int action) struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); TV_ENCODER_CONTROL_PS_ALLOCATION args; int index = 0; - /* fixme - fill in enc_priv for atom dac */ + struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; enum radeon_tv_std tv_std = TV_STD_NTSC; + if (dac_info->tv_std) + tv_std = dac_info->tv_std; + memset(&args, 0, sizeof(args)); index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); args.sTVEncoder.ucAction = action; - if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) args.sTVEncoder.ucTvStandard = ATOM_TV_CV; else { switch (tv_std) { @@ -520,6 +543,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) switch (connector->connector_type) { case DRM_MODE_CONNECTOR_DVII: + case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) return ATOM_ENCODER_MODE_HDMI; else if (radeon_connector->use_digital) @@ -529,7 +553,6 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) break; case DRM_MODE_CONNECTOR_DVID: case DRM_MODE_CONNECTOR_HDMIA: - case DRM_MODE_CONNECTOR_HDMIB: default: if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) return ATOM_ENCODER_MODE_HDMI; @@ -825,10 +848,10 @@ atombios_yuv_setup(struct drm_encoder *encoder, bool enable) /* XXX: fix up scratch reg handling */ temp = RREG32(reg); - if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) WREG32(reg, (ATOM_S3_TV1_ACTIVE | (radeon_crtc->crtc_id << 18))); - else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); else WREG32(reg, 0); @@ -851,9 +874,19 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; int index = 0; bool is_dig = false; + int devices; memset(&args, 0, sizeof(args)); + /* on DPMS off we have no idea if active device is meaningful */ + if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device) + devices = radeon_encoder->devices; + else + devices = radeon_encoder->active_device; + + DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", + radeon_encoder->encoder_id, mode, radeon_encoder->devices, + radeon_encoder->active_device); switch (radeon_encoder->encoder_id) { case ENCODER_OBJECT_ID_INTERNAL_TMDS1: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: @@ -881,18 +914,18 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) break; case ENCODER_OBJECT_ID_INTERNAL_DAC1: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: - if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) + if (devices & (ATOM_DEVICE_TV_SUPPORT)) index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); - else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + else if (devices & (ATOM_DEVICE_CV_SUPPORT)) index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); else index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); break; case ENCODER_OBJECT_ID_INTERNAL_DAC2: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: - if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) + if (devices & (ATOM_DEVICE_TV_SUPPORT)) index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); - else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + else if (devices & (ATOM_DEVICE_CV_SUPPORT)) index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); else index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); @@ -979,18 +1012,18 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder) break; case ENCODER_OBJECT_ID_INTERNAL_DAC1: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: - if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; - else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; else args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; break; case ENCODER_OBJECT_ID_INTERNAL_DAC2: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: - if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; - else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; else args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; @@ -1019,17 +1052,17 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder) args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; break; case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: - if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; - else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; else args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; break; case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: - if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; - else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; else args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; @@ -1097,7 +1130,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, atombios_set_encoder_crtc_source(encoder); if (ASIC_IS_AVIVO(rdev)) { - if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) atombios_yuv_setup(encoder, true); else atombios_yuv_setup(encoder, false); @@ -1135,7 +1168,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, case ENCODER_OBJECT_ID_INTERNAL_DAC2: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: atombios_dac_setup(encoder, ATOM_ENABLE); - if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) atombios_tv_setup(encoder, ATOM_ENABLE); break; } @@ -1143,11 +1176,12 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, } static bool -atombios_dac_load_detect(struct drm_encoder *encoder) +atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) { struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_connector *radeon_connector = to_radeon_connector(connector); if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT | @@ -1168,15 +1202,15 @@ atombios_dac_load_detect(struct drm_encoder *encoder) else args.sDacload.ucDacType = ATOM_DAC_B; - if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) + if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); - else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) + else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); - else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { + else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); if (crev >= 3) args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; - } else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { + } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); if (crev >= 3) args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; @@ -1195,9 +1229,10 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_connector *radeon_connector = to_radeon_connector(connector); uint32_t bios_0_scratch; - if (!atombios_dac_load_detect(encoder)) { + if (!atombios_dac_load_detect(encoder, connector)) { DRM_DEBUG("detect returned false \n"); return connector_status_unknown; } @@ -1207,17 +1242,20 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec else bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); - DRM_DEBUG("Bios 0 scratch %x\n", bios_0_scratch); - if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { + DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); + if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { if (bios_0_scratch & ATOM_S0_CRT1_MASK) return connector_status_connected; - } else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { + } + if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { if (bios_0_scratch & ATOM_S0_CRT2_MASK) return connector_status_connected; - } else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { + } + if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) return connector_status_connected; - } else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { + } + if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) return connector_status_connected; /* CTV */ else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) @@ -1230,6 +1268,8 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) { radeon_atom_output_lock(encoder, true); radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); + + radeon_encoder_set_active_device(encoder); } static void radeon_atom_encoder_commit(struct drm_encoder *encoder) @@ -1238,12 +1278,20 @@ static void radeon_atom_encoder_commit(struct drm_encoder *encoder) radeon_atom_output_lock(encoder, false); } +static void radeon_atom_encoder_disable(struct drm_encoder *encoder) +{ + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); + radeon_encoder->active_device = 0; +} + static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { .dpms = radeon_atom_encoder_dpms, .mode_fixup = radeon_atom_mode_fixup, .prepare = radeon_atom_encoder_prepare, .mode_set = radeon_atom_encoder_mode_set, .commit = radeon_atom_encoder_commit, + .disable = radeon_atom_encoder_disable, /* no detect for TMDS/LVDS yet */ }; @@ -1268,6 +1316,18 @@ static const struct drm_encoder_funcs radeon_atom_enc_funcs = { .destroy = radeon_enc_destroy, }; +struct radeon_encoder_atom_dac * +radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) +{ + struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); + + if (!dac) + return NULL; + + dac->tv_std = TV_STD_NTSC; + return dac; +} + struct radeon_encoder_atom_dig * radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) { @@ -1336,6 +1396,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); + radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); break; case ENCODER_OBJECT_ID_INTERNAL_DVO1: @@ -1345,8 +1406,14 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); - radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); + if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { + radeon_encoder->rmx_type = RMX_FULL; + drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); + radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); + } else { + drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); + radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); + } drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); break; } diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index ec383edf5f38..944e4fa78db5 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c @@ -28,15 +28,7 @@ */ #include -#include -#include -#include -#include -#include -#include -#include #include -#include #include "drmP.h" #include "drm.h" @@ -45,375 +37,24 @@ #include "radeon_drm.h" #include "radeon.h" +#include "drm_fb_helper.h" + struct radeon_fb_device { - struct radeon_device *rdev; - struct drm_display_mode *mode; + struct drm_fb_helper helper; struct radeon_framebuffer *rfb; - int crtc_count; - /* crtc currently bound to this */ - uint32_t crtc_ids[2]; + struct radeon_device *rdev; }; -static int radeonfb_setcolreg(unsigned regno, - unsigned red, - unsigned green, - unsigned blue, - unsigned transp, - struct fb_info *info) -{ - struct radeon_fb_device *rfbdev = info->par; - struct drm_device *dev = rfbdev->rdev->ddev; - struct drm_crtc *crtc; - int i; - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); - struct drm_mode_set *modeset = &radeon_crtc->mode_set; - struct drm_framebuffer *fb = modeset->fb; - - for (i = 0; i < rfbdev->crtc_count; i++) { - if (crtc->base.id == rfbdev->crtc_ids[i]) { - break; - } - } - if (i == rfbdev->crtc_count) { - continue; - } - if (regno > 255) { - return 1; - } - if (fb->depth == 8) { - radeon_crtc_fb_gamma_set(crtc, red, green, blue, regno); - return 0; - } - - if (regno < 16) { - switch (fb->depth) { - case 15: - fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) | - ((green & 0xf800) >> 6) | - ((blue & 0xf800) >> 11); - break; - case 16: - fb->pseudo_palette[regno] = (red & 0xf800) | - ((green & 0xfc00) >> 5) | - ((blue & 0xf800) >> 11); - break; - case 24: - case 32: - fb->pseudo_palette[regno] = - (((red >> 8) & 0xff) << info->var.red.offset) | - (((green >> 8) & 0xff) << info->var.green.offset) | - (((blue >> 8) & 0xff) << info->var.blue.offset); - break; - } - } - } - return 0; -} - -static int radeonfb_check_var(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - struct radeon_fb_device *rfbdev = info->par; - struct radeon_framebuffer *rfb = rfbdev->rfb; - struct drm_framebuffer *fb = &rfb->base; - int depth; - - if (var->pixclock == -1 || !var->pixclock) { - return -EINVAL; - } - /* Need to resize the fb object !!! */ - if (var->xres > fb->width || var->yres > fb->height) { - DRM_ERROR("Requested width/height is greater than current fb " - "object %dx%d > %dx%d\n", var->xres, var->yres, - fb->width, fb->height); - DRM_ERROR("Need resizing code.\n"); - return -EINVAL; - } - - switch (var->bits_per_pixel) { - case 16: - depth = (var->green.length == 6) ? 16 : 15; - break; - case 32: - depth = (var->transp.length > 0) ? 32 : 24; - break; - default: - depth = var->bits_per_pixel; - break; - } - - switch (depth) { - case 8: - var->red.offset = 0; - var->green.offset = 0; - var->blue.offset = 0; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 0; - var->transp.offset = 0; - break; -#ifdef __LITTLE_ENDIAN - case 15: - var->red.offset = 10; - var->green.offset = 5; - var->blue.offset = 0; - var->red.length = 5; - var->green.length = 5; - var->blue.length = 5; - var->transp.length = 1; - var->transp.offset = 15; - break; - case 16: - var->red.offset = 11; - var->green.offset = 5; - var->blue.offset = 0; - var->red.length = 5; - var->green.length = 6; - var->blue.length = 5; - var->transp.length = 0; - var->transp.offset = 0; - break; - case 24: - var->red.offset = 16; - var->green.offset = 8; - var->blue.offset = 0; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 0; - var->transp.offset = 0; - break; - case 32: - var->red.offset = 16; - var->green.offset = 8; - var->blue.offset = 0; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 8; - var->transp.offset = 24; - break; -#else - case 24: - var->red.offset = 8; - var->green.offset = 16; - var->blue.offset = 24; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 0; - var->transp.offset = 0; - break; - case 32: - var->red.offset = 8; - var->green.offset = 16; - var->blue.offset = 24; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 8; - var->transp.offset = 0; - break; -#endif - default: - return -EINVAL; - } - return 0; -} - -/* this will let fbcon do the mode init */ -static int radeonfb_set_par(struct fb_info *info) -{ - struct radeon_fb_device *rfbdev = info->par; - struct drm_device *dev = rfbdev->rdev->ddev; - struct fb_var_screeninfo *var = &info->var; - struct drm_crtc *crtc; - int ret; - int i; - - if (var->pixclock != -1) { - DRM_ERROR("PIXEL CLCOK SET\n"); - return -EINVAL; - } - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); - - for (i = 0; i < rfbdev->crtc_count; i++) { - if (crtc->base.id == rfbdev->crtc_ids[i]) { - break; - } - } - if (i == rfbdev->crtc_count) { - continue; - } - if (crtc->fb == radeon_crtc->mode_set.fb) { - mutex_lock(&dev->mode_config.mutex); - ret = crtc->funcs->set_config(&radeon_crtc->mode_set); - mutex_unlock(&dev->mode_config.mutex); - if (ret) { - return ret; - } - } - } - return 0; -} - -static int radeonfb_pan_display(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - struct radeon_fb_device *rfbdev = info->par; - struct drm_device *dev = rfbdev->rdev->ddev; - struct drm_mode_set *modeset; - struct drm_crtc *crtc; - struct radeon_crtc *radeon_crtc; - int ret = 0; - int i; - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - for (i = 0; i < rfbdev->crtc_count; i++) { - if (crtc->base.id == rfbdev->crtc_ids[i]) { - break; - } - } - - if (i == rfbdev->crtc_count) { - continue; - } - - radeon_crtc = to_radeon_crtc(crtc); - modeset = &radeon_crtc->mode_set; - - modeset->x = var->xoffset; - modeset->y = var->yoffset; - - if (modeset->num_connectors) { - mutex_lock(&dev->mode_config.mutex); - ret = crtc->funcs->set_config(modeset); - mutex_unlock(&dev->mode_config.mutex); - if (!ret) { - info->var.xoffset = var->xoffset; - info->var.yoffset = var->yoffset; - } - } - } - return ret; -} - -static void radeonfb_on(struct fb_info *info) -{ - struct radeon_fb_device *rfbdev = info->par; - struct drm_device *dev = rfbdev->rdev->ddev; - struct drm_crtc *crtc; - struct drm_encoder *encoder; - int i; - - /* - * For each CRTC in this fb, find all associated encoders - * and turn them off, then turn off the CRTC. - */ - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; - - for (i = 0; i < rfbdev->crtc_count; i++) { - if (crtc->base.id == rfbdev->crtc_ids[i]) { - break; - } - } - - mutex_lock(&dev->mode_config.mutex); - crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); - mutex_unlock(&dev->mode_config.mutex); - - /* Found a CRTC on this fb, now find encoders */ - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - if (encoder->crtc == crtc) { - struct drm_encoder_helper_funcs *encoder_funcs; - - encoder_funcs = encoder->helper_private; - mutex_lock(&dev->mode_config.mutex); - encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); - mutex_unlock(&dev->mode_config.mutex); - } - } - } -} - -static void radeonfb_off(struct fb_info *info, int dpms_mode) -{ - struct radeon_fb_device *rfbdev = info->par; - struct drm_device *dev = rfbdev->rdev->ddev; - struct drm_crtc *crtc; - struct drm_encoder *encoder; - int i; - - /* - * For each CRTC in this fb, find all associated encoders - * and turn them off, then turn off the CRTC. - */ - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; - - for (i = 0; i < rfbdev->crtc_count; i++) { - if (crtc->base.id == rfbdev->crtc_ids[i]) { - break; - } - } - - /* Found a CRTC on this fb, now find encoders */ - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - if (encoder->crtc == crtc) { - struct drm_encoder_helper_funcs *encoder_funcs; - - encoder_funcs = encoder->helper_private; - mutex_lock(&dev->mode_config.mutex); - encoder_funcs->dpms(encoder, dpms_mode); - mutex_unlock(&dev->mode_config.mutex); - } - } - if (dpms_mode == DRM_MODE_DPMS_OFF) { - mutex_lock(&dev->mode_config.mutex); - crtc_funcs->dpms(crtc, dpms_mode); - mutex_unlock(&dev->mode_config.mutex); - } - } -} - -int radeonfb_blank(int blank, struct fb_info *info) -{ - switch (blank) { - case FB_BLANK_UNBLANK: - radeonfb_on(info); - break; - case FB_BLANK_NORMAL: - radeonfb_off(info, DRM_MODE_DPMS_STANDBY); - break; - case FB_BLANK_HSYNC_SUSPEND: - radeonfb_off(info, DRM_MODE_DPMS_STANDBY); - break; - case FB_BLANK_VSYNC_SUSPEND: - radeonfb_off(info, DRM_MODE_DPMS_SUSPEND); - break; - case FB_BLANK_POWERDOWN: - radeonfb_off(info, DRM_MODE_DPMS_OFF); - break; - } - return 0; -} - static struct fb_ops radeonfb_ops = { .owner = THIS_MODULE, - .fb_check_var = radeonfb_check_var, - .fb_set_par = radeonfb_set_par, - .fb_setcolreg = radeonfb_setcolreg, + .fb_check_var = drm_fb_helper_check_var, + .fb_set_par = drm_fb_helper_set_par, + .fb_setcolreg = drm_fb_helper_setcolreg, .fb_fillrect = cfb_fillrect, .fb_copyarea = cfb_copyarea, .fb_imageblit = cfb_imageblit, - .fb_pan_display = radeonfb_pan_display, - .fb_blank = radeonfb_blank, + .fb_pan_display = drm_fb_helper_pan_display, + .fb_blank = drm_fb_helper_blank, }; /** @@ -456,21 +97,6 @@ int radeonfb_resize(struct drm_device *dev, struct drm_crtc *crtc) } EXPORT_SYMBOL(radeonfb_resize); -static struct drm_mode_set panic_mode; - -int radeonfb_panic(struct notifier_block *n, unsigned long ununsed, - void *panic_str) -{ - DRM_ERROR("panic occurred, switching back to text console\n"); - drm_crtc_helper_set_config(&panic_mode); - return 0; -} -EXPORT_SYMBOL(radeonfb_panic); - -static struct notifier_block paniced = { - .notifier_call = radeonfb_panic, -}; - static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled) { int aligned = width; @@ -495,11 +121,16 @@ static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bo return aligned; } -int radeonfb_create(struct radeon_device *rdev, +static struct drm_fb_helper_funcs radeon_fb_helper_funcs = { + .gamma_set = radeon_crtc_fb_gamma_set, +}; + +int radeonfb_create(struct drm_device *dev, uint32_t fb_width, uint32_t fb_height, uint32_t surface_width, uint32_t surface_height, - struct radeon_framebuffer **rfb_p) + struct drm_framebuffer **fb_p) { + struct radeon_device *rdev = dev->dev_private; struct fb_info *info; struct radeon_fb_device *rfbdev; struct drm_framebuffer *fb = NULL; @@ -513,6 +144,7 @@ int radeonfb_create(struct radeon_device *rdev, void *fbptr = NULL; unsigned long tmp; bool fb_tiled = false; /* useful for testing */ + u32 tiling_flags = 0; mode_cmd.width = surface_width; mode_cmd.height = surface_height; @@ -537,7 +169,22 @@ int radeonfb_create(struct radeon_device *rdev, robj = gobj->driver_private; if (fb_tiled) - radeon_object_set_tiling_flags(robj, RADEON_TILING_MACRO|RADEON_TILING_SURFACE, mode_cmd.pitch); + tiling_flags = RADEON_TILING_MACRO; + +#ifdef __BIG_ENDIAN + switch (mode_cmd.bpp) { + case 32: + tiling_flags |= RADEON_TILING_SWAP_32BIT; + break; + case 16: + tiling_flags |= RADEON_TILING_SWAP_16BIT; + default: + break; + } +#endif + + if (tiling_flags) + radeon_object_set_tiling_flags(robj, tiling_flags | RADEON_TILING_SURFACE, mode_cmd.pitch); mutex_lock(&rdev->ddev->struct_mutex); fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj); if (fb == NULL) { @@ -554,8 +201,8 @@ int radeonfb_create(struct radeon_device *rdev, list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list); + *fb_p = fb; rfb = to_radeon_framebuffer(fb); - *rfb_p = rfb; rdev->fbdev_rfb = rfb; rdev->fbdev_robj = robj; @@ -564,7 +211,15 @@ int radeonfb_create(struct radeon_device *rdev, ret = -ENOMEM; goto out_unref; } + + rdev->fbdev_info = info; rfbdev = info->par; + rfbdev->helper.funcs = &radeon_fb_helper_funcs; + rfbdev->helper.dev = dev; + ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, 2, + RADEONFB_CONN_LIMIT); + if (ret) + goto out_unref; if (fb_tiled) radeon_object_check_tiling(robj, 0, 0); @@ -577,33 +232,19 @@ int radeonfb_create(struct radeon_device *rdev, memset_io(fbptr, 0, aligned_size); strcpy(info->fix.id, "radeondrmfb"); - info->fix.type = FB_TYPE_PACKED_PIXELS; - info->fix.visual = FB_VISUAL_TRUECOLOR; - info->fix.type_aux = 0; - info->fix.xpanstep = 1; /* doing it in hw */ - info->fix.ypanstep = 1; /* doing it in hw */ - info->fix.ywrapstep = 0; - info->fix.accel = FB_ACCEL_NONE; - info->fix.type_aux = 0; + + drm_fb_helper_fill_fix(info, fb->pitch); + info->flags = FBINFO_DEFAULT; info->fbops = &radeonfb_ops; - info->fix.line_length = fb->pitch; + tmp = fb_gpuaddr - rdev->mc.vram_location; info->fix.smem_start = rdev->mc.aper_base + tmp; info->fix.smem_len = size; info->screen_base = fbptr; info->screen_size = size; - info->pseudo_palette = fb->pseudo_palette; - info->var.xres_virtual = fb->width; - info->var.yres_virtual = fb->height; - info->var.bits_per_pixel = fb->bits_per_pixel; - info->var.xoffset = 0; - info->var.yoffset = 0; - info->var.activate = FB_ACTIVATE_NOW; - info->var.height = -1; - info->var.width = -1; - info->var.xres = fb_width; - info->var.yres = fb_height; + + drm_fb_helper_fill_var(info, fb, fb_width, fb_height); /* setup aperture base/size for vesafb takeover */ info->aperture_base = rdev->ddev->mode_config.fb_base; @@ -626,83 +267,6 @@ int radeonfb_create(struct radeon_device *rdev, DRM_INFO("fb depth is %d\n", fb->depth); DRM_INFO(" pitch is %d\n", fb->pitch); - switch (fb->depth) { - case 8: - info->var.red.offset = 0; - info->var.green.offset = 0; - info->var.blue.offset = 0; - info->var.red.length = 8; /* 8bit DAC */ - info->var.green.length = 8; - info->var.blue.length = 8; - info->var.transp.offset = 0; - info->var.transp.length = 0; - break; -#ifdef __LITTLE_ENDIAN - case 15: - info->var.red.offset = 10; - info->var.green.offset = 5; - info->var.blue.offset = 0; - info->var.red.length = 5; - info->var.green.length = 5; - info->var.blue.length = 5; - info->var.transp.offset = 15; - info->var.transp.length = 1; - break; - case 16: - info->var.red.offset = 11; - info->var.green.offset = 5; - info->var.blue.offset = 0; - info->var.red.length = 5; - info->var.green.length = 6; - info->var.blue.length = 5; - info->var.transp.offset = 0; - break; - case 24: - info->var.red.offset = 16; - info->var.green.offset = 8; - info->var.blue.offset = 0; - info->var.red.length = 8; - info->var.green.length = 8; - info->var.blue.length = 8; - info->var.transp.offset = 0; - info->var.transp.length = 0; - break; - case 32: - info->var.red.offset = 16; - info->var.green.offset = 8; - info->var.blue.offset = 0; - info->var.red.length = 8; - info->var.green.length = 8; - info->var.blue.length = 8; - info->var.transp.offset = 24; - info->var.transp.length = 8; - break; -#else - case 24: - info->var.red.offset = 8; - info->var.green.offset = 16; - info->var.blue.offset = 24; - info->var.red.length = 8; - info->var.green.length = 8; - info->var.blue.length = 8; - info->var.transp.offset = 0; - info->var.transp.length = 0; - break; - case 32: - info->var.red.offset = 8; - info->var.green.offset = 16; - info->var.blue.offset = 24; - info->var.red.length = 8; - info->var.green.length = 8; - info->var.blue.length = 8; - info->var.transp.offset = 0; - info->var.transp.length = 8; - break; - default: -#endif - break; - } - fb->fbdev = info; rfbdev->rfb = rfb; rfbdev->rdev = rdev; @@ -726,145 +290,10 @@ out: return ret; } -static int radeonfb_single_fb_probe(struct radeon_device *rdev) -{ - struct drm_crtc *crtc; - struct drm_connector *connector; - unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1; - unsigned int surface_width = 0, surface_height = 0; - int new_fb = 0; - int crtc_count = 0; - int ret, i, conn_count = 0; - struct radeon_framebuffer *rfb; - struct fb_info *info; - struct radeon_fb_device *rfbdev; - struct drm_mode_set *modeset = NULL; - - /* first up get a count of crtcs now in use and new min/maxes width/heights */ - list_for_each_entry(crtc, &rdev->ddev->mode_config.crtc_list, head) { - if (drm_helper_crtc_in_use(crtc)) { - if (crtc->desired_mode) { - if (crtc->desired_mode->hdisplay < fb_width) - fb_width = crtc->desired_mode->hdisplay; - - if (crtc->desired_mode->vdisplay < fb_height) - fb_height = crtc->desired_mode->vdisplay; - - if (crtc->desired_mode->hdisplay > surface_width) - surface_width = crtc->desired_mode->hdisplay; - - if (crtc->desired_mode->vdisplay > surface_height) - surface_height = crtc->desired_mode->vdisplay; - } - crtc_count++; - } - } - - if (crtc_count == 0 || fb_width == -1 || fb_height == -1) { - /* hmm everyone went away - assume VGA cable just fell out - and will come back later. */ - return 0; - } - - /* do we have an fb already? */ - if (list_empty(&rdev->ddev->mode_config.fb_kernel_list)) { - /* create an fb if we don't have one */ - ret = radeonfb_create(rdev, fb_width, fb_height, surface_width, surface_height, &rfb); - if (ret) { - return -EINVAL; - } - new_fb = 1; - } else { - struct drm_framebuffer *fb; - fb = list_first_entry(&rdev->ddev->mode_config.fb_kernel_list, struct drm_framebuffer, filp_head); - rfb = to_radeon_framebuffer(fb); - - /* if someone hotplugs something bigger than we have already allocated, we are pwned. - As really we can't resize an fbdev that is in the wild currently due to fbdev - not really being designed for the lower layers moving stuff around under it. - - so in the grand style of things - punt. */ - if ((fb->width < surface_width) || (fb->height < surface_height)) { - DRM_ERROR("Framebuffer not large enough to scale console onto.\n"); - return -EINVAL; - } - } - - info = rfb->base.fbdev; - rdev->fbdev_info = info; - rfbdev = info->par; - - crtc_count = 0; - /* okay we need to setup new connector sets in the crtcs */ - list_for_each_entry(crtc, &rdev->ddev->mode_config.crtc_list, head) { - struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); - modeset = &radeon_crtc->mode_set; - modeset->fb = &rfb->base; - conn_count = 0; - list_for_each_entry(connector, &rdev->ddev->mode_config.connector_list, head) { - if (connector->encoder) - if (connector->encoder->crtc == modeset->crtc) { - modeset->connectors[conn_count] = connector; - conn_count++; - if (conn_count > RADEONFB_CONN_LIMIT) - BUG(); - } - } - - for (i = conn_count; i < RADEONFB_CONN_LIMIT; i++) - modeset->connectors[i] = NULL; - - - rfbdev->crtc_ids[crtc_count++] = crtc->base.id; - - modeset->num_connectors = conn_count; - if (modeset->crtc->desired_mode) { - if (modeset->mode) { - drm_mode_destroy(rdev->ddev, modeset->mode); - } - modeset->mode = drm_mode_duplicate(rdev->ddev, - modeset->crtc->desired_mode); - } - } - rfbdev->crtc_count = crtc_count; - - if (new_fb) { - info->var.pixclock = -1; - if (register_framebuffer(info) < 0) - return -EINVAL; - } else { - radeonfb_set_par(info); - } - printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, - info->fix.id); - - /* Switch back to kernel console on panic */ - panic_mode = *modeset; - atomic_notifier_chain_register(&panic_notifier_list, &paniced); - printk(KERN_INFO "registered panic notifier\n"); - - return 0; -} - int radeonfb_probe(struct drm_device *dev) { int ret; - - /* something has changed in the lower levels of hell - deal with it - here */ - - /* two modes : a) 1 fb to rule all crtcs. - b) one fb per crtc. - two actions 1) new connected device - 2) device removed. - case a/1 : if the fb surface isn't big enough - resize the surface fb. - if the fb size isn't big enough - resize fb into surface. - if everything big enough configure the new crtc/etc. - case a/2 : undo the configuration - possibly resize down the fb to fit the new configuration. - case b/1 : see if it is on a new crtc - setup a new fb and add it. - case b/2 : teardown the new fb. - */ - ret = radeonfb_single_fb_probe(dev->dev_private); + ret = drm_fb_helper_single_fb_probe(dev, &radeonfb_create); return ret; } EXPORT_SYMBOL(radeonfb_probe); @@ -880,16 +309,17 @@ int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb) } info = fb->fbdev; if (info) { + struct radeon_fb_device *rfbdev = info->par; robj = rfb->obj->driver_private; unregister_framebuffer(info); radeon_object_kunmap(robj); radeon_object_unpin(robj); + drm_fb_helper_free(&rfbdev->helper); framebuffer_release(info); } printk(KERN_INFO "unregistered panic notifier\n"); - atomic_notifier_chain_unregister(&panic_notifier_list, &paniced); - memset(&panic_mode, 0, sizeof(struct drm_mode_set)); + return 0; } EXPORT_SYMBOL(radeonfb_remove); diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c index b4e48dd2e859..3beb26d74719 100644 --- a/drivers/gpu/drm/radeon/radeon_fence.c +++ b/drivers/gpu/drm/radeon/radeon_fence.c @@ -53,9 +53,9 @@ int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence) * away */ WREG32(rdev->fence_drv.scratch_reg, fence->seq); - } else { + } else radeon_fence_ring_emit(rdev, fence); - } + fence->emited = true; fence->timeout = jiffies + ((2000 * HZ) / 1000); list_del(&fence->list); @@ -168,7 +168,38 @@ bool radeon_fence_signaled(struct radeon_fence *fence) return signaled; } -int radeon_fence_wait(struct radeon_fence *fence, bool interruptible) +int r600_fence_wait(struct radeon_fence *fence, bool intr, bool lazy) +{ + struct radeon_device *rdev; + int ret = 0; + + rdev = fence->rdev; + + __set_current_state(intr ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); + + while (1) { + if (radeon_fence_signaled(fence)) + break; + + if (time_after_eq(jiffies, fence->timeout)) { + ret = -EBUSY; + break; + } + + if (lazy) + schedule_timeout(1); + + if (intr && signal_pending(current)) { + ret = -ERESTARTSYS; + break; + } + } + __set_current_state(TASK_RUNNING); + return ret; +} + + +int radeon_fence_wait(struct radeon_fence *fence, bool intr) { struct radeon_device *rdev; unsigned long cur_jiffies; @@ -176,7 +207,6 @@ int radeon_fence_wait(struct radeon_fence *fence, bool interruptible) bool expired = false; int r; - if (fence == NULL) { WARN(1, "Querying an invalid fence : %p !\n", fence); return 0; @@ -185,13 +215,22 @@ int radeon_fence_wait(struct radeon_fence *fence, bool interruptible) if (radeon_fence_signaled(fence)) { return 0; } + + if (rdev->family >= CHIP_R600) { + r = r600_fence_wait(fence, intr, 0); + if (r == -ERESTARTSYS) + return -EBUSY; + return r; + } + retry: cur_jiffies = jiffies; timeout = HZ / 100; if (time_after(fence->timeout, cur_jiffies)) { timeout = fence->timeout - cur_jiffies; } - if (interruptible) { + + if (intr) { r = wait_event_interruptible_timeout(rdev->fence_drv.queue, radeon_fence_signaled(fence), timeout); if (unlikely(r == -ERESTARTSYS)) { diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c index 2977539880fb..a931af065dd4 100644 --- a/drivers/gpu/drm/radeon/radeon_gart.c +++ b/drivers/gpu/drm/radeon/radeon_gart.c @@ -75,7 +75,6 @@ void radeon_gart_table_ram_free(struct radeon_device *rdev) int radeon_gart_table_vram_alloc(struct radeon_device *rdev) { - uint64_t gpu_addr; int r; if (rdev->gart.table.vram.robj == NULL) { @@ -88,6 +87,14 @@ int radeon_gart_table_vram_alloc(struct radeon_device *rdev) return r; } } + return 0; +} + +int radeon_gart_table_vram_pin(struct radeon_device *rdev) +{ + uint64_t gpu_addr; + int r; + r = radeon_object_pin(rdev->gart.table.vram.robj, RADEON_GEM_DOMAIN_VRAM, &gpu_addr); if (r) { diff --git a/drivers/gpu/drm/radeon/radeon_ioc32.c b/drivers/gpu/drm/radeon/radeon_ioc32.c index 56decda2a71f..a1bf11de308a 100644 --- a/drivers/gpu/drm/radeon/radeon_ioc32.c +++ b/drivers/gpu/drm/radeon/radeon_ioc32.c @@ -422,3 +422,18 @@ long radeon_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) return ret; } + +long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + unsigned int nr = DRM_IOCTL_NR(cmd); + int ret; + + if (nr < DRM_COMMAND_BASE) + return drm_compat_ioctl(filp, cmd, arg); + + lock_kernel(); /* XXX for now */ + ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg); + unlock_kernel(); + + return ret; +} diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c index 9836c705a952..b79ecc4a7cc4 100644 --- a/drivers/gpu/drm/radeon/radeon_irq.c +++ b/drivers/gpu/drm/radeon/radeon_irq.c @@ -188,6 +188,9 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS) u32 stat; u32 r500_disp_int; + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) + return IRQ_NONE; + /* Only consider the bits we're interested in - others could be used * outside the DRM */ @@ -286,6 +289,9 @@ int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_pr drm_radeon_irq_emit_t *emit = data; int result; + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) + return -EINVAL; + LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { @@ -315,6 +321,9 @@ int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_pr return -EINVAL; } + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) + return -EINVAL; + return radeon_wait_irq(dev, irqwait->irq_seq); } @@ -326,6 +335,9 @@ void radeon_driver_irq_preinstall(struct drm_device * dev) (drm_radeon_private_t *) dev->dev_private; u32 dummy; + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) + return; + /* Disable *all* interrupts */ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) RADEON_WRITE(R500_DxMODE_INT_MASK, 0); @@ -345,6 +357,9 @@ int radeon_driver_irq_postinstall(struct drm_device *dev) dev->max_vblank_count = 0x001fffff; + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) + return 0; + radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); return 0; @@ -357,6 +372,9 @@ void radeon_driver_irq_uninstall(struct drm_device * dev) if (!dev_priv) return; + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) + return; + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) RADEON_WRITE(R500_DxMODE_INT_MASK, 0); /* Disable *all* interrupts */ diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c index 9805e4b6ca1b..1841145a7c4f 100644 --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c @@ -28,7 +28,6 @@ #include "drmP.h" #include "radeon_drm.h" #include "radeon_reg.h" -#include "radeon_microcode.h" #include "radeon.h" #include "atom.h" diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index dce09ada32bc..709bd892b3a9 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c @@ -54,12 +54,23 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) flags |= RADEON_IS_PCI; } + /* radeon_device_init should report only fatal error + * like memory allocation failure or iomapping failure, + * or memory manager initialization failure, it must + * properly initialize the GPU MC controller and permit + * VRAM allocation + */ r = radeon_device_init(rdev, dev, dev->pdev, flags); if (r) { - DRM_ERROR("Failed to initialize radeon, disabling IOCTL\n"); - radeon_device_fini(rdev); - kfree(rdev); - dev->dev_private = NULL; + DRM_ERROR("Fatal error while trying to initialize radeon.\n"); + return r; + } + /* Again modeset_init should fail only on fatal error + * otherwise it should provide enough functionalities + * for shadowfb to run + */ + r = radeon_modeset_init(rdev); + if (r) { return r; } return 0; @@ -69,6 +80,9 @@ int radeon_driver_unload_kms(struct drm_device *dev) { struct radeon_device *rdev = dev->dev_private; + if (rdev == NULL) + return 0; + radeon_modeset_fini(rdev); radeon_device_fini(rdev); kfree(rdev); dev->dev_private = NULL; @@ -98,6 +112,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) case RADEON_INFO_NUM_Z_PIPES: value = rdev->num_z_pipes; break; + case RADEON_INFO_ACCEL_WORKING: + value = rdev->accel_working; + break; default: DRM_DEBUG("Invalid request %d\n", info->request); return -EINVAL; diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c index 0da72f18fd3a..2b997a15fb1f 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c @@ -28,6 +28,7 @@ #include #include "radeon_fixed.h" #include "radeon.h" +#include "atom.h" static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, @@ -340,6 +341,9 @@ void radeon_legacy_atom_set_surface(struct drm_crtc *crtc) uint32_t crtc_pitch; switch (crtc->fb->bits_per_pixel) { + case 8: + format = 2; + break; case 15: /* 555 */ format = 3; break; @@ -400,11 +404,33 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; uint32_t crtc_pitch, pitch_pixels; uint32_t tiling_flags; + int format; + uint32_t gen_cntl_reg, gen_cntl_val; DRM_DEBUG("\n"); radeon_fb = to_radeon_framebuffer(crtc->fb); + switch (crtc->fb->bits_per_pixel) { + case 8: + format = 2; + break; + case 15: /* 555 */ + format = 3; + break; + case 16: /* 565 */ + format = 4; + break; + case 24: /* RGB */ + format = 5; + break; + case 32: /* xRGB */ + format = 6; + break; + default: + return false; + } + obj = radeon_fb->obj; if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) { return -EINVAL; @@ -457,6 +483,9 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, } else { int offset = y * pitch_pixels + x; switch (crtc->fb->bits_per_pixel) { + case 8: + offset *= 1; + break; case 15: case 16: offset *= 2; @@ -475,6 +504,16 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, base &= ~7; + if (radeon_crtc->crtc_id == 1) + gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; + else + gen_cntl_reg = RADEON_CRTC_GEN_CNTL; + + gen_cntl_val = RREG32(gen_cntl_reg); + gen_cntl_val &= ~(0xf << 8); + gen_cntl_val |= (format << 8); + WREG32(gen_cntl_reg, gen_cntl_val); + crtc_offset = (u32)base; WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); @@ -501,6 +540,7 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod struct drm_device *dev = crtc->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); + struct drm_encoder *encoder; int format; int hsync_start; int hsync_wid; @@ -509,10 +549,24 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod uint32_t crtc_h_sync_strt_wid; uint32_t crtc_v_total_disp; uint32_t crtc_v_sync_strt_wid; + bool is_tv = false; DRM_DEBUG("\n"); + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + if (encoder->crtc == crtc) { + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { + is_tv = true; + DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); + break; + } + } + } switch (crtc->fb->bits_per_pixel) { + case 8: + format = 2; + break; case 15: /* 555 */ format = 3; break; @@ -642,6 +696,11 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); } + if (is_tv) + radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, + &crtc_h_sync_strt_wid, &crtc_v_total_disp, + &crtc_v_sync_strt_wid); + WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); @@ -668,7 +727,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) uint32_t pll_ref_div = 0; uint32_t pll_fb_post_div = 0; uint32_t htotal_cntl = 0; - + bool is_tv = false; struct radeon_pll *pll; struct { @@ -703,6 +762,13 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { if (encoder->crtc == crtc) { + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + + if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { + is_tv = true; + break; + } + if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { @@ -766,6 +832,12 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); + if (is_tv) { + radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, + &pll_ref_div, &pll_fb_post_div, + &pixclks_cntl); + } + WREG32_PLL_P(RADEON_PIXCLKS_CNTL, RADEON_PIX2CLK_SRC_SEL_CPUCLK, ~(RADEON_PIX2CLK_SRC_SEL_MASK)); @@ -820,6 +892,15 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); } else { + uint32_t pixclks_cntl; + + + if (is_tv) { + pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); + radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, + &pll_fb_post_div, &pixclks_cntl); + } + if (rdev->flags & RADEON_IS_MOBILITY) { /* A temporal workaround for the occational blanking on certain laptop panels. This appears to related to the PLL divider registers (fail to lock?). @@ -914,6 +995,8 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) RADEON_VCLK_SRC_SEL_PPLLCLK, ~(RADEON_VCLK_SRC_SEL_MASK)); + if (is_tv) + WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); } } diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c index 9322675ef6d0..b1547f700d73 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c @@ -29,6 +29,15 @@ #include "radeon.h" #include "atom.h" +static void radeon_legacy_encoder_disable(struct drm_encoder *encoder) +{ + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct drm_encoder_helper_funcs *encoder_funcs; + + encoder_funcs = encoder->helper_private; + encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); + radeon_encoder->active_device = 0; +} static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) { @@ -98,6 +107,8 @@ static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder) else radeon_combios_output_lock(encoder, true); radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF); + + radeon_encoder_set_active_device(encoder); } static void radeon_legacy_lvds_commit(struct drm_encoder *encoder) @@ -195,6 +206,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = { .prepare = radeon_legacy_lvds_prepare, .mode_set = radeon_legacy_lvds_mode_set, .commit = radeon_legacy_lvds_commit, + .disable = radeon_legacy_encoder_disable, }; @@ -260,6 +272,7 @@ static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder) else radeon_combios_output_lock(encoder, true); radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF); + radeon_encoder_set_active_device(encoder); } static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder) @@ -402,6 +415,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_fu .mode_set = radeon_legacy_primary_dac_mode_set, .commit = radeon_legacy_primary_dac_commit, .detect = radeon_legacy_primary_dac_detect, + .disable = radeon_legacy_encoder_disable, }; @@ -454,6 +468,7 @@ static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder) else radeon_combios_output_lock(encoder, true); radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF); + radeon_encoder_set_active_device(encoder); } static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder) @@ -566,6 +581,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs .prepare = radeon_legacy_tmds_int_prepare, .mode_set = radeon_legacy_tmds_int_mode_set, .commit = radeon_legacy_tmds_int_commit, + .disable = radeon_legacy_encoder_disable, }; @@ -620,6 +636,7 @@ static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder) else radeon_combios_output_lock(encoder, true); radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF); + radeon_encoder_set_active_device(encoder); } static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder) @@ -706,6 +723,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs .prepare = radeon_legacy_tmds_ext_prepare, .mode_set = radeon_legacy_tmds_ext_mode_set, .commit = radeon_legacy_tmds_ext_commit, + .disable = radeon_legacy_encoder_disable, }; @@ -727,17 +745,21 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) { struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; - /* uint32_t tv_master_cntl = 0; */ - + uint32_t tv_master_cntl = 0; + bool is_tv; DRM_DEBUG("\n"); + is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; + if (rdev->family == CHIP_R200) fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); else { - crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); - /* FIXME TV */ - /* tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); */ + if (is_tv) + tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); + else + crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); } @@ -746,20 +768,23 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) if (rdev->family == CHIP_R200) { fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); } else { - crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; - /* tv_master_cntl |= RADEON_TV_ON; */ + if (is_tv) + tv_master_cntl |= RADEON_TV_ON; + else + crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; + if (rdev->family == CHIP_R420 || - rdev->family == CHIP_R423 || - rdev->family == CHIP_RV410) + rdev->family == CHIP_R423 || + rdev->family == CHIP_RV410) tv_dac_cntl &= ~(R420_TV_DAC_RDACPD | - R420_TV_DAC_GDACPD | - R420_TV_DAC_BDACPD | - RADEON_TV_DAC_BGSLEEP); + R420_TV_DAC_GDACPD | + R420_TV_DAC_BDACPD | + RADEON_TV_DAC_BGSLEEP); else tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | - RADEON_TV_DAC_GDACPD | - RADEON_TV_DAC_BDACPD | - RADEON_TV_DAC_BGSLEEP); + RADEON_TV_DAC_GDACPD | + RADEON_TV_DAC_BDACPD | + RADEON_TV_DAC_BGSLEEP); } break; case DRM_MODE_DPMS_STANDBY: @@ -768,8 +793,11 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) if (rdev->family == CHIP_R200) fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); else { - crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; - /* tv_master_cntl &= ~RADEON_TV_ON; */ + if (is_tv) + tv_master_cntl &= ~RADEON_TV_ON; + else + crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; + if (rdev->family == CHIP_R420 || rdev->family == CHIP_R423 || rdev->family == CHIP_RV410) @@ -789,8 +817,10 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) if (rdev->family == CHIP_R200) { WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); } else { - WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); - /* WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); */ + if (is_tv) + WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); + else + WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); } @@ -809,6 +839,7 @@ static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder) else radeon_combios_output_lock(encoder, true); radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF); + radeon_encoder_set_active_device(encoder); } static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder) @@ -831,11 +862,15 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, struct radeon_device *rdev = dev->dev_private; struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0; - uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0; + uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0; + bool is_tv = false; DRM_DEBUG("\n"); + is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; + if (rdev->family != CHIP_R200) { tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); if (rdev->family == CHIP_R420 || @@ -858,7 +893,7 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, } /* FIXME TV */ - if (radeon_encoder->enc_priv) { + if (tv_dac) { struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | @@ -875,44 +910,93 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, if (ASIC_IS_R300(rdev)) { gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1; disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); - } else if (rdev->family == CHIP_R200) - fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); + } + + if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) + disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL); else disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); - dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; + if (rdev->family == CHIP_R200) + fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); - if (radeon_crtc->crtc_id == 0) { - if (ASIC_IS_R300(rdev)) { - disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; - disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; - } else if (rdev->family == CHIP_R200) { - fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | - RADEON_FP2_DVO_RATE_SEL_SDR); - } else - disp_hw_debug |= RADEON_CRT2_DISP1_SEL; + if (is_tv) { + uint32_t dac_cntl; + + dac_cntl = RREG32(RADEON_DAC_CNTL); + dac_cntl &= ~RADEON_DAC_TVO_EN; + WREG32(RADEON_DAC_CNTL, dac_cntl); + + if (ASIC_IS_R300(rdev)) + gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1; + + dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL; + if (radeon_crtc->crtc_id == 0) { + if (ASIC_IS_R300(rdev)) { + disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; + disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC | + RADEON_DISP_TV_SOURCE_CRTC); + } + if (rdev->family >= CHIP_R200) { + disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2; + } else { + disp_hw_debug |= RADEON_CRT2_DISP1_SEL; + } + } else { + if (ASIC_IS_R300(rdev)) { + disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; + disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC; + } + if (rdev->family >= CHIP_R200) { + disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2; + } else { + disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; + } + } + WREG32(RADEON_DAC_CNTL2, dac2_cntl); } else { - if (ASIC_IS_R300(rdev)) { - disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; - disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; - } else if (rdev->family == CHIP_R200) { - fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | - RADEON_FP2_DVO_RATE_SEL_SDR); - fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; - } else - disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; - } - WREG32(RADEON_DAC_CNTL2, dac2_cntl); + dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; + + if (radeon_crtc->crtc_id == 0) { + if (ASIC_IS_R300(rdev)) { + disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; + disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; + } else if (rdev->family == CHIP_R200) { + fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | + RADEON_FP2_DVO_RATE_SEL_SDR); + } else + disp_hw_debug |= RADEON_CRT2_DISP1_SEL; + } else { + if (ASIC_IS_R300(rdev)) { + disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; + disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; + } else if (rdev->family == CHIP_R200) { + fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | + RADEON_FP2_DVO_RATE_SEL_SDR); + fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; + } else + disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; + } + WREG32(RADEON_DAC_CNTL2, dac2_cntl); + } if (ASIC_IS_R300(rdev)) { WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); - WREG32(RADEON_DISP_TV_OUT_CNTL, disp_output_cntl); - } else if (rdev->family == CHIP_R200) - WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); + WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); + } + + if (rdev->family >= CHIP_R200) + WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl); else WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); + if (rdev->family == CHIP_R200) + WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); + + if (is_tv) + radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode); + if (rdev->is_atom_bios) radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); else @@ -920,6 +1004,141 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, } +static bool r300_legacy_tv_detect(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; + uint32_t disp_output_cntl, gpiopad_a, tmp; + bool found = false; + + /* save regs needed */ + gpiopad_a = RREG32(RADEON_GPIOPAD_A); + dac_cntl2 = RREG32(RADEON_DAC_CNTL2); + crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); + dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); + tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); + disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); + + WREG32_P(RADEON_GPIOPAD_A, 0, ~1); + + WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL); + + WREG32(RADEON_CRTC2_GEN_CNTL, + RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT); + + tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; + tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; + WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); + + WREG32(RADEON_DAC_EXT_CNTL, + RADEON_DAC2_FORCE_BLANK_OFF_EN | + RADEON_DAC2_FORCE_DATA_EN | + RADEON_DAC_FORCE_DATA_SEL_RGB | + (0xec << RADEON_DAC_FORCE_DATA_SHIFT)); + + WREG32(RADEON_TV_DAC_CNTL, + RADEON_TV_DAC_STD_NTSC | + (8 << RADEON_TV_DAC_BGADJ_SHIFT) | + (6 << RADEON_TV_DAC_DACADJ_SHIFT)); + + RREG32(RADEON_TV_DAC_CNTL); + mdelay(4); + + WREG32(RADEON_TV_DAC_CNTL, + RADEON_TV_DAC_NBLANK | + RADEON_TV_DAC_NHOLD | + RADEON_TV_MONITOR_DETECT_EN | + RADEON_TV_DAC_STD_NTSC | + (8 << RADEON_TV_DAC_BGADJ_SHIFT) | + (6 << RADEON_TV_DAC_DACADJ_SHIFT)); + + RREG32(RADEON_TV_DAC_CNTL); + mdelay(6); + + tmp = RREG32(RADEON_TV_DAC_CNTL); + if ((tmp & RADEON_TV_DAC_GDACDET) != 0) { + found = true; + DRM_DEBUG("S-video TV connection detected\n"); + } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { + found = true; + DRM_DEBUG("Composite TV connection detected\n"); + } + + WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); + WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); + WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); + WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); + WREG32(RADEON_DAC_CNTL2, dac_cntl2); + WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); + return found; +} + +static bool radeon_legacy_tv_detect(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + uint32_t tv_dac_cntl, dac_cntl2; + uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp; + bool found = false; + + if (ASIC_IS_R300(rdev)) + return r300_legacy_tv_detect(encoder, connector); + + dac_cntl2 = RREG32(RADEON_DAC_CNTL2); + tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); + tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); + config_cntl = RREG32(RADEON_CONFIG_CNTL); + tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL); + + tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL; + WREG32(RADEON_DAC_CNTL2, tmp); + + tmp = tv_master_cntl | RADEON_TV_ON; + tmp &= ~(RADEON_TV_ASYNC_RST | + RADEON_RESTART_PHASE_FIX | + RADEON_CRT_FIFO_CE_EN | + RADEON_TV_FIFO_CE_EN | + RADEON_RE_SYNC_NOW_SEL_MASK); + tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST; + WREG32(RADEON_TV_MASTER_CNTL, tmp); + + tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | + RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC | + (8 << RADEON_TV_DAC_BGADJ_SHIFT); + + if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK) + tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT); + else + tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT); + WREG32(RADEON_TV_DAC_CNTL, tmp); + + tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN | + RADEON_RED_MX_FORCE_DAC_DATA | + RADEON_GRN_MX_FORCE_DAC_DATA | + RADEON_BLU_MX_FORCE_DAC_DATA | + (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT); + WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp); + + mdelay(3); + tmp = RREG32(RADEON_TV_DAC_CNTL); + if (tmp & RADEON_TV_DAC_GDACDET) { + found = true; + DRM_DEBUG("S-video TV connection detected\n"); + } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { + found = true; + DRM_DEBUG("Composite TV connection detected\n"); + } + + WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); + WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); + WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); + WREG32(RADEON_DAC_CNTL2, dac_cntl2); + return found; +} + static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) { @@ -928,9 +1147,29 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; enum drm_connector_status found = connector_status_disconnected; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; bool color = true; - /* FIXME tv */ + if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO || + connector->connector_type == DRM_MODE_CONNECTOR_Composite || + connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) { + bool tv_detect; + + if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT)) + return connector_status_disconnected; + + tv_detect = radeon_legacy_tv_detect(encoder, connector); + if (tv_detect && tv_dac) + found = connector_status_connected; + return found; + } + + /* don't probe if the encoder is being used for something else not CRT related */ + if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) { + DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device); + return connector_status_disconnected; + } /* save the regs we need */ pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); @@ -1013,8 +1252,7 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder } WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); - /* return found; */ - return connector_status_disconnected; + return found; } @@ -1025,6 +1263,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = .mode_set = radeon_legacy_tv_dac_mode_set, .commit = radeon_legacy_tv_dac_commit, .detect = radeon_legacy_tv_dac_detect, + .disable = radeon_legacy_encoder_disable, }; @@ -1032,6 +1271,30 @@ static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = { .destroy = radeon_enc_destroy, }; + +static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder) +{ + struct drm_device *dev = encoder->base.dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder_int_tmds *tmds = NULL; + bool ret; + + tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); + + if (!tmds) + return NULL; + + if (rdev->is_atom_bios) + ret = radeon_atombios_get_tmds_info(encoder, tmds); + else + ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds); + + if (ret == false) + radeon_legacy_get_tmds_info_from_table(encoder, tmds); + + return tmds; +} + void radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) { @@ -1078,10 +1341,7 @@ radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t case ENCODER_OBJECT_ID_INTERNAL_TMDS1: drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS); drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs); - if (rdev->is_atom_bios) - radeon_encoder->enc_priv = radeon_atombios_get_tmds_info(radeon_encoder); - else - radeon_encoder->enc_priv = radeon_combios_get_tmds_info(radeon_encoder); + radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder); break; case ENCODER_OBJECT_ID_INTERNAL_DAC1: drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC); diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c new file mode 100644 index 000000000000..3a12bb0c0563 --- /dev/null +++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c @@ -0,0 +1,904 @@ +#include "drmP.h" +#include "drm_crtc_helper.h" +#include "radeon.h" + +/* + * Integrated TV out support based on the GATOS code by + * Federico Ulivi + */ + + +/* + * Limits of h/v positions (hPos & vPos) + */ +#define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */ +#define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */ + +/* + * Unit for hPos (in TV clock periods) + */ +#define H_POS_UNIT 10 + +/* + * Indexes in h. code timing table for horizontal line position adjustment + */ +#define H_TABLE_POS1 6 +#define H_TABLE_POS2 8 + +/* + * Limits of hor. size (hSize) + */ +#define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */ + +/* tv standard constants */ +#define NTSC_TV_CLOCK_T 233 +#define NTSC_TV_VFTOTAL 1 +#define NTSC_TV_LINES_PER_FRAME 525 +#define NTSC_TV_ZERO_H_SIZE 479166 +#define NTSC_TV_H_SIZE_UNIT 9478 + +#define PAL_TV_CLOCK_T 188 +#define PAL_TV_VFTOTAL 3 +#define PAL_TV_LINES_PER_FRAME 625 +#define PAL_TV_ZERO_H_SIZE 473200 +#define PAL_TV_H_SIZE_UNIT 9360 + +/* tv pll setting for 27 mhz ref clk */ +#define NTSC_TV_PLL_M_27 22 +#define NTSC_TV_PLL_N_27 175 +#define NTSC_TV_PLL_P_27 5 + +#define PAL_TV_PLL_M_27 113 +#define PAL_TV_PLL_N_27 668 +#define PAL_TV_PLL_P_27 3 + +/* tv pll setting for 14 mhz ref clk */ +#define NTSC_TV_PLL_M_14 33 +#define NTSC_TV_PLL_N_14 693 +#define NTSC_TV_PLL_P_14 7 + +#define VERT_LEAD_IN_LINES 2 +#define FRAC_BITS 0xe +#define FRAC_MASK 0x3fff + +struct radeon_tv_mode_constants { + uint16_t hor_resolution; + uint16_t ver_resolution; + enum radeon_tv_std standard; + uint16_t hor_total; + uint16_t ver_total; + uint16_t hor_start; + uint16_t hor_syncstart; + uint16_t ver_syncstart; + unsigned def_restart; + uint16_t crtcPLL_N; + uint8_t crtcPLL_M; + uint8_t crtcPLL_post_div; + unsigned pix_to_tv; +}; + +static const uint16_t hor_timing_NTSC[] = { + 0x0007, + 0x003f, + 0x0263, + 0x0a24, + 0x2a6b, + 0x0a36, + 0x126d, /* H_TABLE_POS1 */ + 0x1bfe, + 0x1a8f, /* H_TABLE_POS2 */ + 0x1ec7, + 0x3863, + 0x1bfe, + 0x1bfe, + 0x1a2a, + 0x1e95, + 0x0e31, + 0x201b, + 0 +}; + +static const uint16_t vert_timing_NTSC[] = { + 0x2001, + 0x200d, + 0x1006, + 0x0c06, + 0x1006, + 0x1818, + 0x21e3, + 0x1006, + 0x0c06, + 0x1006, + 0x1817, + 0x21d4, + 0x0002, + 0 +}; + +static const uint16_t hor_timing_PAL[] = { + 0x0007, + 0x0058, + 0x027c, + 0x0a31, + 0x2a77, + 0x0a95, + 0x124f, /* H_TABLE_POS1 */ + 0x1bfe, + 0x1b22, /* H_TABLE_POS2 */ + 0x1ef9, + 0x387c, + 0x1bfe, + 0x1bfe, + 0x1b31, + 0x1eb5, + 0x0e43, + 0x201b, + 0 +}; + +static const uint16_t vert_timing_PAL[] = { + 0x2001, + 0x200c, + 0x1005, + 0x0c05, + 0x1005, + 0x1401, + 0x1821, + 0x2240, + 0x1005, + 0x0c05, + 0x1005, + 0x1401, + 0x1822, + 0x2230, + 0x0002, + 0 +}; + +/********************************************************************** + * + * availableModes + * + * Table of all allowed modes for tv output + * + **********************************************************************/ +static const struct radeon_tv_mode_constants available_tv_modes[] = { + { /* NTSC timing for 27 Mhz ref clk */ + 800, /* horResolution */ + 600, /* verResolution */ + TV_STD_NTSC, /* standard */ + 990, /* horTotal */ + 740, /* verTotal */ + 813, /* horStart */ + 824, /* horSyncStart */ + 632, /* verSyncStart */ + 625592, /* defRestart */ + 592, /* crtcPLL_N */ + 91, /* crtcPLL_M */ + 4, /* crtcPLL_postDiv */ + 1022, /* pixToTV */ + }, + { /* PAL timing for 27 Mhz ref clk */ + 800, /* horResolution */ + 600, /* verResolution */ + TV_STD_PAL, /* standard */ + 1144, /* horTotal */ + 706, /* verTotal */ + 812, /* horStart */ + 824, /* horSyncStart */ + 669, /* verSyncStart */ + 696700, /* defRestart */ + 1382, /* crtcPLL_N */ + 231, /* crtcPLL_M */ + 4, /* crtcPLL_postDiv */ + 759, /* pixToTV */ + }, + { /* NTSC timing for 14 Mhz ref clk */ + 800, /* horResolution */ + 600, /* verResolution */ + TV_STD_NTSC, /* standard */ + 1018, /* horTotal */ + 727, /* verTotal */ + 813, /* horStart */ + 840, /* horSyncStart */ + 633, /* verSyncStart */ + 630627, /* defRestart */ + 347, /* crtcPLL_N */ + 14, /* crtcPLL_M */ + 8, /* crtcPLL_postDiv */ + 1022, /* pixToTV */ + }, +}; + +#define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes) + +static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder, + uint16_t *pll_ref_freq) +{ + struct drm_device *dev = radeon_encoder->base.dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_crtc *radeon_crtc; + struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; + const struct radeon_tv_mode_constants *const_ptr; + struct radeon_pll *pll; + + radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); + if (radeon_crtc->crtc_id == 1) + pll = &rdev->clock.p2pll; + else + pll = &rdev->clock.p1pll; + + if (pll_ref_freq) + *pll_ref_freq = pll->reference_freq; + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M) { + if (pll->reference_freq == 2700) + const_ptr = &available_tv_modes[0]; + else + const_ptr = &available_tv_modes[2]; + } else { + if (pll->reference_freq == 2700) + const_ptr = &available_tv_modes[1]; + else + const_ptr = &available_tv_modes[1]; /* FIX ME */ + } + return const_ptr; +} + +static long YCOEF_value[5] = { 2, 2, 0, 4, 0 }; +static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 }; +static long SLOPE_value[5] = { 1, 2, 2, 4, 8 }; +static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 }; + +static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests, + unsigned n_wait_loops, unsigned cnt_threshold) +{ + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + uint32_t save_pll_test; + unsigned int i, j; + + WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100); + save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL); + WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B); + + WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); + for (i = 0; i < n_tests; i++) { + WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); + for (j = 0; j < n_wait_loops; j++) + if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold) + break; + } + WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test); + WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff); +} + + +static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder, + uint16_t addr, uint32_t value) +{ + struct drm_device *dev = radeon_encoder->base.dev; + struct radeon_device *rdev = dev->dev_private; + uint32_t tmp; + int i = 0; + + WREG32(RADEON_TV_HOST_WRITE_DATA, value); + + WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); + WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT); + + do { + tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); + if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0) + break; + i++; + } while (i < 10000); + WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); +} + +#if 0 /* included for completeness */ +static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr) +{ + struct drm_device *dev = radeon_encoder->base.dev; + struct radeon_device *rdev = dev->dev_private; + uint32_t tmp; + int i = 0; + + WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); + WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD); + + do { + tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); + if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0) + break; + i++; + } while (i < 10000); + WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); + return RREG32(RADEON_TV_HOST_READ_DATA); +} +#endif + +static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr) +{ + uint16_t h_table; + + switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) { + case 0: + h_table = RADEON_TV_MAX_FIFO_ADDR_INTERNAL; + break; + case 1: + h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2; + break; + case 2: + h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2; + break; + default: + h_table = 0; + break; + } + return h_table; +} + +static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr) +{ + uint16_t v_table; + + switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) { + case 0: + v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1; + break; + case 1: + v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1; + break; + case 2: + v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1; + break; + default: + v_table = 0; + break; + } + return v_table; +} + +static void radeon_restore_tv_timing_tables(struct radeon_encoder *radeon_encoder) +{ + struct drm_device *dev = radeon_encoder->base.dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; + uint16_t h_table, v_table; + uint32_t tmp; + int i; + + WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr); + h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr); + v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr); + + for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, h_table--) { + tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]); + radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp); + if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0) + break; + } + for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) { + tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]); + radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp); + if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0) + break; + } +} + +static void radeon_legacy_write_tv_restarts(struct radeon_encoder *radeon_encoder) +{ + struct drm_device *dev = radeon_encoder->base.dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; + WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart); + WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart); + WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart); +} + +static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; + struct radeon_crtc *radeon_crtc; + int restart; + unsigned int h_total, v_total, f_total; + int v_offset, h_offset; + u16 p1, p2, h_inc; + bool h_changed; + const struct radeon_tv_mode_constants *const_ptr; + struct radeon_pll *pll; + + radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); + if (radeon_crtc->crtc_id == 1) + pll = &rdev->clock.p2pll; + else + pll = &rdev->clock.p1pll; + + const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); + if (!const_ptr) + return false; + + h_total = const_ptr->hor_total; + v_total = const_ptr->ver_total; + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M || + tv_dac->tv_std == TV_STD_PAL_60) + f_total = NTSC_TV_VFTOTAL + 1; + else + f_total = PAL_TV_VFTOTAL + 1; + + /* adjust positions 1&2 in hor. cod timing table */ + h_offset = tv_dac->h_pos * H_POS_UNIT; + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M) { + h_offset -= 50; + p1 = hor_timing_NTSC[H_TABLE_POS1]; + p2 = hor_timing_NTSC[H_TABLE_POS2]; + } else { + p1 = hor_timing_PAL[H_TABLE_POS1]; + p2 = hor_timing_PAL[H_TABLE_POS2]; + } + + p1 = (u16)((int)p1 + h_offset); + p2 = (u16)((int)p2 - h_offset); + + h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] || + p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]); + + tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1; + tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2; + + /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */ + h_offset = (h_offset * (int)(const_ptr->pix_to_tv)) / 1000; + + /* adjust restart */ + restart = const_ptr->def_restart; + + /* + * convert v_pos TV lines to n. of CRTC pixels + */ + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M || + tv_dac->tv_std == TV_STD_PAL_60) + v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME); + else + v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME); + + restart -= v_offset + h_offset; + + DRM_DEBUG("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n", + const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart); + + tv_dac->tv.hrestart = restart % h_total; + restart /= h_total; + tv_dac->tv.vrestart = restart % v_total; + restart /= v_total; + tv_dac->tv.frestart = restart % f_total; + + DRM_DEBUG("compute_restart: F/H/V=%u,%u,%u\n", + (unsigned)tv_dac->tv.frestart, + (unsigned)tv_dac->tv.vrestart, + (unsigned)tv_dac->tv.hrestart); + + /* compute h_inc from hsize */ + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M) + h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * NTSC_TV_CLOCK_T) / + (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE))); + else + h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * PAL_TV_CLOCK_T) / + (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE))); + + tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) | + ((u32)h_inc << RADEON_H_INC_SHIFT); + + DRM_DEBUG("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc); + + return h_changed; +} + +void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; + const struct radeon_tv_mode_constants *const_ptr; + struct radeon_crtc *radeon_crtc; + int i; + uint16_t pll_ref_freq; + uint32_t vert_space, flicker_removal, tmp; + uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl; + uint32_t tv_modulator_cntl1, tv_modulator_cntl2; + uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2; + uint32_t tv_pll_cntl, tv_pll_cntl1, tv_ftotal; + uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl; + uint32_t m, n, p; + const uint16_t *hor_timing; + const uint16_t *vert_timing; + + const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq); + if (!const_ptr) + return; + + radeon_crtc = to_radeon_crtc(encoder->crtc); + + tv_master_cntl = (RADEON_VIN_ASYNC_RST | + RADEON_CRT_FIFO_CE_EN | + RADEON_TV_FIFO_CE_EN | + RADEON_TV_ON); + + if (!ASIC_IS_R300(rdev)) + tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb; + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J) + tv_master_cntl |= RADEON_RESTART_PHASE_FIX; + + tv_modulator_cntl1 = (RADEON_SLEW_RATE_LIMIT | + RADEON_SYNC_TIP_LEVEL | + RADEON_YFLT_EN | + RADEON_UVFLT_EN | + (6 << RADEON_CY_FILT_BLEND_SHIFT)); + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J) { + tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) | + (0x3b << RADEON_BLANK_LEVEL_SHIFT); + tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) | + ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); + } else if (tv_dac->tv_std == TV_STD_SCART_PAL) { + tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN; + tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) | + ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); + } else { + tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN | + (0x3b << RADEON_SET_UP_LEVEL_SHIFT) | + (0x3b << RADEON_BLANK_LEVEL_SHIFT); + tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) | + ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); + } + + + tv_rgb_cntl = (RADEON_RGB_DITHER_EN + | RADEON_TVOUT_SCALE_EN + | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT) + | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT) + | RADEON_RGB_ATTEN_SEL(0x3) + | RADEON_RGB_ATTEN_VAL(0xc)); + + if (radeon_crtc->crtc_id == 1) + tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2; + else { + if (radeon_crtc->rmx_type != RMX_OFF) + tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX; + else + tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1; + } + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M || + tv_dac->tv_std == TV_STD_PAL_60) + vert_space = const_ptr->ver_total * 2 * 10000 / NTSC_TV_LINES_PER_FRAME; + else + vert_space = const_ptr->ver_total * 2 * 10000 / PAL_TV_LINES_PER_FRAME; + + tmp = RREG32(RADEON_TV_VSCALER_CNTL1); + tmp &= 0xe3ff0000; + tmp |= (vert_space * (1 << FRAC_BITS) / 10000); + tv_vscaler_cntl1 = tmp; + + if (pll_ref_freq == 2700) + tv_vscaler_cntl1 |= RADEON_RESTART_FIELD; + + if (const_ptr->hor_resolution == 1024) + tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT); + else + tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT); + + /* scale up for int divide */ + tmp = const_ptr->ver_total * 2 * 1000; + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M || + tv_dac->tv_std == TV_STD_PAL_60) { + tmp /= NTSC_TV_LINES_PER_FRAME; + } else { + tmp /= PAL_TV_LINES_PER_FRAME; + } + flicker_removal = (tmp + 500) / 1000; + + if (flicker_removal < 3) + flicker_removal = 3; + for (i = 0; i < 6; ++i) { + if (flicker_removal == SLOPE_limit[i]) + break; + } + + tv_y_saw_tooth_cntl = (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) + + 5001) / 10000 / 8 | ((SLOPE_value[i] * + (1 << (FRAC_BITS - 1)) / 8) << 16); + tv_y_fall_cntl = + (YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) | + RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) / + 1024; + tv_y_rise_cntl = RADEON_Y_RISE_PING_PONG| + (flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024; + + tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0; + tv_vscaler_cntl2 |= (0x10 << 24) | + RADEON_DITHER_MODE | + RADEON_Y_OUTPUT_DITHER_EN | + RADEON_UV_OUTPUT_DITHER_EN | + RADEON_UV_TO_BUF_DITHER_EN; + + tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK; + tmp = ((16384 * 256 * 10) / tmp + 5) / 10; + tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000; + tv_dac->tv.timing_cntl = tmp; + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M || + tv_dac->tv_std == TV_STD_PAL_60) + tv_dac_cntl = tv_dac->ntsc_tvdac_adj; + else + tv_dac_cntl = tv_dac->pal_tvdac_adj; + + tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J) + tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; + else + tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J) { + if (pll_ref_freq == 2700) { + m = NTSC_TV_PLL_M_27; + n = NTSC_TV_PLL_N_27; + p = NTSC_TV_PLL_P_27; + } else { + m = NTSC_TV_PLL_M_14; + n = NTSC_TV_PLL_N_14; + p = NTSC_TV_PLL_P_14; + } + } else { + if (pll_ref_freq == 2700) { + m = PAL_TV_PLL_M_27; + n = PAL_TV_PLL_N_27; + p = PAL_TV_PLL_P_27; + } else { + m = PAL_TV_PLL_M_27; + n = PAL_TV_PLL_N_27; + p = PAL_TV_PLL_P_27; + } + } + + tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) | + (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) | + ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) | + (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) | + ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT); + + tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK) << RADEON_TVPCP_SHIFT) | + ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) | + ((1 & RADEON_TVPDC_MASK) << RADEON_TVPDC_SHIFT) | + RADEON_TVCLK_SRC_SEL_TVPLL | + RADEON_TVPLL_TEST_DIS); + + tv_dac->tv.tv_uv_adr = 0xc8; + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M || + tv_dac->tv_std == TV_STD_PAL_60) { + tv_ftotal = NTSC_TV_VFTOTAL; + hor_timing = hor_timing_NTSC; + vert_timing = vert_timing_NTSC; + } else { + hor_timing = hor_timing_PAL; + vert_timing = vert_timing_PAL; + tv_ftotal = PAL_TV_VFTOTAL; + } + + for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) { + if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0) + break; + } + + for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) { + if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0) + break; + } + + radeon_legacy_tv_init_restarts(encoder); + + /* play with DAC_CNTL */ + /* play with GPIOPAD_A */ + /* DISP_OUTPUT_CNTL */ + /* use reference freq */ + + /* program the TV registers */ + WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | + RADEON_CRT_ASYNC_RST | RADEON_TV_FIFO_ASYNC_RST)); + + tmp = RREG32(RADEON_TV_DAC_CNTL); + tmp &= ~RADEON_TV_DAC_NBLANK; + tmp |= RADEON_TV_DAC_BGSLEEP | + RADEON_TV_DAC_RDACPD | + RADEON_TV_DAC_GDACPD | + RADEON_TV_DAC_BDACPD; + WREG32(RADEON_TV_DAC_CNTL, tmp); + + /* TV PLL */ + WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL); + WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl); + WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET); + + radeon_wait_pll_lock(encoder, 200, 800, 135); + + WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET); + + radeon_wait_pll_lock(encoder, 300, 160, 27); + radeon_wait_pll_lock(encoder, 200, 800, 135); + + WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf); + WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL); + + WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK); + WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP); + + /* TV HV */ + WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl); + WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1); + WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1); + WREG32(RADEON_TV_HSTART, const_ptr->hor_start); + + WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1); + WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1); + WREG32(RADEON_TV_FTOTAL, tv_ftotal); + WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1); + WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2); + + WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl); + WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl); + WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl); + + WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | + RADEON_CRT_ASYNC_RST)); + + /* TV restarts */ + radeon_legacy_write_tv_restarts(radeon_encoder); + + /* tv timings */ + radeon_restore_tv_timing_tables(radeon_encoder); + + WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST)); + + /* tv std */ + WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE)); + WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl); + WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1); + WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2); + WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN | + RADEON_C_GRN_EN | + RADEON_CMP_BLU_EN | + RADEON_DAC_DITHER_EN)); + + WREG32(RADEON_TV_CRC_CNTL, 0); + + WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); + + WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) | + (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT))); + WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) | + (0x100 << RADEON_Y_GAIN_SHIFT))); + + WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); + +} + +void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, + uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, + uint32_t *v_total_disp, uint32_t *v_sync_strt_wid) +{ + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + const struct radeon_tv_mode_constants *const_ptr; + uint32_t tmp; + + const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); + if (!const_ptr) + return; + + *h_total_disp = (((const_ptr->hor_resolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) | + (((const_ptr->hor_total / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT); + + tmp = *h_sync_strt_wid; + tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR); + tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) | + (const_ptr->hor_syncstart & 7); + *h_sync_strt_wid = tmp; + + *v_total_disp = ((const_ptr->ver_resolution - 1) << RADEON_CRTC_V_DISP_SHIFT) | + ((const_ptr->ver_total - 1) << RADEON_CRTC_V_TOTAL_SHIFT); + + tmp = *v_sync_strt_wid; + tmp &= ~RADEON_CRTC_V_SYNC_STRT; + tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT); + *v_sync_strt_wid = tmp; +} + +static inline int get_post_div(int value) +{ + int post_div; + switch (value) { + case 1: post_div = 0; break; + case 2: post_div = 1; break; + case 3: post_div = 4; break; + case 4: post_div = 2; break; + case 6: post_div = 6; break; + case 8: post_div = 3; break; + case 12: post_div = 7; break; + case 16: + default: post_div = 5; break; + } + return post_div; +} + +void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, + uint32_t *htotal_cntl, uint32_t *ppll_ref_div, + uint32_t *ppll_div_3, uint32_t *pixclks_cntl) +{ + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + const struct radeon_tv_mode_constants *const_ptr; + + const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); + if (!const_ptr) + return; + + *htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN; + + *ppll_ref_div = const_ptr->crtcPLL_M; + + *ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); + *pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL); + *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK; +} + +void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, + uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, + uint32_t *p2pll_div_0, uint32_t *pixclks_cntl) +{ + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + const struct radeon_tv_mode_constants *const_ptr; + + const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); + if (!const_ptr) + return; + + *htotal2_cntl = (const_ptr->hor_total & 0x7); + + *p2pll_ref_div = const_ptr->crtcPLL_M; + + *p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); + *pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK; + *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK | RADEON_PIXCLK_TV_SRC_SEL; +} + diff --git a/drivers/gpu/drm/radeon/radeon_microcode.h b/drivers/gpu/drm/radeon/radeon_microcode.h deleted file mode 100644 index a348c9e7db1c..000000000000 --- a/drivers/gpu/drm/radeon/radeon_microcode.h +++ /dev/null @@ -1,1844 +0,0 @@ -/* - * Copyright 2007 Advanced Micro Devices, Inc. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef RADEON_MICROCODE_H -#define RADEON_MICROCODE_H - -/* production radeon ucode r1xx-r6xx */ -static const u32 R100_cp_microcode[][2] = { - { 0x21007000, 0000000000 }, - { 0x20007000, 0000000000 }, - { 0x000000b4, 0x00000004 }, - { 0x000000b8, 0x00000004 }, - { 0x6f5b4d4c, 0000000000 }, - { 0x4c4c427f, 0000000000 }, - { 0x5b568a92, 0000000000 }, - { 0x4ca09c6d, 0000000000 }, - { 0xad4c4c4c, 0000000000 }, - { 0x4ce1af3d, 0000000000 }, - { 0xd8afafaf, 0000000000 }, - { 0xd64c4cdc, 0000000000 }, - { 0x4cd10d10, 0000000000 }, - { 0x000f0000, 0x00000016 }, - { 0x362f242d, 0000000000 }, - { 0x00000012, 0x00000004 }, - { 0x000f0000, 0x00000016 }, - { 0x362f282d, 0000000000 }, - { 0x000380e7, 0x00000002 }, - { 0x04002c97, 0x00000002 }, - { 0x000f0001, 0x00000016 }, - { 0x333a3730, 0000000000 }, - { 0x000077ef, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000021, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000021, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000021, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00000017, 0x00000004 }, - { 0x0003802b, 0x00000002 }, - { 0x040067e0, 0x00000002 }, - { 0x00000017, 0x00000004 }, - { 0x000077e0, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x000037e1, 0x00000002 }, - { 0x040067e1, 0x00000006 }, - { 0x000077e0, 0x00000002 }, - { 0x000077e1, 0x00000002 }, - { 0x000077e1, 0x00000006 }, - { 0xffffffff, 0000000000 }, - { 0x10000000, 0000000000 }, - { 0x0003802b, 0x00000002 }, - { 0x040067e0, 0x00000006 }, - { 0x00007675, 0x00000002 }, - { 0x00007676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0003802c, 0x00000002 }, - { 0x04002676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0000002f, 0x00000018 }, - { 0x0000002f, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x00000030, 0x00000018 }, - { 0x00000030, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x01605000, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00098000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x64c0603e, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00080000, 0x00000016 }, - { 0000000000, 0000000000 }, - { 0x0400251d, 0x00000002 }, - { 0x00007580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x04002580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x00000049, 0x00000004 }, - { 0x00005000, 0000000000 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x00019000, 0x00000002 }, - { 0x00011055, 0x00000014 }, - { 0x00000055, 0x00000012 }, - { 0x0400250f, 0x00000002 }, - { 0x0000504f, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00007565, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x00000058, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x01e655b4, 0x00000002 }, - { 0x4401b0e4, 0x00000002 }, - { 0x01c110e4, 0x00000002 }, - { 0x26667066, 0x00000018 }, - { 0x040c2565, 0x00000002 }, - { 0x00000066, 0x00000018 }, - { 0x04002564, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x0000005d, 0x00000004 }, - { 0x00401069, 0x00000008 }, - { 0x00101000, 0x00000002 }, - { 0x000d80ff, 0x00000002 }, - { 0x0080006c, 0x00000008 }, - { 0x000f9000, 0x00000002 }, - { 0x000e00ff, 0x00000002 }, - { 0000000000, 0x00000006 }, - { 0x0000008f, 0x00000018 }, - { 0x0000005b, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00007576, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00009000, 0x00000002 }, - { 0x00041000, 0x00000002 }, - { 0x0c00350e, 0x00000002 }, - { 0x00049000, 0x00000002 }, - { 0x00051000, 0x00000002 }, - { 0x01e785f8, 0x00000002 }, - { 0x00200000, 0x00000002 }, - { 0x0060007e, 0x0000000c }, - { 0x00007563, 0x00000002 }, - { 0x006075f0, 0x00000021 }, - { 0x20007073, 0x00000004 }, - { 0x00005073, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00007576, 0x00000002 }, - { 0x00007577, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x0000750f, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00600083, 0x0000000c }, - { 0x006075f0, 0x00000021 }, - { 0x000075f8, 0x00000002 }, - { 0x00000083, 0x00000004 }, - { 0x000a750e, 0x00000002 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x0020750f, 0x00000002 }, - { 0x00600086, 0x00000004 }, - { 0x00007570, 0x00000002 }, - { 0x00007571, 0x00000002 }, - { 0x00007572, 0x00000006 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00005000, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00007568, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000095, 0x0000000c }, - { 0x00058000, 0x00000002 }, - { 0x0c607562, 0x00000002 }, - { 0x00000097, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00600096, 0x00000004 }, - { 0x400070e5, 0000000000 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x000380e5, 0x00000002 }, - { 0x000000a8, 0x0000001c }, - { 0x000650aa, 0x00000018 }, - { 0x040025bb, 0x00000002 }, - { 0x000610ab, 0x00000018 }, - { 0x040075bc, 0000000000 }, - { 0x000075bb, 0x00000002 }, - { 0x000075bc, 0000000000 }, - { 0x00090000, 0x00000006 }, - { 0x00090000, 0x00000002 }, - { 0x000d8002, 0x00000006 }, - { 0x00007832, 0x00000002 }, - { 0x00005000, 0x00000002 }, - { 0x000380e7, 0x00000002 }, - { 0x04002c97, 0x00000002 }, - { 0x00007820, 0x00000002 }, - { 0x00007821, 0x00000002 }, - { 0x00007800, 0000000000 }, - { 0x01200000, 0x00000002 }, - { 0x20077000, 0x00000002 }, - { 0x01200000, 0x00000002 }, - { 0x20007000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x0120751b, 0x00000002 }, - { 0x8040750a, 0x00000002 }, - { 0x8040750b, 0x00000002 }, - { 0x00110000, 0x00000002 }, - { 0x000380e5, 0x00000002 }, - { 0x000000c6, 0x0000001c }, - { 0x000610ab, 0x00000018 }, - { 0x844075bd, 0x00000002 }, - { 0x000610aa, 0x00000018 }, - { 0x840075bb, 0x00000002 }, - { 0x000610ab, 0x00000018 }, - { 0x844075bc, 0x00000002 }, - { 0x000000c9, 0x00000004 }, - { 0x804075bd, 0x00000002 }, - { 0x800075bb, 0x00000002 }, - { 0x804075bc, 0x00000002 }, - { 0x00108000, 0x00000002 }, - { 0x01400000, 0x00000002 }, - { 0x006000cd, 0x0000000c }, - { 0x20c07000, 0x00000020 }, - { 0x000000cf, 0x00000012 }, - { 0x00800000, 0x00000006 }, - { 0x0080751d, 0x00000006 }, - { 0000000000, 0000000000 }, - { 0x0000775c, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00661000, 0x00000002 }, - { 0x0460275d, 0x00000020 }, - { 0x00004000, 0000000000 }, - { 0x01e00830, 0x00000002 }, - { 0x21007000, 0000000000 }, - { 0x6464614d, 0000000000 }, - { 0x69687420, 0000000000 }, - { 0x00000073, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x00005000, 0x00000002 }, - { 0x000380d0, 0x00000002 }, - { 0x040025e0, 0x00000002 }, - { 0x000075e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000380e0, 0x00000002 }, - { 0x04002394, 0x00000002 }, - { 0x00005000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x00000008, 0000000000 }, - { 0x00000004, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 R200_cp_microcode[][2] = { - { 0x21007000, 0000000000 }, - { 0x20007000, 0000000000 }, - { 0x000000bf, 0x00000004 }, - { 0x000000c3, 0x00000004 }, - { 0x7a685e5d, 0000000000 }, - { 0x5d5d5588, 0000000000 }, - { 0x68659197, 0000000000 }, - { 0x5da19f78, 0000000000 }, - { 0x5d5d5d5d, 0000000000 }, - { 0x5dee5d50, 0000000000 }, - { 0xf2acacac, 0000000000 }, - { 0xe75df9e9, 0000000000 }, - { 0xb1dd0e11, 0000000000 }, - { 0xe2afafaf, 0000000000 }, - { 0x000f0000, 0x00000016 }, - { 0x452f232d, 0000000000 }, - { 0x00000013, 0x00000004 }, - { 0x000f0000, 0x00000016 }, - { 0x452f272d, 0000000000 }, - { 0x000f0001, 0x00000016 }, - { 0x3e4d4a37, 0000000000 }, - { 0x000077ef, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00000016, 0x00000004 }, - { 0x0003802a, 0x00000002 }, - { 0x040067e0, 0x00000002 }, - { 0x00000016, 0x00000004 }, - { 0x000077e0, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x000037e1, 0x00000002 }, - { 0x040067e1, 0x00000006 }, - { 0x000077e0, 0x00000002 }, - { 0x000077e1, 0x00000002 }, - { 0x000077e1, 0x00000006 }, - { 0xffffffff, 0000000000 }, - { 0x10000000, 0000000000 }, - { 0x07f007f0, 0000000000 }, - { 0x0003802a, 0x00000002 }, - { 0x040067e0, 0x00000006 }, - { 0x0003802c, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002743, 0x00000002 }, - { 0x00007675, 0x00000002 }, - { 0x00007676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0003802c, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002743, 0x00000002 }, - { 0x00007676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0003802b, 0x00000002 }, - { 0x04002676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x0003802c, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002743, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0003802c, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002743, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0000002f, 0x00000018 }, - { 0x0000002f, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x00000037, 0x00000018 }, - { 0x00000037, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x01605000, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00098000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x64c06051, 0x00000004 }, - { 0x00080000, 0x00000016 }, - { 0000000000, 0000000000 }, - { 0x0400251d, 0x00000002 }, - { 0x00007580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x04002580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x0000005a, 0x00000004 }, - { 0x00005000, 0000000000 }, - { 0x00061000, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x00019000, 0x00000002 }, - { 0x00011064, 0x00000014 }, - { 0x00000064, 0x00000012 }, - { 0x0400250f, 0x00000002 }, - { 0x0000505e, 0x00000004 }, - { 0x00007565, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x00000065, 0x00000004 }, - { 0x01e655b4, 0x00000002 }, - { 0x4401b0f0, 0x00000002 }, - { 0x01c110f0, 0x00000002 }, - { 0x26667071, 0x00000018 }, - { 0x040c2565, 0x00000002 }, - { 0x00000071, 0x00000018 }, - { 0x04002564, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x00000068, 0x00000004 }, - { 0x00401074, 0x00000008 }, - { 0x00101000, 0x00000002 }, - { 0x000d80ff, 0x00000002 }, - { 0x00800077, 0x00000008 }, - { 0x000f9000, 0x00000002 }, - { 0x000e00ff, 0x00000002 }, - { 0000000000, 0x00000006 }, - { 0x00000094, 0x00000018 }, - { 0x00000068, 0x00000004 }, - { 0x00007576, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00009000, 0x00000002 }, - { 0x00041000, 0x00000002 }, - { 0x0c00350e, 0x00000002 }, - { 0x00049000, 0x00000002 }, - { 0x00051000, 0x00000002 }, - { 0x01e785f8, 0x00000002 }, - { 0x00200000, 0x00000002 }, - { 0x00600087, 0x0000000c }, - { 0x00007563, 0x00000002 }, - { 0x006075f0, 0x00000021 }, - { 0x2000707c, 0x00000004 }, - { 0x0000507c, 0x00000004 }, - { 0x00007576, 0x00000002 }, - { 0x00007577, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x0000750f, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x0060008a, 0x0000000c }, - { 0x006075f0, 0x00000021 }, - { 0x000075f8, 0x00000002 }, - { 0x0000008a, 0x00000004 }, - { 0x000a750e, 0x00000002 }, - { 0x0020750f, 0x00000002 }, - { 0x0060008d, 0x00000004 }, - { 0x00007570, 0x00000002 }, - { 0x00007571, 0x00000002 }, - { 0x00007572, 0x00000006 }, - { 0x00005000, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00007568, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000098, 0x0000000c }, - { 0x00058000, 0x00000002 }, - { 0x0c607562, 0x00000002 }, - { 0x0000009a, 0x00000004 }, - { 0x00600099, 0x00000004 }, - { 0x400070f1, 0000000000 }, - { 0x000380f1, 0x00000002 }, - { 0x000000a7, 0x0000001c }, - { 0x000650a9, 0x00000018 }, - { 0x040025bb, 0x00000002 }, - { 0x000610aa, 0x00000018 }, - { 0x040075bc, 0000000000 }, - { 0x000075bb, 0x00000002 }, - { 0x000075bc, 0000000000 }, - { 0x00090000, 0x00000006 }, - { 0x00090000, 0x00000002 }, - { 0x000d8002, 0x00000006 }, - { 0x00005000, 0x00000002 }, - { 0x00007821, 0x00000002 }, - { 0x00007800, 0000000000 }, - { 0x00007821, 0x00000002 }, - { 0x00007800, 0000000000 }, - { 0x01665000, 0x00000002 }, - { 0x000a0000, 0x00000002 }, - { 0x000671cc, 0x00000002 }, - { 0x0286f1cd, 0x00000002 }, - { 0x000000b7, 0x00000010 }, - { 0x21007000, 0000000000 }, - { 0x000000be, 0x0000001c }, - { 0x00065000, 0x00000002 }, - { 0x000a0000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x000b0000, 0x00000002 }, - { 0x38067000, 0x00000002 }, - { 0x000a00ba, 0x00000004 }, - { 0x20007000, 0000000000 }, - { 0x01200000, 0x00000002 }, - { 0x20077000, 0x00000002 }, - { 0x01200000, 0x00000002 }, - { 0x20007000, 0000000000 }, - { 0x00061000, 0x00000002 }, - { 0x0120751b, 0x00000002 }, - { 0x8040750a, 0x00000002 }, - { 0x8040750b, 0x00000002 }, - { 0x00110000, 0x00000002 }, - { 0x000380f1, 0x00000002 }, - { 0x000000d1, 0x0000001c }, - { 0x000610aa, 0x00000018 }, - { 0x844075bd, 0x00000002 }, - { 0x000610a9, 0x00000018 }, - { 0x840075bb, 0x00000002 }, - { 0x000610aa, 0x00000018 }, - { 0x844075bc, 0x00000002 }, - { 0x000000d4, 0x00000004 }, - { 0x804075bd, 0x00000002 }, - { 0x800075bb, 0x00000002 }, - { 0x804075bc, 0x00000002 }, - { 0x00108000, 0x00000002 }, - { 0x01400000, 0x00000002 }, - { 0x006000d8, 0x0000000c }, - { 0x20c07000, 0x00000020 }, - { 0x000000da, 0x00000012 }, - { 0x00800000, 0x00000006 }, - { 0x0080751d, 0x00000006 }, - { 0x000025bb, 0x00000002 }, - { 0x000040d4, 0x00000004 }, - { 0x0000775c, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00661000, 0x00000002 }, - { 0x0460275d, 0x00000020 }, - { 0x00004000, 0000000000 }, - { 0x00007999, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00661000, 0x00000002 }, - { 0x0460299b, 0x00000020 }, - { 0x00004000, 0000000000 }, - { 0x01e00830, 0x00000002 }, - { 0x21007000, 0000000000 }, - { 0x00005000, 0x00000002 }, - { 0x00038056, 0x00000002 }, - { 0x040025e0, 0x00000002 }, - { 0x000075e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000380ed, 0x00000002 }, - { 0x04007394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000078c4, 0x00000002 }, - { 0x000078c5, 0x00000002 }, - { 0x000078c6, 0x00000002 }, - { 0x00007924, 0x00000002 }, - { 0x00007925, 0x00000002 }, - { 0x00007926, 0x00000002 }, - { 0x000000f2, 0x00000004 }, - { 0x00007924, 0x00000002 }, - { 0x00007925, 0x00000002 }, - { 0x00007926, 0x00000002 }, - { 0x000000f9, 0x00000004 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 R300_cp_microcode[][2] = { - { 0x4200e000, 0000000000 }, - { 0x4000e000, 0000000000 }, - { 0x000000ae, 0x00000008 }, - { 0x000000b2, 0x00000008 }, - { 0x67554b4a, 0000000000 }, - { 0x4a4a4475, 0000000000 }, - { 0x55527d83, 0000000000 }, - { 0x4a8c8b65, 0000000000 }, - { 0x4aef4af6, 0000000000 }, - { 0x4ae14a4a, 0000000000 }, - { 0xe4979797, 0000000000 }, - { 0xdb4aebdd, 0000000000 }, - { 0x9ccc4a4a, 0000000000 }, - { 0xd1989898, 0000000000 }, - { 0x4a0f9ad6, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 0x0000e857, 0x00000004 }, - { 0x000d001e, 0x00000038 }, - { 0x0000e824, 0x00000004 }, - { 0x000d0020, 0x00000038 }, - { 0x0000e825, 0x00000004 }, - { 0x000d0022, 0x00000038 }, - { 0x0000e830, 0x00000004 }, - { 0x000d0024, 0x00000038 }, - { 0x0000f0c0, 0x00000004 }, - { 0x000d0026, 0x00000038 }, - { 0x0000f0c1, 0x00000004 }, - { 0x000d0028, 0x00000038 }, - { 0x0000f041, 0x00000004 }, - { 0x000d002a, 0x00000038 }, - { 0x0000f184, 0x00000004 }, - { 0x000d002c, 0x00000038 }, - { 0x0000f185, 0x00000004 }, - { 0x000d002e, 0x00000038 }, - { 0x0000f186, 0x00000004 }, - { 0x000d0030, 0x00000038 }, - { 0x0000f187, 0x00000004 }, - { 0x000d0032, 0x00000038 }, - { 0x0000f180, 0x00000004 }, - { 0x000d0034, 0x00000038 }, - { 0x0000f393, 0x00000004 }, - { 0x000d0036, 0x00000038 }, - { 0x0000f38a, 0x00000004 }, - { 0x000d0038, 0x00000038 }, - { 0x0000f38e, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000043, 0x00000018 }, - { 0x00cce800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x0000003a, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x2000451d, 0x00000004 }, - { 0x0000e580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x08004580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x00000047, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x00032000, 0x00000004 }, - { 0x00022051, 0x00000028 }, - { 0x00000051, 0x00000024 }, - { 0x0800450f, 0x00000004 }, - { 0x0000a04b, 0x00000008 }, - { 0x0000e565, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000052, 0x00000008 }, - { 0x03cca5b4, 0x00000004 }, - { 0x05432000, 0x00000004 }, - { 0x00022000, 0x00000004 }, - { 0x4ccce05e, 0x00000030 }, - { 0x08274565, 0x00000004 }, - { 0x0000005e, 0x00000030 }, - { 0x08004564, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000055, 0x00000008 }, - { 0x00802061, 0x00000010 }, - { 0x00202000, 0x00000004 }, - { 0x001b00ff, 0x00000004 }, - { 0x01000064, 0x00000010 }, - { 0x001f2000, 0x00000004 }, - { 0x001c00ff, 0x00000004 }, - { 0000000000, 0x0000000c }, - { 0x00000080, 0x00000030 }, - { 0x00000055, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x00012000, 0x00000004 }, - { 0x00082000, 0x00000004 }, - { 0x1800650e, 0x00000004 }, - { 0x00092000, 0x00000004 }, - { 0x000a2000, 0x00000004 }, - { 0x000f0000, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x00000074, 0x00000018 }, - { 0x0000e563, 0x00000004 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000069, 0x00000008 }, - { 0x0000a069, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x0000e577, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x0000e50f, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000077, 0x00000018 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000077, 0x00000008 }, - { 0x0014e50e, 0x00000004 }, - { 0x0040e50f, 0x00000004 }, - { 0x00c0007a, 0x00000008 }, - { 0x0000e570, 0x00000004 }, - { 0x0000e571, 0x00000004 }, - { 0x0000e572, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000e568, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00000084, 0x00000018 }, - { 0x000b0000, 0x00000004 }, - { 0x18c0e562, 0x00000004 }, - { 0x00000086, 0x00000008 }, - { 0x00c00085, 0x00000008 }, - { 0x000700e3, 0x00000004 }, - { 0x00000092, 0x00000038 }, - { 0x000ca094, 0x00000030 }, - { 0x080045bb, 0x00000004 }, - { 0x000c2095, 0x00000030 }, - { 0x0800e5bc, 0000000000 }, - { 0x0000e5bb, 0x00000004 }, - { 0x0000e5bc, 0000000000 }, - { 0x00120000, 0x0000000c }, - { 0x00120000, 0x00000004 }, - { 0x001b0002, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e800, 0000000000 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e82e, 0000000000 }, - { 0x02cca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000ce1cc, 0x00000004 }, - { 0x050de1cd, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x000000a4, 0x00000018 }, - { 0x00c0a000, 0x00000004 }, - { 0x000000a1, 0x00000008 }, - { 0x000000a6, 0x00000020 }, - { 0x4200e000, 0000000000 }, - { 0x000000ad, 0x00000038 }, - { 0x000ca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00160000, 0x00000004 }, - { 0x700ce000, 0x00000004 }, - { 0x001400a9, 0x00000008 }, - { 0x4000e000, 0000000000 }, - { 0x02400000, 0x00000004 }, - { 0x400ee000, 0x00000004 }, - { 0x02400000, 0x00000004 }, - { 0x4000e000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0240e51b, 0x00000004 }, - { 0x0080e50a, 0x00000005 }, - { 0x0080e50b, 0x00000005 }, - { 0x00220000, 0x00000004 }, - { 0x000700e3, 0x00000004 }, - { 0x000000c0, 0x00000038 }, - { 0x000c2095, 0x00000030 }, - { 0x0880e5bd, 0x00000005 }, - { 0x000c2094, 0x00000030 }, - { 0x0800e5bb, 0x00000005 }, - { 0x000c2095, 0x00000030 }, - { 0x0880e5bc, 0x00000005 }, - { 0x000000c3, 0x00000008 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000c7, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000c9, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080c3, 0x00000008 }, - { 0x0000f3ce, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053cf, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f3d2, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053d3, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f39d, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c0539e, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700e0, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x0000e8c4, 0x00000004 }, - { 0x0000e8c5, 0x00000004 }, - { 0x0000e8c6, 0x00000004 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000e4, 0x00000008 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000eb, 0x00000008 }, - { 0x02c02000, 0x00000004 }, - { 0x00060000, 0x00000004 }, - { 0x000000f3, 0x00000034 }, - { 0x000000f0, 0x00000008 }, - { 0x00008000, 0x00000004 }, - { 0xc000e000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x001d0018, 0x00000004 }, - { 0x001a0001, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0x0500a04a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 R420_cp_microcode[][2] = { - { 0x4200e000, 0000000000 }, - { 0x4000e000, 0000000000 }, - { 0x00000099, 0x00000008 }, - { 0x0000009d, 0x00000008 }, - { 0x4a554b4a, 0000000000 }, - { 0x4a4a4467, 0000000000 }, - { 0x55526f75, 0000000000 }, - { 0x4a7e7d65, 0000000000 }, - { 0xd9d3dff6, 0000000000 }, - { 0x4ac54a4a, 0000000000 }, - { 0xc8828282, 0000000000 }, - { 0xbf4acfc1, 0000000000 }, - { 0x87b04a4a, 0000000000 }, - { 0xb5838383, 0000000000 }, - { 0x4a0f85ba, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 0x0000e857, 0x00000004 }, - { 0x000d001e, 0x00000038 }, - { 0x0000e824, 0x00000004 }, - { 0x000d0020, 0x00000038 }, - { 0x0000e825, 0x00000004 }, - { 0x000d0022, 0x00000038 }, - { 0x0000e830, 0x00000004 }, - { 0x000d0024, 0x00000038 }, - { 0x0000f0c0, 0x00000004 }, - { 0x000d0026, 0x00000038 }, - { 0x0000f0c1, 0x00000004 }, - { 0x000d0028, 0x00000038 }, - { 0x0000f041, 0x00000004 }, - { 0x000d002a, 0x00000038 }, - { 0x0000f184, 0x00000004 }, - { 0x000d002c, 0x00000038 }, - { 0x0000f185, 0x00000004 }, - { 0x000d002e, 0x00000038 }, - { 0x0000f186, 0x00000004 }, - { 0x000d0030, 0x00000038 }, - { 0x0000f187, 0x00000004 }, - { 0x000d0032, 0x00000038 }, - { 0x0000f180, 0x00000004 }, - { 0x000d0034, 0x00000038 }, - { 0x0000f393, 0x00000004 }, - { 0x000d0036, 0x00000038 }, - { 0x0000f38a, 0x00000004 }, - { 0x000d0038, 0x00000038 }, - { 0x0000f38e, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000043, 0x00000018 }, - { 0x00cce800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x0000003a, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x2000451d, 0x00000004 }, - { 0x0000e580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x08004580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x00000047, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x00032000, 0x00000004 }, - { 0x00022051, 0x00000028 }, - { 0x00000051, 0x00000024 }, - { 0x0800450f, 0x00000004 }, - { 0x0000a04b, 0x00000008 }, - { 0x0000e565, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000052, 0x00000008 }, - { 0x03cca5b4, 0x00000004 }, - { 0x05432000, 0x00000004 }, - { 0x00022000, 0x00000004 }, - { 0x4ccce05e, 0x00000030 }, - { 0x08274565, 0x00000004 }, - { 0x0000005e, 0x00000030 }, - { 0x08004564, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000055, 0x00000008 }, - { 0x00802061, 0x00000010 }, - { 0x00202000, 0x00000004 }, - { 0x001b00ff, 0x00000004 }, - { 0x01000064, 0x00000010 }, - { 0x001f2000, 0x00000004 }, - { 0x001c00ff, 0x00000004 }, - { 0000000000, 0x0000000c }, - { 0x00000072, 0x00000030 }, - { 0x00000055, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x0000e577, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x0000e50f, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000069, 0x00000018 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000069, 0x00000008 }, - { 0x0014e50e, 0x00000004 }, - { 0x0040e50f, 0x00000004 }, - { 0x00c0006c, 0x00000008 }, - { 0x0000e570, 0x00000004 }, - { 0x0000e571, 0x00000004 }, - { 0x0000e572, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000e568, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00000076, 0x00000018 }, - { 0x000b0000, 0x00000004 }, - { 0x18c0e562, 0x00000004 }, - { 0x00000078, 0x00000008 }, - { 0x00c00077, 0x00000008 }, - { 0x000700c7, 0x00000004 }, - { 0x00000080, 0x00000038 }, - { 0x0000e5bb, 0x00000004 }, - { 0x0000e5bc, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e800, 0000000000 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e82e, 0000000000 }, - { 0x02cca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000ce1cc, 0x00000004 }, - { 0x050de1cd, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x0000008f, 0x00000018 }, - { 0x00c0a000, 0x00000004 }, - { 0x0000008c, 0x00000008 }, - { 0x00000091, 0x00000020 }, - { 0x4200e000, 0000000000 }, - { 0x00000098, 0x00000038 }, - { 0x000ca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00160000, 0x00000004 }, - { 0x700ce000, 0x00000004 }, - { 0x00140094, 0x00000008 }, - { 0x4000e000, 0000000000 }, - { 0x02400000, 0x00000004 }, - { 0x400ee000, 0x00000004 }, - { 0x02400000, 0x00000004 }, - { 0x4000e000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0240e51b, 0x00000004 }, - { 0x0080e50a, 0x00000005 }, - { 0x0080e50b, 0x00000005 }, - { 0x00220000, 0x00000004 }, - { 0x000700c7, 0x00000004 }, - { 0x000000a4, 0x00000038 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000ab, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000ad, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080a7, 0x00000008 }, - { 0x0000f3ce, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053cf, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f3d2, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053d3, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f39d, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c0539e, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700c4, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x0000e8c4, 0x00000004 }, - { 0x0000e8c5, 0x00000004 }, - { 0x0000e8c6, 0x00000004 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000c8, 0x00000008 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000cf, 0x00000008 }, - { 0x02c02000, 0x00000004 }, - { 0x00060000, 0x00000004 }, - { 0x000000d7, 0x00000034 }, - { 0x000000d4, 0x00000008 }, - { 0x00008000, 0x00000004 }, - { 0xc000e000, 0000000000 }, - { 0x0000e1cc, 0x00000004 }, - { 0x0500e1cd, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x000000de, 0x00000034 }, - { 0x000000da, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x0019e1cc, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x0500a000, 0x00000004 }, - { 0x080041cd, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x001d0018, 0x00000004 }, - { 0x001a0001, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0x0500a04a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 RS600_cp_microcode[][2] = { - { 0x4200e000, 0000000000 }, - { 0x4000e000, 0000000000 }, - { 0x000000a0, 0x00000008 }, - { 0x000000a4, 0x00000008 }, - { 0x4a554b4a, 0000000000 }, - { 0x4a4a4467, 0000000000 }, - { 0x55526f75, 0000000000 }, - { 0x4a7e7d65, 0000000000 }, - { 0x4ae74af6, 0000000000 }, - { 0x4ad34a4a, 0000000000 }, - { 0xd6898989, 0000000000 }, - { 0xcd4addcf, 0000000000 }, - { 0x8ebe4ae2, 0000000000 }, - { 0xc38a8a8a, 0000000000 }, - { 0x4a0f8cc8, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 0x0000e857, 0x00000004 }, - { 0x000d001e, 0x00000038 }, - { 0x0000e824, 0x00000004 }, - { 0x000d0020, 0x00000038 }, - { 0x0000e825, 0x00000004 }, - { 0x000d0022, 0x00000038 }, - { 0x0000e830, 0x00000004 }, - { 0x000d0024, 0x00000038 }, - { 0x0000f0c0, 0x00000004 }, - { 0x000d0026, 0x00000038 }, - { 0x0000f0c1, 0x00000004 }, - { 0x000d0028, 0x00000038 }, - { 0x0000f041, 0x00000004 }, - { 0x000d002a, 0x00000038 }, - { 0x0000f184, 0x00000004 }, - { 0x000d002c, 0x00000038 }, - { 0x0000f185, 0x00000004 }, - { 0x000d002e, 0x00000038 }, - { 0x0000f186, 0x00000004 }, - { 0x000d0030, 0x00000038 }, - { 0x0000f187, 0x00000004 }, - { 0x000d0032, 0x00000038 }, - { 0x0000f180, 0x00000004 }, - { 0x000d0034, 0x00000038 }, - { 0x0000f393, 0x00000004 }, - { 0x000d0036, 0x00000038 }, - { 0x0000f38a, 0x00000004 }, - { 0x000d0038, 0x00000038 }, - { 0x0000f38e, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000043, 0x00000018 }, - { 0x00cce800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x0000003a, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x2000451d, 0x00000004 }, - { 0x0000e580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x08004580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x00000047, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x00032000, 0x00000004 }, - { 0x00022051, 0x00000028 }, - { 0x00000051, 0x00000024 }, - { 0x0800450f, 0x00000004 }, - { 0x0000a04b, 0x00000008 }, - { 0x0000e565, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000052, 0x00000008 }, - { 0x03cca5b4, 0x00000004 }, - { 0x05432000, 0x00000004 }, - { 0x00022000, 0x00000004 }, - { 0x4ccce05e, 0x00000030 }, - { 0x08274565, 0x00000004 }, - { 0x0000005e, 0x00000030 }, - { 0x08004564, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000055, 0x00000008 }, - { 0x00802061, 0x00000010 }, - { 0x00202000, 0x00000004 }, - { 0x001b00ff, 0x00000004 }, - { 0x01000064, 0x00000010 }, - { 0x001f2000, 0x00000004 }, - { 0x001c00ff, 0x00000004 }, - { 0000000000, 0x0000000c }, - { 0x00000072, 0x00000030 }, - { 0x00000055, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x0000e577, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x0000e50f, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000069, 0x00000018 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000069, 0x00000008 }, - { 0x0014e50e, 0x00000004 }, - { 0x0040e50f, 0x00000004 }, - { 0x00c0006c, 0x00000008 }, - { 0x0000e570, 0x00000004 }, - { 0x0000e571, 0x00000004 }, - { 0x0000e572, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000e568, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00000076, 0x00000018 }, - { 0x000b0000, 0x00000004 }, - { 0x18c0e562, 0x00000004 }, - { 0x00000078, 0x00000008 }, - { 0x00c00077, 0x00000008 }, - { 0x000700d5, 0x00000004 }, - { 0x00000084, 0x00000038 }, - { 0x000ca086, 0x00000030 }, - { 0x080045bb, 0x00000004 }, - { 0x000c2087, 0x00000030 }, - { 0x0800e5bc, 0000000000 }, - { 0x0000e5bb, 0x00000004 }, - { 0x0000e5bc, 0000000000 }, - { 0x00120000, 0x0000000c }, - { 0x00120000, 0x00000004 }, - { 0x001b0002, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e800, 0000000000 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e82e, 0000000000 }, - { 0x02cca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000ce1cc, 0x00000004 }, - { 0x050de1cd, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x00000096, 0x00000018 }, - { 0x00c0a000, 0x00000004 }, - { 0x00000093, 0x00000008 }, - { 0x00000098, 0x00000020 }, - { 0x4200e000, 0000000000 }, - { 0x0000009f, 0x00000038 }, - { 0x000ca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00160000, 0x00000004 }, - { 0x700ce000, 0x00000004 }, - { 0x0014009b, 0x00000008 }, - { 0x4000e000, 0000000000 }, - { 0x02400000, 0x00000004 }, - { 0x400ee000, 0x00000004 }, - { 0x02400000, 0x00000004 }, - { 0x4000e000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0240e51b, 0x00000004 }, - { 0x0080e50a, 0x00000005 }, - { 0x0080e50b, 0x00000005 }, - { 0x00220000, 0x00000004 }, - { 0x000700d5, 0x00000004 }, - { 0x000000b2, 0x00000038 }, - { 0x000c2087, 0x00000030 }, - { 0x0880e5bd, 0x00000005 }, - { 0x000c2086, 0x00000030 }, - { 0x0800e5bb, 0x00000005 }, - { 0x000c2087, 0x00000030 }, - { 0x0880e5bc, 0x00000005 }, - { 0x000000b5, 0x00000008 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000b9, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000bb, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080b5, 0x00000008 }, - { 0x0000f3ce, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053cf, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f3d2, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053d3, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f39d, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c0539e, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700d2, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x0000e8c4, 0x00000004 }, - { 0x0000e8c5, 0x00000004 }, - { 0x0000e8c6, 0x00000004 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000d6, 0x00000008 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000dd, 0x00000008 }, - { 0x00e00116, 0000000000 }, - { 0x000700e1, 0x00000004 }, - { 0x0800401c, 0x00000004 }, - { 0x200050e7, 0x00000004 }, - { 0x0000e01d, 0x00000004 }, - { 0x000000e4, 0x00000008 }, - { 0x02c02000, 0x00000004 }, - { 0x00060000, 0x00000004 }, - { 0x000000eb, 0x00000034 }, - { 0x000000e8, 0x00000008 }, - { 0x00008000, 0x00000004 }, - { 0xc000e000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x001d0018, 0x00000004 }, - { 0x001a0001, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0x0500a04a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 RS690_cp_microcode[][2] = { - { 0x000000dd, 0x00000008 }, - { 0x000000df, 0x00000008 }, - { 0x000000a0, 0x00000008 }, - { 0x000000a4, 0x00000008 }, - { 0x4a554b4a, 0000000000 }, - { 0x4a4a4467, 0000000000 }, - { 0x55526f75, 0000000000 }, - { 0x4a7e7d65, 0000000000 }, - { 0x4ad74af6, 0000000000 }, - { 0x4ac94a4a, 0000000000 }, - { 0xcc898989, 0000000000 }, - { 0xc34ad3c5, 0000000000 }, - { 0x8e4a4a4a, 0000000000 }, - { 0x4a8a8a8a, 0000000000 }, - { 0x4a0f8c4a, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 0x0000e857, 0x00000004 }, - { 0x000d001e, 0x00000038 }, - { 0x0000e824, 0x00000004 }, - { 0x000d0020, 0x00000038 }, - { 0x0000e825, 0x00000004 }, - { 0x000d0022, 0x00000038 }, - { 0x0000e830, 0x00000004 }, - { 0x000d0024, 0x00000038 }, - { 0x0000f0c0, 0x00000004 }, - { 0x000d0026, 0x00000038 }, - { 0x0000f0c1, 0x00000004 }, - { 0x000d0028, 0x00000038 }, - { 0x0000f041, 0x00000004 }, - { 0x000d002a, 0x00000038 }, - { 0x0000f184, 0x00000004 }, - { 0x000d002c, 0x00000038 }, - { 0x0000f185, 0x00000004 }, - { 0x000d002e, 0x00000038 }, - { 0x0000f186, 0x00000004 }, - { 0x000d0030, 0x00000038 }, - { 0x0000f187, 0x00000004 }, - { 0x000d0032, 0x00000038 }, - { 0x0000f180, 0x00000004 }, - { 0x000d0034, 0x00000038 }, - { 0x0000f393, 0x00000004 }, - { 0x000d0036, 0x00000038 }, - { 0x0000f38a, 0x00000004 }, - { 0x000d0038, 0x00000038 }, - { 0x0000f38e, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000043, 0x00000018 }, - { 0x00cce800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x0000003a, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x2000451d, 0x00000004 }, - { 0x0000e580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x08004580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x00000047, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x00032000, 0x00000004 }, - { 0x00022051, 0x00000028 }, - { 0x00000051, 0x00000024 }, - { 0x0800450f, 0x00000004 }, - { 0x0000a04b, 0x00000008 }, - { 0x0000e565, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000052, 0x00000008 }, - { 0x03cca5b4, 0x00000004 }, - { 0x05432000, 0x00000004 }, - { 0x00022000, 0x00000004 }, - { 0x4ccce05e, 0x00000030 }, - { 0x08274565, 0x00000004 }, - { 0x0000005e, 0x00000030 }, - { 0x08004564, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000055, 0x00000008 }, - { 0x00802061, 0x00000010 }, - { 0x00202000, 0x00000004 }, - { 0x001b00ff, 0x00000004 }, - { 0x01000064, 0x00000010 }, - { 0x001f2000, 0x00000004 }, - { 0x001c00ff, 0x00000004 }, - { 0000000000, 0x0000000c }, - { 0x00000072, 0x00000030 }, - { 0x00000055, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x0000e577, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x0000e50f, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000069, 0x00000018 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000069, 0x00000008 }, - { 0x0014e50e, 0x00000004 }, - { 0x0040e50f, 0x00000004 }, - { 0x00c0006c, 0x00000008 }, - { 0x0000e570, 0x00000004 }, - { 0x0000e571, 0x00000004 }, - { 0x0000e572, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000e568, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00000076, 0x00000018 }, - { 0x000b0000, 0x00000004 }, - { 0x18c0e562, 0x00000004 }, - { 0x00000078, 0x00000008 }, - { 0x00c00077, 0x00000008 }, - { 0x000700cb, 0x00000004 }, - { 0x00000084, 0x00000038 }, - { 0x000ca086, 0x00000030 }, - { 0x080045bb, 0x00000004 }, - { 0x000c2087, 0x00000030 }, - { 0x0800e5bc, 0000000000 }, - { 0x0000e5bb, 0x00000004 }, - { 0x0000e5bc, 0000000000 }, - { 0x00120000, 0x0000000c }, - { 0x00120000, 0x00000004 }, - { 0x001b0002, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e800, 0000000000 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e82e, 0000000000 }, - { 0x02cca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000ce1cc, 0x00000004 }, - { 0x050de1cd, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x00000096, 0x00000018 }, - { 0x00c0a000, 0x00000004 }, - { 0x00000093, 0x00000008 }, - { 0x00000098, 0x00000020 }, - { 0x4200e000, 0000000000 }, - { 0x0000009f, 0x00000038 }, - { 0x000ca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00160000, 0x00000004 }, - { 0x700ce000, 0x00000004 }, - { 0x0014009b, 0x00000008 }, - { 0x4000e000, 0000000000 }, - { 0x02400000, 0x00000004 }, - { 0x400ee000, 0x00000004 }, - { 0x02400000, 0x00000004 }, - { 0x4000e000, 0000000000 }, - { 0x00100000, 0x0000002c }, - { 0x00004000, 0000000000 }, - { 0x080045c8, 0x00000004 }, - { 0x00240005, 0x00000004 }, - { 0x08004d0b, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x0240e51b, 0x00000004 }, - { 0x0080e50a, 0x00000005 }, - { 0x0080e50b, 0x00000005 }, - { 0x00220000, 0x00000004 }, - { 0x000700cb, 0x00000004 }, - { 0x000000b7, 0x00000038 }, - { 0x000c2087, 0x00000030 }, - { 0x0880e5bd, 0x00000005 }, - { 0x000c2086, 0x00000030 }, - { 0x0800e5bb, 0x00000005 }, - { 0x000c2087, 0x00000030 }, - { 0x0880e5bc, 0x00000005 }, - { 0x000000ba, 0x00000008 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000be, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000c0, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080ba, 0x00000008 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700c8, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x0000e8c4, 0x00000004 }, - { 0x0000e8c5, 0x00000004 }, - { 0x0000e8c6, 0x00000004 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000cc, 0x00000008 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000d3, 0x00000008 }, - { 0x02c02000, 0x00000004 }, - { 0x00060000, 0x00000004 }, - { 0x000000db, 0x00000034 }, - { 0x000000d8, 0x00000008 }, - { 0x00008000, 0x00000004 }, - { 0xc000e000, 0000000000 }, - { 0x000000e1, 0x00000030 }, - { 0x4200e000, 0000000000 }, - { 0x000000e1, 0x00000030 }, - { 0x4000e000, 0000000000 }, - { 0x0025001b, 0x00000004 }, - { 0x00230000, 0x00000004 }, - { 0x00250005, 0x00000004 }, - { 0x000000e6, 0x00000034 }, - { 0000000000, 0x0000000c }, - { 0x00244000, 0x00000004 }, - { 0x080045c8, 0x00000004 }, - { 0x00240005, 0x00000004 }, - { 0x08004d0b, 0x0000000c }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x001d0018, 0x00000004 }, - { 0x001a0001, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0x0500a04a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 R520_cp_microcode[][2] = { - { 0x4200e000, 0000000000 }, - { 0x4000e000, 0000000000 }, - { 0x00000099, 0x00000008 }, - { 0x0000009d, 0x00000008 }, - { 0x4a554b4a, 0000000000 }, - { 0x4a4a4467, 0000000000 }, - { 0x55526f75, 0000000000 }, - { 0x4a7e7d65, 0000000000 }, - { 0xe0dae6f6, 0000000000 }, - { 0x4ac54a4a, 0000000000 }, - { 0xc8828282, 0000000000 }, - { 0xbf4acfc1, 0000000000 }, - { 0x87b04ad5, 0000000000 }, - { 0xb5838383, 0000000000 }, - { 0x4a0f85ba, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 0x0000e857, 0x00000004 }, - { 0x000d001e, 0x00000038 }, - { 0x0000e824, 0x00000004 }, - { 0x000d0020, 0x00000038 }, - { 0x0000e825, 0x00000004 }, - { 0x000d0022, 0x00000038 }, - { 0x0000e830, 0x00000004 }, - { 0x000d0024, 0x00000038 }, - { 0x0000f0c0, 0x00000004 }, - { 0x000d0026, 0x00000038 }, - { 0x0000f0c1, 0x00000004 }, - { 0x000d0028, 0x00000038 }, - { 0x0000e000, 0x00000004 }, - { 0x000d002a, 0x00000038 }, - { 0x0000e000, 0x00000004 }, - { 0x000d002c, 0x00000038 }, - { 0x0000e000, 0x00000004 }, - { 0x000d002e, 0x00000038 }, - { 0x0000e000, 0x00000004 }, - { 0x000d0030, 0x00000038 }, - { 0x0000e000, 0x00000004 }, - { 0x000d0032, 0x00000038 }, - { 0x0000f180, 0x00000004 }, - { 0x000d0034, 0x00000038 }, - { 0x0000f393, 0x00000004 }, - { 0x000d0036, 0x00000038 }, - { 0x0000f38a, 0x00000004 }, - { 0x000d0038, 0x00000038 }, - { 0x0000f38e, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000043, 0x00000018 }, - { 0x00cce800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x0000003a, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x2000451d, 0x00000004 }, - { 0x0000e580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x08004580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x00000047, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x00032000, 0x00000004 }, - { 0x00022051, 0x00000028 }, - { 0x00000051, 0x00000024 }, - { 0x0800450f, 0x00000004 }, - { 0x0000a04b, 0x00000008 }, - { 0x0000e565, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000052, 0x00000008 }, - { 0x03cca5b4, 0x00000004 }, - { 0x05432000, 0x00000004 }, - { 0x00022000, 0x00000004 }, - { 0x4ccce05e, 0x00000030 }, - { 0x08274565, 0x00000004 }, - { 0x0000005e, 0x00000030 }, - { 0x08004564, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000055, 0x00000008 }, - { 0x00802061, 0x00000010 }, - { 0x00202000, 0x00000004 }, - { 0x001b00ff, 0x00000004 }, - { 0x01000064, 0x00000010 }, - { 0x001f2000, 0x00000004 }, - { 0x001c00ff, 0x00000004 }, - { 0000000000, 0x0000000c }, - { 0x00000072, 0x00000030 }, - { 0x00000055, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x0000e577, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x0000e50f, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000069, 0x00000018 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000069, 0x00000008 }, - { 0x0014e50e, 0x00000004 }, - { 0x0040e50f, 0x00000004 }, - { 0x00c0006c, 0x00000008 }, - { 0x0000e570, 0x00000004 }, - { 0x0000e571, 0x00000004 }, - { 0x0000e572, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000e568, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00000076, 0x00000018 }, - { 0x000b0000, 0x00000004 }, - { 0x18c0e562, 0x00000004 }, - { 0x00000078, 0x00000008 }, - { 0x00c00077, 0x00000008 }, - { 0x000700c7, 0x00000004 }, - { 0x00000080, 0x00000038 }, - { 0x0000e5bb, 0x00000004 }, - { 0x0000e5bc, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e800, 0000000000 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e82e, 0000000000 }, - { 0x02cca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000ce1cc, 0x00000004 }, - { 0x050de1cd, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x0000008f, 0x00000018 }, - { 0x00c0a000, 0x00000004 }, - { 0x0000008c, 0x00000008 }, - { 0x00000091, 0x00000020 }, - { 0x4200e000, 0000000000 }, - { 0x00000098, 0x00000038 }, - { 0x000ca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00160000, 0x00000004 }, - { 0x700ce000, 0x00000004 }, - { 0x00140094, 0x00000008 }, - { 0x4000e000, 0000000000 }, - { 0x02400000, 0x00000004 }, - { 0x400ee000, 0x00000004 }, - { 0x02400000, 0x00000004 }, - { 0x4000e000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0240e51b, 0x00000004 }, - { 0x0080e50a, 0x00000005 }, - { 0x0080e50b, 0x00000005 }, - { 0x00220000, 0x00000004 }, - { 0x000700c7, 0x00000004 }, - { 0x000000a4, 0x00000038 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000ab, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000ad, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080a7, 0x00000008 }, - { 0x0000f3ce, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053cf, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f3d2, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053d3, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f39d, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c0539e, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700c4, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x0000e8c4, 0x00000004 }, - { 0x0000e8c5, 0x00000004 }, - { 0x0000e8c6, 0x00000004 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000c8, 0x00000008 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000cf, 0x00000008 }, - { 0xdeadbeef, 0000000000 }, - { 0x00000116, 0000000000 }, - { 0x000700d3, 0x00000004 }, - { 0x080050e7, 0x00000004 }, - { 0x000700d4, 0x00000004 }, - { 0x0800401c, 0x00000004 }, - { 0x0000e01d, 0000000000 }, - { 0x02c02000, 0x00000004 }, - { 0x00060000, 0x00000004 }, - { 0x000000de, 0x00000034 }, - { 0x000000db, 0x00000008 }, - { 0x00008000, 0x00000004 }, - { 0xc000e000, 0000000000 }, - { 0x0000e1cc, 0x00000004 }, - { 0x0500e1cd, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x000000e5, 0x00000034 }, - { 0x000000e1, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x0019e1cc, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x0500a000, 0x00000004 }, - { 0x080041cd, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x001d0018, 0x00000004 }, - { 0x001a0001, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0x0500a04a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - - -#endif diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 3b09a1f2d8f9..570a58729daf 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -175,6 +175,15 @@ struct radeon_mode_info { enum radeon_connector_table connector_table; bool mode_config_initialized; struct radeon_crtc *crtcs[2]; + /* DVI-I properties */ + struct drm_property *coherent_mode_property; + /* DAC enable load detect */ + struct drm_property *load_detect_property; + /* TV standard load detect */ + struct drm_property *tv_std_property; + /* legacy TMDS PLL detect */ + struct drm_property *tmds_pll_property; + }; struct radeon_native_mode { @@ -188,6 +197,21 @@ struct radeon_native_mode { uint32_t flags; }; +#define MAX_H_CODE_TIMING_LEN 32 +#define MAX_V_CODE_TIMING_LEN 32 + +/* need to store these as reading + back code tables is excessive */ +struct radeon_tv_regs { + uint32_t tv_uv_adr; + uint32_t timing_cntl; + uint32_t hrestart; + uint32_t vrestart; + uint32_t frestart; + uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; + uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; +}; + struct radeon_crtc { struct drm_crtc base; int crtc_id; @@ -195,8 +219,6 @@ struct radeon_crtc { bool enabled; bool can_tile; uint32_t crtc_offset; - struct radeon_framebuffer *fbdev_fb; - struct drm_mode_set mode_set; struct drm_gem_object *cursor_bo; uint64_t cursor_addr; int cursor_width; @@ -204,7 +226,6 @@ struct radeon_crtc { uint32_t legacy_display_base_addr; uint32_t legacy_cursor_offset; enum radeon_rmx_type rmx_type; - uint32_t devices; fixed20_12 vsc; fixed20_12 hsc; struct radeon_native_mode native_mode; @@ -236,7 +257,13 @@ struct radeon_encoder_tv_dac { uint32_t ntsc_tvdac_adj; uint32_t pal_tvdac_adj; + int h_pos; + int v_pos; + int h_size; + int supported_tv_stds; + bool tv_on; enum radeon_tv_std tv_std; + struct radeon_tv_regs tv; }; struct radeon_encoder_int_tmds { @@ -255,10 +282,15 @@ struct radeon_encoder_atom_dig { struct radeon_native_mode native_mode; }; +struct radeon_encoder_atom_dac { + enum radeon_tv_std tv_std; +}; + struct radeon_encoder { struct drm_encoder base; uint32_t encoder_id; uint32_t devices; + uint32_t active_device; uint32_t flags; uint32_t pixel_clock; enum radeon_rmx_type rmx_type; @@ -276,8 +308,12 @@ struct radeon_connector { uint32_t connector_id; uint32_t devices; struct radeon_i2c_chan *ddc_bus; - int use_digital; + bool use_digital; + /* we need to mind the EDID between detect + and get modes due to analog/digital/tvencoder */ + struct edid *edid; void *con_priv; + bool dac_load_detect; }; struct radeon_framebuffer { @@ -310,6 +346,7 @@ struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, i struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); extern int atombios_get_encoder_mode(struct drm_encoder *encoder); +extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); extern void radeon_crtc_load_lut(struct drm_crtc *crtc); extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, @@ -337,16 +374,18 @@ extern bool radeon_atom_get_clock_info(struct drm_device *dev); extern bool radeon_combios_get_clock_info(struct drm_device *dev); extern struct radeon_encoder_atom_dig * radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); -extern struct radeon_encoder_int_tmds * -radeon_atombios_get_tmds_info(struct radeon_encoder *encoder); +bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, + struct radeon_encoder_int_tmds *tmds); +bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, + struct radeon_encoder_int_tmds *tmds); +bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, + struct radeon_encoder_int_tmds *tmds); extern struct radeon_encoder_primary_dac * radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); extern struct radeon_encoder_tv_dac * radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); extern struct radeon_encoder_lvds * radeon_combios_get_lvds_info(struct radeon_encoder *encoder); -extern struct radeon_encoder_int_tmds * -radeon_combios_get_tmds_info(struct radeon_encoder *encoder); extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); extern struct radeon_encoder_tv_dac * radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); @@ -356,6 +395,8 @@ extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); +extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); +extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); extern void radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); extern void @@ -396,6 +437,19 @@ extern int radeon_static_clocks_init(struct drm_device *dev); bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode); -void atom_rv515_force_tv_scaler(struct radeon_device *rdev); - +void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); + +/* legacy tv */ +void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, + uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, + uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); +void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, + uint32_t *htotal_cntl, uint32_t *ppll_ref_div, + uint32_t *ppll_div_3, uint32_t *pixclks_cntl); +void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, + uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, + uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); +void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode); #endif diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index b85fb83d7ae8..73af463b7a59 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -188,6 +188,7 @@ int radeon_object_kmap(struct radeon_object *robj, void **ptr) if (ptr) { *ptr = robj->kptr; } + radeon_object_check_tiling(robj, 0, 0); return 0; } @@ -200,6 +201,7 @@ void radeon_object_kunmap(struct radeon_object *robj) } robj->kptr = NULL; spin_unlock(&robj->tobj.lock); + radeon_object_check_tiling(robj, 0, 0); ttm_bo_kunmap(&robj->kmap); } @@ -369,6 +371,14 @@ void radeon_object_force_delete(struct radeon_device *rdev) int radeon_object_init(struct radeon_device *rdev) { + /* Add an MTRR for the VRAM */ + rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, + MTRR_TYPE_WRCOMB, 1); + DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", + rdev->mc.mc_vram_size >> 20, + (unsigned long long)rdev->mc.aper_size >> 20); + DRM_INFO("RAM width %dbits %cDR\n", + rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); return radeon_ttm_init(rdev); } diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h index 473e4775dc5a..10e8af6bb456 100644 --- a/drivers/gpu/drm/radeon/radeon_object.h +++ b/drivers/gpu/drm/radeon/radeon_object.h @@ -37,6 +37,7 @@ * TTM. */ struct radeon_mman { + struct ttm_bo_global_ref bo_global_ref; struct ttm_global_reference mem_global_ref; bool mem_global_referenced; struct ttm_bo_device bdev; diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h index 4df43f62c678..21da871a793c 100644 --- a/drivers/gpu/drm/radeon/radeon_reg.h +++ b/drivers/gpu/drm/radeon/radeon_reg.h @@ -1945,6 +1945,11 @@ # define RADEON_TXFORMAT_DXT1 (12 << 0) # define RADEON_TXFORMAT_DXT23 (14 << 0) # define RADEON_TXFORMAT_DXT45 (15 << 0) +# define RADEON_TXFORMAT_SHADOW16 (16 << 0) +# define RADEON_TXFORMAT_SHADOW32 (17 << 0) +# define RADEON_TXFORMAT_DUDV88 (18 << 0) +# define RADEON_TXFORMAT_LDUDV655 (19 << 0) +# define RADEON_TXFORMAT_LDUDUV8888 (20 << 0) # define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) # define RADEON_TXFORMAT_FORMAT_SHIFT 0 # define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) @@ -2203,7 +2208,7 @@ # define RADEON_ROP_ENABLE (1 << 6) # define RADEON_STENCIL_ENABLE (1 << 7) # define RADEON_Z_ENABLE (1 << 8) -# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) +# define RADEON_DEPTHXY_OFFSET_ENABLE (1 << 9) # define RADEON_RB3D_COLOR_FORMAT_SHIFT 10 # define RADEON_COLOR_FORMAT_ARGB1555 3 @@ -2773,7 +2778,12 @@ # define R200_TXFORMAT_DXT1 (12 << 0) # define R200_TXFORMAT_DXT23 (14 << 0) # define R200_TXFORMAT_DXT45 (15 << 0) +# define R200_TXFORMAT_DVDU88 (18 << 0) +# define R200_TXFORMAT_LDVDU655 (19 << 0) +# define R200_TXFORMAT_LDVDU8888 (20 << 0) +# define R200_TXFORMAT_GR1616 (21 << 0) # define R200_TXFORMAT_ABGR8888 (22 << 0) +# define R200_TXFORMAT_BGR111110 (23 << 0) # define R200_TXFORMAT_FORMAT_MASK (31 << 0) # define R200_TXFORMAT_FORMAT_SHIFT 0 # define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) @@ -2818,6 +2828,13 @@ #define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */ #define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */ +#define R200_PP_CUBIC_FACES_0 0x2c18 +#define R200_PP_CUBIC_FACES_1 0x2c38 +#define R200_PP_CUBIC_FACES_2 0x2c58 +#define R200_PP_CUBIC_FACES_3 0x2c78 +#define R200_PP_CUBIC_FACES_4 0x2c98 +#define R200_PP_CUBIC_FACES_5 0x2cb8 + #define R200_PP_TXOFFSET_0 0x2d00 # define R200_TXO_ENDIAN_NO_SWAP (0 << 0) # define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) @@ -2829,11 +2846,44 @@ # define R200_TXO_MICRO_TILE (1 << 3) # define R200_TXO_OFFSET_MASK 0xffffffe0 # define R200_TXO_OFFSET_SHIFT 5 +#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 +#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 +#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c +#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 +#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 + #define R200_PP_TXOFFSET_1 0x2d18 +#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c +#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 +#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 +#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 +#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c + #define R200_PP_TXOFFSET_2 0x2d30 +#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 +#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 +#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c +#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 +#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 + #define R200_PP_TXOFFSET_3 0x2d48 +#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c +#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 +#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 +#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 +#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c #define R200_PP_TXOFFSET_4 0x2d60 +#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 +#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 +#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c +#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 +#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 #define R200_PP_TXOFFSET_5 0x2d78 +#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c +#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 +#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 +#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 +#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c #define R200_PP_TFACTOR_0 0x2ee0 #define R200_PP_TFACTOR_1 0x2ee4 @@ -3175,6 +3225,11 @@ # define R200_FORCE_INORDER_PROC (1<<31) #define R200_PP_CNTL_X 0x2cc4 #define R200_PP_TXMULTI_CTL_0 0x2c1c +#define R200_PP_TXMULTI_CTL_1 0x2c3c +#define R200_PP_TXMULTI_CTL_2 0x2c5c +#define R200_PP_TXMULTI_CTL_3 0x2c7c +#define R200_PP_TXMULTI_CTL_4 0x2c9c +#define R200_PP_TXMULTI_CTL_5 0x2cbc #define R200_SE_VTX_STATE_CNTL 0x2180 # define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) @@ -3200,6 +3255,24 @@ #define RADEON_CP_RB_WPTR 0x0714 #define RADEON_CP_RB_RPTR_WR 0x071c +#define RADEON_SCRATCH_UMSK 0x0770 +#define RADEON_SCRATCH_ADDR 0x0774 + +#define R600_CP_RB_BASE 0xc100 +#define R600_CP_RB_CNTL 0xc104 +# define R600_RB_BUFSZ(x) ((x) << 0) +# define R600_RB_BLKSZ(x) ((x) << 8) +# define R600_RB_NO_UPDATE (1 << 27) +# define R600_RB_RPTR_WR_ENA (1 << 31) +#define R600_CP_RB_RPTR_WR 0xc108 +#define R600_CP_RB_RPTR_ADDR 0xc10c +#define R600_CP_RB_RPTR_ADDR_HI 0xc110 +#define R600_CP_RB_WPTR 0xc114 +#define R600_CP_RB_WPTR_ADDR 0xc118 +#define R600_CP_RB_WPTR_ADDR_HI 0xc11c +#define R600_CP_RB_RPTR 0x8700 +#define R600_CP_RB_WPTR_DELAY 0x8704 + #define RADEON_CP_IB_BASE 0x0738 #define RADEON_CP_IB_BUFSZ 0x073c @@ -3407,7 +3480,9 @@ # define RADEON_RGB_CONVERT_BY_PASS (1 << 10) # define RADEON_UVRAM_READ_MARGIN_SHIFT 16 # define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20 -# define RADEON_TVOUT_SCALE_EN (1 << 26) +# define RADEON_RGB_ATTEN_SEL(x) ((x) << 24) +# define RADEON_TVOUT_SCALE_EN (1 << 26) +# define RADEON_RGB_ATTEN_VAL(x) ((x) << 28) #define RADEON_TV_SYNC_CNTL 0x0808 # define RADEON_SYNC_OE (1 << 0) # define RADEON_SYNC_OUT (1 << 1) diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c index 60d159308b88..747b4bffb84b 100644 --- a/drivers/gpu/drm/radeon/radeon_ring.c +++ b/drivers/gpu/drm/radeon/radeon_ring.c @@ -56,10 +56,12 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib) set_bit(i, rdev->ib_pool.alloc_bm); rdev->ib_pool.ibs[i].length_dw = 0; *ib = &rdev->ib_pool.ibs[i]; + mutex_unlock(&rdev->ib_pool.mutex); goto out; } if (list_empty(&rdev->ib_pool.scheduled_ibs)) { /* we go do nothings here */ + mutex_unlock(&rdev->ib_pool.mutex); DRM_ERROR("all IB allocated none scheduled.\n"); r = -EINVAL; goto out; @@ -69,10 +71,13 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib) struct radeon_ib, list); if (nib->fence == NULL) { /* we go do nothings here */ + mutex_unlock(&rdev->ib_pool.mutex); DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx); r = -EINVAL; goto out; } + mutex_unlock(&rdev->ib_pool.mutex); + r = radeon_fence_wait(nib->fence, false); if (r) { DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx, @@ -81,12 +86,17 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib) goto out; } radeon_fence_unref(&nib->fence); + nib->length_dw = 0; + + /* scheduled list is accessed here */ + mutex_lock(&rdev->ib_pool.mutex); list_del(&nib->list); INIT_LIST_HEAD(&nib->list); + mutex_unlock(&rdev->ib_pool.mutex); + *ib = nib; out: - mutex_unlock(&rdev->ib_pool.mutex); if (r) { radeon_fence_unref(&fence); } else { @@ -111,47 +121,36 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) } list_del(&tmp->list); INIT_LIST_HEAD(&tmp->list); - if (tmp->fence) { + if (tmp->fence) radeon_fence_unref(&tmp->fence); - } + tmp->length_dw = 0; clear_bit(tmp->idx, rdev->ib_pool.alloc_bm); mutex_unlock(&rdev->ib_pool.mutex); } -static void radeon_ib_align(struct radeon_device *rdev, struct radeon_ib *ib) -{ - while ((ib->length_dw & rdev->cp.align_mask)) { - ib->ptr[ib->length_dw++] = PACKET2(0); - } -} - int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) { int r = 0; - mutex_lock(&rdev->ib_pool.mutex); - radeon_ib_align(rdev, ib); if (!ib->length_dw || !rdev->cp.ready) { /* TODO: Nothings in the ib we should report. */ - mutex_unlock(&rdev->ib_pool.mutex); DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx); return -EINVAL; } + /* 64 dwords should be enough for fence too */ r = radeon_ring_lock(rdev, 64); if (r) { DRM_ERROR("radeon: scheduling IB failled (%d).\n", r); - mutex_unlock(&rdev->ib_pool.mutex); return r; } - radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); - radeon_ring_write(rdev, ib->gpu_addr); - radeon_ring_write(rdev, ib->length_dw); + radeon_ring_ib_execute(rdev, ib); radeon_fence_emit(rdev, ib->fence); - radeon_ring_unlock_commit(rdev); + mutex_lock(&rdev->ib_pool.mutex); list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs); mutex_unlock(&rdev->ib_pool.mutex); + radeon_ring_unlock_commit(rdev); return 0; } @@ -162,6 +161,8 @@ int radeon_ib_pool_init(struct radeon_device *rdev) int i; int r = 0; + if (rdev->ib_pool.robj) + return 0; /* Allocate 1M object buffer */ INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs); r = radeon_object_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024, @@ -215,69 +216,16 @@ void radeon_ib_pool_fini(struct radeon_device *rdev) mutex_unlock(&rdev->ib_pool.mutex); } -int radeon_ib_test(struct radeon_device *rdev) -{ - struct radeon_ib *ib; - uint32_t scratch; - uint32_t tmp = 0; - unsigned i; - int r; - - r = radeon_scratch_get(rdev, &scratch); - if (r) { - DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); - return r; - } - WREG32(scratch, 0xCAFEDEAD); - r = radeon_ib_get(rdev, &ib); - if (r) { - return r; - } - ib->ptr[0] = PACKET0(scratch, 0); - ib->ptr[1] = 0xDEADBEEF; - ib->ptr[2] = PACKET2(0); - ib->ptr[3] = PACKET2(0); - ib->ptr[4] = PACKET2(0); - ib->ptr[5] = PACKET2(0); - ib->ptr[6] = PACKET2(0); - ib->ptr[7] = PACKET2(0); - ib->length_dw = 8; - r = radeon_ib_schedule(rdev, ib); - if (r) { - radeon_scratch_free(rdev, scratch); - radeon_ib_free(rdev, &ib); - return r; - } - r = radeon_fence_wait(ib->fence, false); - if (r) { - return r; - } - for (i = 0; i < rdev->usec_timeout; i++) { - tmp = RREG32(scratch); - if (tmp == 0xDEADBEEF) { - break; - } - DRM_UDELAY(1); - } - if (i < rdev->usec_timeout) { - DRM_INFO("ib test succeeded in %u usecs\n", i); - } else { - DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", - scratch, tmp); - r = -EINVAL; - } - radeon_scratch_free(rdev, scratch); - radeon_ib_free(rdev, &ib); - return r; -} - /* * Ring. */ void radeon_ring_free_size(struct radeon_device *rdev) { - rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); + if (rdev->family >= CHIP_R600) + rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); + else + rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); /* This works because ring_size is a power of 2 */ rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4)); rdev->cp.ring_free_dw -= rdev->cp.wptr; @@ -320,11 +268,10 @@ void radeon_ring_unlock_commit(struct radeon_device *rdev) count_dw_pad = (rdev->cp.align_mask + 1) - (rdev->cp.wptr & rdev->cp.align_mask); for (i = 0; i < count_dw_pad; i++) { - radeon_ring_write(rdev, PACKET2(0)); + radeon_ring_write(rdev, 2 << 30); } DRM_MEMORYBARRIER(); - WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); - (void)RREG32(RADEON_CP_RB_WPTR); + radeon_cp_commit(rdev); mutex_unlock(&rdev->cp.mutex); } @@ -334,46 +281,6 @@ void radeon_ring_unlock_undo(struct radeon_device *rdev) mutex_unlock(&rdev->cp.mutex); } -int radeon_ring_test(struct radeon_device *rdev) -{ - uint32_t scratch; - uint32_t tmp = 0; - unsigned i; - int r; - - r = radeon_scratch_get(rdev, &scratch); - if (r) { - DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); - return r; - } - WREG32(scratch, 0xCAFEDEAD); - r = radeon_ring_lock(rdev, 2); - if (r) { - DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); - radeon_scratch_free(rdev, scratch); - return r; - } - radeon_ring_write(rdev, PACKET0(scratch, 0)); - radeon_ring_write(rdev, 0xDEADBEEF); - radeon_ring_unlock_commit(rdev); - for (i = 0; i < rdev->usec_timeout; i++) { - tmp = RREG32(scratch); - if (tmp == 0xDEADBEEF) { - break; - } - DRM_UDELAY(1); - } - if (i < rdev->usec_timeout) { - DRM_INFO("ring test succeeded in %d usecs\n", i); - } else { - DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n", - scratch, tmp); - r = -EINVAL; - } - radeon_scratch_free(rdev, scratch); - return r; -} - int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size) { int r; diff --git a/drivers/gpu/drm/radeon/radeon_share.h b/drivers/gpu/drm/radeon/radeon_share.h deleted file mode 100644 index 63a773578f17..000000000000 --- a/drivers/gpu/drm/radeon/radeon_share.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright 2008 Advanced Micro Devices, Inc. - * Copyright 2008 Red Hat Inc. - * Copyright 2009 Jerome Glisse. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Dave Airlie - * Alex Deucher - * Jerome Glisse - */ -#ifndef __RADEON_SHARE_H__ -#define __RADEON_SHARE_H__ - -void r100_vram_init_sizes(struct radeon_device *rdev); - -void rs690_line_buffer_adjust(struct radeon_device *rdev, - struct drm_display_mode *mode1, - struct drm_display_mode *mode2); - -void rv515_bandwidth_avivo_update(struct radeon_device *rdev); - -#endif diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c index 2882f40d5ec5..38537d971a3e 100644 --- a/drivers/gpu/drm/radeon/radeon_state.c +++ b/drivers/gpu/drm/radeon/radeon_state.c @@ -1546,7 +1546,7 @@ static void radeon_cp_dispatch_vertex(struct drm_device * dev, } while (i < nbox); } -static void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf) +void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf) { drm_radeon_private_t *dev_priv = dev->dev_private; struct drm_radeon_master_private *master_priv = master->driver_priv; @@ -2213,7 +2213,10 @@ static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *f if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; - radeon_cp_dispatch_swap(dev, file_priv->master); + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) + r600_cp_dispatch_swap(dev, file_priv); + else + radeon_cp_dispatch_swap(dev, file_priv->master); sarea_priv->ctx_owner = 0; COMMIT_RING(); @@ -2412,7 +2415,10 @@ static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); - ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image); + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) + ret = r600_cp_dispatch_texture(dev, file_priv, tex, &image); + else + ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image); return ret; } @@ -2495,8 +2501,9 @@ static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_fil radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end); } - if (indirect->discard) + if (indirect->discard) { radeon_cp_discard_buffer(dev, file_priv->master, buf); + } COMMIT_RING(); return 0; @@ -3027,7 +3034,10 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil value = GET_SCRATCH(dev_priv, 2); break; case RADEON_PARAM_IRQ_NR: - value = drm_dev_to_irq(dev); + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) + value = 0; + else + value = drm_dev_to_irq(dev); break; case RADEON_PARAM_GART_BASE: value = dev_priv->gart_vm_start; @@ -3227,7 +3237,8 @@ struct drm_ioctl_desc radeon_ioctls[] = { DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH), DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH), DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH) + DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_CS, r600_cs_legacy_ioctl, DRM_AUTH) }; int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 15c3531377ed..acd889c94549 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -35,11 +35,14 @@ #include #include #include +#include #include "radeon_reg.h" #include "radeon.h" #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) +static int radeon_ttm_debugfs_init(struct radeon_device *rdev); + static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) { struct radeon_mman *mman; @@ -77,9 +80,25 @@ static int radeon_ttm_global_init(struct radeon_device *rdev) global_ref->release = &radeon_ttm_mem_global_release; r = ttm_global_item_ref(global_ref); if (r != 0) { - DRM_ERROR("Failed referencing a global TTM memory object.\n"); + DRM_ERROR("Failed setting up TTM memory accounting " + "subsystem.\n"); + return r; + } + + rdev->mman.bo_global_ref.mem_glob = + rdev->mman.mem_global_ref.object; + global_ref = &rdev->mman.bo_global_ref.ref; + global_ref->global_type = TTM_GLOBAL_TTM_BO; + global_ref->size = sizeof(struct ttm_bo_global); + global_ref->init = &ttm_bo_global_init; + global_ref->release = &ttm_bo_global_release; + r = ttm_global_item_ref(global_ref); + if (r != 0) { + DRM_ERROR("Failed setting up TTM BO subsystem.\n"); + ttm_global_item_unref(&rdev->mman.mem_global_ref); return r; } + rdev->mman.mem_global_referenced = true; return 0; } @@ -87,6 +106,7 @@ static int radeon_ttm_global_init(struct radeon_device *rdev) static void radeon_ttm_global_fini(struct radeon_device *rdev) { if (rdev->mman.mem_global_referenced) { + ttm_global_item_unref(&rdev->mman.bo_global_ref.ref); ttm_global_item_unref(&rdev->mman.mem_global_ref); rdev->mman.mem_global_referenced = false; } @@ -286,9 +306,11 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo, r = ttm_bo_move_ttm(bo, true, no_wait, new_mem); out_cleanup: if (tmp_mem.mm_node) { - spin_lock(&rdev->mman.bdev.lru_lock); + struct ttm_bo_global *glob = rdev->mman.bdev.glob; + + spin_lock(&glob->lru_lock); drm_mm_put_block(tmp_mem.mm_node); - spin_unlock(&rdev->mman.bdev.lru_lock); + spin_unlock(&glob->lru_lock); return r; } return r; @@ -323,9 +345,11 @@ static int radeon_move_ram_vram(struct ttm_buffer_object *bo, } out_cleanup: if (tmp_mem.mm_node) { - spin_lock(&rdev->mman.bdev.lru_lock); + struct ttm_bo_global *glob = rdev->mman.bdev.glob; + + spin_lock(&glob->lru_lock); drm_mm_put_block(tmp_mem.mm_node); - spin_unlock(&rdev->mman.bdev.lru_lock); + spin_unlock(&glob->lru_lock); return r; } return r; @@ -352,9 +376,8 @@ static int radeon_bo_move(struct ttm_buffer_object *bo, radeon_move_null(bo, new_mem); return 0; } - if (!rdev->cp.ready) { + if (!rdev->cp.ready || rdev->asic->copy == NULL) { /* use memcpy */ - DRM_ERROR("CP is not ready use memcpy.\n"); goto memcpy; } @@ -446,7 +469,7 @@ int radeon_ttm_init(struct radeon_device *rdev) } /* No others user of address space so set it to 0 */ r = ttm_bo_device_init(&rdev->mman.bdev, - rdev->mman.mem_global_ref.object, + rdev->mman.bo_global_ref.ref.object, &radeon_bo_driver, DRM_FILE_PAGE_OFFSET, rdev->need_dma32); if (r) { @@ -471,7 +494,7 @@ int radeon_ttm_init(struct radeon_device *rdev) return r; } DRM_INFO("radeon: %uM of VRAM memory ready\n", - rdev->mc.real_vram_size / (1024 * 1024)); + (unsigned)rdev->mc.real_vram_size / (1024 * 1024)); r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 0, ((rdev->mc.gtt_size) >> PAGE_SHIFT)); if (r) { @@ -479,10 +502,16 @@ int radeon_ttm_init(struct radeon_device *rdev) return r; } DRM_INFO("radeon: %uM of GTT memory ready.\n", - rdev->mc.gtt_size / (1024 * 1024)); + (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; } + + r = radeon_ttm_debugfs_init(rdev); + if (r) { + DRM_ERROR("Failed to init debugfs\n"); + return r; + } return 0; } @@ -657,3 +686,50 @@ struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev) gtt->bound = false; return >t->backend; } + +#define RADEON_DEBUGFS_MEM_TYPES 2 + +static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES]; +static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES][32]; + +#if defined(CONFIG_DEBUG_FS) +static int radeon_mm_dump_table(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_mm *mm = (struct drm_mm *)node->info_ent->data; + struct drm_device *dev = node->minor->dev; + struct radeon_device *rdev = dev->dev_private; + int ret; + struct ttm_bo_global *glob = rdev->mman.bdev.glob; + + spin_lock(&glob->lru_lock); + ret = drm_mm_dump_table(m, mm); + spin_unlock(&glob->lru_lock); + return ret; +} +#endif + +static int radeon_ttm_debugfs_init(struct radeon_device *rdev) +{ + unsigned i; + +#if defined(CONFIG_DEBUG_FS) + for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) { + if (i == 0) + sprintf(radeon_mem_types_names[i], "radeon_vram_mm"); + else + sprintf(radeon_mem_types_names[i], "radeon_gtt_mm"); + radeon_mem_types_list[i].name = radeon_mem_types_names[i]; + radeon_mem_types_list[i].show = &radeon_mm_dump_table; + radeon_mem_types_list[i].driver_features = 0; + if (i == 0) + radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_VRAM].manager; + else + radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_TT].manager; + + } + return radeon_debugfs_add_files(rdev, radeon_mem_types_list, RADEON_DEBUGFS_MEM_TYPES); + +#endif + return 0; +} diff --git a/drivers/gpu/drm/radeon/reg_srcs/r100 b/drivers/gpu/drm/radeon/reg_srcs/r100 new file mode 100644 index 000000000000..f7ee062f1184 --- /dev/null +++ b/drivers/gpu/drm/radeon/reg_srcs/r100 @@ -0,0 +1,105 @@ +r100 0x3294 +0x1434 SRC_Y_X +0x1438 DST_Y_X +0x143C DST_HEIGHT_WIDTH +0x146C DP_GUI_MASTER_CNTL +0x1474 BRUSH_Y_X +0x1478 DP_BRUSH_BKGD_CLR +0x147C DP_BRUSH_FRGD_CLR +0x1480 BRUSH_DATA0 +0x1484 BRUSH_DATA1 +0x1598 DST_WIDTH_HEIGHT +0x15C0 CLR_CMP_CNTL +0x15C4 CLR_CMP_CLR_SRC +0x15C8 CLR_CMP_CLR_DST +0x15CC CLR_CMP_MSK +0x15D8 DP_SRC_FRGD_CLR +0x15DC DP_SRC_BKGD_CLR +0x1600 DST_LINE_START +0x1604 DST_LINE_END +0x1608 DST_LINE_PATCOUNT +0x16C0 DP_CNTL +0x16CC DP_WRITE_MSK +0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR +0x16E8 DEFAULT_SC_BOTTOM_RIGHT +0x16EC SC_TOP_LEFT +0x16F0 SC_BOTTOM_RIGHT +0x16F4 SRC_SC_BOTTOM_RIGHT +0x1714 DSTCACHE_CTLSTAT +0x1720 WAIT_UNTIL +0x172C RBBM_GUICNTL +0x1810 FOG_3D_TABLE_START +0x1814 FOG_3D_TABLE_END +0x1a14 FOG_TABLE_INDEX +0x1a18 FOG_TABLE_DATA +0x1c14 PP_MISC +0x1c18 PP_FOG_COLOR +0x1c1c RE_SOLID_COLOR +0x1c20 RB3D_BLENDCNTL +0x1c4c SE_CNTL +0x1c50 SE_COORD_FMT +0x1c60 PP_TXCBLEND_0 +0x1c64 PP_TXABLEND_0 +0x1c68 PP_TFACTOR_0 +0x1c78 PP_TXCBLEND_1 +0x1c7c PP_TXABLEND_1 +0x1c80 PP_TFACTOR_1 +0x1c90 PP_TXCBLEND_2 +0x1c94 PP_TXABLEND_2 +0x1c98 PP_TFACTOR_2 +0x1cc8 RE_STIPPLE_ADDR +0x1ccc RE_STIPPLE_DATA +0x1cd0 RE_LINE_PATTERN +0x1cd4 RE_LINE_STATE +0x1d40 PP_BORDER_COLOR0 +0x1d44 PP_BORDER_COLOR1 +0x1d48 PP_BORDER_COLOR2 +0x1d7c RB3D_STENCILREFMASK +0x1d80 RB3D_ROPCNTL +0x1d84 RB3D_PLANEMASK +0x1d98 VAP_VPORT_XSCALE +0x1d9C VAP_VPORT_XOFFSET +0x1da0 VAP_VPORT_YSCALE +0x1da4 VAP_VPORT_YOFFSET +0x1da8 VAP_VPORT_ZSCALE +0x1dac VAP_VPORT_ZOFFSET +0x1db0 SE_ZBIAS_FACTOR +0x1db4 SE_ZBIAS_CONSTANT +0x1db8 SE_LINE_WIDTH +0x2140 SE_CNTL_STATUS +0x2200 SE_TCL_VECTOR_INDX_REG +0x2204 SE_TCL_VECTOR_DATA_REG +0x2208 SE_TCL_SCALAR_INDX_REG +0x220c SE_TCL_SCALAR_DATA_REG +0x2210 SE_TCL_MATERIAL_EMISSIVE_RED +0x2214 SE_TCL_MATERIAL_EMISSIVE_GREEN +0x2218 SE_TCL_MATERIAL_EMISSIVE_BLUE +0x221c SE_TCL_MATERIAL_EMISSIVE_ALPHA +0x2220 SE_TCL_MATERIAL_AMBIENT_RED +0x2224 SE_TCL_MATERIAL_AMBIENT_GREEN +0x2228 SE_TCL_MATERIAL_AMBIENT_BLUE +0x222c SE_TCL_MATERIAL_AMBIENT_ALPHA +0x2230 SE_TCL_MATERIAL_DIFFUSE_RED +0x2234 SE_TCL_MATERIAL_DIFFUSE_GREEN +0x2238 SE_TCL_MATERIAL_DIFFUSE_BLUE +0x223c SE_TCL_MATERIAL_DIFFUSE_ALPHA +0x2240 SE_TCL_MATERIAL_SPECULAR_RED +0x2244 SE_TCL_MATERIAL_SPECULAR_GREEN +0x2248 SE_TCL_MATERIAL_SPECULAR_BLUE +0x224c SE_TCL_MATERIAL_SPECULAR_ALPHA +0x2250 SE_TCL_SHININESS +0x2254 SE_TCL_OUTPUT_VTX_FMT +0x2258 SE_TCL_OUTPUT_VTX_SEL +0x225c SE_TCL_MATRIX_SELECT_0 +0x2260 SE_TCL_MATRIX_SELECT_1 +0x2264 SE_TCL_UCP_VERT_BLEND_CNTL +0x2268 SE_TCL_TEXTURE_PROC_CTL +0x226c SE_TCL_LIGHT_MODEL_CTL +0x2270 SE_TCL_PER_LIGHT_CTL_0 +0x2274 SE_TCL_PER_LIGHT_CTL_1 +0x2278 SE_TCL_PER_LIGHT_CTL_2 +0x227c SE_TCL_PER_LIGHT_CTL_3 +0x2284 SE_TCL_STATE_FLUSH +0x26c0 RE_TOP_LEFT +0x26c4 RE_MISC +0x3290 RB3D_ZPASS_DATA diff --git a/drivers/gpu/drm/radeon/reg_srcs/r200 b/drivers/gpu/drm/radeon/reg_srcs/r200 new file mode 100644 index 000000000000..6021c8849a16 --- /dev/null +++ b/drivers/gpu/drm/radeon/reg_srcs/r200 @@ -0,0 +1,184 @@ +r200 0x3294 +0x1434 SRC_Y_X +0x1438 DST_Y_X +0x143C DST_HEIGHT_WIDTH +0x146C DP_GUI_MASTER_CNTL +0x1474 BRUSH_Y_X +0x1478 DP_BRUSH_BKGD_CLR +0x147C DP_BRUSH_FRGD_CLR +0x1480 BRUSH_DATA0 +0x1484 BRUSH_DATA1 +0x1598 DST_WIDTH_HEIGHT +0x15C0 CLR_CMP_CNTL +0x15C4 CLR_CMP_CLR_SRC +0x15C8 CLR_CMP_CLR_DST +0x15CC CLR_CMP_MSK +0x15D8 DP_SRC_FRGD_CLR +0x15DC DP_SRC_BKGD_CLR +0x1600 DST_LINE_START +0x1604 DST_LINE_END +0x1608 DST_LINE_PATCOUNT +0x16C0 DP_CNTL +0x16CC DP_WRITE_MSK +0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR +0x16E8 DEFAULT_SC_BOTTOM_RIGHT +0x16EC SC_TOP_LEFT +0x16F0 SC_BOTTOM_RIGHT +0x16F4 SRC_SC_BOTTOM_RIGHT +0x1714 DSTCACHE_CTLSTAT +0x1720 WAIT_UNTIL +0x172C RBBM_GUICNTL +0x1c14 PP_MISC +0x1c18 PP_FOG_COLOR +0x1c1c RE_SOLID_COLOR +0x1c20 RB3D_BLENDCNTL +0x1c4c SE_CNTL +0x1c50 RE_CNTL +0x1cc8 RE_STIPPLE_ADDR +0x1ccc RE_STIPPLE_DATA +0x1cd0 RE_LINE_PATTERN +0x1cd4 RE_LINE_STATE +0x1cd8 RE_SCISSOR_TL_0 +0x1cdc RE_SCISSOR_BR_0 +0x1ce0 RE_SCISSOR_TL_1 +0x1ce4 RE_SCISSOR_BR_1 +0x1ce8 RE_SCISSOR_TL_2 +0x1cec RE_SCISSOR_BR_2 +0x1d60 RB3D_DEPTHXY_OFFSET +0x1d7c RB3D_STENCILREFMASK +0x1d80 RB3D_ROPCNTL +0x1d84 RB3D_PLANEMASK +0x1d98 VAP_VPORT_XSCALE +0x1d9c VAP_VPORT_XOFFSET +0x1da0 VAP_VPORT_YSCALE +0x1da4 VAP_VPORT_YOFFSET +0x1da8 VAP_VPORT_ZSCALE +0x1dac VAP_VPORT_ZOFFSET +0x1db0 SE_ZBIAS_FACTOR +0x1db4 SE_ZBIAS_CONSTANT +0x1db8 SE_LINE_WIDTH +0x2080 SE_VAP_CNTL +0x2090 SE_TCL_OUTPUT_VTX_FMT_0 +0x2094 SE_TCL_OUTPUT_VTX_FMT_1 +0x20b0 SE_VTE_CNTL +0x2140 SE_CNTL_STATUS +0x2180 SE_VTX_STATE_CNTL +0x2200 SE_TCL_VECTOR_INDX_REG +0x2204 SE_TCL_VECTOR_DATA_REG +0x2208 SE_TCL_SCALAR_INDX_REG +0x220c SE_TCL_SCALAR_DATA_REG +0x2230 SE_TCL_MATRIX_SEL_0 +0x2234 SE_TCL_MATRIX_SEL_1 +0x2238 SE_TCL_MATRIX_SEL_2 +0x223c SE_TCL_MATRIX_SEL_3 +0x2240 SE_TCL_MATRIX_SEL_4 +0x2250 SE_TCL_OUTPUT_VTX_COMP_SEL +0x2254 SE_TCL_INPUT_VTX_VECTOR_ADDR_0 +0x2258 SE_TCL_INPUT_VTX_VECTOR_ADDR_1 +0x225c SE_TCL_INPUT_VTX_VECTOR_ADDR_2 +0x2260 SE_TCL_INPUT_VTX_VECTOR_ADDR_3 +0x2268 SE_TCL_LIGHT_MODEL_CTL_0 +0x226c SE_TCL_LIGHT_MODEL_CTL_1 +0x2270 SE_TCL_PER_LIGHT_CTL_0 +0x2274 SE_TCL_PER_LIGHT_CTL_1 +0x2278 SE_TCL_PER_LIGHT_CTL_2 +0x227c SE_TCL_PER_LIGHT_CTL_3 +0x2284 VAP_PVS_STATE_FLUSH_REG +0x22a8 SE_TCL_TEX_PROC_CTL_2 +0x22ac SE_TCL_TEX_PROC_CTL_3 +0x22b0 SE_TCL_TEX_PROC_CTL_0 +0x22b4 SE_TCL_TEX_PROC_CTL_1 +0x22b8 SE_TCL_TEX_CYL_WRAP_CTL +0x22c0 SE_TCL_UCP_VERT_BLEND_CNTL +0x22c4 SE_TCL_POINT_SPRITE_CNTL +0x2648 RE_POINTSIZE +0x26c0 RE_TOP_LEFT +0x26c4 RE_MISC +0x26f0 RE_AUX_SCISSOR_CNTL +0x2c14 PP_BORDER_COLOR_0 +0x2c34 PP_BORDER_COLOR_1 +0x2c54 PP_BORDER_COLOR_2 +0x2c74 PP_BORDER_COLOR_3 +0x2c94 PP_BORDER_COLOR_4 +0x2cb4 PP_BORDER_COLOR_5 +0x2cc4 PP_CNTL_X +0x2cf8 PP_TRI_PERF +0x2cfc PP_PERF_CNTL +0x2d9c PP_TAM_DEBUG3 +0x2ee0 PP_TFACTOR_0 +0x2ee4 PP_TFACTOR_1 +0x2ee8 PP_TFACTOR_2 +0x2eec PP_TFACTOR_3 +0x2ef0 PP_TFACTOR_4 +0x2ef4 PP_TFACTOR_5 +0x2ef8 PP_TFACTOR_6 +0x2efc PP_TFACTOR_7 +0x2f00 PP_TXCBLEND_0 +0x2f04 PP_TXCBLEND2_0 +0x2f08 PP_TXABLEND_0 +0x2f0c PP_TXABLEND2_0 +0x2f10 PP_TXCBLEND_1 +0x2f14 PP_TXCBLEND2_1 +0x2f18 PP_TXABLEND_1 +0x2f1c PP_TXABLEND2_1 +0x2f20 PP_TXCBLEND_2 +0x2f24 PP_TXCBLEND2_2 +0x2f28 PP_TXABLEND_2 +0x2f2c PP_TXABLEND2_2 +0x2f30 PP_TXCBLEND_3 +0x2f34 PP_TXCBLEND2_3 +0x2f38 PP_TXABLEND_3 +0x2f3c PP_TXABLEND2_3 +0x2f40 PP_TXCBLEND_4 +0x2f44 PP_TXCBLEND2_4 +0x2f48 PP_TXABLEND_4 +0x2f4c PP_TXABLEND2_4 +0x2f50 PP_TXCBLEND_5 +0x2f54 PP_TXCBLEND2_5 +0x2f58 PP_TXABLEND_5 +0x2f5c PP_TXABLEND2_5 +0x2f60 PP_TXCBLEND_6 +0x2f64 PP_TXCBLEND2_6 +0x2f68 PP_TXABLEND_6 +0x2f6c PP_TXABLEND2_6 +0x2f70 PP_TXCBLEND_7 +0x2f74 PP_TXCBLEND2_7 +0x2f78 PP_TXABLEND_7 +0x2f7c PP_TXABLEND2_7 +0x2f80 PP_TXCBLEND_8 +0x2f84 PP_TXCBLEND2_8 +0x2f88 PP_TXABLEND_8 +0x2f8c PP_TXABLEND2_8 +0x2f90 PP_TXCBLEND_9 +0x2f94 PP_TXCBLEND2_9 +0x2f98 PP_TXABLEND_9 +0x2f9c PP_TXABLEND2_9 +0x2fa0 PP_TXCBLEND_10 +0x2fa4 PP_TXCBLEND2_10 +0x2fa8 PP_TXABLEND_10 +0x2fac PP_TXABLEND2_10 +0x2fb0 PP_TXCBLEND_11 +0x2fb4 PP_TXCBLEND2_11 +0x2fb8 PP_TXABLEND_11 +0x2fbc PP_TXABLEND2_11 +0x2fc0 PP_TXCBLEND_12 +0x2fc4 PP_TXCBLEND2_12 +0x2fc8 PP_TXABLEND_12 +0x2fcc PP_TXABLEND2_12 +0x2fd0 PP_TXCBLEND_13 +0x2fd4 PP_TXCBLEND2_13 +0x2fd8 PP_TXABLEND_13 +0x2fdc PP_TXABLEND2_13 +0x2fe0 PP_TXCBLEND_14 +0x2fe4 PP_TXCBLEND2_14 +0x2fe8 PP_TXABLEND_14 +0x2fec PP_TXABLEND2_14 +0x2ff0 PP_TXCBLEND_15 +0x2ff4 PP_TXCBLEND2_15 +0x2ff8 PP_TXABLEND_15 +0x2ffc PP_TXABLEND2_15 +0x3218 RB3D_BLENCOLOR +0x321c RB3D_ABLENDCNTL +0x3220 RB3D_CBLENDCNTL +0x3290 RB3D_ZPASS_DATA + diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300 new file mode 100644 index 000000000000..19c4663fa9c6 --- /dev/null +++ b/drivers/gpu/drm/radeon/reg_srcs/r300 @@ -0,0 +1,729 @@ +r300 0x4f60 +0x1434 SRC_Y_X +0x1438 DST_Y_X +0x143C DST_HEIGHT_WIDTH +0x146C DP_GUI_MASTER_CNTL +0x1474 BRUSH_Y_X +0x1478 DP_BRUSH_BKGD_CLR +0x147C DP_BRUSH_FRGD_CLR +0x1480 BRUSH_DATA0 +0x1484 BRUSH_DATA1 +0x1598 DST_WIDTH_HEIGHT +0x15C0 CLR_CMP_CNTL +0x15C4 CLR_CMP_CLR_SRC +0x15C8 CLR_CMP_CLR_DST +0x15CC CLR_CMP_MSK +0x15D8 DP_SRC_FRGD_CLR +0x15DC DP_SRC_BKGD_CLR +0x1600 DST_LINE_START +0x1604 DST_LINE_END +0x1608 DST_LINE_PATCOUNT +0x16C0 DP_CNTL +0x16CC DP_WRITE_MSK +0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR +0x16E8 DEFAULT_SC_BOTTOM_RIGHT +0x16EC SC_TOP_LEFT +0x16F0 SC_BOTTOM_RIGHT +0x16F4 SRC_SC_BOTTOM_RIGHT +0x1714 DSTCACHE_CTLSTAT +0x1720 WAIT_UNTIL +0x172C RBBM_GUICNTL +0x1D98 VAP_VPORT_XSCALE +0x1D9C VAP_VPORT_XOFFSET +0x1DA0 VAP_VPORT_YSCALE +0x1DA4 VAP_VPORT_YOFFSET +0x1DA8 VAP_VPORT_ZSCALE +0x1DAC VAP_VPORT_ZOFFSET +0x2080 VAP_CNTL +0x2090 VAP_OUT_VTX_FMT_0 +0x2094 VAP_OUT_VTX_FMT_1 +0x20B0 VAP_VTE_CNTL +0x2138 VAP_VF_MIN_VTX_INDX +0x2140 VAP_CNTL_STATUS +0x2150 VAP_PROG_STREAM_CNTL_0 +0x2154 VAP_PROG_STREAM_CNTL_1 +0x2158 VAP_PROG_STREAM_CNTL_2 +0x215C VAP_PROG_STREAM_CNTL_3 +0x2160 VAP_PROG_STREAM_CNTL_4 +0x2164 VAP_PROG_STREAM_CNTL_5 +0x2168 VAP_PROG_STREAM_CNTL_6 +0x216C VAP_PROG_STREAM_CNTL_7 +0x2180 VAP_VTX_STATE_CNTL +0x2184 VAP_VSM_VTX_ASSM +0x2188 VAP_VTX_STATE_IND_REG_0 +0x218C VAP_VTX_STATE_IND_REG_1 +0x2190 VAP_VTX_STATE_IND_REG_2 +0x2194 VAP_VTX_STATE_IND_REG_3 +0x2198 VAP_VTX_STATE_IND_REG_4 +0x219C VAP_VTX_STATE_IND_REG_5 +0x21A0 VAP_VTX_STATE_IND_REG_6 +0x21A4 VAP_VTX_STATE_IND_REG_7 +0x21A8 VAP_VTX_STATE_IND_REG_8 +0x21AC VAP_VTX_STATE_IND_REG_9 +0x21B0 VAP_VTX_STATE_IND_REG_10 +0x21B4 VAP_VTX_STATE_IND_REG_11 +0x21B8 VAP_VTX_STATE_IND_REG_12 +0x21BC VAP_VTX_STATE_IND_REG_13 +0x21C0 VAP_VTX_STATE_IND_REG_14 +0x21C4 VAP_VTX_STATE_IND_REG_15 +0x21DC VAP_PSC_SGN_NORM_CNTL +0x21E0 VAP_PROG_STREAM_CNTL_EXT_0 +0x21E4 VAP_PROG_STREAM_CNTL_EXT_1 +0x21E8 VAP_PROG_STREAM_CNTL_EXT_2 +0x21EC VAP_PROG_STREAM_CNTL_EXT_3 +0x21F0 VAP_PROG_STREAM_CNTL_EXT_4 +0x21F4 VAP_PROG_STREAM_CNTL_EXT_5 +0x21F8 VAP_PROG_STREAM_CNTL_EXT_6 +0x21FC VAP_PROG_STREAM_CNTL_EXT_7 +0x2200 VAP_PVS_VECTOR_INDX_REG +0x2204 VAP_PVS_VECTOR_DATA_REG +0x2208 VAP_PVS_VECTOR_DATA_REG_128 +0x221C VAP_CLIP_CNTL +0x2220 VAP_GB_VERT_CLIP_ADJ +0x2224 VAP_GB_VERT_DISC_ADJ +0x2228 VAP_GB_HORZ_CLIP_ADJ +0x222C VAP_GB_HORZ_DISC_ADJ +0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0 +0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1 +0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2 +0x223C VAP_PVS_FLOW_CNTL_ADDRS_3 +0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4 +0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5 +0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6 +0x224C VAP_PVS_FLOW_CNTL_ADDRS_7 +0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8 +0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9 +0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10 +0x225C VAP_PVS_FLOW_CNTL_ADDRS_11 +0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12 +0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13 +0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14 +0x226C VAP_PVS_FLOW_CNTL_ADDRS_15 +0x2284 VAP_PVS_STATE_FLUSH_REG +0x2288 VAP_PVS_VTX_TIMEOUT_REG +0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0 +0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1 +0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2 +0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3 +0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4 +0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5 +0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6 +0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7 +0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8 +0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9 +0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10 +0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11 +0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12 +0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13 +0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14 +0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15 +0x22D0 VAP_PVS_CODE_CNTL_0 +0x22D4 VAP_PVS_CONST_CNTL +0x22D8 VAP_PVS_CODE_CNTL_1 +0x22DC VAP_PVS_FLOW_CNTL_OPC +0x342C RB2D_DSTCACHE_CTLSTAT +0x4000 GB_VAP_RASTER_VTX_FMT_0 +0x4004 GB_VAP_RASTER_VTX_FMT_1 +0x4008 GB_ENABLE +0x401C GB_SELECT +0x4020 GB_AA_CONFIG +0x4024 GB_FIFO_SIZE +0x4100 TX_INVALTAGS +0x4200 GA_POINT_S0 +0x4204 GA_POINT_T0 +0x4208 GA_POINT_S1 +0x420C GA_POINT_T1 +0x4214 GA_TRIANGLE_STIPPLE +0x421C GA_POINT_SIZE +0x4230 GA_POINT_MINMAX +0x4234 GA_LINE_CNTL +0x4238 GA_LINE_STIPPLE_CONFIG +0x4260 GA_LINE_STIPPLE_VALUE +0x4264 GA_LINE_S0 +0x4268 GA_LINE_S1 +0x4278 GA_COLOR_CONTROL +0x427C GA_SOLID_RG +0x4280 GA_SOLID_BA +0x4288 GA_POLY_MODE +0x428C GA_ROUND_MODE +0x4290 GA_OFFSET +0x4294 GA_FOG_SCALE +0x4298 GA_FOG_OFFSET +0x42A0 SU_TEX_WRAP +0x42A4 SU_POLY_OFFSET_FRONT_SCALE +0x42A8 SU_POLY_OFFSET_FRONT_OFFSET +0x42AC SU_POLY_OFFSET_BACK_SCALE +0x42B0 SU_POLY_OFFSET_BACK_OFFSET +0x42B4 SU_POLY_OFFSET_ENABLE +0x42B8 SU_CULL_MODE +0x42C0 SU_DEPTH_SCALE +0x42C4 SU_DEPTH_OFFSET +0x42C8 SU_REG_DEST +0x4300 RS_COUNT +0x4304 RS_INST_COUNT +0x4310 RS_IP_0 +0x4314 RS_IP_1 +0x4318 RS_IP_2 +0x431C RS_IP_3 +0x4320 RS_IP_4 +0x4324 RS_IP_5 +0x4328 RS_IP_6 +0x432C RS_IP_7 +0x4330 RS_INST_0 +0x4334 RS_INST_1 +0x4338 RS_INST_2 +0x433C RS_INST_3 +0x4340 RS_INST_4 +0x4344 RS_INST_5 +0x4348 RS_INST_6 +0x434C RS_INST_7 +0x4350 RS_INST_8 +0x4354 RS_INST_9 +0x4358 RS_INST_10 +0x435C RS_INST_11 +0x4360 RS_INST_12 +0x4364 RS_INST_13 +0x4368 RS_INST_14 +0x436C RS_INST_15 +0x43A4 SC_HYPERZ_EN +0x43A8 SC_EDGERULE +0x43B0 SC_CLIP_0_A +0x43B4 SC_CLIP_0_B +0x43B8 SC_CLIP_1_A +0x43BC SC_CLIP_1_B +0x43C0 SC_CLIP_2_A +0x43C4 SC_CLIP_2_B +0x43C8 SC_CLIP_3_A +0x43CC SC_CLIP_3_B +0x43D0 SC_CLIP_RULE +0x43E0 SC_SCISSOR0 +0x43E8 SC_SCREENDOOR +0x4440 TX_FILTER1_0 +0x4444 TX_FILTER1_1 +0x4448 TX_FILTER1_2 +0x444C TX_FILTER1_3 +0x4450 TX_FILTER1_4 +0x4454 TX_FILTER1_5 +0x4458 TX_FILTER1_6 +0x445C TX_FILTER1_7 +0x4460 TX_FILTER1_8 +0x4464 TX_FILTER1_9 +0x4468 TX_FILTER1_10 +0x446C TX_FILTER1_11 +0x4470 TX_FILTER1_12 +0x4474 TX_FILTER1_13 +0x4478 TX_FILTER1_14 +0x447C TX_FILTER1_15 +0x4580 TX_CHROMA_KEY_0 +0x4584 TX_CHROMA_KEY_1 +0x4588 TX_CHROMA_KEY_2 +0x458C TX_CHROMA_KEY_3 +0x4590 TX_CHROMA_KEY_4 +0x4594 TX_CHROMA_KEY_5 +0x4598 TX_CHROMA_KEY_6 +0x459C TX_CHROMA_KEY_7 +0x45A0 TX_CHROMA_KEY_8 +0x45A4 TX_CHROMA_KEY_9 +0x45A8 TX_CHROMA_KEY_10 +0x45AC TX_CHROMA_KEY_11 +0x45B0 TX_CHROMA_KEY_12 +0x45B4 TX_CHROMA_KEY_13 +0x45B8 TX_CHROMA_KEY_14 +0x45BC TX_CHROMA_KEY_15 +0x45C0 TX_BORDER_COLOR_0 +0x45C4 TX_BORDER_COLOR_1 +0x45C8 TX_BORDER_COLOR_2 +0x45CC TX_BORDER_COLOR_3 +0x45D0 TX_BORDER_COLOR_4 +0x45D4 TX_BORDER_COLOR_5 +0x45D8 TX_BORDER_COLOR_6 +0x45DC TX_BORDER_COLOR_7 +0x45E0 TX_BORDER_COLOR_8 +0x45E4 TX_BORDER_COLOR_9 +0x45E8 TX_BORDER_COLOR_10 +0x45EC TX_BORDER_COLOR_11 +0x45F0 TX_BORDER_COLOR_12 +0x45F4 TX_BORDER_COLOR_13 +0x45F8 TX_BORDER_COLOR_14 +0x45FC TX_BORDER_COLOR_15 +0x4600 US_CONFIG +0x4604 US_PIXSIZE +0x4608 US_CODE_OFFSET +0x460C US_RESET +0x4610 US_CODE_ADDR_0 +0x4614 US_CODE_ADDR_1 +0x4618 US_CODE_ADDR_2 +0x461C US_CODE_ADDR_3 +0x4620 US_TEX_INST_0 +0x4624 US_TEX_INST_1 +0x4628 US_TEX_INST_2 +0x462C US_TEX_INST_3 +0x4630 US_TEX_INST_4 +0x4634 US_TEX_INST_5 +0x4638 US_TEX_INST_6 +0x463C US_TEX_INST_7 +0x4640 US_TEX_INST_8 +0x4644 US_TEX_INST_9 +0x4648 US_TEX_INST_10 +0x464C US_TEX_INST_11 +0x4650 US_TEX_INST_12 +0x4654 US_TEX_INST_13 +0x4658 US_TEX_INST_14 +0x465C US_TEX_INST_15 +0x4660 US_TEX_INST_16 +0x4664 US_TEX_INST_17 +0x4668 US_TEX_INST_18 +0x466C US_TEX_INST_19 +0x4670 US_TEX_INST_20 +0x4674 US_TEX_INST_21 +0x4678 US_TEX_INST_22 +0x467C US_TEX_INST_23 +0x4680 US_TEX_INST_24 +0x4684 US_TEX_INST_25 +0x4688 US_TEX_INST_26 +0x468C US_TEX_INST_27 +0x4690 US_TEX_INST_28 +0x4694 US_TEX_INST_29 +0x4698 US_TEX_INST_30 +0x469C US_TEX_INST_31 +0x46A4 US_OUT_FMT_0 +0x46A8 US_OUT_FMT_1 +0x46AC US_OUT_FMT_2 +0x46B0 US_OUT_FMT_3 +0x46B4 US_W_FMT +0x46C0 US_ALU_RGB_ADDR_0 +0x46C4 US_ALU_RGB_ADDR_1 +0x46C8 US_ALU_RGB_ADDR_2 +0x46CC US_ALU_RGB_ADDR_3 +0x46D0 US_ALU_RGB_ADDR_4 +0x46D4 US_ALU_RGB_ADDR_5 +0x46D8 US_ALU_RGB_ADDR_6 +0x46DC US_ALU_RGB_ADDR_7 +0x46E0 US_ALU_RGB_ADDR_8 +0x46E4 US_ALU_RGB_ADDR_9 +0x46E8 US_ALU_RGB_ADDR_10 +0x46EC US_ALU_RGB_ADDR_11 +0x46F0 US_ALU_RGB_ADDR_12 +0x46F4 US_ALU_RGB_ADDR_13 +0x46F8 US_ALU_RGB_ADDR_14 +0x46FC US_ALU_RGB_ADDR_15 +0x4700 US_ALU_RGB_ADDR_16 +0x4704 US_ALU_RGB_ADDR_17 +0x4708 US_ALU_RGB_ADDR_18 +0x470C US_ALU_RGB_ADDR_19 +0x4710 US_ALU_RGB_ADDR_20 +0x4714 US_ALU_RGB_ADDR_21 +0x4718 US_ALU_RGB_ADDR_22 +0x471C US_ALU_RGB_ADDR_23 +0x4720 US_ALU_RGB_ADDR_24 +0x4724 US_ALU_RGB_ADDR_25 +0x4728 US_ALU_RGB_ADDR_26 +0x472C US_ALU_RGB_ADDR_27 +0x4730 US_ALU_RGB_ADDR_28 +0x4734 US_ALU_RGB_ADDR_29 +0x4738 US_ALU_RGB_ADDR_30 +0x473C US_ALU_RGB_ADDR_31 +0x4740 US_ALU_RGB_ADDR_32 +0x4744 US_ALU_RGB_ADDR_33 +0x4748 US_ALU_RGB_ADDR_34 +0x474C US_ALU_RGB_ADDR_35 +0x4750 US_ALU_RGB_ADDR_36 +0x4754 US_ALU_RGB_ADDR_37 +0x4758 US_ALU_RGB_ADDR_38 +0x475C US_ALU_RGB_ADDR_39 +0x4760 US_ALU_RGB_ADDR_40 +0x4764 US_ALU_RGB_ADDR_41 +0x4768 US_ALU_RGB_ADDR_42 +0x476C US_ALU_RGB_ADDR_43 +0x4770 US_ALU_RGB_ADDR_44 +0x4774 US_ALU_RGB_ADDR_45 +0x4778 US_ALU_RGB_ADDR_46 +0x477C US_ALU_RGB_ADDR_47 +0x4780 US_ALU_RGB_ADDR_48 +0x4784 US_ALU_RGB_ADDR_49 +0x4788 US_ALU_RGB_ADDR_50 +0x478C US_ALU_RGB_ADDR_51 +0x4790 US_ALU_RGB_ADDR_52 +0x4794 US_ALU_RGB_ADDR_53 +0x4798 US_ALU_RGB_ADDR_54 +0x479C US_ALU_RGB_ADDR_55 +0x47A0 US_ALU_RGB_ADDR_56 +0x47A4 US_ALU_RGB_ADDR_57 +0x47A8 US_ALU_RGB_ADDR_58 +0x47AC US_ALU_RGB_ADDR_59 +0x47B0 US_ALU_RGB_ADDR_60 +0x47B4 US_ALU_RGB_ADDR_61 +0x47B8 US_ALU_RGB_ADDR_62 +0x47BC US_ALU_RGB_ADDR_63 +0x47C0 US_ALU_ALPHA_ADDR_0 +0x47C4 US_ALU_ALPHA_ADDR_1 +0x47C8 US_ALU_ALPHA_ADDR_2 +0x47CC US_ALU_ALPHA_ADDR_3 +0x47D0 US_ALU_ALPHA_ADDR_4 +0x47D4 US_ALU_ALPHA_ADDR_5 +0x47D8 US_ALU_ALPHA_ADDR_6 +0x47DC US_ALU_ALPHA_ADDR_7 +0x47E0 US_ALU_ALPHA_ADDR_8 +0x47E4 US_ALU_ALPHA_ADDR_9 +0x47E8 US_ALU_ALPHA_ADDR_10 +0x47EC US_ALU_ALPHA_ADDR_11 +0x47F0 US_ALU_ALPHA_ADDR_12 +0x47F4 US_ALU_ALPHA_ADDR_13 +0x47F8 US_ALU_ALPHA_ADDR_14 +0x47FC US_ALU_ALPHA_ADDR_15 +0x4800 US_ALU_ALPHA_ADDR_16 +0x4804 US_ALU_ALPHA_ADDR_17 +0x4808 US_ALU_ALPHA_ADDR_18 +0x480C US_ALU_ALPHA_ADDR_19 +0x4810 US_ALU_ALPHA_ADDR_20 +0x4814 US_ALU_ALPHA_ADDR_21 +0x4818 US_ALU_ALPHA_ADDR_22 +0x481C US_ALU_ALPHA_ADDR_23 +0x4820 US_ALU_ALPHA_ADDR_24 +0x4824 US_ALU_ALPHA_ADDR_25 +0x4828 US_ALU_ALPHA_ADDR_26 +0x482C US_ALU_ALPHA_ADDR_27 +0x4830 US_ALU_ALPHA_ADDR_28 +0x4834 US_ALU_ALPHA_ADDR_29 +0x4838 US_ALU_ALPHA_ADDR_30 +0x483C US_ALU_ALPHA_ADDR_31 +0x4840 US_ALU_ALPHA_ADDR_32 +0x4844 US_ALU_ALPHA_ADDR_33 +0x4848 US_ALU_ALPHA_ADDR_34 +0x484C US_ALU_ALPHA_ADDR_35 +0x4850 US_ALU_ALPHA_ADDR_36 +0x4854 US_ALU_ALPHA_ADDR_37 +0x4858 US_ALU_ALPHA_ADDR_38 +0x485C US_ALU_ALPHA_ADDR_39 +0x4860 US_ALU_ALPHA_ADDR_40 +0x4864 US_ALU_ALPHA_ADDR_41 +0x4868 US_ALU_ALPHA_ADDR_42 +0x486C US_ALU_ALPHA_ADDR_43 +0x4870 US_ALU_ALPHA_ADDR_44 +0x4874 US_ALU_ALPHA_ADDR_45 +0x4878 US_ALU_ALPHA_ADDR_46 +0x487C US_ALU_ALPHA_ADDR_47 +0x4880 US_ALU_ALPHA_ADDR_48 +0x4884 US_ALU_ALPHA_ADDR_49 +0x4888 US_ALU_ALPHA_ADDR_50 +0x488C US_ALU_ALPHA_ADDR_51 +0x4890 US_ALU_ALPHA_ADDR_52 +0x4894 US_ALU_ALPHA_ADDR_53 +0x4898 US_ALU_ALPHA_ADDR_54 +0x489C US_ALU_ALPHA_ADDR_55 +0x48A0 US_ALU_ALPHA_ADDR_56 +0x48A4 US_ALU_ALPHA_ADDR_57 +0x48A8 US_ALU_ALPHA_ADDR_58 +0x48AC US_ALU_ALPHA_ADDR_59 +0x48B0 US_ALU_ALPHA_ADDR_60 +0x48B4 US_ALU_ALPHA_ADDR_61 +0x48B8 US_ALU_ALPHA_ADDR_62 +0x48BC US_ALU_ALPHA_ADDR_63 +0x48C0 US_ALU_RGB_INST_0 +0x48C4 US_ALU_RGB_INST_1 +0x48C8 US_ALU_RGB_INST_2 +0x48CC US_ALU_RGB_INST_3 +0x48D0 US_ALU_RGB_INST_4 +0x48D4 US_ALU_RGB_INST_5 +0x48D8 US_ALU_RGB_INST_6 +0x48DC US_ALU_RGB_INST_7 +0x48E0 US_ALU_RGB_INST_8 +0x48E4 US_ALU_RGB_INST_9 +0x48E8 US_ALU_RGB_INST_10 +0x48EC US_ALU_RGB_INST_11 +0x48F0 US_ALU_RGB_INST_12 +0x48F4 US_ALU_RGB_INST_13 +0x48F8 US_ALU_RGB_INST_14 +0x48FC US_ALU_RGB_INST_15 +0x4900 US_ALU_RGB_INST_16 +0x4904 US_ALU_RGB_INST_17 +0x4908 US_ALU_RGB_INST_18 +0x490C US_ALU_RGB_INST_19 +0x4910 US_ALU_RGB_INST_20 +0x4914 US_ALU_RGB_INST_21 +0x4918 US_ALU_RGB_INST_22 +0x491C US_ALU_RGB_INST_23 +0x4920 US_ALU_RGB_INST_24 +0x4924 US_ALU_RGB_INST_25 +0x4928 US_ALU_RGB_INST_26 +0x492C US_ALU_RGB_INST_27 +0x4930 US_ALU_RGB_INST_28 +0x4934 US_ALU_RGB_INST_29 +0x4938 US_ALU_RGB_INST_30 +0x493C US_ALU_RGB_INST_31 +0x4940 US_ALU_RGB_INST_32 +0x4944 US_ALU_RGB_INST_33 +0x4948 US_ALU_RGB_INST_34 +0x494C US_ALU_RGB_INST_35 +0x4950 US_ALU_RGB_INST_36 +0x4954 US_ALU_RGB_INST_37 +0x4958 US_ALU_RGB_INST_38 +0x495C US_ALU_RGB_INST_39 +0x4960 US_ALU_RGB_INST_40 +0x4964 US_ALU_RGB_INST_41 +0x4968 US_ALU_RGB_INST_42 +0x496C US_ALU_RGB_INST_43 +0x4970 US_ALU_RGB_INST_44 +0x4974 US_ALU_RGB_INST_45 +0x4978 US_ALU_RGB_INST_46 +0x497C US_ALU_RGB_INST_47 +0x4980 US_ALU_RGB_INST_48 +0x4984 US_ALU_RGB_INST_49 +0x4988 US_ALU_RGB_INST_50 +0x498C US_ALU_RGB_INST_51 +0x4990 US_ALU_RGB_INST_52 +0x4994 US_ALU_RGB_INST_53 +0x4998 US_ALU_RGB_INST_54 +0x499C US_ALU_RGB_INST_55 +0x49A0 US_ALU_RGB_INST_56 +0x49A4 US_ALU_RGB_INST_57 +0x49A8 US_ALU_RGB_INST_58 +0x49AC US_ALU_RGB_INST_59 +0x49B0 US_ALU_RGB_INST_60 +0x49B4 US_ALU_RGB_INST_61 +0x49B8 US_ALU_RGB_INST_62 +0x49BC US_ALU_RGB_INST_63 +0x49C0 US_ALU_ALPHA_INST_0 +0x49C4 US_ALU_ALPHA_INST_1 +0x49C8 US_ALU_ALPHA_INST_2 +0x49CC US_ALU_ALPHA_INST_3 +0x49D0 US_ALU_ALPHA_INST_4 +0x49D4 US_ALU_ALPHA_INST_5 +0x49D8 US_ALU_ALPHA_INST_6 +0x49DC US_ALU_ALPHA_INST_7 +0x49E0 US_ALU_ALPHA_INST_8 +0x49E4 US_ALU_ALPHA_INST_9 +0x49E8 US_ALU_ALPHA_INST_10 +0x49EC US_ALU_ALPHA_INST_11 +0x49F0 US_ALU_ALPHA_INST_12 +0x49F4 US_ALU_ALPHA_INST_13 +0x49F8 US_ALU_ALPHA_INST_14 +0x49FC US_ALU_ALPHA_INST_15 +0x4A00 US_ALU_ALPHA_INST_16 +0x4A04 US_ALU_ALPHA_INST_17 +0x4A08 US_ALU_ALPHA_INST_18 +0x4A0C US_ALU_ALPHA_INST_19 +0x4A10 US_ALU_ALPHA_INST_20 +0x4A14 US_ALU_ALPHA_INST_21 +0x4A18 US_ALU_ALPHA_INST_22 +0x4A1C US_ALU_ALPHA_INST_23 +0x4A20 US_ALU_ALPHA_INST_24 +0x4A24 US_ALU_ALPHA_INST_25 +0x4A28 US_ALU_ALPHA_INST_26 +0x4A2C US_ALU_ALPHA_INST_27 +0x4A30 US_ALU_ALPHA_INST_28 +0x4A34 US_ALU_ALPHA_INST_29 +0x4A38 US_ALU_ALPHA_INST_30 +0x4A3C US_ALU_ALPHA_INST_31 +0x4A40 US_ALU_ALPHA_INST_32 +0x4A44 US_ALU_ALPHA_INST_33 +0x4A48 US_ALU_ALPHA_INST_34 +0x4A4C US_ALU_ALPHA_INST_35 +0x4A50 US_ALU_ALPHA_INST_36 +0x4A54 US_ALU_ALPHA_INST_37 +0x4A58 US_ALU_ALPHA_INST_38 +0x4A5C US_ALU_ALPHA_INST_39 +0x4A60 US_ALU_ALPHA_INST_40 +0x4A64 US_ALU_ALPHA_INST_41 +0x4A68 US_ALU_ALPHA_INST_42 +0x4A6C US_ALU_ALPHA_INST_43 +0x4A70 US_ALU_ALPHA_INST_44 +0x4A74 US_ALU_ALPHA_INST_45 +0x4A78 US_ALU_ALPHA_INST_46 +0x4A7C US_ALU_ALPHA_INST_47 +0x4A80 US_ALU_ALPHA_INST_48 +0x4A84 US_ALU_ALPHA_INST_49 +0x4A88 US_ALU_ALPHA_INST_50 +0x4A8C US_ALU_ALPHA_INST_51 +0x4A90 US_ALU_ALPHA_INST_52 +0x4A94 US_ALU_ALPHA_INST_53 +0x4A98 US_ALU_ALPHA_INST_54 +0x4A9C US_ALU_ALPHA_INST_55 +0x4AA0 US_ALU_ALPHA_INST_56 +0x4AA4 US_ALU_ALPHA_INST_57 +0x4AA8 US_ALU_ALPHA_INST_58 +0x4AAC US_ALU_ALPHA_INST_59 +0x4AB0 US_ALU_ALPHA_INST_60 +0x4AB4 US_ALU_ALPHA_INST_61 +0x4AB8 US_ALU_ALPHA_INST_62 +0x4ABC US_ALU_ALPHA_INST_63 +0x4BC0 FG_FOG_BLEND +0x4BC4 FG_FOG_FACTOR +0x4BC8 FG_FOG_COLOR_R +0x4BCC FG_FOG_COLOR_G +0x4BD0 FG_FOG_COLOR_B +0x4BD4 FG_ALPHA_FUNC +0x4BD8 FG_DEPTH_SRC +0x4C00 US_ALU_CONST_R_0 +0x4C04 US_ALU_CONST_G_0 +0x4C08 US_ALU_CONST_B_0 +0x4C0C US_ALU_CONST_A_0 +0x4C10 US_ALU_CONST_R_1 +0x4C14 US_ALU_CONST_G_1 +0x4C18 US_ALU_CONST_B_1 +0x4C1C US_ALU_CONST_A_1 +0x4C20 US_ALU_CONST_R_2 +0x4C24 US_ALU_CONST_G_2 +0x4C28 US_ALU_CONST_B_2 +0x4C2C US_ALU_CONST_A_2 +0x4C30 US_ALU_CONST_R_3 +0x4C34 US_ALU_CONST_G_3 +0x4C38 US_ALU_CONST_B_3 +0x4C3C US_ALU_CONST_A_3 +0x4C40 US_ALU_CONST_R_4 +0x4C44 US_ALU_CONST_G_4 +0x4C48 US_ALU_CONST_B_4 +0x4C4C US_ALU_CONST_A_4 +0x4C50 US_ALU_CONST_R_5 +0x4C54 US_ALU_CONST_G_5 +0x4C58 US_ALU_CONST_B_5 +0x4C5C US_ALU_CONST_A_5 +0x4C60 US_ALU_CONST_R_6 +0x4C64 US_ALU_CONST_G_6 +0x4C68 US_ALU_CONST_B_6 +0x4C6C US_ALU_CONST_A_6 +0x4C70 US_ALU_CONST_R_7 +0x4C74 US_ALU_CONST_G_7 +0x4C78 US_ALU_CONST_B_7 +0x4C7C US_ALU_CONST_A_7 +0x4C80 US_ALU_CONST_R_8 +0x4C84 US_ALU_CONST_G_8 +0x4C88 US_ALU_CONST_B_8 +0x4C8C US_ALU_CONST_A_8 +0x4C90 US_ALU_CONST_R_9 +0x4C94 US_ALU_CONST_G_9 +0x4C98 US_ALU_CONST_B_9 +0x4C9C US_ALU_CONST_A_9 +0x4CA0 US_ALU_CONST_R_10 +0x4CA4 US_ALU_CONST_G_10 +0x4CA8 US_ALU_CONST_B_10 +0x4CAC US_ALU_CONST_A_10 +0x4CB0 US_ALU_CONST_R_11 +0x4CB4 US_ALU_CONST_G_11 +0x4CB8 US_ALU_CONST_B_11 +0x4CBC US_ALU_CONST_A_11 +0x4CC0 US_ALU_CONST_R_12 +0x4CC4 US_ALU_CONST_G_12 +0x4CC8 US_ALU_CONST_B_12 +0x4CCC US_ALU_CONST_A_12 +0x4CD0 US_ALU_CONST_R_13 +0x4CD4 US_ALU_CONST_G_13 +0x4CD8 US_ALU_CONST_B_13 +0x4CDC US_ALU_CONST_A_13 +0x4CE0 US_ALU_CONST_R_14 +0x4CE4 US_ALU_CONST_G_14 +0x4CE8 US_ALU_CONST_B_14 +0x4CEC US_ALU_CONST_A_14 +0x4CF0 US_ALU_CONST_R_15 +0x4CF4 US_ALU_CONST_G_15 +0x4CF8 US_ALU_CONST_B_15 +0x4CFC US_ALU_CONST_A_15 +0x4D00 US_ALU_CONST_R_16 +0x4D04 US_ALU_CONST_G_16 +0x4D08 US_ALU_CONST_B_16 +0x4D0C US_ALU_CONST_A_16 +0x4D10 US_ALU_CONST_R_17 +0x4D14 US_ALU_CONST_G_17 +0x4D18 US_ALU_CONST_B_17 +0x4D1C US_ALU_CONST_A_17 +0x4D20 US_ALU_CONST_R_18 +0x4D24 US_ALU_CONST_G_18 +0x4D28 US_ALU_CONST_B_18 +0x4D2C US_ALU_CONST_A_18 +0x4D30 US_ALU_CONST_R_19 +0x4D34 US_ALU_CONST_G_19 +0x4D38 US_ALU_CONST_B_19 +0x4D3C US_ALU_CONST_A_19 +0x4D40 US_ALU_CONST_R_20 +0x4D44 US_ALU_CONST_G_20 +0x4D48 US_ALU_CONST_B_20 +0x4D4C US_ALU_CONST_A_20 +0x4D50 US_ALU_CONST_R_21 +0x4D54 US_ALU_CONST_G_21 +0x4D58 US_ALU_CONST_B_21 +0x4D5C US_ALU_CONST_A_21 +0x4D60 US_ALU_CONST_R_22 +0x4D64 US_ALU_CONST_G_22 +0x4D68 US_ALU_CONST_B_22 +0x4D6C US_ALU_CONST_A_22 +0x4D70 US_ALU_CONST_R_23 +0x4D74 US_ALU_CONST_G_23 +0x4D78 US_ALU_CONST_B_23 +0x4D7C US_ALU_CONST_A_23 +0x4D80 US_ALU_CONST_R_24 +0x4D84 US_ALU_CONST_G_24 +0x4D88 US_ALU_CONST_B_24 +0x4D8C US_ALU_CONST_A_24 +0x4D90 US_ALU_CONST_R_25 +0x4D94 US_ALU_CONST_G_25 +0x4D98 US_ALU_CONST_B_25 +0x4D9C US_ALU_CONST_A_25 +0x4DA0 US_ALU_CONST_R_26 +0x4DA4 US_ALU_CONST_G_26 +0x4DA8 US_ALU_CONST_B_26 +0x4DAC US_ALU_CONST_A_26 +0x4DB0 US_ALU_CONST_R_27 +0x4DB4 US_ALU_CONST_G_27 +0x4DB8 US_ALU_CONST_B_27 +0x4DBC US_ALU_CONST_A_27 +0x4DC0 US_ALU_CONST_R_28 +0x4DC4 US_ALU_CONST_G_28 +0x4DC8 US_ALU_CONST_B_28 +0x4DCC US_ALU_CONST_A_28 +0x4DD0 US_ALU_CONST_R_29 +0x4DD4 US_ALU_CONST_G_29 +0x4DD8 US_ALU_CONST_B_29 +0x4DDC US_ALU_CONST_A_29 +0x4DE0 US_ALU_CONST_R_30 +0x4DE4 US_ALU_CONST_G_30 +0x4DE8 US_ALU_CONST_B_30 +0x4DEC US_ALU_CONST_A_30 +0x4DF0 US_ALU_CONST_R_31 +0x4DF4 US_ALU_CONST_G_31 +0x4DF8 US_ALU_CONST_B_31 +0x4DFC US_ALU_CONST_A_31 +0x4E04 RB3D_BLENDCNTL_R3 +0x4E08 RB3D_ABLENDCNTL_R3 +0x4E0C RB3D_COLOR_CHANNEL_MASK +0x4E10 RB3D_CONSTANT_COLOR +0x4E14 RB3D_COLOR_CLEAR_VALUE +0x4E18 RB3D_ROPCNTL_R3 +0x4E1C RB3D_CLRCMP_FLIPE_R3 +0x4E20 RB3D_CLRCMP_CLR_R3 +0x4E24 RB3D_CLRCMP_MSK_R3 +0x4E48 RB3D_DEBUG_CTL +0x4E4C RB3D_DSTCACHE_CTLSTAT_R3 +0x4E50 RB3D_DITHER_CTL +0x4E54 RB3D_CMASK_OFFSET0 +0x4E58 RB3D_CMASK_OFFSET1 +0x4E5C RB3D_CMASK_OFFSET2 +0x4E60 RB3D_CMASK_OFFSET3 +0x4E64 RB3D_CMASK_PITCH0 +0x4E68 RB3D_CMASK_PITCH1 +0x4E6C RB3D_CMASK_PITCH2 +0x4E70 RB3D_CMASK_PITCH3 +0x4E74 RB3D_CMASK_WRINDEX +0x4E78 RB3D_CMASK_DWORD +0x4E7C RB3D_CMASK_RDINDEX +0x4E80 RB3D_AARESOLVE_OFFSET +0x4E84 RB3D_AARESOLVE_PITCH +0x4E88 RB3D_AARESOLVE_CTL +0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD +0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD +0x4F04 ZB_ZSTENCILCNTL +0x4F08 ZB_STENCILREFMASK +0x4F14 ZB_ZTOP +0x4F18 ZB_ZCACHE_CTLSTAT +0x4F1C ZB_BW_CNTL +0x4F28 ZB_DEPTHCLEARVALUE +0x4F30 ZB_ZMASK_OFFSET +0x4F34 ZB_ZMASK_PITCH +0x4F38 ZB_ZMASK_WRINDEX +0x4F3C ZB_ZMASK_DWORD +0x4F40 ZB_ZMASK_RDINDEX +0x4F44 ZB_HIZ_OFFSET +0x4F48 ZB_HIZ_WRINDEX +0x4F4C ZB_HIZ_DWORD +0x4F50 ZB_HIZ_RDINDEX +0x4F54 ZB_HIZ_PITCH +0x4F58 ZB_ZPASS_DATA diff --git a/drivers/gpu/drm/radeon/reg_srcs/rn50 b/drivers/gpu/drm/radeon/reg_srcs/rn50 new file mode 100644 index 000000000000..2687b6307260 --- /dev/null +++ b/drivers/gpu/drm/radeon/reg_srcs/rn50 @@ -0,0 +1,30 @@ +rn50 0x3294 +0x1434 SRC_Y_X +0x1438 DST_Y_X +0x143C DST_HEIGHT_WIDTH +0x146C DP_GUI_MASTER_CNTL +0x1474 BRUSH_Y_X +0x1478 DP_BRUSH_BKGD_CLR +0x147C DP_BRUSH_FRGD_CLR +0x1480 BRUSH_DATA0 +0x1484 BRUSH_DATA1 +0x1598 DST_WIDTH_HEIGHT +0x15C0 CLR_CMP_CNTL +0x15C4 CLR_CMP_CLR_SRC +0x15C8 CLR_CMP_CLR_DST +0x15CC CLR_CMP_MSK +0x15D8 DP_SRC_FRGD_CLR +0x15DC DP_SRC_BKGD_CLR +0x1600 DST_LINE_START +0x1604 DST_LINE_END +0x1608 DST_LINE_PATCOUNT +0x16C0 DP_CNTL +0x16CC DP_WRITE_MSK +0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR +0x16E8 DEFAULT_SC_BOTTOM_RIGHT +0x16EC SC_TOP_LEFT +0x16F0 SC_BOTTOM_RIGHT +0x16F4 SRC_SC_BOTTOM_RIGHT +0x1714 DSTCACHE_CTLSTAT +0x1720 WAIT_UNTIL +0x172C RBBM_GUICNTL diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600 new file mode 100644 index 000000000000..8e3c0b807add --- /dev/null +++ b/drivers/gpu/drm/radeon/reg_srcs/rs600 @@ -0,0 +1,729 @@ +rs600 0x6d40 +0x1434 SRC_Y_X +0x1438 DST_Y_X +0x143C DST_HEIGHT_WIDTH +0x146C DP_GUI_MASTER_CNTL +0x1474 BRUSH_Y_X +0x1478 DP_BRUSH_BKGD_CLR +0x147C DP_BRUSH_FRGD_CLR +0x1480 BRUSH_DATA0 +0x1484 BRUSH_DATA1 +0x1598 DST_WIDTH_HEIGHT +0x15C0 CLR_CMP_CNTL +0x15C4 CLR_CMP_CLR_SRC +0x15C8 CLR_CMP_CLR_DST +0x15CC CLR_CMP_MSK +0x15D8 DP_SRC_FRGD_CLR +0x15DC DP_SRC_BKGD_CLR +0x1600 DST_LINE_START +0x1604 DST_LINE_END +0x1608 DST_LINE_PATCOUNT +0x16C0 DP_CNTL +0x16CC DP_WRITE_MSK +0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR +0x16E8 DEFAULT_SC_BOTTOM_RIGHT +0x16EC SC_TOP_LEFT +0x16F0 SC_BOTTOM_RIGHT +0x16F4 SRC_SC_BOTTOM_RIGHT +0x1714 DSTCACHE_CTLSTAT +0x1720 WAIT_UNTIL +0x172C RBBM_GUICNTL +0x1D98 VAP_VPORT_XSCALE +0x1D9C VAP_VPORT_XOFFSET +0x1DA0 VAP_VPORT_YSCALE +0x1DA4 VAP_VPORT_YOFFSET +0x1DA8 VAP_VPORT_ZSCALE +0x1DAC VAP_VPORT_ZOFFSET +0x2080 VAP_CNTL +0x2090 VAP_OUT_VTX_FMT_0 +0x2094 VAP_OUT_VTX_FMT_1 +0x20B0 VAP_VTE_CNTL +0x2138 VAP_VF_MIN_VTX_INDX +0x2140 VAP_CNTL_STATUS +0x2150 VAP_PROG_STREAM_CNTL_0 +0x2154 VAP_PROG_STREAM_CNTL_1 +0x2158 VAP_PROG_STREAM_CNTL_2 +0x215C VAP_PROG_STREAM_CNTL_3 +0x2160 VAP_PROG_STREAM_CNTL_4 +0x2164 VAP_PROG_STREAM_CNTL_5 +0x2168 VAP_PROG_STREAM_CNTL_6 +0x216C VAP_PROG_STREAM_CNTL_7 +0x2180 VAP_VTX_STATE_CNTL +0x2184 VAP_VSM_VTX_ASSM +0x2188 VAP_VTX_STATE_IND_REG_0 +0x218C VAP_VTX_STATE_IND_REG_1 +0x2190 VAP_VTX_STATE_IND_REG_2 +0x2194 VAP_VTX_STATE_IND_REG_3 +0x2198 VAP_VTX_STATE_IND_REG_4 +0x219C VAP_VTX_STATE_IND_REG_5 +0x21A0 VAP_VTX_STATE_IND_REG_6 +0x21A4 VAP_VTX_STATE_IND_REG_7 +0x21A8 VAP_VTX_STATE_IND_REG_8 +0x21AC VAP_VTX_STATE_IND_REG_9 +0x21B0 VAP_VTX_STATE_IND_REG_10 +0x21B4 VAP_VTX_STATE_IND_REG_11 +0x21B8 VAP_VTX_STATE_IND_REG_12 +0x21BC VAP_VTX_STATE_IND_REG_13 +0x21C0 VAP_VTX_STATE_IND_REG_14 +0x21C4 VAP_VTX_STATE_IND_REG_15 +0x21DC VAP_PSC_SGN_NORM_CNTL +0x21E0 VAP_PROG_STREAM_CNTL_EXT_0 +0x21E4 VAP_PROG_STREAM_CNTL_EXT_1 +0x21E8 VAP_PROG_STREAM_CNTL_EXT_2 +0x21EC VAP_PROG_STREAM_CNTL_EXT_3 +0x21F0 VAP_PROG_STREAM_CNTL_EXT_4 +0x21F4 VAP_PROG_STREAM_CNTL_EXT_5 +0x21F8 VAP_PROG_STREAM_CNTL_EXT_6 +0x21FC VAP_PROG_STREAM_CNTL_EXT_7 +0x2200 VAP_PVS_VECTOR_INDX_REG +0x2204 VAP_PVS_VECTOR_DATA_REG +0x2208 VAP_PVS_VECTOR_DATA_REG_128 +0x221C VAP_CLIP_CNTL +0x2220 VAP_GB_VERT_CLIP_ADJ +0x2224 VAP_GB_VERT_DISC_ADJ +0x2228 VAP_GB_HORZ_CLIP_ADJ +0x222C VAP_GB_HORZ_DISC_ADJ +0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0 +0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1 +0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2 +0x223C VAP_PVS_FLOW_CNTL_ADDRS_3 +0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4 +0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5 +0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6 +0x224C VAP_PVS_FLOW_CNTL_ADDRS_7 +0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8 +0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9 +0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10 +0x225C VAP_PVS_FLOW_CNTL_ADDRS_11 +0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12 +0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13 +0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14 +0x226C VAP_PVS_FLOW_CNTL_ADDRS_15 +0x2284 VAP_PVS_STATE_FLUSH_REG +0x2288 VAP_PVS_VTX_TIMEOUT_REG +0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0 +0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1 +0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2 +0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3 +0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4 +0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5 +0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6 +0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7 +0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8 +0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9 +0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10 +0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11 +0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12 +0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13 +0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14 +0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15 +0x22D0 VAP_PVS_CODE_CNTL_0 +0x22D4 VAP_PVS_CONST_CNTL +0x22D8 VAP_PVS_CODE_CNTL_1 +0x22DC VAP_PVS_FLOW_CNTL_OPC +0x342C RB2D_DSTCACHE_CTLSTAT +0x4000 GB_VAP_RASTER_VTX_FMT_0 +0x4004 GB_VAP_RASTER_VTX_FMT_1 +0x4008 GB_ENABLE +0x401C GB_SELECT +0x4020 GB_AA_CONFIG +0x4024 GB_FIFO_SIZE +0x4100 TX_INVALTAGS +0x4200 GA_POINT_S0 +0x4204 GA_POINT_T0 +0x4208 GA_POINT_S1 +0x420C GA_POINT_T1 +0x4214 GA_TRIANGLE_STIPPLE +0x421C GA_POINT_SIZE +0x4230 GA_POINT_MINMAX +0x4234 GA_LINE_CNTL +0x4238 GA_LINE_STIPPLE_CONFIG +0x4260 GA_LINE_STIPPLE_VALUE +0x4264 GA_LINE_S0 +0x4268 GA_LINE_S1 +0x4278 GA_COLOR_CONTROL +0x427C GA_SOLID_RG +0x4280 GA_SOLID_BA +0x4288 GA_POLY_MODE +0x428C GA_ROUND_MODE +0x4290 GA_OFFSET +0x4294 GA_FOG_SCALE +0x4298 GA_FOG_OFFSET +0x42A0 SU_TEX_WRAP +0x42A4 SU_POLY_OFFSET_FRONT_SCALE +0x42A8 SU_POLY_OFFSET_FRONT_OFFSET +0x42AC SU_POLY_OFFSET_BACK_SCALE +0x42B0 SU_POLY_OFFSET_BACK_OFFSET +0x42B4 SU_POLY_OFFSET_ENABLE +0x42B8 SU_CULL_MODE +0x42C0 SU_DEPTH_SCALE +0x42C4 SU_DEPTH_OFFSET +0x42C8 SU_REG_DEST +0x4300 RS_COUNT +0x4304 RS_INST_COUNT +0x4310 RS_IP_0 +0x4314 RS_IP_1 +0x4318 RS_IP_2 +0x431C RS_IP_3 +0x4320 RS_IP_4 +0x4324 RS_IP_5 +0x4328 RS_IP_6 +0x432C RS_IP_7 +0x4330 RS_INST_0 +0x4334 RS_INST_1 +0x4338 RS_INST_2 +0x433C RS_INST_3 +0x4340 RS_INST_4 +0x4344 RS_INST_5 +0x4348 RS_INST_6 +0x434C RS_INST_7 +0x4350 RS_INST_8 +0x4354 RS_INST_9 +0x4358 RS_INST_10 +0x435C RS_INST_11 +0x4360 RS_INST_12 +0x4364 RS_INST_13 +0x4368 RS_INST_14 +0x436C RS_INST_15 +0x43A4 SC_HYPERZ_EN +0x43A8 SC_EDGERULE +0x43B0 SC_CLIP_0_A +0x43B4 SC_CLIP_0_B +0x43B8 SC_CLIP_1_A +0x43BC SC_CLIP_1_B +0x43C0 SC_CLIP_2_A +0x43C4 SC_CLIP_2_B +0x43C8 SC_CLIP_3_A +0x43CC SC_CLIP_3_B +0x43D0 SC_CLIP_RULE +0x43E0 SC_SCISSOR0 +0x43E8 SC_SCREENDOOR +0x4440 TX_FILTER1_0 +0x4444 TX_FILTER1_1 +0x4448 TX_FILTER1_2 +0x444C TX_FILTER1_3 +0x4450 TX_FILTER1_4 +0x4454 TX_FILTER1_5 +0x4458 TX_FILTER1_6 +0x445C TX_FILTER1_7 +0x4460 TX_FILTER1_8 +0x4464 TX_FILTER1_9 +0x4468 TX_FILTER1_10 +0x446C TX_FILTER1_11 +0x4470 TX_FILTER1_12 +0x4474 TX_FILTER1_13 +0x4478 TX_FILTER1_14 +0x447C TX_FILTER1_15 +0x4580 TX_CHROMA_KEY_0 +0x4584 TX_CHROMA_KEY_1 +0x4588 TX_CHROMA_KEY_2 +0x458C TX_CHROMA_KEY_3 +0x4590 TX_CHROMA_KEY_4 +0x4594 TX_CHROMA_KEY_5 +0x4598 TX_CHROMA_KEY_6 +0x459C TX_CHROMA_KEY_7 +0x45A0 TX_CHROMA_KEY_8 +0x45A4 TX_CHROMA_KEY_9 +0x45A8 TX_CHROMA_KEY_10 +0x45AC TX_CHROMA_KEY_11 +0x45B0 TX_CHROMA_KEY_12 +0x45B4 TX_CHROMA_KEY_13 +0x45B8 TX_CHROMA_KEY_14 +0x45BC TX_CHROMA_KEY_15 +0x45C0 TX_BORDER_COLOR_0 +0x45C4 TX_BORDER_COLOR_1 +0x45C8 TX_BORDER_COLOR_2 +0x45CC TX_BORDER_COLOR_3 +0x45D0 TX_BORDER_COLOR_4 +0x45D4 TX_BORDER_COLOR_5 +0x45D8 TX_BORDER_COLOR_6 +0x45DC TX_BORDER_COLOR_7 +0x45E0 TX_BORDER_COLOR_8 +0x45E4 TX_BORDER_COLOR_9 +0x45E8 TX_BORDER_COLOR_10 +0x45EC TX_BORDER_COLOR_11 +0x45F0 TX_BORDER_COLOR_12 +0x45F4 TX_BORDER_COLOR_13 +0x45F8 TX_BORDER_COLOR_14 +0x45FC TX_BORDER_COLOR_15 +0x4600 US_CONFIG +0x4604 US_PIXSIZE +0x4608 US_CODE_OFFSET +0x460C US_RESET +0x4610 US_CODE_ADDR_0 +0x4614 US_CODE_ADDR_1 +0x4618 US_CODE_ADDR_2 +0x461C US_CODE_ADDR_3 +0x4620 US_TEX_INST_0 +0x4624 US_TEX_INST_1 +0x4628 US_TEX_INST_2 +0x462C US_TEX_INST_3 +0x4630 US_TEX_INST_4 +0x4634 US_TEX_INST_5 +0x4638 US_TEX_INST_6 +0x463C US_TEX_INST_7 +0x4640 US_TEX_INST_8 +0x4644 US_TEX_INST_9 +0x4648 US_TEX_INST_10 +0x464C US_TEX_INST_11 +0x4650 US_TEX_INST_12 +0x4654 US_TEX_INST_13 +0x4658 US_TEX_INST_14 +0x465C US_TEX_INST_15 +0x4660 US_TEX_INST_16 +0x4664 US_TEX_INST_17 +0x4668 US_TEX_INST_18 +0x466C US_TEX_INST_19 +0x4670 US_TEX_INST_20 +0x4674 US_TEX_INST_21 +0x4678 US_TEX_INST_22 +0x467C US_TEX_INST_23 +0x4680 US_TEX_INST_24 +0x4684 US_TEX_INST_25 +0x4688 US_TEX_INST_26 +0x468C US_TEX_INST_27 +0x4690 US_TEX_INST_28 +0x4694 US_TEX_INST_29 +0x4698 US_TEX_INST_30 +0x469C US_TEX_INST_31 +0x46A4 US_OUT_FMT_0 +0x46A8 US_OUT_FMT_1 +0x46AC US_OUT_FMT_2 +0x46B0 US_OUT_FMT_3 +0x46B4 US_W_FMT +0x46C0 US_ALU_RGB_ADDR_0 +0x46C4 US_ALU_RGB_ADDR_1 +0x46C8 US_ALU_RGB_ADDR_2 +0x46CC US_ALU_RGB_ADDR_3 +0x46D0 US_ALU_RGB_ADDR_4 +0x46D4 US_ALU_RGB_ADDR_5 +0x46D8 US_ALU_RGB_ADDR_6 +0x46DC US_ALU_RGB_ADDR_7 +0x46E0 US_ALU_RGB_ADDR_8 +0x46E4 US_ALU_RGB_ADDR_9 +0x46E8 US_ALU_RGB_ADDR_10 +0x46EC US_ALU_RGB_ADDR_11 +0x46F0 US_ALU_RGB_ADDR_12 +0x46F4 US_ALU_RGB_ADDR_13 +0x46F8 US_ALU_RGB_ADDR_14 +0x46FC US_ALU_RGB_ADDR_15 +0x4700 US_ALU_RGB_ADDR_16 +0x4704 US_ALU_RGB_ADDR_17 +0x4708 US_ALU_RGB_ADDR_18 +0x470C US_ALU_RGB_ADDR_19 +0x4710 US_ALU_RGB_ADDR_20 +0x4714 US_ALU_RGB_ADDR_21 +0x4718 US_ALU_RGB_ADDR_22 +0x471C US_ALU_RGB_ADDR_23 +0x4720 US_ALU_RGB_ADDR_24 +0x4724 US_ALU_RGB_ADDR_25 +0x4728 US_ALU_RGB_ADDR_26 +0x472C US_ALU_RGB_ADDR_27 +0x4730 US_ALU_RGB_ADDR_28 +0x4734 US_ALU_RGB_ADDR_29 +0x4738 US_ALU_RGB_ADDR_30 +0x473C US_ALU_RGB_ADDR_31 +0x4740 US_ALU_RGB_ADDR_32 +0x4744 US_ALU_RGB_ADDR_33 +0x4748 US_ALU_RGB_ADDR_34 +0x474C US_ALU_RGB_ADDR_35 +0x4750 US_ALU_RGB_ADDR_36 +0x4754 US_ALU_RGB_ADDR_37 +0x4758 US_ALU_RGB_ADDR_38 +0x475C US_ALU_RGB_ADDR_39 +0x4760 US_ALU_RGB_ADDR_40 +0x4764 US_ALU_RGB_ADDR_41 +0x4768 US_ALU_RGB_ADDR_42 +0x476C US_ALU_RGB_ADDR_43 +0x4770 US_ALU_RGB_ADDR_44 +0x4774 US_ALU_RGB_ADDR_45 +0x4778 US_ALU_RGB_ADDR_46 +0x477C US_ALU_RGB_ADDR_47 +0x4780 US_ALU_RGB_ADDR_48 +0x4784 US_ALU_RGB_ADDR_49 +0x4788 US_ALU_RGB_ADDR_50 +0x478C US_ALU_RGB_ADDR_51 +0x4790 US_ALU_RGB_ADDR_52 +0x4794 US_ALU_RGB_ADDR_53 +0x4798 US_ALU_RGB_ADDR_54 +0x479C US_ALU_RGB_ADDR_55 +0x47A0 US_ALU_RGB_ADDR_56 +0x47A4 US_ALU_RGB_ADDR_57 +0x47A8 US_ALU_RGB_ADDR_58 +0x47AC US_ALU_RGB_ADDR_59 +0x47B0 US_ALU_RGB_ADDR_60 +0x47B4 US_ALU_RGB_ADDR_61 +0x47B8 US_ALU_RGB_ADDR_62 +0x47BC US_ALU_RGB_ADDR_63 +0x47C0 US_ALU_ALPHA_ADDR_0 +0x47C4 US_ALU_ALPHA_ADDR_1 +0x47C8 US_ALU_ALPHA_ADDR_2 +0x47CC US_ALU_ALPHA_ADDR_3 +0x47D0 US_ALU_ALPHA_ADDR_4 +0x47D4 US_ALU_ALPHA_ADDR_5 +0x47D8 US_ALU_ALPHA_ADDR_6 +0x47DC US_ALU_ALPHA_ADDR_7 +0x47E0 US_ALU_ALPHA_ADDR_8 +0x47E4 US_ALU_ALPHA_ADDR_9 +0x47E8 US_ALU_ALPHA_ADDR_10 +0x47EC US_ALU_ALPHA_ADDR_11 +0x47F0 US_ALU_ALPHA_ADDR_12 +0x47F4 US_ALU_ALPHA_ADDR_13 +0x47F8 US_ALU_ALPHA_ADDR_14 +0x47FC US_ALU_ALPHA_ADDR_15 +0x4800 US_ALU_ALPHA_ADDR_16 +0x4804 US_ALU_ALPHA_ADDR_17 +0x4808 US_ALU_ALPHA_ADDR_18 +0x480C US_ALU_ALPHA_ADDR_19 +0x4810 US_ALU_ALPHA_ADDR_20 +0x4814 US_ALU_ALPHA_ADDR_21 +0x4818 US_ALU_ALPHA_ADDR_22 +0x481C US_ALU_ALPHA_ADDR_23 +0x4820 US_ALU_ALPHA_ADDR_24 +0x4824 US_ALU_ALPHA_ADDR_25 +0x4828 US_ALU_ALPHA_ADDR_26 +0x482C US_ALU_ALPHA_ADDR_27 +0x4830 US_ALU_ALPHA_ADDR_28 +0x4834 US_ALU_ALPHA_ADDR_29 +0x4838 US_ALU_ALPHA_ADDR_30 +0x483C US_ALU_ALPHA_ADDR_31 +0x4840 US_ALU_ALPHA_ADDR_32 +0x4844 US_ALU_ALPHA_ADDR_33 +0x4848 US_ALU_ALPHA_ADDR_34 +0x484C US_ALU_ALPHA_ADDR_35 +0x4850 US_ALU_ALPHA_ADDR_36 +0x4854 US_ALU_ALPHA_ADDR_37 +0x4858 US_ALU_ALPHA_ADDR_38 +0x485C US_ALU_ALPHA_ADDR_39 +0x4860 US_ALU_ALPHA_ADDR_40 +0x4864 US_ALU_ALPHA_ADDR_41 +0x4868 US_ALU_ALPHA_ADDR_42 +0x486C US_ALU_ALPHA_ADDR_43 +0x4870 US_ALU_ALPHA_ADDR_44 +0x4874 US_ALU_ALPHA_ADDR_45 +0x4878 US_ALU_ALPHA_ADDR_46 +0x487C US_ALU_ALPHA_ADDR_47 +0x4880 US_ALU_ALPHA_ADDR_48 +0x4884 US_ALU_ALPHA_ADDR_49 +0x4888 US_ALU_ALPHA_ADDR_50 +0x488C US_ALU_ALPHA_ADDR_51 +0x4890 US_ALU_ALPHA_ADDR_52 +0x4894 US_ALU_ALPHA_ADDR_53 +0x4898 US_ALU_ALPHA_ADDR_54 +0x489C US_ALU_ALPHA_ADDR_55 +0x48A0 US_ALU_ALPHA_ADDR_56 +0x48A4 US_ALU_ALPHA_ADDR_57 +0x48A8 US_ALU_ALPHA_ADDR_58 +0x48AC US_ALU_ALPHA_ADDR_59 +0x48B0 US_ALU_ALPHA_ADDR_60 +0x48B4 US_ALU_ALPHA_ADDR_61 +0x48B8 US_ALU_ALPHA_ADDR_62 +0x48BC US_ALU_ALPHA_ADDR_63 +0x48C0 US_ALU_RGB_INST_0 +0x48C4 US_ALU_RGB_INST_1 +0x48C8 US_ALU_RGB_INST_2 +0x48CC US_ALU_RGB_INST_3 +0x48D0 US_ALU_RGB_INST_4 +0x48D4 US_ALU_RGB_INST_5 +0x48D8 US_ALU_RGB_INST_6 +0x48DC US_ALU_RGB_INST_7 +0x48E0 US_ALU_RGB_INST_8 +0x48E4 US_ALU_RGB_INST_9 +0x48E8 US_ALU_RGB_INST_10 +0x48EC US_ALU_RGB_INST_11 +0x48F0 US_ALU_RGB_INST_12 +0x48F4 US_ALU_RGB_INST_13 +0x48F8 US_ALU_RGB_INST_14 +0x48FC US_ALU_RGB_INST_15 +0x4900 US_ALU_RGB_INST_16 +0x4904 US_ALU_RGB_INST_17 +0x4908 US_ALU_RGB_INST_18 +0x490C US_ALU_RGB_INST_19 +0x4910 US_ALU_RGB_INST_20 +0x4914 US_ALU_RGB_INST_21 +0x4918 US_ALU_RGB_INST_22 +0x491C US_ALU_RGB_INST_23 +0x4920 US_ALU_RGB_INST_24 +0x4924 US_ALU_RGB_INST_25 +0x4928 US_ALU_RGB_INST_26 +0x492C US_ALU_RGB_INST_27 +0x4930 US_ALU_RGB_INST_28 +0x4934 US_ALU_RGB_INST_29 +0x4938 US_ALU_RGB_INST_30 +0x493C US_ALU_RGB_INST_31 +0x4940 US_ALU_RGB_INST_32 +0x4944 US_ALU_RGB_INST_33 +0x4948 US_ALU_RGB_INST_34 +0x494C US_ALU_RGB_INST_35 +0x4950 US_ALU_RGB_INST_36 +0x4954 US_ALU_RGB_INST_37 +0x4958 US_ALU_RGB_INST_38 +0x495C US_ALU_RGB_INST_39 +0x4960 US_ALU_RGB_INST_40 +0x4964 US_ALU_RGB_INST_41 +0x4968 US_ALU_RGB_INST_42 +0x496C US_ALU_RGB_INST_43 +0x4970 US_ALU_RGB_INST_44 +0x4974 US_ALU_RGB_INST_45 +0x4978 US_ALU_RGB_INST_46 +0x497C US_ALU_RGB_INST_47 +0x4980 US_ALU_RGB_INST_48 +0x4984 US_ALU_RGB_INST_49 +0x4988 US_ALU_RGB_INST_50 +0x498C US_ALU_RGB_INST_51 +0x4990 US_ALU_RGB_INST_52 +0x4994 US_ALU_RGB_INST_53 +0x4998 US_ALU_RGB_INST_54 +0x499C US_ALU_RGB_INST_55 +0x49A0 US_ALU_RGB_INST_56 +0x49A4 US_ALU_RGB_INST_57 +0x49A8 US_ALU_RGB_INST_58 +0x49AC US_ALU_RGB_INST_59 +0x49B0 US_ALU_RGB_INST_60 +0x49B4 US_ALU_RGB_INST_61 +0x49B8 US_ALU_RGB_INST_62 +0x49BC US_ALU_RGB_INST_63 +0x49C0 US_ALU_ALPHA_INST_0 +0x49C4 US_ALU_ALPHA_INST_1 +0x49C8 US_ALU_ALPHA_INST_2 +0x49CC US_ALU_ALPHA_INST_3 +0x49D0 US_ALU_ALPHA_INST_4 +0x49D4 US_ALU_ALPHA_INST_5 +0x49D8 US_ALU_ALPHA_INST_6 +0x49DC US_ALU_ALPHA_INST_7 +0x49E0 US_ALU_ALPHA_INST_8 +0x49E4 US_ALU_ALPHA_INST_9 +0x49E8 US_ALU_ALPHA_INST_10 +0x49EC US_ALU_ALPHA_INST_11 +0x49F0 US_ALU_ALPHA_INST_12 +0x49F4 US_ALU_ALPHA_INST_13 +0x49F8 US_ALU_ALPHA_INST_14 +0x49FC US_ALU_ALPHA_INST_15 +0x4A00 US_ALU_ALPHA_INST_16 +0x4A04 US_ALU_ALPHA_INST_17 +0x4A08 US_ALU_ALPHA_INST_18 +0x4A0C US_ALU_ALPHA_INST_19 +0x4A10 US_ALU_ALPHA_INST_20 +0x4A14 US_ALU_ALPHA_INST_21 +0x4A18 US_ALU_ALPHA_INST_22 +0x4A1C US_ALU_ALPHA_INST_23 +0x4A20 US_ALU_ALPHA_INST_24 +0x4A24 US_ALU_ALPHA_INST_25 +0x4A28 US_ALU_ALPHA_INST_26 +0x4A2C US_ALU_ALPHA_INST_27 +0x4A30 US_ALU_ALPHA_INST_28 +0x4A34 US_ALU_ALPHA_INST_29 +0x4A38 US_ALU_ALPHA_INST_30 +0x4A3C US_ALU_ALPHA_INST_31 +0x4A40 US_ALU_ALPHA_INST_32 +0x4A44 US_ALU_ALPHA_INST_33 +0x4A48 US_ALU_ALPHA_INST_34 +0x4A4C US_ALU_ALPHA_INST_35 +0x4A50 US_ALU_ALPHA_INST_36 +0x4A54 US_ALU_ALPHA_INST_37 +0x4A58 US_ALU_ALPHA_INST_38 +0x4A5C US_ALU_ALPHA_INST_39 +0x4A60 US_ALU_ALPHA_INST_40 +0x4A64 US_ALU_ALPHA_INST_41 +0x4A68 US_ALU_ALPHA_INST_42 +0x4A6C US_ALU_ALPHA_INST_43 +0x4A70 US_ALU_ALPHA_INST_44 +0x4A74 US_ALU_ALPHA_INST_45 +0x4A78 US_ALU_ALPHA_INST_46 +0x4A7C US_ALU_ALPHA_INST_47 +0x4A80 US_ALU_ALPHA_INST_48 +0x4A84 US_ALU_ALPHA_INST_49 +0x4A88 US_ALU_ALPHA_INST_50 +0x4A8C US_ALU_ALPHA_INST_51 +0x4A90 US_ALU_ALPHA_INST_52 +0x4A94 US_ALU_ALPHA_INST_53 +0x4A98 US_ALU_ALPHA_INST_54 +0x4A9C US_ALU_ALPHA_INST_55 +0x4AA0 US_ALU_ALPHA_INST_56 +0x4AA4 US_ALU_ALPHA_INST_57 +0x4AA8 US_ALU_ALPHA_INST_58 +0x4AAC US_ALU_ALPHA_INST_59 +0x4AB0 US_ALU_ALPHA_INST_60 +0x4AB4 US_ALU_ALPHA_INST_61 +0x4AB8 US_ALU_ALPHA_INST_62 +0x4ABC US_ALU_ALPHA_INST_63 +0x4BC0 FG_FOG_BLEND +0x4BC4 FG_FOG_FACTOR +0x4BC8 FG_FOG_COLOR_R +0x4BCC FG_FOG_COLOR_G +0x4BD0 FG_FOG_COLOR_B +0x4BD4 FG_ALPHA_FUNC +0x4BD8 FG_DEPTH_SRC +0x4C00 US_ALU_CONST_R_0 +0x4C04 US_ALU_CONST_G_0 +0x4C08 US_ALU_CONST_B_0 +0x4C0C US_ALU_CONST_A_0 +0x4C10 US_ALU_CONST_R_1 +0x4C14 US_ALU_CONST_G_1 +0x4C18 US_ALU_CONST_B_1 +0x4C1C US_ALU_CONST_A_1 +0x4C20 US_ALU_CONST_R_2 +0x4C24 US_ALU_CONST_G_2 +0x4C28 US_ALU_CONST_B_2 +0x4C2C US_ALU_CONST_A_2 +0x4C30 US_ALU_CONST_R_3 +0x4C34 US_ALU_CONST_G_3 +0x4C38 US_ALU_CONST_B_3 +0x4C3C US_ALU_CONST_A_3 +0x4C40 US_ALU_CONST_R_4 +0x4C44 US_ALU_CONST_G_4 +0x4C48 US_ALU_CONST_B_4 +0x4C4C US_ALU_CONST_A_4 +0x4C50 US_ALU_CONST_R_5 +0x4C54 US_ALU_CONST_G_5 +0x4C58 US_ALU_CONST_B_5 +0x4C5C US_ALU_CONST_A_5 +0x4C60 US_ALU_CONST_R_6 +0x4C64 US_ALU_CONST_G_6 +0x4C68 US_ALU_CONST_B_6 +0x4C6C US_ALU_CONST_A_6 +0x4C70 US_ALU_CONST_R_7 +0x4C74 US_ALU_CONST_G_7 +0x4C78 US_ALU_CONST_B_7 +0x4C7C US_ALU_CONST_A_7 +0x4C80 US_ALU_CONST_R_8 +0x4C84 US_ALU_CONST_G_8 +0x4C88 US_ALU_CONST_B_8 +0x4C8C US_ALU_CONST_A_8 +0x4C90 US_ALU_CONST_R_9 +0x4C94 US_ALU_CONST_G_9 +0x4C98 US_ALU_CONST_B_9 +0x4C9C US_ALU_CONST_A_9 +0x4CA0 US_ALU_CONST_R_10 +0x4CA4 US_ALU_CONST_G_10 +0x4CA8 US_ALU_CONST_B_10 +0x4CAC US_ALU_CONST_A_10 +0x4CB0 US_ALU_CONST_R_11 +0x4CB4 US_ALU_CONST_G_11 +0x4CB8 US_ALU_CONST_B_11 +0x4CBC US_ALU_CONST_A_11 +0x4CC0 US_ALU_CONST_R_12 +0x4CC4 US_ALU_CONST_G_12 +0x4CC8 US_ALU_CONST_B_12 +0x4CCC US_ALU_CONST_A_12 +0x4CD0 US_ALU_CONST_R_13 +0x4CD4 US_ALU_CONST_G_13 +0x4CD8 US_ALU_CONST_B_13 +0x4CDC US_ALU_CONST_A_13 +0x4CE0 US_ALU_CONST_R_14 +0x4CE4 US_ALU_CONST_G_14 +0x4CE8 US_ALU_CONST_B_14 +0x4CEC US_ALU_CONST_A_14 +0x4CF0 US_ALU_CONST_R_15 +0x4CF4 US_ALU_CONST_G_15 +0x4CF8 US_ALU_CONST_B_15 +0x4CFC US_ALU_CONST_A_15 +0x4D00 US_ALU_CONST_R_16 +0x4D04 US_ALU_CONST_G_16 +0x4D08 US_ALU_CONST_B_16 +0x4D0C US_ALU_CONST_A_16 +0x4D10 US_ALU_CONST_R_17 +0x4D14 US_ALU_CONST_G_17 +0x4D18 US_ALU_CONST_B_17 +0x4D1C US_ALU_CONST_A_17 +0x4D20 US_ALU_CONST_R_18 +0x4D24 US_ALU_CONST_G_18 +0x4D28 US_ALU_CONST_B_18 +0x4D2C US_ALU_CONST_A_18 +0x4D30 US_ALU_CONST_R_19 +0x4D34 US_ALU_CONST_G_19 +0x4D38 US_ALU_CONST_B_19 +0x4D3C US_ALU_CONST_A_19 +0x4D40 US_ALU_CONST_R_20 +0x4D44 US_ALU_CONST_G_20 +0x4D48 US_ALU_CONST_B_20 +0x4D4C US_ALU_CONST_A_20 +0x4D50 US_ALU_CONST_R_21 +0x4D54 US_ALU_CONST_G_21 +0x4D58 US_ALU_CONST_B_21 +0x4D5C US_ALU_CONST_A_21 +0x4D60 US_ALU_CONST_R_22 +0x4D64 US_ALU_CONST_G_22 +0x4D68 US_ALU_CONST_B_22 +0x4D6C US_ALU_CONST_A_22 +0x4D70 US_ALU_CONST_R_23 +0x4D74 US_ALU_CONST_G_23 +0x4D78 US_ALU_CONST_B_23 +0x4D7C US_ALU_CONST_A_23 +0x4D80 US_ALU_CONST_R_24 +0x4D84 US_ALU_CONST_G_24 +0x4D88 US_ALU_CONST_B_24 +0x4D8C US_ALU_CONST_A_24 +0x4D90 US_ALU_CONST_R_25 +0x4D94 US_ALU_CONST_G_25 +0x4D98 US_ALU_CONST_B_25 +0x4D9C US_ALU_CONST_A_25 +0x4DA0 US_ALU_CONST_R_26 +0x4DA4 US_ALU_CONST_G_26 +0x4DA8 US_ALU_CONST_B_26 +0x4DAC US_ALU_CONST_A_26 +0x4DB0 US_ALU_CONST_R_27 +0x4DB4 US_ALU_CONST_G_27 +0x4DB8 US_ALU_CONST_B_27 +0x4DBC US_ALU_CONST_A_27 +0x4DC0 US_ALU_CONST_R_28 +0x4DC4 US_ALU_CONST_G_28 +0x4DC8 US_ALU_CONST_B_28 +0x4DCC US_ALU_CONST_A_28 +0x4DD0 US_ALU_CONST_R_29 +0x4DD4 US_ALU_CONST_G_29 +0x4DD8 US_ALU_CONST_B_29 +0x4DDC US_ALU_CONST_A_29 +0x4DE0 US_ALU_CONST_R_30 +0x4DE4 US_ALU_CONST_G_30 +0x4DE8 US_ALU_CONST_B_30 +0x4DEC US_ALU_CONST_A_30 +0x4DF0 US_ALU_CONST_R_31 +0x4DF4 US_ALU_CONST_G_31 +0x4DF8 US_ALU_CONST_B_31 +0x4DFC US_ALU_CONST_A_31 +0x4E04 RB3D_BLENDCNTL_R3 +0x4E08 RB3D_ABLENDCNTL_R3 +0x4E0C RB3D_COLOR_CHANNEL_MASK +0x4E10 RB3D_CONSTANT_COLOR +0x4E14 RB3D_COLOR_CLEAR_VALUE +0x4E18 RB3D_ROPCNTL_R3 +0x4E1C RB3D_CLRCMP_FLIPE_R3 +0x4E20 RB3D_CLRCMP_CLR_R3 +0x4E24 RB3D_CLRCMP_MSK_R3 +0x4E48 RB3D_DEBUG_CTL +0x4E4C RB3D_DSTCACHE_CTLSTAT_R3 +0x4E50 RB3D_DITHER_CTL +0x4E54 RB3D_CMASK_OFFSET0 +0x4E58 RB3D_CMASK_OFFSET1 +0x4E5C RB3D_CMASK_OFFSET2 +0x4E60 RB3D_CMASK_OFFSET3 +0x4E64 RB3D_CMASK_PITCH0 +0x4E68 RB3D_CMASK_PITCH1 +0x4E6C RB3D_CMASK_PITCH2 +0x4E70 RB3D_CMASK_PITCH3 +0x4E74 RB3D_CMASK_WRINDEX +0x4E78 RB3D_CMASK_DWORD +0x4E7C RB3D_CMASK_RDINDEX +0x4E80 RB3D_AARESOLVE_OFFSET +0x4E84 RB3D_AARESOLVE_PITCH +0x4E88 RB3D_AARESOLVE_CTL +0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD +0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD +0x4F04 ZB_ZSTENCILCNTL +0x4F08 ZB_STENCILREFMASK +0x4F14 ZB_ZTOP +0x4F18 ZB_ZCACHE_CTLSTAT +0x4F1C ZB_BW_CNTL +0x4F28 ZB_DEPTHCLEARVALUE +0x4F30 ZB_ZMASK_OFFSET +0x4F34 ZB_ZMASK_PITCH +0x4F38 ZB_ZMASK_WRINDEX +0x4F3C ZB_ZMASK_DWORD +0x4F40 ZB_ZMASK_RDINDEX +0x4F44 ZB_HIZ_OFFSET +0x4F48 ZB_HIZ_WRINDEX +0x4F4C ZB_HIZ_DWORD +0x4F50 ZB_HIZ_RDINDEX +0x4F54 ZB_HIZ_PITCH +0x4F58 ZB_ZPASS_DATA diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515 new file mode 100644 index 000000000000..0102a0d5735c --- /dev/null +++ b/drivers/gpu/drm/radeon/reg_srcs/rv515 @@ -0,0 +1,486 @@ +rv515 0x6d40 +0x1434 SRC_Y_X +0x1438 DST_Y_X +0x143C DST_HEIGHT_WIDTH +0x146C DP_GUI_MASTER_CNTL +0x1474 BRUSH_Y_X +0x1478 DP_BRUSH_BKGD_CLR +0x147C DP_BRUSH_FRGD_CLR +0x1480 BRUSH_DATA0 +0x1484 BRUSH_DATA1 +0x1598 DST_WIDTH_HEIGHT +0x15C0 CLR_CMP_CNTL +0x15C4 CLR_CMP_CLR_SRC +0x15C8 CLR_CMP_CLR_DST +0x15CC CLR_CMP_MSK +0x15D8 DP_SRC_FRGD_CLR +0x15DC DP_SRC_BKGD_CLR +0x1600 DST_LINE_START +0x1604 DST_LINE_END +0x1608 DST_LINE_PATCOUNT +0x16C0 DP_CNTL +0x16CC DP_WRITE_MSK +0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR +0x16E8 DEFAULT_SC_BOTTOM_RIGHT +0x16EC SC_TOP_LEFT +0x16F0 SC_BOTTOM_RIGHT +0x16F4 SRC_SC_BOTTOM_RIGHT +0x1714 DSTCACHE_CTLSTAT +0x1720 WAIT_UNTIL +0x172C RBBM_GUICNTL +0x1D98 VAP_VPORT_XSCALE +0x1D9C VAP_VPORT_XOFFSET +0x1DA0 VAP_VPORT_YSCALE +0x1DA4 VAP_VPORT_YOFFSET +0x1DA8 VAP_VPORT_ZSCALE +0x1DAC VAP_VPORT_ZOFFSET +0x2080 VAP_CNTL +0x2090 VAP_OUT_VTX_FMT_0 +0x2094 VAP_OUT_VTX_FMT_1 +0x20B0 VAP_VTE_CNTL +0x2138 VAP_VF_MIN_VTX_INDX +0x2140 VAP_CNTL_STATUS +0x2150 VAP_PROG_STREAM_CNTL_0 +0x2154 VAP_PROG_STREAM_CNTL_1 +0x2158 VAP_PROG_STREAM_CNTL_2 +0x215C VAP_PROG_STREAM_CNTL_3 +0x2160 VAP_PROG_STREAM_CNTL_4 +0x2164 VAP_PROG_STREAM_CNTL_5 +0x2168 VAP_PROG_STREAM_CNTL_6 +0x216C VAP_PROG_STREAM_CNTL_7 +0x2180 VAP_VTX_STATE_CNTL +0x2184 VAP_VSM_VTX_ASSM +0x2188 VAP_VTX_STATE_IND_REG_0 +0x218C VAP_VTX_STATE_IND_REG_1 +0x2190 VAP_VTX_STATE_IND_REG_2 +0x2194 VAP_VTX_STATE_IND_REG_3 +0x2198 VAP_VTX_STATE_IND_REG_4 +0x219C VAP_VTX_STATE_IND_REG_5 +0x21A0 VAP_VTX_STATE_IND_REG_6 +0x21A4 VAP_VTX_STATE_IND_REG_7 +0x21A8 VAP_VTX_STATE_IND_REG_8 +0x21AC VAP_VTX_STATE_IND_REG_9 +0x21B0 VAP_VTX_STATE_IND_REG_10 +0x21B4 VAP_VTX_STATE_IND_REG_11 +0x21B8 VAP_VTX_STATE_IND_REG_12 +0x21BC VAP_VTX_STATE_IND_REG_13 +0x21C0 VAP_VTX_STATE_IND_REG_14 +0x21C4 VAP_VTX_STATE_IND_REG_15 +0x21DC VAP_PSC_SGN_NORM_CNTL +0x21E0 VAP_PROG_STREAM_CNTL_EXT_0 +0x21E4 VAP_PROG_STREAM_CNTL_EXT_1 +0x21E8 VAP_PROG_STREAM_CNTL_EXT_2 +0x21EC VAP_PROG_STREAM_CNTL_EXT_3 +0x21F0 VAP_PROG_STREAM_CNTL_EXT_4 +0x21F4 VAP_PROG_STREAM_CNTL_EXT_5 +0x21F8 VAP_PROG_STREAM_CNTL_EXT_6 +0x21FC VAP_PROG_STREAM_CNTL_EXT_7 +0x2200 VAP_PVS_VECTOR_INDX_REG +0x2204 VAP_PVS_VECTOR_DATA_REG +0x2208 VAP_PVS_VECTOR_DATA_REG_128 +0x2218 VAP_TEX_TO_COLOR_CNTL +0x221C VAP_CLIP_CNTL +0x2220 VAP_GB_VERT_CLIP_ADJ +0x2224 VAP_GB_VERT_DISC_ADJ +0x2228 VAP_GB_HORZ_CLIP_ADJ +0x222C VAP_GB_HORZ_DISC_ADJ +0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0 +0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1 +0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2 +0x223C VAP_PVS_FLOW_CNTL_ADDRS_3 +0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4 +0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5 +0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6 +0x224C VAP_PVS_FLOW_CNTL_ADDRS_7 +0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8 +0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9 +0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10 +0x225C VAP_PVS_FLOW_CNTL_ADDRS_11 +0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12 +0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13 +0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14 +0x226C VAP_PVS_FLOW_CNTL_ADDRS_15 +0x2284 VAP_PVS_STATE_FLUSH_REG +0x2288 VAP_PVS_VTX_TIMEOUT_REG +0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0 +0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1 +0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2 +0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3 +0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4 +0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5 +0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6 +0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7 +0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8 +0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9 +0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10 +0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11 +0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12 +0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13 +0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14 +0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15 +0x22D0 VAP_PVS_CODE_CNTL_0 +0x22D4 VAP_PVS_CONST_CNTL +0x22D8 VAP_PVS_CODE_CNTL_1 +0x22DC VAP_PVS_FLOW_CNTL_OPC +0x2500 VAP_PVS_FLOW_CNTL_ADDRS_LW_0 +0x2504 VAP_PVS_FLOW_CNTL_ADDRS_UW_0 +0x2508 VAP_PVS_FLOW_CNTL_ADDRS_LW_1 +0x250C VAP_PVS_FLOW_CNTL_ADDRS_UW_1 +0x2510 VAP_PVS_FLOW_CNTL_ADDRS_LW_2 +0x2514 VAP_PVS_FLOW_CNTL_ADDRS_UW_2 +0x2518 VAP_PVS_FLOW_CNTL_ADDRS_LW_3 +0x251C VAP_PVS_FLOW_CNTL_ADDRS_UW_3 +0x2520 VAP_PVS_FLOW_CNTL_ADDRS_LW_4 +0x2524 VAP_PVS_FLOW_CNTL_ADDRS_UW_4 +0x2528 VAP_PVS_FLOW_CNTL_ADDRS_LW_5 +0x252C VAP_PVS_FLOW_CNTL_ADDRS_UW_5 +0x2530 VAP_PVS_FLOW_CNTL_ADDRS_LW_6 +0x2534 VAP_PVS_FLOW_CNTL_ADDRS_UW_6 +0x2538 VAP_PVS_FLOW_CNTL_ADDRS_LW_7 +0x253C VAP_PVS_FLOW_CNTL_ADDRS_UW_7 +0x2540 VAP_PVS_FLOW_CNTL_ADDRS_LW_8 +0x2544 VAP_PVS_FLOW_CNTL_ADDRS_UW_8 +0x2548 VAP_PVS_FLOW_CNTL_ADDRS_LW_9 +0x254C VAP_PVS_FLOW_CNTL_ADDRS_UW_9 +0x2550 VAP_PVS_FLOW_CNTL_ADDRS_LW_10 +0x2554 VAP_PVS_FLOW_CNTL_ADDRS_UW_10 +0x2558 VAP_PVS_FLOW_CNTL_ADDRS_LW_11 +0x255C VAP_PVS_FLOW_CNTL_ADDRS_UW_11 +0x2560 VAP_PVS_FLOW_CNTL_ADDRS_LW_12 +0x2564 VAP_PVS_FLOW_CNTL_ADDRS_UW_12 +0x2568 VAP_PVS_FLOW_CNTL_ADDRS_LW_13 +0x256C VAP_PVS_FLOW_CNTL_ADDRS_UW_13 +0x2570 VAP_PVS_FLOW_CNTL_ADDRS_LW_14 +0x2574 VAP_PVS_FLOW_CNTL_ADDRS_UW_14 +0x2578 VAP_PVS_FLOW_CNTL_ADDRS_LW_15 +0x257C VAP_PVS_FLOW_CNTL_ADDRS_UW_15 +0x342C RB2D_DSTCACHE_CTLSTAT +0x4000 GB_VAP_RASTER_VTX_FMT_0 +0x4004 GB_VAP_RASTER_VTX_FMT_1 +0x4008 GB_ENABLE +0x401C GB_SELECT +0x4020 GB_AA_CONFIG +0x4024 GB_FIFO_SIZE +0x4100 TX_INVALTAGS +0x4200 GA_POINT_S0 +0x4204 GA_POINT_T0 +0x4208 GA_POINT_S1 +0x420C GA_POINT_T1 +0x4214 GA_TRIANGLE_STIPPLE +0x421C GA_POINT_SIZE +0x4230 GA_POINT_MINMAX +0x4234 GA_LINE_CNTL +0x4238 GA_LINE_STIPPLE_CONFIG +0x4260 GA_LINE_STIPPLE_VALUE +0x4264 GA_LINE_S0 +0x4268 GA_LINE_S1 +0x4278 GA_COLOR_CONTROL +0x427C GA_SOLID_RG +0x4280 GA_SOLID_BA +0x4288 GA_POLY_MODE +0x428C GA_ROUND_MODE +0x4290 GA_OFFSET +0x4294 GA_FOG_SCALE +0x4298 GA_FOG_OFFSET +0x42A0 SU_TEX_WRAP +0x42A4 SU_POLY_OFFSET_FRONT_SCALE +0x42A8 SU_POLY_OFFSET_FRONT_OFFSET +0x42AC SU_POLY_OFFSET_BACK_SCALE +0x42B0 SU_POLY_OFFSET_BACK_OFFSET +0x42B4 SU_POLY_OFFSET_ENABLE +0x42B8 SU_CULL_MODE +0x42C0 SU_DEPTH_SCALE +0x42C4 SU_DEPTH_OFFSET +0x42C8 SU_REG_DEST +0x4300 RS_COUNT +0x4304 RS_INST_COUNT +0x4074 RS_IP_0 +0x4078 RS_IP_1 +0x407C RS_IP_2 +0x4080 RS_IP_3 +0x4084 RS_IP_4 +0x4088 RS_IP_5 +0x408C RS_IP_6 +0x4090 RS_IP_7 +0x4094 RS_IP_8 +0x4098 RS_IP_9 +0x409C RS_IP_10 +0x40A0 RS_IP_11 +0x40A4 RS_IP_12 +0x40A8 RS_IP_13 +0x40AC RS_IP_14 +0x40B0 RS_IP_15 +0x4320 RS_INST_0 +0x4324 RS_INST_1 +0x4328 RS_INST_2 +0x432C RS_INST_3 +0x4330 RS_INST_4 +0x4334 RS_INST_5 +0x4338 RS_INST_6 +0x433C RS_INST_7 +0x4340 RS_INST_8 +0x4344 RS_INST_9 +0x4348 RS_INST_10 +0x434C RS_INST_11 +0x4350 RS_INST_12 +0x4354 RS_INST_13 +0x4358 RS_INST_14 +0x435C RS_INST_15 +0x43A4 SC_HYPERZ_EN +0x43A8 SC_EDGERULE +0x43B0 SC_CLIP_0_A +0x43B4 SC_CLIP_0_B +0x43B8 SC_CLIP_1_A +0x43BC SC_CLIP_1_B +0x43C0 SC_CLIP_2_A +0x43C4 SC_CLIP_2_B +0x43C8 SC_CLIP_3_A +0x43CC SC_CLIP_3_B +0x43D0 SC_CLIP_RULE +0x43E0 SC_SCISSOR0 +0x43E8 SC_SCREENDOOR +0x4440 TX_FILTER1_0 +0x4444 TX_FILTER1_1 +0x4448 TX_FILTER1_2 +0x444C TX_FILTER1_3 +0x4450 TX_FILTER1_4 +0x4454 TX_FILTER1_5 +0x4458 TX_FILTER1_6 +0x445C TX_FILTER1_7 +0x4460 TX_FILTER1_8 +0x4464 TX_FILTER1_9 +0x4468 TX_FILTER1_10 +0x446C TX_FILTER1_11 +0x4470 TX_FILTER1_12 +0x4474 TX_FILTER1_13 +0x4478 TX_FILTER1_14 +0x447C TX_FILTER1_15 +0x4580 TX_CHROMA_KEY_0 +0x4584 TX_CHROMA_KEY_1 +0x4588 TX_CHROMA_KEY_2 +0x458C TX_CHROMA_KEY_3 +0x4590 TX_CHROMA_KEY_4 +0x4594 TX_CHROMA_KEY_5 +0x4598 TX_CHROMA_KEY_6 +0x459C TX_CHROMA_KEY_7 +0x45A0 TX_CHROMA_KEY_8 +0x45A4 TX_CHROMA_KEY_9 +0x45A8 TX_CHROMA_KEY_10 +0x45AC TX_CHROMA_KEY_11 +0x45B0 TX_CHROMA_KEY_12 +0x45B4 TX_CHROMA_KEY_13 +0x45B8 TX_CHROMA_KEY_14 +0x45BC TX_CHROMA_KEY_15 +0x45C0 TX_BORDER_COLOR_0 +0x45C4 TX_BORDER_COLOR_1 +0x45C8 TX_BORDER_COLOR_2 +0x45CC TX_BORDER_COLOR_3 +0x45D0 TX_BORDER_COLOR_4 +0x45D4 TX_BORDER_COLOR_5 +0x45D8 TX_BORDER_COLOR_6 +0x45DC TX_BORDER_COLOR_7 +0x45E0 TX_BORDER_COLOR_8 +0x45E4 TX_BORDER_COLOR_9 +0x45E8 TX_BORDER_COLOR_10 +0x45EC TX_BORDER_COLOR_11 +0x45F0 TX_BORDER_COLOR_12 +0x45F4 TX_BORDER_COLOR_13 +0x45F8 TX_BORDER_COLOR_14 +0x45FC TX_BORDER_COLOR_15 +0x4250 GA_US_VECTOR_INDEX +0x4254 GA_US_VECTOR_DATA +0x4600 US_CONFIG +0x4604 US_PIXSIZE +0x4620 US_FC_BOOL_CONST +0x4624 US_FC_CTRL +0x4630 US_CODE_ADDR +0x4634 US_CODE_RANGE +0x4638 US_CODE_OFFSET +0x46A4 US_OUT_FMT_0 +0x46A8 US_OUT_FMT_1 +0x46AC US_OUT_FMT_2 +0x46B0 US_OUT_FMT_3 +0x46B4 US_W_FMT +0x4BC0 FG_FOG_BLEND +0x4BC4 FG_FOG_FACTOR +0x4BC8 FG_FOG_COLOR_R +0x4BCC FG_FOG_COLOR_G +0x4BD0 FG_FOG_COLOR_B +0x4BD4 FG_ALPHA_FUNC +0x4BD8 FG_DEPTH_SRC +0x4C00 US_ALU_CONST_R_0 +0x4C04 US_ALU_CONST_G_0 +0x4C08 US_ALU_CONST_B_0 +0x4C0C US_ALU_CONST_A_0 +0x4C10 US_ALU_CONST_R_1 +0x4C14 US_ALU_CONST_G_1 +0x4C18 US_ALU_CONST_B_1 +0x4C1C US_ALU_CONST_A_1 +0x4C20 US_ALU_CONST_R_2 +0x4C24 US_ALU_CONST_G_2 +0x4C28 US_ALU_CONST_B_2 +0x4C2C US_ALU_CONST_A_2 +0x4C30 US_ALU_CONST_R_3 +0x4C34 US_ALU_CONST_G_3 +0x4C38 US_ALU_CONST_B_3 +0x4C3C US_ALU_CONST_A_3 +0x4C40 US_ALU_CONST_R_4 +0x4C44 US_ALU_CONST_G_4 +0x4C48 US_ALU_CONST_B_4 +0x4C4C US_ALU_CONST_A_4 +0x4C50 US_ALU_CONST_R_5 +0x4C54 US_ALU_CONST_G_5 +0x4C58 US_ALU_CONST_B_5 +0x4C5C US_ALU_CONST_A_5 +0x4C60 US_ALU_CONST_R_6 +0x4C64 US_ALU_CONST_G_6 +0x4C68 US_ALU_CONST_B_6 +0x4C6C US_ALU_CONST_A_6 +0x4C70 US_ALU_CONST_R_7 +0x4C74 US_ALU_CONST_G_7 +0x4C78 US_ALU_CONST_B_7 +0x4C7C US_ALU_CONST_A_7 +0x4C80 US_ALU_CONST_R_8 +0x4C84 US_ALU_CONST_G_8 +0x4C88 US_ALU_CONST_B_8 +0x4C8C US_ALU_CONST_A_8 +0x4C90 US_ALU_CONST_R_9 +0x4C94 US_ALU_CONST_G_9 +0x4C98 US_ALU_CONST_B_9 +0x4C9C US_ALU_CONST_A_9 +0x4CA0 US_ALU_CONST_R_10 +0x4CA4 US_ALU_CONST_G_10 +0x4CA8 US_ALU_CONST_B_10 +0x4CAC US_ALU_CONST_A_10 +0x4CB0 US_ALU_CONST_R_11 +0x4CB4 US_ALU_CONST_G_11 +0x4CB8 US_ALU_CONST_B_11 +0x4CBC US_ALU_CONST_A_11 +0x4CC0 US_ALU_CONST_R_12 +0x4CC4 US_ALU_CONST_G_12 +0x4CC8 US_ALU_CONST_B_12 +0x4CCC US_ALU_CONST_A_12 +0x4CD0 US_ALU_CONST_R_13 +0x4CD4 US_ALU_CONST_G_13 +0x4CD8 US_ALU_CONST_B_13 +0x4CDC US_ALU_CONST_A_13 +0x4CE0 US_ALU_CONST_R_14 +0x4CE4 US_ALU_CONST_G_14 +0x4CE8 US_ALU_CONST_B_14 +0x4CEC US_ALU_CONST_A_14 +0x4CF0 US_ALU_CONST_R_15 +0x4CF4 US_ALU_CONST_G_15 +0x4CF8 US_ALU_CONST_B_15 +0x4CFC US_ALU_CONST_A_15 +0x4D00 US_ALU_CONST_R_16 +0x4D04 US_ALU_CONST_G_16 +0x4D08 US_ALU_CONST_B_16 +0x4D0C US_ALU_CONST_A_16 +0x4D10 US_ALU_CONST_R_17 +0x4D14 US_ALU_CONST_G_17 +0x4D18 US_ALU_CONST_B_17 +0x4D1C US_ALU_CONST_A_17 +0x4D20 US_ALU_CONST_R_18 +0x4D24 US_ALU_CONST_G_18 +0x4D28 US_ALU_CONST_B_18 +0x4D2C US_ALU_CONST_A_18 +0x4D30 US_ALU_CONST_R_19 +0x4D34 US_ALU_CONST_G_19 +0x4D38 US_ALU_CONST_B_19 +0x4D3C US_ALU_CONST_A_19 +0x4D40 US_ALU_CONST_R_20 +0x4D44 US_ALU_CONST_G_20 +0x4D48 US_ALU_CONST_B_20 +0x4D4C US_ALU_CONST_A_20 +0x4D50 US_ALU_CONST_R_21 +0x4D54 US_ALU_CONST_G_21 +0x4D58 US_ALU_CONST_B_21 +0x4D5C US_ALU_CONST_A_21 +0x4D60 US_ALU_CONST_R_22 +0x4D64 US_ALU_CONST_G_22 +0x4D68 US_ALU_CONST_B_22 +0x4D6C US_ALU_CONST_A_22 +0x4D70 US_ALU_CONST_R_23 +0x4D74 US_ALU_CONST_G_23 +0x4D78 US_ALU_CONST_B_23 +0x4D7C US_ALU_CONST_A_23 +0x4D80 US_ALU_CONST_R_24 +0x4D84 US_ALU_CONST_G_24 +0x4D88 US_ALU_CONST_B_24 +0x4D8C US_ALU_CONST_A_24 +0x4D90 US_ALU_CONST_R_25 +0x4D94 US_ALU_CONST_G_25 +0x4D98 US_ALU_CONST_B_25 +0x4D9C US_ALU_CONST_A_25 +0x4DA0 US_ALU_CONST_R_26 +0x4DA4 US_ALU_CONST_G_26 +0x4DA8 US_ALU_CONST_B_26 +0x4DAC US_ALU_CONST_A_26 +0x4DB0 US_ALU_CONST_R_27 +0x4DB4 US_ALU_CONST_G_27 +0x4DB8 US_ALU_CONST_B_27 +0x4DBC US_ALU_CONST_A_27 +0x4DC0 US_ALU_CONST_R_28 +0x4DC4 US_ALU_CONST_G_28 +0x4DC8 US_ALU_CONST_B_28 +0x4DCC US_ALU_CONST_A_28 +0x4DD0 US_ALU_CONST_R_29 +0x4DD4 US_ALU_CONST_G_29 +0x4DD8 US_ALU_CONST_B_29 +0x4DDC US_ALU_CONST_A_29 +0x4DE0 US_ALU_CONST_R_30 +0x4DE4 US_ALU_CONST_G_30 +0x4DE8 US_ALU_CONST_B_30 +0x4DEC US_ALU_CONST_A_30 +0x4DF0 US_ALU_CONST_R_31 +0x4DF4 US_ALU_CONST_G_31 +0x4DF8 US_ALU_CONST_B_31 +0x4DFC US_ALU_CONST_A_31 +0x4E04 RB3D_BLENDCNTL_R3 +0x4E08 RB3D_ABLENDCNTL_R3 +0x4E0C RB3D_COLOR_CHANNEL_MASK +0x4E10 RB3D_CONSTANT_COLOR +0x4E14 RB3D_COLOR_CLEAR_VALUE +0x4E18 RB3D_ROPCNTL_R3 +0x4E1C RB3D_CLRCMP_FLIPE_R3 +0x4E20 RB3D_CLRCMP_CLR_R3 +0x4E24 RB3D_CLRCMP_MSK_R3 +0x4E48 RB3D_DEBUG_CTL +0x4E4C RB3D_DSTCACHE_CTLSTAT_R3 +0x4E50 RB3D_DITHER_CTL +0x4E54 RB3D_CMASK_OFFSET0 +0x4E58 RB3D_CMASK_OFFSET1 +0x4E5C RB3D_CMASK_OFFSET2 +0x4E60 RB3D_CMASK_OFFSET3 +0x4E64 RB3D_CMASK_PITCH0 +0x4E68 RB3D_CMASK_PITCH1 +0x4E6C RB3D_CMASK_PITCH2 +0x4E70 RB3D_CMASK_PITCH3 +0x4E74 RB3D_CMASK_WRINDEX +0x4E78 RB3D_CMASK_DWORD +0x4E7C RB3D_CMASK_RDINDEX +0x4E80 RB3D_AARESOLVE_OFFSET +0x4E84 RB3D_AARESOLVE_PITCH +0x4E88 RB3D_AARESOLVE_CTL +0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD +0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD +0x4EF8 RB3D_CONSTANT_COLOR_AR +0x4EFC RB3D_CONSTANT_COLOR_GB +0x4F04 ZB_ZSTENCILCNTL +0x4F08 ZB_STENCILREFMASK +0x4F14 ZB_ZTOP +0x4F18 ZB_ZCACHE_CTLSTAT +0x4F1C ZB_BW_CNTL +0x4F28 ZB_DEPTHCLEARVALUE +0x4F30 ZB_ZMASK_OFFSET +0x4F34 ZB_ZMASK_PITCH +0x4F38 ZB_ZMASK_WRINDEX +0x4F3C ZB_ZMASK_DWORD +0x4F40 ZB_ZMASK_RDINDEX +0x4F44 ZB_HIZ_OFFSET +0x4F48 ZB_HIZ_WRINDEX +0x4F4C ZB_HIZ_DWORD +0x4F50 ZB_HIZ_RDINDEX +0x4F54 ZB_HIZ_PITCH +0x4F58 ZB_ZPASS_DATA +0x4FD4 ZB_STENCILREFMASK_BF diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c index b29affd9c5d8..a3fbdad938c7 100644 --- a/drivers/gpu/drm/radeon/rs400.c +++ b/drivers/gpu/drm/radeon/rs400.c @@ -29,7 +29,6 @@ #include #include "radeon_reg.h" #include "radeon.h" -#include "radeon_share.h" /* rs400,rs480 depends on : */ void r100_hdp_reset(struct radeon_device *rdev); @@ -63,7 +62,7 @@ void rs400_gart_adjust_size(struct radeon_device *rdev) break; default: DRM_ERROR("Unable to use IGP GART size %uM\n", - rdev->mc.gtt_size >> 20); + (unsigned)(rdev->mc.gtt_size >> 20)); DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); DRM_ERROR("Forcing to 32M GART size\n"); rdev->mc.gtt_size = 32 * 1024 * 1024; @@ -93,20 +92,41 @@ void rs400_gart_tlb_flush(struct radeon_device *rdev) WREG32_MC(RS480_GART_CACHE_CNTRL, 0); } -int rs400_gart_enable(struct radeon_device *rdev) +int rs400_gart_init(struct radeon_device *rdev) { - uint32_t size_reg; - uint32_t tmp; int r; + if (rdev->gart.table.ram.ptr) { + WARN(1, "RS400 GART already initialized.\n"); + return 0; + } + /* Check gart size */ + switch(rdev->mc.gtt_size / (1024 * 1024)) { + case 32: + case 64: + case 128: + case 256: + case 512: + case 1024: + case 2048: + break; + default: + return -EINVAL; + } /* Initialize common gart structure */ r = radeon_gart_init(rdev); - if (r) { + if (r) return r; - } - if (rs400_debugfs_pcie_gart_info_init(rdev)) { + if (rs400_debugfs_pcie_gart_info_init(rdev)) DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); - } + rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; + return radeon_gart_table_ram_alloc(rdev); +} + +int rs400_gart_enable(struct radeon_device *rdev) +{ + uint32_t size_reg; + uint32_t tmp; tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; @@ -137,13 +157,6 @@ int rs400_gart_enable(struct radeon_device *rdev) default: return -EINVAL; } - if (rdev->gart.table.ram.ptr == NULL) { - rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; - r = radeon_gart_table_ram_alloc(rdev); - if (r) { - return r; - } - } /* It should be fine to program it to max value */ if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); @@ -202,6 +215,13 @@ void rs400_gart_disable(struct radeon_device *rdev) WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); } +void rs400_gart_fini(struct radeon_device *rdev) +{ + rs400_gart_disable(rdev); + radeon_gart_table_ram_free(rdev); + radeon_gart_fini(rdev); +} + int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) { uint32_t entry; @@ -256,14 +276,12 @@ int rs400_mc_init(struct radeon_device *rdev) (void)RREG32(RADEON_HOST_PATH_CNTL); WREG32(RADEON_HOST_PATH_CNTL, tmp); (void)RREG32(RADEON_HOST_PATH_CNTL); + return 0; } void rs400_mc_fini(struct radeon_device *rdev) { - rs400_gart_disable(rdev); - radeon_gart_table_ram_free(rdev); - radeon_gart_fini(rdev); } diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index 02fd11aad6a2..0e791e26def3 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c @@ -28,6 +28,9 @@ #include "drmP.h" #include "radeon_reg.h" #include "radeon.h" +#include "avivod.h" + +#include "rs600_reg_safe.h" /* rs600 depends on : */ void r100_hdp_reset(struct radeon_device *rdev); @@ -66,22 +69,35 @@ void rs600_gart_tlb_flush(struct radeon_device *rdev) tmp = RREG32_MC(RS600_MC_PT0_CNTL); } -int rs600_gart_enable(struct radeon_device *rdev) +int rs600_gart_init(struct radeon_device *rdev) { - uint32_t tmp; - int i; int r; + if (rdev->gart.table.vram.robj) { + WARN(1, "RS600 GART already initialized.\n"); + return 0; + } /* Initialize common gart structure */ r = radeon_gart_init(rdev); if (r) { return r; } rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; - r = radeon_gart_table_vram_alloc(rdev); - if (r) { - return r; + return radeon_gart_table_vram_alloc(rdev); +} + +int rs600_gart_enable(struct radeon_device *rdev) +{ + uint32_t tmp; + int r, i; + + if (rdev->gart.table.vram.robj == NULL) { + dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); + return -EINVAL; } + r = radeon_gart_table_vram_pin(rdev); + if (r) + return r; /* FIXME: setup default page */ WREG32_MC(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) | @@ -136,8 +152,17 @@ void rs600_gart_disable(struct radeon_device *rdev) tmp = RREG32_MC(RS600_MC_CNTL1); tmp &= ~RS600_ENABLE_PAGE_TABLES; WREG32_MC(RS600_MC_CNTL1, tmp); - radeon_object_kunmap(rdev->gart.table.vram.robj); - radeon_object_unpin(rdev->gart.table.vram.robj); + if (rdev->gart.table.vram.robj) { + radeon_object_kunmap(rdev->gart.table.vram.robj); + radeon_object_unpin(rdev->gart.table.vram.robj); + } +} + +void rs600_gart_fini(struct radeon_device *rdev) +{ + rs600_gart_disable(rdev); + radeon_gart_table_vram_free(rdev); + radeon_gart_fini(rdev); } #define R600_PTE_VALID (1 << 0) @@ -173,6 +198,8 @@ void rs600_mc_disable_clients(struct radeon_device *rdev) "programming pipes. Bad things might happen.\n"); } + radeon_avivo_vga_render_disable(rdev); + tmp = RREG32(AVIVO_D1VGA_CONTROL); WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); tmp = RREG32(AVIVO_D2VGA_CONTROL); @@ -233,9 +260,6 @@ int rs600_mc_init(struct radeon_device *rdev) void rs600_mc_fini(struct radeon_device *rdev) { - rs600_gart_disable(rdev); - radeon_gart_table_vram_free(rdev); - radeon_gart_fini(rdev); } @@ -251,11 +275,9 @@ int rs600_irq_set(struct radeon_device *rdev) tmp |= RADEON_SW_INT_ENABLE; } if (rdev->irq.crtc_vblank_int[0]) { - tmp |= AVIVO_DISPLAY_INT_STATUS; mode_int |= AVIVO_D1MODE_INT_MASK; } if (rdev->irq.crtc_vblank_int[1]) { - tmp |= AVIVO_DISPLAY_INT_STATUS; mode_int |= AVIVO_D2MODE_INT_MASK; } WREG32(RADEON_GEN_INT_CNTL, tmp); @@ -410,64 +432,6 @@ void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) WREG32(RS600_MC_DATA, v); } -static const unsigned rs600_reg_safe_bm[219] = { - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF, - 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000, - 0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFF, - 0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF, - 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, - 0x00000000, 0x0000C100, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x0003FC01, 0xFFFFFCF8, 0xFF800B19, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, -}; - int rs600_init(struct radeon_device *rdev) { rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c index 879882533e45..0f585ca8276d 100644 --- a/drivers/gpu/drm/radeon/rs690.c +++ b/drivers/gpu/drm/radeon/rs690.c @@ -94,9 +94,6 @@ int rs690_mc_init(struct radeon_device *rdev) void rs690_mc_fini(struct radeon_device *rdev) { - rs400_gart_disable(rdev); - radeon_gart_table_ram_free(rdev); - radeon_gart_fini(rdev); } @@ -652,4 +649,3 @@ void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) WREG32(RS690_MC_DATA, v); WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); } - diff --git a/drivers/gpu/drm/radeon/rs780.c b/drivers/gpu/drm/radeon/rs780.c deleted file mode 100644 index 0affcff81825..000000000000 --- a/drivers/gpu/drm/radeon/rs780.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright 2008 Advanced Micro Devices, Inc. - * Copyright 2008 Red Hat Inc. - * Copyright 2009 Jerome Glisse. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Dave Airlie - * Alex Deucher - * Jerome Glisse - */ -#include "drmP.h" -#include "radeon_reg.h" -#include "radeon.h" - -/* rs780 depends on : */ -void rs600_mc_disable_clients(struct radeon_device *rdev); - -/* This files gather functions specifics to: - * rs780 - * - * Some of these functions might be used by newer ASICs. - */ -int rs780_mc_wait_for_idle(struct radeon_device *rdev); -void rs780_gpu_init(struct radeon_device *rdev); - - -/* - * MC - */ -int rs780_mc_init(struct radeon_device *rdev) -{ - rs780_gpu_init(rdev); - /* FIXME: implement */ - - rs600_mc_disable_clients(rdev); - if (rs780_mc_wait_for_idle(rdev)) { - printk(KERN_WARNING "Failed to wait MC idle while " - "programming pipes. Bad things might happen.\n"); - } - return 0; -} - -void rs780_mc_fini(struct radeon_device *rdev) -{ - /* FIXME: implement */ -} - - -/* - * Global GPU functions - */ -void rs780_errata(struct radeon_device *rdev) -{ - rdev->pll_errata = 0; -} - -int rs780_mc_wait_for_idle(struct radeon_device *rdev) -{ - /* FIXME: implement */ - return 0; -} - -void rs780_gpu_init(struct radeon_device *rdev) -{ - /* FIXME: implement */ -} - - -/* - * VRAM info - */ -void rs780_vram_get_type(struct radeon_device *rdev) -{ - /* FIXME: implement */ -} - -void rs780_vram_info(struct radeon_device *rdev) -{ - rs780_vram_get_type(rdev); - - /* FIXME: implement */ - /* Could aper size report 0 ? */ - rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); - rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); -} diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index 0566fb67e460..fd799748e7d8 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c @@ -27,18 +27,16 @@ */ #include #include "drmP.h" -#include "rv515r.h" +#include "rv515d.h" #include "radeon.h" -#include "radeon_share.h" +#include "rv515_reg_safe.h" /* rv515 depends on : */ void r100_hdp_reset(struct radeon_device *rdev); int r100_cp_reset(struct radeon_device *rdev); int r100_rb2d_reset(struct radeon_device *rdev); int r100_gui_wait_for_idle(struct radeon_device *rdev); int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); -int rv370_pcie_gart_enable(struct radeon_device *rdev); -void rv370_pcie_gart_disable(struct radeon_device *rdev); void r420_pipes_init(struct radeon_device *rdev); void rs600_mc_disable_clients(struct radeon_device *rdev); void rs600_disable_vga(struct radeon_device *rdev); @@ -126,9 +124,6 @@ int rv515_mc_init(struct radeon_device *rdev) void rv515_mc_fini(struct radeon_device *rdev) { - rv370_pcie_gart_disable(rdev); - radeon_gart_table_vram_free(rdev); - radeon_gart_fini(rdev); } @@ -464,301 +459,244 @@ int rv515_debugfs_ga_info_init(struct radeon_device *rdev) #endif } - /* * Asic initialization */ -static const unsigned r500_reg_safe_bm[219] = { - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF, - 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000, - 0xF0000038, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0x1FFFFC78, 0xFFFFE000, 0xFFFFFFFE, 0xFFFFFFFF, - 0x38CF8F50, 0xFFF88082, 0xFF0000FC, 0xFAE009FF, - 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, - 0xFFFF8CFC, 0xFFFFC1FF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x0003FC01, 0x3FFFFCF8, 0xFF800B19, 0xFFDFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, -}; - int rv515_init(struct radeon_device *rdev) { - rdev->config.r300.reg_safe_bm = r500_reg_safe_bm; - rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r500_reg_safe_bm); + rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; + rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); return 0; } -void atom_rv515_force_tv_scaler(struct radeon_device *rdev) +void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) { - - WREG32(0x659C, 0x0); - WREG32(0x6594, 0x705); - WREG32(0x65A4, 0x10001); - WREG32(0x65D8, 0x0); - WREG32(0x65B0, 0x0); - WREG32(0x65C0, 0x0); - WREG32(0x65D4, 0x0); - WREG32(0x6578, 0x0); - WREG32(0x657C, 0x841880A8); - WREG32(0x6578, 0x1); - WREG32(0x657C, 0x84208680); - WREG32(0x6578, 0x2); - WREG32(0x657C, 0xBFF880B0); - WREG32(0x6578, 0x100); - WREG32(0x657C, 0x83D88088); - WREG32(0x6578, 0x101); - WREG32(0x657C, 0x84608680); - WREG32(0x6578, 0x102); - WREG32(0x657C, 0xBFF080D0); - WREG32(0x6578, 0x200); - WREG32(0x657C, 0x83988068); - WREG32(0x6578, 0x201); - WREG32(0x657C, 0x84A08680); - WREG32(0x6578, 0x202); - WREG32(0x657C, 0xBFF080F8); - WREG32(0x6578, 0x300); - WREG32(0x657C, 0x83588058); - WREG32(0x6578, 0x301); - WREG32(0x657C, 0x84E08660); - WREG32(0x6578, 0x302); - WREG32(0x657C, 0xBFF88120); - WREG32(0x6578, 0x400); - WREG32(0x657C, 0x83188040); - WREG32(0x6578, 0x401); - WREG32(0x657C, 0x85008660); - WREG32(0x6578, 0x402); - WREG32(0x657C, 0xBFF88150); - WREG32(0x6578, 0x500); - WREG32(0x657C, 0x82D88030); - WREG32(0x6578, 0x501); - WREG32(0x657C, 0x85408640); - WREG32(0x6578, 0x502); - WREG32(0x657C, 0xBFF88180); - WREG32(0x6578, 0x600); - WREG32(0x657C, 0x82A08018); - WREG32(0x6578, 0x601); - WREG32(0x657C, 0x85808620); - WREG32(0x6578, 0x602); - WREG32(0x657C, 0xBFF081B8); - WREG32(0x6578, 0x700); - WREG32(0x657C, 0x82608010); - WREG32(0x6578, 0x701); - WREG32(0x657C, 0x85A08600); - WREG32(0x6578, 0x702); - WREG32(0x657C, 0x800081F0); - WREG32(0x6578, 0x800); - WREG32(0x657C, 0x8228BFF8); - WREG32(0x6578, 0x801); - WREG32(0x657C, 0x85E085E0); - WREG32(0x6578, 0x802); - WREG32(0x657C, 0xBFF88228); - WREG32(0x6578, 0x10000); - WREG32(0x657C, 0x82A8BF00); - WREG32(0x6578, 0x10001); - WREG32(0x657C, 0x82A08CC0); - WREG32(0x6578, 0x10002); - WREG32(0x657C, 0x8008BEF8); - WREG32(0x6578, 0x10100); - WREG32(0x657C, 0x81F0BF28); - WREG32(0x6578, 0x10101); - WREG32(0x657C, 0x83608CA0); - WREG32(0x6578, 0x10102); - WREG32(0x657C, 0x8018BED0); - WREG32(0x6578, 0x10200); - WREG32(0x657C, 0x8148BF38); - WREG32(0x6578, 0x10201); - WREG32(0x657C, 0x84408C80); - WREG32(0x6578, 0x10202); - WREG32(0x657C, 0x8008BEB8); - WREG32(0x6578, 0x10300); - WREG32(0x657C, 0x80B0BF78); - WREG32(0x6578, 0x10301); - WREG32(0x657C, 0x85008C20); - WREG32(0x6578, 0x10302); - WREG32(0x657C, 0x8020BEA0); - WREG32(0x6578, 0x10400); - WREG32(0x657C, 0x8028BF90); - WREG32(0x6578, 0x10401); - WREG32(0x657C, 0x85E08BC0); - WREG32(0x6578, 0x10402); - WREG32(0x657C, 0x8018BE90); - WREG32(0x6578, 0x10500); - WREG32(0x657C, 0xBFB8BFB0); - WREG32(0x6578, 0x10501); - WREG32(0x657C, 0x86C08B40); - WREG32(0x6578, 0x10502); - WREG32(0x657C, 0x8010BE90); - WREG32(0x6578, 0x10600); - WREG32(0x657C, 0xBF58BFC8); - WREG32(0x6578, 0x10601); - WREG32(0x657C, 0x87A08AA0); - WREG32(0x6578, 0x10602); - WREG32(0x657C, 0x8010BE98); - WREG32(0x6578, 0x10700); - WREG32(0x657C, 0xBF10BFF0); - WREG32(0x6578, 0x10701); - WREG32(0x657C, 0x886089E0); - WREG32(0x6578, 0x10702); - WREG32(0x657C, 0x8018BEB0); - WREG32(0x6578, 0x10800); - WREG32(0x657C, 0xBED8BFE8); - WREG32(0x6578, 0x10801); - WREG32(0x657C, 0x89408940); - WREG32(0x6578, 0x10802); - WREG32(0x657C, 0xBFE8BED8); - WREG32(0x6578, 0x20000); - WREG32(0x657C, 0x80008000); - WREG32(0x6578, 0x20001); - WREG32(0x657C, 0x90008000); - WREG32(0x6578, 0x20002); - WREG32(0x657C, 0x80008000); - WREG32(0x6578, 0x20003); - WREG32(0x657C, 0x80008000); - WREG32(0x6578, 0x20100); - WREG32(0x657C, 0x80108000); - WREG32(0x6578, 0x20101); - WREG32(0x657C, 0x8FE0BF70); - WREG32(0x6578, 0x20102); - WREG32(0x657C, 0xBFE880C0); - WREG32(0x6578, 0x20103); - WREG32(0x657C, 0x80008000); - WREG32(0x6578, 0x20200); - WREG32(0x657C, 0x8018BFF8); - WREG32(0x6578, 0x20201); - WREG32(0x657C, 0x8F80BF08); - WREG32(0x6578, 0x20202); - WREG32(0x657C, 0xBFD081A0); - WREG32(0x6578, 0x20203); - WREG32(0x657C, 0xBFF88000); - WREG32(0x6578, 0x20300); - WREG32(0x657C, 0x80188000); - WREG32(0x6578, 0x20301); - WREG32(0x657C, 0x8EE0BEC0); - WREG32(0x6578, 0x20302); - WREG32(0x657C, 0xBFB082A0); - WREG32(0x6578, 0x20303); - WREG32(0x657C, 0x80008000); - WREG32(0x6578, 0x20400); - WREG32(0x657C, 0x80188000); - WREG32(0x6578, 0x20401); - WREG32(0x657C, 0x8E00BEA0); - WREG32(0x6578, 0x20402); - WREG32(0x657C, 0xBF8883C0); - WREG32(0x6578, 0x20403); - WREG32(0x657C, 0x80008000); - WREG32(0x6578, 0x20500); - WREG32(0x657C, 0x80188000); - WREG32(0x6578, 0x20501); - WREG32(0x657C, 0x8D00BE90); - WREG32(0x6578, 0x20502); - WREG32(0x657C, 0xBF588500); - WREG32(0x6578, 0x20503); - WREG32(0x657C, 0x80008008); - WREG32(0x6578, 0x20600); - WREG32(0x657C, 0x80188000); - WREG32(0x6578, 0x20601); - WREG32(0x657C, 0x8BC0BE98); - WREG32(0x6578, 0x20602); - WREG32(0x657C, 0xBF308660); - WREG32(0x6578, 0x20603); - WREG32(0x657C, 0x80008008); - WREG32(0x6578, 0x20700); - WREG32(0x657C, 0x80108000); - WREG32(0x6578, 0x20701); - WREG32(0x657C, 0x8A80BEB0); - WREG32(0x6578, 0x20702); - WREG32(0x657C, 0xBF0087C0); - WREG32(0x6578, 0x20703); - WREG32(0x657C, 0x80008008); - WREG32(0x6578, 0x20800); - WREG32(0x657C, 0x80108000); - WREG32(0x6578, 0x20801); - WREG32(0x657C, 0x8920BED0); - WREG32(0x6578, 0x20802); - WREG32(0x657C, 0xBED08920); - WREG32(0x6578, 0x20803); - WREG32(0x657C, 0x80008010); - WREG32(0x6578, 0x30000); - WREG32(0x657C, 0x90008000); - WREG32(0x6578, 0x30001); - WREG32(0x657C, 0x80008000); - WREG32(0x6578, 0x30100); - WREG32(0x657C, 0x8FE0BF90); - WREG32(0x6578, 0x30101); - WREG32(0x657C, 0xBFF880A0); - WREG32(0x6578, 0x30200); - WREG32(0x657C, 0x8F60BF40); - WREG32(0x6578, 0x30201); - WREG32(0x657C, 0xBFE88180); - WREG32(0x6578, 0x30300); - WREG32(0x657C, 0x8EC0BF00); - WREG32(0x6578, 0x30301); - WREG32(0x657C, 0xBFC88280); - WREG32(0x6578, 0x30400); - WREG32(0x657C, 0x8DE0BEE0); - WREG32(0x6578, 0x30401); - WREG32(0x657C, 0xBFA083A0); - WREG32(0x6578, 0x30500); - WREG32(0x657C, 0x8CE0BED0); - WREG32(0x6578, 0x30501); - WREG32(0x657C, 0xBF7884E0); - WREG32(0x6578, 0x30600); - WREG32(0x657C, 0x8BA0BED8); - WREG32(0x6578, 0x30601); - WREG32(0x657C, 0xBF508640); - WREG32(0x6578, 0x30700); - WREG32(0x657C, 0x8A60BEE8); - WREG32(0x6578, 0x30701); - WREG32(0x657C, 0xBF2087A0); - WREG32(0x6578, 0x30800); - WREG32(0x657C, 0x8900BF00); - WREG32(0x6578, 0x30801); - WREG32(0x657C, 0xBF008900); + int index_reg = 0x6578 + crtc->crtc_offset; + int data_reg = 0x657c + crtc->crtc_offset; + + WREG32(0x659C + crtc->crtc_offset, 0x0); + WREG32(0x6594 + crtc->crtc_offset, 0x705); + WREG32(0x65A4 + crtc->crtc_offset, 0x10001); + WREG32(0x65D8 + crtc->crtc_offset, 0x0); + WREG32(0x65B0 + crtc->crtc_offset, 0x0); + WREG32(0x65C0 + crtc->crtc_offset, 0x0); + WREG32(0x65D4 + crtc->crtc_offset, 0x0); + WREG32(index_reg, 0x0); + WREG32(data_reg, 0x841880A8); + WREG32(index_reg, 0x1); + WREG32(data_reg, 0x84208680); + WREG32(index_reg, 0x2); + WREG32(data_reg, 0xBFF880B0); + WREG32(index_reg, 0x100); + WREG32(data_reg, 0x83D88088); + WREG32(index_reg, 0x101); + WREG32(data_reg, 0x84608680); + WREG32(index_reg, 0x102); + WREG32(data_reg, 0xBFF080D0); + WREG32(index_reg, 0x200); + WREG32(data_reg, 0x83988068); + WREG32(index_reg, 0x201); + WREG32(data_reg, 0x84A08680); + WREG32(index_reg, 0x202); + WREG32(data_reg, 0xBFF080F8); + WREG32(index_reg, 0x300); + WREG32(data_reg, 0x83588058); + WREG32(index_reg, 0x301); + WREG32(data_reg, 0x84E08660); + WREG32(index_reg, 0x302); + WREG32(data_reg, 0xBFF88120); + WREG32(index_reg, 0x400); + WREG32(data_reg, 0x83188040); + WREG32(index_reg, 0x401); + WREG32(data_reg, 0x85008660); + WREG32(index_reg, 0x402); + WREG32(data_reg, 0xBFF88150); + WREG32(index_reg, 0x500); + WREG32(data_reg, 0x82D88030); + WREG32(index_reg, 0x501); + WREG32(data_reg, 0x85408640); + WREG32(index_reg, 0x502); + WREG32(data_reg, 0xBFF88180); + WREG32(index_reg, 0x600); + WREG32(data_reg, 0x82A08018); + WREG32(index_reg, 0x601); + WREG32(data_reg, 0x85808620); + WREG32(index_reg, 0x602); + WREG32(data_reg, 0xBFF081B8); + WREG32(index_reg, 0x700); + WREG32(data_reg, 0x82608010); + WREG32(index_reg, 0x701); + WREG32(data_reg, 0x85A08600); + WREG32(index_reg, 0x702); + WREG32(data_reg, 0x800081F0); + WREG32(index_reg, 0x800); + WREG32(data_reg, 0x8228BFF8); + WREG32(index_reg, 0x801); + WREG32(data_reg, 0x85E085E0); + WREG32(index_reg, 0x802); + WREG32(data_reg, 0xBFF88228); + WREG32(index_reg, 0x10000); + WREG32(data_reg, 0x82A8BF00); + WREG32(index_reg, 0x10001); + WREG32(data_reg, 0x82A08CC0); + WREG32(index_reg, 0x10002); + WREG32(data_reg, 0x8008BEF8); + WREG32(index_reg, 0x10100); + WREG32(data_reg, 0x81F0BF28); + WREG32(index_reg, 0x10101); + WREG32(data_reg, 0x83608CA0); + WREG32(index_reg, 0x10102); + WREG32(data_reg, 0x8018BED0); + WREG32(index_reg, 0x10200); + WREG32(data_reg, 0x8148BF38); + WREG32(index_reg, 0x10201); + WREG32(data_reg, 0x84408C80); + WREG32(index_reg, 0x10202); + WREG32(data_reg, 0x8008BEB8); + WREG32(index_reg, 0x10300); + WREG32(data_reg, 0x80B0BF78); + WREG32(index_reg, 0x10301); + WREG32(data_reg, 0x85008C20); + WREG32(index_reg, 0x10302); + WREG32(data_reg, 0x8020BEA0); + WREG32(index_reg, 0x10400); + WREG32(data_reg, 0x8028BF90); + WREG32(index_reg, 0x10401); + WREG32(data_reg, 0x85E08BC0); + WREG32(index_reg, 0x10402); + WREG32(data_reg, 0x8018BE90); + WREG32(index_reg, 0x10500); + WREG32(data_reg, 0xBFB8BFB0); + WREG32(index_reg, 0x10501); + WREG32(data_reg, 0x86C08B40); + WREG32(index_reg, 0x10502); + WREG32(data_reg, 0x8010BE90); + WREG32(index_reg, 0x10600); + WREG32(data_reg, 0xBF58BFC8); + WREG32(index_reg, 0x10601); + WREG32(data_reg, 0x87A08AA0); + WREG32(index_reg, 0x10602); + WREG32(data_reg, 0x8010BE98); + WREG32(index_reg, 0x10700); + WREG32(data_reg, 0xBF10BFF0); + WREG32(index_reg, 0x10701); + WREG32(data_reg, 0x886089E0); + WREG32(index_reg, 0x10702); + WREG32(data_reg, 0x8018BEB0); + WREG32(index_reg, 0x10800); + WREG32(data_reg, 0xBED8BFE8); + WREG32(index_reg, 0x10801); + WREG32(data_reg, 0x89408940); + WREG32(index_reg, 0x10802); + WREG32(data_reg, 0xBFE8BED8); + WREG32(index_reg, 0x20000); + WREG32(data_reg, 0x80008000); + WREG32(index_reg, 0x20001); + WREG32(data_reg, 0x90008000); + WREG32(index_reg, 0x20002); + WREG32(data_reg, 0x80008000); + WREG32(index_reg, 0x20003); + WREG32(data_reg, 0x80008000); + WREG32(index_reg, 0x20100); + WREG32(data_reg, 0x80108000); + WREG32(index_reg, 0x20101); + WREG32(data_reg, 0x8FE0BF70); + WREG32(index_reg, 0x20102); + WREG32(data_reg, 0xBFE880C0); + WREG32(index_reg, 0x20103); + WREG32(data_reg, 0x80008000); + WREG32(index_reg, 0x20200); + WREG32(data_reg, 0x8018BFF8); + WREG32(index_reg, 0x20201); + WREG32(data_reg, 0x8F80BF08); + WREG32(index_reg, 0x20202); + WREG32(data_reg, 0xBFD081A0); + WREG32(index_reg, 0x20203); + WREG32(data_reg, 0xBFF88000); + WREG32(index_reg, 0x20300); + WREG32(data_reg, 0x80188000); + WREG32(index_reg, 0x20301); + WREG32(data_reg, 0x8EE0BEC0); + WREG32(index_reg, 0x20302); + WREG32(data_reg, 0xBFB082A0); + WREG32(index_reg, 0x20303); + WREG32(data_reg, 0x80008000); + WREG32(index_reg, 0x20400); + WREG32(data_reg, 0x80188000); + WREG32(index_reg, 0x20401); + WREG32(data_reg, 0x8E00BEA0); + WREG32(index_reg, 0x20402); + WREG32(data_reg, 0xBF8883C0); + WREG32(index_reg, 0x20403); + WREG32(data_reg, 0x80008000); + WREG32(index_reg, 0x20500); + WREG32(data_reg, 0x80188000); + WREG32(index_reg, 0x20501); + WREG32(data_reg, 0x8D00BE90); + WREG32(index_reg, 0x20502); + WREG32(data_reg, 0xBF588500); + WREG32(index_reg, 0x20503); + WREG32(data_reg, 0x80008008); + WREG32(index_reg, 0x20600); + WREG32(data_reg, 0x80188000); + WREG32(index_reg, 0x20601); + WREG32(data_reg, 0x8BC0BE98); + WREG32(index_reg, 0x20602); + WREG32(data_reg, 0xBF308660); + WREG32(index_reg, 0x20603); + WREG32(data_reg, 0x80008008); + WREG32(index_reg, 0x20700); + WREG32(data_reg, 0x80108000); + WREG32(index_reg, 0x20701); + WREG32(data_reg, 0x8A80BEB0); + WREG32(index_reg, 0x20702); + WREG32(data_reg, 0xBF0087C0); + WREG32(index_reg, 0x20703); + WREG32(data_reg, 0x80008008); + WREG32(index_reg, 0x20800); + WREG32(data_reg, 0x80108000); + WREG32(index_reg, 0x20801); + WREG32(data_reg, 0x8920BED0); + WREG32(index_reg, 0x20802); + WREG32(data_reg, 0xBED08920); + WREG32(index_reg, 0x20803); + WREG32(data_reg, 0x80008010); + WREG32(index_reg, 0x30000); + WREG32(data_reg, 0x90008000); + WREG32(index_reg, 0x30001); + WREG32(data_reg, 0x80008000); + WREG32(index_reg, 0x30100); + WREG32(data_reg, 0x8FE0BF90); + WREG32(index_reg, 0x30101); + WREG32(data_reg, 0xBFF880A0); + WREG32(index_reg, 0x30200); + WREG32(data_reg, 0x8F60BF40); + WREG32(index_reg, 0x30201); + WREG32(data_reg, 0xBFE88180); + WREG32(index_reg, 0x30300); + WREG32(data_reg, 0x8EC0BF00); + WREG32(index_reg, 0x30301); + WREG32(data_reg, 0xBFC88280); + WREG32(index_reg, 0x30400); + WREG32(data_reg, 0x8DE0BEE0); + WREG32(index_reg, 0x30401); + WREG32(data_reg, 0xBFA083A0); + WREG32(index_reg, 0x30500); + WREG32(data_reg, 0x8CE0BED0); + WREG32(index_reg, 0x30501); + WREG32(data_reg, 0xBF7884E0); + WREG32(index_reg, 0x30600); + WREG32(data_reg, 0x8BA0BED8); + WREG32(index_reg, 0x30601); + WREG32(data_reg, 0xBF508640); + WREG32(index_reg, 0x30700); + WREG32(data_reg, 0x8A60BEE8); + WREG32(index_reg, 0x30701); + WREG32(data_reg, 0xBF2087A0); + WREG32(index_reg, 0x30800); + WREG32(data_reg, 0x8900BF00); + WREG32(index_reg, 0x30801); + WREG32(data_reg, 0xBF008900); } struct rv515_watermark { diff --git a/drivers/gpu/drm/radeon/rv515r.h b/drivers/gpu/drm/radeon/rv515d.h similarity index 78% rename from drivers/gpu/drm/radeon/rv515r.h rename to drivers/gpu/drm/radeon/rv515d.h index f3cf84039906..a65e17ec1c08 100644 --- a/drivers/gpu/drm/radeon/rv515r.h +++ b/drivers/gpu/drm/radeon/rv515d.h @@ -25,10 +25,12 @@ * Alex Deucher * Jerome Glisse */ -#ifndef RV515R_H -#define RV515R_H +#ifndef __RV515D_H__ +#define __RV515D_H__ -/* RV515 registers */ +/* + * RV515 registers + */ #define PCIE_INDEX 0x0030 #define PCIE_DATA 0x0034 #define MC_IND_INDEX 0x0070 @@ -166,5 +168,53 @@ #define MC_GLOBW_INIT_LAT_MASK 0xF0000000 +/* + * PM4 packet + */ +#define CP_PACKET0 0x00000000 +#define PACKET0_BASE_INDEX_SHIFT 0 +#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) +#define PACKET0_COUNT_SHIFT 16 +#define PACKET0_COUNT_MASK (0x3fff << 16) +#define CP_PACKET1 0x40000000 +#define CP_PACKET2 0x80000000 +#define PACKET2_PAD_SHIFT 0 +#define PACKET2_PAD_MASK (0x3fffffff << 0) +#define CP_PACKET3 0xC0000000 +#define PACKET3_IT_OPCODE_SHIFT 8 +#define PACKET3_IT_OPCODE_MASK (0xff << 8) +#define PACKET3_COUNT_SHIFT 16 +#define PACKET3_COUNT_MASK (0x3fff << 16) +/* PACKET3 op code */ +#define PACKET3_NOP 0x10 +#define PACKET3_3D_DRAW_VBUF 0x28 +#define PACKET3_3D_DRAW_IMMD 0x29 +#define PACKET3_3D_DRAW_INDX 0x2A +#define PACKET3_3D_LOAD_VBPNTR 0x2F +#define PACKET3_INDX_BUFFER 0x33 +#define PACKET3_3D_DRAW_VBUF_2 0x34 +#define PACKET3_3D_DRAW_IMMD_2 0x35 +#define PACKET3_3D_DRAW_INDX_2 0x36 +#define PACKET3_BITBLT_MULTI 0x9B + +#define PACKET0(reg, n) (CP_PACKET0 | \ + REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ + REG_SET(PACKET0_COUNT, (n))) +#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) +#define PACKET3(op, n) (CP_PACKET3 | \ + REG_SET(PACKET3_IT_OPCODE, (op)) | \ + REG_SET(PACKET3_COUNT, (n))) + +#define PACKET_TYPE0 0 +#define PACKET_TYPE1 1 +#define PACKET_TYPE2 2 +#define PACKET_TYPE3 3 + +#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) +#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) +#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) +#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) +#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) + #endif diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 21d8ffd57308..b574c73a5109 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -25,100 +25,1038 @@ * Alex Deucher * Jerome Glisse */ +#include +#include #include "drmP.h" -#include "radeon_reg.h" #include "radeon.h" +#include "radeon_drm.h" +#include "rv770d.h" +#include "avivod.h" +#include "atom.h" -/* rv770,rv730,rv710 depends on : */ -void rs600_mc_disable_clients(struct radeon_device *rdev); +#define R700_PFP_UCODE_SIZE 848 +#define R700_PM4_UCODE_SIZE 1360 -/* This files gather functions specifics to: - * rv770,rv730,rv710 - * - * Some of these functions might be used by newer ASICs. - */ -int rv770_mc_wait_for_idle(struct radeon_device *rdev); -void rv770_gpu_init(struct radeon_device *rdev); +static void rv770_gpu_init(struct radeon_device *rdev); +void rv770_fini(struct radeon_device *rdev); /* - * MC + * GART */ -int rv770_mc_init(struct radeon_device *rdev) +int rv770_pcie_gart_enable(struct radeon_device *rdev) { - uint32_t tmp; + u32 tmp; + int r, i; - rv770_gpu_init(rdev); + if (rdev->gart.table.vram.robj == NULL) { + dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); + return -EINVAL; + } + r = radeon_gart_table_vram_pin(rdev); + if (r) + return r; + /* Setup L2 cache */ + WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | + ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | + EFFECTIVE_L2_QUEUE_SIZE(7)); + WREG32(VM_L2_CNTL2, 0); + WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); + /* Setup TLB control */ + tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | + SYSTEM_ACCESS_MODE_NOT_IN_SYS | + SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | + EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); + WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); + WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); + WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); + WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12); + WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); + WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); + WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, + (u32)(rdev->dummy_page.addr >> 12)); + for (i = 1; i < 7; i++) + WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); - /* setup the gart before changing location so we can ask to - * discard unmapped mc request - */ - /* FIXME: disable out of gart access */ - tmp = rdev->mc.gtt_location / 4096; - tmp = REG_SET(R700_LOGICAL_PAGE_NUMBER, tmp); - WREG32(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp); - tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096; - tmp = REG_SET(R700_LOGICAL_PAGE_NUMBER, tmp); - WREG32(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp); - - rs600_mc_disable_clients(rdev); - if (rv770_mc_wait_for_idle(rdev)) { - printk(KERN_WARNING "Failed to wait MC idle while " - "programming pipes. Bad things might happen.\n"); - } - - tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; - tmp = REG_SET(R700_MC_FB_TOP, tmp >> 24); - tmp |= REG_SET(R700_MC_FB_BASE, rdev->mc.vram_location >> 24); - WREG32(R700_MC_VM_FB_LOCATION, tmp); - tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; - tmp = REG_SET(R700_MC_AGP_TOP, tmp >> 22); - WREG32(R700_MC_VM_AGP_TOP, tmp); - tmp = REG_SET(R700_MC_AGP_BOT, rdev->mc.gtt_location >> 22); - WREG32(R700_MC_VM_AGP_BOT, tmp); + r600_pcie_gart_tlb_flush(rdev); + rdev->gart.ready = true; return 0; } -void rv770_mc_fini(struct radeon_device *rdev) +void rv770_pcie_gart_disable(struct radeon_device *rdev) +{ + u32 tmp; + int i; + + /* Disable all tables */ + for (i = 0; i < 7; i++) + WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); + + /* Setup L2 cache */ + WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | + EFFECTIVE_L2_QUEUE_SIZE(7)); + WREG32(VM_L2_CNTL2, 0); + WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); + /* Setup TLB control */ + tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); + WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); + WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); + WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); + if (rdev->gart.table.vram.robj) { + radeon_object_kunmap(rdev->gart.table.vram.robj); + radeon_object_unpin(rdev->gart.table.vram.robj); + } +} + +void rv770_pcie_gart_fini(struct radeon_device *rdev) { - /* FIXME: implement */ + rv770_pcie_gart_disable(rdev); + radeon_gart_table_vram_free(rdev); + radeon_gart_fini(rdev); } /* - * Global GPU functions + * MC */ -void rv770_errata(struct radeon_device *rdev) +static void rv770_mc_resume(struct radeon_device *rdev) { - rdev->pll_errata = 0; + u32 d1vga_control, d2vga_control; + u32 vga_render_control, vga_hdp_control; + u32 d1crtc_control, d2crtc_control; + u32 new_d1grph_primary, new_d1grph_secondary; + u32 new_d2grph_primary, new_d2grph_secondary; + u64 old_vram_start; + u32 tmp; + int i, j; + + /* Initialize HDP */ + for (i = 0, j = 0; i < 32; i++, j += 0x18) { + WREG32((0x2c14 + j), 0x00000000); + WREG32((0x2c18 + j), 0x00000000); + WREG32((0x2c1c + j), 0x00000000); + WREG32((0x2c20 + j), 0x00000000); + WREG32((0x2c24 + j), 0x00000000); + } + WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); + + d1vga_control = RREG32(D1VGA_CONTROL); + d2vga_control = RREG32(D2VGA_CONTROL); + vga_render_control = RREG32(VGA_RENDER_CONTROL); + vga_hdp_control = RREG32(VGA_HDP_CONTROL); + d1crtc_control = RREG32(D1CRTC_CONTROL); + d2crtc_control = RREG32(D2CRTC_CONTROL); + old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; + new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS); + new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS); + new_d1grph_primary += rdev->mc.vram_start - old_vram_start; + new_d1grph_secondary += rdev->mc.vram_start - old_vram_start; + new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS); + new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS); + new_d2grph_primary += rdev->mc.vram_start - old_vram_start; + new_d2grph_secondary += rdev->mc.vram_start - old_vram_start; + + /* Stop all video */ + WREG32(D1VGA_CONTROL, 0); + WREG32(D2VGA_CONTROL, 0); + WREG32(VGA_RENDER_CONTROL, 0); + WREG32(D1CRTC_UPDATE_LOCK, 1); + WREG32(D2CRTC_UPDATE_LOCK, 1); + WREG32(D1CRTC_CONTROL, 0); + WREG32(D2CRTC_CONTROL, 0); + WREG32(D1CRTC_UPDATE_LOCK, 0); + WREG32(D2CRTC_UPDATE_LOCK, 0); + + mdelay(1); + if (r600_mc_wait_for_idle(rdev)) { + printk(KERN_WARNING "[drm] MC not idle !\n"); + } + + /* Lockout access through VGA aperture*/ + WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); + + /* Update configuration */ + WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); + WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12); + WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); + tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16; + tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); + WREG32(MC_VM_FB_LOCATION, tmp); + WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); + WREG32(HDP_NONSURFACE_INFO, (2 << 7)); + WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF); + if (rdev->flags & RADEON_IS_AGP) { + WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16); + WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); + WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); + } else { + WREG32(MC_VM_AGP_BASE, 0); + WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); + WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); + } + WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary); + WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary); + WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary); + WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary); + WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); + + /* Unlock host access */ + WREG32(VGA_HDP_CONTROL, vga_hdp_control); + + mdelay(1); + if (r600_mc_wait_for_idle(rdev)) { + printk(KERN_WARNING "[drm] MC not idle !\n"); + } + + /* Restore video state */ + WREG32(D1CRTC_UPDATE_LOCK, 1); + WREG32(D2CRTC_UPDATE_LOCK, 1); + WREG32(D1CRTC_CONTROL, d1crtc_control); + WREG32(D2CRTC_CONTROL, d2crtc_control); + WREG32(D1CRTC_UPDATE_LOCK, 0); + WREG32(D2CRTC_UPDATE_LOCK, 0); + WREG32(D1VGA_CONTROL, d1vga_control); + WREG32(D2VGA_CONTROL, d2vga_control); + WREG32(VGA_RENDER_CONTROL, vga_render_control); + + /* we need to own VRAM, so turn off the VGA renderer here + * to stop it overwriting our objects */ + radeon_avivo_vga_render_disable(rdev); } -int rv770_mc_wait_for_idle(struct radeon_device *rdev) + +/* + * CP. + */ +void r700_cp_stop(struct radeon_device *rdev) { - /* FIXME: implement */ - return 0; + WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); } -void rv770_gpu_init(struct radeon_device *rdev) + +static int rv770_cp_load_microcode(struct radeon_device *rdev) { - /* FIXME: implement */ + const __be32 *fw_data; + int i; + + if (!rdev->me_fw || !rdev->pfp_fw) + return -EINVAL; + + r700_cp_stop(rdev); + WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0)); + + /* Reset cp */ + WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); + RREG32(GRBM_SOFT_RESET); + mdelay(15); + WREG32(GRBM_SOFT_RESET, 0); + + fw_data = (const __be32 *)rdev->pfp_fw->data; + WREG32(CP_PFP_UCODE_ADDR, 0); + for (i = 0; i < R700_PFP_UCODE_SIZE; i++) + WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); + WREG32(CP_PFP_UCODE_ADDR, 0); + + fw_data = (const __be32 *)rdev->me_fw->data; + WREG32(CP_ME_RAM_WADDR, 0); + for (i = 0; i < R700_PM4_UCODE_SIZE; i++) + WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); + + WREG32(CP_PFP_UCODE_ADDR, 0); + WREG32(CP_ME_RAM_WADDR, 0); + WREG32(CP_ME_RAM_RADDR, 0); + return 0; } /* - * VRAM info + * Core functions */ -void rv770_vram_get_type(struct radeon_device *rdev) +static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, + u32 num_backends, + u32 backend_disable_mask) +{ + u32 backend_map = 0; + u32 enabled_backends_mask; + u32 enabled_backends_count; + u32 cur_pipe; + u32 swizzle_pipe[R7XX_MAX_PIPES]; + u32 cur_backend; + u32 i; + + if (num_tile_pipes > R7XX_MAX_PIPES) + num_tile_pipes = R7XX_MAX_PIPES; + if (num_tile_pipes < 1) + num_tile_pipes = 1; + if (num_backends > R7XX_MAX_BACKENDS) + num_backends = R7XX_MAX_BACKENDS; + if (num_backends < 1) + num_backends = 1; + + enabled_backends_mask = 0; + enabled_backends_count = 0; + for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { + if (((backend_disable_mask >> i) & 1) == 0) { + enabled_backends_mask |= (1 << i); + ++enabled_backends_count; + } + if (enabled_backends_count == num_backends) + break; + } + + if (enabled_backends_count == 0) { + enabled_backends_mask = 1; + enabled_backends_count = 1; + } + + if (enabled_backends_count != num_backends) + num_backends = enabled_backends_count; + + memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); + switch (num_tile_pipes) { + case 1: + swizzle_pipe[0] = 0; + break; + case 2: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + break; + case 3: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 1; + break; + case 4: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 3; + swizzle_pipe[3] = 1; + break; + case 5: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 1; + swizzle_pipe[4] = 3; + break; + case 6: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 5; + swizzle_pipe[4] = 3; + swizzle_pipe[5] = 1; + break; + case 7: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 6; + swizzle_pipe[4] = 3; + swizzle_pipe[5] = 1; + swizzle_pipe[6] = 5; + break; + case 8: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 6; + swizzle_pipe[4] = 3; + swizzle_pipe[5] = 1; + swizzle_pipe[6] = 7; + swizzle_pipe[7] = 5; + break; + } + + cur_backend = 0; + for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { + while (((1 << cur_backend) & enabled_backends_mask) == 0) + cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; + + backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); + + cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; + } + + return backend_map; +} + +static void rv770_gpu_init(struct radeon_device *rdev) { - /* FIXME: implement */ + int i, j, num_qd_pipes; + u32 sx_debug_1; + u32 smx_dc_ctl0; + u32 num_gs_verts_per_thread; + u32 vgt_gs_per_es; + u32 gs_prim_buffer_depth = 0; + u32 sq_ms_fifo_sizes; + u32 sq_config; + u32 sq_thread_resource_mgmt; + u32 hdp_host_path_cntl; + u32 sq_dyn_gpr_size_simd_ab_0; + u32 backend_map; + u32 gb_tiling_config = 0; + u32 cc_rb_backend_disable = 0; + u32 cc_gc_shader_pipe_config = 0; + u32 mc_arb_ramcfg; + u32 db_debug4; + + /* setup chip specs */ + switch (rdev->family) { + case CHIP_RV770: + rdev->config.rv770.max_pipes = 4; + rdev->config.rv770.max_tile_pipes = 8; + rdev->config.rv770.max_simds = 10; + rdev->config.rv770.max_backends = 4; + rdev->config.rv770.max_gprs = 256; + rdev->config.rv770.max_threads = 248; + rdev->config.rv770.max_stack_entries = 512; + rdev->config.rv770.max_hw_contexts = 8; + rdev->config.rv770.max_gs_threads = 16 * 2; + rdev->config.rv770.sx_max_export_size = 128; + rdev->config.rv770.sx_max_export_pos_size = 16; + rdev->config.rv770.sx_max_export_smx_size = 112; + rdev->config.rv770.sq_num_cf_insts = 2; + + rdev->config.rv770.sx_num_of_sets = 7; + rdev->config.rv770.sc_prim_fifo_size = 0xF9; + rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; + rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; + break; + case CHIP_RV730: + rdev->config.rv770.max_pipes = 2; + rdev->config.rv770.max_tile_pipes = 4; + rdev->config.rv770.max_simds = 8; + rdev->config.rv770.max_backends = 2; + rdev->config.rv770.max_gprs = 128; + rdev->config.rv770.max_threads = 248; + rdev->config.rv770.max_stack_entries = 256; + rdev->config.rv770.max_hw_contexts = 8; + rdev->config.rv770.max_gs_threads = 16 * 2; + rdev->config.rv770.sx_max_export_size = 256; + rdev->config.rv770.sx_max_export_pos_size = 32; + rdev->config.rv770.sx_max_export_smx_size = 224; + rdev->config.rv770.sq_num_cf_insts = 2; + + rdev->config.rv770.sx_num_of_sets = 7; + rdev->config.rv770.sc_prim_fifo_size = 0xf9; + rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; + rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; + if (rdev->config.rv770.sx_max_export_pos_size > 16) { + rdev->config.rv770.sx_max_export_pos_size -= 16; + rdev->config.rv770.sx_max_export_smx_size += 16; + } + break; + case CHIP_RV710: + rdev->config.rv770.max_pipes = 2; + rdev->config.rv770.max_tile_pipes = 2; + rdev->config.rv770.max_simds = 2; + rdev->config.rv770.max_backends = 1; + rdev->config.rv770.max_gprs = 256; + rdev->config.rv770.max_threads = 192; + rdev->config.rv770.max_stack_entries = 256; + rdev->config.rv770.max_hw_contexts = 4; + rdev->config.rv770.max_gs_threads = 8 * 2; + rdev->config.rv770.sx_max_export_size = 128; + rdev->config.rv770.sx_max_export_pos_size = 16; + rdev->config.rv770.sx_max_export_smx_size = 112; + rdev->config.rv770.sq_num_cf_insts = 1; + + rdev->config.rv770.sx_num_of_sets = 7; + rdev->config.rv770.sc_prim_fifo_size = 0x40; + rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; + rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; + break; + case CHIP_RV740: + rdev->config.rv770.max_pipes = 4; + rdev->config.rv770.max_tile_pipes = 4; + rdev->config.rv770.max_simds = 8; + rdev->config.rv770.max_backends = 4; + rdev->config.rv770.max_gprs = 256; + rdev->config.rv770.max_threads = 248; + rdev->config.rv770.max_stack_entries = 512; + rdev->config.rv770.max_hw_contexts = 8; + rdev->config.rv770.max_gs_threads = 16 * 2; + rdev->config.rv770.sx_max_export_size = 256; + rdev->config.rv770.sx_max_export_pos_size = 32; + rdev->config.rv770.sx_max_export_smx_size = 224; + rdev->config.rv770.sq_num_cf_insts = 2; + + rdev->config.rv770.sx_num_of_sets = 7; + rdev->config.rv770.sc_prim_fifo_size = 0x100; + rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; + rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; + + if (rdev->config.rv770.sx_max_export_pos_size > 16) { + rdev->config.rv770.sx_max_export_pos_size -= 16; + rdev->config.rv770.sx_max_export_smx_size += 16; + } + break; + default: + break; + } + + /* Initialize HDP */ + j = 0; + for (i = 0; i < 32; i++) { + WREG32((0x2c14 + j), 0x00000000); + WREG32((0x2c18 + j), 0x00000000); + WREG32((0x2c1c + j), 0x00000000); + WREG32((0x2c20 + j), 0x00000000); + WREG32((0x2c24 + j), 0x00000000); + j += 0x18; + } + + WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); + + /* setup tiling, simd, pipe config */ + mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); + + switch (rdev->config.rv770.max_tile_pipes) { + case 1: + gb_tiling_config |= PIPE_TILING(0); + break; + case 2: + gb_tiling_config |= PIPE_TILING(1); + break; + case 4: + gb_tiling_config |= PIPE_TILING(2); + break; + case 8: + gb_tiling_config |= PIPE_TILING(3); + break; + default: + break; + } + + if (rdev->family == CHIP_RV770) + gb_tiling_config |= BANK_TILING(1); + else + gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK); + + gb_tiling_config |= GROUP_SIZE(0); + + if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) { + gb_tiling_config |= ROW_TILING(3); + gb_tiling_config |= SAMPLE_SPLIT(3); + } else { + gb_tiling_config |= + ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); + gb_tiling_config |= + SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); + } + + gb_tiling_config |= BANK_SWAPS(1); + + backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes, + rdev->config.rv770.max_backends, + (0xff << rdev->config.rv770.max_backends) & 0xff); + gb_tiling_config |= BACKEND_MAP(backend_map); + + cc_gc_shader_pipe_config = + INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK); + cc_gc_shader_pipe_config |= + INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK); + + cc_rb_backend_disable = + BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK); + + WREG32(GB_TILING_CONFIG, gb_tiling_config); + WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); + WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); + + WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); + WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); + WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); + + WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); + WREG32(CGTS_SYS_TCC_DISABLE, 0); + WREG32(CGTS_TCC_DISABLE, 0); + WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); + WREG32(CGTS_USER_TCC_DISABLE, 0); + + num_qd_pipes = + R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK); + WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); + WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); + + /* set HW defaults for 3D engine */ + WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | + ROQ_IB2_START(0x2b))); + + WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); + + WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | + SYNC_GRADIENT | + SYNC_WALKER | + SYNC_ALIGNER)); + + sx_debug_1 = RREG32(SX_DEBUG_1); + sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; + WREG32(SX_DEBUG_1, sx_debug_1); + + smx_dc_ctl0 = RREG32(SMX_DC_CTL0); + smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); + smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); + WREG32(SMX_DC_CTL0, smx_dc_ctl0); + + WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | + GS_FLUSH_CTL(4) | + ACK_FLUSH_CTL(3) | + SYNC_FLUSH_CTL)); + + if (rdev->family == CHIP_RV770) + WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f)); + else { + db_debug4 = RREG32(DB_DEBUG4); + db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; + WREG32(DB_DEBUG4, db_debug4); + } + + WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | + POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | + SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); + + WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | + SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | + SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); + + WREG32(PA_SC_MULTI_CHIP_CNTL, 0); + + WREG32(VGT_NUM_INSTANCES, 1); + + WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); + + WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); + + WREG32(CP_PERFMON_CNTL, 0); + + sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | + DONE_FIFO_HIWATER(0xe0) | + ALU_UPDATE_FIFO_HIWATER(0x8)); + switch (rdev->family) { + case CHIP_RV770: + sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); + break; + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + default: + sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); + break; + } + WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); + + /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT + * should be adjusted as needed by the 2D/3D drivers. This just sets default values + */ + sq_config = RREG32(SQ_CONFIG); + sq_config &= ~(PS_PRIO(3) | + VS_PRIO(3) | + GS_PRIO(3) | + ES_PRIO(3)); + sq_config |= (DX9_CONSTS | + VC_ENABLE | + EXPORT_SRC_C | + PS_PRIO(0) | + VS_PRIO(1) | + GS_PRIO(2) | + ES_PRIO(3)); + if (rdev->family == CHIP_RV710) + /* no vertex cache */ + sq_config &= ~VC_ENABLE; + + WREG32(SQ_CONFIG, sq_config); + + WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | + NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | + NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); + + WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | + NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); + + sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | + NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | + NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); + if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) + sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); + else + sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); + WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); + + WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | + NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); + + WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | + NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); + + sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | + SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | + SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | + SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); + + WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); + WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); + WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); + WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); + WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); + WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); + WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); + WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); + + WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | + FORCE_EOV_MAX_REZ_CNT(255))); + + if (rdev->family == CHIP_RV710) + WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | + AUTO_INVLD_EN(ES_AND_GS_AUTO))); + else + WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | + AUTO_INVLD_EN(ES_AND_GS_AUTO))); + + switch (rdev->family) { + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV740: + gs_prim_buffer_depth = 384; + break; + case CHIP_RV710: + gs_prim_buffer_depth = 128; + break; + default: + break; + } + + num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; + vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; + /* Max value for this is 256 */ + if (vgt_gs_per_es > 256) + vgt_gs_per_es = 256; + + WREG32(VGT_ES_PER_GS, 128); + WREG32(VGT_GS_PER_ES, vgt_gs_per_es); + WREG32(VGT_GS_PER_VS, 2); + + /* more default values. 2D/3D driver should adjust as needed */ + WREG32(VGT_GS_VERTEX_REUSE, 16); + WREG32(PA_SC_LINE_STIPPLE_STATE, 0); + WREG32(VGT_STRMOUT_EN, 0); + WREG32(SX_MISC, 0); + WREG32(PA_SC_MODE_CNTL, 0); + WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); + WREG32(PA_SC_AA_CONFIG, 0); + WREG32(PA_SC_CLIPRECT_RULE, 0xffff); + WREG32(PA_SC_LINE_STIPPLE, 0); + WREG32(SPI_INPUT_Z, 0); + WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); + WREG32(CB_COLOR7_FRAG, 0); + + /* clear render buffer base addresses */ + WREG32(CB_COLOR0_BASE, 0); + WREG32(CB_COLOR1_BASE, 0); + WREG32(CB_COLOR2_BASE, 0); + WREG32(CB_COLOR3_BASE, 0); + WREG32(CB_COLOR4_BASE, 0); + WREG32(CB_COLOR5_BASE, 0); + WREG32(CB_COLOR6_BASE, 0); + WREG32(CB_COLOR7_BASE, 0); + + WREG32(TCP_CNTL, 0); + + hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); + WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); + + WREG32(PA_SC_MULTI_CHIP_CNTL, 0); + + WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | + NUM_CLIP_SEQ(3))); + } -void rv770_vram_info(struct radeon_device *rdev) +int rv770_mc_init(struct radeon_device *rdev) { - rv770_vram_get_type(rdev); + fixed20_12 a; + u32 tmp; + int r; - /* FIXME: implement */ + /* Get VRAM informations */ + /* FIXME: Don't know how to determine vram width, need to check + * vram_width usage + */ + rdev->mc.vram_width = 128; + rdev->mc.vram_is_ddr = true; /* Could aper size report 0 ? */ rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); + /* Setup GPU memory space */ + rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); + rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); + if (rdev->flags & RADEON_IS_AGP) { + r = radeon_agp_init(rdev); + if (r) + return r; + /* gtt_size is setup by radeon_agp_init */ + rdev->mc.gtt_location = rdev->mc.agp_base; + tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; + /* Try to put vram before or after AGP because we + * we want SYSTEM_APERTURE to cover both VRAM and + * AGP so that GPU can catch out of VRAM/AGP access + */ + if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { + /* Enought place before */ + rdev->mc.vram_location = rdev->mc.gtt_location - + rdev->mc.mc_vram_size; + } else if (tmp > rdev->mc.mc_vram_size) { + /* Enought place after */ + rdev->mc.vram_location = rdev->mc.gtt_location + + rdev->mc.gtt_size; + } else { + /* Try to setup VRAM then AGP might not + * not work on some card + */ + rdev->mc.vram_location = 0x00000000UL; + rdev->mc.gtt_location = rdev->mc.mc_vram_size; + } + } else { + rdev->mc.vram_location = 0x00000000UL; + rdev->mc.gtt_location = rdev->mc.mc_vram_size; + rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; + } + rdev->mc.vram_start = rdev->mc.vram_location; + rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size; + rdev->mc.gtt_start = rdev->mc.gtt_location; + rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size; + /* FIXME: we should enforce default clock in case GPU is not in + * default setup + */ + a.full = rfixed_const(100); + rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); + rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); + return 0; +} +int rv770_gpu_reset(struct radeon_device *rdev) +{ + /* FIXME: implement any rv770 specific bits */ + return r600_gpu_reset(rdev); +} + +static int rv770_startup(struct radeon_device *rdev) +{ + int r; + + radeon_gpu_reset(rdev); + rv770_mc_resume(rdev); + r = rv770_pcie_gart_enable(rdev); + if (r) + return r; + rv770_gpu_init(rdev); + + r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, + &rdev->r600_blit.shader_gpu_addr); + if (r) { + DRM_ERROR("failed to pin blit object %d\n", r); + return r; + } + + r = radeon_ring_init(rdev, rdev->cp.ring_size); + if (r) + return r; + r = rv770_cp_load_microcode(rdev); + if (r) + return r; + r = r600_cp_resume(rdev); + if (r) + return r; + r = r600_wb_init(rdev); + if (r) + return r; + return 0; +} + +int rv770_resume(struct radeon_device *rdev) +{ + int r; + + if (radeon_gpu_reset(rdev)) { + /* FIXME: what do we want to do here ? */ + } + /* post card */ + if (rdev->is_atom_bios) { + atom_asic_init(rdev->mode_info.atom_context); + } else { + radeon_combios_asic_init(rdev->ddev); + } + /* Initialize clocks */ + r = radeon_clocks_init(rdev); + if (r) { + return r; + } + + r = rv770_startup(rdev); + if (r) { + DRM_ERROR("r600 startup failed on resume\n"); + return r; + } + + r = radeon_ib_test(rdev); + if (r) { + DRM_ERROR("radeon: failled testing IB (%d).\n", r); + return r; + } + return r; + +} + +int rv770_suspend(struct radeon_device *rdev) +{ + /* FIXME: we should wait for ring to be empty */ + r700_cp_stop(rdev); + rdev->cp.ready = false; + rv770_pcie_gart_disable(rdev); + + /* unpin shaders bo */ + radeon_object_unpin(rdev->r600_blit.shader_obj); + return 0; +} + +/* Plan is to move initialization in that function and use + * helper function so that radeon_device_init pretty much + * do nothing more than calling asic specific function. This + * should also allow to remove a bunch of callback function + * like vram_info. + */ +int rv770_init(struct radeon_device *rdev) +{ + int r; + + rdev->new_init_path = true; + r = radeon_dummy_page_init(rdev); + if (r) + return r; + /* This don't do much */ + r = radeon_gem_init(rdev); + if (r) + return r; + /* Read BIOS */ + if (!radeon_get_bios(rdev)) { + if (ASIC_IS_AVIVO(rdev)) + return -EINVAL; + } + /* Must be an ATOMBIOS */ + if (!rdev->is_atom_bios) + return -EINVAL; + r = radeon_atombios_init(rdev); + if (r) + return r; + /* Post card if necessary */ + if (!r600_card_posted(rdev) && rdev->bios) { + DRM_INFO("GPU not posted. posting now...\n"); + atom_asic_init(rdev->mode_info.atom_context); + } + /* Initialize scratch registers */ + r600_scratch_init(rdev); + /* Initialize surface registers */ + radeon_surface_init(rdev); + radeon_get_clock_info(rdev->ddev); + r = radeon_clocks_init(rdev); + if (r) + return r; + /* Fence driver */ + r = radeon_fence_driver_init(rdev); + if (r) + return r; + r = rv770_mc_init(rdev); + if (r) { + if (rdev->flags & RADEON_IS_AGP) { + /* Retry with disabling AGP */ + rv770_fini(rdev); + rdev->flags &= ~RADEON_IS_AGP; + return rv770_init(rdev); + } + return r; + } + /* Memory manager */ + r = radeon_object_init(rdev); + if (r) + return r; + rdev->cp.ring_obj = NULL; + r600_ring_init(rdev, 1024 * 1024); + + if (!rdev->me_fw || !rdev->pfp_fw) { + r = r600_cp_init_microcode(rdev); + if (r) { + DRM_ERROR("Failed to load firmware!\n"); + return r; + } + } + + r = r600_pcie_gart_init(rdev); + if (r) + return r; + + rdev->accel_working = true; + r = r600_blit_init(rdev); + if (r) { + DRM_ERROR("radeon: failled blitter (%d).\n", r); + rdev->accel_working = false; + } + + r = rv770_startup(rdev); + if (r) { + if (rdev->flags & RADEON_IS_AGP) { + /* Retry with disabling AGP */ + rv770_fini(rdev); + rdev->flags &= ~RADEON_IS_AGP; + return rv770_init(rdev); + } + rdev->accel_working = false; + } + if (rdev->accel_working) { + r = radeon_ib_pool_init(rdev); + if (r) { + DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); + rdev->accel_working = false; + } + r = radeon_ib_test(rdev); + if (r) { + DRM_ERROR("radeon: failled testing IB (%d).\n", r); + rdev->accel_working = false; + } + } + return 0; +} + +void rv770_fini(struct radeon_device *rdev) +{ + rv770_suspend(rdev); + + r600_blit_fini(rdev); + radeon_ring_fini(rdev); + rv770_pcie_gart_fini(rdev); + radeon_gem_fini(rdev); + radeon_fence_driver_fini(rdev); + radeon_clocks_fini(rdev); +#if __OS_HAS_AGP + if (rdev->flags & RADEON_IS_AGP) + radeon_agp_fini(rdev); +#endif + radeon_object_fini(rdev); + if (rdev->is_atom_bios) { + radeon_atombios_fini(rdev); + } else { + radeon_combios_fini(rdev); + } + kfree(rdev->bios); + rdev->bios = NULL; + radeon_dummy_page_fini(rdev); } diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h new file mode 100644 index 000000000000..4b9c3d6396ff --- /dev/null +++ b/drivers/gpu/drm/radeon/rv770d.h @@ -0,0 +1,341 @@ +/* + * Copyright 2009 Advanced Micro Devices, Inc. + * Copyright 2009 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef RV770_H +#define RV770_H + +#define R7XX_MAX_SH_GPRS 256 +#define R7XX_MAX_TEMP_GPRS 16 +#define R7XX_MAX_SH_THREADS 256 +#define R7XX_MAX_SH_STACK_ENTRIES 4096 +#define R7XX_MAX_BACKENDS 8 +#define R7XX_MAX_BACKENDS_MASK 0xff +#define R7XX_MAX_SIMDS 16 +#define R7XX_MAX_SIMDS_MASK 0xffff +#define R7XX_MAX_PIPES 8 +#define R7XX_MAX_PIPES_MASK 0xff + +/* Registers */ +#define CB_COLOR0_BASE 0x28040 +#define CB_COLOR1_BASE 0x28044 +#define CB_COLOR2_BASE 0x28048 +#define CB_COLOR3_BASE 0x2804C +#define CB_COLOR4_BASE 0x28050 +#define CB_COLOR5_BASE 0x28054 +#define CB_COLOR6_BASE 0x28058 +#define CB_COLOR7_BASE 0x2805C +#define CB_COLOR7_FRAG 0x280FC + +#define CC_GC_SHADER_PIPE_CONFIG 0x8950 +#define CC_RB_BACKEND_DISABLE 0x98F4 +#define BACKEND_DISABLE(x) ((x) << 16) +#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 + +#define CGTS_SYS_TCC_DISABLE 0x3F90 +#define CGTS_TCC_DISABLE 0x9148 +#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 +#define CGTS_USER_TCC_DISABLE 0x914C + +#define CONFIG_MEMSIZE 0x5428 + +#define CP_ME_CNTL 0x86D8 +#define CP_ME_HALT (1<<28) +#define CP_PFP_HALT (1<<26) +#define CP_ME_RAM_DATA 0xC160 +#define CP_ME_RAM_RADDR 0xC158 +#define CP_ME_RAM_WADDR 0xC15C +#define CP_MEQ_THRESHOLDS 0x8764 +#define STQ_SPLIT(x) ((x) << 0) +#define CP_PERFMON_CNTL 0x87FC +#define CP_PFP_UCODE_ADDR 0xC150 +#define CP_PFP_UCODE_DATA 0xC154 +#define CP_QUEUE_THRESHOLDS 0x8760 +#define ROQ_IB1_START(x) ((x) << 0) +#define ROQ_IB2_START(x) ((x) << 8) +#define CP_RB_CNTL 0xC104 +#define RB_BUFSZ(x) ((x)<<0) +#define RB_BLKSZ(x) ((x)<<8) +#define RB_NO_UPDATE (1<<27) +#define RB_RPTR_WR_ENA (1<<31) +#define BUF_SWAP_32BIT (2 << 16) +#define CP_RB_RPTR 0x8700 +#define CP_RB_RPTR_ADDR 0xC10C +#define CP_RB_RPTR_ADDR_HI 0xC110 +#define CP_RB_RPTR_WR 0xC108 +#define CP_RB_WPTR 0xC114 +#define CP_RB_WPTR_ADDR 0xC118 +#define CP_RB_WPTR_ADDR_HI 0xC11C +#define CP_RB_WPTR_DELAY 0x8704 +#define CP_SEM_WAIT_TIMER 0x85BC + +#define DB_DEBUG3 0x98B0 +#define DB_CLK_OFF_DELAY(x) ((x) << 11) +#define DB_DEBUG4 0x9B8C +#define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) + +#define DCP_TILING_CONFIG 0x6CA0 +#define PIPE_TILING(x) ((x) << 1) +#define BANK_TILING(x) ((x) << 4) +#define GROUP_SIZE(x) ((x) << 6) +#define ROW_TILING(x) ((x) << 8) +#define BANK_SWAPS(x) ((x) << 11) +#define SAMPLE_SPLIT(x) ((x) << 14) +#define BACKEND_MAP(x) ((x) << 16) + +#define GB_TILING_CONFIG 0x98F0 + +#define GC_USER_SHADER_PIPE_CONFIG 0x8954 +#define INACTIVE_QD_PIPES(x) ((x) << 8) +#define INACTIVE_QD_PIPES_MASK 0x0000FF00 +#define INACTIVE_SIMDS(x) ((x) << 16) +#define INACTIVE_SIMDS_MASK 0x00FF0000 + +#define GRBM_CNTL 0x8000 +#define GRBM_READ_TIMEOUT(x) ((x) << 0) +#define GRBM_SOFT_RESET 0x8020 +#define SOFT_RESET_CP (1<<0) +#define GRBM_STATUS 0x8010 +#define CMDFIFO_AVAIL_MASK 0x0000000F +#define GUI_ACTIVE (1<<31) +#define GRBM_STATUS2 0x8014 + +#define HDP_HOST_PATH_CNTL 0x2C00 +#define HDP_NONSURFACE_BASE 0x2C04 +#define HDP_NONSURFACE_INFO 0x2C08 +#define HDP_NONSURFACE_SIZE 0x2C0C +#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 +#define HDP_TILING_CONFIG 0x2F3C + +#define MC_ARB_RAMCFG 0x2760 +#define NOOFBANK_SHIFT 0 +#define NOOFBANK_MASK 0x00000003 +#define NOOFRANK_SHIFT 2 +#define NOOFRANK_MASK 0x00000004 +#define NOOFROWS_SHIFT 3 +#define NOOFROWS_MASK 0x00000038 +#define NOOFCOLS_SHIFT 6 +#define NOOFCOLS_MASK 0x000000C0 +#define CHANSIZE_SHIFT 8 +#define CHANSIZE_MASK 0x00000100 +#define BURSTLENGTH_SHIFT 9 +#define BURSTLENGTH_MASK 0x00000200 +#define MC_VM_AGP_TOP 0x2028 +#define MC_VM_AGP_BOT 0x202C +#define MC_VM_AGP_BASE 0x2030 +#define MC_VM_FB_LOCATION 0x2024 +#define MC_VM_MB_L1_TLB0_CNTL 0x2234 +#define MC_VM_MB_L1_TLB1_CNTL 0x2238 +#define MC_VM_MB_L1_TLB2_CNTL 0x223C +#define MC_VM_MB_L1_TLB3_CNTL 0x2240 +#define ENABLE_L1_TLB (1 << 0) +#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) +#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) +#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) +#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) +#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) +#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) +#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) +#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) +#define MC_VM_MD_L1_TLB0_CNTL 0x2654 +#define MC_VM_MD_L1_TLB1_CNTL 0x2658 +#define MC_VM_MD_L1_TLB2_CNTL 0x265C +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 + +#define PA_CL_ENHANCE 0x8A14 +#define CLIP_VTX_REORDER_ENA (1 << 0) +#define NUM_CLIP_SEQ(x) ((x) << 1) +#define PA_SC_AA_CONFIG 0x28C04 +#define PA_SC_CLIPRECT_RULE 0x2820C +#define PA_SC_EDGERULE 0x28230 +#define PA_SC_FIFO_SIZE 0x8BCC +#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) +#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) +#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 +#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) +#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) +#define PA_SC_LINE_STIPPLE 0x28A0C +#define PA_SC_LINE_STIPPLE_STATE 0x8B10 +#define PA_SC_MODE_CNTL 0x28A4C +#define PA_SC_MULTI_CHIP_CNTL 0x8B20 +#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) + +#define SCRATCH_REG0 0x8500 +#define SCRATCH_REG1 0x8504 +#define SCRATCH_REG2 0x8508 +#define SCRATCH_REG3 0x850C +#define SCRATCH_REG4 0x8510 +#define SCRATCH_REG5 0x8514 +#define SCRATCH_REG6 0x8518 +#define SCRATCH_REG7 0x851C +#define SCRATCH_UMSK 0x8540 +#define SCRATCH_ADDR 0x8544 + +#define SMX_DC_CTL0 0xA020 +#define USE_HASH_FUNCTION (1 << 0) +#define CACHE_DEPTH(x) ((x) << 1) +#define FLUSH_ALL_ON_EVENT (1 << 10) +#define STALL_ON_EVENT (1 << 11) +#define SMX_EVENT_CTL 0xA02C +#define ES_FLUSH_CTL(x) ((x) << 0) +#define GS_FLUSH_CTL(x) ((x) << 3) +#define ACK_FLUSH_CTL(x) ((x) << 6) +#define SYNC_FLUSH_CTL (1 << 8) + +#define SPI_CONFIG_CNTL 0x9100 +#define GPR_WRITE_PRIORITY(x) ((x) << 0) +#define DISABLE_INTERP_1 (1 << 5) +#define SPI_CONFIG_CNTL_1 0x913C +#define VTX_DONE_DELAY(x) ((x) << 0) +#define INTERP_ONE_PRIM_PER_ROW (1 << 4) +#define SPI_INPUT_Z 0x286D8 +#define SPI_PS_IN_CONTROL_0 0x286CC +#define NUM_INTERP(x) ((x)<<0) +#define POSITION_ENA (1<<8) +#define POSITION_CENTROID (1<<9) +#define POSITION_ADDR(x) ((x)<<10) +#define PARAM_GEN(x) ((x)<<15) +#define PARAM_GEN_ADDR(x) ((x)<<19) +#define BARYC_SAMPLE_CNTL(x) ((x)<<26) +#define PERSP_GRADIENT_ENA (1<<28) +#define LINEAR_GRADIENT_ENA (1<<29) +#define POSITION_SAMPLE (1<<30) +#define BARYC_AT_SAMPLE_ENA (1<<31) + +#define SQ_CONFIG 0x8C00 +#define VC_ENABLE (1 << 0) +#define EXPORT_SRC_C (1 << 1) +#define DX9_CONSTS (1 << 2) +#define ALU_INST_PREFER_VECTOR (1 << 3) +#define DX10_CLAMP (1 << 4) +#define CLAUSE_SEQ_PRIO(x) ((x) << 8) +#define PS_PRIO(x) ((x) << 24) +#define VS_PRIO(x) ((x) << 26) +#define GS_PRIO(x) ((x) << 28) +#define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0 +#define SIMDA_RING0(x) ((x)<<0) +#define SIMDA_RING1(x) ((x)<<8) +#define SIMDB_RING0(x) ((x)<<16) +#define SIMDB_RING1(x) ((x)<<24) +#define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4 +#define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8 +#define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC +#define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0 +#define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4 +#define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8 +#define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC +#define ES_PRIO(x) ((x) << 30) +#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 +#define NUM_PS_GPRS(x) ((x) << 0) +#define NUM_VS_GPRS(x) ((x) << 16) +#define DYN_GPR_ENABLE (1 << 27) +#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) +#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 +#define NUM_GS_GPRS(x) ((x) << 0) +#define NUM_ES_GPRS(x) ((x) << 16) +#define SQ_MS_FIFO_SIZES 0x8CF0 +#define CACHE_FIFO_SIZE(x) ((x) << 0) +#define FETCH_FIFO_HIWATER(x) ((x) << 8) +#define DONE_FIFO_HIWATER(x) ((x) << 16) +#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) +#define SQ_STACK_RESOURCE_MGMT_1 0x8C10 +#define NUM_PS_STACK_ENTRIES(x) ((x) << 0) +#define NUM_VS_STACK_ENTRIES(x) ((x) << 16) +#define SQ_STACK_RESOURCE_MGMT_2 0x8C14 +#define NUM_GS_STACK_ENTRIES(x) ((x) << 0) +#define NUM_ES_STACK_ENTRIES(x) ((x) << 16) +#define SQ_THREAD_RESOURCE_MGMT 0x8C0C +#define NUM_PS_THREADS(x) ((x) << 0) +#define NUM_VS_THREADS(x) ((x) << 8) +#define NUM_GS_THREADS(x) ((x) << 16) +#define NUM_ES_THREADS(x) ((x) << 24) + +#define SX_DEBUG_1 0x9058 +#define ENABLE_NEW_SMX_ADDRESS (1 << 16) +#define SX_EXPORT_BUFFER_SIZES 0x900C +#define COLOR_BUFFER_SIZE(x) ((x) << 0) +#define POSITION_BUFFER_SIZE(x) ((x) << 8) +#define SMX_BUFFER_SIZE(x) ((x) << 16) +#define SX_MISC 0x28350 + +#define TA_CNTL_AUX 0x9508 +#define DISABLE_CUBE_WRAP (1 << 0) +#define DISABLE_CUBE_ANISO (1 << 1) +#define SYNC_GRADIENT (1 << 24) +#define SYNC_WALKER (1 << 25) +#define SYNC_ALIGNER (1 << 26) +#define BILINEAR_PRECISION_6_BIT (0 << 31) +#define BILINEAR_PRECISION_8_BIT (1 << 31) + +#define TCP_CNTL 0x9610 + +#define VGT_CACHE_INVALIDATION 0x88C4 +#define CACHE_INVALIDATION(x) ((x)<<0) +#define VC_ONLY 0 +#define TC_ONLY 1 +#define VC_AND_TC 2 +#define AUTO_INVLD_EN(x) ((x) << 6) +#define NO_AUTO 0 +#define ES_AUTO 1 +#define GS_AUTO 2 +#define ES_AND_GS_AUTO 3 +#define VGT_ES_PER_GS 0x88CC +#define VGT_GS_PER_ES 0x88C8 +#define VGT_GS_PER_VS 0x88E8 +#define VGT_GS_VERTEX_REUSE 0x88D4 +#define VGT_NUM_INSTANCES 0x8974 +#define VGT_OUT_DEALLOC_CNTL 0x28C5C +#define DEALLOC_DIST_MASK 0x0000007F +#define VGT_STRMOUT_EN 0x28AB0 +#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 +#define VTX_REUSE_DEPTH_MASK 0x000000FF + +#define VM_CONTEXT0_CNTL 0x1410 +#define ENABLE_CONTEXT (1 << 0) +#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) +#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 +#define VM_L2_CNTL 0x1400 +#define ENABLE_L2_CACHE (1 << 0) +#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) +#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) +#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) +#define VM_L2_CNTL2 0x1404 +#define INVALIDATE_ALL_L1_TLBS (1 << 0) +#define INVALIDATE_L2_CACHE (1 << 1) +#define VM_L2_CNTL3 0x1408 +#define BANK_SELECT(x) ((x) << 0) +#define CACHE_UPDATE_MODE(x) ((x) << 6) +#define VM_L2_STATUS 0x140C +#define L2_BUSY (1 << 0) + +#define WAIT_UNTIL 0x8040 + +#endif diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index c2b0d710d10f..87c06252d464 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -44,6 +44,39 @@ static int ttm_bo_setup_vm(struct ttm_buffer_object *bo); static int ttm_bo_swapout(struct ttm_mem_shrink *shrink); +static void ttm_bo_global_kobj_release(struct kobject *kobj); + +static struct attribute ttm_bo_count = { + .name = "bo_count", + .mode = S_IRUGO +}; + +static ssize_t ttm_bo_global_show(struct kobject *kobj, + struct attribute *attr, + char *buffer) +{ + struct ttm_bo_global *glob = + container_of(kobj, struct ttm_bo_global, kobj); + + return snprintf(buffer, PAGE_SIZE, "%lu\n", + (unsigned long) atomic_read(&glob->bo_count)); +} + +static struct attribute *ttm_bo_global_attrs[] = { + &ttm_bo_count, + NULL +}; + +static struct sysfs_ops ttm_bo_global_ops = { + .show = &ttm_bo_global_show +}; + +static struct kobj_type ttm_bo_glob_kobj_type = { + .release = &ttm_bo_global_kobj_release, + .sysfs_ops = &ttm_bo_global_ops, + .default_attrs = ttm_bo_global_attrs +}; + static inline uint32_t ttm_bo_type_flags(unsigned type) { @@ -66,10 +99,11 @@ static void ttm_bo_release_list(struct kref *list_kref) if (bo->ttm) ttm_tt_destroy(bo->ttm); + atomic_dec(&bo->glob->bo_count); if (bo->destroy) bo->destroy(bo); else { - ttm_mem_global_free(bdev->mem_glob, bo->acc_size, false); + ttm_mem_global_free(bdev->glob->mem_glob, bo->acc_size); kfree(bo); } } @@ -106,7 +140,7 @@ static void ttm_bo_add_to_lru(struct ttm_buffer_object *bo) kref_get(&bo->list_kref); if (bo->ttm != NULL) { - list_add_tail(&bo->swap, &bdev->swap_lru); + list_add_tail(&bo->swap, &bo->glob->swap_lru); kref_get(&bo->list_kref); } } @@ -141,7 +175,7 @@ int ttm_bo_reserve_locked(struct ttm_buffer_object *bo, bool interruptible, bool no_wait, bool use_sequence, uint32_t sequence) { - struct ttm_bo_device *bdev = bo->bdev; + struct ttm_bo_global *glob = bo->glob; int ret; while (unlikely(atomic_cmpxchg(&bo->reserved, 0, 1) != 0)) { @@ -153,9 +187,9 @@ int ttm_bo_reserve_locked(struct ttm_buffer_object *bo, if (no_wait) return -EBUSY; - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); ret = ttm_bo_wait_unreserved(bo, interruptible); - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); if (unlikely(ret)) return ret; @@ -181,16 +215,16 @@ int ttm_bo_reserve(struct ttm_buffer_object *bo, bool interruptible, bool no_wait, bool use_sequence, uint32_t sequence) { - struct ttm_bo_device *bdev = bo->bdev; + struct ttm_bo_global *glob = bo->glob; int put_count = 0; int ret; - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); ret = ttm_bo_reserve_locked(bo, interruptible, no_wait, use_sequence, sequence); if (likely(ret == 0)) put_count = ttm_bo_del_from_lru(bo); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); while (put_count--) kref_put(&bo->list_kref, ttm_bo_ref_bug); @@ -200,13 +234,13 @@ int ttm_bo_reserve(struct ttm_buffer_object *bo, void ttm_bo_unreserve(struct ttm_buffer_object *bo) { - struct ttm_bo_device *bdev = bo->bdev; + struct ttm_bo_global *glob = bo->glob; - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); ttm_bo_add_to_lru(bo); atomic_set(&bo->reserved, 0); wake_up_all(&bo->event_queue); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); } EXPORT_SYMBOL(ttm_bo_unreserve); @@ -217,6 +251,7 @@ EXPORT_SYMBOL(ttm_bo_unreserve); static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc) { struct ttm_bo_device *bdev = bo->bdev; + struct ttm_bo_global *glob = bo->glob; int ret = 0; uint32_t page_flags = 0; @@ -232,14 +267,14 @@ static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc) page_flags |= TTM_PAGE_FLAG_ZERO_ALLOC; case ttm_bo_type_kernel: bo->ttm = ttm_tt_create(bdev, bo->num_pages << PAGE_SHIFT, - page_flags, bdev->dummy_read_page); + page_flags, glob->dummy_read_page); if (unlikely(bo->ttm == NULL)) ret = -ENOMEM; break; case ttm_bo_type_user: bo->ttm = ttm_tt_create(bdev, bo->num_pages << PAGE_SHIFT, page_flags | TTM_PAGE_FLAG_USER, - bdev->dummy_read_page); + glob->dummy_read_page); if (unlikely(bo->ttm == NULL)) ret = -ENOMEM; break; @@ -360,6 +395,7 @@ out_err: static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) { struct ttm_bo_device *bdev = bo->bdev; + struct ttm_bo_global *glob = bo->glob; struct ttm_bo_driver *driver = bdev->driver; int ret; @@ -371,7 +407,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) spin_unlock(&bo->lock); - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); ret = ttm_bo_reserve_locked(bo, false, false, false, 0); BUG_ON(ret); if (bo->ttm) @@ -386,7 +422,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) bo->mem.mm_node = NULL; } put_count = ttm_bo_del_from_lru(bo); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); atomic_set(&bo->reserved, 0); @@ -396,14 +432,14 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) return 0; } - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); if (list_empty(&bo->ddestroy)) { void *sync_obj = bo->sync_obj; void *sync_obj_arg = bo->sync_obj_arg; kref_get(&bo->list_kref); list_add_tail(&bo->ddestroy, &bdev->ddestroy); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); spin_unlock(&bo->lock); if (sync_obj) @@ -413,7 +449,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) ret = 0; } else { - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); spin_unlock(&bo->lock); ret = -EBUSY; } @@ -428,11 +464,12 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) { + struct ttm_bo_global *glob = bdev->glob; struct ttm_buffer_object *entry, *nentry; struct list_head *list, *next; int ret; - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); list_for_each_safe(list, next, &bdev->ddestroy) { entry = list_entry(list, struct ttm_buffer_object, ddestroy); nentry = NULL; @@ -449,16 +486,16 @@ static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) } kref_get(&entry->list_kref); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); ret = ttm_bo_cleanup_refs(entry, remove_all); kref_put(&entry->list_kref, ttm_bo_release_list); - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); if (nentry) { bool next_onlist = !list_empty(next); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); kref_put(&nentry->list_kref, ttm_bo_release_list); - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); /* * Someone might have raced us and removed the * next entry from the list. We don't bother restarting @@ -472,7 +509,7 @@ static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) break; } ret = !list_empty(&bdev->ddestroy); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); return ret; } @@ -522,6 +559,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, unsigned mem_type, { int ret = 0; struct ttm_bo_device *bdev = bo->bdev; + struct ttm_bo_global *glob = bo->glob; struct ttm_mem_reg evict_mem; uint32_t proposed_placement; @@ -570,12 +608,12 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, unsigned mem_type, goto out; } - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); if (evict_mem.mm_node) { drm_mm_put_block(evict_mem.mm_node); evict_mem.mm_node = NULL; } - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); bo->evicted = true; out: return ret; @@ -590,6 +628,7 @@ static int ttm_bo_mem_force_space(struct ttm_bo_device *bdev, uint32_t mem_type, bool interruptible, bool no_wait) { + struct ttm_bo_global *glob = bdev->glob; struct drm_mm_node *node; struct ttm_buffer_object *entry; struct ttm_mem_type_manager *man = &bdev->man[mem_type]; @@ -603,7 +642,7 @@ retry_pre_get: if (unlikely(ret != 0)) return ret; - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); do { node = drm_mm_search_free(&man->manager, num_pages, mem->page_alignment, 1); @@ -624,7 +663,7 @@ retry_pre_get: if (likely(ret == 0)) put_count = ttm_bo_del_from_lru(entry); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); if (unlikely(ret != 0)) return ret; @@ -640,21 +679,21 @@ retry_pre_get: if (ret) return ret; - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); } while (1); if (!node) { - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); return -ENOMEM; } node = drm_mm_get_block_atomic(node, num_pages, mem->page_alignment); if (unlikely(!node)) { - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); goto retry_pre_get; } - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); mem->mm_node = node; mem->mem_type = mem_type; return 0; @@ -723,6 +762,7 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, bool interruptible, bool no_wait) { struct ttm_bo_device *bdev = bo->bdev; + struct ttm_bo_global *glob = bo->glob; struct ttm_mem_type_manager *man; uint32_t num_prios = bdev->driver->num_mem_type_prio; @@ -762,20 +802,20 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, if (unlikely(ret)) return ret; - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); node = drm_mm_search_free(&man->manager, mem->num_pages, mem->page_alignment, 1); if (unlikely(!node)) { - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); break; } node = drm_mm_get_block_atomic(node, mem->num_pages, mem-> page_alignment); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); } while (!node); } if (node) @@ -848,7 +888,7 @@ int ttm_bo_move_buffer(struct ttm_buffer_object *bo, uint32_t proposed_placement, bool interruptible, bool no_wait) { - struct ttm_bo_device *bdev = bo->bdev; + struct ttm_bo_global *glob = bo->glob; int ret = 0; struct ttm_mem_reg mem; @@ -884,9 +924,9 @@ int ttm_bo_move_buffer(struct ttm_buffer_object *bo, out_unlock: if (ret && mem.mm_node) { - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); drm_mm_put_block(mem.mm_node); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); } return ret; } @@ -1022,6 +1062,7 @@ int ttm_buffer_object_init(struct ttm_bo_device *bdev, INIT_LIST_HEAD(&bo->ddestroy); INIT_LIST_HEAD(&bo->swap); bo->bdev = bdev; + bo->glob = bdev->glob; bo->type = type; bo->num_pages = num_pages; bo->mem.mem_type = TTM_PL_SYSTEM; @@ -1034,6 +1075,7 @@ int ttm_buffer_object_init(struct ttm_bo_device *bdev, bo->seq_valid = false; bo->persistant_swap_storage = persistant_swap_storage; bo->acc_size = acc_size; + atomic_inc(&bo->glob->bo_count); ret = ttm_bo_check_placement(bo, flags, 0ULL); if (unlikely(ret != 0)) @@ -1072,13 +1114,13 @@ out_err: } EXPORT_SYMBOL(ttm_buffer_object_init); -static inline size_t ttm_bo_size(struct ttm_bo_device *bdev, +static inline size_t ttm_bo_size(struct ttm_bo_global *glob, unsigned long num_pages) { size_t page_array_size = (num_pages * sizeof(void *) + PAGE_SIZE - 1) & PAGE_MASK; - return bdev->ttm_bo_size + 2 * page_array_size; + return glob->ttm_bo_size + 2 * page_array_size; } int ttm_buffer_object_create(struct ttm_bo_device *bdev, @@ -1093,18 +1135,18 @@ int ttm_buffer_object_create(struct ttm_bo_device *bdev, { struct ttm_buffer_object *bo; int ret; - struct ttm_mem_global *mem_glob = bdev->mem_glob; + struct ttm_mem_global *mem_glob = bdev->glob->mem_glob; size_t acc_size = - ttm_bo_size(bdev, (size + PAGE_SIZE - 1) >> PAGE_SHIFT); - ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false, false); + ttm_bo_size(bdev->glob, (size + PAGE_SIZE - 1) >> PAGE_SHIFT); + ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false); if (unlikely(ret != 0)) return ret; bo = kzalloc(sizeof(*bo), GFP_KERNEL); if (unlikely(bo == NULL)) { - ttm_mem_global_free(mem_glob, acc_size, false); + ttm_mem_global_free(mem_glob, acc_size); return -ENOMEM; } @@ -1150,6 +1192,7 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev, struct list_head *head, unsigned mem_type, bool allow_errors) { + struct ttm_bo_global *glob = bdev->glob; struct ttm_buffer_object *entry; int ret; int put_count; @@ -1158,30 +1201,31 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev, * Can't use standard list traversal since we're unlocking. */ - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); while (!list_empty(head)) { entry = list_first_entry(head, struct ttm_buffer_object, lru); kref_get(&entry->list_kref); ret = ttm_bo_reserve_locked(entry, false, false, false, 0); put_count = ttm_bo_del_from_lru(entry); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); while (put_count--) kref_put(&entry->list_kref, ttm_bo_ref_bug); BUG_ON(ret); ret = ttm_bo_leave_list(entry, mem_type, allow_errors); ttm_bo_unreserve(entry); kref_put(&entry->list_kref, ttm_bo_release_list); - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); } - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); return 0; } int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type) { + struct ttm_bo_global *glob = bdev->glob; struct ttm_mem_type_manager *man; int ret = -EINVAL; @@ -1204,13 +1248,13 @@ int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type) if (mem_type > 0) { ttm_bo_force_list_clean(bdev, &man->lru, mem_type, false); - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); if (drm_mm_clean(&man->manager)) drm_mm_takedown(&man->manager); else ret = -EBUSY; - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); } return ret; @@ -1284,11 +1328,82 @@ int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned type, } EXPORT_SYMBOL(ttm_bo_init_mm); +static void ttm_bo_global_kobj_release(struct kobject *kobj) +{ + struct ttm_bo_global *glob = + container_of(kobj, struct ttm_bo_global, kobj); + + ttm_mem_unregister_shrink(glob->mem_glob, &glob->shrink); + __free_page(glob->dummy_read_page); + kfree(glob); +} + +void ttm_bo_global_release(struct ttm_global_reference *ref) +{ + struct ttm_bo_global *glob = ref->object; + + kobject_del(&glob->kobj); + kobject_put(&glob->kobj); +} +EXPORT_SYMBOL(ttm_bo_global_release); + +int ttm_bo_global_init(struct ttm_global_reference *ref) +{ + struct ttm_bo_global_ref *bo_ref = + container_of(ref, struct ttm_bo_global_ref, ref); + struct ttm_bo_global *glob = ref->object; + int ret; + + mutex_init(&glob->device_list_mutex); + spin_lock_init(&glob->lru_lock); + glob->mem_glob = bo_ref->mem_glob; + glob->dummy_read_page = alloc_page(__GFP_ZERO | GFP_DMA32); + + if (unlikely(glob->dummy_read_page == NULL)) { + ret = -ENOMEM; + goto out_no_drp; + } + + INIT_LIST_HEAD(&glob->swap_lru); + INIT_LIST_HEAD(&glob->device_list); + + ttm_mem_init_shrink(&glob->shrink, ttm_bo_swapout); + ret = ttm_mem_register_shrink(glob->mem_glob, &glob->shrink); + if (unlikely(ret != 0)) { + printk(KERN_ERR TTM_PFX + "Could not register buffer object swapout.\n"); + goto out_no_shrink; + } + + glob->ttm_bo_extra_size = + ttm_round_pot(sizeof(struct ttm_tt)) + + ttm_round_pot(sizeof(struct ttm_backend)); + + glob->ttm_bo_size = glob->ttm_bo_extra_size + + ttm_round_pot(sizeof(struct ttm_buffer_object)); + + atomic_set(&glob->bo_count, 0); + + kobject_init(&glob->kobj, &ttm_bo_glob_kobj_type); + ret = kobject_add(&glob->kobj, ttm_get_kobj(), "buffer_objects"); + if (unlikely(ret != 0)) + kobject_put(&glob->kobj); + return ret; +out_no_shrink: + __free_page(glob->dummy_read_page); +out_no_drp: + kfree(glob); + return ret; +} +EXPORT_SYMBOL(ttm_bo_global_init); + + int ttm_bo_device_release(struct ttm_bo_device *bdev) { int ret = 0; unsigned i = TTM_NUM_MEM_TYPES; struct ttm_mem_type_manager *man; + struct ttm_bo_global *glob = bdev->glob; while (i--) { man = &bdev->man[i]; @@ -1304,100 +1419,74 @@ int ttm_bo_device_release(struct ttm_bo_device *bdev) } } + mutex_lock(&glob->device_list_mutex); + list_del(&bdev->device_list); + mutex_unlock(&glob->device_list_mutex); + if (!cancel_delayed_work(&bdev->wq)) flush_scheduled_work(); while (ttm_bo_delayed_delete(bdev, true)) ; - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); if (list_empty(&bdev->ddestroy)) TTM_DEBUG("Delayed destroy list was clean\n"); if (list_empty(&bdev->man[0].lru)) TTM_DEBUG("Swap list was clean\n"); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); - ttm_mem_unregister_shrink(bdev->mem_glob, &bdev->shrink); BUG_ON(!drm_mm_clean(&bdev->addr_space_mm)); write_lock(&bdev->vm_lock); drm_mm_takedown(&bdev->addr_space_mm); write_unlock(&bdev->vm_lock); - __free_page(bdev->dummy_read_page); return ret; } EXPORT_SYMBOL(ttm_bo_device_release); -/* - * This function is intended to be called on drm driver load. - * If you decide to call it from firstopen, you must protect the call - * from a potentially racing ttm_bo_driver_finish in lastclose. - * (This may happen on X server restart). - */ - int ttm_bo_device_init(struct ttm_bo_device *bdev, - struct ttm_mem_global *mem_glob, - struct ttm_bo_driver *driver, uint64_t file_page_offset, + struct ttm_bo_global *glob, + struct ttm_bo_driver *driver, + uint64_t file_page_offset, bool need_dma32) { int ret = -EINVAL; - bdev->dummy_read_page = NULL; rwlock_init(&bdev->vm_lock); - spin_lock_init(&bdev->lru_lock); - bdev->driver = driver; - bdev->mem_glob = mem_glob; memset(bdev->man, 0, sizeof(bdev->man)); - bdev->dummy_read_page = alloc_page(__GFP_ZERO | GFP_DMA32); - if (unlikely(bdev->dummy_read_page == NULL)) { - ret = -ENOMEM; - goto out_err0; - } - /* * Initialize the system memory buffer type. * Other types need to be driver / IOCTL initialized. */ ret = ttm_bo_init_mm(bdev, TTM_PL_SYSTEM, 0, 0); if (unlikely(ret != 0)) - goto out_err1; + goto out_no_sys; bdev->addr_space_rb = RB_ROOT; ret = drm_mm_init(&bdev->addr_space_mm, file_page_offset, 0x10000000); if (unlikely(ret != 0)) - goto out_err2; + goto out_no_addr_mm; INIT_DELAYED_WORK(&bdev->wq, ttm_bo_delayed_workqueue); bdev->nice_mode = true; INIT_LIST_HEAD(&bdev->ddestroy); - INIT_LIST_HEAD(&bdev->swap_lru); bdev->dev_mapping = NULL; + bdev->glob = glob; bdev->need_dma32 = need_dma32; - ttm_mem_init_shrink(&bdev->shrink, ttm_bo_swapout); - ret = ttm_mem_register_shrink(mem_glob, &bdev->shrink); - if (unlikely(ret != 0)) { - printk(KERN_ERR TTM_PFX - "Could not register buffer object swapout.\n"); - goto out_err2; - } - bdev->ttm_bo_extra_size = - ttm_round_pot(sizeof(struct ttm_tt)) + - ttm_round_pot(sizeof(struct ttm_backend)); - - bdev->ttm_bo_size = bdev->ttm_bo_extra_size + - ttm_round_pot(sizeof(struct ttm_buffer_object)); + mutex_lock(&glob->device_list_mutex); + list_add_tail(&bdev->device_list, &glob->device_list); + mutex_unlock(&glob->device_list_mutex); return 0; -out_err2: +out_no_addr_mm: ttm_bo_clean_mm(bdev, 0); -out_err1: - __free_page(bdev->dummy_read_page); -out_err0: +out_no_sys: return ret; } EXPORT_SYMBOL(ttm_bo_device_init); @@ -1647,21 +1736,21 @@ void ttm_bo_synccpu_write_release(struct ttm_buffer_object *bo) static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) { - struct ttm_bo_device *bdev = - container_of(shrink, struct ttm_bo_device, shrink); + struct ttm_bo_global *glob = + container_of(shrink, struct ttm_bo_global, shrink); struct ttm_buffer_object *bo; int ret = -EBUSY; int put_count; uint32_t swap_placement = (TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM); - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); while (ret == -EBUSY) { - if (unlikely(list_empty(&bdev->swap_lru))) { - spin_unlock(&bdev->lru_lock); + if (unlikely(list_empty(&glob->swap_lru))) { + spin_unlock(&glob->lru_lock); return -EBUSY; } - bo = list_first_entry(&bdev->swap_lru, + bo = list_first_entry(&glob->swap_lru, struct ttm_buffer_object, swap); kref_get(&bo->list_kref); @@ -1673,16 +1762,16 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) ret = ttm_bo_reserve_locked(bo, false, true, false, 0); if (unlikely(ret == -EBUSY)) { - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); ttm_bo_wait_unreserved(bo, false); kref_put(&bo->list_kref, ttm_bo_release_list); - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); } } BUG_ON(ret != 0); put_count = ttm_bo_del_from_lru(bo); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); while (put_count--) kref_put(&bo->list_kref, ttm_bo_ref_bug); @@ -1736,6 +1825,6 @@ out: void ttm_bo_swapout_all(struct ttm_bo_device *bdev) { - while (ttm_bo_swapout(&bdev->shrink) == 0) + while (ttm_bo_swapout(&bdev->glob->shrink) == 0) ; } diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index ad4ada07c6cf..c70927ecda21 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -41,9 +41,9 @@ void ttm_bo_free_old_node(struct ttm_buffer_object *bo) struct ttm_mem_reg *old_mem = &bo->mem; if (old_mem->mm_node) { - spin_lock(&bo->bdev->lru_lock); + spin_lock(&bo->glob->lru_lock); drm_mm_put_block(old_mem->mm_node); - spin_unlock(&bo->bdev->lru_lock); + spin_unlock(&bo->glob->lru_lock); } old_mem->mm_node = NULL; } diff --git a/drivers/gpu/drm/ttm/ttm_global.c b/drivers/gpu/drm/ttm/ttm_global.c index 0b14eb1972b8..541744d00d3e 100644 --- a/drivers/gpu/drm/ttm/ttm_global.c +++ b/drivers/gpu/drm/ttm/ttm_global.c @@ -71,7 +71,7 @@ int ttm_global_item_ref(struct ttm_global_reference *ref) mutex_lock(&item->mutex); if (item->refcount == 0) { - item->object = kmalloc(ref->size, GFP_KERNEL); + item->object = kzalloc(ref->size, GFP_KERNEL); if (unlikely(item->object == NULL)) { ret = -ENOMEM; goto out_err; @@ -89,7 +89,6 @@ int ttm_global_item_ref(struct ttm_global_reference *ref) mutex_unlock(&item->mutex); return 0; out_err: - kfree(item->object); mutex_unlock(&item->mutex); item->object = NULL; return ret; @@ -105,7 +104,6 @@ void ttm_global_item_unref(struct ttm_global_reference *ref) BUG_ON(ref->object != item->object); if (--item->refcount == 0) { ref->release(ref); - kfree(item->object); item->object = NULL; } mutex_unlock(&item->mutex); diff --git a/drivers/gpu/drm/ttm/ttm_memory.c b/drivers/gpu/drm/ttm/ttm_memory.c index 87323d4ff68d..072c281a6bb5 100644 --- a/drivers/gpu/drm/ttm/ttm_memory.c +++ b/drivers/gpu/drm/ttm/ttm_memory.c @@ -26,15 +26,180 @@ **************************************************************************/ #include "ttm/ttm_memory.h" +#include "ttm/ttm_module.h" #include #include #include #include #include -#define TTM_PFX "[TTM] " #define TTM_MEMORY_ALLOC_RETRIES 4 +struct ttm_mem_zone { + struct kobject kobj; + struct ttm_mem_global *glob; + const char *name; + uint64_t zone_mem; + uint64_t emer_mem; + uint64_t max_mem; + uint64_t swap_limit; + uint64_t used_mem; +}; + +static struct attribute ttm_mem_sys = { + .name = "zone_memory", + .mode = S_IRUGO +}; +static struct attribute ttm_mem_emer = { + .name = "emergency_memory", + .mode = S_IRUGO | S_IWUSR +}; +static struct attribute ttm_mem_max = { + .name = "available_memory", + .mode = S_IRUGO | S_IWUSR +}; +static struct attribute ttm_mem_swap = { + .name = "swap_limit", + .mode = S_IRUGO | S_IWUSR +}; +static struct attribute ttm_mem_used = { + .name = "used_memory", + .mode = S_IRUGO +}; + +static void ttm_mem_zone_kobj_release(struct kobject *kobj) +{ + struct ttm_mem_zone *zone = + container_of(kobj, struct ttm_mem_zone, kobj); + + printk(KERN_INFO TTM_PFX + "Zone %7s: Used memory at exit: %llu kiB.\n", + zone->name, (unsigned long long) zone->used_mem >> 10); + kfree(zone); +} + +static ssize_t ttm_mem_zone_show(struct kobject *kobj, + struct attribute *attr, + char *buffer) +{ + struct ttm_mem_zone *zone = + container_of(kobj, struct ttm_mem_zone, kobj); + uint64_t val = 0; + + spin_lock(&zone->glob->lock); + if (attr == &ttm_mem_sys) + val = zone->zone_mem; + else if (attr == &ttm_mem_emer) + val = zone->emer_mem; + else if (attr == &ttm_mem_max) + val = zone->max_mem; + else if (attr == &ttm_mem_swap) + val = zone->swap_limit; + else if (attr == &ttm_mem_used) + val = zone->used_mem; + spin_unlock(&zone->glob->lock); + + return snprintf(buffer, PAGE_SIZE, "%llu\n", + (unsigned long long) val >> 10); +} + +static void ttm_check_swapping(struct ttm_mem_global *glob); + +static ssize_t ttm_mem_zone_store(struct kobject *kobj, + struct attribute *attr, + const char *buffer, + size_t size) +{ + struct ttm_mem_zone *zone = + container_of(kobj, struct ttm_mem_zone, kobj); + int chars; + unsigned long val; + uint64_t val64; + + chars = sscanf(buffer, "%lu", &val); + if (chars == 0) + return size; + + val64 = val; + val64 <<= 10; + + spin_lock(&zone->glob->lock); + if (val64 > zone->zone_mem) + val64 = zone->zone_mem; + if (attr == &ttm_mem_emer) { + zone->emer_mem = val64; + if (zone->max_mem > val64) + zone->max_mem = val64; + } else if (attr == &ttm_mem_max) { + zone->max_mem = val64; + if (zone->emer_mem < val64) + zone->emer_mem = val64; + } else if (attr == &ttm_mem_swap) + zone->swap_limit = val64; + spin_unlock(&zone->glob->lock); + + ttm_check_swapping(zone->glob); + + return size; +} + +static struct attribute *ttm_mem_zone_attrs[] = { + &ttm_mem_sys, + &ttm_mem_emer, + &ttm_mem_max, + &ttm_mem_swap, + &ttm_mem_used, + NULL +}; + +static struct sysfs_ops ttm_mem_zone_ops = { + .show = &ttm_mem_zone_show, + .store = &ttm_mem_zone_store +}; + +static struct kobj_type ttm_mem_zone_kobj_type = { + .release = &ttm_mem_zone_kobj_release, + .sysfs_ops = &ttm_mem_zone_ops, + .default_attrs = ttm_mem_zone_attrs, +}; + +static void ttm_mem_global_kobj_release(struct kobject *kobj) +{ + struct ttm_mem_global *glob = + container_of(kobj, struct ttm_mem_global, kobj); + + kfree(glob); +} + +static struct kobj_type ttm_mem_glob_kobj_type = { + .release = &ttm_mem_global_kobj_release, +}; + +static bool ttm_zones_above_swap_target(struct ttm_mem_global *glob, + bool from_wq, uint64_t extra) +{ + unsigned int i; + struct ttm_mem_zone *zone; + uint64_t target; + + for (i = 0; i < glob->num_zones; ++i) { + zone = glob->zones[i]; + + if (from_wq) + target = zone->swap_limit; + else if (capable(CAP_SYS_ADMIN)) + target = zone->emer_mem; + else + target = zone->max_mem; + + target = (extra > target) ? 0ULL : target; + + if (zone->used_mem > target) + return true; + } + return false; +} + /** * At this point we only support a single shrink callback. * Extend this if needed, perhaps using a linked list of callbacks. @@ -42,34 +207,17 @@ * many threads may try to swap out at any given time. */ -static void ttm_shrink(struct ttm_mem_global *glob, bool from_workqueue, +static void ttm_shrink(struct ttm_mem_global *glob, bool from_wq, uint64_t extra) { int ret; struct ttm_mem_shrink *shrink; - uint64_t target; - uint64_t total_target; spin_lock(&glob->lock); if (glob->shrink == NULL) goto out; - if (from_workqueue) { - target = glob->swap_limit; - total_target = glob->total_memory_swap_limit; - } else if (capable(CAP_SYS_ADMIN)) { - total_target = glob->emer_total_memory; - target = glob->emer_memory; - } else { - total_target = glob->max_total_memory; - target = glob->max_memory; - } - - total_target = (extra >= total_target) ? 0 : total_target - extra; - target = (extra >= target) ? 0 : target - extra; - - while (glob->used_memory > target || - glob->used_total_memory > total_target) { + while (ttm_zones_above_swap_target(glob, from_wq, extra)) { shrink = glob->shrink; spin_unlock(&glob->lock); ret = shrink->do_shrink(shrink); @@ -81,6 +229,8 @@ out: spin_unlock(&glob->lock); } + + static void ttm_shrink_work(struct work_struct *work) { struct ttm_mem_global *glob = @@ -89,63 +239,198 @@ static void ttm_shrink_work(struct work_struct *work) ttm_shrink(glob, true, 0ULL); } +static int ttm_mem_init_kernel_zone(struct ttm_mem_global *glob, + const struct sysinfo *si) +{ + struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL); + uint64_t mem; + int ret; + + if (unlikely(!zone)) + return -ENOMEM; + + mem = si->totalram - si->totalhigh; + mem *= si->mem_unit; + + zone->name = "kernel"; + zone->zone_mem = mem; + zone->max_mem = mem >> 1; + zone->emer_mem = (mem >> 1) + (mem >> 2); + zone->swap_limit = zone->max_mem - (mem >> 3); + zone->used_mem = 0; + zone->glob = glob; + glob->zone_kernel = zone; + kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type); + ret = kobject_add(&zone->kobj, &glob->kobj, zone->name); + if (unlikely(ret != 0)) { + kobject_put(&zone->kobj); + return ret; + } + glob->zones[glob->num_zones++] = zone; + return 0; +} + +#ifdef CONFIG_HIGHMEM +static int ttm_mem_init_highmem_zone(struct ttm_mem_global *glob, + const struct sysinfo *si) +{ + struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL); + uint64_t mem; + int ret; + + if (unlikely(!zone)) + return -ENOMEM; + + if (si->totalhigh == 0) + return 0; + + mem = si->totalram; + mem *= si->mem_unit; + + zone->name = "highmem"; + zone->zone_mem = mem; + zone->max_mem = mem >> 1; + zone->emer_mem = (mem >> 1) + (mem >> 2); + zone->swap_limit = zone->max_mem - (mem >> 3); + zone->used_mem = 0; + zone->glob = glob; + glob->zone_highmem = zone; + kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type); + ret = kobject_add(&zone->kobj, &glob->kobj, zone->name); + if (unlikely(ret != 0)) { + kobject_put(&zone->kobj); + return ret; + } + glob->zones[glob->num_zones++] = zone; + return 0; +} +#else +static int ttm_mem_init_dma32_zone(struct ttm_mem_global *glob, + const struct sysinfo *si) +{ + struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL); + uint64_t mem; + int ret; + + if (unlikely(!zone)) + return -ENOMEM; + + mem = si->totalram; + mem *= si->mem_unit; + + /** + * No special dma32 zone needed. + */ + + if (mem <= ((uint64_t) 1ULL << 32)) + return 0; + + /* + * Limit max dma32 memory to 4GB for now + * until we can figure out how big this + * zone really is. + */ + + mem = ((uint64_t) 1ULL << 32); + zone->name = "dma32"; + zone->zone_mem = mem; + zone->max_mem = mem >> 1; + zone->emer_mem = (mem >> 1) + (mem >> 2); + zone->swap_limit = zone->max_mem - (mem >> 3); + zone->used_mem = 0; + zone->glob = glob; + glob->zone_dma32 = zone; + kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type); + ret = kobject_add(&zone->kobj, &glob->kobj, zone->name); + if (unlikely(ret != 0)) { + kobject_put(&zone->kobj); + return ret; + } + glob->zones[glob->num_zones++] = zone; + return 0; +} +#endif + int ttm_mem_global_init(struct ttm_mem_global *glob) { struct sysinfo si; - uint64_t mem; + int ret; + int i; + struct ttm_mem_zone *zone; spin_lock_init(&glob->lock); glob->swap_queue = create_singlethread_workqueue("ttm_swap"); INIT_WORK(&glob->work, ttm_shrink_work); init_waitqueue_head(&glob->queue); + kobject_init(&glob->kobj, &ttm_mem_glob_kobj_type); + ret = kobject_add(&glob->kobj, + ttm_get_kobj(), + "memory_accounting"); + if (unlikely(ret != 0)) { + kobject_put(&glob->kobj); + return ret; + } si_meminfo(&si); - mem = si.totalram - si.totalhigh; - mem *= si.mem_unit; - - glob->max_memory = mem >> 1; - glob->emer_memory = (mem >> 1) + (mem >> 2); - glob->swap_limit = glob->max_memory - (mem >> 3); - glob->used_memory = 0; - glob->used_total_memory = 0; - glob->shrink = NULL; - - mem = si.totalram; - mem *= si.mem_unit; - - glob->max_total_memory = mem >> 1; - glob->emer_total_memory = (mem >> 1) + (mem >> 2); - - glob->total_memory_swap_limit = glob->max_total_memory - (mem >> 3); - - printk(KERN_INFO TTM_PFX "TTM available graphics memory: %llu MiB\n", - glob->max_total_memory >> 20); - printk(KERN_INFO TTM_PFX "TTM available object memory: %llu MiB\n", - glob->max_memory >> 20); - + ret = ttm_mem_init_kernel_zone(glob, &si); + if (unlikely(ret != 0)) + goto out_no_zone; +#ifdef CONFIG_HIGHMEM + ret = ttm_mem_init_highmem_zone(glob, &si); + if (unlikely(ret != 0)) + goto out_no_zone; +#else + ret = ttm_mem_init_dma32_zone(glob, &si); + if (unlikely(ret != 0)) + goto out_no_zone; +#endif + for (i = 0; i < glob->num_zones; ++i) { + zone = glob->zones[i]; + printk(KERN_INFO TTM_PFX + "Zone %7s: Available graphics memory: %llu kiB.\n", + zone->name, (unsigned long long) zone->max_mem >> 10); + } return 0; +out_no_zone: + ttm_mem_global_release(glob); + return ret; } EXPORT_SYMBOL(ttm_mem_global_init); void ttm_mem_global_release(struct ttm_mem_global *glob) { - printk(KERN_INFO TTM_PFX "Used total memory is %llu bytes.\n", - (unsigned long long)glob->used_total_memory); + unsigned int i; + struct ttm_mem_zone *zone; + flush_workqueue(glob->swap_queue); destroy_workqueue(glob->swap_queue); glob->swap_queue = NULL; + for (i = 0; i < glob->num_zones; ++i) { + zone = glob->zones[i]; + kobject_del(&zone->kobj); + kobject_put(&zone->kobj); + } + kobject_del(&glob->kobj); + kobject_put(&glob->kobj); } EXPORT_SYMBOL(ttm_mem_global_release); -static inline void ttm_check_swapping(struct ttm_mem_global *glob) +static void ttm_check_swapping(struct ttm_mem_global *glob) { - bool needs_swapping; + bool needs_swapping = false; + unsigned int i; + struct ttm_mem_zone *zone; spin_lock(&glob->lock); - needs_swapping = (glob->used_memory > glob->swap_limit || - glob->used_total_memory > - glob->total_memory_swap_limit); + for (i = 0; i < glob->num_zones; ++i) { + zone = glob->zones[i]; + if (zone->used_mem > zone->swap_limit) { + needs_swapping = true; + break; + } + } + spin_unlock(&glob->lock); if (unlikely(needs_swapping)) @@ -153,44 +438,60 @@ static inline void ttm_check_swapping(struct ttm_mem_global *glob) } -void ttm_mem_global_free(struct ttm_mem_global *glob, - uint64_t amount, bool himem) +static void ttm_mem_global_free_zone(struct ttm_mem_global *glob, + struct ttm_mem_zone *single_zone, + uint64_t amount) { + unsigned int i; + struct ttm_mem_zone *zone; + spin_lock(&glob->lock); - glob->used_total_memory -= amount; - if (!himem) - glob->used_memory -= amount; - wake_up_all(&glob->queue); + for (i = 0; i < glob->num_zones; ++i) { + zone = glob->zones[i]; + if (single_zone && zone != single_zone) + continue; + zone->used_mem -= amount; + } spin_unlock(&glob->lock); } +void ttm_mem_global_free(struct ttm_mem_global *glob, + uint64_t amount) +{ + return ttm_mem_global_free_zone(glob, NULL, amount); +} + static int ttm_mem_global_reserve(struct ttm_mem_global *glob, - uint64_t amount, bool himem, bool reserve) + struct ttm_mem_zone *single_zone, + uint64_t amount, bool reserve) { uint64_t limit; - uint64_t lomem_limit; int ret = -ENOMEM; + unsigned int i; + struct ttm_mem_zone *zone; spin_lock(&glob->lock); + for (i = 0; i < glob->num_zones; ++i) { + zone = glob->zones[i]; + if (single_zone && zone != single_zone) + continue; - if (capable(CAP_SYS_ADMIN)) { - limit = glob->emer_total_memory; - lomem_limit = glob->emer_memory; - } else { - limit = glob->max_total_memory; - lomem_limit = glob->max_memory; - } + limit = (capable(CAP_SYS_ADMIN)) ? + zone->emer_mem : zone->max_mem; - if (unlikely(glob->used_total_memory + amount > limit)) - goto out_unlock; - if (unlikely(!himem && glob->used_memory + amount > lomem_limit)) - goto out_unlock; + if (zone->used_mem > limit) + goto out_unlock; + } if (reserve) { - glob->used_total_memory += amount; - if (!himem) - glob->used_memory += amount; + for (i = 0; i < glob->num_zones; ++i) { + zone = glob->zones[i]; + if (single_zone && zone != single_zone) + continue; + zone->used_mem += amount; + } } + ret = 0; out_unlock: spin_unlock(&glob->lock); @@ -199,12 +500,17 @@ out_unlock: return ret; } -int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory, - bool no_wait, bool interruptible, bool himem) + +static int ttm_mem_global_alloc_zone(struct ttm_mem_global *glob, + struct ttm_mem_zone *single_zone, + uint64_t memory, + bool no_wait, bool interruptible) { int count = TTM_MEMORY_ALLOC_RETRIES; - while (unlikely(ttm_mem_global_reserve(glob, memory, himem, true) + while (unlikely(ttm_mem_global_reserve(glob, + single_zone, + memory, true) != 0)) { if (no_wait) return -ENOMEM; @@ -216,6 +522,56 @@ int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory, return 0; } +int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory, + bool no_wait, bool interruptible) +{ + /** + * Normal allocations of kernel memory are registered in + * all zones. + */ + + return ttm_mem_global_alloc_zone(glob, NULL, memory, no_wait, + interruptible); +} + +int ttm_mem_global_alloc_page(struct ttm_mem_global *glob, + struct page *page, + bool no_wait, bool interruptible) +{ + + struct ttm_mem_zone *zone = NULL; + + /** + * Page allocations may be registed in a single zone + * only if highmem or !dma32. + */ + +#ifdef CONFIG_HIGHMEM + if (PageHighMem(page) && glob->zone_highmem != NULL) + zone = glob->zone_highmem; +#else + if (glob->zone_dma32 && page_to_pfn(page) > 0x00100000UL) + zone = glob->zone_kernel; +#endif + return ttm_mem_global_alloc_zone(glob, zone, PAGE_SIZE, no_wait, + interruptible); +} + +void ttm_mem_global_free_page(struct ttm_mem_global *glob, struct page *page) +{ + struct ttm_mem_zone *zone = NULL; + +#ifdef CONFIG_HIGHMEM + if (PageHighMem(page) && glob->zone_highmem != NULL) + zone = glob->zone_highmem; +#else + if (glob->zone_dma32 && page_to_pfn(page) > 0x00100000UL) + zone = glob->zone_kernel; +#endif + ttm_mem_global_free_zone(glob, zone, PAGE_SIZE); +} + + size_t ttm_round_pot(size_t size) { if ((size & (size - 1)) == 0) diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c index 59ce8191d584..9a6edbfeaa9e 100644 --- a/drivers/gpu/drm/ttm/ttm_module.c +++ b/drivers/gpu/drm/ttm/ttm_module.c @@ -29,16 +29,72 @@ * Jerome Glisse */ #include -#include +#include +#include +#include "ttm/ttm_module.h" +#include "drm_sysfs.h" + +static DECLARE_WAIT_QUEUE_HEAD(exit_q); +atomic_t device_released; + +static struct device_type ttm_drm_class_type = { + .name = "ttm", + /** + * Add pm ops here. + */ +}; + +static void ttm_drm_class_device_release(struct device *dev) +{ + atomic_set(&device_released, 1); + wake_up_all(&exit_q); +} + +static struct device ttm_drm_class_device = { + .type = &ttm_drm_class_type, + .release = &ttm_drm_class_device_release +}; + +struct kobject *ttm_get_kobj(void) +{ + struct kobject *kobj = &ttm_drm_class_device.kobj; + BUG_ON(kobj == NULL); + return kobj; +} static int __init ttm_init(void) { + int ret; + + ret = dev_set_name(&ttm_drm_class_device, "ttm"); + if (unlikely(ret != 0)) + return ret; + ttm_global_init(); + + atomic_set(&device_released, 0); + ret = drm_class_device_register(&ttm_drm_class_device); + if (unlikely(ret != 0)) + goto out_no_dev_reg; + return 0; +out_no_dev_reg: + atomic_set(&device_released, 1); + wake_up_all(&exit_q); + ttm_global_release(); + return ret; } static void __exit ttm_exit(void) { + drm_class_device_unregister(&ttm_drm_class_device); + + /** + * Refuse to unload until the TTM device is released. + * Not sure this is 100% needed. + */ + + wait_event(exit_q, atomic_read(&device_released) == 1); ttm_global_release(); } diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index b8b6c4a5f983..a55ee1a56c16 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -34,76 +34,13 @@ #include #include #include +#include "drm_cache.h" #include "ttm/ttm_module.h" #include "ttm/ttm_bo_driver.h" #include "ttm/ttm_placement.h" static int ttm_tt_swapin(struct ttm_tt *ttm); -#if defined(CONFIG_X86) -static void ttm_tt_clflush_page(struct page *page) -{ - uint8_t *page_virtual; - unsigned int i; - - if (unlikely(page == NULL)) - return; - - page_virtual = kmap_atomic(page, KM_USER0); - - for (i = 0; i < PAGE_SIZE; i += boot_cpu_data.x86_clflush_size) - clflush(page_virtual + i); - - kunmap_atomic(page_virtual, KM_USER0); -} - -static void ttm_tt_cache_flush_clflush(struct page *pages[], - unsigned long num_pages) -{ - unsigned long i; - - mb(); - for (i = 0; i < num_pages; ++i) - ttm_tt_clflush_page(*pages++); - mb(); -} -#elif !defined(__powerpc__) -static void ttm_tt_ipi_handler(void *null) -{ - ; -} -#endif - -void ttm_tt_cache_flush(struct page *pages[], unsigned long num_pages) -{ - -#if defined(CONFIG_X86) - if (cpu_has_clflush) { - ttm_tt_cache_flush_clflush(pages, num_pages); - return; - } -#elif defined(__powerpc__) - unsigned long i; - - for (i = 0; i < num_pages; ++i) { - struct page *page = pages[i]; - void *page_virtual; - - if (unlikely(page == NULL)) - continue; - - page_virtual = kmap_atomic(page, KM_USER0); - flush_dcache_range((unsigned long) page_virtual, - (unsigned long) page_virtual + PAGE_SIZE); - kunmap_atomic(page_virtual, KM_USER0); - } -#else - if (on_each_cpu(ttm_tt_ipi_handler, NULL, 1) != 0) - printk(KERN_ERR TTM_PFX - "Timed out waiting for drm cache flush.\n"); -#endif -} - /** * Allocates storage for pointers to the pages that back the ttm. * @@ -179,7 +116,7 @@ static void ttm_tt_free_user_pages(struct ttm_tt *ttm) set_page_dirty_lock(page); ttm->pages[i] = NULL; - ttm_mem_global_free(ttm->bdev->mem_glob, PAGE_SIZE, false); + ttm_mem_global_free(ttm->glob->mem_glob, PAGE_SIZE); put_page(page); } ttm->state = tt_unpopulated; @@ -190,8 +127,7 @@ static void ttm_tt_free_user_pages(struct ttm_tt *ttm) static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, int index) { struct page *p; - struct ttm_bo_device *bdev = ttm->bdev; - struct ttm_mem_global *mem_glob = bdev->mem_glob; + struct ttm_mem_global *mem_glob = ttm->glob->mem_glob; int ret; while (NULL == (p = ttm->pages[index])) { @@ -200,21 +136,14 @@ static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, int index) if (!p) return NULL; - if (PageHighMem(p)) { - ret = - ttm_mem_global_alloc(mem_glob, PAGE_SIZE, - false, false, true); - if (unlikely(ret != 0)) - goto out_err; + ret = ttm_mem_global_alloc_page(mem_glob, p, false, false); + if (unlikely(ret != 0)) + goto out_err; + + if (PageHighMem(p)) ttm->pages[--ttm->first_himem_page] = p; - } else { - ret = - ttm_mem_global_alloc(mem_glob, PAGE_SIZE, - false, false, false); - if (unlikely(ret != 0)) - goto out_err; + else ttm->pages[++ttm->last_lomem_page] = p; - } } return p; out_err: @@ -310,7 +239,7 @@ static int ttm_tt_set_caching(struct ttm_tt *ttm, } if (ttm->caching_state == tt_cached) - ttm_tt_cache_flush(ttm->pages, ttm->num_pages); + drm_clflush_pages(ttm->pages, ttm->num_pages); for (i = 0; i < ttm->num_pages; ++i) { cur_page = ttm->pages[i]; @@ -368,8 +297,8 @@ static void ttm_tt_free_alloced_pages(struct ttm_tt *ttm) printk(KERN_ERR TTM_PFX "Erroneous page count. " "Leaking pages.\n"); - ttm_mem_global_free(ttm->bdev->mem_glob, PAGE_SIZE, - PageHighMem(cur_page)); + ttm_mem_global_free_page(ttm->glob->mem_glob, + cur_page); __free_page(cur_page); } } @@ -414,7 +343,7 @@ int ttm_tt_set_user(struct ttm_tt *ttm, struct mm_struct *mm = tsk->mm; int ret; int write = (ttm->page_flags & TTM_PAGE_FLAG_WRITE) != 0; - struct ttm_mem_global *mem_glob = ttm->bdev->mem_glob; + struct ttm_mem_global *mem_glob = ttm->glob->mem_glob; BUG_ON(num_pages != ttm->num_pages); BUG_ON((ttm->page_flags & TTM_PAGE_FLAG_USER) == 0); @@ -424,7 +353,7 @@ int ttm_tt_set_user(struct ttm_tt *ttm, */ ret = ttm_mem_global_alloc(mem_glob, num_pages * PAGE_SIZE, - false, false, false); + false, false); if (unlikely(ret != 0)) return ret; @@ -435,7 +364,7 @@ int ttm_tt_set_user(struct ttm_tt *ttm, if (ret != num_pages && write) { ttm_tt_free_user_pages(ttm); - ttm_mem_global_free(mem_glob, num_pages * PAGE_SIZE, false); + ttm_mem_global_free(mem_glob, num_pages * PAGE_SIZE); return -ENOMEM; } @@ -459,8 +388,7 @@ struct ttm_tt *ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size, if (!ttm) return NULL; - ttm->bdev = bdev; - + ttm->glob = bdev->glob; ttm->num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; ttm->first_himem_page = ttm->num_pages; ttm->last_lomem_page = -1; diff --git a/drivers/media/common/tuners/tda18271-common.c b/drivers/media/common/tuners/tda18271-common.c index fc76c30e24f1..155c93eb75da 100644 --- a/drivers/media/common/tuners/tda18271-common.c +++ b/drivers/media/common/tuners/tda18271-common.c @@ -210,7 +210,8 @@ int tda18271_write_regs(struct dvb_frontend *fe, int idx, int len) tda18271_i2c_gate_ctrl(fe, 0); if (ret != 1) - tda_err("ERROR: i2c_transfer returned: %d\n", ret); + tda_err("ERROR: idx = 0x%x, len = %d, " + "i2c_transfer returned: %d\n", idx, len, ret); return (ret == 1 ? 0 : ret); } diff --git a/drivers/media/common/tuners/tda18271-fe.c b/drivers/media/common/tuners/tda18271-fe.c index bc4b004ba7db..64595112000d 100644 --- a/drivers/media/common/tuners/tda18271-fe.c +++ b/drivers/media/common/tuners/tda18271-fe.c @@ -36,6 +36,27 @@ static LIST_HEAD(hybrid_tuner_instance_list); /*---------------------------------------------------------------------*/ +static int tda18271_toggle_output(struct dvb_frontend *fe, int standby) +{ + struct tda18271_priv *priv = fe->tuner_priv; + + int ret = tda18271_set_standby_mode(fe, standby ? 1 : 0, + priv->output_opt & TDA18271_OUTPUT_LT_OFF ? 1 : 0, + priv->output_opt & TDA18271_OUTPUT_XT_OFF ? 1 : 0); + + if (tda_fail(ret)) + goto fail; + + tda_dbg("%s mode: xtal oscillator %s, slave tuner loop thru %s\n", + standby ? "standby" : "active", + priv->output_opt & TDA18271_OUTPUT_XT_OFF ? "off" : "on", + priv->output_opt & TDA18271_OUTPUT_LT_OFF ? "off" : "on"); +fail: + return ret; +} + +/*---------------------------------------------------------------------*/ + static inline int charge_pump_source(struct dvb_frontend *fe, int force) { struct tda18271_priv *priv = fe->tuner_priv; @@ -271,7 +292,7 @@ static int tda18271c2_rf_tracking_filters_correction(struct dvb_frontend *fe, tda18271_lookup_map(fe, RF_CAL_DC_OVER_DT, &freq, &dc_over_dt); /* calculate temperature compensation */ - rfcal_comp = dc_over_dt * (tm_current - priv->tm_rfcal); + rfcal_comp = dc_over_dt * (tm_current - priv->tm_rfcal) / 1000; regs[R_EB14] = approx + rfcal_comp; ret = tda18271_write_regs(fe, R_EB14, 1); @@ -800,7 +821,7 @@ static int tda18271_init(struct dvb_frontend *fe) mutex_lock(&priv->lock); - /* power up */ + /* full power up */ ret = tda18271_set_standby_mode(fe, 0, 0, 0); if (tda_fail(ret)) goto fail; @@ -818,6 +839,21 @@ fail: return ret; } +static int tda18271_sleep(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + int ret; + + mutex_lock(&priv->lock); + + /* enter standby mode, with required output features enabled */ + ret = tda18271_toggle_output(fe, 1); + + mutex_unlock(&priv->lock); + + return ret; +} + /* ------------------------------------------------------------------ */ static int tda18271_agc(struct dvb_frontend *fe) @@ -827,8 +863,9 @@ static int tda18271_agc(struct dvb_frontend *fe) switch (priv->config) { case 0: - /* no LNA */ - tda_dbg("no agc configuration provided\n"); + /* no external agc configuration required */ + if (tda18271_debug & DBG_ADV) + tda_dbg("no agc configuration provided\n"); break; case 3: /* switch with GPIO of saa713x */ @@ -1010,22 +1047,6 @@ fail: return ret; } -static int tda18271_sleep(struct dvb_frontend *fe) -{ - struct tda18271_priv *priv = fe->tuner_priv; - int ret; - - mutex_lock(&priv->lock); - - /* standby mode w/ slave tuner output - * & loop thru & xtal oscillator on */ - ret = tda18271_set_standby_mode(fe, 1, 0, 0); - - mutex_unlock(&priv->lock); - - return ret; -} - static int tda18271_release(struct dvb_frontend *fe) { struct tda18271_priv *priv = fe->tuner_priv; @@ -1199,6 +1220,9 @@ struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr, priv->gate = (cfg) ? cfg->gate : TDA18271_GATE_AUTO; priv->role = (cfg) ? cfg->role : TDA18271_MASTER; priv->config = (cfg) ? cfg->config : 0; + priv->small_i2c = (cfg) ? cfg->small_i2c : 0; + priv->output_opt = (cfg) ? + cfg->output_opt : TDA18271_OUTPUT_LT_XT_ON; /* tda18271_cal_on_startup == -1 when cal * module option is unset */ @@ -1216,9 +1240,6 @@ struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr, fe->tuner_priv = priv; - if (cfg) - priv->small_i2c = cfg->small_i2c; - if (tda_fail(tda18271_get_id(fe))) goto fail; @@ -1238,9 +1259,19 @@ struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr, /* existing tuner instance */ fe->tuner_priv = priv; - /* allow dvb driver to override i2c gate setting */ - if ((cfg) && (cfg->gate != TDA18271_GATE_ANALOG)) - priv->gate = cfg->gate; + /* allow dvb driver to override configuration settings */ + if (cfg) { + if (cfg->gate != TDA18271_GATE_ANALOG) + priv->gate = cfg->gate; + if (cfg->role) + priv->role = cfg->role; + if (cfg->config) + priv->config = cfg->config; + if (cfg->small_i2c) + priv->small_i2c = cfg->small_i2c; + if (cfg->output_opt) + priv->output_opt = cfg->output_opt; + } break; } diff --git a/drivers/media/common/tuners/tda18271-maps.c b/drivers/media/common/tuners/tda18271-maps.c index ab14ceb9e0ce..e21fdeff3ddf 100644 --- a/drivers/media/common/tuners/tda18271-maps.c +++ b/drivers/media/common/tuners/tda18271-maps.c @@ -962,10 +962,9 @@ struct tda18271_cid_target_map { static struct tda18271_cid_target_map tda18271_cid_target[] = { { .rfmax = 46000, .target = 0x04, .limit = 1800 }, { .rfmax = 52200, .target = 0x0a, .limit = 1500 }, - { .rfmax = 79100, .target = 0x01, .limit = 4000 }, + { .rfmax = 70100, .target = 0x01, .limit = 4000 }, { .rfmax = 136800, .target = 0x18, .limit = 4000 }, { .rfmax = 156700, .target = 0x18, .limit = 4000 }, - { .rfmax = 156700, .target = 0x18, .limit = 4000 }, { .rfmax = 186250, .target = 0x0a, .limit = 4000 }, { .rfmax = 230000, .target = 0x0a, .limit = 4000 }, { .rfmax = 345000, .target = 0x18, .limit = 4000 }, diff --git a/drivers/media/common/tuners/tda18271-priv.h b/drivers/media/common/tuners/tda18271-priv.h index e6a80ad09356..2bee229acd91 100644 --- a/drivers/media/common/tuners/tda18271-priv.h +++ b/drivers/media/common/tuners/tda18271-priv.h @@ -108,6 +108,7 @@ struct tda18271_priv { enum tda18271_role role; enum tda18271_i2c_gate gate; enum tda18271_ver id; + enum tda18271_output_options output_opt; unsigned int config; /* interface to saa713x / tda829x */ unsigned int tm_rfcal; diff --git a/drivers/media/common/tuners/tda18271.h b/drivers/media/common/tuners/tda18271.h index 71bac9593f1e..323f2912128d 100644 --- a/drivers/media/common/tuners/tda18271.h +++ b/drivers/media/common/tuners/tda18271.h @@ -67,6 +67,17 @@ enum tda18271_i2c_gate { TDA18271_GATE_DIGITAL, }; +enum tda18271_output_options { + /* slave tuner output & loop thru & xtal oscillator always on */ + TDA18271_OUTPUT_LT_XT_ON = 0, + + /* slave tuner output loop thru off */ + TDA18271_OUTPUT_LT_OFF = 1, + + /* xtal oscillator off */ + TDA18271_OUTPUT_XT_OFF = 2, +}; + struct tda18271_config { /* override default if freq / std settings (optional) */ struct tda18271_std_map *std_map; @@ -77,6 +88,9 @@ struct tda18271_config { /* use i2c gate provided by analog or digital demod */ enum tda18271_i2c_gate gate; + /* output options that can be disabled */ + enum tda18271_output_options output_opt; + /* force rf tracking filter calibration on startup */ unsigned int rf_cal_on_startup:1; diff --git a/drivers/media/common/tuners/tuner-types.c b/drivers/media/common/tuners/tuner-types.c index 5c6ef1e23c94..2b876f3988c1 100644 --- a/drivers/media/common/tuners/tuner-types.c +++ b/drivers/media/common/tuners/tuner-types.c @@ -1320,6 +1320,23 @@ static struct tuner_params tuner_partsnic_pti_5nf05_params[] = { }, }; +/* --------- TUNER_PHILIPS_CU1216L - DVB-C NIM ------------------------- */ + +static struct tuner_range tuner_cu1216l_ranges[] = { + { 16 * 160.25 /*MHz*/, 0xce, 0x01 }, + { 16 * 444.25 /*MHz*/, 0xce, 0x02 }, + { 16 * 999.99 , 0xce, 0x04 }, +}; + +static struct tuner_params tuner_philips_cu1216l_params[] = { + { + .type = TUNER_PARAM_TYPE_DIGITAL, + .ranges = tuner_cu1216l_ranges, + .count = ARRAY_SIZE(tuner_cu1216l_ranges), + .iffreq = 16 * 36.125, /*MHz*/ + }, +}; + /* --------------------------------------------------------------------- */ struct tunertype tuners[] = { @@ -1778,6 +1795,16 @@ struct tunertype tuners[] = { .params = tuner_partsnic_pti_5nf05_params, .count = ARRAY_SIZE(tuner_partsnic_pti_5nf05_params), }, + [TUNER_PHILIPS_CU1216L] = { + .name = "Philips CU1216L", + .params = tuner_philips_cu1216l_params, + .count = ARRAY_SIZE(tuner_philips_cu1216l_params), + .stepsize = 62500, + }, + [TUNER_NXP_TDA18271] = { + .name = "NXP TDA18271", + /* see tda18271-fe.c for details */ + }, }; EXPORT_SYMBOL(tuners); diff --git a/drivers/media/dvb/Kconfig b/drivers/media/dvb/Kconfig index 1d0e4b1ef10c..35d0817126e9 100644 --- a/drivers/media/dvb/Kconfig +++ b/drivers/media/dvb/Kconfig @@ -68,6 +68,10 @@ comment "Supported FireWire (IEEE 1394) Adapters" depends on DVB_CORE && IEEE1394 source "drivers/media/dvb/firewire/Kconfig" +comment "Supported Earthsoft PT1 Adapters" + depends on DVB_CORE && PCI && I2C +source "drivers/media/dvb/pt1/Kconfig" + comment "Supported DVB Frontends" depends on DVB_CORE source "drivers/media/dvb/frontends/Kconfig" diff --git a/drivers/media/dvb/Makefile b/drivers/media/dvb/Makefile index 6092a5bb5a7d..16d262ddb45d 100644 --- a/drivers/media/dvb/Makefile +++ b/drivers/media/dvb/Makefile @@ -2,6 +2,6 @@ # Makefile for the kernel multimedia device drivers. # -obj-y := dvb-core/ frontends/ ttpci/ ttusb-dec/ ttusb-budget/ b2c2/ bt8xx/ dvb-usb/ pluto2/ siano/ dm1105/ +obj-y := dvb-core/ frontends/ ttpci/ ttusb-dec/ ttusb-budget/ b2c2/ bt8xx/ dvb-usb/ pluto2/ siano/ dm1105/ pt1/ obj-$(CONFIG_DVB_FIREDTV) += firewire/ diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c index d13ebcb0c6b6..ddf639ed2fd8 100644 --- a/drivers/media/dvb/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb/dvb-core/dvb_frontend.c @@ -850,6 +850,49 @@ static int dvb_frontend_check_parameters(struct dvb_frontend *fe, return 0; } +static int dvb_frontend_clear_cache(struct dvb_frontend *fe) +{ + int i; + + memset(&(fe->dtv_property_cache), 0, + sizeof(struct dtv_frontend_properties)); + + fe->dtv_property_cache.state = DTV_CLEAR; + fe->dtv_property_cache.delivery_system = SYS_UNDEFINED; + fe->dtv_property_cache.inversion = INVERSION_AUTO; + fe->dtv_property_cache.fec_inner = FEC_AUTO; + fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_AUTO; + fe->dtv_property_cache.bandwidth_hz = BANDWIDTH_AUTO; + fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_AUTO; + fe->dtv_property_cache.hierarchy = HIERARCHY_AUTO; + fe->dtv_property_cache.symbol_rate = QAM_AUTO; + fe->dtv_property_cache.code_rate_HP = FEC_AUTO; + fe->dtv_property_cache.code_rate_LP = FEC_AUTO; + + fe->dtv_property_cache.isdbt_partial_reception = -1; + fe->dtv_property_cache.isdbt_sb_mode = -1; + fe->dtv_property_cache.isdbt_sb_subchannel = -1; + fe->dtv_property_cache.isdbt_sb_segment_idx = -1; + fe->dtv_property_cache.isdbt_sb_segment_count = -1; + fe->dtv_property_cache.isdbt_layer_enabled = 0x7; + for (i = 0; i < 3; i++) { + fe->dtv_property_cache.layer[i].fec = FEC_AUTO; + fe->dtv_property_cache.layer[i].modulation = QAM_AUTO; + fe->dtv_property_cache.layer[i].interleaving = -1; + fe->dtv_property_cache.layer[i].segment_count = -1; + } + + return 0; +} + +#define _DTV_CMD(n, s, b) \ +[n] = { \ + .name = #n, \ + .cmd = n, \ + .set = s,\ + .buffer = b \ +} + static struct dtv_cmds_h dtv_cmds[] = { [DTV_TUNE] = { .name = "DTV_TUNE", @@ -949,6 +992,47 @@ static struct dtv_cmds_h dtv_cmds[] = { .cmd = DTV_TRANSMISSION_MODE, .set = 1, }, + + _DTV_CMD(DTV_ISDBT_PARTIAL_RECEPTION, 1, 0), + _DTV_CMD(DTV_ISDBT_SOUND_BROADCASTING, 1, 0), + _DTV_CMD(DTV_ISDBT_SB_SUBCHANNEL_ID, 1, 0), + _DTV_CMD(DTV_ISDBT_SB_SEGMENT_IDX, 1, 0), + _DTV_CMD(DTV_ISDBT_SB_SEGMENT_COUNT, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYER_ENABLED, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERA_FEC, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERA_MODULATION, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERA_SEGMENT_COUNT, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERA_TIME_INTERLEAVING, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERB_FEC, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERB_MODULATION, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERB_SEGMENT_COUNT, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERB_TIME_INTERLEAVING, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERC_FEC, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERC_MODULATION, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERC_SEGMENT_COUNT, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERC_TIME_INTERLEAVING, 1, 0), + + _DTV_CMD(DTV_ISDBT_PARTIAL_RECEPTION, 0, 0), + _DTV_CMD(DTV_ISDBT_SOUND_BROADCASTING, 0, 0), + _DTV_CMD(DTV_ISDBT_SB_SUBCHANNEL_ID, 0, 0), + _DTV_CMD(DTV_ISDBT_SB_SEGMENT_IDX, 0, 0), + _DTV_CMD(DTV_ISDBT_SB_SEGMENT_COUNT, 0, 0), + _DTV_CMD(DTV_ISDBT_LAYER_ENABLED, 0, 0), + _DTV_CMD(DTV_ISDBT_LAYERA_FEC, 0, 0), + _DTV_CMD(DTV_ISDBT_LAYERA_MODULATION, 0, 0), + _DTV_CMD(DTV_ISDBT_LAYERA_SEGMENT_COUNT, 0, 0), + _DTV_CMD(DTV_ISDBT_LAYERA_TIME_INTERLEAVING, 0, 0), + _DTV_CMD(DTV_ISDBT_LAYERB_FEC, 0, 0), + _DTV_CMD(DTV_ISDBT_LAYERB_MODULATION, 0, 0), + _DTV_CMD(DTV_ISDBT_LAYERB_SEGMENT_COUNT, 0, 0), + _DTV_CMD(DTV_ISDBT_LAYERB_TIME_INTERLEAVING, 0, 0), + _DTV_CMD(DTV_ISDBT_LAYERC_FEC, 0, 0), + _DTV_CMD(DTV_ISDBT_LAYERC_MODULATION, 0, 0), + _DTV_CMD(DTV_ISDBT_LAYERC_SEGMENT_COUNT, 0, 0), + _DTV_CMD(DTV_ISDBT_LAYERC_TIME_INTERLEAVING, 0, 0), + + _DTV_CMD(DTV_ISDBS_TS_ID, 1, 0), + /* Get */ [DTV_DISEQC_SLAVE_REPLY] = { .name = "DTV_DISEQC_SLAVE_REPLY", @@ -956,6 +1040,7 @@ static struct dtv_cmds_h dtv_cmds[] = { .set = 0, .buffer = 1, }, + [DTV_API_VERSION] = { .name = "DTV_API_VERSION", .cmd = DTV_API_VERSION, @@ -1165,14 +1250,21 @@ static void dtv_property_adv_params_sync(struct dvb_frontend *fe) if(c->delivery_system == SYS_ISDBT) { /* Fake out a generic DVB-T request so we pass validation in the ioctl */ p->frequency = c->frequency; - p->inversion = INVERSION_AUTO; + p->inversion = c->inversion; p->u.ofdm.constellation = QAM_AUTO; p->u.ofdm.code_rate_HP = FEC_AUTO; p->u.ofdm.code_rate_LP = FEC_AUTO; - p->u.ofdm.bandwidth = BANDWIDTH_AUTO; p->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO; p->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO; p->u.ofdm.hierarchy_information = HIERARCHY_AUTO; + if (c->bandwidth_hz == 8000000) + p->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; + else if (c->bandwidth_hz == 7000000) + p->u.ofdm.bandwidth = BANDWIDTH_7_MHZ; + else if (c->bandwidth_hz == 6000000) + p->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; + else + p->u.ofdm.bandwidth = BANDWIDTH_AUTO; } } @@ -1274,6 +1366,65 @@ static int dtv_property_process_get(struct dvb_frontend *fe, case DTV_HIERARCHY: tvp->u.data = fe->dtv_property_cache.hierarchy; break; + + /* ISDB-T Support here */ + case DTV_ISDBT_PARTIAL_RECEPTION: + tvp->u.data = fe->dtv_property_cache.isdbt_partial_reception; + break; + case DTV_ISDBT_SOUND_BROADCASTING: + tvp->u.data = fe->dtv_property_cache.isdbt_sb_mode; + break; + case DTV_ISDBT_SB_SUBCHANNEL_ID: + tvp->u.data = fe->dtv_property_cache.isdbt_sb_subchannel; + break; + case DTV_ISDBT_SB_SEGMENT_IDX: + tvp->u.data = fe->dtv_property_cache.isdbt_sb_segment_idx; + break; + case DTV_ISDBT_SB_SEGMENT_COUNT: + tvp->u.data = fe->dtv_property_cache.isdbt_sb_segment_count; + break; + case DTV_ISDBT_LAYER_ENABLED: + tvp->u.data = fe->dtv_property_cache.isdbt_layer_enabled; + break; + case DTV_ISDBT_LAYERA_FEC: + tvp->u.data = fe->dtv_property_cache.layer[0].fec; + break; + case DTV_ISDBT_LAYERA_MODULATION: + tvp->u.data = fe->dtv_property_cache.layer[0].modulation; + break; + case DTV_ISDBT_LAYERA_SEGMENT_COUNT: + tvp->u.data = fe->dtv_property_cache.layer[0].segment_count; + break; + case DTV_ISDBT_LAYERA_TIME_INTERLEAVING: + tvp->u.data = fe->dtv_property_cache.layer[0].interleaving; + break; + case DTV_ISDBT_LAYERB_FEC: + tvp->u.data = fe->dtv_property_cache.layer[1].fec; + break; + case DTV_ISDBT_LAYERB_MODULATION: + tvp->u.data = fe->dtv_property_cache.layer[1].modulation; + break; + case DTV_ISDBT_LAYERB_SEGMENT_COUNT: + tvp->u.data = fe->dtv_property_cache.layer[1].segment_count; + break; + case DTV_ISDBT_LAYERB_TIME_INTERLEAVING: + tvp->u.data = fe->dtv_property_cache.layer[1].interleaving; + break; + case DTV_ISDBT_LAYERC_FEC: + tvp->u.data = fe->dtv_property_cache.layer[2].fec; + break; + case DTV_ISDBT_LAYERC_MODULATION: + tvp->u.data = fe->dtv_property_cache.layer[2].modulation; + break; + case DTV_ISDBT_LAYERC_SEGMENT_COUNT: + tvp->u.data = fe->dtv_property_cache.layer[2].segment_count; + break; + case DTV_ISDBT_LAYERC_TIME_INTERLEAVING: + tvp->u.data = fe->dtv_property_cache.layer[2].interleaving; + break; + case DTV_ISDBS_TS_ID: + tvp->u.data = fe->dtv_property_cache.isdbs_ts_id; + break; default: r = -1; } @@ -1302,10 +1453,8 @@ static int dtv_property_process_set(struct dvb_frontend *fe, /* Reset a cache of data specific to the frontend here. This does * not effect hardware. */ + dvb_frontend_clear_cache(fe); dprintk("%s() Flushing property cache\n", __func__); - memset(&fe->dtv_property_cache, 0, sizeof(struct dtv_frontend_properties)); - fe->dtv_property_cache.state = tvp->cmd; - fe->dtv_property_cache.delivery_system = SYS_UNDEFINED; break; case DTV_TUNE: /* interpret the cache of data, build either a traditional frontend @@ -1371,6 +1520,65 @@ static int dtv_property_process_set(struct dvb_frontend *fe, case DTV_HIERARCHY: fe->dtv_property_cache.hierarchy = tvp->u.data; break; + + /* ISDB-T Support here */ + case DTV_ISDBT_PARTIAL_RECEPTION: + fe->dtv_property_cache.isdbt_partial_reception = tvp->u.data; + break; + case DTV_ISDBT_SOUND_BROADCASTING: + fe->dtv_property_cache.isdbt_sb_mode = tvp->u.data; + break; + case DTV_ISDBT_SB_SUBCHANNEL_ID: + fe->dtv_property_cache.isdbt_sb_subchannel = tvp->u.data; + break; + case DTV_ISDBT_SB_SEGMENT_IDX: + fe->dtv_property_cache.isdbt_sb_segment_idx = tvp->u.data; + break; + case DTV_ISDBT_SB_SEGMENT_COUNT: + fe->dtv_property_cache.isdbt_sb_segment_count = tvp->u.data; + break; + case DTV_ISDBT_LAYER_ENABLED: + fe->dtv_property_cache.isdbt_layer_enabled = tvp->u.data; + break; + case DTV_ISDBT_LAYERA_FEC: + fe->dtv_property_cache.layer[0].fec = tvp->u.data; + break; + case DTV_ISDBT_LAYERA_MODULATION: + fe->dtv_property_cache.layer[0].modulation = tvp->u.data; + break; + case DTV_ISDBT_LAYERA_SEGMENT_COUNT: + fe->dtv_property_cache.layer[0].segment_count = tvp->u.data; + break; + case DTV_ISDBT_LAYERA_TIME_INTERLEAVING: + fe->dtv_property_cache.layer[0].interleaving = tvp->u.data; + break; + case DTV_ISDBT_LAYERB_FEC: + fe->dtv_property_cache.layer[1].fec = tvp->u.data; + break; + case DTV_ISDBT_LAYERB_MODULATION: + fe->dtv_property_cache.layer[1].modulation = tvp->u.data; + break; + case DTV_ISDBT_LAYERB_SEGMENT_COUNT: + fe->dtv_property_cache.layer[1].segment_count = tvp->u.data; + break; + case DTV_ISDBT_LAYERB_TIME_INTERLEAVING: + fe->dtv_property_cache.layer[1].interleaving = tvp->u.data; + break; + case DTV_ISDBT_LAYERC_FEC: + fe->dtv_property_cache.layer[2].fec = tvp->u.data; + break; + case DTV_ISDBT_LAYERC_MODULATION: + fe->dtv_property_cache.layer[2].modulation = tvp->u.data; + break; + case DTV_ISDBT_LAYERC_SEGMENT_COUNT: + fe->dtv_property_cache.layer[2].segment_count = tvp->u.data; + break; + case DTV_ISDBT_LAYERC_TIME_INTERLEAVING: + fe->dtv_property_cache.layer[2].interleaving = tvp->u.data; + break; + case DTV_ISDBS_TS_ID: + fe->dtv_property_cache.isdbs_ts_id = tvp->u.data; + break; default: r = -1; } diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.h b/drivers/media/dvb/dvb-core/dvb_frontend.h index e176da472d7a..810f07d63246 100644 --- a/drivers/media/dvb/dvb-core/dvb_frontend.h +++ b/drivers/media/dvb/dvb-core/dvb_frontend.h @@ -341,6 +341,23 @@ struct dtv_frontend_properties { fe_rolloff_t rolloff; fe_delivery_system_t delivery_system; + + /* ISDB-T specifics */ + u8 isdbt_partial_reception; + u8 isdbt_sb_mode; + u8 isdbt_sb_subchannel; + u32 isdbt_sb_segment_idx; + u32 isdbt_sb_segment_count; + u8 isdbt_layer_enabled; + struct { + u8 segment_count; + fe_code_rate_t fec; + fe_modulation_t modulation; + u8 interleaving; + } layer[3]; + + /* ISDB-T specifics */ + u32 isdbs_ts_id; }; struct dvb_frontend { diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig index 8b8bc04ee980..0e4b97fba384 100644 --- a/drivers/media/dvb/dvb-usb/Kconfig +++ b/drivers/media/dvb/dvb-usb/Kconfig @@ -71,6 +71,7 @@ config DVB_USB_DIB0700 depends on DVB_USB select DVB_DIB7000P if !DVB_FE_CUSTOMISE select DVB_DIB7000M if !DVB_FE_CUSTOMISE + select DVB_DIB8000 if !DVB_FE_CUSTOMISE select DVB_DIB3000MC if !DVB_FE_CUSTOMISE select DVB_S5H1411 if !DVB_FE_CUSTOMISE select DVB_LGDT3305 if !DVB_FE_CUSTOMISE @@ -87,7 +88,7 @@ config DVB_USB_DIB0700 Avermedia and other big and small companies. For an up-to-date list of devices supported by this driver, have a look - on the Linux-DVB Wiki at www.linuxtv.org. + on the LinuxTV Wiki at www.linuxtv.org. Say Y if you own such a device and want to use it. You should build it as a module. @@ -315,3 +316,9 @@ config DVB_USB_CE6230 select MEDIA_TUNER_MXL5005S if !MEDIA_TUNER_CUSTOMISE help Say Y here to support the Intel CE6230 DVB-T USB2.0 receiver + +config DVB_USB_FRIIO + tristate "Friio ISDB-T USB2.0 Receiver support" + depends on DVB_USB + help + Say Y here to support the Japanese DTV receiver Friio. diff --git a/drivers/media/dvb/dvb-usb/Makefile b/drivers/media/dvb/dvb-usb/Makefile index f92734ed777a..85b83a43d55d 100644 --- a/drivers/media/dvb/dvb-usb/Makefile +++ b/drivers/media/dvb/dvb-usb/Makefile @@ -79,6 +79,9 @@ obj-$(CONFIG_DVB_USB_CINERGY_T2) += dvb-usb-cinergyT2.o dvb-usb-ce6230-objs = ce6230.o obj-$(CONFIG_DVB_USB_CE6230) += dvb-usb-ce6230.o +dvb-usb-friio-objs = friio.o friio-fe.o +obj-$(CONFIG_DVB_USB_FRIIO) += dvb-usb-friio.o + EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/ -Idrivers/media/dvb/frontends/ # due to tuner-xc3028 EXTRA_CFLAGS += -Idrivers/media/common/tuners diff --git a/drivers/media/dvb/dvb-usb/af9015.c b/drivers/media/dvb/dvb-usb/af9015.c index 99cdd0d101ca..cf042b309b46 100644 --- a/drivers/media/dvb/dvb-usb/af9015.c +++ b/drivers/media/dvb/dvb-usb/af9015.c @@ -61,10 +61,13 @@ static struct af9013_config af9015_af9013_config[] = { static int af9015_rw_udev(struct usb_device *udev, struct req_t *req) { +#define BUF_LEN 63 +#define REQ_HDR_LEN 8 /* send header size */ +#define ACK_HDR_LEN 2 /* rece header size */ int act_len, ret; - u8 buf[64]; + u8 buf[BUF_LEN]; u8 write = 1; - u8 msg_len = 8; + u8 msg_len = REQ_HDR_LEN; static u8 seq; /* packet sequence number */ if (mutex_lock_interruptible(&af9015_usb_mutex) < 0) @@ -94,7 +97,7 @@ static int af9015_rw_udev(struct usb_device *udev, struct req_t *req) break; case WRITE_MEMORY: if (((req->addr & 0xff00) == 0xff00) || - ((req->addr & 0xae00) == 0xae00)) + ((req->addr & 0xff00) == 0xae00)) buf[0] = WRITE_VIRTUAL_MEMORY; case WRITE_VIRTUAL_MEMORY: case COPY_FIRMWARE: @@ -107,17 +110,26 @@ static int af9015_rw_udev(struct usb_device *udev, struct req_t *req) goto error_unlock; } + /* buffer overflow check */ + if ((write && (req->data_len > BUF_LEN - REQ_HDR_LEN)) || + (!write && (req->data_len > BUF_LEN - ACK_HDR_LEN))) { + err("too much data; cmd:%d len:%d", req->cmd, req->data_len); + ret = -EINVAL; + goto error_unlock; + } + /* write requested */ if (write) { - memcpy(&buf[8], req->data, req->data_len); + memcpy(&buf[REQ_HDR_LEN], req->data, req->data_len); msg_len += req->data_len; } + deb_xfer(">>> "); debug_dump(buf, msg_len, deb_xfer); /* send req */ ret = usb_bulk_msg(udev, usb_sndbulkpipe(udev, 0x02), buf, msg_len, - &act_len, AF9015_USB_TIMEOUT); + &act_len, AF9015_USB_TIMEOUT); if (ret) err("bulk message failed:%d (%d/%d)", ret, msg_len, act_len); else @@ -130,10 +142,14 @@ static int af9015_rw_udev(struct usb_device *udev, struct req_t *req) if (req->cmd == DOWNLOAD_FIRMWARE || req->cmd == RECONNECT_USB) goto exit_unlock; - /* receive ack and data if read req */ - msg_len = 1 + 1 + req->data_len; /* seq + status + data len */ + /* write receives seq + status = 2 bytes + read receives seq + status + data = 2 + N bytes */ + msg_len = ACK_HDR_LEN; + if (!write) + msg_len += req->data_len; + ret = usb_bulk_msg(udev, usb_rcvbulkpipe(udev, 0x81), buf, msg_len, - &act_len, AF9015_USB_TIMEOUT); + &act_len, AF9015_USB_TIMEOUT); if (ret) { err("recv bulk message failed:%d", ret); ret = -1; @@ -159,7 +175,7 @@ static int af9015_rw_udev(struct usb_device *udev, struct req_t *req) /* read request, copy returned data to return buf */ if (!write) - memcpy(req->data, &buf[2], req->data_len); + memcpy(req->data, &buf[ACK_HDR_LEN], req->data_len); error_unlock: exit_unlock: @@ -369,12 +385,14 @@ static int af9015_init_endpoint(struct dvb_usb_device *d) u8 packet_size; deb_info("%s: USB speed:%d\n", __func__, d->udev->speed); + /* Windows driver uses packet count 21 for USB1.1 and 348 for USB2.0. + We use smaller - about 1/4 from the original, 5 and 87. */ #define TS_PACKET_SIZE 188 -#define TS_USB20_PACKET_COUNT 348 +#define TS_USB20_PACKET_COUNT 87 #define TS_USB20_FRAME_SIZE (TS_PACKET_SIZE*TS_USB20_PACKET_COUNT) -#define TS_USB11_PACKET_COUNT 21 +#define TS_USB11_PACKET_COUNT 5 #define TS_USB11_FRAME_SIZE (TS_PACKET_SIZE*TS_USB11_PACKET_COUNT) #define TS_USB20_MAX_PACKET_SIZE 512 @@ -868,13 +886,13 @@ static int af9015_read_config(struct usb_device *udev) /* USB1.1 set smaller buffersize and disable 2nd adapter */ if (udev->speed == USB_SPEED_FULL) { af9015_properties[i].adapter[0].stream.u.bulk.buffersize - = TS_USB11_MAX_PACKET_SIZE; + = TS_USB11_FRAME_SIZE; /* disable 2nd adapter because we don't have PID-filters */ af9015_config.dual_mode = 0; } else { af9015_properties[i].adapter[0].stream.u.bulk.buffersize - = TS_USB20_MAX_PACKET_SIZE; + = TS_USB20_FRAME_SIZE; } } @@ -1310,7 +1328,7 @@ static struct dvb_usb_device_properties af9015_properties[] = { .u = { .bulk = { .buffersize = - TS_USB20_MAX_PACKET_SIZE, + TS_USB20_FRAME_SIZE, } } }, @@ -1416,7 +1434,7 @@ static struct dvb_usb_device_properties af9015_properties[] = { .u = { .bulk = { .buffersize = - TS_USB20_MAX_PACKET_SIZE, + TS_USB20_FRAME_SIZE, } } }, @@ -1522,7 +1540,7 @@ static struct dvb_usb_device_properties af9015_properties[] = { .u = { .bulk = { .buffersize = - TS_USB20_MAX_PACKET_SIZE, + TS_USB20_FRAME_SIZE, } } }, diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c index 7381aff4dcf6..2ae7f648effe 100644 --- a/drivers/media/dvb/dvb-usb/anysee.c +++ b/drivers/media/dvb/dvb-usb/anysee.c @@ -203,11 +203,11 @@ static struct i2c_algorithm anysee_i2c_algo = { static int anysee_mt352_demod_init(struct dvb_frontend *fe) { - static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x28 }; - static u8 reset [] = { RESET, 0x80 }; - static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; - static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0x20 }; - static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 }; + static u8 clock_config[] = { CLOCK_CTL, 0x38, 0x28 }; + static u8 reset[] = { RESET, 0x80 }; + static u8 adc_ctl_1_cfg[] = { ADC_CTL_1, 0x40 }; + static u8 agc_cfg[] = { AGC_TARGET, 0x28, 0x20 }; + static u8 gpp_ctl_cfg[] = { GPP_CTL, 0x33 }; static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 }; mt352_write(fe, clock_config, sizeof(clock_config)); @@ -485,7 +485,7 @@ static int anysee_probe(struct usb_interface *intf, return ret; } -static struct usb_device_id anysee_table [] = { +static struct usb_device_id anysee_table[] = { { USB_DEVICE(USB_VID_CYPRESS, USB_PID_ANYSEE) }, { USB_DEVICE(USB_VID_AMT, USB_PID_ANYSEE) }, { } /* Terminating entry */ @@ -511,7 +511,7 @@ static struct dvb_usb_device_properties anysee_properties = { .endpoint = 0x82, .u = { .bulk = { - .buffersize = 512, + .buffersize = (16*512), } } }, diff --git a/drivers/media/dvb/dvb-usb/ce6230.c b/drivers/media/dvb/dvb-usb/ce6230.c index 52badc00e673..0737c6377892 100644 --- a/drivers/media/dvb/dvb-usb/ce6230.c +++ b/drivers/media/dvb/dvb-usb/ce6230.c @@ -274,7 +274,7 @@ static struct dvb_usb_device_properties ce6230_properties = { .endpoint = 0x82, .u = { .bulk = { - .buffersize = 512, + .buffersize = (16*512), } } }, diff --git a/drivers/media/dvb/dvb-usb/dib0700_devices.c b/drivers/media/dvb/dvb-usb/dib0700_devices.c index d1d6f4491403..0b2812aa30a4 100644 --- a/drivers/media/dvb/dvb-usb/dib0700_devices.c +++ b/drivers/media/dvb/dvb-usb/dib0700_devices.c @@ -4,13 +4,14 @@ * under the terms of the GNU General Public License as published by the Free * Software Foundation, version 2. * - * Copyright (C) 2005-7 DiBcom, SA + * Copyright (C) 2005-9 DiBcom, SA et al */ #include "dib0700.h" #include "dib3000mc.h" #include "dib7000m.h" #include "dib7000p.h" +#include "dib8000.h" #include "mt2060.h" #include "mt2266.h" #include "tuner-xc2028.h" @@ -1098,11 +1099,13 @@ static struct dibx000_agc_config dib7070_agc_config = { static int dib7070_tuner_reset(struct dvb_frontend *fe, int onoff) { + deb_info("reset: %d", onoff); return dib7000p_set_gpio(fe, 8, 0, !onoff); } static int dib7070_tuner_sleep(struct dvb_frontend *fe, int onoff) { + deb_info("sleep: %d", onoff); return dib7000p_set_gpio(fe, 9, 0, onoff); } @@ -1112,16 +1115,26 @@ static struct dib0070_config dib7070p_dib0070_config[2] = { .reset = dib7070_tuner_reset, .sleep = dib7070_tuner_sleep, .clock_khz = 12000, - .clock_pad_drive = 4 + .clock_pad_drive = 4, + .charge_pump = 2, }, { .i2c_address = DEFAULT_DIB0070_I2C_ADDRESS, .reset = dib7070_tuner_reset, .sleep = dib7070_tuner_sleep, .clock_khz = 12000, - + .charge_pump = 2, } }; +static struct dib0070_config dib7770p_dib0070_config = { + .i2c_address = DEFAULT_DIB0070_I2C_ADDRESS, + .reset = dib7070_tuner_reset, + .sleep = dib7070_tuner_sleep, + .clock_khz = 12000, + .clock_pad_drive = 0, + .flip_chip = 1, +}; + static int dib7070_set_param_override(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep) { struct dvb_usb_adapter *adap = fe->dvb->priv; @@ -1139,6 +1152,45 @@ static int dib7070_set_param_override(struct dvb_frontend *fe, struct dvb_fronte return state->set_param_save(fe, fep); } +static int dib7770_set_param_override(struct dvb_frontend *fe, + struct dvb_frontend_parameters *fep) +{ + struct dvb_usb_adapter *adap = fe->dvb->priv; + struct dib0700_adapter_state *state = adap->priv; + + u16 offset; + u8 band = BAND_OF_FREQUENCY(fep->frequency/1000); + switch (band) { + case BAND_VHF: + dib7000p_set_gpio(fe, 0, 0, 1); + offset = 850; + break; + case BAND_UHF: + default: + dib7000p_set_gpio(fe, 0, 0, 0); + offset = 250; + break; + } + deb_info("WBD for DiB7000P: %d\n", offset + dib0070_wbd_offset(fe)); + dib7000p_set_wbd_ref(fe, offset + dib0070_wbd_offset(fe)); + return state->set_param_save(fe, fep); +} + +static int dib7770p_tuner_attach(struct dvb_usb_adapter *adap) +{ + struct dib0700_adapter_state *st = adap->priv; + struct i2c_adapter *tun_i2c = dib7000p_get_i2c_master(adap->fe, + DIBX000_I2C_INTERFACE_TUNER, 1); + + if (dvb_attach(dib0070_attach, adap->fe, tun_i2c, + &dib7770p_dib0070_config) == NULL) + return -ENODEV; + + st->set_param_save = adap->fe->ops.tuner_ops.set_params; + adap->fe->ops.tuner_ops.set_params = dib7770_set_param_override; + return 0; +} + static int dib7070p_tuner_attach(struct dvb_usb_adapter *adap) { struct dib0700_adapter_state *st = adap->priv; @@ -1217,6 +1269,306 @@ static int stk7070p_frontend_attach(struct dvb_usb_adapter *adap) return adap->fe == NULL ? -ENODEV : 0; } +/* DIB807x generic */ +static struct dibx000_agc_config dib807x_agc_config[2] = { + { + BAND_VHF, + /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, + * P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0, + * P_agc_inv_pwm2=0,P_agc_inh_dc_rv_est=0, + * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, + * P_agc_write=0 */ + (0 << 15) | (0 << 14) | (7 << 11) | (0 << 10) | (0 << 9) | + (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | + (0 << 0), /* setup*/ + + 600, /* inv_gain*/ + 10, /* time_stabiliz*/ + + 0, /* alpha_level*/ + 118, /* thlock*/ + + 0, /* wbd_inv*/ + 3530, /* wbd_ref*/ + 1, /* wbd_sel*/ + 5, /* wbd_alpha*/ + + 65535, /* agc1_max*/ + 0, /* agc1_min*/ + + 65535, /* agc2_max*/ + 0, /* agc2_min*/ + + 0, /* agc1_pt1*/ + 40, /* agc1_pt2*/ + 183, /* agc1_pt3*/ + 206, /* agc1_slope1*/ + 255, /* agc1_slope2*/ + 72, /* agc2_pt1*/ + 152, /* agc2_pt2*/ + 88, /* agc2_slope1*/ + 90, /* agc2_slope2*/ + + 17, /* alpha_mant*/ + 27, /* alpha_exp*/ + 23, /* beta_mant*/ + 51, /* beta_exp*/ + + 0, /* perform_agc_softsplit*/ + }, { + BAND_UHF, + /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, + * P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0, + * P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0, + * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, + * P_agc_write=0 */ + (0 << 15) | (0 << 14) | (1 << 11) | (0 << 10) | (0 << 9) | + (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | + (0 << 0), /* setup */ + + 600, /* inv_gain*/ + 10, /* time_stabiliz*/ + + 0, /* alpha_level*/ + 118, /* thlock*/ + + 0, /* wbd_inv*/ + 3530, /* wbd_ref*/ + 1, /* wbd_sel*/ + 5, /* wbd_alpha*/ + + 65535, /* agc1_max*/ + 0, /* agc1_min*/ + + 65535, /* agc2_max*/ + 0, /* agc2_min*/ + + 0, /* agc1_pt1*/ + 40, /* agc1_pt2*/ + 183, /* agc1_pt3*/ + 206, /* agc1_slope1*/ + 255, /* agc1_slope2*/ + 72, /* agc2_pt1*/ + 152, /* agc2_pt2*/ + 88, /* agc2_slope1*/ + 90, /* agc2_slope2*/ + + 17, /* alpha_mant*/ + 27, /* alpha_exp*/ + 23, /* beta_mant*/ + 51, /* beta_exp*/ + + 0, /* perform_agc_softsplit*/ + } +}; + +static struct dibx000_bandwidth_config dib807x_bw_config_12_mhz = { + 60000, 15000, /* internal, sampling*/ + 1, 20, 3, 1, 0, /* pll_cfg: prediv, ratio, range, reset, bypass*/ + 0, 0, 1, 1, 2, /* misc: refdiv, bypclk_div, IO_CLK_en_core, + ADClkSrc, modulo */ + (3 << 14) | (1 << 12) | (599 << 0), /* sad_cfg: refsel, sel, freq_15k*/ + (0 << 25) | 0, /* ifreq = 0.000000 MHz*/ + 18179755, /* timf*/ + 12000000, /* xtal_hz*/ +}; + +static struct dib8000_config dib807x_dib8000_config[2] = { + { + .output_mpeg2_in_188_bytes = 1, + + .agc_config_count = 2, + .agc = dib807x_agc_config, + .pll = &dib807x_bw_config_12_mhz, + .tuner_is_baseband = 1, + + .gpio_dir = DIB8000_GPIO_DEFAULT_DIRECTIONS, + .gpio_val = DIB8000_GPIO_DEFAULT_VALUES, + .gpio_pwm_pos = DIB8000_GPIO_DEFAULT_PWM_POS, + + .hostbus_diversity = 1, + .div_cfg = 1, + .agc_control = &dib0070_ctrl_agc_filter, + .output_mode = OUTMODE_MPEG2_FIFO, + .drives = 0x2d98, + }, { + .output_mpeg2_in_188_bytes = 1, + + .agc_config_count = 2, + .agc = dib807x_agc_config, + .pll = &dib807x_bw_config_12_mhz, + .tuner_is_baseband = 1, + + .gpio_dir = DIB8000_GPIO_DEFAULT_DIRECTIONS, + .gpio_val = DIB8000_GPIO_DEFAULT_VALUES, + .gpio_pwm_pos = DIB8000_GPIO_DEFAULT_PWM_POS, + + .hostbus_diversity = 1, + .agc_control = &dib0070_ctrl_agc_filter, + .output_mode = OUTMODE_MPEG2_FIFO, + .drives = 0x2d98, + } +}; + +static int dib807x_tuner_reset(struct dvb_frontend *fe, int onoff) +{ + return dib8000_set_gpio(fe, 5, 0, !onoff); +} + +static int dib807x_tuner_sleep(struct dvb_frontend *fe, int onoff) +{ + return dib8000_set_gpio(fe, 0, 0, onoff); +} + +static const struct dib0070_wbd_gain_cfg dib8070_wbd_gain_cfg[] = { + { 240, 7}, + { 0xffff, 6}, +}; + +static struct dib0070_config dib807x_dib0070_config[2] = { + { + .i2c_address = DEFAULT_DIB0070_I2C_ADDRESS, + .reset = dib807x_tuner_reset, + .sleep = dib807x_tuner_sleep, + .clock_khz = 12000, + .clock_pad_drive = 4, + .vga_filter = 1, + .force_crystal_mode = 1, + .enable_third_order_filter = 1, + .charge_pump = 0, + .wbd_gain = dib8070_wbd_gain_cfg, + .osc_buffer_state = 0, + .freq_offset_khz_uhf = -100, + .freq_offset_khz_vhf = -100, + }, { + .i2c_address = DEFAULT_DIB0070_I2C_ADDRESS, + .reset = dib807x_tuner_reset, + .sleep = dib807x_tuner_sleep, + .clock_khz = 12000, + .clock_pad_drive = 2, + .vga_filter = 1, + .force_crystal_mode = 1, + .enable_third_order_filter = 1, + .charge_pump = 0, + .wbd_gain = dib8070_wbd_gain_cfg, + .osc_buffer_state = 0, + .freq_offset_khz_uhf = -25, + .freq_offset_khz_vhf = -25, + } +}; + +static int dib807x_set_param_override(struct dvb_frontend *fe, + struct dvb_frontend_parameters *fep) +{ + struct dvb_usb_adapter *adap = fe->dvb->priv; + struct dib0700_adapter_state *state = adap->priv; + + u16 offset = dib0070_wbd_offset(fe); + u8 band = BAND_OF_FREQUENCY(fep->frequency/1000); + switch (band) { + case BAND_VHF: + offset += 750; + break; + case BAND_UHF: /* fall-thru wanted */ + default: + offset += 250; break; + } + deb_info("WBD for DiB8000: %d\n", offset); + dib8000_set_wbd_ref(fe, offset); + + return state->set_param_save(fe, fep); +} + +static int dib807x_tuner_attach(struct dvb_usb_adapter *adap) +{ + struct dib0700_adapter_state *st = adap->priv; + struct i2c_adapter *tun_i2c = dib8000_get_i2c_master(adap->fe, + DIBX000_I2C_INTERFACE_TUNER, 1); + + if (adap->id == 0) { + if (dvb_attach(dib0070_attach, adap->fe, tun_i2c, + &dib807x_dib0070_config[0]) == NULL) + return -ENODEV; + } else { + if (dvb_attach(dib0070_attach, adap->fe, tun_i2c, + &dib807x_dib0070_config[1]) == NULL) + return -ENODEV; + } + + st->set_param_save = adap->fe->ops.tuner_ops.set_params; + adap->fe->ops.tuner_ops.set_params = dib807x_set_param_override; + return 0; +} + + +/* STK807x */ +static int stk807x_frontend_attach(struct dvb_usb_adapter *adap) +{ + dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1); + msleep(10); + dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1); + dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1); + dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1); + + dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0); + + dib0700_ctrl_clock(adap->dev, 72, 1); + + msleep(10); + dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1); + msleep(10); + dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1); + + dib8000_i2c_enumeration(&adap->dev->i2c_adap, 1, 18, + 0x80); + + adap->fe = dvb_attach(dib8000_attach, &adap->dev->i2c_adap, 0x80, + &dib807x_dib8000_config[0]); + + return adap->fe == NULL ? -ENODEV : 0; +} + +/* STK807xPVR */ +static int stk807xpvr_frontend_attach0(struct dvb_usb_adapter *adap) +{ + dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 0); + msleep(30); + dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1); + msleep(500); + dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1); + dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1); + dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1); + + dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0); + + dib0700_ctrl_clock(adap->dev, 72, 1); + + msleep(10); + dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1); + msleep(10); + dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1); + + /* initialize IC 0 */ + dib8000_i2c_enumeration(&adap->dev->i2c_adap, 1, 0x12, 0x80); + + adap->fe = dvb_attach(dib8000_attach, &adap->dev->i2c_adap, 0x80, + &dib807x_dib8000_config[0]); + + return adap->fe == NULL ? -ENODEV : 0; +} + +static int stk807xpvr_frontend_attach1(struct dvb_usb_adapter *adap) +{ + /* initialize IC 1 */ + dib8000_i2c_enumeration(&adap->dev->i2c_adap, 1, 0x22, 0x82); + + adap->fe = dvb_attach(dib8000_attach, &adap->dev->i2c_adap, 0x82, + &dib807x_dib8000_config[1]); + + return adap->fe == NULL ? -ENODEV : 0; +} + + /* STK7070PD */ static struct dib7000p_config stk7070pd_dib7000p_config[2] = { { @@ -1500,7 +1852,15 @@ struct usb_device_id dib0700_usb_id_table[] = { { USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_T3) }, { USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_T5) }, { USB_DEVICE(USB_VID_YUAN, USB_PID_YUAN_STK7700D) }, - { USB_DEVICE(USB_VID_YUAN, USB_PID_YUAN_STK7700D_2) }, +/* 55 */{ USB_DEVICE(USB_VID_YUAN, USB_PID_YUAN_STK7700D_2) }, + { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV73A) }, + { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV73ESE) }, + { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV282E) }, + { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK7770P) }, +/* 60 */{ USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_CINERGY_T_XXS_2) }, + { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK807XPVR) }, + { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK807XP) }, + { USB_DEVICE(USB_VID_PIXELVIEW, USB_PID_PIXELVIEW_SBTVD) }, { 0 } /* Terminating entry */ }; MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table); @@ -1565,7 +1925,7 @@ struct dvb_usb_device_properties dib0700_devices[] = { { NULL }, }, { "Leadtek Winfast DTV Dongle (STK7700P based)", - { &dib0700_usb_id_table[8], &dib0700_usb_id_table[34] }, + { &dib0700_usb_id_table[8] }, { NULL }, }, { "AVerMedia AVerTV DVB-T Express", @@ -1762,6 +2122,41 @@ struct dvb_usb_device_properties dib0700_devices[] = { .rc_key_map_size = ARRAY_SIZE(dib0700_rc_keys), .rc_query = dib0700_rc_query + }, { DIB0700_DEFAULT_DEVICE_PROPERTIES, + + .num_adapters = 1, + .adapter = { + { + .frontend_attach = stk7070p_frontend_attach, + .tuner_attach = dib7070p_tuner_attach, + + DIB0700_DEFAULT_STREAMING_CONFIG(0x02), + + .size_of_priv = sizeof(struct dib0700_adapter_state), + }, + }, + + .num_device_descs = 3, + .devices = { + { "Pinnacle PCTV 73A", + { &dib0700_usb_id_table[56], NULL }, + { NULL }, + }, + { "Pinnacle PCTV 73e SE", + { &dib0700_usb_id_table[57], NULL }, + { NULL }, + }, + { "Pinnacle PCTV 282e", + { &dib0700_usb_id_table[58], NULL }, + { NULL }, + }, + }, + + .rc_interval = DEFAULT_RC_INTERVAL, + .rc_key_map = dib0700_rc_keys, + .rc_key_map_size = ARRAY_SIZE(dib0700_rc_keys), + .rc_query = dib0700_rc_query + }, { DIB0700_DEFAULT_DEVICE_PROPERTIES, .num_adapters = 2, @@ -1927,6 +2322,102 @@ struct dvb_usb_device_properties dib0700_devices[] = { { NULL }, }, }, + }, { DIB0700_DEFAULT_DEVICE_PROPERTIES, + + .num_adapters = 1, + .adapter = { + { + .frontend_attach = stk7070p_frontend_attach, + .tuner_attach = dib7770p_tuner_attach, + + DIB0700_DEFAULT_STREAMING_CONFIG(0x02), + + .size_of_priv = + sizeof(struct dib0700_adapter_state), + }, + }, + + .num_device_descs = 2, + .devices = { + { "DiBcom STK7770P reference design", + { &dib0700_usb_id_table[59], NULL }, + { NULL }, + }, + { "Terratec Cinergy T USB XXS (HD)", + { &dib0700_usb_id_table[34], &dib0700_usb_id_table[60] }, + { NULL }, + }, + }, + .rc_interval = DEFAULT_RC_INTERVAL, + .rc_key_map = dib0700_rc_keys, + .rc_key_map_size = ARRAY_SIZE(dib0700_rc_keys), + .rc_query = dib0700_rc_query + }, { DIB0700_DEFAULT_DEVICE_PROPERTIES, + .num_adapters = 1, + .adapter = { + { + .frontend_attach = stk807x_frontend_attach, + .tuner_attach = dib807x_tuner_attach, + + DIB0700_DEFAULT_STREAMING_CONFIG(0x02), + + .size_of_priv = + sizeof(struct dib0700_adapter_state), + }, + }, + + .num_device_descs = 2, + .devices = { + { "DiBcom STK807xP reference design", + { &dib0700_usb_id_table[62], NULL }, + { NULL }, + }, + { "Prolink Pixelview SBTVD", + { &dib0700_usb_id_table[63], NULL }, + { NULL }, + }, + }, + + .rc_interval = DEFAULT_RC_INTERVAL, + .rc_key_map = dib0700_rc_keys, + .rc_key_map_size = ARRAY_SIZE(dib0700_rc_keys), + .rc_query = dib0700_rc_query + + }, { DIB0700_DEFAULT_DEVICE_PROPERTIES, + .num_adapters = 2, + .adapter = { + { + .frontend_attach = stk807xpvr_frontend_attach0, + .tuner_attach = dib807x_tuner_attach, + + DIB0700_DEFAULT_STREAMING_CONFIG(0x02), + + .size_of_priv = + sizeof(struct dib0700_adapter_state), + }, + { + .frontend_attach = stk807xpvr_frontend_attach1, + .tuner_attach = dib807x_tuner_attach, + + DIB0700_DEFAULT_STREAMING_CONFIG(0x03), + + .size_of_priv = + sizeof(struct dib0700_adapter_state), + }, + }, + + .num_device_descs = 1, + .devices = { + { "DiBcom STK807xPVR reference design", + { &dib0700_usb_id_table[61], NULL }, + { NULL }, + }, + }, + + .rc_interval = DEFAULT_RC_INTERVAL, + .rc_key_map = dib0700_rc_keys, + .rc_key_map_size = ARRAY_SIZE(dib0700_rc_keys), + .rc_query = dib0700_rc_query }, }; diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h index 185a5069b10b..a548c14c1944 100644 --- a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h +++ b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h @@ -46,6 +46,7 @@ #define USB_VID_MSI_2 0x1462 #define USB_VID_OPERA1 0x695c #define USB_VID_PINNACLE 0x2304 +#define USB_VID_PIXELVIEW 0x1554 #define USB_VID_TECHNOTREND 0x0b48 #define USB_VID_TERRATEC 0x0ccd #define USB_VID_TELESTAR 0x10b9 @@ -59,6 +60,7 @@ #define USB_VID_YUAN 0x1164 #define USB_VID_XTENSIONS 0x1ae7 #define USB_VID_HUMAX_COEX 0x10b9 +#define USB_VID_774 0x7a69 /* Product IDs */ #define USB_PID_ADSTECH_USB2_COLD 0xa333 @@ -95,7 +97,10 @@ #define USB_PID_DIBCOM_STK7700_U7000 0x7001 #define USB_PID_DIBCOM_STK7070P 0x1ebc #define USB_PID_DIBCOM_STK7070PD 0x1ebe +#define USB_PID_DIBCOM_STK807XP 0x1f90 +#define USB_PID_DIBCOM_STK807XPVR 0x1f98 #define USB_PID_DIBCOM_ANCHOR_2135_COLD 0x2131 +#define USB_PID_DIBCOM_STK7770P 0x1e80 #define USB_PID_DPOSH_M9206_COLD 0x9206 #define USB_PID_DPOSH_M9206_WARM 0xa090 #define USB_PID_UNIWILL_STK7700P 0x6003 @@ -184,6 +189,7 @@ #define USB_PID_TERRATEC_CINERGY_HT_EXPRESS 0x0060 #define USB_PID_TERRATEC_CINERGY_T_EXPRESS 0x0062 #define USB_PID_TERRATEC_CINERGY_T_XXS 0x0078 +#define USB_PID_TERRATEC_CINERGY_T_XXS_2 0x00ab #define USB_PID_TERRATEC_T3 0x10a0 #define USB_PID_TERRATEC_T5 0x10a1 #define USB_PID_PINNACLE_EXPRESSCARD_320CX 0x022e @@ -195,6 +201,10 @@ #define USB_PID_PINNACLE_PCTV73E 0x0237 #define USB_PID_PINNACLE_PCTV801E 0x023a #define USB_PID_PINNACLE_PCTV801E_SE 0x023b +#define USB_PID_PINNACLE_PCTV73A 0x0243 +#define USB_PID_PINNACLE_PCTV73ESE 0x0245 +#define USB_PID_PINNACLE_PCTV282E 0x0248 +#define USB_PID_PIXELVIEW_SBTVD 0x5010 #define USB_PID_PCTV_200E 0x020e #define USB_PID_PCTV_400E 0x020f #define USB_PID_PCTV_450E 0x0222 @@ -265,5 +275,6 @@ #define USB_PID_ELGATO_EYETV_DTT_Dlx 0x0020 #define USB_PID_DVB_T_USB_STICK_HIGH_SPEED_COLD 0x5000 #define USB_PID_DVB_T_USB_STICK_HIGH_SPEED_WARM 0x5001 +#define USB_PID_FRIIO_WHITE 0x0001 #endif diff --git a/drivers/media/dvb/dvb-usb/friio-fe.c b/drivers/media/dvb/dvb-usb/friio-fe.c new file mode 100644 index 000000000000..c4dfe25cf60d --- /dev/null +++ b/drivers/media/dvb/dvb-usb/friio-fe.c @@ -0,0 +1,483 @@ +/* DVB USB compliant Linux driver for the Friio USB2.0 ISDB-T receiver. + * + * Copyright (C) 2009 Akihiro Tsukada + * + * This module is based off the the gl861 and vp702x modules. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation, version 2. + * + * see Documentation/dvb/README.dvb-usb for more information + */ +#include +#include +#include + +#include "friio.h" + +struct jdvbt90502_state { + struct i2c_adapter *i2c; + struct dvb_frontend frontend; + struct jdvbt90502_config config; +}; + +/* NOTE: TC90502 has 16bit register-address? */ +/* register 0x0100 is used for reading PLL status, so reg is u16 here */ +static int jdvbt90502_reg_read(struct jdvbt90502_state *state, + const u16 reg, u8 *buf, const size_t count) +{ + int ret; + u8 wbuf[3]; + struct i2c_msg msg[2]; + + wbuf[0] = reg & 0xFF; + wbuf[1] = 0; + wbuf[2] = reg >> 8; + + msg[0].addr = state->config.demod_address; + msg[0].flags = 0; + msg[0].buf = wbuf; + msg[0].len = sizeof(wbuf); + + msg[1].addr = msg[0].addr; + msg[1].flags = I2C_M_RD; + msg[1].buf = buf; + msg[1].len = count; + + ret = i2c_transfer(state->i2c, msg, 2); + if (ret != 2) { + deb_fe(" reg read failed.\n"); + return -EREMOTEIO; + } + return 0; +} + +/* currently 16bit register-address is not used, so reg is u8 here */ +static int jdvbt90502_single_reg_write(struct jdvbt90502_state *state, + const u8 reg, const u8 val) +{ + struct i2c_msg msg; + u8 wbuf[2]; + + wbuf[0] = reg; + wbuf[1] = val; + + msg.addr = state->config.demod_address; + msg.flags = 0; + msg.buf = wbuf; + msg.len = sizeof(wbuf); + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + deb_fe(" reg write failed."); + return -EREMOTEIO; + } + return 0; +} + +static int _jdvbt90502_write(struct dvb_frontend *fe, u8 *buf, int len) +{ + struct jdvbt90502_state *state = fe->demodulator_priv; + int err, i; + for (i = 0; i < len - 1; i++) { + err = jdvbt90502_single_reg_write(state, + buf[0] + i, buf[i + 1]); + if (err) + return err; + } + + return 0; +} + +/* read pll status byte via the demodulator's I2C register */ +/* note: Win box reads it by 8B block at the I2C addr 0x30 from reg:0x80 */ +static int jdvbt90502_pll_read(struct jdvbt90502_state *state, u8 *result) +{ + int ret; + + /* +1 for reading */ + u8 pll_addr_byte = (state->config.pll_address << 1) + 1; + + *result = 0; + + ret = jdvbt90502_single_reg_write(state, JDVBT90502_2ND_I2C_REG, + pll_addr_byte); + if (ret) + goto error; + + ret = jdvbt90502_reg_read(state, 0x0100, result, 1); + if (ret) + goto error; + + deb_fe("PLL read val:%02x\n", *result); + return 0; + +error: + deb_fe("%s:ret == %d\n", __func__, ret); + return -EREMOTEIO; +} + + +/* set pll frequency via the demodulator's I2C register */ +static int jdvbt90502_pll_set_freq(struct jdvbt90502_state *state, u32 freq) +{ + int ret; + int retry; + u8 res1; + u8 res2[9]; + + u8 pll_freq_cmd[PLL_CMD_LEN]; + u8 pll_agc_cmd[PLL_CMD_LEN]; + struct i2c_msg msg[2]; + u32 f; + + deb_fe("%s: freq=%d, step=%d\n", __func__, freq, + state->frontend.ops.info.frequency_stepsize); + /* freq -> oscilator frequency conversion. */ + /* freq: 473,000,000 + n*6,000,000 (no 1/7MHz shift to center freq) */ + /* add 400[1/7 MHZ] = 57.142857MHz. 57MHz for the IF, */ + /* 1/7MHz for center freq shift */ + f = freq / state->frontend.ops.info.frequency_stepsize; + f += 400; + pll_freq_cmd[DEMOD_REDIRECT_REG] = JDVBT90502_2ND_I2C_REG; /* 0xFE */ + pll_freq_cmd[ADDRESS_BYTE] = state->config.pll_address << 1; + pll_freq_cmd[DIVIDER_BYTE1] = (f >> 8) & 0x7F; + pll_freq_cmd[DIVIDER_BYTE2] = f & 0xFF; + pll_freq_cmd[CONTROL_BYTE] = 0xB2; /* ref.divider:28, 4MHz/28=1/7MHz */ + pll_freq_cmd[BANDSWITCH_BYTE] = 0x08; /* UHF band */ + + msg[0].addr = state->config.demod_address; + msg[0].flags = 0; + msg[0].buf = pll_freq_cmd; + msg[0].len = sizeof(pll_freq_cmd); + + ret = i2c_transfer(state->i2c, &msg[0], 1); + if (ret != 1) + goto error; + + udelay(50); + + pll_agc_cmd[DEMOD_REDIRECT_REG] = pll_freq_cmd[DEMOD_REDIRECT_REG]; + pll_agc_cmd[ADDRESS_BYTE] = pll_freq_cmd[ADDRESS_BYTE]; + pll_agc_cmd[DIVIDER_BYTE1] = pll_freq_cmd[DIVIDER_BYTE1]; + pll_agc_cmd[DIVIDER_BYTE2] = pll_freq_cmd[DIVIDER_BYTE2]; + pll_agc_cmd[CONTROL_BYTE] = 0x9A; /* AGC_CTRL instead of BANDSWITCH */ + pll_agc_cmd[AGC_CTRL_BYTE] = 0x50; + /* AGC Time Constant 2s, AGC take-over point:103dBuV(lowest) */ + + msg[1].addr = msg[0].addr; + msg[1].flags = 0; + msg[1].buf = pll_agc_cmd; + msg[1].len = sizeof(pll_agc_cmd); + + ret = i2c_transfer(state->i2c, &msg[1], 1); + if (ret != 1) + goto error; + + /* I don't know what these cmds are for, */ + /* but the USB log on a windows box contains them */ + ret = jdvbt90502_single_reg_write(state, 0x01, 0x40); + ret |= jdvbt90502_single_reg_write(state, 0x01, 0x00); + if (ret) + goto error; + udelay(100); + + /* wait for the demod to be ready? */ +#define RETRY_COUNT 5 + for (retry = 0; retry < RETRY_COUNT; retry++) { + ret = jdvbt90502_reg_read(state, 0x0096, &res1, 1); + if (ret) + goto error; + /* if (res1 != 0x00) goto error; */ + ret = jdvbt90502_reg_read(state, 0x00B0, res2, sizeof(res2)); + if (ret) + goto error; + if (res2[0] >= 0xA7) + break; + msleep(100); + } + if (retry >= RETRY_COUNT) { + deb_fe("%s: FE does not get ready after freq setting.\n", + __func__); + return -EREMOTEIO; + } + + return 0; +error: + deb_fe("%s:ret == %d\n", __func__, ret); + return -EREMOTEIO; +} + +static int jdvbt90502_read_status(struct dvb_frontend *fe, fe_status_t *state) +{ + u8 result; + int ret; + + *state = FE_HAS_SIGNAL; + + ret = jdvbt90502_pll_read(fe->demodulator_priv, &result); + if (ret) { + deb_fe("%s:ret == %d\n", __func__, ret); + return -EREMOTEIO; + } + + *state = FE_HAS_SIGNAL + | FE_HAS_CARRIER + | FE_HAS_VITERBI + | FE_HAS_SYNC; + + if (result & PLL_STATUS_LOCKED) + *state |= FE_HAS_LOCK; + + return 0; +} + +static int jdvbt90502_read_ber(struct dvb_frontend *fe, u32 *ber) +{ + *ber = 0; + return 0; +} + +static int jdvbt90502_read_signal_strength(struct dvb_frontend *fe, + u16 *strength) +{ + int ret; + u8 rbuf[37]; + + *strength = 0; + + /* status register (incl. signal strength) : 0x89 */ + /* TODO: read just the necessary registers [0x8B..0x8D]? */ + ret = jdvbt90502_reg_read(fe->demodulator_priv, 0x0089, + rbuf, sizeof(rbuf)); + + if (ret) { + deb_fe("%s:ret == %d\n", __func__, ret); + return -EREMOTEIO; + } + + /* signal_strength: rbuf[2-4] (24bit BE), use lower 16bit for now. */ + *strength = (rbuf[3] << 8) + rbuf[4]; + if (rbuf[2]) + *strength = 0xffff; + + return 0; +} + +static int jdvbt90502_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + *snr = 0x0101; + return 0; +} + +static int jdvbt90502_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + *ucblocks = 0; + return 0; +} + +static int jdvbt90502_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *fs) +{ + fs->min_delay_ms = 500; + fs->step_size = 0; + fs->max_drift = 0; + + return 0; +} + +static int jdvbt90502_get_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +{ + p->inversion = INVERSION_AUTO; + p->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; + p->u.ofdm.code_rate_HP = FEC_AUTO; + p->u.ofdm.code_rate_LP = FEC_AUTO; + p->u.ofdm.constellation = QAM_64; + p->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO; + p->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO; + p->u.ofdm.hierarchy_information = HIERARCHY_AUTO; + return 0; +} + +static int jdvbt90502_set_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +{ + /** + * NOTE: ignore all the paramters except frequency. + * others should be fixed to the proper value for ISDB-T, + * but don't check here. + */ + + struct jdvbt90502_state *state = fe->demodulator_priv; + int ret; + + deb_fe("%s: Freq:%d\n", __func__, p->frequency); + + ret = jdvbt90502_pll_set_freq(state, p->frequency); + if (ret) { + deb_fe("%s:ret == %d\n", __func__, ret); + return -EREMOTEIO; + } + + return 0; +} + +static int jdvbt90502_sleep(struct dvb_frontend *fe) +{ + deb_fe("%s called.\n", __func__); + return 0; +} + + +/** + * (reg, val) commad list to initialize this module. + * captured on a Windows box. + */ +static u8 init_code[][2] = { + {0x01, 0x40}, + {0x04, 0x38}, + {0x05, 0x40}, + {0x07, 0x40}, + {0x0F, 0x4F}, + {0x11, 0x21}, + {0x12, 0x0B}, + {0x13, 0x2F}, + {0x14, 0x31}, + {0x16, 0x02}, + {0x21, 0xC4}, + {0x22, 0x20}, + {0x2C, 0x79}, + {0x2D, 0x34}, + {0x2F, 0x00}, + {0x30, 0x28}, + {0x31, 0x31}, + {0x32, 0xDF}, + {0x38, 0x01}, + {0x39, 0x78}, + {0x3B, 0x33}, + {0x3C, 0x33}, + {0x48, 0x90}, + {0x51, 0x68}, + {0x5E, 0x38}, + {0x71, 0x00}, + {0x72, 0x08}, + {0x77, 0x00}, + {0xC0, 0x21}, + {0xC1, 0x10}, + {0xE4, 0x1A}, + {0xEA, 0x1F}, + {0x77, 0x00}, + {0x71, 0x00}, + {0x71, 0x00}, + {0x76, 0x0C}, +}; + +const static int init_code_len = sizeof(init_code) / sizeof(u8[2]); + +static int jdvbt90502_init(struct dvb_frontend *fe) +{ + int i = -1; + int ret; + struct i2c_msg msg; + + struct jdvbt90502_state *state = fe->demodulator_priv; + + deb_fe("%s called.\n", __func__); + + msg.addr = state->config.demod_address; + msg.flags = 0; + msg.len = 2; + for (i = 0; i < init_code_len; i++) { + msg.buf = init_code[i]; + ret = i2c_transfer(state->i2c, &msg, 1); + if (ret != 1) + goto error; + } + msleep(100); + + return 0; + +error: + deb_fe("%s: init_code[%d] failed. ret==%d\n", __func__, i, ret); + return -EREMOTEIO; +} + + +static void jdvbt90502_release(struct dvb_frontend *fe) +{ + struct jdvbt90502_state *state = fe->demodulator_priv; + kfree(state); +} + + +static struct dvb_frontend_ops jdvbt90502_ops; + +struct dvb_frontend *jdvbt90502_attach(struct dvb_usb_device *d) +{ + struct jdvbt90502_state *state = NULL; + + deb_info("%s called.\n", __func__); + + /* allocate memory for the internal state */ + state = kzalloc(sizeof(struct jdvbt90502_state), GFP_KERNEL); + if (state == NULL) + goto error; + + /* setup the state */ + state->i2c = &d->i2c_adap; + memcpy(&state->config, &friio_fe_config, sizeof(friio_fe_config)); + + /* create dvb_frontend */ + memcpy(&state->frontend.ops, &jdvbt90502_ops, + sizeof(jdvbt90502_ops)); + state->frontend.demodulator_priv = state; + + if (jdvbt90502_init(&state->frontend) < 0) + goto error; + + return &state->frontend; + +error: + kfree(state); + return NULL; +} + +static struct dvb_frontend_ops jdvbt90502_ops = { + + .info = { + .name = "Comtech JDVBT90502 ISDB-T", + .type = FE_OFDM, + .frequency_min = 473000000, /* UHF 13ch, center */ + .frequency_max = 767142857, /* UHF 62ch, center */ + .frequency_stepsize = JDVBT90502_PLL_CLK / + JDVBT90502_PLL_DIVIDER, + .frequency_tolerance = 0, + + /* NOTE: this driver ignores all parameters but frequency. */ + .caps = FE_CAN_INVERSION_AUTO | + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | + FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | + FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO | + FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | + FE_CAN_HIERARCHY_AUTO, + }, + + .release = jdvbt90502_release, + + .init = jdvbt90502_init, + .sleep = jdvbt90502_sleep, + .write = _jdvbt90502_write, + + .set_frontend = jdvbt90502_set_frontend, + .get_frontend = jdvbt90502_get_frontend, + .get_tune_settings = jdvbt90502_get_tune_settings, + + .read_status = jdvbt90502_read_status, + .read_ber = jdvbt90502_read_ber, + .read_signal_strength = jdvbt90502_read_signal_strength, + .read_snr = jdvbt90502_read_snr, + .read_ucblocks = jdvbt90502_read_ucblocks, +}; diff --git a/drivers/media/dvb/dvb-usb/friio.c b/drivers/media/dvb/dvb-usb/friio.c new file mode 100644 index 000000000000..14a65b4aec07 --- /dev/null +++ b/drivers/media/dvb/dvb-usb/friio.c @@ -0,0 +1,525 @@ +/* DVB USB compliant Linux driver for the Friio USB2.0 ISDB-T receiver. + * + * Copyright (C) 2009 Akihiro Tsukada + * + * This module is based off the the gl861 and vp702x modules. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation, version 2. + * + * see Documentation/dvb/README.dvb-usb for more information + */ +#include "friio.h" + +/* debug */ +int dvb_usb_friio_debug; +module_param_named(debug, dvb_usb_friio_debug, int, 0644); +MODULE_PARM_DESC(debug, + "set debugging level (1=info,2=xfer,4=rc,8=fe (or-able))." + DVB_USB_DEBUG_STATUS); + +DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); + +/** + * Indirect I2C access to the PLL via FE. + * whole I2C protocol data to the PLL is sent via the FE's I2C register. + * This is done by a control msg to the FE with the I2C data accompanied, and + * a specific USB request number is assigned for that purpose. + * + * this func sends wbuf[1..] to the I2C register wbuf[0] at addr (= at FE). + * TODO: refoctored, smarter i2c functions. + */ +static int gl861_i2c_ctrlmsg_data(struct dvb_usb_device *d, u8 addr, + u8 *wbuf, u16 wlen, u8 *rbuf, u16 rlen) +{ + u16 index = wbuf[0]; /* must be JDVBT90502_2ND_I2C_REG(=0xFE) */ + u16 value = addr << (8 + 1); + int wo = (rbuf == NULL || rlen == 0); /* write only */ + u8 req, type; + + deb_xfer("write to PLL:0x%02x via FE reg:0x%02x, len:%d\n", + wbuf[1], wbuf[0], wlen - 1); + + if (wo && wlen >= 2) { + req = GL861_REQ_I2C_DATA_CTRL_WRITE; + type = GL861_WRITE; + udelay(20); + return usb_control_msg(d->udev, usb_sndctrlpipe(d->udev, 0), + req, type, value, index, + &wbuf[1], wlen - 1, 2000); + } + + deb_xfer("not supported ctrl-msg, aborting."); + return -EINVAL; +} + +/* normal I2C access (without extra data arguments). + * write to the register wbuf[0] at I2C address addr with the value wbuf[1], + * or read from the register wbuf[0]. + * register address can be 16bit (wbuf[2]<<8 | wbuf[0]) if wlen==3 + */ +static int gl861_i2c_msg(struct dvb_usb_device *d, u8 addr, + u8 *wbuf, u16 wlen, u8 *rbuf, u16 rlen) +{ + u16 index; + u16 value = addr << (8 + 1); + int wo = (rbuf == NULL || rlen == 0); /* write-only */ + u8 req, type; + unsigned int pipe; + + /* special case for the indirect I2C access to the PLL via FE, */ + if (addr == friio_fe_config.demod_address && + wbuf[0] == JDVBT90502_2ND_I2C_REG) + return gl861_i2c_ctrlmsg_data(d, addr, wbuf, wlen, rbuf, rlen); + + if (wo) { + req = GL861_REQ_I2C_WRITE; + type = GL861_WRITE; + pipe = usb_sndctrlpipe(d->udev, 0); + } else { /* rw */ + req = GL861_REQ_I2C_READ; + type = GL861_READ; + pipe = usb_rcvctrlpipe(d->udev, 0); + } + + switch (wlen) { + case 1: + index = wbuf[0]; + break; + case 2: + index = wbuf[0]; + value = value + wbuf[1]; + break; + case 3: + /* special case for 16bit register-address */ + index = (wbuf[2] << 8) | wbuf[0]; + value = value + wbuf[1]; + break; + default: + deb_xfer("wlen = %x, aborting.", wlen); + return -EINVAL; + } + msleep(1); + return usb_control_msg(d->udev, pipe, req, type, + value, index, rbuf, rlen, 2000); +} + +/* I2C */ +static int gl861_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], + int num) +{ + struct dvb_usb_device *d = i2c_get_adapdata(adap); + int i; + + + if (num > 2) + return -EINVAL; + + if (mutex_lock_interruptible(&d->i2c_mutex) < 0) + return -EAGAIN; + + for (i = 0; i < num; i++) { + /* write/read request */ + if (i + 1 < num && (msg[i + 1].flags & I2C_M_RD)) { + if (gl861_i2c_msg(d, msg[i].addr, + msg[i].buf, msg[i].len, + msg[i + 1].buf, msg[i + 1].len) < 0) + break; + i++; + } else + if (gl861_i2c_msg(d, msg[i].addr, msg[i].buf, + msg[i].len, NULL, 0) < 0) + break; + } + + mutex_unlock(&d->i2c_mutex); + return i; +} + +static u32 gl861_i2c_func(struct i2c_adapter *adapter) +{ + return I2C_FUNC_I2C; +} + + +static int friio_ext_ctl(struct dvb_usb_adapter *adap, + u32 sat_color, int lnb_on) +{ + int i; + int ret; + struct i2c_msg msg; + u8 buf[2]; + u32 mask; + u8 lnb = (lnb_on) ? FRIIO_CTL_LNB : 0; + + msg.addr = 0x00; + msg.flags = 0; + msg.len = 2; + msg.buf = buf; + + buf[0] = 0x00; + + /* send 2bit header (&B10) */ + buf[1] = lnb | FRIIO_CTL_LED | FRIIO_CTL_STROBE; + ret = gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); + buf[1] |= FRIIO_CTL_CLK; + ret += gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); + + buf[1] = lnb | FRIIO_CTL_STROBE; + ret += gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); + buf[1] |= FRIIO_CTL_CLK; + ret += gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); + + /* send 32bit(satur, R, G, B) data in serial */ + mask = 1 << 31; + for (i = 0; i < 32; i++) { + buf[1] = lnb | FRIIO_CTL_STROBE; + if (sat_color & mask) + buf[1] |= FRIIO_CTL_LED; + ret += gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); + buf[1] |= FRIIO_CTL_CLK; + ret += gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); + mask >>= 1; + } + + /* set the strobe off */ + buf[1] = lnb; + ret += gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); + buf[1] |= FRIIO_CTL_CLK; + ret += gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); + + return (ret == 70); +} + + +static int friio_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff); + +/* TODO: move these init cmds to the FE's init routine? */ +static u8 streaming_init_cmds[][2] = { + {0x33, 0x08}, + {0x37, 0x40}, + {0x3A, 0x1F}, + {0x3B, 0xFF}, + {0x3C, 0x1F}, + {0x3D, 0xFF}, + {0x38, 0x00}, + {0x35, 0x00}, + {0x39, 0x00}, + {0x36, 0x00}, +}; +static int cmdlen = sizeof(streaming_init_cmds) / 2; + +/* + * Command sequence in this init function is a replay + * of the captured USB commands from the Windows proprietary driver. + */ +static int friio_initialize(struct dvb_usb_device *d) +{ + int ret; + int i; + int retry = 0; + u8 rbuf[2]; + u8 wbuf[3]; + + deb_info("%s called.\n", __func__); + + /* use gl861_i2c_msg instead of gl861_i2c_xfer(), */ + /* because the i2c device is not set up yet. */ + wbuf[0] = 0x11; + wbuf[1] = 0x02; + ret = gl861_i2c_msg(d, 0x00, wbuf, 2, NULL, 0); + if (ret < 0) + goto error; + msleep(2); + + wbuf[0] = 0x11; + wbuf[1] = 0x00; + ret = gl861_i2c_msg(d, 0x00, wbuf, 2, NULL, 0); + if (ret < 0) + goto error; + msleep(1); + + /* following msgs should be in the FE's init code? */ + /* cmd sequence to identify the device type? (friio black/white) */ + wbuf[0] = 0x03; + wbuf[1] = 0x80; + /* can't use gl861_i2c_cmd, as the register-addr is 16bit(0x0100) */ + ret = usb_control_msg(d->udev, usb_sndctrlpipe(d->udev, 0), + GL861_REQ_I2C_DATA_CTRL_WRITE, GL861_WRITE, + 0x1200, 0x0100, wbuf, 2, 2000); + if (ret < 0) + goto error; + + msleep(2); + wbuf[0] = 0x00; + wbuf[2] = 0x01; /* reg.0x0100 */ + wbuf[1] = 0x00; + ret = gl861_i2c_msg(d, 0x12 >> 1, wbuf, 3, rbuf, 2); + /* my Friio White returns 0xffff. */ + if (ret < 0 || rbuf[0] != 0xff || rbuf[1] != 0xff) + goto error; + + msleep(2); + wbuf[0] = 0x03; + wbuf[1] = 0x80; + ret = usb_control_msg(d->udev, usb_sndctrlpipe(d->udev, 0), + GL861_REQ_I2C_DATA_CTRL_WRITE, GL861_WRITE, + 0x9000, 0x0100, wbuf, 2, 2000); + if (ret < 0) + goto error; + + msleep(2); + wbuf[0] = 0x00; + wbuf[2] = 0x01; /* reg.0x0100 */ + wbuf[1] = 0x00; + ret = gl861_i2c_msg(d, 0x90 >> 1, wbuf, 3, rbuf, 2); + /* my Friio White returns 0xffff again. */ + if (ret < 0 || rbuf[0] != 0xff || rbuf[1] != 0xff) + goto error; + + msleep(1); + +restart: + /* ============ start DEMOD init cmds ================== */ + /* read PLL status to clear the POR bit */ + wbuf[0] = JDVBT90502_2ND_I2C_REG; + wbuf[1] = (FRIIO_PLL_ADDR << 1) + 1; /* +1 for reading */ + ret = gl861_i2c_msg(d, FRIIO_DEMOD_ADDR, wbuf, 2, NULL, 0); + if (ret < 0) + goto error; + + msleep(5); + /* note: DEMODULATOR has 16bit register-address. */ + wbuf[0] = 0x00; + wbuf[2] = 0x01; /* reg addr: 0x0100 */ + wbuf[1] = 0x00; /* val: not used */ + ret = gl861_i2c_msg(d, FRIIO_DEMOD_ADDR, wbuf, 3, rbuf, 1); + if (ret < 0) + goto error; +/* + msleep(1); + wbuf[0] = 0x80; + wbuf[1] = 0x00; + ret = gl861_i2c_msg(d, FRIIO_DEMOD_ADDR, wbuf, 2, rbuf, 1); + if (ret < 0) + goto error; + */ + if (rbuf[0] & 0x80) { /* still in PowerOnReset state? */ + if (++retry > 3) { + deb_info("failed to get the correct" + " FE demod status:0x%02x\n", rbuf[0]); + goto error; + } + msleep(100); + goto restart; + } + + /* TODO: check return value in rbuf */ + /* =========== end DEMOD init cmds ===================== */ + msleep(1); + + wbuf[0] = 0x30; + wbuf[1] = 0x04; + ret = gl861_i2c_msg(d, 0x00, wbuf, 2, NULL, 0); + if (ret < 0) + goto error; + + msleep(2); + /* following 2 cmds unnecessary? */ + wbuf[0] = 0x00; + wbuf[1] = 0x01; + ret = gl861_i2c_msg(d, 0x00, wbuf, 2, NULL, 0); + if (ret < 0) + goto error; + + wbuf[0] = 0x06; + wbuf[1] = 0x0F; + ret = gl861_i2c_msg(d, 0x00, wbuf, 2, NULL, 0); + if (ret < 0) + goto error; + + /* some streaming ctl cmds (maybe) */ + msleep(10); + for (i = 0; i < cmdlen; i++) { + ret = gl861_i2c_msg(d, 0x00, streaming_init_cmds[i], 2, + NULL, 0); + if (ret < 0) + goto error; + msleep(1); + } + msleep(20); + + /* change the LED color etc. */ + ret = friio_streaming_ctrl(&d->adapter[0], 0); + if (ret < 0) + goto error; + + return 0; + +error: + deb_info("%s:ret == %d\n", __func__, ret); + return -EIO; +} + +/* Callbacks for DVB USB */ + +static int friio_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff) +{ + int ret; + + deb_info("%s called.(%d)\n", __func__, onoff); + + /* set the LED color and saturation (and LNB on) */ + if (onoff) + ret = friio_ext_ctl(adap, 0x6400ff64, 1); + else + ret = friio_ext_ctl(adap, 0x96ff00ff, 1); + + if (ret != 1) { + deb_info("%s failed to send cmdx. ret==%d\n", __func__, ret); + return -EREMOTEIO; + } + return 0; +} + +static int friio_frontend_attach(struct dvb_usb_adapter *adap) +{ + if (friio_initialize(adap->dev) < 0) + return -EIO; + + adap->fe = jdvbt90502_attach(adap->dev); + if (adap->fe == NULL) + return -EIO; + + return 0; +} + +/* DVB USB Driver stuff */ +static struct dvb_usb_device_properties friio_properties; + +static int friio_probe(struct usb_interface *intf, + const struct usb_device_id *id) +{ + struct dvb_usb_device *d; + struct usb_host_interface *alt; + int ret; + + if (intf->num_altsetting < GL861_ALTSETTING_COUNT) + return -ENODEV; + + alt = usb_altnum_to_altsetting(intf, FRIIO_BULK_ALTSETTING); + if (alt == NULL) { + deb_rc("not alt found!\n"); + return -ENODEV; + } + ret = usb_set_interface(interface_to_usbdev(intf), + alt->desc.bInterfaceNumber, + alt->desc.bAlternateSetting); + if (ret != 0) { + deb_rc("failed to set alt-setting!\n"); + return ret; + } + + ret = dvb_usb_device_init(intf, &friio_properties, + THIS_MODULE, &d, adapter_nr); + if (ret == 0) + friio_streaming_ctrl(&d->adapter[0], 1); + + return ret; +} + + +struct jdvbt90502_config friio_fe_config = { + .demod_address = FRIIO_DEMOD_ADDR, + .pll_address = FRIIO_PLL_ADDR, +}; + +static struct i2c_algorithm gl861_i2c_algo = { + .master_xfer = gl861_i2c_xfer, + .functionality = gl861_i2c_func, +}; + +static struct usb_device_id friio_table[] = { + { USB_DEVICE(USB_VID_774, USB_PID_FRIIO_WHITE) }, + { } /* Terminating entry */ +}; +MODULE_DEVICE_TABLE(usb, friio_table); + + +static struct dvb_usb_device_properties friio_properties = { + .caps = DVB_USB_IS_AN_I2C_ADAPTER, + .usb_ctrl = DEVICE_SPECIFIC, + + .size_of_priv = 0, + + .num_adapters = 1, + .adapter = { + /* caps:0 => no pid filter, 188B TS packet */ + /* GL861 has a HW pid filter, but no info available. */ + { + .caps = 0, + + .frontend_attach = friio_frontend_attach, + .streaming_ctrl = friio_streaming_ctrl, + + .stream = { + .type = USB_BULK, + /* count <= MAX_NO_URBS_FOR_DATA_STREAM(10) */ + .count = 8, + .endpoint = 0x01, + .u = { + /* GL861 has 6KB buf inside */ + .bulk = { + .buffersize = 16384, + } + } + }, + } + }, + .i2c_algo = &gl861_i2c_algo, + + .num_device_descs = 1, + .devices = { + { + .name = "774 Friio ISDB-T USB2.0", + .cold_ids = { NULL }, + .warm_ids = { &friio_table[0], NULL }, + }, + } +}; + +static struct usb_driver friio_driver = { + .name = "dvb_usb_friio", + .probe = friio_probe, + .disconnect = dvb_usb_device_exit, + .id_table = friio_table, +}; + + +/* module stuff */ +static int __init friio_module_init(void) +{ + int ret; + + ret = usb_register(&friio_driver); + if (ret) + err("usb_register failed. Error number %d", ret); + + return ret; +} + + +static void __exit friio_module_exit(void) +{ + /* deregister this driver from the USB subsystem */ + usb_deregister(&friio_driver); +} + +module_init(friio_module_init); +module_exit(friio_module_exit); + +MODULE_AUTHOR("Akihiro Tsukada "); +MODULE_DESCRIPTION("Driver for Friio ISDB-T USB2.0 Receiver"); +MODULE_VERSION("0.2"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb/dvb-usb/friio.h b/drivers/media/dvb/dvb-usb/friio.h new file mode 100644 index 000000000000..af8d55e390fb --- /dev/null +++ b/drivers/media/dvb/dvb-usb/friio.h @@ -0,0 +1,99 @@ +/* DVB USB compliant Linux driver for the Friio USB2.0 ISDB-T receiver. + * + * Copyright (C) 2009 Akihiro Tsukada + * + * This module is based off the the gl861 and vp702x modules. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation, version 2. + * + * see Documentation/dvb/README.dvb-usb for more information + */ +#ifndef _DVB_USB_FRIIO_H_ +#define _DVB_USB_FRIIO_H_ + +/** + * Friio Components + * USB hub: AU4254 + * USB controller(+ TS dmx & streaming): GL861 + * Frontend: comtech JDVBT-90502 + * (tuner PLL: tua6034, I2C addr:(0xC0 >> 1)) + * (OFDM demodulator: TC90502, I2C addr:(0x30 >> 1)) + * LED x3 (+LNB) controll: PIC 16F676 + * EEPROM: 24C08 + * + * (USB smart card reader: AU9522) + * + */ + +#define DVB_USB_LOG_PREFIX "friio" +#include "dvb-usb.h" + +extern int dvb_usb_friio_debug; +#define deb_info(args...) dprintk(dvb_usb_friio_debug, 0x01, args) +#define deb_xfer(args...) dprintk(dvb_usb_friio_debug, 0x02, args) +#define deb_rc(args...) dprintk(dvb_usb_friio_debug, 0x04, args) +#define deb_fe(args...) dprintk(dvb_usb_friio_debug, 0x08, args) + +/* Vendor requests */ +#define GL861_WRITE 0x40 +#define GL861_READ 0xc0 + +/* command bytes */ +#define GL861_REQ_I2C_WRITE 0x01 +#define GL861_REQ_I2C_READ 0x02 +/* For control msg with data argument */ +/* Used for accessing the PLL on the secondary I2C bus of FE via GL861 */ +#define GL861_REQ_I2C_DATA_CTRL_WRITE 0x03 + +#define GL861_ALTSETTING_COUNT 2 +#define FRIIO_BULK_ALTSETTING 0 +#define FRIIO_ISOC_ALTSETTING 1 + +/* LED & LNB control via PIC. */ +/* basically, it's serial control with clock and strobe. */ +/* write the below 4bit control data to the reg 0x00 at the I2C addr 0x00 */ +/* when controlling the LEDs, 32bit(saturation, R, G, B) is sent on the bit3*/ +#define FRIIO_CTL_LNB (1 << 0) +#define FRIIO_CTL_STROBE (1 << 1) +#define FRIIO_CTL_CLK (1 << 2) +#define FRIIO_CTL_LED (1 << 3) + +/* Front End related */ + +#define FRIIO_DEMOD_ADDR (0x30 >> 1) +#define FRIIO_PLL_ADDR (0xC0 >> 1) + +#define JDVBT90502_PLL_CLK 4000000 +#define JDVBT90502_PLL_DIVIDER 28 + +#define JDVBT90502_2ND_I2C_REG 0xFE + +/* byte index for pll i2c command data structure*/ +/* see datasheet for tua6034 */ +#define DEMOD_REDIRECT_REG 0 +#define ADDRESS_BYTE 1 +#define DIVIDER_BYTE1 2 +#define DIVIDER_BYTE2 3 +#define CONTROL_BYTE 4 +#define BANDSWITCH_BYTE 5 +#define AGC_CTRL_BYTE 5 +#define PLL_CMD_LEN 6 + +/* bit masks for PLL STATUS response */ +#define PLL_STATUS_POR_MODE 0x80 /* 1: Power on Reset (test) Mode */ +#define PLL_STATUS_LOCKED 0x40 /* 1: locked */ +#define PLL_STATUS_AGC_ACTIVE 0x08 /* 1:active */ +#define PLL_STATUS_TESTMODE 0x07 /* digital output level (5 level) */ + /* 0.15Vcc step 0x00: < 0.15Vcc, ..., 0x04: >= 0.6Vcc (<= 1Vcc) */ + + +struct jdvbt90502_config { + u8 demod_address; /* i2c addr for demodulator IC */ + u8 pll_address; /* PLL addr on the secondary i2c*/ +}; +extern struct jdvbt90502_config friio_fe_config; + +extern struct dvb_frontend *jdvbt90502_attach(struct dvb_usb_device *d); +#endif diff --git a/drivers/media/dvb/dvb-usb/m920x.c b/drivers/media/dvb/dvb-usb/m920x.c index aec7a1943b66..ef9b7bed13ff 100644 --- a/drivers/media/dvb/dvb-usb/m920x.c +++ b/drivers/media/dvb/dvb-usb/m920x.c @@ -337,6 +337,8 @@ static int m920x_firmware_download(struct usb_device *udev, const struct firmwar int i, pass, ret = 0; buff = kmalloc(65536, GFP_KERNEL); + if (buff == NULL) + return -ENOMEM; if ((ret = m920x_read(udev, M9206_FILTER, 0x0, 0x8000, read, 4)) != 0) goto done; diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig index b794e860b4e2..d7c4837fa71c 100644 --- a/drivers/media/dvb/frontends/Kconfig +++ b/drivers/media/dvb/frontends/Kconfig @@ -484,6 +484,14 @@ config DVB_S921 AN ISDB-T DQPSK, QPSK, 16QAM and 64QAM 1seg tuner module. Say Y when you want to support this frontend. +config DVB_DIB8000 + tristate "DiBcom 8000MB/MC" + depends on DVB_CORE && I2C + default m if DVB_FE_CUSTOMISE + help + A driver for DiBcom's DiB8000 ISDB-T/ISDB-Tsb demodulator. + Say Y when you want to support this frontend. + comment "Digital terrestrial only tuners/PLL" depends on DVB_CORE diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile index 3b49d37ab5fa..3523767e7a76 100644 --- a/drivers/media/dvb/frontends/Makefile +++ b/drivers/media/dvb/frontends/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_DVB_DIB3000MB) += dib3000mb.o obj-$(CONFIG_DVB_DIB3000MC) += dib3000mc.o dibx000_common.o obj-$(CONFIG_DVB_DIB7000M) += dib7000m.o dibx000_common.o obj-$(CONFIG_DVB_DIB7000P) += dib7000p.o dibx000_common.o +obj-$(CONFIG_DVB_DIB8000) += dib8000.o dibx000_common.o obj-$(CONFIG_DVB_MT312) += mt312.o obj-$(CONFIG_DVB_VES1820) += ves1820.o obj-$(CONFIG_DVB_VES1X93) += ves1x93.o diff --git a/drivers/media/dvb/frontends/au8522_decoder.c b/drivers/media/dvb/frontends/au8522_decoder.c index 9e9a75576a1d..74981ee923c8 100644 --- a/drivers/media/dvb/frontends/au8522_decoder.c +++ b/drivers/media/dvb/frontends/au8522_decoder.c @@ -792,6 +792,11 @@ static int au8522_probe(struct i2c_client *client, } demod_config = kzalloc(sizeof(struct au8522_config), GFP_KERNEL); + if (demod_config == NULL) { + if (instance == 1) + kfree(state); + return -ENOMEM; + } demod_config->demod_address = 0x8e >> 1; state->config = demod_config; diff --git a/drivers/media/dvb/frontends/dib0070.c b/drivers/media/dvb/frontends/dib0070.c index da92cbe1b8ea..2be17b93e0bd 100644 --- a/drivers/media/dvb/frontends/dib0070.c +++ b/drivers/media/dvb/frontends/dib0070.c @@ -1,12 +1,29 @@ /* * Linux-DVB Driver for DiBcom's DiB0070 base-band RF Tuner. * - * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/) + * Copyright (C) 2005-9 DiBcom (http://www.dibcom.fr/) * * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation, version 2. + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * This code is more or less generated from another driver, please + * excuse some codingstyle oddities. + * */ + #include #include @@ -19,27 +36,65 @@ static int debug; module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "turn on debugging (default: 0)"); -#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB0070: "); printk(args); printk("\n"); } } while (0) +#define dprintk(args...) do { \ + if (debug) { \ + printk(KERN_DEBUG "DiB0070: "); \ + printk(args); \ + printk("\n"); \ + } \ +} while (0) #define DIB0070_P1D 0x00 #define DIB0070_P1F 0x01 #define DIB0070_P1G 0x03 #define DIB0070S_P1A 0x02 +enum frontend_tune_state { + CT_TUNER_START = 10, + CT_TUNER_STEP_0, + CT_TUNER_STEP_1, + CT_TUNER_STEP_2, + CT_TUNER_STEP_3, + CT_TUNER_STEP_4, + CT_TUNER_STEP_5, + CT_TUNER_STEP_6, + CT_TUNER_STEP_7, + CT_TUNER_STOP, +}; + +#define FE_CALLBACK_TIME_NEVER 0xffffffff + struct dib0070_state { struct i2c_adapter *i2c; struct dvb_frontend *fe; const struct dib0070_config *cfg; u16 wbd_ff_offset; u8 revision; + + enum frontend_tune_state tune_state; + u32 current_rf; + + /* for the captrim binary search */ + s8 step; + u16 adc_diff; + + s8 captrim; + s8 fcaptrim; + u16 lo4; + + const struct dib0070_tuning *current_tune_table_index; + const struct dib0070_lna_match *lna_match; + + u8 wbd_gain_current; + u16 wbd_offset_3_3[2]; }; static uint16_t dib0070_read_reg(struct dib0070_state *state, u8 reg) { u8 b[2]; struct i2c_msg msg[2] = { - { .addr = state->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 }, - { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = b, .len = 2 }, + {.addr = state->cfg->i2c_address,.flags = 0,.buf = ®,.len = 1}, + {.addr = state->cfg->i2c_address,.flags = I2C_M_RD,.buf = b,.len = 2}, }; if (i2c_transfer(state->i2c, msg, 2) != 2) { printk(KERN_WARNING "DiB0070 I2C read failed\n"); @@ -51,7 +106,7 @@ static uint16_t dib0070_read_reg(struct dib0070_state *state, u8 reg) static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val) { u8 b[3] = { reg, val >> 8, val & 0xff }; - struct i2c_msg msg = { .addr = state->cfg->i2c_address, .flags = 0, .buf = b, .len = 3 }; + struct i2c_msg msg = {.addr = state->cfg->i2c_address,.flags = 0,.buf = b,.len = 3 }; if (i2c_transfer(state->i2c, &msg, 1) != 1) { printk(KERN_WARNING "DiB0070 I2C write failed\n"); return -EREMOTEIO; @@ -59,55 +114,71 @@ static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val) return 0; } -#define HARD_RESET(state) do { if (state->cfg->reset) { state->cfg->reset(state->fe,1); msleep(10); state->cfg->reset(state->fe,0); msleep(10); } } while (0) +#define HARD_RESET(state) do { \ + state->cfg->sleep(state->fe, 0); \ + if (state->cfg->reset) { \ + state->cfg->reset(state->fe,1); msleep(10); \ + state->cfg->reset(state->fe,0); msleep(10); \ + } \ +} while (0) static int dib0070_set_bandwidth(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch) { - struct dib0070_state *st = fe->tuner_priv; - u16 tmp = 0; - tmp = dib0070_read_reg(st, 0x02) & 0x3fff; + struct dib0070_state *state = fe->tuner_priv; + u16 tmp = dib0070_read_reg(state, 0x02) & 0x3fff; + + if (state->fe->dtv_property_cache.bandwidth_hz / 1000 > 7000) + tmp |= (0 << 14); + else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 > 6000) + tmp |= (1 << 14); + else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 > 5000) + tmp |= (2 << 14); + else + tmp |= (3 << 14); - switch(BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)) { - case 8000: - tmp |= (0 << 14); - break; - case 7000: - tmp |= (1 << 14); - break; - case 6000: - tmp |= (2 << 14); - break; - case 5000: - default: - tmp |= (3 << 14); - break; + dib0070_write_reg(state, 0x02, tmp); + + /* sharpen the BB filter in ISDB-T to have higher immunity to adjacent channels */ + if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) { + u16 value = dib0070_read_reg(state, 0x17); + + dib0070_write_reg(state, 0x17, value & 0xfffc); + tmp = dib0070_read_reg(state, 0x01) & 0x01ff; + dib0070_write_reg(state, 0x01, tmp | (60 << 9)); + + dib0070_write_reg(state, 0x17, value); } - dib0070_write_reg(st, 0x02, tmp); return 0; } -static void dib0070_captrim(struct dib0070_state *st, u16 LO4) +static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state *tune_state) { - int8_t captrim, fcaptrim, step_sign, step; - u16 adc, adc_diff = 3000; + int8_t step_sign; + u16 adc; + int ret = 0; + if (*tune_state == CT_TUNER_STEP_0) { + dib0070_write_reg(state, 0x0f, 0xed10); + dib0070_write_reg(state, 0x17, 0x0034); - dib0070_write_reg(st, 0x0f, 0xed10); - dib0070_write_reg(st, 0x17, 0x0034); + dib0070_write_reg(state, 0x18, 0x0032); + state->step = state->captrim = state->fcaptrim = 64; + state->adc_diff = 3000; + ret = 20; - dib0070_write_reg(st, 0x18, 0x0032); - msleep(2); + *tune_state = CT_TUNER_STEP_1; + } else if (*tune_state == CT_TUNER_STEP_1) { + state->step /= 2; + dib0070_write_reg(state, 0x14, state->lo4 | state->captrim); + ret = 15; - step = captrim = fcaptrim = 64; + *tune_state = CT_TUNER_STEP_2; + } else if (*tune_state == CT_TUNER_STEP_2) { - do { - step /= 2; - dib0070_write_reg(st, 0x14, LO4 | captrim); - msleep(1); - adc = dib0070_read_reg(st, 0x19); + adc = dib0070_read_reg(state, 0x19); - dprintk( "CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", captrim, adc, (u32) adc*(u32)1800/(u32)1024); + dprintk("CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", state->captrim, adc, (u32) adc * (u32) 1800 / (u32) 1024); if (adc >= 400) { adc -= 400; @@ -117,379 +188,430 @@ static void dib0070_captrim(struct dib0070_state *st, u16 LO4) step_sign = 1; } - if (adc < adc_diff) { - dprintk( "CAPTRIM=%hd is closer to target (%hd/%hd)", captrim, adc, adc_diff); - adc_diff = adc; - fcaptrim = captrim; + if (adc < state->adc_diff) { + dprintk("CAPTRIM=%hd is closer to target (%hd/%hd)", state->captrim, adc, state->adc_diff); + state->adc_diff = adc; + state->fcaptrim = state->captrim; + } + state->captrim += (step_sign * state->step); + if (state->step >= 1) + *tune_state = CT_TUNER_STEP_1; + else + *tune_state = CT_TUNER_STEP_3; - } - captrim += (step_sign * step); - } while (step >= 1); + } else if (*tune_state == CT_TUNER_STEP_3) { + dib0070_write_reg(state, 0x14, state->lo4 | state->fcaptrim); + dib0070_write_reg(state, 0x18, 0x07ff); + *tune_state = CT_TUNER_STEP_4; + } - dib0070_write_reg(st, 0x14, LO4 | fcaptrim); - dib0070_write_reg(st, 0x18, 0x07ff); + return ret; } -#define LPF 100 // define for the loop filter 100kHz by default 16-07-06 -#define LO4_SET_VCO_HFDIV(l, v, h) l |= ((v) << 11) | ((h) << 7) -#define LO4_SET_SD(l, s) l |= ((s) << 14) | ((s) << 12) -#define LO4_SET_CTRIM(l, c) l |= (c) << 10 -static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch) +static int dib0070_set_ctrl_lo5(struct dvb_frontend *fe, u8 vco_bias_trim, u8 hf_div_trim, u8 cp_current, u8 third_order_filt) { - struct dib0070_state *st = fe->tuner_priv; - u32 freq = ch->frequency/1000 + (BAND_OF_FREQUENCY(ch->frequency/1000) == BAND_VHF ? st->cfg->freq_offset_khz_vhf : st->cfg->freq_offset_khz_uhf); - - u8 band = BAND_OF_FREQUENCY(freq), c; + struct dib0070_state *state = fe->tuner_priv; + u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0); + dprintk("CTRL_LO5: 0x%x", lo5); + return dib0070_write_reg(state, 0x15, lo5); +} - /*******************VCO***********************************/ - u16 lo4 = 0; +void dib0070_ctrl_agc_filter(struct dvb_frontend *fe, u8 open) +{ + struct dib0070_state *state = fe->tuner_priv; - u8 REFDIV, PRESC = 2; - u32 FBDiv, Rest, FREF, VCOF_kHz; - u16 Num, Den; - /*******************FrontEnd******************************/ - u16 value = 0; + if (open) { + dib0070_write_reg(state, 0x1b, 0xff00); + dib0070_write_reg(state, 0x1a, 0x0000); + } else { + dib0070_write_reg(state, 0x1b, 0x4112); + if (state->cfg->vga_filter != 0) { + dib0070_write_reg(state, 0x1a, state->cfg->vga_filter); + dprintk("vga filter register is set to %x", state->cfg->vga_filter); + } else + dib0070_write_reg(state, 0x1a, 0x0009); + } +} - dprintk( "Tuning for Band: %hd (%d kHz)", band, freq); +EXPORT_SYMBOL(dib0070_ctrl_agc_filter); +struct dib0070_tuning { + u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */ + u8 switch_trim; + u8 vco_band; + u8 hfdiv; + u8 vco_multi; + u8 presc; + u8 wbdmux; + u16 tuner_enable; +}; +struct dib0070_lna_match { + u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */ + u8 lna_band; +}; - dib0070_write_reg(st, 0x17, 0x30); +static const struct dib0070_tuning dib0070s_tuning_table[] = { + {570000, 2, 1, 3, 6, 6, 2, 0x4000 | 0x0800}, /* UHF */ + {700000, 2, 0, 2, 4, 2, 2, 0x4000 | 0x0800}, + {863999, 2, 1, 2, 4, 2, 2, 0x4000 | 0x0800}, + {1500000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400}, /* LBAND */ + {1600000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400}, + {2000000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400}, + {0xffffffff, 0, 0, 8, 1, 2, 1, 0x8000 | 0x1000}, /* SBAND */ +}; - dib0070_set_bandwidth(fe, ch); /* c is used as HF */ - switch (st->revision) { - case DIB0070S_P1A: - switch (band) { - case BAND_LBAND: - LO4_SET_VCO_HFDIV(lo4, 1, 1); - c = 2; - break; - case BAND_SBAND: - LO4_SET_VCO_HFDIV(lo4, 0, 0); - LO4_SET_CTRIM(lo4, 1); - c = 1; - break; - case BAND_UHF: - default: - if (freq < 570000) { - LO4_SET_VCO_HFDIV(lo4, 1, 3); - PRESC = 6; c = 6; - } else if (freq < 680000) { - LO4_SET_VCO_HFDIV(lo4, 0, 2); - c = 4; - } else { - LO4_SET_VCO_HFDIV(lo4, 1, 2); - c = 4; - } - break; - } break; - - case DIB0070_P1G: - case DIB0070_P1F: - default: - switch (band) { - case BAND_FM: - LO4_SET_VCO_HFDIV(lo4, 0, 7); - c = 24; - break; - case BAND_LBAND: - LO4_SET_VCO_HFDIV(lo4, 1, 0); - c = 2; - break; - case BAND_VHF: - if (freq < 180000) { - LO4_SET_VCO_HFDIV(lo4, 0, 3); - c = 16; - } else if (freq < 190000) { - LO4_SET_VCO_HFDIV(lo4, 1, 3); - c = 16; - } else { - LO4_SET_VCO_HFDIV(lo4, 0, 6); - c = 12; - } - break; - - case BAND_UHF: - default: - if (freq < 570000) { - LO4_SET_VCO_HFDIV(lo4, 1, 5); - c = 6; - } else if (freq < 700000) { - LO4_SET_VCO_HFDIV(lo4, 0, 1); - c = 4; - } else { - LO4_SET_VCO_HFDIV(lo4, 1, 1); - c = 4; - } - break; - } - break; - } +static const struct dib0070_tuning dib0070_tuning_table[] = { + {115000, 1, 0, 7, 24, 2, 1, 0x8000 | 0x1000}, /* FM below 92MHz cannot be tuned */ + {179500, 1, 0, 3, 16, 2, 1, 0x8000 | 0x1000}, /* VHF */ + {189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000}, + {250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000}, + {569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800}, /* UHF */ + {699999, 2, 0, 1, 4, 2, 2, 0x4000 | 0x0800}, + {863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800}, + {0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400}, /* LBAND or everything higher than UHF */ +}; - dprintk( "HFDIV code: %hd", (lo4 >> 7) & 0xf); - dprintk( "VCO = %hd", (lo4 >> 11) & 0x3); +static const struct dib0070_lna_match dib0070_lna_flip_chip[] = { + {180000, 0}, /* VHF */ + {188000, 1}, + {196400, 2}, + {250000, 3}, + {550000, 0}, /* UHF */ + {590000, 1}, + {666000, 3}, + {864000, 5}, + {1500000, 0}, /* LBAND or everything higher than UHF */ + {1600000, 1}, + {2000000, 3}, + {0xffffffff, 7}, +}; +static const struct dib0070_lna_match dib0070_lna[] = { + {180000, 0}, /* VHF */ + {188000, 1}, + {196400, 2}, + {250000, 3}, + {550000, 2}, /* UHF */ + {650000, 3}, + {750000, 5}, + {850000, 6}, + {864000, 7}, + {1500000, 0}, /* LBAND or everything higher than UHF */ + {1600000, 1}, + {2000000, 3}, + {0xffffffff, 7}, +}; - VCOF_kHz = (c * freq) * 2; - dprintk( "VCOF in kHz: %d ((%hd*%d) << 1))",VCOF_kHz, c, freq); +#define LPF 100 // define for the loop filter 100kHz by default 16-07-06 +static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch) +{ + struct dib0070_state *state = fe->tuner_priv; - switch (band) { - case BAND_VHF: - REFDIV = (u8) ((st->cfg->clock_khz + 9999) / 10000); - break; - case BAND_FM: - REFDIV = (u8) ((st->cfg->clock_khz) / 1000); - break; - default: - REFDIV = (u8) ( st->cfg->clock_khz / 10000); - break; - } - FREF = st->cfg->clock_khz / REFDIV; + const struct dib0070_tuning *tune; + const struct dib0070_lna_match *lna_match; - dprintk( "REFDIV: %hd, FREF: %d", REFDIV, FREF); + enum frontend_tune_state *tune_state = &state->tune_state; + int ret = 10; /* 1ms is the default delay most of the time */ + u8 band = (u8) BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000); + u32 freq = fe->dtv_property_cache.frequency / 1000 + (band == BAND_VHF ? state->cfg->freq_offset_khz_vhf : state->cfg->freq_offset_khz_uhf); +#ifdef CONFIG_SYS_ISDBT + if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1) + if (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) + && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))) + || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0) + && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == (state->fe->dtv_property_cache.isdbt_sb_segment_count / 2))) + || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0) + && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))) + freq += 850; +#endif + if (state->current_rf != freq) { - switch (st->revision) { + switch (state->revision) { case DIB0070S_P1A: - FBDiv = (VCOF_kHz / PRESC / FREF); - Rest = (VCOF_kHz / PRESC) - FBDiv * FREF; + tune = dib0070s_tuning_table; + lna_match = dib0070_lna; break; - - case DIB0070_P1G: - case DIB0070_P1F: default: - FBDiv = (freq / (FREF / 2)); - Rest = 2 * freq - FBDiv * FREF; + tune = dib0070_tuning_table; + if (state->cfg->flip_chip) + lna_match = dib0070_lna_flip_chip; + else + lna_match = dib0070_lna; break; - } - - - if (Rest < LPF) Rest = 0; - else if (Rest < 2 * LPF) Rest = 2 * LPF; - else if (Rest > (FREF - LPF)) { Rest = 0 ; FBDiv += 1; } - else if (Rest > (FREF - 2 * LPF)) Rest = FREF - 2 * LPF; - Rest = (Rest * 6528) / (FREF / 10); - dprintk( "FBDIV: %d, Rest: %d", FBDiv, Rest); - - Num = 0; - Den = 1; + } + while (freq > tune->max_freq) /* find the right one */ + tune++; + while (freq > lna_match->max_freq) /* find the right one */ + lna_match++; - if (Rest > 0) { - LO4_SET_SD(lo4, 1); - Den = 255; - Num = (u16)Rest; + state->current_tune_table_index = tune; + state->lna_match = lna_match; } - dprintk( "Num: %hd, Den: %hd, SD: %hd",Num, Den, (lo4 >> 12) & 0x1); + if (*tune_state == CT_TUNER_START) { + dprintk("Tuning for Band: %hd (%d kHz)", band, freq); + if (state->current_rf != freq) { + u8 REFDIV; + u32 FBDiv, Rest, FREF, VCOF_kHz; + u8 Den; + state->current_rf = freq; + state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7); - dib0070_write_reg(st, 0x11, (u16)FBDiv); + dib0070_write_reg(state, 0x17, 0x30); + VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2; - dib0070_write_reg(st, 0x12, (Den << 8) | REFDIV); - + switch (band) { + case BAND_VHF: + REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000); + break; + case BAND_FM: + REFDIV = (u8) ((state->cfg->clock_khz) / 1000); + break; + default: + REFDIV = (u8) (state->cfg->clock_khz / 10000); + break; + } + FREF = state->cfg->clock_khz / REFDIV; + + switch (state->revision) { + case DIB0070S_P1A: + FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF); + Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF; + break; + + case DIB0070_P1G: + case DIB0070_P1F: + default: + FBDiv = (freq / (FREF / 2)); + Rest = 2 * freq - FBDiv * FREF; + break; + } - dib0070_write_reg(st, 0x13, Num); + if (Rest < LPF) + Rest = 0; + else if (Rest < 2 * LPF) + Rest = 2 * LPF; + else if (Rest > (FREF - LPF)) { + Rest = 0; + FBDiv += 1; + } else if (Rest > (FREF - 2 * LPF)) + Rest = FREF - 2 * LPF; + Rest = (Rest * 6528) / (FREF / 10); + + Den = 1; + if (Rest > 0) { + state->lo4 |= (1 << 14) | (1 << 12); + Den = 255; + } + dib0070_write_reg(state, 0x11, (u16) FBDiv); + dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV); + dib0070_write_reg(state, 0x13, (u16) Rest); - value = 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001; + if (state->revision == DIB0070S_P1A) { - switch (band) { - case BAND_UHF: value |= 0x4000 | 0x0800; break; - case BAND_LBAND: value |= 0x2000 | 0x0400; break; - default: value |= 0x8000 | 0x1000; break; - } - dib0070_write_reg(st, 0x20, value); + if (band == BAND_SBAND) { + dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0); + dib0070_write_reg(state, 0x1d, 0xFFFF); + } else + dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1); + } - dib0070_captrim(st, lo4); - if (st->revision == DIB0070S_P1A) { - if (band == BAND_SBAND) - dib0070_write_reg(st, 0x15, 0x16e2); - else - dib0070_write_reg(st, 0x15, 0x56e5); - } + dib0070_write_reg(state, 0x20, + 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable); + dprintk("REFDIV: %hd, FREF: %d", REFDIV, FREF); + dprintk("FBDIV: %d, Rest: %d", FBDiv, Rest); + dprintk("Num: %hd, Den: %hd, SD: %hd", (u16) Rest, Den, (state->lo4 >> 12) & 0x1); + dprintk("HFDIV code: %hd", state->current_tune_table_index->hfdiv); + dprintk("VCO = %hd", state->current_tune_table_index->vco_band); + dprintk("VCOF: ((%hd*%d) << 1))", state->current_tune_table_index->vco_multi, freq); + *tune_state = CT_TUNER_STEP_0; + } else { /* we are already tuned to this frequency - the configuration is correct */ + ret = 50; /* wakeup time */ + *tune_state = CT_TUNER_STEP_5; + } + } else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) { + + ret = dib0070_captrim(state, tune_state); + + } else if (*tune_state == CT_TUNER_STEP_4) { + const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain; + if (tmp != NULL) { + while (freq / 1000 > tmp->freq) /* find the right one */ + tmp++; + dib0070_write_reg(state, 0x0f, + (0 << 15) | (1 << 14) | (3 << 12) | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7) | (state-> + current_tune_table_index-> + wbdmux << 0)); + state->wbd_gain_current = tmp->wbd_gain_val; + } else { + dib0070_write_reg(state, 0x0f, + (0 << 15) | (1 << 14) | (3 << 12) | (6 << 9) | (0 << 8) | (1 << 7) | (state->current_tune_table_index-> + wbdmux << 0)); + state->wbd_gain_current = 6; + } - switch (band) { - case BAND_UHF: value = 0x7c82; break; - case BAND_LBAND: value = 0x7c84; break; - default: value = 0x7c81; break; - } - dib0070_write_reg(st, 0x0f, value); - dib0070_write_reg(st, 0x06, 0x3fff); - - /* Front End */ - /* c == TUNE, value = SWITCH */ - c = 0; - value = 0; - switch (band) { - case BAND_FM: - c = 0; value = 1; - break; - - case BAND_VHF: - if (freq <= 180000) c = 0; - else if (freq <= 188200) c = 1; - else if (freq <= 196400) c = 2; - else c = 3; - value = 1; - break; - - case BAND_LBAND: - if (freq <= 1500000) c = 0; - else if (freq <= 1600000) c = 1; - else c = 3; - break; - - case BAND_SBAND: - c = 7; - dib0070_write_reg(st, 0x1d,0xFFFF); - break; - - case BAND_UHF: - default: - if (st->cfg->flip_chip) { - if (freq <= 550000) c = 0; - else if (freq <= 590000) c = 1; - else if (freq <= 666000) c = 3; - else c = 5; - } else { - if (freq <= 550000) c = 2; - else if (freq <= 650000) c = 3; - else if (freq <= 750000) c = 5; - else if (freq <= 850000) c = 6; - else c = 7; - } - value = 2; - break; + dib0070_write_reg(state, 0x06, 0x3fff); + dib0070_write_reg(state, 0x07, + (state->current_tune_table_index->switch_trim << 11) | (7 << 8) | (state->lna_match->lna_band << 3) | (3 << 0)); + dib0070_write_reg(state, 0x08, (state->lna_match->lna_band << 10) | (3 << 7) | (127)); + dib0070_write_reg(state, 0x0d, 0x0d80); + + dib0070_write_reg(state, 0x18, 0x07ff); + dib0070_write_reg(state, 0x17, 0x0033); + + *tune_state = CT_TUNER_STEP_5; + } else if (*tune_state == CT_TUNER_STEP_5) { + dib0070_set_bandwidth(fe, ch); + *tune_state = CT_TUNER_STOP; + } else { + ret = FE_CALLBACK_TIME_NEVER; /* tuner finished, time to call again infinite */ } + return ret; +} - /* default: LNA_MATCH=7, BIAS=3 */ - dib0070_write_reg(st, 0x07, (value << 11) | (7 << 8) | (c << 3) | (3 << 0)); - dib0070_write_reg(st, 0x08, (c << 10) | (3 << 7) | (127)); - dib0070_write_reg(st, 0x0d, 0x0d80); +static int dib0070_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +{ + struct dib0070_state *state = fe->tuner_priv; + uint32_t ret; + state->tune_state = CT_TUNER_START; - dib0070_write_reg(st, 0x18, 0x07ff); - dib0070_write_reg(st, 0x17, 0x0033); + do { + ret = dib0070_tune_digital(fe, p); + if (ret != FE_CALLBACK_TIME_NEVER) + msleep(ret / 10); + else + break; + } while (state->tune_state != CT_TUNER_STOP); return 0; } static int dib0070_wakeup(struct dvb_frontend *fe) { - struct dib0070_state *st = fe->tuner_priv; - if (st->cfg->sleep) - st->cfg->sleep(fe, 0); + struct dib0070_state *state = fe->tuner_priv; + if (state->cfg->sleep) + state->cfg->sleep(fe, 0); return 0; } static int dib0070_sleep(struct dvb_frontend *fe) { - struct dib0070_state *st = fe->tuner_priv; - if (st->cfg->sleep) - st->cfg->sleep(fe, 1); + struct dib0070_state *state = fe->tuner_priv; + if (state->cfg->sleep) + state->cfg->sleep(fe, 1); return 0; } -static u16 dib0070_p1f_defaults[] = - -{ +static const u16 dib0070_p1f_defaults[] = { 7, 0x02, - 0x0008, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0002, - 0x0100, + 0x0008, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0002, + 0x0100, 3, 0x0d, - 0x0d80, - 0x0001, - 0x0000, + 0x0d80, + 0x0001, + 0x0000, 4, 0x11, - 0x0000, - 0x0103, - 0x0000, - 0x0000, + 0x0000, + 0x0103, + 0x0000, + 0x0000, 3, 0x16, - 0x0004 | 0x0040, - 0x0030, - 0x07ff, + 0x0004 | 0x0040, + 0x0030, + 0x07ff, 6, 0x1b, - 0x4112, - 0xff00, - 0xc07f, - 0x0000, - 0x0180, - 0x4000 | 0x0800 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001, + 0x4112, + 0xff00, + 0xc07f, + 0x0000, + 0x0180, + 0x4000 | 0x0800 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001, 0, }; -static void dib0070_wbd_calibration(struct dvb_frontend *fe) +static u16 dib0070_read_wbd_offset(struct dib0070_state *state, u8 gain) { - u16 wbd_offs; - struct dib0070_state *state = fe->tuner_priv; - - if (state->cfg->sleep) - state->cfg->sleep(fe, 0); + u16 tuner_en = dib0070_read_reg(state, 0x20); + u16 offset; - dib0070_write_reg(state, 0x0f, 0x6d81); - dib0070_write_reg(state, 0x20, 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001); + dib0070_write_reg(state, 0x18, 0x07ff); + dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001); + dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0)); msleep(9); - wbd_offs = dib0070_read_reg(state, 0x19); - dib0070_write_reg(state, 0x20, 0); - state->wbd_ff_offset = ((wbd_offs * 8 * 18 / 33 + 1) / 2); - dprintk( "WBDStart = %d (Vargen) - FF = %hd", (u32) wbd_offs * 1800/1024, state->wbd_ff_offset); - - if (state->cfg->sleep) - state->cfg->sleep(fe, 1); - + offset = dib0070_read_reg(state, 0x19); + dib0070_write_reg(state, 0x20, tuner_en); + return offset; } -u16 dib0070_wbd_offset(struct dvb_frontend *fe) +static void dib0070_wbd_offset_calibration(struct dib0070_state *state) { - struct dib0070_state *st = fe->tuner_priv; - return st->wbd_ff_offset; + u8 gain; + for (gain = 6; gain < 8; gain++) { + state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2); + dprintk("Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain - 6]); + } } -EXPORT_SYMBOL(dib0070_wbd_offset); -static int dib0070_set_ctrl_lo5(struct dvb_frontend *fe, u8 vco_bias_trim, u8 hf_div_trim, u8 cp_current, u8 third_order_filt) +u16 dib0070_wbd_offset(struct dvb_frontend *fe) { struct dib0070_state *state = fe->tuner_priv; - u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0); - dprintk( "CTRL_LO5: 0x%x", lo5); - return dib0070_write_reg(state, 0x15, lo5); + const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain; + u32 freq = fe->dtv_property_cache.frequency / 1000; + + if (tmp != NULL) { + while (freq / 1000 > tmp->freq) /* find the right one */ + tmp++; + state->wbd_gain_current = tmp->wbd_gain_val; + } else + state->wbd_gain_current = 6; + + return state->wbd_offset_3_3[state->wbd_gain_current - 6]; } +EXPORT_SYMBOL(dib0070_wbd_offset); + #define pgm_read_word(w) (*w) -static int dib0070_reset(struct dib0070_state *state) +static int dib0070_reset(struct dvb_frontend *fe) { + struct dib0070_state *state = fe->tuner_priv; u16 l, r, *n; HARD_RESET(state); - #ifndef FORCE_SBAND_TUNER if ((dib0070_read_reg(state, 0x22) >> 9) & 0x1) state->revision = (dib0070_read_reg(state, 0x1f) >> 8) & 0xff; else +#else +#warning forcing SBAND #endif - state->revision = DIB0070S_P1A; + state->revision = DIB0070S_P1A; /* P1F or not */ - dprintk( "Revision: %x", state->revision); + dprintk("Revision: %x", state->revision); if (state->revision == DIB0070_P1D) { - dprintk( "Error: this driver is not to be used meant for P1D or earlier"); + dprintk("Error: this driver is not to be used meant for P1D or earlier"); return -EINVAL; } @@ -498,7 +620,7 @@ static int dib0070_reset(struct dib0070_state *state) while (l) { r = pgm_read_word(n++); do { - dib0070_write_reg(state, (u8)r, pgm_read_word(n++)); + dib0070_write_reg(state, (u8) r, pgm_read_word(n++)); r++; } while (--l); l = pgm_read_word(n++); @@ -514,24 +636,25 @@ static int dib0070_reset(struct dib0070_state *state) r |= state->cfg->osc_buffer_state << 3; dib0070_write_reg(state, 0x10, r); - dib0070_write_reg(state, 0x1f, (1 << 8) | ((state->cfg->clock_pad_drive & 0xf) << 4)); + dib0070_write_reg(state, 0x1f, (1 << 8) | ((state->cfg->clock_pad_drive & 0xf) << 5)); if (state->cfg->invert_iq) { r = dib0070_read_reg(state, 0x02) & 0xffdf; dib0070_write_reg(state, 0x02, r | (1 << 5)); } - if (state->revision == DIB0070S_P1A) - dib0070_set_ctrl_lo5(state->fe, 4, 7, 3, 1); + dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0); else - dib0070_set_ctrl_lo5(state->fe, 4, 4, 2, 0); + dib0070_set_ctrl_lo5(fe, 5, 4, state->cfg->charge_pump, state->cfg->enable_third_order_filter); dib0070_write_reg(state, 0x01, (54 << 9) | 0xc8); + + dib0070_wbd_offset_calibration(state); + return 0; } - static int dib0070_release(struct dvb_frontend *fe) { kfree(fe->tuner_priv); @@ -539,23 +662,24 @@ static int dib0070_release(struct dvb_frontend *fe) return 0; } -static struct dvb_tuner_ops dib0070_ops = { +static const struct dvb_tuner_ops dib0070_ops = { .info = { - .name = "DiBcom DiB0070", - .frequency_min = 45000000, - .frequency_max = 860000000, - .frequency_step = 1000, - }, - .release = dib0070_release, - - .init = dib0070_wakeup, - .sleep = dib0070_sleep, - .set_params = dib0070_tune_digital, -// .get_frequency = dib0070_get_frequency, -// .get_bandwidth = dib0070_get_bandwidth + .name = "DiBcom DiB0070", + .frequency_min = 45000000, + .frequency_max = 860000000, + .frequency_step = 1000, + }, + .release = dib0070_release, + + .init = dib0070_wakeup, + .sleep = dib0070_sleep, + .set_params = dib0070_tune, + +// .get_frequency = dib0070_get_frequency, +// .get_bandwidth = dib0070_get_bandwidth }; -struct dvb_frontend * dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg) +struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg) { struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL); if (state == NULL) @@ -563,25 +687,24 @@ struct dvb_frontend * dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter state->cfg = cfg; state->i2c = i2c; - state->fe = fe; + state->fe = fe; fe->tuner_priv = state; - if (dib0070_reset(state) != 0) + if (dib0070_reset(fe) != 0) goto free_mem; - dib0070_wbd_calibration(fe); - printk(KERN_INFO "DiB0070: successfully identified\n"); memcpy(&fe->ops.tuner_ops, &dib0070_ops, sizeof(struct dvb_tuner_ops)); fe->tuner_priv = state; return fe; -free_mem: + free_mem: kfree(state); fe->tuner_priv = NULL; return NULL; } + EXPORT_SYMBOL(dib0070_attach); MODULE_AUTHOR("Patrick Boettcher "); diff --git a/drivers/media/dvb/frontends/dib0070.h b/drivers/media/dvb/frontends/dib0070.h index 9670f5d20cfb..8a2e1e710adb 100644 --- a/drivers/media/dvb/frontends/dib0070.h +++ b/drivers/media/dvb/frontends/dib0070.h @@ -15,6 +15,11 @@ struct i2c_adapter; #define DEFAULT_DIB0070_I2C_ADDRESS 0x60 +struct dib0070_wbd_gain_cfg { + u16 freq; + u16 wbd_gain_val; +}; + struct dib0070_config { u8 i2c_address; @@ -26,26 +31,28 @@ struct dib0070_config { int freq_offset_khz_uhf; int freq_offset_khz_vhf; - u8 osc_buffer_state; /* 0= normal, 1= tri-state */ - u32 clock_khz; - u8 clock_pad_drive; /* (Drive + 1) * 2mA */ + u8 osc_buffer_state; /* 0= normal, 1= tri-state */ + u32 clock_khz; + u8 clock_pad_drive; /* (Drive + 1) * 2mA */ - u8 invert_iq; /* invert Q - in case I or Q is inverted on the board */ + u8 invert_iq; /* invert Q - in case I or Q is inverted on the board */ - u8 force_crystal_mode; /* if == 0 -> decision is made in the driver default: <24 -> 2, >=24 -> 1 */ + u8 force_crystal_mode; /* if == 0 -> decision is made in the driver default: <24 -> 2, >=24 -> 1 */ u8 flip_chip; + u8 enable_third_order_filter; + u8 charge_pump; + + const struct dib0070_wbd_gain_cfg *wbd_gain; + + u8 vga_filter; }; #if defined(CONFIG_DVB_TUNER_DIB0070) || (defined(CONFIG_DVB_TUNER_DIB0070_MODULE) && defined(MODULE)) -extern struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, - struct dib0070_config *cfg); +extern struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg); extern u16 dib0070_wbd_offset(struct dvb_frontend *); #else -static inline struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, - struct dib0070_config *cfg) +static inline struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg) { printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); return NULL; @@ -57,5 +64,6 @@ static inline u16 dib0070_wbd_offset(struct dvb_frontend *fe) return -ENODEV; } #endif +extern void dib0070_ctrl_agc_filter(struct dvb_frontend *, u8 open); #endif diff --git a/drivers/media/dvb/frontends/dib7000p.c b/drivers/media/dvb/frontends/dib7000p.c index fc96fbf03d6d..55ef6eeb0769 100644 --- a/drivers/media/dvb/frontends/dib7000p.c +++ b/drivers/media/dvb/frontends/dib7000p.c @@ -10,6 +10,7 @@ #include #include +#include "dvb_math.h" #include "dvb_frontend.h" #include "dib7000p.h" @@ -1217,7 +1218,37 @@ static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 *strength) static int dib7000p_read_snr(struct dvb_frontend* fe, u16 *snr) { - *snr = 0x0000; + struct dib7000p_state *state = fe->demodulator_priv; + u16 val; + s32 signal_mant, signal_exp, noise_mant, noise_exp; + u32 result = 0; + + val = dib7000p_read_word(state, 479); + noise_mant = (val >> 4) & 0xff; + noise_exp = ((val & 0xf) << 2); + val = dib7000p_read_word(state, 480); + noise_exp += ((val >> 14) & 0x3); + if ((noise_exp & 0x20) != 0) + noise_exp -= 0x40; + + signal_mant = (val >> 6) & 0xFF; + signal_exp = (val & 0x3F); + if ((signal_exp & 0x20) != 0) + signal_exp -= 0x40; + + if (signal_mant != 0) + result = intlog10(2) * 10 * signal_exp + 10 * + intlog10(signal_mant); + else + result = intlog10(2) * 10 * signal_exp - 100; + + if (noise_mant != 0) + result -= intlog10(2) * 10 * noise_exp + 10 * + intlog10(noise_mant); + else + result -= intlog10(2) * 10 * noise_exp - 100; + + *snr = result / ((1 << 24) / 10); return 0; } diff --git a/drivers/media/dvb/frontends/dib8000.c b/drivers/media/dvb/frontends/dib8000.c new file mode 100644 index 000000000000..852c790d09d9 --- /dev/null +++ b/drivers/media/dvb/frontends/dib8000.c @@ -0,0 +1,2277 @@ +/* + * Linux-DVB Driver for DiBcom's DiB8000 chip (ISDB-T). + * + * Copyright (C) 2009 DiBcom (http://www.dibcom.fr/) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation, version 2. + */ +#include +#include +#include "dvb_math.h" + +#include "dvb_frontend.h" + +#include "dib8000.h" + +#define LAYER_ALL -1 +#define LAYER_A 1 +#define LAYER_B 2 +#define LAYER_C 3 + +#define FE_CALLBACK_TIME_NEVER 0xffffffff + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "turn on debugging (default: 0)"); + +#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB8000: "); printk(args); printk("\n"); } } while (0) + +enum frontend_tune_state { + CT_AGC_START = 20, + CT_AGC_STEP_0, + CT_AGC_STEP_1, + CT_AGC_STEP_2, + CT_AGC_STEP_3, + CT_AGC_STEP_4, + CT_AGC_STOP, + + CT_DEMOD_START = 30, +}; + +#define FE_STATUS_TUNE_FAILED 0 + +struct i2c_device { + struct i2c_adapter *adap; + u8 addr; +}; + +struct dib8000_state { + struct dvb_frontend fe; + struct dib8000_config cfg; + + struct i2c_device i2c; + + struct dibx000_i2c_master i2c_master; + + u16 wbd_ref; + + u8 current_band; + u32 current_bandwidth; + struct dibx000_agc_config *current_agc; + u32 timf; + u32 timf_default; + + u8 div_force_off:1; + u8 div_state:1; + u16 div_sync_wait; + + u8 agc_state; + u8 differential_constellation; + u8 diversity_onoff; + + s16 ber_monitored_layer; + u16 gpio_dir; + u16 gpio_val; + + u16 revision; + u8 isdbt_cfg_loaded; + enum frontend_tune_state tune_state; + u32 status; +}; + +enum dib8000_power_mode { + DIB8000M_POWER_ALL = 0, + DIB8000M_POWER_INTERFACE_ONLY, +}; + +static u16 dib8000_i2c_read16(struct i2c_device *i2c, u16 reg) +{ + u8 wb[2] = { reg >> 8, reg & 0xff }; + u8 rb[2]; + struct i2c_msg msg[2] = { + {.addr = i2c->addr >> 1,.flags = 0,.buf = wb,.len = 2}, + {.addr = i2c->addr >> 1,.flags = I2C_M_RD,.buf = rb,.len = 2}, + }; + + if (i2c_transfer(i2c->adap, msg, 2) != 2) + dprintk("i2c read error on %d", reg); + + return (rb[0] << 8) | rb[1]; +} + +static u16 dib8000_read_word(struct dib8000_state *state, u16 reg) +{ + return dib8000_i2c_read16(&state->i2c, reg); +} + +static u32 dib8000_read32(struct dib8000_state *state, u16 reg) +{ + u16 rw[2]; + + rw[0] = dib8000_read_word(state, reg + 0); + rw[1] = dib8000_read_word(state, reg + 1); + + return ((rw[0] << 16) | (rw[1])); +} + +static int dib8000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val) +{ + u8 b[4] = { + (reg >> 8) & 0xff, reg & 0xff, + (val >> 8) & 0xff, val & 0xff, + }; + struct i2c_msg msg = { + .addr = i2c->addr >> 1,.flags = 0,.buf = b,.len = 4 + }; + return i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0; +} + +static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val) +{ + return dib8000_i2c_write16(&state->i2c, reg, val); +} + +const int16_t coeff_2k_sb_1seg_dqpsk[8] = { + (769 << 5) | 0x0a, (745 << 5) | 0x03, (595 << 5) | 0x0d, (769 << 5) | 0x0a, (920 << 5) | 0x09, (784 << 5) | 0x02, (519 << 5) | 0x0c, + (920 << 5) | 0x09 +}; + +const int16_t coeff_2k_sb_1seg[8] = { + (692 << 5) | 0x0b, (683 << 5) | 0x01, (519 << 5) | 0x09, (692 << 5) | 0x0b, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f +}; + +const int16_t coeff_2k_sb_3seg_0dqpsk_1dqpsk[8] = { + (832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (912 << 5) | 0x04, (807 << 5) | 0x11, + (-931 << 5) | 0x0f +}; + +const int16_t coeff_2k_sb_3seg_0dqpsk[8] = { + (622 << 5) | 0x0c, (941 << 5) | 0x04, (796 << 5) | 0x10, (622 << 5) | 0x0c, (982 << 5) | 0x0c, (519 << 5) | 0x02, (572 << 5) | 0x0e, + (982 << 5) | 0x0c +}; + +const int16_t coeff_2k_sb_3seg_1dqpsk[8] = { + (699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (640 << 5) | 0x03, (866 << 5) | 0x12, + (-720 << 5) | 0x0d +}; + +const int16_t coeff_2k_sb_3seg[8] = { + (664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (697 << 5) | 0x01, (836 << 5) | 0x0e, + (-610 << 5) | 0x0a +}; + +const int16_t coeff_4k_sb_1seg_dqpsk[8] = { + (-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, (750 << 5) | 0x03, (665 << 5) | 0x0f, + (-922 << 5) | 0x0d +}; + +const int16_t coeff_4k_sb_1seg[8] = { + (638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (517 << 5) | 0x00, (698 << 5) | 0x0d, + (-655 << 5) | 0x0a +}; + +const int16_t coeff_4k_sb_3seg_0dqpsk_1dqpsk[8] = { + (-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, (993 << 5) | 0x05, (523 << 5) | 0x14, + (-958 << 5) | 0x13 +}; + +const int16_t coeff_4k_sb_3seg_0dqpsk[8] = { + (-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, (547 << 5) | 0x03, (696 << 5) | 0x12, + (-568 << 5) | 0x0f +}; + +const int16_t coeff_4k_sb_3seg_1dqpsk[8] = { + (-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, (683 << 5) | 0x04, (543 << 5) | 0x14, + (-848 << 5) | 0x13 +}; + +const int16_t coeff_4k_sb_3seg[8] = { + (612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (683 << 5) | 0x02, (869 << 5) | 0x12, + (-869 << 5) | 0x13 +}; + +const int16_t coeff_8k_sb_1seg_dqpsk[8] = { + (-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, (781 << 5) | 0x04, (739 << 5) | 0x13, + (-598 << 5) | 0x10 +}; + +const int16_t coeff_8k_sb_1seg[8] = { + (673 << 5) | 0x0f, (683 << 5) | 0x03, (808 << 5) | 0x12, (673 << 5) | 0x0f, (585 << 5) | 0x0f, (512 << 5) | 0x01, (780 << 5) | 0x0f, + (585 << 5) | 0x0f +}; + +const int16_t coeff_8k_sb_3seg_0dqpsk_1dqpsk[8] = { + (863 << 5) | 0x17, (930 << 5) | 0x07, (878 << 5) | 0x19, (863 << 5) | 0x17, (0 << 5) | 0x14, (521 << 5) | 0x05, (980 << 5) | 0x18, + (0 << 5) | 0x14 +}; + +const int16_t coeff_8k_sb_3seg_0dqpsk[8] = { + (-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, (565 << 5) | 0x04, (553 << 5) | 0x15, + (-877 << 5) | 0x15 +}; + +const int16_t coeff_8k_sb_3seg_1dqpsk[8] = { + (-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, (713 << 5) | 0x05, (1018 << 5) | 0x18, + (-921 << 5) | 0x14 +}; + +const int16_t coeff_8k_sb_3seg[8] = { + (514 << 5) | 0x14, (910 << 5) | 0x05, (861 << 5) | 0x17, (514 << 5) | 0x14, (690 << 5) | 0x14, (683 << 5) | 0x03, (662 << 5) | 0x15, + (690 << 5) | 0x14 +}; + +const int16_t ana_fe_coeff_3seg[24] = { + 81, 80, 78, 74, 68, 61, 54, 45, 37, 28, 19, 11, 4, 1022, 1017, 1013, 1010, 1008, 1008, 1008, 1008, 1010, 1014, 1017 +}; + +const int16_t ana_fe_coeff_1seg[24] = { + 249, 226, 164, 82, 5, 981, 970, 988, 1018, 20, 31, 26, 8, 1012, 1000, 1018, 1012, 8, 15, 14, 9, 3, 1017, 1003 +}; + +const int16_t ana_fe_coeff_13seg[24] = { + 396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1 +}; + +static u16 fft_to_mode(struct dib8000_state *state) +{ + u16 mode; + switch (state->fe.dtv_property_cache.transmission_mode) { + case TRANSMISSION_MODE_2K: + mode = 1; + break; + case TRANSMISSION_MODE_4K: + mode = 2; + break; + default: + case TRANSMISSION_MODE_AUTO: + case TRANSMISSION_MODE_8K: + mode = 3; + break; + } + return mode; +} + +static void dib8000_set_acquisition_mode(struct dib8000_state *state) +{ + u16 nud = dib8000_read_word(state, 298); + nud |= (1 << 3) | (1 << 0); + dprintk("acquisition mode activated"); + dib8000_write_word(state, 298, nud); +} + +static int dib8000_set_output_mode(struct dib8000_state *state, int mode) +{ + u16 outreg, fifo_threshold, smo_mode, sram = 0x0205; /* by default SDRAM deintlv is enabled */ + + outreg = 0; + fifo_threshold = 1792; + smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1); + + dprintk("-I- Setting output mode for demod %p to %d", &state->fe, mode); + + switch (mode) { + case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock + outreg = (1 << 10); /* 0x0400 */ + break; + case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock + outreg = (1 << 10) | (1 << 6); /* 0x0440 */ + break; + case OUTMODE_MPEG2_SERIAL: // STBs with serial input + outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */ + break; + case OUTMODE_DIVERSITY: + if (state->cfg.hostbus_diversity) { + outreg = (1 << 10) | (4 << 6); /* 0x0500 */ + sram &= 0xfdff; + } else + sram |= 0x0c00; + break; + case OUTMODE_MPEG2_FIFO: // e.g. USB feeding + smo_mode |= (3 << 1); + fifo_threshold = 512; + outreg = (1 << 10) | (5 << 6); + break; + case OUTMODE_HIGH_Z: // disable + outreg = 0; + break; + + case OUTMODE_ANALOG_ADC: + outreg = (1 << 10) | (3 << 6); + dib8000_set_acquisition_mode(state); + break; + + default: + dprintk("Unhandled output_mode passed to be set for demod %p", &state->fe); + return -EINVAL; + } + + if (state->cfg.output_mpeg2_in_188_bytes) + smo_mode |= (1 << 5); + + dib8000_write_word(state, 299, smo_mode); + dib8000_write_word(state, 300, fifo_threshold); /* synchronous fread */ + dib8000_write_word(state, 1286, outreg); + dib8000_write_word(state, 1291, sram); + + return 0; +} + +static int dib8000_set_diversity_in(struct dvb_frontend *fe, int onoff) +{ + struct dib8000_state *state = fe->demodulator_priv; + u16 sync_wait = dib8000_read_word(state, 273) & 0xfff0; + + if (!state->differential_constellation) { + dib8000_write_word(state, 272, 1 << 9); //dvsy_off_lmod4 = 1 + dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2); // sync_enable = 1; comb_mode = 2 + } else { + dib8000_write_word(state, 272, 0); //dvsy_off_lmod4 = 0 + dib8000_write_word(state, 273, sync_wait); // sync_enable = 0; comb_mode = 0 + } + state->diversity_onoff = onoff; + + switch (onoff) { + case 0: /* only use the internal way - not the diversity input */ + dib8000_write_word(state, 270, 1); + dib8000_write_word(state, 271, 0); + break; + case 1: /* both ways */ + dib8000_write_word(state, 270, 6); + dib8000_write_word(state, 271, 6); + break; + case 2: /* only the diversity input */ + dib8000_write_word(state, 270, 0); + dib8000_write_word(state, 271, 1); + break; + } + return 0; +} + +static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_power_mode mode) +{ + /* by default everything is going to be powered off */ + u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff, + reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3, reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00; + + /* now, depending on the requested mode, we power on */ + switch (mode) { + /* power up everything in the demod */ + case DIB8000M_POWER_ALL: + reg_774 = 0x0000; + reg_775 = 0x0000; + reg_776 = 0x0000; + reg_900 &= 0xfffc; + reg_1280 &= 0x00ff; + break; + case DIB8000M_POWER_INTERFACE_ONLY: + reg_1280 &= 0x00ff; + break; + } + + dprintk("powermode : 774 : %x ; 775 : %x; 776 : %x ; 900 : %x; 1280 : %x", reg_774, reg_775, reg_776, reg_900, reg_1280); + dib8000_write_word(state, 774, reg_774); + dib8000_write_word(state, 775, reg_775); + dib8000_write_word(state, 776, reg_776); + dib8000_write_word(state, 900, reg_900); + dib8000_write_word(state, 1280, reg_1280); +} + +static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no) +{ + int ret = 0; + u16 reg_907 = dib8000_read_word(state, 907), reg_908 = dib8000_read_word(state, 908); + + switch (no) { + case DIBX000_SLOW_ADC_ON: + reg_908 |= (1 << 1) | (1 << 0); + ret |= dib8000_write_word(state, 908, reg_908); + reg_908 &= ~(1 << 1); + break; + + case DIBX000_SLOW_ADC_OFF: + reg_908 |= (1 << 1) | (1 << 0); + break; + + case DIBX000_ADC_ON: + reg_907 &= 0x0fff; + reg_908 &= 0x0003; + break; + + case DIBX000_ADC_OFF: // leave the VBG voltage on + reg_907 |= (1 << 14) | (1 << 13) | (1 << 12); + reg_908 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2); + break; + + case DIBX000_VBG_ENABLE: + reg_907 &= ~(1 << 15); + break; + + case DIBX000_VBG_DISABLE: + reg_907 |= (1 << 15); + break; + + default: + break; + } + + ret |= dib8000_write_word(state, 907, reg_907); + ret |= dib8000_write_word(state, 908, reg_908); + + return ret; +} + +static int dib8000_set_bandwidth(struct dib8000_state *state, u32 bw) +{ + u32 timf; + + if (bw == 0) + bw = 6000; + + if (state->timf == 0) { + dprintk("using default timf"); + timf = state->timf_default; + } else { + dprintk("using updated timf"); + timf = state->timf; + } + + dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff)); + dib8000_write_word(state, 30, (u16) ((timf) & 0xffff)); + + return 0; +} + +static int dib8000_sad_calib(struct dib8000_state *state) +{ +/* internal */ + dib8000_write_word(state, 923, (0 << 1) | (0 << 0)); + dib8000_write_word(state, 924, 776); // 0.625*3.3 / 4096 + + /* do the calibration */ + dib8000_write_word(state, 923, (1 << 0)); + dib8000_write_word(state, 923, (0 << 0)); + + msleep(1); + return 0; +} + +int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value) +{ + struct dib8000_state *state = fe->demodulator_priv; + if (value > 4095) + value = 4095; + state->wbd_ref = value; + return dib8000_write_word(state, 106, value); +} + +EXPORT_SYMBOL(dib8000_set_wbd_ref); +static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_config *bw) +{ + dprintk("ifreq: %d %x, inversion: %d", bw->ifreq, bw->ifreq, bw->ifreq >> 25); + dib8000_write_word(state, 23, (u16) (((bw->internal * 1000) >> 16) & 0xffff)); /* P_sec_len */ + dib8000_write_word(state, 24, (u16) ((bw->internal * 1000) & 0xffff)); + dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff)); + dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff)); + dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003)); + + dib8000_write_word(state, 922, bw->sad_cfg); +} + +static void dib8000_reset_pll(struct dib8000_state *state) +{ + const struct dibx000_bandwidth_config *pll = state->cfg.pll; + u16 clk_cfg1; + + // clk_cfg0 + dib8000_write_word(state, 901, (pll->pll_prediv << 8) | (pll->pll_ratio << 0)); + + // clk_cfg1 + clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) | + (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | (1 << 3) | (pll->pll_range << 1) | (pll->pll_reset << 0); + + dib8000_write_word(state, 902, clk_cfg1); + clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3); + dib8000_write_word(state, 902, clk_cfg1); + + dprintk("clk_cfg1: 0x%04x", clk_cfg1); /* 0x507 1 0 1 000 0 0 11 1 */ + + /* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */ + if (state->cfg.pll->ADClkSrc == 0) + dib8000_write_word(state, 904, (0 << 15) | (0 << 12) | (0 << 10) | (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1)); + else if (state->cfg.refclksel != 0) + dib8000_write_word(state, 904, + (0 << 15) | (1 << 12) | ((state->cfg.refclksel & 0x3) << 10) | (pll->modulo << 8) | (pll-> + ADClkSrc << 7) | (0 << 1)); + else + dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | (3 << 10) | (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1)); + + dib8000_reset_pll_common(state, pll); +} + +static int dib8000_reset_gpio(struct dib8000_state *st) +{ + /* reset the GPIOs */ + dib8000_write_word(st, 1029, st->cfg.gpio_dir); + dib8000_write_word(st, 1030, st->cfg.gpio_val); + + /* TODO 782 is P_gpio_od */ + + dib8000_write_word(st, 1032, st->cfg.gpio_pwm_pos); + + dib8000_write_word(st, 1037, st->cfg.pwm_freq_div); + return 0; +} + +static int dib8000_cfg_gpio(struct dib8000_state *st, u8 num, u8 dir, u8 val) +{ + st->cfg.gpio_dir = dib8000_read_word(st, 1029); + st->cfg.gpio_dir &= ~(1 << num); /* reset the direction bit */ + st->cfg.gpio_dir |= (dir & 0x1) << num; /* set the new direction */ + dib8000_write_word(st, 1029, st->cfg.gpio_dir); + + st->cfg.gpio_val = dib8000_read_word(st, 1030); + st->cfg.gpio_val &= ~(1 << num); /* reset the direction bit */ + st->cfg.gpio_val |= (val & 0x01) << num; /* set the new value */ + dib8000_write_word(st, 1030, st->cfg.gpio_val); + + dprintk("gpio dir: %x: gpio val: %x", st->cfg.gpio_dir, st->cfg.gpio_val); + + return 0; +} + +int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val) +{ + struct dib8000_state *state = fe->demodulator_priv; + return dib8000_cfg_gpio(state, num, dir, val); +} + +EXPORT_SYMBOL(dib8000_set_gpio); +static const u16 dib8000_defaults[] = { + /* auto search configuration - lock0 by default waiting + * for cpil_lock; lock1 cpil_lock; lock2 tmcc_sync_lock */ + 3, 7, + 0x0004, + 0x0400, + 0x0814, + + 12, 11, + 0x001b, + 0x7740, + 0x005b, + 0x8d80, + 0x01c9, + 0xc380, + 0x0000, + 0x0080, + 0x0000, + 0x0090, + 0x0001, + 0xd4c0, + + /*1, 32, + 0x6680 // P_corm_thres Lock algorithms configuration */ + + 11, 80, /* set ADC level to -16 */ + (1 << 13) - 825 - 117, + (1 << 13) - 837 - 117, + (1 << 13) - 811 - 117, + (1 << 13) - 766 - 117, + (1 << 13) - 737 - 117, + (1 << 13) - 693 - 117, + (1 << 13) - 648 - 117, + (1 << 13) - 619 - 117, + (1 << 13) - 575 - 117, + (1 << 13) - 531 - 117, + (1 << 13) - 501 - 117, + + 4, 108, + 0, + 0, + 0, + 0, + + 1, 175, + 0x0410, + 1, 179, + 8192, // P_fft_nb_to_cut + + 6, 181, + 0x2800, // P_coff_corthres_ ( 2k 4k 8k ) 0x2800 + 0x2800, + 0x2800, + 0x2800, // P_coff_cpilthres_ ( 2k 4k 8k ) 0x2800 + 0x2800, + 0x2800, + + 2, 193, + 0x0666, // P_pha3_thres + 0x0000, // P_cti_use_cpe, P_cti_use_prog + + 2, 205, + 0x200f, // P_cspu_regul, P_cspu_win_cut + 0x000f, // P_des_shift_work + + 5, 215, + 0x023d, // P_adp_regul_cnt + 0x00a4, // P_adp_noise_cnt + 0x00a4, // P_adp_regul_ext + 0x7ff0, // P_adp_noise_ext + 0x3ccc, // P_adp_fil + + 1, 230, + 0x0000, // P_2d_byp_ti_num + + 1, 263, + 0x800, //P_equal_thres_wgn + + 1, 268, + (2 << 9) | 39, // P_equal_ctrl_synchro, P_equal_speedmode + + 1, 270, + 0x0001, // P_div_lock0_wait + 1, 285, + 0x0020, //p_fec_ + 1, 299, + 0x0062, // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard + + 1, 338, + (1 << 12) | // P_ctrl_corm_thres4pre_freq_inh=1 + (1 << 10) | // P_ctrl_pre_freq_mode_sat=1 + (0 << 9) | // P_ctrl_pre_freq_inh=0 + (3 << 5) | // P_ctrl_pre_freq_step=3 + (1 << 0), // P_pre_freq_win_len=1 + + 1, 903, + (0 << 4) | 2, // P_divclksel=0 P_divbitsel=2 (was clk=3,bit=1 for MPW) + + 0, +}; + +static u16 dib8000_identify(struct i2c_device *client) +{ + u16 value; + + //because of glitches sometimes + value = dib8000_i2c_read16(client, 896); + + if ((value = dib8000_i2c_read16(client, 896)) != 0x01b3) { + dprintk("wrong Vendor ID (read=0x%x)", value); + return 0; + } + + value = dib8000_i2c_read16(client, 897); + if (value != 0x8000 && value != 0x8001 && value != 0x8002) { + dprintk("wrong Device ID (%x)", value); + return 0; + } + + switch (value) { + case 0x8000: + dprintk("found DiB8000A"); + break; + case 0x8001: + dprintk("found DiB8000B"); + break; + case 0x8002: + dprintk("found DiB8000C"); + break; + } + return value; +} + +static int dib8000_reset(struct dvb_frontend *fe) +{ + struct dib8000_state *state = fe->demodulator_priv; + + dib8000_write_word(state, 1287, 0x0003); /* sram lead in, rdy */ + + if ((state->revision = dib8000_identify(&state->i2c)) == 0) + return -EINVAL; + + if (state->revision == 0x8000) + dprintk("error : dib8000 MA not supported"); + + dibx000_reset_i2c_master(&state->i2c_master); + + dib8000_set_power_mode(state, DIB8000M_POWER_ALL); + + /* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */ + dib8000_set_adc_state(state, DIBX000_VBG_ENABLE); + + /* restart all parts */ + dib8000_write_word(state, 770, 0xffff); + dib8000_write_word(state, 771, 0xffff); + dib8000_write_word(state, 772, 0xfffc); + dib8000_write_word(state, 898, 0x000c); // sad + dib8000_write_word(state, 1280, 0x004d); + dib8000_write_word(state, 1281, 0x000c); + + dib8000_write_word(state, 770, 0x0000); + dib8000_write_word(state, 771, 0x0000); + dib8000_write_word(state, 772, 0x0000); + dib8000_write_word(state, 898, 0x0004); // sad + dib8000_write_word(state, 1280, 0x0000); + dib8000_write_word(state, 1281, 0x0000); + + /* drives */ + if (state->cfg.drives) + dib8000_write_word(state, 906, state->cfg.drives); + else { + dprintk("using standard PAD-drive-settings, please adjust settings in config-struct to be optimal."); + dib8000_write_word(state, 906, 0x2d98); // min drive SDRAM - not optimal - adjust + } + + dib8000_reset_pll(state); + + if (dib8000_reset_gpio(state) != 0) + dprintk("GPIO reset was not successful."); + + if (dib8000_set_output_mode(state, OUTMODE_HIGH_Z) != 0) + dprintk("OUTPUT_MODE could not be resetted."); + + state->current_agc = NULL; + + // P_iqc_alpha_pha, P_iqc_alpha_amp, P_iqc_dcc_alpha, ... + /* P_iqc_ca2 = 0; P_iqc_impnc_on = 0; P_iqc_mode = 0; */ + if (state->cfg.pll->ifreq == 0) + dib8000_write_word(state, 40, 0x0755); /* P_iqc_corr_inh = 0 enable IQcorr block */ + else + dib8000_write_word(state, 40, 0x1f55); /* P_iqc_corr_inh = 1 disable IQcorr block */ + + { + u16 l = 0, r; + const u16 *n; + n = dib8000_defaults; + l = *n++; + while (l) { + r = *n++; + do { + dib8000_write_word(state, r, *n++); + r++; + } while (--l); + l = *n++; + } + } + state->isdbt_cfg_loaded = 0; + + //div_cfg override for special configs + if (state->cfg.div_cfg != 0) + dib8000_write_word(state, 903, state->cfg.div_cfg); + + /* unforce divstr regardless whether i2c enumeration was done or not */ + dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1)); + + dib8000_set_bandwidth(state, 6000); + + dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON); + dib8000_sad_calib(state); + dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF); + + dib8000_set_power_mode(state, DIB8000M_POWER_INTERFACE_ONLY); + + return 0; +} + +static void dib8000_restart_agc(struct dib8000_state *state) +{ + // P_restart_iqc & P_restart_agc + dib8000_write_word(state, 770, 0x0a00); + dib8000_write_word(state, 770, 0x0000); +} + +static int dib8000_update_lna(struct dib8000_state *state) +{ + u16 dyn_gain; + + if (state->cfg.update_lna) { + // read dyn_gain here (because it is demod-dependent and not tuner) + dyn_gain = dib8000_read_word(state, 390); + + if (state->cfg.update_lna(&state->fe, dyn_gain)) { // LNA has changed + dib8000_restart_agc(state); + return 1; + } + } + return 0; +} + +static int dib8000_set_agc_config(struct dib8000_state *state, u8 band) +{ + struct dibx000_agc_config *agc = NULL; + int i; + if (state->current_band == band && state->current_agc != NULL) + return 0; + state->current_band = band; + + for (i = 0; i < state->cfg.agc_config_count; i++) + if (state->cfg.agc[i].band_caps & band) { + agc = &state->cfg.agc[i]; + break; + } + + if (agc == NULL) { + dprintk("no valid AGC configuration found for band 0x%02x", band); + return -EINVAL; + } + + state->current_agc = agc; + + /* AGC */ + dib8000_write_word(state, 76, agc->setup); + dib8000_write_word(state, 77, agc->inv_gain); + dib8000_write_word(state, 78, agc->time_stabiliz); + dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock); + + // Demod AGC loop configuration + dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp); + dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp); + + dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d", + state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel); + + /* AGC continued */ + if (state->wbd_ref != 0) + dib8000_write_word(state, 106, state->wbd_ref); + else // use default + dib8000_write_word(state, 106, agc->wbd_ref); + dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8)); + dib8000_write_word(state, 108, agc->agc1_max); + dib8000_write_word(state, 109, agc->agc1_min); + dib8000_write_word(state, 110, agc->agc2_max); + dib8000_write_word(state, 111, agc->agc2_min); + dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2); + dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2); + dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2); + dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2); + + dib8000_write_word(state, 75, agc->agc1_pt3); + dib8000_write_word(state, 923, (dib8000_read_word(state, 923) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2)); /*LB : 929 -> 923 */ + + return 0; +} + +static int dib8000_agc_soft_split(struct dib8000_state *state) +{ + u16 agc, split_offset; + + if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0) + return FE_CALLBACK_TIME_NEVER; + + // n_agc_global + agc = dib8000_read_word(state, 390); + + if (agc > state->current_agc->split.min_thres) + split_offset = state->current_agc->split.min; + else if (agc < state->current_agc->split.max_thres) + split_offset = state->current_agc->split.max; + else + split_offset = state->current_agc->split.max * + (agc - state->current_agc->split.min_thres) / (state->current_agc->split.max_thres - state->current_agc->split.min_thres); + + dprintk("AGC split_offset: %d", split_offset); + + // P_agc_force_split and P_agc_split_offset + dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset); + return 5000; +} + +static int dib8000_agc_startup(struct dvb_frontend *fe) +{ + struct dib8000_state *state = fe->demodulator_priv; + enum frontend_tune_state *tune_state = &state->tune_state; + + int ret = 0; + + switch (*tune_state) { + case CT_AGC_START: + // set power-up level: interf+analog+AGC + + dib8000_set_adc_state(state, DIBX000_ADC_ON); + + if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))) != 0) { + *tune_state = CT_AGC_STOP; + state->status = FE_STATUS_TUNE_FAILED; + break; + } + + ret = 70; + *tune_state = CT_AGC_STEP_0; + break; + + case CT_AGC_STEP_0: + //AGC initialization + if (state->cfg.agc_control) + state->cfg.agc_control(&state->fe, 1); + + dib8000_restart_agc(state); + + // wait AGC rough lock time + ret = 50; + *tune_state = CT_AGC_STEP_1; + break; + + case CT_AGC_STEP_1: + // wait AGC accurate lock time + ret = 70; + + if (dib8000_update_lna(state)) + // wait only AGC rough lock time + ret = 50; + else + *tune_state = CT_AGC_STEP_2; + break; + + case CT_AGC_STEP_2: + dib8000_agc_soft_split(state); + + if (state->cfg.agc_control) + state->cfg.agc_control(&state->fe, 0); + + *tune_state = CT_AGC_STOP; + break; + default: + ret = dib8000_agc_soft_split(state); + break; + } + return ret; + +} + +static void dib8000_update_timf(struct dib8000_state *state) +{ + u32 timf = state->timf = dib8000_read32(state, 435); + + dib8000_write_word(state, 29, (u16) (timf >> 16)); + dib8000_write_word(state, 30, (u16) (timf & 0xffff)); + dprintk("Updated timing frequency: %d (default: %d)", state->timf, state->timf_default); +} + +static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosearching) +{ + u16 mode, max_constellation, seg_diff_mask = 0, nbseg_diff = 0; + u8 guard, crate, constellation, timeI; + u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 }; + u16 i, coeff[4], P_cfr_left_edge = 0, P_cfr_right_edge = 0, seg_mask13 = 0x1fff; // All 13 segments enabled + const s16 *ncoeff, *ana_fe; + u16 tmcc_pow = 0; + u16 coff_pow = 0x2800; + u16 init_prbs = 0xfff; + u16 ana_gain = 0; + u16 adc_target_16dB[11] = { + (1 << 13) - 825 - 117, + (1 << 13) - 837 - 117, + (1 << 13) - 811 - 117, + (1 << 13) - 766 - 117, + (1 << 13) - 737 - 117, + (1 << 13) - 693 - 117, + (1 << 13) - 648 - 117, + (1 << 13) - 619 - 117, + (1 << 13) - 575 - 117, + (1 << 13) - 531 - 117, + (1 << 13) - 501 - 117 + }; + + if (state->ber_monitored_layer != LAYER_ALL) + dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & 0x60) | state->ber_monitored_layer); + else + dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60); + + i = dib8000_read_word(state, 26) & 1; // P_dds_invspec + dib8000_write_word(state, 26, state->fe.dtv_property_cache.inversion ^ i); + + if (state->fe.dtv_property_cache.isdbt_sb_mode) { + //compute new dds_freq for the seg and adjust prbs + int seg_offset = + state->fe.dtv_property_cache.isdbt_sb_segment_idx - (state->fe.dtv_property_cache.isdbt_sb_segment_count / 2) - + (state->fe.dtv_property_cache.isdbt_sb_segment_count % 2); + int clk = state->cfg.pll->internal; + u32 segtodds = ((u32) (430 << 23) / clk) << 3; // segtodds = SegBW / Fclk * pow(2,26) + int dds_offset = seg_offset * segtodds; + int new_dds, sub_channel; + if ((state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) == 0) // if even + dds_offset -= (int)(segtodds / 2); + + if (state->cfg.pll->ifreq == 0) { + if ((state->fe.dtv_property_cache.inversion ^ i) == 0) { + dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1); + new_dds = dds_offset; + } else + new_dds = dds_offset; + + // We shift tuning frequency if the wanted segment is : + // - the segment of center frequency with an odd total number of segments + // - the segment to the left of center frequency with an even total number of segments + // - the segment to the right of center frequency with an even total number of segments + if ((state->fe.dtv_property_cache.delivery_system == SYS_ISDBT) && (state->fe.dtv_property_cache.isdbt_sb_mode == 1) + && + (((state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) + && (state->fe.dtv_property_cache.isdbt_sb_segment_idx == + ((state->fe.dtv_property_cache.isdbt_sb_segment_count / 2) + 1))) + || (((state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) == 0) + && (state->fe.dtv_property_cache.isdbt_sb_segment_idx == (state->fe.dtv_property_cache.isdbt_sb_segment_count / 2))) + || (((state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) == 0) + && (state->fe.dtv_property_cache.isdbt_sb_segment_idx == + ((state->fe.dtv_property_cache.isdbt_sb_segment_count / 2) + 1))) + )) { + new_dds -= ((u32) (850 << 22) / clk) << 4; // new_dds = 850 (freq shift in KHz) / Fclk * pow(2,26) + } + } else { + if ((state->fe.dtv_property_cache.inversion ^ i) == 0) + new_dds = state->cfg.pll->ifreq - dds_offset; + else + new_dds = state->cfg.pll->ifreq + dds_offset; + } + dib8000_write_word(state, 27, (u16) ((new_dds >> 16) & 0x01ff)); + dib8000_write_word(state, 28, (u16) (new_dds & 0xffff)); + if (state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) // if odd + sub_channel = ((state->fe.dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset) + 1) % 41) / 3; + else // if even + sub_channel = ((state->fe.dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset)) % 41) / 3; + sub_channel -= 6; + + if (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K + || state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_4K) { + dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); //adp_pass =1 + dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); //pha3_force_pha_shift = 1 + } else { + dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); //adp_pass =0 + dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); //pha3_force_pha_shift = 0 + } + + switch (state->fe.dtv_property_cache.transmission_mode) { + case TRANSMISSION_MODE_2K: + switch (sub_channel) { + case -6: + init_prbs = 0x0; + break; // 41, 0, 1 + case -5: + init_prbs = 0x423; + break; // 02~04 + case -4: + init_prbs = 0x9; + break; // 05~07 + case -3: + init_prbs = 0x5C7; + break; // 08~10 + case -2: + init_prbs = 0x7A6; + break; // 11~13 + case -1: + init_prbs = 0x3D8; + break; // 14~16 + case 0: + init_prbs = 0x527; + break; // 17~19 + case 1: + init_prbs = 0x7FF; + break; // 20~22 + case 2: + init_prbs = 0x79B; + break; // 23~25 + case 3: + init_prbs = 0x3D6; + break; // 26~28 + case 4: + init_prbs = 0x3A2; + break; // 29~31 + case 5: + init_prbs = 0x53B; + break; // 32~34 + case 6: + init_prbs = 0x2F4; + break; // 35~37 + default: + case 7: + init_prbs = 0x213; + break; // 38~40 + } + break; + + case TRANSMISSION_MODE_4K: + switch (sub_channel) { + case -6: + init_prbs = 0x0; + break; // 41, 0, 1 + case -5: + init_prbs = 0x208; + break; // 02~04 + case -4: + init_prbs = 0xC3; + break; // 05~07 + case -3: + init_prbs = 0x7B9; + break; // 08~10 + case -2: + init_prbs = 0x423; + break; // 11~13 + case -1: + init_prbs = 0x5C7; + break; // 14~16 + case 0: + init_prbs = 0x3D8; + break; // 17~19 + case 1: + init_prbs = 0x7FF; + break; // 20~22 + case 2: + init_prbs = 0x3D6; + break; // 23~25 + case 3: + init_prbs = 0x53B; + break; // 26~28 + case 4: + init_prbs = 0x213; + break; // 29~31 + case 5: + init_prbs = 0x29; + break; // 32~34 + case 6: + init_prbs = 0xD0; + break; // 35~37 + default: + case 7: + init_prbs = 0x48E; + break; // 38~40 + } + break; + + default: + case TRANSMISSION_MODE_8K: + switch (sub_channel) { + case -6: + init_prbs = 0x0; + break; // 41, 0, 1 + case -5: + init_prbs = 0x740; + break; // 02~04 + case -4: + init_prbs = 0x069; + break; // 05~07 + case -3: + init_prbs = 0x7DD; + break; // 08~10 + case -2: + init_prbs = 0x208; + break; // 11~13 + case -1: + init_prbs = 0x7B9; + break; // 14~16 + case 0: + init_prbs = 0x5C7; + break; // 17~19 + case 1: + init_prbs = 0x7FF; + break; // 20~22 + case 2: + init_prbs = 0x53B; + break; // 23~25 + case 3: + init_prbs = 0x29; + break; // 26~28 + case 4: + init_prbs = 0x48E; + break; // 29~31 + case 5: + init_prbs = 0x4C4; + break; // 32~34 + case 6: + init_prbs = 0x367; + break; // 33~37 + default: + case 7: + init_prbs = 0x684; + break; // 38~40 + } + break; + } + } else { // if not state->fe.dtv_property_cache.isdbt_sb_mode + dib8000_write_word(state, 27, (u16) ((state->cfg.pll->ifreq >> 16) & 0x01ff)); + dib8000_write_word(state, 28, (u16) (state->cfg.pll->ifreq & 0xffff)); + dib8000_write_word(state, 26, (u16) ((state->cfg.pll->ifreq >> 25) & 0x0003)); + } + /*P_mode == ?? */ + dib8000_write_word(state, 10, (seq << 4)); + // dib8000_write_word(state, 287, (dib8000_read_word(state, 287) & 0xe000) | 0x1000); + + switch (state->fe.dtv_property_cache.guard_interval) { + case GUARD_INTERVAL_1_32: + guard = 0; + break; + case GUARD_INTERVAL_1_16: + guard = 1; + break; + case GUARD_INTERVAL_1_8: + guard = 2; + break; + case GUARD_INTERVAL_1_4: + default: + guard = 3; + break; + } + + dib8000_write_word(state, 1, (init_prbs << 2) | (guard & 0x3)); // ADDR 1 + + max_constellation = DQPSK; + for (i = 0; i < 3; i++) { + switch (state->fe.dtv_property_cache.layer[i].modulation) { + case DQPSK: + constellation = 0; + break; + case QPSK: + constellation = 1; + break; + case QAM_16: + constellation = 2; + break; + case QAM_64: + default: + constellation = 3; + break; + } + + switch (state->fe.dtv_property_cache.layer[i].fec) { + case FEC_1_2: + crate = 1; + break; + case FEC_2_3: + crate = 2; + break; + case FEC_3_4: + crate = 3; + break; + case FEC_5_6: + crate = 5; + break; + case FEC_7_8: + default: + crate = 7; + break; + } + + if ((state->fe.dtv_property_cache.layer[i].interleaving > 0) && + ((state->fe.dtv_property_cache.layer[i].interleaving <= 3) || + (state->fe.dtv_property_cache.layer[i].interleaving == 4 && state->fe.dtv_property_cache.isdbt_sb_mode == 1)) + ) + timeI = state->fe.dtv_property_cache.layer[i].interleaving; + else + timeI = 0; + dib8000_write_word(state, 2 + i, (constellation << 10) | ((state->fe.dtv_property_cache.layer[i].segment_count & 0xf) << 6) | + (crate << 3) | timeI); + if (state->fe.dtv_property_cache.layer[i].segment_count > 0) { + switch (max_constellation) { + case DQPSK: + case QPSK: + if (state->fe.dtv_property_cache.layer[i].modulation == QAM_16 || + state->fe.dtv_property_cache.layer[i].modulation == QAM_64) + max_constellation = state->fe.dtv_property_cache.layer[i].modulation; + break; + case QAM_16: + if (state->fe.dtv_property_cache.layer[i].modulation == QAM_64) + max_constellation = state->fe.dtv_property_cache.layer[i].modulation; + break; + } + } + } + + mode = fft_to_mode(state); + + //dib8000_write_word(state, 5, 13); /*p_last_seg = 13*/ + + dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | + ((state->fe.dtv_property_cache.isdbt_partial_reception & 1) << 5) | ((state->fe.dtv_property_cache. + isdbt_sb_mode & 1) << 4)); + + dprintk("mode = %d ; guard = %d", mode, state->fe.dtv_property_cache.guard_interval); + + /* signal optimization parameter */ + + if (state->fe.dtv_property_cache.isdbt_partial_reception) { + seg_diff_mask = (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) << permu_seg[0]; + for (i = 1; i < 3; i++) + nbseg_diff += + (state->fe.dtv_property_cache.layer[i].modulation == DQPSK) * state->fe.dtv_property_cache.layer[i].segment_count; + for (i = 0; i < nbseg_diff; i++) + seg_diff_mask |= 1 << permu_seg[i + 1]; + } else { + for (i = 0; i < 3; i++) + nbseg_diff += + (state->fe.dtv_property_cache.layer[i].modulation == DQPSK) * state->fe.dtv_property_cache.layer[i].segment_count; + for (i = 0; i < nbseg_diff; i++) + seg_diff_mask |= 1 << permu_seg[i]; + } + dprintk("nbseg_diff = %X (%d)", seg_diff_mask, seg_diff_mask); + + state->differential_constellation = (seg_diff_mask != 0); + dib8000_set_diversity_in(&state->fe, state->diversity_onoff); + + if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { // ISDB-Tsb + if (state->fe.dtv_property_cache.isdbt_partial_reception == 1) // 3-segments + seg_mask13 = 0x00E0; + else // 1-segment + seg_mask13 = 0x0040; + } else + seg_mask13 = 0x1fff; + + // WRITE: Mode & Diff mask + dib8000_write_word(state, 0, (mode << 13) | seg_diff_mask); + + if ((seg_diff_mask) || (state->fe.dtv_property_cache.isdbt_sb_mode)) + dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); + else + dib8000_write_word(state, 268, (2 << 9) | 39); //init value + + // ---- SMALL ---- + // P_small_seg_diff + dib8000_write_word(state, 352, seg_diff_mask); // ADDR 352 + + dib8000_write_word(state, 353, seg_mask13); // ADDR 353 + +/* // P_small_narrow_band=0, P_small_last_seg=13, P_small_offset_num_car=5 */ + // dib8000_write_word(state, 351, (state->fe.dtv_property_cache.isdbt_sb_mode << 8) | (13 << 4) | 5 ); + + // ---- SMALL ---- + if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { + switch (state->fe.dtv_property_cache.transmission_mode) { + case TRANSMISSION_MODE_2K: + if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // 1-seg + if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) // DQPSK + ncoeff = coeff_2k_sb_1seg_dqpsk; + else // QPSK or QAM + ncoeff = coeff_2k_sb_1seg; + } else { // 3-segments + if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) { // DQPSK on central segment + if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) // DQPSK on external segments + ncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk; + else // QPSK or QAM on external segments + ncoeff = coeff_2k_sb_3seg_0dqpsk; + } else { // QPSK or QAM on central segment + if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) // DQPSK on external segments + ncoeff = coeff_2k_sb_3seg_1dqpsk; + else // QPSK or QAM on external segments + ncoeff = coeff_2k_sb_3seg; + } + } + break; + + case TRANSMISSION_MODE_4K: + if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // 1-seg + if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) // DQPSK + ncoeff = coeff_4k_sb_1seg_dqpsk; + else // QPSK or QAM + ncoeff = coeff_4k_sb_1seg; + } else { // 3-segments + if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) { // DQPSK on central segment + if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments + ncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk; + } else { // QPSK or QAM on external segments + ncoeff = coeff_4k_sb_3seg_0dqpsk; + } + } else { // QPSK or QAM on central segment + if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments + ncoeff = coeff_4k_sb_3seg_1dqpsk; + } else // QPSK or QAM on external segments + ncoeff = coeff_4k_sb_3seg; + } + } + break; + + case TRANSMISSION_MODE_AUTO: + case TRANSMISSION_MODE_8K: + default: + if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // 1-seg + if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) // DQPSK + ncoeff = coeff_8k_sb_1seg_dqpsk; + else // QPSK or QAM + ncoeff = coeff_8k_sb_1seg; + } else { // 3-segments + if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) { // DQPSK on central segment + if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments + ncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk; + } else { // QPSK or QAM on external segments + ncoeff = coeff_8k_sb_3seg_0dqpsk; + } + } else { // QPSK or QAM on central segment + if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments + ncoeff = coeff_8k_sb_3seg_1dqpsk; + } else // QPSK or QAM on external segments + ncoeff = coeff_8k_sb_3seg; + } + } + break; + } + } + if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) + for (i = 0; i < 8; i++) + dib8000_write_word(state, 343 + i, ncoeff[i]); + + // P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_offset_num_car=5 + dib8000_write_word(state, 351, + (state->fe.dtv_property_cache.isdbt_sb_mode << 9) | (state->fe.dtv_property_cache.isdbt_sb_mode << 8) | (13 << 4) | 5); + + // ---- COFF ---- + // Carloff, the most robust + if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { // Sound Broadcasting mode - use both TMCC and AC pilots + + // P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64 + // P_coff_narrow_band=1, P_coff_square_val=1, P_coff_one_seg=~partial_rcpt, P_coff_use_tmcc=1, P_coff_use_ac=1 + dib8000_write_word(state, 187, + (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~state->fe.dtv_property_cache.isdbt_partial_reception & 1) << 2) + | 0x3); + +/* // P_small_coef_ext_enable = 1 */ +/* dib8000_write_word(state, 351, dib8000_read_word(state, 351) | 0x200); */ + + if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // Sound Broadcasting mode 1 seg + + // P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width= (P_mode == 3) , P_coff_one_seg_sym= (P_mode-1) + if (mode == 3) + dib8000_write_word(state, 180, 0x1fcf | ((mode - 1) << 14)); + else + dib8000_write_word(state, 180, 0x0fcf | ((mode - 1) << 14)); + // P_ctrl_corm_thres4pre_freq_inh=1,P_ctrl_pre_freq_mode_sat=1, + // P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 5, P_pre_freq_win_len=4 + dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4); + // P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8 + dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); + // P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1 + dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); + + // P_coff_corthres_8k, 4k, 2k and P_coff_cpilthres_8k, 4k, 2k + dib8000_write_word(state, 181, 300); + dib8000_write_word(state, 182, 150); + dib8000_write_word(state, 183, 80); + dib8000_write_word(state, 184, 300); + dib8000_write_word(state, 185, 150); + dib8000_write_word(state, 186, 80); + } else { // Sound Broadcasting mode 3 seg + // P_coff_one_seg_sym= 1, P_coff_one_seg_width= 1, P_coff_winlen=63, P_coff_thres_lock=15 + /* if (mode == 3) */ + /* dib8000_write_word(state, 180, 0x2fca | ((0) << 14)); */ + /* else */ + /* dib8000_write_word(state, 180, 0x2fca | ((1) << 14)); */ + dib8000_write_word(state, 180, 0x1fcf | (1 << 14)); + + // P_ctrl_corm_thres4pre_freq_inh = 1, P_ctrl_pre_freq_mode_sat=1, + // P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 4, P_pre_freq_win_len=4 + dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4); + // P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8 + dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); + //P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1 + dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); + + // P_coff_corthres_8k, 4k, 2k and P_coff_cpilthres_8k, 4k, 2k + dib8000_write_word(state, 181, 350); + dib8000_write_word(state, 182, 300); + dib8000_write_word(state, 183, 250); + dib8000_write_word(state, 184, 350); + dib8000_write_word(state, 185, 300); + dib8000_write_word(state, 186, 250); + } + + } else if (state->isdbt_cfg_loaded == 0) { // if not Sound Broadcasting mode : put default values for 13 segments + dib8000_write_word(state, 180, (16 << 6) | 9); + dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2); + coff_pow = 0x2800; + for (i = 0; i < 6; i++) + dib8000_write_word(state, 181 + i, coff_pow); + + // P_ctrl_corm_thres4pre_freq_inh=1, P_ctrl_pre_freq_mode_sat=1, + // P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 3, P_pre_freq_win_len=1 + dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1); + + // P_ctrl_pre_freq_win_len=8, P_ctrl_pre_freq_thres_lockin=6 + dib8000_write_word(state, 340, (8 << 6) | (6 << 0)); + // P_ctrl_pre_freq_thres_lockout=4, P_small_use_tmcc/ac/cp=1 + dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); + } + // ---- FFT ---- + if (state->fe.dtv_property_cache.isdbt_sb_mode == 1 && state->fe.dtv_property_cache.isdbt_partial_reception == 0) // 1-seg + dib8000_write_word(state, 178, 64); // P_fft_powrange=64 + else + dib8000_write_word(state, 178, 32); // P_fft_powrange=32 + + /* make the cpil_coff_lock more robust but slower p_coff_winlen + * 6bits; p_coff_thres_lock 6bits (for coff lock if needed) + */ + /* if ( ( nbseg_diff>0)&&(nbseg_diff<13)) + dib8000_write_word(state, 187, (dib8000_read_word(state, 187) & 0xfffb) | (1 << 3)); */ + + dib8000_write_word(state, 189, ~seg_mask13 | seg_diff_mask); /* P_lmod4_seg_inh */ + dib8000_write_word(state, 192, ~seg_mask13 | seg_diff_mask); /* P_pha3_seg_inh */ + dib8000_write_word(state, 225, ~seg_mask13 | seg_diff_mask); /* P_tac_seg_inh */ + if ((!state->fe.dtv_property_cache.isdbt_sb_mode) && (state->cfg.pll->ifreq == 0)) + dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */ + else + dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask); /* P_equal_noise_seg_inh */ + dib8000_write_word(state, 287, ~seg_mask13 | 0x1000); /* P_tmcc_seg_inh */ + //dib8000_write_word(state, 288, ~seg_mask13 | seg_diff_mask); /* P_tmcc_seg_eq_inh */ + if (!autosearching) + dib8000_write_word(state, 288, (~seg_mask13 | seg_diff_mask) & 0x1fff); /* P_tmcc_seg_eq_inh */ + else + dib8000_write_word(state, 288, 0x1fff); //disable equalisation of the tmcc when autosearch to be able to find the DQPSK channels. + dprintk("287 = %X (%d)", ~seg_mask13 | 0x1000, ~seg_mask13 | 0x1000); + + dib8000_write_word(state, 211, seg_mask13 & (~seg_diff_mask)); /* P_des_seg_enabled */ + + /* offset loop parameters */ + if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { + if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) // Sound Broadcasting mode 1 seg + /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x80 */ + dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x40); + + else // Sound Broadcasting mode 3 seg + /* P_timf_alpha = (10-P_mode), P_corm_alpha=6, P_corm_thres=0x80 */ + dib8000_write_word(state, 32, ((10 - mode) << 12) | (6 << 8) | 0x60); + } else + // TODO in 13 seg, timf_alpha can always be the same or not ? + /* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_corm_thres=0x80 */ + dib8000_write_word(state, 32, ((9 - mode) << 12) | (6 << 8) | 0x80); + + if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { + if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) // Sound Broadcasting mode 1 seg + /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (11-P_mode) */ + dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (10 - mode)); + + else // Sound Broadcasting mode 3 seg + /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (10-P_mode) */ + dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (9 - mode)); + } else + /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = 9 */ + dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (8 - mode)); + + /* P_dvsy_sync_wait - reuse mode */ + switch (state->fe.dtv_property_cache.transmission_mode) { + case TRANSMISSION_MODE_8K: + mode = 256; + break; + case TRANSMISSION_MODE_4K: + mode = 128; + break; + default: + case TRANSMISSION_MODE_2K: + mode = 64; + break; + } + if (state->cfg.diversity_delay == 0) + mode = (mode * (1 << (guard)) * 3) / 2 + 48; // add 50% SFN margin + compensate for one DVSY-fifo + else + mode = (mode * (1 << (guard)) * 3) / 2 + state->cfg.diversity_delay; // add 50% SFN margin + compensate for DVSY-fifo + mode <<= 4; + dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | mode); + + /* channel estimation fine configuration */ + switch (max_constellation) { + case QAM_64: + ana_gain = 0x7; // -1 : avoid def_est saturation when ADC target is -16dB + coeff[0] = 0x0148; /* P_adp_regul_cnt 0.04 */ + coeff[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */ + coeff[2] = 0x00a4; /* P_adp_regul_ext 0.02 */ + coeff[3] = 0xfff8; /* P_adp_noise_ext -0.001 */ + //if (!state->cfg.hostbus_diversity) //if diversity, we should prehaps use the configuration of the max_constallation -1 + break; + case QAM_16: + ana_gain = 0x7; // -1 : avoid def_est saturation when ADC target is -16dB + coeff[0] = 0x023d; /* P_adp_regul_cnt 0.07 */ + coeff[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */ + coeff[2] = 0x00a4; /* P_adp_regul_ext 0.02 */ + coeff[3] = 0xfff0; /* P_adp_noise_ext -0.002 */ + //if (!((state->cfg.hostbus_diversity) && (max_constellation == QAM_16))) + break; + default: + ana_gain = 0; // 0 : goes along with ADC target at -22dB to keep good mobile performance and lock at sensitivity level + coeff[0] = 0x099a; /* P_adp_regul_cnt 0.3 */ + coeff[1] = 0xffae; /* P_adp_noise_cnt -0.01 */ + coeff[2] = 0x0333; /* P_adp_regul_ext 0.1 */ + coeff[3] = 0xfff8; /* P_adp_noise_ext -0.002 */ + break; + } + for (mode = 0; mode < 4; mode++) + dib8000_write_word(state, 215 + mode, coeff[mode]); + + // update ana_gain depending on max constellation + dib8000_write_word(state, 116, ana_gain); + // update ADC target depending on ana_gain + if (ana_gain) { // set -16dB ADC target for ana_gain=-1 + for (i = 0; i < 10; i++) + dib8000_write_word(state, 80 + i, adc_target_16dB[i]); + } else { // set -22dB ADC target for ana_gain=0 + for (i = 0; i < 10; i++) + dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355); + } + + // ---- ANA_FE ---- + if (state->fe.dtv_property_cache.isdbt_sb_mode) { + if (state->fe.dtv_property_cache.isdbt_partial_reception == 1) // 3-segments + ana_fe = ana_fe_coeff_3seg; + else // 1-segment + ana_fe = ana_fe_coeff_1seg; + } else + ana_fe = ana_fe_coeff_13seg; + + if (state->fe.dtv_property_cache.isdbt_sb_mode == 1 || state->isdbt_cfg_loaded == 0) + for (mode = 0; mode < 24; mode++) + dib8000_write_word(state, 117 + mode, ana_fe[mode]); + + // ---- CHAN_BLK ---- + for (i = 0; i < 13; i++) { + if ((((~seg_diff_mask) >> i) & 1) == 1) { + P_cfr_left_edge += (1 << i) * ((i == 0) || ((((seg_mask13 & (~seg_diff_mask)) >> (i - 1)) & 1) == 0)); + P_cfr_right_edge += (1 << i) * ((i == 12) || ((((seg_mask13 & (~seg_diff_mask)) >> (i + 1)) & 1) == 0)); + } + } + dib8000_write_word(state, 222, P_cfr_left_edge); // P_cfr_left_edge + dib8000_write_word(state, 223, P_cfr_right_edge); // P_cfr_right_edge + // "P_cspu_left_edge" not used => do not care + // "P_cspu_right_edge" not used => do not care + + if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { // ISDB-Tsb + dib8000_write_word(state, 228, 1); // P_2d_mode_byp=1 + dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); // P_cspu_win_cut = 0 + if (state->fe.dtv_property_cache.isdbt_partial_reception == 0 // 1-segment + && state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K) { + //dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); // P_adp_pass = 0 + dib8000_write_word(state, 265, 15); // P_equal_noise_sel = 15 + } + } else if (state->isdbt_cfg_loaded == 0) { + dib8000_write_word(state, 228, 0); // default value + dib8000_write_word(state, 265, 31); // default value + dib8000_write_word(state, 205, 0x200f); // init value + } + // ---- TMCC ---- + for (i = 0; i < 3; i++) + tmcc_pow += + (((state->fe.dtv_property_cache.layer[i].modulation == DQPSK) * 4 + 1) * state->fe.dtv_property_cache.layer[i].segment_count); + // Quantif of "P_tmcc_dec_thres_?k" is (0, 5+mode, 9); + // Threshold is set at 1/4 of max power. + tmcc_pow *= (1 << (9 - 2)); + + dib8000_write_word(state, 290, tmcc_pow); // P_tmcc_dec_thres_2k + dib8000_write_word(state, 291, tmcc_pow); // P_tmcc_dec_thres_4k + dib8000_write_word(state, 292, tmcc_pow); // P_tmcc_dec_thres_8k + //dib8000_write_word(state, 287, (1 << 13) | 0x1000 ); + // ---- PHA3 ---- + + if (state->isdbt_cfg_loaded == 0) + dib8000_write_word(state, 250, 3285); /*p_2d_hspeed_thr0 */ + + if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) + state->isdbt_cfg_loaded = 0; + else + state->isdbt_cfg_loaded = 1; + +} + +static int dib8000_autosearch_start(struct dvb_frontend *fe) +{ + u8 factor; + u32 value; + struct dib8000_state *state = fe->demodulator_priv; + + int slist = 0; + + state->fe.dtv_property_cache.inversion = 0; + if (!state->fe.dtv_property_cache.isdbt_sb_mode) + state->fe.dtv_property_cache.layer[0].segment_count = 13; + state->fe.dtv_property_cache.layer[0].modulation = QAM_64; + state->fe.dtv_property_cache.layer[0].fec = FEC_2_3; + state->fe.dtv_property_cache.layer[0].interleaving = 0; + + //choose the right list, in sb, always do everything + if (state->fe.dtv_property_cache.isdbt_sb_mode) { + state->fe.dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K; + state->fe.dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8; + slist = 7; + dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); + } else { + if (state->fe.dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) { + if (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) { + slist = 7; + dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1 to have autosearch start ok with mode2 + } else + slist = 3; + } else { + if (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) { + slist = 2; + dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1 + } else + slist = 0; + } + + if (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) + state->fe.dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K; + if (state->fe.dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) + state->fe.dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8; + + dprintk("using list for autosearch : %d", slist); + dib8000_set_channel(state, (unsigned char)slist, 1); + //dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1 + + factor = 1; + + //set lock_mask values + dib8000_write_word(state, 6, 0x4); + dib8000_write_word(state, 7, 0x8); + dib8000_write_word(state, 8, 0x1000); + + //set lock_mask wait time values + value = 50 * state->cfg.pll->internal * factor; + dib8000_write_word(state, 11, (u16) ((value >> 16) & 0xffff)); // lock0 wait time + dib8000_write_word(state, 12, (u16) (value & 0xffff)); // lock0 wait time + value = 100 * state->cfg.pll->internal * factor; + dib8000_write_word(state, 13, (u16) ((value >> 16) & 0xffff)); // lock1 wait time + dib8000_write_word(state, 14, (u16) (value & 0xffff)); // lock1 wait time + value = 1000 * state->cfg.pll->internal * factor; + dib8000_write_word(state, 15, (u16) ((value >> 16) & 0xffff)); // lock2 wait time + dib8000_write_word(state, 16, (u16) (value & 0xffff)); // lock2 wait time + + value = dib8000_read_word(state, 0); + dib8000_write_word(state, 0, (u16) ((1 << 15) | value)); + dib8000_read_word(state, 1284); // reset the INT. n_irq_pending + dib8000_write_word(state, 0, (u16) value); + + } + + return 0; +} + +static int dib8000_autosearch_irq(struct dvb_frontend *fe) +{ + struct dib8000_state *state = fe->demodulator_priv; + u16 irq_pending = dib8000_read_word(state, 1284); + + if (irq_pending & 0x1) { // failed + dprintk("dib8000_autosearch_irq failed"); + return 1; + } + + if (irq_pending & 0x2) { // succeeded + dprintk("dib8000_autosearch_irq succeeded"); + return 2; + } + + return 0; // still pending +} + +static int dib8000_tune(struct dvb_frontend *fe) +{ + struct dib8000_state *state = fe->demodulator_priv; + int ret = 0; + u16 value, mode = fft_to_mode(state); + + // we are already tuned - just resuming from suspend + if (state == NULL) + return -EINVAL; + + dib8000_set_bandwidth(state, state->fe.dtv_property_cache.bandwidth_hz / 1000); + dib8000_set_channel(state, 0, 0); + + // restart demod + ret |= dib8000_write_word(state, 770, 0x4000); + ret |= dib8000_write_word(state, 770, 0x0000); + msleep(45); + + /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3 */ + /* ret |= dib8000_write_word(state, 29, (0 << 9) | (4 << 5) | (0 << 4) | (3 << 0) ); workaround inh_isi stays at 1 */ + + // never achieved a lock before - wait for timfreq to update + if (state->timf == 0) { + if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { + if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) // Sound Broadcasting mode 1 seg + msleep(300); + else // Sound Broadcasting mode 3 seg + msleep(500); + } else // 13 seg + msleep(200); + } + //dump_reg(state); + if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { + if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // Sound Broadcasting mode 1 seg + + /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40 alpha to check on board */ + dib8000_write_word(state, 32, ((13 - mode) << 12) | (6 << 8) | 0x40); + //dib8000_write_word(state, 32, (8 << 12) | (6 << 8) | 0x80); + + /* P_ctrl_sfreq_step= (12-P_mode) P_ctrl_sfreq_inh =0 P_ctrl_pha_off_max */ + ret |= dib8000_write_word(state, 37, (12 - mode) | ((5 + mode) << 5)); + + } else { // Sound Broadcasting mode 3 seg + + /* P_timf_alpha = (12-P_mode) , P_corm_alpha=6, P_corm_thres=0x60 alpha to check on board */ + dib8000_write_word(state, 32, ((12 - mode) << 12) | (6 << 8) | 0x60); + + ret |= dib8000_write_word(state, 37, (11 - mode) | ((5 + mode) << 5)); + } + + } else { // 13 seg + /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_thres=0x80 alpha to check on board */ + dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x80); + + ret |= dib8000_write_word(state, 37, (10 - mode) | ((5 + mode) << 5)); + + } + + // we achieved a coff_cpil_lock - it's time to update the timf + if ((dib8000_read_word(state, 568) >> 11) & 0x1) + dib8000_update_timf(state); + + //now that tune is finished, lock0 should lock on fec_mpeg to output this lock on MP_LOCK. It's changed in autosearch start + dib8000_write_word(state, 6, 0x200); + + if (state->revision == 0x8002) { + value = dib8000_read_word(state, 903); + dib8000_write_word(state, 903, value & ~(1 << 3)); + msleep(1); + dib8000_write_word(state, 903, value | (1 << 3)); + } + + return ret; +} + +static int dib8000_wakeup(struct dvb_frontend *fe) +{ + struct dib8000_state *state = fe->demodulator_priv; + + dib8000_set_power_mode(state, DIB8000M_POWER_ALL); + dib8000_set_adc_state(state, DIBX000_ADC_ON); + if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0) + dprintk("could not start Slow ADC"); + + return 0; +} + +static int dib8000_sleep(struct dvb_frontend *fe) +{ + struct dib8000_state *st = fe->demodulator_priv; + if (1) { + dib8000_set_output_mode(st, OUTMODE_HIGH_Z); + dib8000_set_power_mode(st, DIB8000M_POWER_INTERFACE_ONLY); + return dib8000_set_adc_state(st, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(st, DIBX000_ADC_OFF); + } else { + + return 0; + } +} + +static int dib8000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep) +{ + struct dib8000_state *state = fe->demodulator_priv; + u16 i, val = 0; + + fe->dtv_property_cache.bandwidth_hz = 6000000; + + fe->dtv_property_cache.isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1; + + val = dib8000_read_word(state, 570); + fe->dtv_property_cache.inversion = (val & 0x40) >> 6; + switch ((val & 0x30) >> 4) { + case 1: + fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K; + break; + case 3: + default: + fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K; + break; + } + + switch (val & 0x3) { + case 0: + fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32; + dprintk("dib8000_get_frontend GI = 1/32 "); + break; + case 1: + fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_16; + dprintk("dib8000_get_frontend GI = 1/16 "); + break; + case 2: + dprintk("dib8000_get_frontend GI = 1/8 "); + fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8; + break; + case 3: + dprintk("dib8000_get_frontend GI = 1/4 "); + fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_4; + break; + } + + val = dib8000_read_word(state, 505); + fe->dtv_property_cache.isdbt_partial_reception = val & 1; + dprintk("dib8000_get_frontend : partial_reception = %d ", fe->dtv_property_cache.isdbt_partial_reception); + + for (i = 0; i < 3; i++) { + val = dib8000_read_word(state, 493 + i); + fe->dtv_property_cache.layer[i].segment_count = val & 0x0F; + dprintk("dib8000_get_frontend : Layer %d segments = %d ", i, fe->dtv_property_cache.layer[i].segment_count); + + val = dib8000_read_word(state, 499 + i); + fe->dtv_property_cache.layer[i].interleaving = val & 0x3; + dprintk("dib8000_get_frontend : Layer %d time_intlv = %d ", i, fe->dtv_property_cache.layer[i].interleaving); + + val = dib8000_read_word(state, 481 + i); + switch (val & 0x7) { + case 1: + fe->dtv_property_cache.layer[i].fec = FEC_1_2; + dprintk("dib8000_get_frontend : Layer %d Code Rate = 1/2 ", i); + break; + case 2: + fe->dtv_property_cache.layer[i].fec = FEC_2_3; + dprintk("dib8000_get_frontend : Layer %d Code Rate = 2/3 ", i); + break; + case 3: + fe->dtv_property_cache.layer[i].fec = FEC_3_4; + dprintk("dib8000_get_frontend : Layer %d Code Rate = 3/4 ", i); + break; + case 5: + fe->dtv_property_cache.layer[i].fec = FEC_5_6; + dprintk("dib8000_get_frontend : Layer %d Code Rate = 5/6 ", i); + break; + default: + fe->dtv_property_cache.layer[i].fec = FEC_7_8; + dprintk("dib8000_get_frontend : Layer %d Code Rate = 7/8 ", i); + break; + } + + val = dib8000_read_word(state, 487 + i); + switch (val & 0x3) { + case 0: + dprintk("dib8000_get_frontend : Layer %d DQPSK ", i); + fe->dtv_property_cache.layer[i].modulation = DQPSK; + break; + case 1: + fe->dtv_property_cache.layer[i].modulation = QPSK; + dprintk("dib8000_get_frontend : Layer %d QPSK ", i); + break; + case 2: + fe->dtv_property_cache.layer[i].modulation = QAM_16; + dprintk("dib8000_get_frontend : Layer %d QAM16 ", i); + break; + case 3: + default: + dprintk("dib8000_get_frontend : Layer %d QAM64 ", i); + fe->dtv_property_cache.layer[i].modulation = QAM_64; + break; + } + } + return 0; +} + +static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep) +{ + struct dib8000_state *state = fe->demodulator_priv; + int time, ret; + + dib8000_set_output_mode(state, OUTMODE_HIGH_Z); + + if (fe->ops.tuner_ops.set_params) + fe->ops.tuner_ops.set_params(fe, fep); + + /* start up the AGC */ + state->tune_state = CT_AGC_START; + do { + time = dib8000_agc_startup(fe); + if (time != FE_CALLBACK_TIME_NEVER) + msleep(time / 10); + else + break; + } while (state->tune_state != CT_AGC_STOP); + + if (state->fe.dtv_property_cache.frequency == 0) { + dprintk("dib8000: must at least specify frequency "); + return 0; + } + + if (state->fe.dtv_property_cache.bandwidth_hz == 0) { + dprintk("dib8000: no bandwidth specified, set to default "); + state->fe.dtv_property_cache.bandwidth_hz = 6000000; + } + + state->tune_state = CT_DEMOD_START; + + if ((state->fe.dtv_property_cache.delivery_system != SYS_ISDBT) || + (state->fe.dtv_property_cache.inversion == INVERSION_AUTO) || + (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) || + (state->fe.dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) || + (((state->fe.dtv_property_cache.isdbt_layer_enabled & (1 << 0)) != 0) && + (state->fe.dtv_property_cache.layer[0].segment_count != 0xff) && + (state->fe.dtv_property_cache.layer[0].segment_count != 0) && + ((state->fe.dtv_property_cache.layer[0].modulation == QAM_AUTO) || + (state->fe.dtv_property_cache.layer[0].fec == FEC_AUTO))) || + (((state->fe.dtv_property_cache.isdbt_layer_enabled & (1 << 1)) != 0) && + (state->fe.dtv_property_cache.layer[1].segment_count != 0xff) && + (state->fe.dtv_property_cache.layer[1].segment_count != 0) && + ((state->fe.dtv_property_cache.layer[1].modulation == QAM_AUTO) || + (state->fe.dtv_property_cache.layer[1].fec == FEC_AUTO))) || + (((state->fe.dtv_property_cache.isdbt_layer_enabled & (1 << 2)) != 0) && + (state->fe.dtv_property_cache.layer[2].segment_count != 0xff) && + (state->fe.dtv_property_cache.layer[2].segment_count != 0) && + ((state->fe.dtv_property_cache.layer[2].modulation == QAM_AUTO) || + (state->fe.dtv_property_cache.layer[2].fec == FEC_AUTO))) || + (((state->fe.dtv_property_cache.layer[0].segment_count == 0) || + ((state->fe.dtv_property_cache.isdbt_layer_enabled & (1 << 0)) == 0)) && + ((state->fe.dtv_property_cache.layer[1].segment_count == 0) || + ((state->fe.dtv_property_cache.isdbt_layer_enabled & (2 << 0)) == 0)) && + ((state->fe.dtv_property_cache.layer[2].segment_count == 0) || ((state->fe.dtv_property_cache.isdbt_layer_enabled & (3 << 0)) == 0)))) { + int i = 800, found; + + dib8000_set_bandwidth(state, fe->dtv_property_cache.bandwidth_hz / 1000); + dib8000_autosearch_start(fe); + do { + msleep(10); + found = dib8000_autosearch_irq(fe); + } while (found == 0 && i--); + + dprintk("Frequency %d Hz, autosearch returns: %d", fep->frequency, found); + + if (found == 0 || found == 1) + return 0; // no channel found + + dib8000_get_frontend(fe, fep); + } + + ret = dib8000_tune(fe); + + /* make this a config parameter */ + dib8000_set_output_mode(state, state->cfg.output_mode); + + return ret; +} + +static int dib8000_read_status(struct dvb_frontend *fe, fe_status_t * stat) +{ + struct dib8000_state *state = fe->demodulator_priv; + u16 lock = dib8000_read_word(state, 568); + + *stat = 0; + + if ((lock >> 14) & 1) // AGC + *stat |= FE_HAS_SIGNAL; + + if ((lock >> 8) & 1) // Equal + *stat |= FE_HAS_CARRIER; + + if ((lock >> 3) & 1) // TMCC_SYNC + *stat |= FE_HAS_SYNC; + + if ((lock >> 5) & 7) // FEC MPEG + *stat |= FE_HAS_LOCK; + + lock = dib8000_read_word(state, 554); // Viterbi Layer A + if (lock & 0x01) + *stat |= FE_HAS_VITERBI; + + lock = dib8000_read_word(state, 555); // Viterbi Layer B + if (lock & 0x01) + *stat |= FE_HAS_VITERBI; + + lock = dib8000_read_word(state, 556); // Viterbi Layer C + if (lock & 0x01) + *stat |= FE_HAS_VITERBI; + + return 0; +} + +static int dib8000_read_ber(struct dvb_frontend *fe, u32 * ber) +{ + struct dib8000_state *state = fe->demodulator_priv; + *ber = (dib8000_read_word(state, 560) << 16) | dib8000_read_word(state, 561); // 13 segments + return 0; +} + +static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc) +{ + struct dib8000_state *state = fe->demodulator_priv; + *unc = dib8000_read_word(state, 565); // packet error on 13 seg + return 0; +} + +static int dib8000_read_signal_strength(struct dvb_frontend *fe, u16 * strength) +{ + struct dib8000_state *state = fe->demodulator_priv; + u16 val = dib8000_read_word(state, 390); + *strength = 65535 - val; + return 0; +} + +static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr) +{ + struct dib8000_state *state = fe->demodulator_priv; + u16 val; + s32 signal_mant, signal_exp, noise_mant, noise_exp; + u32 result = 0; + + val = dib8000_read_word(state, 542); + noise_mant = (val >> 6) & 0xff; + noise_exp = (val & 0x3f); + + val = dib8000_read_word(state, 543); + signal_mant = (val >> 6) & 0xff; + signal_exp = (val & 0x3f); + + if ((noise_exp & 0x20) != 0) + noise_exp -= 0x40; + if ((signal_exp & 0x20) != 0) + signal_exp -= 0x40; + + if (signal_mant != 0) + result = intlog10(2) * 10 * signal_exp + 10 * intlog10(signal_mant); + else + result = intlog10(2) * 10 * signal_exp - 100; + if (noise_mant != 0) + result -= intlog10(2) * 10 * noise_exp + 10 * intlog10(noise_mant); + else + result -= intlog10(2) * 10 * noise_exp - 100; + + *snr = result / (1 << 24); + return 0; +} + +int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr) +{ + int k = 0; + u8 new_addr = 0; + struct i2c_device client = {.adap = host }; + + for (k = no_of_demods - 1; k >= 0; k--) { + /* designated i2c address */ + new_addr = first_addr + (k << 1); + + client.addr = new_addr; + dib8000_i2c_write16(&client, 1287, 0x0003); /* sram lead in, rdy */ + if (dib8000_identify(&client) == 0) { + dib8000_i2c_write16(&client, 1287, 0x0003); /* sram lead in, rdy */ + client.addr = default_addr; + if (dib8000_identify(&client) == 0) { + dprintk("#%d: not identified", k); + return -EINVAL; + } + } + + /* start diversity to pull_down div_str - just for i2c-enumeration */ + dib8000_i2c_write16(&client, 1286, (1 << 10) | (4 << 6)); + + /* set new i2c address and force divstart */ + dib8000_i2c_write16(&client, 1285, (new_addr << 2) | 0x2); + client.addr = new_addr; + dib8000_identify(&client); + + dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr); + } + + for (k = 0; k < no_of_demods; k++) { + new_addr = first_addr | (k << 1); + client.addr = new_addr; + + // unforce divstr + dib8000_i2c_write16(&client, 1285, new_addr << 2); + + /* deactivate div - it was just for i2c-enumeration */ + dib8000_i2c_write16(&client, 1286, 0); + } + + return 0; +} + +EXPORT_SYMBOL(dib8000_i2c_enumeration); +static int dib8000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune) +{ + tune->min_delay_ms = 1000; + tune->step_size = 0; + tune->max_drift = 0; + return 0; +} + +static void dib8000_release(struct dvb_frontend *fe) +{ + struct dib8000_state *st = fe->demodulator_priv; + dibx000_exit_i2c_master(&st->i2c_master); + kfree(st); +} + +struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating) +{ + struct dib8000_state *st = fe->demodulator_priv; + return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating); +} + +EXPORT_SYMBOL(dib8000_get_i2c_master); + +static const struct dvb_frontend_ops dib8000_ops = { + .info = { + .name = "DiBcom 8000 ISDB-T", + .type = FE_OFDM, + .frequency_min = 44250000, + .frequency_max = 867250000, + .frequency_stepsize = 62500, + .caps = FE_CAN_INVERSION_AUTO | + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | + FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO, + }, + + .release = dib8000_release, + + .init = dib8000_wakeup, + .sleep = dib8000_sleep, + + .set_frontend = dib8000_set_frontend, + .get_tune_settings = dib8000_fe_get_tune_settings, + .get_frontend = dib8000_get_frontend, + + .read_status = dib8000_read_status, + .read_ber = dib8000_read_ber, + .read_signal_strength = dib8000_read_signal_strength, + .read_snr = dib8000_read_snr, + .read_ucblocks = dib8000_read_unc_blocks, +}; + +struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg) +{ + struct dvb_frontend *fe; + struct dib8000_state *state; + + dprintk("dib8000_attach"); + + state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL); + if (state == NULL) + return NULL; + + memcpy(&state->cfg, cfg, sizeof(struct dib8000_config)); + state->i2c.adap = i2c_adap; + state->i2c.addr = i2c_addr; + state->gpio_val = cfg->gpio_val; + state->gpio_dir = cfg->gpio_dir; + + /* Ensure the output mode remains at the previous default if it's + * not specifically set by the caller. + */ + if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK)) + state->cfg.output_mode = OUTMODE_MPEG2_FIFO; + + fe = &state->fe; + fe->demodulator_priv = state; + memcpy(&state->fe.ops, &dib8000_ops, sizeof(struct dvb_frontend_ops)); + + state->timf_default = cfg->pll->timf; + + if (dib8000_identify(&state->i2c) == 0) + goto error; + + dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr); + + dib8000_reset(fe); + + dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len = 3 */ + + return fe; + + error: + kfree(state); + return NULL; +} + +EXPORT_SYMBOL(dib8000_attach); + +MODULE_AUTHOR("Olivier Grenie "); +MODULE_DESCRIPTION("Driver for the DiBcom 8000 ISDB-T demodulator"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb/frontends/dib8000.h b/drivers/media/dvb/frontends/dib8000.h new file mode 100644 index 000000000000..a86de340dd54 --- /dev/null +++ b/drivers/media/dvb/frontends/dib8000.h @@ -0,0 +1,79 @@ +#ifndef DIB8000_H +#define DIB8000_H + +#include "dibx000_common.h" + +struct dib8000_config { + u8 output_mpeg2_in_188_bytes; + u8 hostbus_diversity; + u8 tuner_is_baseband; + int (*update_lna) (struct dvb_frontend *, u16 agc_global); + + u8 agc_config_count; + struct dibx000_agc_config *agc; + struct dibx000_bandwidth_config *pll; + +#define DIB8000_GPIO_DEFAULT_DIRECTIONS 0xffff + u16 gpio_dir; +#define DIB8000_GPIO_DEFAULT_VALUES 0x0000 + u16 gpio_val; +#define DIB8000_GPIO_PWM_POS0(v) ((v & 0xf) << 12) +#define DIB8000_GPIO_PWM_POS1(v) ((v & 0xf) << 8 ) +#define DIB8000_GPIO_PWM_POS2(v) ((v & 0xf) << 4 ) +#define DIB8000_GPIO_PWM_POS3(v) (v & 0xf) +#define DIB8000_GPIO_DEFAULT_PWM_POS 0xffff + u16 gpio_pwm_pos; + u16 pwm_freq_div; + + void (*agc_control) (struct dvb_frontend *, u8 before); + + u16 drives; + u16 diversity_delay; + u8 div_cfg; + u8 output_mode; + u8 refclksel; +}; + +#define DEFAULT_DIB8000_I2C_ADDRESS 18 + +#if defined(CONFIG_DVB_DIB8000) || (defined(CONFIG_DVB_DIB8000_MODULE) && defined(MODULE)) +extern struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg); +extern struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *, enum dibx000_i2c_interface, int); + +extern int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr); + +extern int dib8000_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val); +extern int dib8000_set_wbd_ref(struct dvb_frontend *, u16 value); +#else +static inline struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} + +static inline struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface i, int x) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} + +int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return -ENODEV; +} + +int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return -ENODEV; +} + +int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return -ENODEV; +} +#endif + +#endif diff --git a/drivers/media/dvb/frontends/dibx000_common.c b/drivers/media/dvb/frontends/dibx000_common.c index 315e09e95b0c..4efca30d2127 100644 --- a/drivers/media/dvb/frontends/dibx000_common.c +++ b/drivers/media/dvb/frontends/dibx000_common.c @@ -15,29 +15,31 @@ static int dibx000_write_word(struct dibx000_i2c_master *mst, u16 reg, u16 val) (val >> 8) & 0xff, val & 0xff, }; struct i2c_msg msg = { - .addr = mst->i2c_addr, .flags = 0, .buf = b, .len = 4 + .addr = mst->i2c_addr,.flags = 0,.buf = b,.len = 4 }; return i2c_transfer(mst->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; } -static int dibx000_i2c_select_interface(struct dibx000_i2c_master *mst, enum dibx000_i2c_interface intf) +static int dibx000_i2c_select_interface(struct dibx000_i2c_master *mst, + enum dibx000_i2c_interface intf) { if (mst->device_rev > DIB3000MC && mst->selected_interface != intf) { - dprintk("selecting interface: %d\n",intf); + dprintk("selecting interface: %d\n", intf); mst->selected_interface = intf; return dibx000_write_word(mst, mst->base_reg + 4, intf); } return 0; } -static int dibx000_i2c_gate_ctrl(struct dibx000_i2c_master *mst, u8 tx[4], u8 addr, int onoff) +static int dibx000_i2c_gate_ctrl(struct dibx000_i2c_master *mst, u8 tx[4], + u8 addr, int onoff) { u16 val; if (onoff) - val = addr << 8; // bit 7 = use master or not, if 0, the gate is open + val = addr << 8; // bit 7 = use master or not, if 0, the gate is open else val = 1 << 7; @@ -45,7 +47,7 @@ static int dibx000_i2c_gate_ctrl(struct dibx000_i2c_master *mst, u8 tx[4], u8 ad val <<= 1; tx[0] = (((mst->base_reg + 1) >> 8) & 0xff); - tx[1] = ( (mst->base_reg + 1) & 0xff); + tx[1] = ((mst->base_reg + 1) & 0xff); tx[2] = val >> 8; tx[3] = val & 0xff; @@ -57,59 +59,78 @@ static u32 dibx000_i2c_func(struct i2c_adapter *adapter) return I2C_FUNC_I2C; } -static int dibx000_i2c_gated_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num) +static int dibx000_i2c_gated_tuner_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg msg[], int num) { struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap); struct i2c_msg m[2 + num]; u8 tx_open[4], tx_close[4]; - memset(m,0, sizeof(struct i2c_msg) * (2 + num)); + memset(m, 0, sizeof(struct i2c_msg) * (2 + num)); dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_TUNER); - dibx000_i2c_gate_ctrl(mst, tx_open, msg[0].addr, 1); + dibx000_i2c_gate_ctrl(mst, tx_open, msg[0].addr, 1); m[0].addr = mst->i2c_addr; - m[0].buf = tx_open; - m[0].len = 4; + m[0].buf = tx_open; + m[0].len = 4; memcpy(&m[1], msg, sizeof(struct i2c_msg) * num); dibx000_i2c_gate_ctrl(mst, tx_close, 0, 0); - m[num+1].addr = mst->i2c_addr; - m[num+1].buf = tx_close; - m[num+1].len = 4; + m[num + 1].addr = mst->i2c_addr; + m[num + 1].buf = tx_close; + m[num + 1].len = 4; - return i2c_transfer(mst->i2c_adap, m, 2+num) == 2 + num ? num : -EIO; + return i2c_transfer(mst->i2c_adap, m, 2 + num) == 2 + num ? num : -EIO; } static struct i2c_algorithm dibx000_i2c_gated_tuner_algo = { - .master_xfer = dibx000_i2c_gated_tuner_xfer, + .master_xfer = dibx000_i2c_gated_tuner_xfer, .functionality = dibx000_i2c_func, }; -struct i2c_adapter * dibx000_get_i2c_adapter(struct dibx000_i2c_master *mst, enum dibx000_i2c_interface intf, int gating) +struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master *mst, + enum dibx000_i2c_interface intf, + int gating) { struct i2c_adapter *i2c = NULL; switch (intf) { - case DIBX000_I2C_INTERFACE_TUNER: - if (gating) - i2c = &mst->gated_tuner_i2c_adap; - break; - default: - printk(KERN_ERR "DiBX000: incorrect I2C interface selected\n"); - break; + case DIBX000_I2C_INTERFACE_TUNER: + if (gating) + i2c = &mst->gated_tuner_i2c_adap; + break; + default: + printk(KERN_ERR "DiBX000: incorrect I2C interface selected\n"); + break; } return i2c; } + EXPORT_SYMBOL(dibx000_get_i2c_adapter); -static int i2c_adapter_init(struct i2c_adapter *i2c_adap, struct i2c_algorithm *algo, const char *name, struct dibx000_i2c_master *mst) +void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst) +{ + /* initialize the i2c-master by closing the gate */ + u8 tx[4]; + struct i2c_msg m = {.addr = mst->i2c_addr,.buf = tx,.len = 4 }; + + dibx000_i2c_gate_ctrl(mst, tx, 0, 0); + i2c_transfer(mst->i2c_adap, &m, 1); + mst->selected_interface = 0xff; // the first time force a select of the I2C + dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_TUNER); +} + +EXPORT_SYMBOL(dibx000_reset_i2c_master); + +static int i2c_adapter_init(struct i2c_adapter *i2c_adap, + struct i2c_algorithm *algo, const char *name, + struct dibx000_i2c_master *mst) { strncpy(i2c_adap->name, name, sizeof(i2c_adap->name)); - i2c_adap->class = I2C_CLASS_TV_DIGITAL, - i2c_adap->algo = algo; + i2c_adap->class = I2C_CLASS_TV_DIGITAL, i2c_adap->algo = algo; i2c_adap->algo_data = NULL; i2c_set_adapdata(i2c_adap, mst); if (i2c_add_adapter(i2c_adap) < 0) @@ -117,34 +138,40 @@ static int i2c_adapter_init(struct i2c_adapter *i2c_adap, struct i2c_algorithm * return 0; } -int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, u16 device_rev, struct i2c_adapter *i2c_adap, u8 i2c_addr) +int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, u16 device_rev, + struct i2c_adapter *i2c_adap, u8 i2c_addr) { u8 tx[4]; - struct i2c_msg m = { .addr = i2c_addr >> 1, .buf = tx, .len = 4 }; + struct i2c_msg m = {.addr = i2c_addr >> 1,.buf = tx,.len = 4 }; mst->device_rev = device_rev; - mst->i2c_adap = i2c_adap; - mst->i2c_addr = i2c_addr >> 1; + mst->i2c_adap = i2c_adap; + mst->i2c_addr = i2c_addr >> 1; - if (device_rev == DIB7000P) + if (device_rev == DIB7000P || device_rev == DIB8000) mst->base_reg = 1024; else mst->base_reg = 768; - if (i2c_adapter_init(&mst->gated_tuner_i2c_adap, &dibx000_i2c_gated_tuner_algo, "DiBX000 tuner I2C bus", mst) != 0) - printk(KERN_ERR "DiBX000: could not initialize the tuner i2c_adapter\n"); + if (i2c_adapter_init + (&mst->gated_tuner_i2c_adap, &dibx000_i2c_gated_tuner_algo, + "DiBX000 tuner I2C bus", mst) != 0) + printk(KERN_ERR + "DiBX000: could not initialize the tuner i2c_adapter\n"); /* initialize the i2c-master by closing the gate */ dibx000_i2c_gate_ctrl(mst, tx, 0, 0); return i2c_transfer(i2c_adap, &m, 1) == 1; } + EXPORT_SYMBOL(dibx000_init_i2c_master); void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst) { i2c_del_adapter(&mst->gated_tuner_i2c_adap); } + EXPORT_SYMBOL(dibx000_exit_i2c_master); MODULE_AUTHOR("Patrick Boettcher "); diff --git a/drivers/media/dvb/frontends/dibx000_common.h b/drivers/media/dvb/frontends/dibx000_common.h index 84e4d5362922..5be10eca07c0 100644 --- a/drivers/media/dvb/frontends/dibx000_common.h +++ b/drivers/media/dvb/frontends/dibx000_common.h @@ -2,7 +2,7 @@ #define DIBX000_COMMON_H enum dibx000_i2c_interface { - DIBX000_I2C_INTERFACE_TUNER = 0, + DIBX000_I2C_INTERFACE_TUNER = 0, DIBX000_I2C_INTERFACE_GPIO_1_2 = 1, DIBX000_I2C_INTERFACE_GPIO_3_4 = 2 }; @@ -12,22 +12,29 @@ struct dibx000_i2c_master { #define DIB7000 2 #define DIB7000P 11 #define DIB7000MC 12 +#define DIB8000 13 u16 device_rev; enum dibx000_i2c_interface selected_interface; -// struct i2c_adapter tuner_i2c_adap; - struct i2c_adapter gated_tuner_i2c_adap; +// struct i2c_adapter tuner_i2c_adap; + struct i2c_adapter gated_tuner_i2c_adap; struct i2c_adapter *i2c_adap; - u8 i2c_addr; + u8 i2c_addr; u16 base_reg; }; -extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, u16 device_rev, struct i2c_adapter *i2c_adap, u8 i2c_addr); -extern struct i2c_adapter * dibx000_get_i2c_adapter(struct dibx000_i2c_master *mst, enum dibx000_i2c_interface intf, int gating); +extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, + u16 device_rev, struct i2c_adapter *i2c_adap, + u8 i2c_addr); +extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master + *mst, + enum dibx000_i2c_interface + intf, int gating); extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst); +extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst); #define BAND_LBAND 0x01 #define BAND_UHF 0x02 @@ -41,18 +48,18 @@ extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst); (freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND ) struct dibx000_agc_config { - /* defines the capabilities of this AGC-setting - using the BAND_-defines*/ - u8 band_caps; + /* defines the capabilities of this AGC-setting - using the BAND_-defines */ + u8 band_caps; u16 setup; u16 inv_gain; u16 time_stabiliz; - u8 alpha_level; + u8 alpha_level; u16 thlock; - u8 wbd_inv; + u8 wbd_inv; u16 wbd_ref; u8 wbd_sel; u8 wbd_alpha; @@ -92,8 +99,8 @@ struct dibx000_agc_config { }; struct dibx000_bandwidth_config { - u32 internal; - u32 sampling; + u32 internal; + u32 sampling; u8 pll_prediv; u8 pll_ratio; diff --git a/drivers/media/dvb/frontends/lgdt3304.c b/drivers/media/dvb/frontends/lgdt3304.c index eb72a9866c93..e334b5d4e578 100644 --- a/drivers/media/dvb/frontends/lgdt3304.c +++ b/drivers/media/dvb/frontends/lgdt3304.c @@ -363,6 +363,8 @@ struct dvb_frontend* lgdt3304_attach(const struct lgdt3304_config *config, struct lgdt3304_state *state; state = kzalloc(sizeof(struct lgdt3304_state), GFP_KERNEL); + if (state == NULL) + return NULL; state->addr = config->i2c_address; state->i2c = i2c; diff --git a/drivers/media/dvb/frontends/s921_module.c b/drivers/media/dvb/frontends/s921_module.c index 3f5a0e1dfdf5..3156b64cfc96 100644 --- a/drivers/media/dvb/frontends/s921_module.c +++ b/drivers/media/dvb/frontends/s921_module.c @@ -169,6 +169,8 @@ struct dvb_frontend* s921_attach(const struct s921_config *config, struct s921_state *state; state = kzalloc(sizeof(struct s921_state), GFP_KERNEL); + if (state == NULL) + return NULL; state->addr = config->i2c_address; state->i2c = i2c; diff --git a/drivers/media/dvb/pt1/Kconfig b/drivers/media/dvb/pt1/Kconfig new file mode 100644 index 000000000000..24501d5bf70d --- /dev/null +++ b/drivers/media/dvb/pt1/Kconfig @@ -0,0 +1,12 @@ +config DVB_PT1 + tristate "PT1 cards" + depends on DVB_CORE && PCI && I2C + help + Support for Earthsoft PT1 PCI cards. + + Since these cards have no MPEG decoder onboard, they transmit + only compressed MPEG data over the PCI bus, so you need + an external software decoder to watch TV on your computer. + + Say Y or M if you own such a device and want to use it. + diff --git a/drivers/media/dvb/pt1/Makefile b/drivers/media/dvb/pt1/Makefile new file mode 100644 index 000000000000..a66da17bbe31 --- /dev/null +++ b/drivers/media/dvb/pt1/Makefile @@ -0,0 +1,5 @@ +earth-pt1-objs := pt1.o va1j5jf8007s.o va1j5jf8007t.o + +obj-$(CONFIG_DVB_PT1) += earth-pt1.o + +EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core -Idrivers/media/dvb/frontends diff --git a/drivers/media/dvb/pt1/pt1.c b/drivers/media/dvb/pt1/pt1.c new file mode 100644 index 000000000000..8ffbcecad931 --- /dev/null +++ b/drivers/media/dvb/pt1/pt1.c @@ -0,0 +1,1056 @@ +/* + * driver for Earthsoft PT1 + * + * Copyright (C) 2009 HIRANO Takahito + * + * based on pt1dvr - http://pt1dvr.sourceforge.jp/ + * by Tomoaki Ishikawa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include + +#include "dvbdev.h" +#include "dvb_demux.h" +#include "dmxdev.h" +#include "dvb_net.h" +#include "dvb_frontend.h" + +#include "va1j5jf8007t.h" +#include "va1j5jf8007s.h" + +#define DRIVER_NAME "earth-pt1" + +#define PT1_PAGE_SHIFT 12 +#define PT1_PAGE_SIZE (1 << PT1_PAGE_SHIFT) +#define PT1_NR_UPACKETS 1024 +#define PT1_NR_BUFS 511 + +struct pt1_buffer_page { + __le32 upackets[PT1_NR_UPACKETS]; +}; + +struct pt1_table_page { + __le32 next_pfn; + __le32 buf_pfns[PT1_NR_BUFS]; +}; + +struct pt1_buffer { + struct pt1_buffer_page *page; + dma_addr_t addr; +}; + +struct pt1_table { + struct pt1_table_page *page; + dma_addr_t addr; + struct pt1_buffer bufs[PT1_NR_BUFS]; +}; + +#define PT1_NR_ADAPS 4 + +struct pt1_adapter; + +struct pt1 { + struct pci_dev *pdev; + void __iomem *regs; + struct i2c_adapter i2c_adap; + int i2c_running; + struct pt1_adapter *adaps[PT1_NR_ADAPS]; + struct pt1_table *tables; + struct task_struct *kthread; +}; + +struct pt1_adapter { + struct pt1 *pt1; + int index; + + u8 *buf; + int upacket_count; + int packet_count; + + struct dvb_adapter adap; + struct dvb_demux demux; + int users; + struct dmxdev dmxdev; + struct dvb_net net; + struct dvb_frontend *fe; + int (*orig_set_voltage)(struct dvb_frontend *fe, + fe_sec_voltage_t voltage); +}; + +#define pt1_printk(level, pt1, format, arg...) \ + dev_printk(level, &(pt1)->pdev->dev, format, ##arg) + +static void pt1_write_reg(struct pt1 *pt1, int reg, u32 data) +{ + writel(data, pt1->regs + reg * 4); +} + +static u32 pt1_read_reg(struct pt1 *pt1, int reg) +{ + return readl(pt1->regs + reg * 4); +} + +static int pt1_nr_tables = 64; +module_param_named(nr_tables, pt1_nr_tables, int, 0); + +static void pt1_increment_table_count(struct pt1 *pt1) +{ + pt1_write_reg(pt1, 0, 0x00000020); +} + +static void pt1_init_table_count(struct pt1 *pt1) +{ + pt1_write_reg(pt1, 0, 0x00000010); +} + +static void pt1_register_tables(struct pt1 *pt1, u32 first_pfn) +{ + pt1_write_reg(pt1, 5, first_pfn); + pt1_write_reg(pt1, 0, 0x0c000040); +} + +static void pt1_unregister_tables(struct pt1 *pt1) +{ + pt1_write_reg(pt1, 0, 0x08080000); +} + +static int pt1_sync(struct pt1 *pt1) +{ + int i; + for (i = 0; i < 57; i++) { + if (pt1_read_reg(pt1, 0) & 0x20000000) + return 0; + pt1_write_reg(pt1, 0, 0x00000008); + } + pt1_printk(KERN_ERR, pt1, "could not sync\n"); + return -EIO; +} + +static u64 pt1_identify(struct pt1 *pt1) +{ + int i; + u64 id; + id = 0; + for (i = 0; i < 57; i++) { + id |= (u64)(pt1_read_reg(pt1, 0) >> 30 & 1) << i; + pt1_write_reg(pt1, 0, 0x00000008); + } + return id; +} + +static int pt1_unlock(struct pt1 *pt1) +{ + int i; + pt1_write_reg(pt1, 0, 0x00000008); + for (i = 0; i < 3; i++) { + if (pt1_read_reg(pt1, 0) & 0x80000000) + return 0; + schedule_timeout_uninterruptible((HZ + 999) / 1000); + } + pt1_printk(KERN_ERR, pt1, "could not unlock\n"); + return -EIO; +} + +static int pt1_reset_pci(struct pt1 *pt1) +{ + int i; + pt1_write_reg(pt1, 0, 0x01010000); + pt1_write_reg(pt1, 0, 0x01000000); + for (i = 0; i < 10; i++) { + if (pt1_read_reg(pt1, 0) & 0x00000001) + return 0; + schedule_timeout_uninterruptible((HZ + 999) / 1000); + } + pt1_printk(KERN_ERR, pt1, "could not reset PCI\n"); + return -EIO; +} + +static int pt1_reset_ram(struct pt1 *pt1) +{ + int i; + pt1_write_reg(pt1, 0, 0x02020000); + pt1_write_reg(pt1, 0, 0x02000000); + for (i = 0; i < 10; i++) { + if (pt1_read_reg(pt1, 0) & 0x00000002) + return 0; + schedule_timeout_uninterruptible((HZ + 999) / 1000); + } + pt1_printk(KERN_ERR, pt1, "could not reset RAM\n"); + return -EIO; +} + +static int pt1_do_enable_ram(struct pt1 *pt1) +{ + int i, j; + u32 status; + status = pt1_read_reg(pt1, 0) & 0x00000004; + pt1_write_reg(pt1, 0, 0x00000002); + for (i = 0; i < 10; i++) { + for (j = 0; j < 1024; j++) { + if ((pt1_read_reg(pt1, 0) & 0x00000004) != status) + return 0; + } + schedule_timeout_uninterruptible((HZ + 999) / 1000); + } + pt1_printk(KERN_ERR, pt1, "could not enable RAM\n"); + return -EIO; +} + +static int pt1_enable_ram(struct pt1 *pt1) +{ + int i, ret; + schedule_timeout_uninterruptible((HZ + 999) / 1000); + for (i = 0; i < 10; i++) { + ret = pt1_do_enable_ram(pt1); + if (ret < 0) + return ret; + } + return 0; +} + +static void pt1_disable_ram(struct pt1 *pt1) +{ + pt1_write_reg(pt1, 0, 0x0b0b0000); +} + +static void pt1_set_stream(struct pt1 *pt1, int index, int enabled) +{ + pt1_write_reg(pt1, 2, 1 << (index + 8) | enabled << index); +} + +static void pt1_init_streams(struct pt1 *pt1) +{ + int i; + for (i = 0; i < PT1_NR_ADAPS; i++) + pt1_set_stream(pt1, i, 0); +} + +static int pt1_filter(struct pt1 *pt1, struct pt1_buffer_page *page) +{ + u32 upacket; + int i; + int index; + struct pt1_adapter *adap; + int offset; + u8 *buf; + + if (!page->upackets[PT1_NR_UPACKETS - 1]) + return 0; + + for (i = 0; i < PT1_NR_UPACKETS; i++) { + upacket = le32_to_cpu(page->upackets[i]); + index = (upacket >> 29) - 1; + if (index < 0 || index >= PT1_NR_ADAPS) + continue; + + adap = pt1->adaps[index]; + if (upacket >> 25 & 1) + adap->upacket_count = 0; + else if (!adap->upacket_count) + continue; + + buf = adap->buf; + offset = adap->packet_count * 188 + adap->upacket_count * 3; + buf[offset] = upacket >> 16; + buf[offset + 1] = upacket >> 8; + if (adap->upacket_count != 62) + buf[offset + 2] = upacket; + + if (++adap->upacket_count >= 63) { + adap->upacket_count = 0; + if (++adap->packet_count >= 21) { + dvb_dmx_swfilter_packets(&adap->demux, buf, 21); + adap->packet_count = 0; + } + } + } + + page->upackets[PT1_NR_UPACKETS - 1] = 0; + return 1; +} + +static int pt1_thread(void *data) +{ + struct pt1 *pt1; + int table_index; + int buf_index; + struct pt1_buffer_page *page; + + pt1 = data; + set_freezable(); + + table_index = 0; + buf_index = 0; + + while (!kthread_should_stop()) { + try_to_freeze(); + + page = pt1->tables[table_index].bufs[buf_index].page; + if (!pt1_filter(pt1, page)) { + schedule_timeout_interruptible((HZ + 999) / 1000); + continue; + } + + if (++buf_index >= PT1_NR_BUFS) { + pt1_increment_table_count(pt1); + buf_index = 0; + if (++table_index >= pt1_nr_tables) + table_index = 0; + } + } + + return 0; +} + +static void pt1_free_page(struct pt1 *pt1, void *page, dma_addr_t addr) +{ + dma_free_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, page, addr); +} + +static void *pt1_alloc_page(struct pt1 *pt1, dma_addr_t *addrp, u32 *pfnp) +{ + void *page; + dma_addr_t addr; + + page = dma_alloc_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, &addr, + GFP_KERNEL); + if (page == NULL) + return NULL; + + BUG_ON(addr & (PT1_PAGE_SIZE - 1)); + BUG_ON(addr >> PT1_PAGE_SHIFT >> 31 >> 1); + + *addrp = addr; + *pfnp = addr >> PT1_PAGE_SHIFT; + return page; +} + +static void pt1_cleanup_buffer(struct pt1 *pt1, struct pt1_buffer *buf) +{ + pt1_free_page(pt1, buf->page, buf->addr); +} + +static int +pt1_init_buffer(struct pt1 *pt1, struct pt1_buffer *buf, u32 *pfnp) +{ + struct pt1_buffer_page *page; + dma_addr_t addr; + + page = pt1_alloc_page(pt1, &addr, pfnp); + if (page == NULL) + return -ENOMEM; + + page->upackets[PT1_NR_UPACKETS - 1] = 0; + + buf->page = page; + buf->addr = addr; + return 0; +} + +static void pt1_cleanup_table(struct pt1 *pt1, struct pt1_table *table) +{ + int i; + + for (i = 0; i < PT1_NR_BUFS; i++) + pt1_cleanup_buffer(pt1, &table->bufs[i]); + + pt1_free_page(pt1, table->page, table->addr); +} + +static int +pt1_init_table(struct pt1 *pt1, struct pt1_table *table, u32 *pfnp) +{ + struct pt1_table_page *page; + dma_addr_t addr; + int i, ret; + u32 buf_pfn; + + page = pt1_alloc_page(pt1, &addr, pfnp); + if (page == NULL) + return -ENOMEM; + + for (i = 0; i < PT1_NR_BUFS; i++) { + ret = pt1_init_buffer(pt1, &table->bufs[i], &buf_pfn); + if (ret < 0) + goto err; + + page->buf_pfns[i] = cpu_to_le32(buf_pfn); + } + + pt1_increment_table_count(pt1); + table->page = page; + table->addr = addr; + return 0; + +err: + while (i--) + pt1_cleanup_buffer(pt1, &table->bufs[i]); + + pt1_free_page(pt1, page, addr); + return ret; +} + +static void pt1_cleanup_tables(struct pt1 *pt1) +{ + struct pt1_table *tables; + int i; + + tables = pt1->tables; + pt1_unregister_tables(pt1); + + for (i = 0; i < pt1_nr_tables; i++) + pt1_cleanup_table(pt1, &tables[i]); + + vfree(tables); +} + +static int pt1_init_tables(struct pt1 *pt1) +{ + struct pt1_table *tables; + int i, ret; + u32 first_pfn, pfn; + + tables = vmalloc(sizeof(struct pt1_table) * pt1_nr_tables); + if (tables == NULL) + return -ENOMEM; + + pt1_init_table_count(pt1); + + i = 0; + if (pt1_nr_tables) { + ret = pt1_init_table(pt1, &tables[0], &first_pfn); + if (ret) + goto err; + i++; + } + + while (i < pt1_nr_tables) { + ret = pt1_init_table(pt1, &tables[i], &pfn); + if (ret) + goto err; + tables[i - 1].page->next_pfn = cpu_to_le32(pfn); + i++; + } + + tables[pt1_nr_tables - 1].page->next_pfn = cpu_to_le32(first_pfn); + + pt1_register_tables(pt1, first_pfn); + pt1->tables = tables; + return 0; + +err: + while (i--) + pt1_cleanup_table(pt1, &tables[i]); + + vfree(tables); + return ret; +} + +static int pt1_start_feed(struct dvb_demux_feed *feed) +{ + struct pt1_adapter *adap; + adap = container_of(feed->demux, struct pt1_adapter, demux); + if (!adap->users++) + pt1_set_stream(adap->pt1, adap->index, 1); + return 0; +} + +static int pt1_stop_feed(struct dvb_demux_feed *feed) +{ + struct pt1_adapter *adap; + adap = container_of(feed->demux, struct pt1_adapter, demux); + if (!--adap->users) + pt1_set_stream(adap->pt1, adap->index, 0); + return 0; +} + +static void +pt1_set_power(struct pt1 *pt1, int power, int lnb, int reset) +{ + pt1_write_reg(pt1, 1, power | lnb << 1 | !reset << 3); +} + +static int pt1_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) +{ + struct pt1_adapter *adap; + int lnb; + + adap = container_of(fe->dvb, struct pt1_adapter, adap); + + switch (voltage) { + case SEC_VOLTAGE_13: /* actually 11V */ + lnb = 2; + break; + case SEC_VOLTAGE_18: /* actually 15V */ + lnb = 3; + break; + case SEC_VOLTAGE_OFF: + lnb = 0; + break; + default: + return -EINVAL; + } + + pt1_set_power(adap->pt1, 1, lnb, 0); + + if (adap->orig_set_voltage) + return adap->orig_set_voltage(fe, voltage); + else + return 0; +} + +static void pt1_free_adapter(struct pt1_adapter *adap) +{ + dvb_unregister_frontend(adap->fe); + dvb_net_release(&adap->net); + adap->demux.dmx.close(&adap->demux.dmx); + dvb_dmxdev_release(&adap->dmxdev); + dvb_dmx_release(&adap->demux); + dvb_unregister_adapter(&adap->adap); + free_page((unsigned long)adap->buf); + kfree(adap); +} + +DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); + +static struct pt1_adapter * +pt1_alloc_adapter(struct pt1 *pt1, struct dvb_frontend *fe) +{ + struct pt1_adapter *adap; + void *buf; + struct dvb_adapter *dvb_adap; + struct dvb_demux *demux; + struct dmxdev *dmxdev; + int ret; + + adap = kzalloc(sizeof(struct pt1_adapter), GFP_KERNEL); + if (!adap) { + ret = -ENOMEM; + goto err; + } + + adap->pt1 = pt1; + + adap->orig_set_voltage = fe->ops.set_voltage; + fe->ops.set_voltage = pt1_set_voltage; + + buf = (u8 *)__get_free_page(GFP_KERNEL); + if (!buf) { + ret = -ENOMEM; + goto err_kfree; + } + + adap->buf = buf; + adap->upacket_count = 0; + adap->packet_count = 0; + + dvb_adap = &adap->adap; + dvb_adap->priv = adap; + ret = dvb_register_adapter(dvb_adap, DRIVER_NAME, THIS_MODULE, + &pt1->pdev->dev, adapter_nr); + if (ret < 0) + goto err_free_page; + + demux = &adap->demux; + demux->dmx.capabilities = DMX_TS_FILTERING | DMX_SECTION_FILTERING; + demux->priv = adap; + demux->feednum = 256; + demux->filternum = 256; + demux->start_feed = pt1_start_feed; + demux->stop_feed = pt1_stop_feed; + demux->write_to_decoder = NULL; + ret = dvb_dmx_init(demux); + if (ret < 0) + goto err_unregister_adapter; + + dmxdev = &adap->dmxdev; + dmxdev->filternum = 256; + dmxdev->demux = &demux->dmx; + dmxdev->capabilities = 0; + ret = dvb_dmxdev_init(dmxdev, dvb_adap); + if (ret < 0) + goto err_dmx_release; + + dvb_net_init(dvb_adap, &adap->net, &demux->dmx); + + ret = dvb_register_frontend(dvb_adap, fe); + if (ret < 0) + goto err_net_release; + adap->fe = fe; + + return adap; + +err_net_release: + dvb_net_release(&adap->net); + adap->demux.dmx.close(&adap->demux.dmx); + dvb_dmxdev_release(&adap->dmxdev); +err_dmx_release: + dvb_dmx_release(demux); +err_unregister_adapter: + dvb_unregister_adapter(dvb_adap); +err_free_page: + free_page((unsigned long)buf); +err_kfree: + kfree(adap); +err: + return ERR_PTR(ret); +} + +static void pt1_cleanup_adapters(struct pt1 *pt1) +{ + int i; + for (i = 0; i < PT1_NR_ADAPS; i++) + pt1_free_adapter(pt1->adaps[i]); +} + +struct pt1_config { + struct va1j5jf8007s_config va1j5jf8007s_config; + struct va1j5jf8007t_config va1j5jf8007t_config; +}; + +static const struct pt1_config pt1_configs[2] = { + { + { .demod_address = 0x1b }, + { .demod_address = 0x1a }, + }, { + { .demod_address = 0x19 }, + { .demod_address = 0x18 }, + }, +}; + +static int pt1_init_adapters(struct pt1 *pt1) +{ + int i, j; + struct i2c_adapter *i2c_adap; + const struct pt1_config *config; + struct dvb_frontend *fe[4]; + struct pt1_adapter *adap; + int ret; + + i = 0; + j = 0; + + i2c_adap = &pt1->i2c_adap; + do { + config = &pt1_configs[i / 2]; + + fe[i] = va1j5jf8007s_attach(&config->va1j5jf8007s_config, + i2c_adap); + if (!fe[i]) { + ret = -ENODEV; /* This does not sound nice... */ + goto err; + } + i++; + + fe[i] = va1j5jf8007t_attach(&config->va1j5jf8007t_config, + i2c_adap); + if (!fe[i]) { + ret = -ENODEV; + goto err; + } + i++; + + ret = va1j5jf8007s_prepare(fe[i - 2]); + if (ret < 0) + goto err; + + ret = va1j5jf8007t_prepare(fe[i - 1]); + if (ret < 0) + goto err; + + } while (i < 4); + + do { + adap = pt1_alloc_adapter(pt1, fe[j]); + if (IS_ERR(adap)) + goto err; + adap->index = j; + pt1->adaps[j] = adap; + } while (++j < 4); + + return 0; + +err: + while (i-- > j) + fe[i]->ops.release(fe[i]); + + while (j--) + pt1_free_adapter(pt1->adaps[j]); + + return ret; +} + +static void pt1_i2c_emit(struct pt1 *pt1, int addr, int busy, int read_enable, + int clock, int data, int next_addr) +{ + pt1_write_reg(pt1, 4, addr << 18 | busy << 13 | read_enable << 12 | + !clock << 11 | !data << 10 | next_addr); +} + +static void pt1_i2c_write_bit(struct pt1 *pt1, int addr, int *addrp, int data) +{ + pt1_i2c_emit(pt1, addr, 1, 0, 0, data, addr + 1); + pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, data, addr + 2); + pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, data, addr + 3); + *addrp = addr + 3; +} + +static void pt1_i2c_read_bit(struct pt1 *pt1, int addr, int *addrp) +{ + pt1_i2c_emit(pt1, addr, 1, 0, 0, 1, addr + 1); + pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 1, addr + 2); + pt1_i2c_emit(pt1, addr + 2, 1, 1, 1, 1, addr + 3); + pt1_i2c_emit(pt1, addr + 3, 1, 0, 0, 1, addr + 4); + *addrp = addr + 4; +} + +static void pt1_i2c_write_byte(struct pt1 *pt1, int addr, int *addrp, int data) +{ + int i; + for (i = 0; i < 8; i++) + pt1_i2c_write_bit(pt1, addr, &addr, data >> (7 - i) & 1); + pt1_i2c_write_bit(pt1, addr, &addr, 1); + *addrp = addr; +} + +static void pt1_i2c_read_byte(struct pt1 *pt1, int addr, int *addrp, int last) +{ + int i; + for (i = 0; i < 8; i++) + pt1_i2c_read_bit(pt1, addr, &addr); + pt1_i2c_write_bit(pt1, addr, &addr, last); + *addrp = addr; +} + +static void pt1_i2c_prepare(struct pt1 *pt1, int addr, int *addrp) +{ + pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1); + pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2); + pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, 0, addr + 3); + *addrp = addr + 3; +} + +static void +pt1_i2c_write_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg) +{ + int i; + pt1_i2c_prepare(pt1, addr, &addr); + pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1); + for (i = 0; i < msg->len; i++) + pt1_i2c_write_byte(pt1, addr, &addr, msg->buf[i]); + *addrp = addr; +} + +static void +pt1_i2c_read_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg) +{ + int i; + pt1_i2c_prepare(pt1, addr, &addr); + pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1 | 1); + for (i = 0; i < msg->len; i++) + pt1_i2c_read_byte(pt1, addr, &addr, i == msg->len - 1); + *addrp = addr; +} + +static int pt1_i2c_end(struct pt1 *pt1, int addr) +{ + pt1_i2c_emit(pt1, addr, 1, 0, 0, 0, addr + 1); + pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2); + pt1_i2c_emit(pt1, addr + 2, 1, 0, 1, 1, 0); + + pt1_write_reg(pt1, 0, 0x00000004); + do { + if (signal_pending(current)) + return -EINTR; + schedule_timeout_interruptible((HZ + 999) / 1000); + } while (pt1_read_reg(pt1, 0) & 0x00000080); + return 0; +} + +static void pt1_i2c_begin(struct pt1 *pt1, int *addrp) +{ + int addr; + addr = 0; + + pt1_i2c_emit(pt1, addr, 0, 0, 1, 1, addr /* itself */); + addr = addr + 1; + + if (!pt1->i2c_running) { + pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1); + pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2); + addr = addr + 2; + pt1->i2c_running = 1; + } + *addrp = addr; +} + +static int pt1_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) +{ + struct pt1 *pt1; + int i; + struct i2c_msg *msg, *next_msg; + int addr, ret; + u16 len; + u32 word; + + pt1 = i2c_get_adapdata(adap); + + for (i = 0; i < num; i++) { + msg = &msgs[i]; + if (msg->flags & I2C_M_RD) + return -ENOTSUPP; + + if (i + 1 < num) + next_msg = &msgs[i + 1]; + else + next_msg = NULL; + + if (next_msg && next_msg->flags & I2C_M_RD) { + i++; + + len = next_msg->len; + if (len > 4) + return -ENOTSUPP; + + pt1_i2c_begin(pt1, &addr); + pt1_i2c_write_msg(pt1, addr, &addr, msg); + pt1_i2c_read_msg(pt1, addr, &addr, next_msg); + ret = pt1_i2c_end(pt1, addr); + if (ret < 0) + return ret; + + word = pt1_read_reg(pt1, 2); + while (len--) { + next_msg->buf[len] = word; + word >>= 8; + } + } else { + pt1_i2c_begin(pt1, &addr); + pt1_i2c_write_msg(pt1, addr, &addr, msg); + ret = pt1_i2c_end(pt1, addr); + if (ret < 0) + return ret; + } + } + + return num; +} + +static u32 pt1_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C; +} + +static const struct i2c_algorithm pt1_i2c_algo = { + .master_xfer = pt1_i2c_xfer, + .functionality = pt1_i2c_func, +}; + +static void pt1_i2c_wait(struct pt1 *pt1) +{ + int i; + for (i = 0; i < 128; i++) + pt1_i2c_emit(pt1, 0, 0, 0, 1, 1, 0); +} + +static void pt1_i2c_init(struct pt1 *pt1) +{ + int i; + for (i = 0; i < 1024; i++) + pt1_i2c_emit(pt1, i, 0, 0, 1, 1, 0); +} + +static void __devexit pt1_remove(struct pci_dev *pdev) +{ + struct pt1 *pt1; + void __iomem *regs; + + pt1 = pci_get_drvdata(pdev); + regs = pt1->regs; + + kthread_stop(pt1->kthread); + pt1_cleanup_tables(pt1); + pt1_cleanup_adapters(pt1); + pt1_disable_ram(pt1); + pt1_set_power(pt1, 0, 0, 1); + i2c_del_adapter(&pt1->i2c_adap); + pci_set_drvdata(pdev, NULL); + kfree(pt1); + pci_iounmap(pdev, regs); + pci_release_regions(pdev); + pci_disable_device(pdev); +} + +static int __devinit +pt1_probe(struct pci_dev *pdev, const struct pci_device_id *ent) +{ + int ret; + void __iomem *regs; + struct pt1 *pt1; + struct i2c_adapter *i2c_adap; + struct task_struct *kthread; + + ret = pci_enable_device(pdev); + if (ret < 0) + goto err; + + ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + if (ret < 0) + goto err_pci_disable_device; + + pci_set_master(pdev); + + ret = pci_request_regions(pdev, DRIVER_NAME); + if (ret < 0) + goto err_pci_disable_device; + + regs = pci_iomap(pdev, 0, 0); + if (!regs) { + ret = -EIO; + goto err_pci_release_regions; + } + + pt1 = kzalloc(sizeof(struct pt1), GFP_KERNEL); + if (!pt1) { + ret = -ENOMEM; + goto err_pci_iounmap; + } + + pt1->pdev = pdev; + pt1->regs = regs; + pci_set_drvdata(pdev, pt1); + + i2c_adap = &pt1->i2c_adap; + i2c_adap->class = I2C_CLASS_TV_DIGITAL; + i2c_adap->algo = &pt1_i2c_algo; + i2c_adap->algo_data = NULL; + i2c_adap->dev.parent = &pdev->dev; + i2c_set_adapdata(i2c_adap, pt1); + ret = i2c_add_adapter(i2c_adap); + if (ret < 0) + goto err_kfree; + + pt1_set_power(pt1, 0, 0, 1); + + pt1_i2c_init(pt1); + pt1_i2c_wait(pt1); + + ret = pt1_sync(pt1); + if (ret < 0) + goto err_i2c_del_adapter; + + pt1_identify(pt1); + + ret = pt1_unlock(pt1); + if (ret < 0) + goto err_i2c_del_adapter; + + ret = pt1_reset_pci(pt1); + if (ret < 0) + goto err_i2c_del_adapter; + + ret = pt1_reset_ram(pt1); + if (ret < 0) + goto err_i2c_del_adapter; + + ret = pt1_enable_ram(pt1); + if (ret < 0) + goto err_i2c_del_adapter; + + pt1_init_streams(pt1); + + pt1_set_power(pt1, 1, 0, 1); + schedule_timeout_uninterruptible((HZ + 49) / 50); + + pt1_set_power(pt1, 1, 0, 0); + schedule_timeout_uninterruptible((HZ + 999) / 1000); + + ret = pt1_init_adapters(pt1); + if (ret < 0) + goto err_pt1_disable_ram; + + ret = pt1_init_tables(pt1); + if (ret < 0) + goto err_pt1_cleanup_adapters; + + kthread = kthread_run(pt1_thread, pt1, "pt1"); + if (IS_ERR(kthread)) { + ret = PTR_ERR(kthread); + goto err_pt1_cleanup_tables; + } + + pt1->kthread = kthread; + return 0; + +err_pt1_cleanup_tables: + pt1_cleanup_tables(pt1); +err_pt1_cleanup_adapters: + pt1_cleanup_adapters(pt1); +err_pt1_disable_ram: + pt1_disable_ram(pt1); + pt1_set_power(pt1, 0, 0, 1); +err_i2c_del_adapter: + i2c_del_adapter(i2c_adap); +err_kfree: + pci_set_drvdata(pdev, NULL); + kfree(pt1); +err_pci_iounmap: + pci_iounmap(pdev, regs); +err_pci_release_regions: + pci_release_regions(pdev); +err_pci_disable_device: + pci_disable_device(pdev); +err: + return ret; + +} + +static struct pci_device_id pt1_id_table[] = { + { PCI_DEVICE(0x10ee, 0x211a) }, + { }, +}; +MODULE_DEVICE_TABLE(pci, pt1_id_table); + +static struct pci_driver pt1_driver = { + .name = DRIVER_NAME, + .probe = pt1_probe, + .remove = __devexit_p(pt1_remove), + .id_table = pt1_id_table, +}; + + +static int __init pt1_init(void) +{ + return pci_register_driver(&pt1_driver); +} + + +static void __exit pt1_cleanup(void) +{ + pci_unregister_driver(&pt1_driver); +} + +module_init(pt1_init); +module_exit(pt1_cleanup); + +MODULE_AUTHOR("Takahito HIRANO "); +MODULE_DESCRIPTION("Earthsoft PT1 Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb/pt1/va1j5jf8007s.c b/drivers/media/dvb/pt1/va1j5jf8007s.c new file mode 100644 index 000000000000..2db940f8635f --- /dev/null +++ b/drivers/media/dvb/pt1/va1j5jf8007s.c @@ -0,0 +1,658 @@ +/* + * ISDB-S driver for VA1J5JF8007 + * + * Copyright (C) 2009 HIRANO Takahito + * + * based on pt1dvr - http://pt1dvr.sourceforge.jp/ + * by Tomoaki Ishikawa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include "dvb_frontend.h" +#include "va1j5jf8007s.h" + +enum va1j5jf8007s_tune_state { + VA1J5JF8007S_IDLE, + VA1J5JF8007S_SET_FREQUENCY_1, + VA1J5JF8007S_SET_FREQUENCY_2, + VA1J5JF8007S_SET_FREQUENCY_3, + VA1J5JF8007S_CHECK_FREQUENCY, + VA1J5JF8007S_SET_MODULATION, + VA1J5JF8007S_CHECK_MODULATION, + VA1J5JF8007S_SET_TS_ID, + VA1J5JF8007S_CHECK_TS_ID, + VA1J5JF8007S_TRACK, +}; + +struct va1j5jf8007s_state { + const struct va1j5jf8007s_config *config; + struct i2c_adapter *adap; + struct dvb_frontend fe; + enum va1j5jf8007s_tune_state tune_state; +}; + +static int va1j5jf8007s_get_frontend_algo(struct dvb_frontend *fe) +{ + return DVBFE_ALGO_HW; +} + +static int +va1j5jf8007s_read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct va1j5jf8007s_state *state; + + state = fe->demodulator_priv; + + switch (state->tune_state) { + case VA1J5JF8007S_IDLE: + case VA1J5JF8007S_SET_FREQUENCY_1: + case VA1J5JF8007S_SET_FREQUENCY_2: + case VA1J5JF8007S_SET_FREQUENCY_3: + case VA1J5JF8007S_CHECK_FREQUENCY: + *status = 0; + return 0; + + + case VA1J5JF8007S_SET_MODULATION: + case VA1J5JF8007S_CHECK_MODULATION: + *status |= FE_HAS_SIGNAL; + return 0; + + case VA1J5JF8007S_SET_TS_ID: + case VA1J5JF8007S_CHECK_TS_ID: + *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER; + return 0; + + case VA1J5JF8007S_TRACK: + *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_LOCK; + return 0; + } + + BUG(); +} + +struct va1j5jf8007s_cb_map { + u32 frequency; + u8 cb; +}; + +static const struct va1j5jf8007s_cb_map va1j5jf8007s_cb_maps[] = { + { 986000, 0xb2 }, + { 1072000, 0xd2 }, + { 1154000, 0xe2 }, + { 1291000, 0x20 }, + { 1447000, 0x40 }, + { 1615000, 0x60 }, + { 1791000, 0x80 }, + { 1972000, 0xa0 }, +}; + +static u8 va1j5jf8007s_lookup_cb(u32 frequency) +{ + int i; + const struct va1j5jf8007s_cb_map *map; + + for (i = 0; i < ARRAY_SIZE(va1j5jf8007s_cb_maps); i++) { + map = &va1j5jf8007s_cb_maps[i]; + if (frequency < map->frequency) + return map->cb; + } + return 0xc0; +} + +static int va1j5jf8007s_set_frequency_1(struct va1j5jf8007s_state *state) +{ + u32 frequency; + u16 word; + u8 buf[6]; + struct i2c_msg msg; + + frequency = state->fe.dtv_property_cache.frequency; + + word = (frequency + 500) / 1000; + if (frequency < 1072000) + word = (word << 1 & ~0x1f) | (word & 0x0f); + + buf[0] = 0xfe; + buf[1] = 0xc0; + buf[2] = 0x40 | word >> 8; + buf[3] = word; + buf[4] = 0xe0; + buf[5] = va1j5jf8007s_lookup_cb(frequency); + + msg.addr = state->config->demod_address; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(state->adap, &msg, 1) != 1) + return -EREMOTEIO; + + return 0; +} + +static int va1j5jf8007s_set_frequency_2(struct va1j5jf8007s_state *state) +{ + u8 buf[3]; + struct i2c_msg msg; + + buf[0] = 0xfe; + buf[1] = 0xc0; + buf[2] = 0xe4; + + msg.addr = state->config->demod_address; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(state->adap, &msg, 1) != 1) + return -EREMOTEIO; + + return 0; +} + +static int va1j5jf8007s_set_frequency_3(struct va1j5jf8007s_state *state) +{ + u32 frequency; + u8 buf[4]; + struct i2c_msg msg; + + frequency = state->fe.dtv_property_cache.frequency; + + buf[0] = 0xfe; + buf[1] = 0xc0; + buf[2] = 0xf4; + buf[3] = va1j5jf8007s_lookup_cb(frequency) | 0x4; + + msg.addr = state->config->demod_address; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(state->adap, &msg, 1) != 1) + return -EREMOTEIO; + + return 0; +} + +static int +va1j5jf8007s_check_frequency(struct va1j5jf8007s_state *state, int *lock) +{ + u8 addr; + u8 write_buf[2], read_buf[1]; + struct i2c_msg msgs[2]; + + addr = state->config->demod_address; + + write_buf[0] = 0xfe; + write_buf[1] = 0xc1; + + msgs[0].addr = addr; + msgs[0].flags = 0; + msgs[0].len = sizeof(write_buf); + msgs[0].buf = write_buf; + + msgs[1].addr = addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = sizeof(read_buf); + msgs[1].buf = read_buf; + + if (i2c_transfer(state->adap, msgs, 2) != 2) + return -EREMOTEIO; + + *lock = read_buf[0] & 0x40; + return 0; +} + +static int va1j5jf8007s_set_modulation(struct va1j5jf8007s_state *state) +{ + u8 buf[2]; + struct i2c_msg msg; + + buf[0] = 0x03; + buf[1] = 0x01; + + msg.addr = state->config->demod_address; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(state->adap, &msg, 1) != 1) + return -EREMOTEIO; + + return 0; +} + +static int +va1j5jf8007s_check_modulation(struct va1j5jf8007s_state *state, int *lock) +{ + u8 addr; + u8 write_buf[1], read_buf[1]; + struct i2c_msg msgs[2]; + + addr = state->config->demod_address; + + write_buf[0] = 0xc3; + + msgs[0].addr = addr; + msgs[0].flags = 0; + msgs[0].len = sizeof(write_buf); + msgs[0].buf = write_buf; + + msgs[1].addr = addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = sizeof(read_buf); + msgs[1].buf = read_buf; + + if (i2c_transfer(state->adap, msgs, 2) != 2) + return -EREMOTEIO; + + *lock = !(read_buf[0] & 0x10); + return 0; +} + +static int +va1j5jf8007s_set_ts_id(struct va1j5jf8007s_state *state) +{ + u32 ts_id; + u8 buf[3]; + struct i2c_msg msg; + + ts_id = state->fe.dtv_property_cache.isdbs_ts_id; + if (!ts_id) + return 0; + + buf[0] = 0x8f; + buf[1] = ts_id >> 8; + buf[2] = ts_id; + + msg.addr = state->config->demod_address; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(state->adap, &msg, 1) != 1) + return -EREMOTEIO; + + return 0; +} + +static int +va1j5jf8007s_check_ts_id(struct va1j5jf8007s_state *state, int *lock) +{ + u8 addr; + u8 write_buf[1], read_buf[2]; + struct i2c_msg msgs[2]; + u32 ts_id; + + ts_id = state->fe.dtv_property_cache.isdbs_ts_id; + if (!ts_id) { + *lock = 1; + return 0; + } + + addr = state->config->demod_address; + + write_buf[0] = 0xe6; + + msgs[0].addr = addr; + msgs[0].flags = 0; + msgs[0].len = sizeof(write_buf); + msgs[0].buf = write_buf; + + msgs[1].addr = addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = sizeof(read_buf); + msgs[1].buf = read_buf; + + if (i2c_transfer(state->adap, msgs, 2) != 2) + return -EREMOTEIO; + + *lock = (read_buf[0] << 8 | read_buf[1]) == ts_id; + return 0; +} + +static int +va1j5jf8007s_tune(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params, + unsigned int mode_flags, unsigned int *delay, + fe_status_t *status) +{ + struct va1j5jf8007s_state *state; + int ret; + int lock; + + state = fe->demodulator_priv; + + if (params != NULL) + state->tune_state = VA1J5JF8007S_SET_FREQUENCY_1; + + switch (state->tune_state) { + case VA1J5JF8007S_IDLE: + *delay = 3 * HZ; + *status = 0; + return 0; + + case VA1J5JF8007S_SET_FREQUENCY_1: + ret = va1j5jf8007s_set_frequency_1(state); + if (ret < 0) + return ret; + + state->tune_state = VA1J5JF8007S_SET_FREQUENCY_2; + *delay = 0; + *status = 0; + return 0; + + case VA1J5JF8007S_SET_FREQUENCY_2: + ret = va1j5jf8007s_set_frequency_2(state); + if (ret < 0) + return ret; + + state->tune_state = VA1J5JF8007S_SET_FREQUENCY_3; + *delay = (HZ + 99) / 100; + *status = 0; + return 0; + + case VA1J5JF8007S_SET_FREQUENCY_3: + ret = va1j5jf8007s_set_frequency_3(state); + if (ret < 0) + return ret; + + state->tune_state = VA1J5JF8007S_CHECK_FREQUENCY; + *delay = 0; + *status = 0; + return 0; + + case VA1J5JF8007S_CHECK_FREQUENCY: + ret = va1j5jf8007s_check_frequency(state, &lock); + if (ret < 0) + return ret; + + if (!lock) { + *delay = (HZ + 999) / 1000; + *status = 0; + return 0; + } + + state->tune_state = VA1J5JF8007S_SET_MODULATION; + *delay = 0; + *status = FE_HAS_SIGNAL; + return 0; + + case VA1J5JF8007S_SET_MODULATION: + ret = va1j5jf8007s_set_modulation(state); + if (ret < 0) + return ret; + + state->tune_state = VA1J5JF8007S_CHECK_MODULATION; + *delay = 0; + *status = FE_HAS_SIGNAL; + return 0; + + case VA1J5JF8007S_CHECK_MODULATION: + ret = va1j5jf8007s_check_modulation(state, &lock); + if (ret < 0) + return ret; + + if (!lock) { + *delay = (HZ + 49) / 50; + *status = FE_HAS_SIGNAL; + return 0; + } + + state->tune_state = VA1J5JF8007S_SET_TS_ID; + *delay = 0; + *status = FE_HAS_SIGNAL | FE_HAS_CARRIER; + return 0; + + case VA1J5JF8007S_SET_TS_ID: + ret = va1j5jf8007s_set_ts_id(state); + if (ret < 0) + return ret; + + state->tune_state = VA1J5JF8007S_CHECK_TS_ID; + return 0; + + case VA1J5JF8007S_CHECK_TS_ID: + ret = va1j5jf8007s_check_ts_id(state, &lock); + if (ret < 0) + return ret; + + if (!lock) { + *delay = (HZ + 99) / 100; + *status = FE_HAS_SIGNAL | FE_HAS_CARRIER; + return 0; + } + + state->tune_state = VA1J5JF8007S_TRACK; + /* fall through */ + + case VA1J5JF8007S_TRACK: + *delay = 3 * HZ; + *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_LOCK; + return 0; + } + + BUG(); +} + +static int va1j5jf8007s_init_frequency(struct va1j5jf8007s_state *state) +{ + u8 buf[4]; + struct i2c_msg msg; + + buf[0] = 0xfe; + buf[1] = 0xc0; + buf[2] = 0xf0; + buf[3] = 0x04; + + msg.addr = state->config->demod_address; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(state->adap, &msg, 1) != 1) + return -EREMOTEIO; + + return 0; +} + +static int va1j5jf8007s_set_sleep(struct va1j5jf8007s_state *state, int sleep) +{ + u8 buf[2]; + struct i2c_msg msg; + + buf[0] = 0x17; + buf[1] = sleep ? 0x01 : 0x00; + + msg.addr = state->config->demod_address; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(state->adap, &msg, 1) != 1) + return -EREMOTEIO; + + return 0; +} + +static int va1j5jf8007s_sleep(struct dvb_frontend *fe) +{ + struct va1j5jf8007s_state *state; + int ret; + + state = fe->demodulator_priv; + + ret = va1j5jf8007s_init_frequency(state); + if (ret < 0) + return ret; + + return va1j5jf8007s_set_sleep(state, 1); +} + +static int va1j5jf8007s_init(struct dvb_frontend *fe) +{ + struct va1j5jf8007s_state *state; + + state = fe->demodulator_priv; + state->tune_state = VA1J5JF8007S_IDLE; + + return va1j5jf8007s_set_sleep(state, 0); +} + +static void va1j5jf8007s_release(struct dvb_frontend *fe) +{ + struct va1j5jf8007s_state *state; + state = fe->demodulator_priv; + kfree(state); +} + +static struct dvb_frontend_ops va1j5jf8007s_ops = { + .info = { + .name = "VA1J5JF8007 ISDB-S", + .type = FE_QPSK, + .frequency_min = 950000, + .frequency_max = 2150000, + .frequency_stepsize = 1000, + .caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO | + FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO, + }, + + .get_frontend_algo = va1j5jf8007s_get_frontend_algo, + .read_status = va1j5jf8007s_read_status, + .tune = va1j5jf8007s_tune, + .sleep = va1j5jf8007s_sleep, + .init = va1j5jf8007s_init, + .release = va1j5jf8007s_release, +}; + +static int va1j5jf8007s_prepare_1(struct va1j5jf8007s_state *state) +{ + u8 addr; + u8 write_buf[1], read_buf[1]; + struct i2c_msg msgs[2]; + + addr = state->config->demod_address; + + write_buf[0] = 0x07; + + msgs[0].addr = addr; + msgs[0].flags = 0; + msgs[0].len = sizeof(write_buf); + msgs[0].buf = write_buf; + + msgs[1].addr = addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = sizeof(read_buf); + msgs[1].buf = read_buf; + + if (i2c_transfer(state->adap, msgs, 2) != 2) + return -EREMOTEIO; + + if (read_buf[0] != 0x41) + return -EIO; + + return 0; +} + +static const u8 va1j5jf8007s_prepare_bufs[][2] = { + {0x04, 0x02}, {0x0d, 0x55}, {0x11, 0x40}, {0x13, 0x80}, {0x17, 0x01}, + {0x1c, 0x0a}, {0x1d, 0xaa}, {0x1e, 0x20}, {0x1f, 0x88}, {0x51, 0xb0}, + {0x52, 0x89}, {0x53, 0xb3}, {0x5a, 0x2d}, {0x5b, 0xd3}, {0x85, 0x69}, + {0x87, 0x04}, {0x8e, 0x02}, {0xa3, 0xf7}, {0xa5, 0xc0}, +}; + +static int va1j5jf8007s_prepare_2(struct va1j5jf8007s_state *state) +{ + u8 addr; + u8 buf[2]; + struct i2c_msg msg; + int i; + + addr = state->config->demod_address; + + msg.addr = addr; + msg.flags = 0; + msg.len = 2; + msg.buf = buf; + for (i = 0; i < ARRAY_SIZE(va1j5jf8007s_prepare_bufs); i++) { + memcpy(buf, va1j5jf8007s_prepare_bufs[i], sizeof(buf)); + if (i2c_transfer(state->adap, &msg, 1) != 1) + return -EREMOTEIO; + } + + return 0; +} + +/* must be called after va1j5jf8007t_attach */ +int va1j5jf8007s_prepare(struct dvb_frontend *fe) +{ + struct va1j5jf8007s_state *state; + int ret; + + state = fe->demodulator_priv; + + ret = va1j5jf8007s_prepare_1(state); + if (ret < 0) + return ret; + + ret = va1j5jf8007s_prepare_2(state); + if (ret < 0) + return ret; + + return va1j5jf8007s_init_frequency(state); +} + +struct dvb_frontend * +va1j5jf8007s_attach(const struct va1j5jf8007s_config *config, + struct i2c_adapter *adap) +{ + struct va1j5jf8007s_state *state; + struct dvb_frontend *fe; + u8 buf[2]; + struct i2c_msg msg; + + state = kzalloc(sizeof(struct va1j5jf8007s_state), GFP_KERNEL); + if (!state) + return NULL; + + state->config = config; + state->adap = adap; + + fe = &state->fe; + memcpy(&fe->ops, &va1j5jf8007s_ops, sizeof(struct dvb_frontend_ops)); + fe->demodulator_priv = state; + + buf[0] = 0x01; + buf[1] = 0x80; + + msg.addr = state->config->demod_address; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(state->adap, &msg, 1) != 1) { + kfree(state); + return NULL; + } + + return fe; +} diff --git a/drivers/media/dvb/pt1/va1j5jf8007s.h b/drivers/media/dvb/pt1/va1j5jf8007s.h new file mode 100644 index 000000000000..aa228a816353 --- /dev/null +++ b/drivers/media/dvb/pt1/va1j5jf8007s.h @@ -0,0 +1,40 @@ +/* + * ISDB-S driver for VA1J5JF8007 + * + * Copyright (C) 2009 HIRANO Takahito + * + * based on pt1dvr - http://pt1dvr.sourceforge.jp/ + * by Tomoaki Ishikawa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef VA1J5JF8007S_H +#define VA1J5JF8007S_H + +struct va1j5jf8007s_config { + u8 demod_address; +}; + +struct i2c_adapter; + +struct dvb_frontend * +va1j5jf8007s_attach(const struct va1j5jf8007s_config *config, + struct i2c_adapter *adap); + +/* must be called after va1j5jf8007t_attach */ +int va1j5jf8007s_prepare(struct dvb_frontend *fe); + +#endif diff --git a/drivers/media/dvb/pt1/va1j5jf8007t.c b/drivers/media/dvb/pt1/va1j5jf8007t.c new file mode 100644 index 000000000000..71117f4ca7e6 --- /dev/null +++ b/drivers/media/dvb/pt1/va1j5jf8007t.c @@ -0,0 +1,468 @@ +/* + * ISDB-T driver for VA1J5JF8007 + * + * Copyright (C) 2009 HIRANO Takahito + * + * based on pt1dvr - http://pt1dvr.sourceforge.jp/ + * by Tomoaki Ishikawa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include "dvb_frontend.h" +#include "dvb_math.h" +#include "va1j5jf8007t.h" + +enum va1j5jf8007t_tune_state { + VA1J5JF8007T_IDLE, + VA1J5JF8007T_SET_FREQUENCY, + VA1J5JF8007T_CHECK_FREQUENCY, + VA1J5JF8007T_SET_MODULATION, + VA1J5JF8007T_CHECK_MODULATION, + VA1J5JF8007T_TRACK, + VA1J5JF8007T_ABORT, +}; + +struct va1j5jf8007t_state { + const struct va1j5jf8007t_config *config; + struct i2c_adapter *adap; + struct dvb_frontend fe; + enum va1j5jf8007t_tune_state tune_state; +}; + +static int va1j5jf8007t_get_frontend_algo(struct dvb_frontend *fe) +{ + return DVBFE_ALGO_HW; +} + +static int +va1j5jf8007t_read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct va1j5jf8007t_state *state; + + state = fe->demodulator_priv; + + switch (state->tune_state) { + case VA1J5JF8007T_IDLE: + case VA1J5JF8007T_SET_FREQUENCY: + case VA1J5JF8007T_CHECK_FREQUENCY: + *status = 0; + return 0; + + + case VA1J5JF8007T_SET_MODULATION: + case VA1J5JF8007T_CHECK_MODULATION: + case VA1J5JF8007T_ABORT: + *status |= FE_HAS_SIGNAL; + return 0; + + case VA1J5JF8007T_TRACK: + *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_LOCK; + return 0; + } + + BUG(); +} + +struct va1j5jf8007t_cb_map { + u32 frequency; + u8 cb; +}; + +static const struct va1j5jf8007t_cb_map va1j5jf8007t_cb_maps[] = { + { 90000000, 0x80 }, + { 140000000, 0x81 }, + { 170000000, 0xa1 }, + { 220000000, 0x62 }, + { 330000000, 0xa2 }, + { 402000000, 0xe2 }, + { 450000000, 0x64 }, + { 550000000, 0x84 }, + { 600000000, 0xa4 }, + { 700000000, 0xc4 }, +}; + +static u8 va1j5jf8007t_lookup_cb(u32 frequency) +{ + int i; + const struct va1j5jf8007t_cb_map *map; + + for (i = 0; i < ARRAY_SIZE(va1j5jf8007t_cb_maps); i++) { + map = &va1j5jf8007t_cb_maps[i]; + if (frequency < map->frequency) + return map->cb; + } + return 0xe4; +} + +static int va1j5jf8007t_set_frequency(struct va1j5jf8007t_state *state) +{ + u32 frequency; + u16 word; + u8 buf[6]; + struct i2c_msg msg; + + frequency = state->fe.dtv_property_cache.frequency; + + word = (frequency + 71428) / 142857 + 399; + buf[0] = 0xfe; + buf[1] = 0xc2; + buf[2] = word >> 8; + buf[3] = word; + buf[4] = 0x80; + buf[5] = va1j5jf8007t_lookup_cb(frequency); + + msg.addr = state->config->demod_address; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(state->adap, &msg, 1) != 1) + return -EREMOTEIO; + + return 0; +} + +static int +va1j5jf8007t_check_frequency(struct va1j5jf8007t_state *state, int *lock) +{ + u8 addr; + u8 write_buf[2], read_buf[1]; + struct i2c_msg msgs[2]; + + addr = state->config->demod_address; + + write_buf[0] = 0xfe; + write_buf[1] = 0xc3; + + msgs[0].addr = addr; + msgs[0].flags = 0; + msgs[0].len = sizeof(write_buf); + msgs[0].buf = write_buf; + + msgs[1].addr = addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = sizeof(read_buf); + msgs[1].buf = read_buf; + + if (i2c_transfer(state->adap, msgs, 2) != 2) + return -EREMOTEIO; + + *lock = read_buf[0] & 0x40; + return 0; +} + +static int va1j5jf8007t_set_modulation(struct va1j5jf8007t_state *state) +{ + u8 buf[2]; + struct i2c_msg msg; + + buf[0] = 0x01; + buf[1] = 0x40; + + msg.addr = state->config->demod_address; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(state->adap, &msg, 1) != 1) + return -EREMOTEIO; + + return 0; +} + +static int va1j5jf8007t_check_modulation(struct va1j5jf8007t_state *state, + int *lock, int *retry) +{ + u8 addr; + u8 write_buf[1], read_buf[1]; + struct i2c_msg msgs[2]; + + addr = state->config->demod_address; + + write_buf[0] = 0x80; + + msgs[0].addr = addr; + msgs[0].flags = 0; + msgs[0].len = sizeof(write_buf); + msgs[0].buf = write_buf; + + msgs[1].addr = addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = sizeof(read_buf); + msgs[1].buf = read_buf; + + if (i2c_transfer(state->adap, msgs, 2) != 2) + return -EREMOTEIO; + + *lock = !(read_buf[0] & 0x10); + *retry = read_buf[0] & 0x80; + return 0; +} + +static int +va1j5jf8007t_tune(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params, + unsigned int mode_flags, unsigned int *delay, + fe_status_t *status) +{ + struct va1j5jf8007t_state *state; + int ret; + int lock, retry; + + state = fe->demodulator_priv; + + if (params != NULL) + state->tune_state = VA1J5JF8007T_SET_FREQUENCY; + + switch (state->tune_state) { + case VA1J5JF8007T_IDLE: + *delay = 3 * HZ; + *status = 0; + return 0; + + case VA1J5JF8007T_SET_FREQUENCY: + ret = va1j5jf8007t_set_frequency(state); + if (ret < 0) + return ret; + + state->tune_state = VA1J5JF8007T_CHECK_FREQUENCY; + *delay = 0; + *status = 0; + return 0; + + case VA1J5JF8007T_CHECK_FREQUENCY: + ret = va1j5jf8007t_check_frequency(state, &lock); + if (ret < 0) + return ret; + + if (!lock) { + *delay = (HZ + 999) / 1000; + *status = 0; + return 0; + } + + state->tune_state = VA1J5JF8007T_SET_MODULATION; + *delay = 0; + *status = FE_HAS_SIGNAL; + return 0; + + case VA1J5JF8007T_SET_MODULATION: + ret = va1j5jf8007t_set_modulation(state); + if (ret < 0) + return ret; + + state->tune_state = VA1J5JF8007T_CHECK_MODULATION; + *delay = 0; + *status = FE_HAS_SIGNAL; + return 0; + + case VA1J5JF8007T_CHECK_MODULATION: + ret = va1j5jf8007t_check_modulation(state, &lock, &retry); + if (ret < 0) + return ret; + + if (!lock) { + if (!retry) { + state->tune_state = VA1J5JF8007T_ABORT; + *delay = 3 * HZ; + *status = FE_HAS_SIGNAL; + return 0; + } + *delay = (HZ + 999) / 1000; + *status = FE_HAS_SIGNAL; + return 0; + } + + state->tune_state = VA1J5JF8007T_TRACK; + /* fall through */ + + case VA1J5JF8007T_TRACK: + *delay = 3 * HZ; + *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_LOCK; + return 0; + + case VA1J5JF8007T_ABORT: + *delay = 3 * HZ; + *status = FE_HAS_SIGNAL; + return 0; + } + + BUG(); +} + +static int va1j5jf8007t_init_frequency(struct va1j5jf8007t_state *state) +{ + u8 buf[7]; + struct i2c_msg msg; + + buf[0] = 0xfe; + buf[1] = 0xc2; + buf[2] = 0x01; + buf[3] = 0x8f; + buf[4] = 0xc1; + buf[5] = 0x80; + buf[6] = 0x80; + + msg.addr = state->config->demod_address; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(state->adap, &msg, 1) != 1) + return -EREMOTEIO; + + return 0; +} + +static int va1j5jf8007t_set_sleep(struct va1j5jf8007t_state *state, int sleep) +{ + u8 buf[2]; + struct i2c_msg msg; + + buf[0] = 0x03; + buf[1] = sleep ? 0x90 : 0x80; + + msg.addr = state->config->demod_address; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(state->adap, &msg, 1) != 1) + return -EREMOTEIO; + + return 0; +} + +static int va1j5jf8007t_sleep(struct dvb_frontend *fe) +{ + struct va1j5jf8007t_state *state; + int ret; + + state = fe->demodulator_priv; + + ret = va1j5jf8007t_init_frequency(state); + if (ret < 0) + return ret; + + return va1j5jf8007t_set_sleep(state, 1); +} + +static int va1j5jf8007t_init(struct dvb_frontend *fe) +{ + struct va1j5jf8007t_state *state; + + state = fe->demodulator_priv; + state->tune_state = VA1J5JF8007T_IDLE; + + return va1j5jf8007t_set_sleep(state, 0); +} + +static void va1j5jf8007t_release(struct dvb_frontend *fe) +{ + struct va1j5jf8007t_state *state; + state = fe->demodulator_priv; + kfree(state); +} + +static struct dvb_frontend_ops va1j5jf8007t_ops = { + .info = { + .name = "VA1J5JF8007 ISDB-T", + .type = FE_OFDM, + .frequency_min = 90000000, + .frequency_max = 770000000, + .frequency_stepsize = 142857, + .caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO | + FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO, + }, + + .get_frontend_algo = va1j5jf8007t_get_frontend_algo, + .read_status = va1j5jf8007t_read_status, + .tune = va1j5jf8007t_tune, + .sleep = va1j5jf8007t_sleep, + .init = va1j5jf8007t_init, + .release = va1j5jf8007t_release, +}; + +static const u8 va1j5jf8007t_prepare_bufs[][2] = { + {0x03, 0x90}, {0x14, 0x8f}, {0x1c, 0x2a}, {0x1d, 0xa8}, {0x1e, 0xa2}, + {0x22, 0x83}, {0x31, 0x0d}, {0x32, 0xe0}, {0x39, 0xd3}, {0x3a, 0x00}, + {0x5c, 0x40}, {0x5f, 0x80}, {0x75, 0x02}, {0x76, 0x4e}, {0x77, 0x03}, + {0xef, 0x01} +}; + +int va1j5jf8007t_prepare(struct dvb_frontend *fe) +{ + struct va1j5jf8007t_state *state; + u8 buf[2]; + struct i2c_msg msg; + int i; + + state = fe->demodulator_priv; + + msg.addr = state->config->demod_address; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + for (i = 0; i < ARRAY_SIZE(va1j5jf8007t_prepare_bufs); i++) { + memcpy(buf, va1j5jf8007t_prepare_bufs[i], sizeof(buf)); + if (i2c_transfer(state->adap, &msg, 1) != 1) + return -EREMOTEIO; + } + + return va1j5jf8007t_init_frequency(state); +} + +struct dvb_frontend * +va1j5jf8007t_attach(const struct va1j5jf8007t_config *config, + struct i2c_adapter *adap) +{ + struct va1j5jf8007t_state *state; + struct dvb_frontend *fe; + u8 buf[2]; + struct i2c_msg msg; + + state = kzalloc(sizeof(struct va1j5jf8007t_state), GFP_KERNEL); + if (!state) + return NULL; + + state->config = config; + state->adap = adap; + + fe = &state->fe; + memcpy(&fe->ops, &va1j5jf8007t_ops, sizeof(struct dvb_frontend_ops)); + fe->demodulator_priv = state; + + buf[0] = 0x01; + buf[1] = 0x80; + + msg.addr = state->config->demod_address; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(state->adap, &msg, 1) != 1) { + kfree(state); + return NULL; + } + + return fe; +} diff --git a/drivers/media/dvb/pt1/va1j5jf8007t.h b/drivers/media/dvb/pt1/va1j5jf8007t.h new file mode 100644 index 000000000000..ed49906f7769 --- /dev/null +++ b/drivers/media/dvb/pt1/va1j5jf8007t.h @@ -0,0 +1,40 @@ +/* + * ISDB-T driver for VA1J5JF8007 + * + * Copyright (C) 2009 HIRANO Takahito + * + * based on pt1dvr - http://pt1dvr.sourceforge.jp/ + * by Tomoaki Ishikawa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef VA1J5JF8007T_H +#define VA1J5JF8007T_H + +struct va1j5jf8007t_config { + u8 demod_address; +}; + +struct i2c_adapter; + +struct dvb_frontend * +va1j5jf8007t_attach(const struct va1j5jf8007t_config *config, + struct i2c_adapter *adap); + +/* must be called after va1j5jf8007s_attach */ +int va1j5jf8007t_prepare(struct dvb_frontend *fe); + +#endif diff --git a/drivers/media/radio/Kconfig b/drivers/media/radio/Kconfig index 25a36ad60c5e..a87a477c87f2 100644 --- a/drivers/media/radio/Kconfig +++ b/drivers/media/radio/Kconfig @@ -346,7 +346,7 @@ config RADIO_SI4713 ---help--- Say Y here if you want support to Si4713 FM Radio Transmitter. This device can transmit audio through FM. It can transmit - EDS and EBDS signals as well. This module is the v4l2 radio + RDS and RBDS signals as well. This module is the v4l2 radio interface for the i2c driver of this device. To compile this driver as a module, choose M here: the diff --git a/drivers/media/radio/radio-si4713.c b/drivers/media/radio/radio-si4713.c index 65c14b704586..170bbe554787 100644 --- a/drivers/media/radio/radio-si4713.c +++ b/drivers/media/radio/radio-si4713.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig index 1d758525d236..e6186b338a12 100644 --- a/drivers/media/video/Kconfig +++ b/drivers/media/video/Kconfig @@ -265,6 +265,15 @@ config VIDEO_SAA6588 comment "Video decoders" +config VIDEO_ADV7180 + tristate "Analog Devices ADV7180 decoder" + depends on VIDEO_V4L2 && I2C + ---help--- + Support for the Analog Devices ADV7180 video decoder. + + To compile this driver as a module, choose M here: the + module will be called adv7180. + config VIDEO_BT819 tristate "BT819A VideoStream decoder" depends on VIDEO_V4L2 && I2C @@ -493,6 +502,39 @@ config VIDEO_UPD64083 endmenu # encoder / decoder chips +config DISPLAY_DAVINCI_DM646X_EVM + tristate "DM646x EVM Video Display" + depends on VIDEO_DEV && MACH_DAVINCI_DM6467_EVM + select VIDEOBUF_DMA_CONTIG + select VIDEO_DAVINCI_VPIF + select VIDEO_ADV7343 + select VIDEO_THS7303 + help + Support for DM6467 based display device. + + To compile this driver as a module, choose M here: the + module will be called vpif_display. + +config CAPTURE_DAVINCI_DM646X_EVM + tristate "DM646x EVM Video Capture" + depends on VIDEO_DEV && MACH_DAVINCI_DM6467_EVM + select VIDEOBUF_DMA_CONTIG + select VIDEO_DAVINCI_VPIF + help + Support for DM6467 based capture device. + + To compile this driver as a module, choose M here: the + module will be called vpif_capture. + +config VIDEO_DAVINCI_VPIF + tristate "DaVinci VPIF Driver" + depends on DISPLAY_DAVINCI_DM646X_EVM + help + Support for DaVinci VPIF Driver. + + To compile this driver as a module, choose M here: the + module will be called vpif. + config VIDEO_VIVI tristate "Virtual Video Driver" depends on VIDEO_DEV && VIDEO_V4L2 && !SPARC32 && !SPARC64 @@ -505,6 +547,55 @@ config VIDEO_VIVI Say Y here if you want to test video apps or debug V4L devices. In doubt, say N. +config VIDEO_VPSS_SYSTEM + tristate "VPSS System module driver" + depends on ARCH_DAVINCI + help + Support for vpss system module for video driver + default y + +config VIDEO_VPFE_CAPTURE + tristate "VPFE Video Capture Driver" + depends on VIDEO_V4L2 && ARCH_DAVINCI + select VIDEOBUF_DMA_CONTIG + help + Support for DMXXXX VPFE based frame grabber. This is the + common V4L2 module for following DMXXX SoCs from Texas + Instruments:- DM6446 & DM355. + + To compile this driver as a module, choose M here: the + module will be called vpfe-capture. + +config VIDEO_DM6446_CCDC + tristate "DM6446 CCDC HW module" + depends on ARCH_DAVINCI_DM644x && VIDEO_VPFE_CAPTURE + select VIDEO_VPSS_SYSTEM + default y + help + Enables DaVinci CCD hw module. DaVinci CCDC hw interfaces + with decoder modules such as TVP5146 over BT656 or + sensor module such as MT9T001 over a raw interface. This + module configures the interface and CCDC/ISIF to do + video frame capture from slave decoders. + + To compile this driver as a module, choose M here: the + module will be called vpfe. + +config VIDEO_DM355_CCDC + tristate "DM355 CCDC HW module" + depends on ARCH_DAVINCI_DM355 && VIDEO_VPFE_CAPTURE + select VIDEO_VPSS_SYSTEM + default y + help + Enables DM355 CCD hw module. DM355 CCDC hw interfaces + with decoder modules such as TVP5146 over BT656 or + sensor module such as MT9T001 over a raw interface. This + module configures the interface and CCDC/ISIF to do + video frame capture from a slave decoders + + To compile this driver as a module, choose M here: the + module will be called vpfe. + source "drivers/media/video/bt8xx/Kconfig" config VIDEO_PMS @@ -690,6 +781,8 @@ source "drivers/media/video/ivtv/Kconfig" source "drivers/media/video/cx18/Kconfig" +source "drivers/media/video/saa7164/Kconfig" + config VIDEO_M32R_AR tristate "AR devices" depends on M32R && VIDEO_V4L1 diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile index 9f2e3214a482..e541932a789b 100644 --- a/drivers/media/video/Makefile +++ b/drivers/media/video/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_VIDEO_SAA7185) += saa7185.o obj-$(CONFIG_VIDEO_SAA7191) += saa7191.o obj-$(CONFIG_VIDEO_ADV7170) += adv7170.o obj-$(CONFIG_VIDEO_ADV7175) += adv7175.o +obj-$(CONFIG_VIDEO_ADV7180) += adv7180.o obj-$(CONFIG_VIDEO_ADV7343) += adv7343.o obj-$(CONFIG_VIDEO_VPX3220) += vpx3220.o obj-$(CONFIG_VIDEO_BT819) += bt819.o @@ -154,12 +155,17 @@ obj-$(CONFIG_VIDEO_MX3) += mx3_camera.o obj-$(CONFIG_VIDEO_PXA27x) += pxa_camera.o obj-$(CONFIG_VIDEO_SH_MOBILE_CEU) += sh_mobile_ceu_camera.o +obj-$(CONFIG_ARCH_DAVINCI) += davinci/ + obj-$(CONFIG_VIDEO_AU0828) += au0828/ obj-$(CONFIG_USB_VIDEO_CLASS) += uvc/ +obj-$(CONFIG_VIDEO_SAA7164) += saa7164/ obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o +obj-$(CONFIG_ARCH_DAVINCI) += davinci/ + EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core EXTRA_CFLAGS += -Idrivers/media/dvb/frontends EXTRA_CFLAGS += -Idrivers/media/common/tuners diff --git a/drivers/media/video/adv7180.c b/drivers/media/video/adv7180.c new file mode 100644 index 000000000000..1b3cbd02a7fd --- /dev/null +++ b/drivers/media/video/adv7180.c @@ -0,0 +1,202 @@ +/* + * adv7180.c Analog Devices ADV7180 video decoder driver + * Copyright (c) 2009 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "adv7180" + +#define ADV7180_INPUT_CONTROL_REG 0x00 +#define ADV7180_INPUT_CONTROL_PAL_BG_NTSC_J_SECAM 0x00 +#define ADV7180_AUTODETECT_ENABLE_REG 0x07 +#define ADV7180_AUTODETECT_DEFAULT 0x7f + + +#define ADV7180_STATUS1_REG 0x10 +#define ADV7180_STATUS1_AUTOD_MASK 0x70 +#define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00 +#define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10 +#define ADV7180_STATUS1_AUTOD_PAL_M 0x20 +#define ADV7180_STATUS1_AUTOD_PAL_60 0x30 +#define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40 +#define ADV7180_STATUS1_AUTOD_SECAM 0x50 +#define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60 +#define ADV7180_STATUS1_AUTOD_SECAM_525 0x70 + +#define ADV7180_IDENT_REG 0x11 +#define ADV7180_ID_7180 0x18 + + +struct adv7180_state { + struct v4l2_subdev sd; +}; + +static v4l2_std_id determine_norm(struct i2c_client *client) +{ + u8 status1 = i2c_smbus_read_byte_data(client, ADV7180_STATUS1_REG); + + switch (status1 & ADV7180_STATUS1_AUTOD_MASK) { + case ADV7180_STATUS1_AUTOD_NTSM_M_J: + return V4L2_STD_NTSC_M_JP; + case ADV7180_STATUS1_AUTOD_NTSC_4_43: + return V4L2_STD_NTSC_443; + case ADV7180_STATUS1_AUTOD_PAL_M: + return V4L2_STD_PAL_M; + case ADV7180_STATUS1_AUTOD_PAL_60: + return V4L2_STD_PAL_60; + case ADV7180_STATUS1_AUTOD_PAL_B_G: + return V4L2_STD_PAL; + case ADV7180_STATUS1_AUTOD_SECAM: + return V4L2_STD_SECAM; + case ADV7180_STATUS1_AUTOD_PAL_COMB: + return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N; + case ADV7180_STATUS1_AUTOD_SECAM_525: + return V4L2_STD_SECAM; + default: + return V4L2_STD_UNKNOWN; + } +} + +static inline struct adv7180_state *to_state(struct v4l2_subdev *sd) +{ + return container_of(sd, struct adv7180_state, sd); +} + +static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + + *std = determine_norm(client); + return 0; +} + +static int adv7180_g_chip_ident(struct v4l2_subdev *sd, + struct v4l2_dbg_chip_ident *chip) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + + return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_ADV7180, 0); +} + +static const struct v4l2_subdev_video_ops adv7180_video_ops = { + .querystd = adv7180_querystd, +}; + +static const struct v4l2_subdev_core_ops adv7180_core_ops = { + .g_chip_ident = adv7180_g_chip_ident, +}; + +static const struct v4l2_subdev_ops adv7180_ops = { + .core = &adv7180_core_ops, + .video = &adv7180_video_ops, +}; + +/* + * Generic i2c probe + * concerning the addresses: i2c wants 7 bit (without the r/w bit), so '>>1' + */ + +static int adv7180_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct adv7180_state *state; + struct v4l2_subdev *sd; + int ret; + + /* Check if the adapter supports the needed features */ + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) + return -EIO; + + v4l_info(client, "chip found @ 0x%02x (%s)\n", + client->addr << 1, client->adapter->name); + + state = kzalloc(sizeof(struct adv7180_state), GFP_KERNEL); + if (state == NULL) + return -ENOMEM; + sd = &state->sd; + v4l2_i2c_subdev_init(sd, client, &adv7180_ops); + + /* Initialize adv7180 */ + /* enable autodetection */ + ret = i2c_smbus_write_byte_data(client, ADV7180_INPUT_CONTROL_REG, + ADV7180_INPUT_CONTROL_PAL_BG_NTSC_J_SECAM); + if (ret > 0) + ret = i2c_smbus_write_byte_data(client, + ADV7180_AUTODETECT_ENABLE_REG, + ADV7180_AUTODETECT_DEFAULT); + if (ret < 0) { + printk(KERN_ERR DRIVER_NAME + ": Failed to communicate to chip: %d\n", ret); + return ret; + } + + return 0; +} + +static int adv7180_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + + v4l2_device_unregister_subdev(sd); + kfree(to_state(sd)); + return 0; +} + +static const struct i2c_device_id adv7180_id[] = { + {DRIVER_NAME, 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, adv7180_id); + +static struct i2c_driver adv7180_driver = { + .driver = { + .owner = THIS_MODULE, + .name = DRIVER_NAME, + }, + .probe = adv7180_probe, + .remove = adv7180_remove, + .id_table = adv7180_id, +}; + +static __init int adv7180_init(void) +{ + return i2c_add_driver(&adv7180_driver); +} + +static __exit void adv7180_exit(void) +{ + i2c_del_driver(&adv7180_driver); +} + +module_init(adv7180_init); +module_exit(adv7180_exit); + +MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver"); +MODULE_AUTHOR("Mocean Laboratories"); +MODULE_LICENSE("GPL v2"); + diff --git a/drivers/media/video/adv7343.c b/drivers/media/video/adv7343.c index 30f5caf5dda5..df26f2fe44eb 100644 --- a/drivers/media/video/adv7343.c +++ b/drivers/media/video/adv7343.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include diff --git a/drivers/media/video/au0828/au0828-cards.c b/drivers/media/video/au0828/au0828-cards.c index 830c4a933f63..57dd9195daf5 100644 --- a/drivers/media/video/au0828/au0828-cards.c +++ b/drivers/media/video/au0828/au0828-cards.c @@ -212,7 +212,7 @@ void au0828_card_setup(struct au0828_dev *dev) be abstracted out if we ever need to support a different demod) */ sd = v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, - "au8522", "au8522", 0x8e >> 1); + "au8522", "au8522", 0x8e >> 1, NULL); if (sd == NULL) printk(KERN_ERR "analog subdev registration failed\n"); } @@ -221,7 +221,7 @@ void au0828_card_setup(struct au0828_dev *dev) if (dev->board.tuner_type != TUNER_ABSENT) { /* Load the tuner module, which does the attach */ sd = v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, - "tuner", "tuner", dev->board.tuner_addr); + "tuner", "tuner", dev->board.tuner_addr, NULL); if (sd == NULL) printk(KERN_ERR "tuner subdev registration fail\n"); diff --git a/drivers/media/video/bt8xx/bttv-cards.c b/drivers/media/video/bt8xx/bttv-cards.c index b42251fa96ba..12279f6d9bc4 100644 --- a/drivers/media/video/bt8xx/bttv-cards.c +++ b/drivers/media/video/bt8xx/bttv-cards.c @@ -3524,8 +3524,8 @@ void __devinit bttv_init_card2(struct bttv *btv) }; struct v4l2_subdev *sd; - sd = v4l2_i2c_new_probed_subdev(&btv->c.v4l2_dev, - &btv->c.i2c_adap, "saa6588", "saa6588", addrs); + sd = v4l2_i2c_new_subdev(&btv->c.v4l2_dev, + &btv->c.i2c_adap, "saa6588", "saa6588", 0, addrs); btv->has_saa6588 = (sd != NULL); } @@ -3549,8 +3549,8 @@ void __devinit bttv_init_card2(struct bttv *btv) I2C_CLIENT_END }; - btv->sd_msp34xx = v4l2_i2c_new_probed_subdev(&btv->c.v4l2_dev, - &btv->c.i2c_adap, "msp3400", "msp3400", addrs); + btv->sd_msp34xx = v4l2_i2c_new_subdev(&btv->c.v4l2_dev, + &btv->c.i2c_adap, "msp3400", "msp3400", 0, addrs); if (btv->sd_msp34xx) return; goto no_audio; @@ -3563,16 +3563,16 @@ void __devinit bttv_init_card2(struct bttv *btv) I2C_CLIENT_END }; - if (v4l2_i2c_new_probed_subdev(&btv->c.v4l2_dev, - &btv->c.i2c_adap, "tda7432", "tda7432", addrs)) + if (v4l2_i2c_new_subdev(&btv->c.v4l2_dev, + &btv->c.i2c_adap, "tda7432", "tda7432", 0, addrs)) return; goto no_audio; } case 3: { /* The user specified that we should probe for tvaudio */ - btv->sd_tvaudio = v4l2_i2c_new_probed_subdev(&btv->c.v4l2_dev, - &btv->c.i2c_adap, "tvaudio", "tvaudio", tvaudio_addrs()); + btv->sd_tvaudio = v4l2_i2c_new_subdev(&btv->c.v4l2_dev, + &btv->c.i2c_adap, "tvaudio", "tvaudio", 0, tvaudio_addrs()); if (btv->sd_tvaudio) return; goto no_audio; @@ -3591,13 +3591,13 @@ void __devinit bttv_init_card2(struct bttv *btv) it really is a msp3400, so it will return NULL when the device found is really something else (e.g. a tea6300). */ if (!bttv_tvcards[btv->c.type].no_msp34xx) { - btv->sd_msp34xx = v4l2_i2c_new_probed_subdev_addr(&btv->c.v4l2_dev, + btv->sd_msp34xx = v4l2_i2c_new_subdev(&btv->c.v4l2_dev, &btv->c.i2c_adap, "msp3400", "msp3400", - I2C_ADDR_MSP3400 >> 1); + 0, I2C_ADDRS(I2C_ADDR_MSP3400 >> 1)); } else if (bttv_tvcards[btv->c.type].msp34xx_alt) { - btv->sd_msp34xx = v4l2_i2c_new_probed_subdev_addr(&btv->c.v4l2_dev, + btv->sd_msp34xx = v4l2_i2c_new_subdev(&btv->c.v4l2_dev, &btv->c.i2c_adap, "msp3400", "msp3400", - I2C_ADDR_MSP3400_ALT >> 1); + 0, I2C_ADDRS(I2C_ADDR_MSP3400_ALT >> 1)); } /* If we found a msp34xx, then we're done. */ @@ -3611,14 +3611,14 @@ void __devinit bttv_init_card2(struct bttv *btv) I2C_CLIENT_END }; - if (v4l2_i2c_new_probed_subdev(&btv->c.v4l2_dev, - &btv->c.i2c_adap, "tda7432", "tda7432", addrs)) + if (v4l2_i2c_new_subdev(&btv->c.v4l2_dev, + &btv->c.i2c_adap, "tda7432", "tda7432", 0, addrs)) return; } /* Now see if we can find one of the tvaudio devices. */ - btv->sd_tvaudio = v4l2_i2c_new_probed_subdev(&btv->c.v4l2_dev, - &btv->c.i2c_adap, "tvaudio", "tvaudio", tvaudio_addrs()); + btv->sd_tvaudio = v4l2_i2c_new_subdev(&btv->c.v4l2_dev, + &btv->c.i2c_adap, "tvaudio", "tvaudio", 0, tvaudio_addrs()); if (btv->sd_tvaudio) return; @@ -3641,15 +3641,15 @@ void __devinit bttv_init_tuner(struct bttv *btv) /* Load tuner module before issuing tuner config call! */ if (bttv_tvcards[btv->c.type].has_radio) - v4l2_i2c_new_probed_subdev(&btv->c.v4l2_dev, + v4l2_i2c_new_subdev(&btv->c.v4l2_dev, &btv->c.i2c_adap, "tuner", "tuner", - v4l2_i2c_tuner_addrs(ADDRS_RADIO)); - v4l2_i2c_new_probed_subdev(&btv->c.v4l2_dev, + 0, v4l2_i2c_tuner_addrs(ADDRS_RADIO)); + v4l2_i2c_new_subdev(&btv->c.v4l2_dev, &btv->c.i2c_adap, "tuner", "tuner", - v4l2_i2c_tuner_addrs(ADDRS_DEMOD)); - v4l2_i2c_new_probed_subdev(&btv->c.v4l2_dev, + 0, v4l2_i2c_tuner_addrs(ADDRS_DEMOD)); + v4l2_i2c_new_subdev(&btv->c.v4l2_dev, &btv->c.i2c_adap, "tuner", "tuner", - v4l2_i2c_tuner_addrs(ADDRS_TV_WITH_DEMOD)); + 0, v4l2_i2c_tuner_addrs(ADDRS_TV_WITH_DEMOD)); tun_setup.mode_mask = T_ANALOG_TV | T_DIGITAL_TV; tun_setup.type = btv->tuner_type; diff --git a/drivers/media/video/cafe_ccic.c b/drivers/media/video/cafe_ccic.c index 9c149a781294..657c481d255c 100644 --- a/drivers/media/video/cafe_ccic.c +++ b/drivers/media/video/cafe_ccic.c @@ -1955,7 +1955,7 @@ static int cafe_pci_probe(struct pci_dev *pdev, cam->sensor_addr = 0x42; cam->sensor = v4l2_i2c_new_subdev(&cam->v4l2_dev, &cam->i2c_adapter, - "ov7670", "ov7670", cam->sensor_addr); + "ov7670", "ov7670", cam->sensor_addr, NULL); if (cam->sensor == NULL) { ret = -ENODEV; goto out_smbus; diff --git a/drivers/media/video/cx18/cx18-driver.c b/drivers/media/video/cx18/cx18-driver.c index dd0224f328ad..6dd51e27582c 100644 --- a/drivers/media/video/cx18/cx18-driver.c +++ b/drivers/media/video/cx18/cx18-driver.c @@ -231,7 +231,7 @@ MODULE_PARM_DESC(enc_pcm_bufs, "Number of encoder PCM buffers\n" "\t\t\tDefault is computed from other enc_pcm_* parameters"); -MODULE_PARM_DESC(cx18_first_minor, "Set kernel number assigned to first card"); +MODULE_PARM_DESC(cx18_first_minor, "Set device node number assigned to first card"); MODULE_AUTHOR("Hans Verkuil"); MODULE_DESCRIPTION("CX23418 driver"); diff --git a/drivers/media/video/cx18/cx18-i2c.c b/drivers/media/video/cx18/cx18-i2c.c index da395fef50df..2477461e84d7 100644 --- a/drivers/media/video/cx18/cx18-i2c.c +++ b/drivers/media/video/cx18/cx18-i2c.c @@ -116,7 +116,7 @@ static int cx18_i2c_new_ir(struct i2c_adapter *adap, u32 hw, const char *type, /* Our default information for ir-kbd-i2c.c to use */ switch (hw) { case CX18_HW_Z8F0811_IR_RX_HAUP: - info.platform_data = &z8f0811_ir_init_data; + info.platform_data = (void *) &z8f0811_ir_init_data; break; default: break; @@ -139,16 +139,16 @@ int cx18_i2c_register(struct cx18 *cx, unsigned idx) if (hw == CX18_HW_TUNER) { /* special tuner group handling */ - sd = v4l2_i2c_new_probed_subdev(&cx->v4l2_dev, - adap, mod, type, cx->card_i2c->radio); + sd = v4l2_i2c_new_subdev(&cx->v4l2_dev, + adap, mod, type, 0, cx->card_i2c->radio); if (sd != NULL) sd->grp_id = hw; - sd = v4l2_i2c_new_probed_subdev(&cx->v4l2_dev, - adap, mod, type, cx->card_i2c->demod); + sd = v4l2_i2c_new_subdev(&cx->v4l2_dev, + adap, mod, type, 0, cx->card_i2c->demod); if (sd != NULL) sd->grp_id = hw; - sd = v4l2_i2c_new_probed_subdev(&cx->v4l2_dev, - adap, mod, type, cx->card_i2c->tv); + sd = v4l2_i2c_new_subdev(&cx->v4l2_dev, + adap, mod, type, 0, cx->card_i2c->tv); if (sd != NULL) sd->grp_id = hw; return sd != NULL ? 0 : -1; @@ -162,7 +162,7 @@ int cx18_i2c_register(struct cx18 *cx, unsigned idx) return -1; /* It's an I2C device other than an analog tuner or IR chip */ - sd = v4l2_i2c_new_subdev(&cx->v4l2_dev, adap, mod, type, hw_addrs[idx]); + sd = v4l2_i2c_new_subdev(&cx->v4l2_dev, adap, mod, type, hw_addrs[idx], NULL); if (sd != NULL) sd->grp_id = hw; return sd != NULL ? 0 : -1; diff --git a/drivers/media/video/cx18/cx18-streams.c b/drivers/media/video/cx18/cx18-streams.c index 54d248e16d85..7df513a2dba8 100644 --- a/drivers/media/video/cx18/cx18-streams.c +++ b/drivers/media/video/cx18/cx18-streams.c @@ -245,9 +245,9 @@ static int cx18_reg_dev(struct cx18 *cx, int type) video_set_drvdata(s->video_dev, s); /* Register device. First try the desired minor, then any free one. */ - ret = video_register_device(s->video_dev, vfl_type, num); + ret = video_register_device_no_warn(s->video_dev, vfl_type, num); if (ret < 0) { - CX18_ERR("Couldn't register v4l2 device for %s kernel number %d\n", + CX18_ERR("Couldn't register v4l2 device for %s (device node number %d)\n", s->name, num); video_device_release(s->video_dev); s->video_dev = NULL; diff --git a/drivers/media/video/cx231xx/cx231xx-cards.c b/drivers/media/video/cx231xx/cx231xx-cards.c index 63d2239fd324..319c459459e0 100644 --- a/drivers/media/video/cx231xx/cx231xx-cards.c +++ b/drivers/media/video/cx231xx/cx231xx-cards.c @@ -313,7 +313,7 @@ void cx231xx_card_setup(struct cx231xx *dev) if (dev->board.decoder == CX231XX_AVDECODER) { dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_bus[0].i2c_adap, - "cx25840", "cx25840", 0x88 >> 1); + "cx25840", "cx25840", 0x88 >> 1, NULL); if (dev->sd_cx25840 == NULL) cx231xx_info("cx25840 subdev registration failure\n"); cx25840_call(dev, core, load_fw); @@ -323,7 +323,7 @@ void cx231xx_card_setup(struct cx231xx *dev) if (dev->board.tuner_type != TUNER_ABSENT) { dev->sd_tuner = v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_bus[1].i2c_adap, - "tuner", "tuner", 0xc2 >> 1); + "tuner", "tuner", 0xc2 >> 1, NULL); if (dev->sd_tuner == NULL) cx231xx_info("tuner subdev registration failure\n"); diff --git a/drivers/media/video/cx23885/cimax2.c b/drivers/media/video/cx23885/cimax2.c index 0316257b7345..c04222ffb286 100644 --- a/drivers/media/video/cx23885/cimax2.c +++ b/drivers/media/video/cx23885/cimax2.c @@ -75,7 +75,6 @@ struct netup_ci_state { void *priv; }; -struct mutex gpio_mutex;/* Two CiMax's uses same GPIO lines */ int netup_read_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg, u8 *buf, int len) @@ -183,10 +182,11 @@ int netup_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot, if (ret != 0) return ret; - mutex_lock(&gpio_mutex); + mutex_lock(&dev->gpio_lock); /* write addr */ cx_write(MC417_OEN, NETUP_EN_ALL); + msleep(2); cx_write(MC417_RWD, NETUP_CTRL_OFF | NETUP_ADLO | (0xff & addr)); cx_clear(MC417_RWD, NETUP_ADLO); @@ -194,9 +194,10 @@ int netup_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot, NETUP_ADHI | (0xff & (addr >> 8))); cx_clear(MC417_RWD, NETUP_ADHI); - if (read) /* data in */ + if (read) { /* data in */ cx_write(MC417_OEN, NETUP_EN_ALL | NETUP_DATA); - else /* data out */ + msleep(2); + } else /* data out */ cx_write(MC417_RWD, NETUP_CTRL_OFF | data); /* choose chip */ @@ -206,7 +207,7 @@ int netup_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot, cx_clear(MC417_RWD, (read) ? NETUP_RD : NETUP_WR); mem = netup_ci_get_mem(dev); - mutex_unlock(&gpio_mutex); + mutex_unlock(&dev->gpio_lock); if (!read) if (mem < 0) @@ -403,7 +404,6 @@ int netup_ci_init(struct cx23885_tsport *port) switch (port->nr) { case 1: state->ci_i2c_addr = 0x40; - mutex_init(&gpio_mutex); break; case 2: state->ci_i2c_addr = 0x41; diff --git a/drivers/media/video/cx23885/cx23885-cards.c b/drivers/media/video/cx23885/cx23885-cards.c index 3143d85ef31d..bfdf79f1033c 100644 --- a/drivers/media/video/cx23885/cx23885-cards.c +++ b/drivers/media/video/cx23885/cx23885-cards.c @@ -210,6 +210,10 @@ struct cx23885_board cx23885_boards[] = { .portb = CX23885_MPEG_ENCODER, .portc = CX23885_MPEG_DVB, }, + [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = { + .name = "Compro VideoMate E800", + .portc = CX23885_MPEG_DVB, + }, }; const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards); @@ -341,6 +345,10 @@ struct cx23885_subid cx23885_subids[] = { .subvendor = 0x0070, .subdevice = 0x8541, .card = CX23885_BOARD_HAUPPAUGE_HVR1850, + }, { + .subvendor = 0x1858, + .subdevice = 0xe800, + .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800, }, }; const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids); @@ -536,6 +544,7 @@ int cx23885_tuner_callback(void *priv, int component, int command, int arg) case CX23885_BOARD_HAUPPAUGE_HVR1500Q: case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: + case CX23885_BOARD_COMPRO_VIDEOMATE_E800: /* Tuner Reset Command */ bitmask = 0x04; break; @@ -687,6 +696,7 @@ void cx23885_gpio_setup(struct cx23885_dev *dev) break; case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: + case CX23885_BOARD_COMPRO_VIDEOMATE_E800: /* GPIO-2 xc3028 tuner reset */ /* The following GPIO's are on the internal AVCore (cx25840) */ @@ -911,6 +921,7 @@ void cx23885_card_setup(struct cx23885_dev *dev) case CX23885_BOARD_HAUPPAUGE_HVR1255: case CX23885_BOARD_HAUPPAUGE_HVR1210: case CX23885_BOARD_HAUPPAUGE_HVR1850: + case CX23885_BOARD_COMPRO_VIDEOMATE_E800: default: ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ @@ -927,9 +938,10 @@ void cx23885_card_setup(struct cx23885_dev *dev) case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: + case CX23885_BOARD_COMPRO_VIDEOMATE_E800: dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_bus[2].i2c_adap, - "cx25840", "cx25840", 0x88 >> 1); + "cx25840", "cx25840", 0x88 >> 1, NULL); v4l2_subdev_call(dev->sd_cx25840, core, load_fw); break; } diff --git a/drivers/media/video/cx23885/cx23885-core.c b/drivers/media/video/cx23885/cx23885-core.c index 40d438d7234d..c31284ba19dd 100644 --- a/drivers/media/video/cx23885/cx23885-core.c +++ b/drivers/media/video/cx23885/cx23885-core.c @@ -758,6 +758,7 @@ static int cx23885_dev_setup(struct cx23885_dev *dev) int i; mutex_init(&dev->lock); + mutex_init(&dev->gpio_lock); atomic_inc(&dev->refcount); diff --git a/drivers/media/video/cx23885/cx23885-dvb.c b/drivers/media/video/cx23885/cx23885-dvb.c index 022fad798fc2..45e13ee66dc7 100644 --- a/drivers/media/video/cx23885/cx23885-dvb.c +++ b/drivers/media/video/cx23885/cx23885-dvb.c @@ -255,15 +255,18 @@ static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = { static struct tda18271_config hauppauge_tda18271_config = { .std_map = &hauppauge_tda18271_std_map, .gate = TDA18271_GATE_ANALOG, + .output_opt = TDA18271_OUTPUT_LT_OFF, }; static struct tda18271_config hauppauge_hvr1200_tuner_config = { .std_map = &hauppauge_hvr1200_tda18271_std_map, .gate = TDA18271_GATE_ANALOG, + .output_opt = TDA18271_OUTPUT_LT_OFF, }; static struct tda18271_config hauppauge_hvr1210_tuner_config = { .gate = TDA18271_GATE_DIGITAL, + .output_opt = TDA18271_OUTPUT_LT_OFF, }; static struct tda18271_std_map hauppauge_hvr127x_std_map = { @@ -275,6 +278,7 @@ static struct tda18271_std_map hauppauge_hvr127x_std_map = { static struct tda18271_config hauppauge_hvr127x_config = { .std_map = &hauppauge_hvr127x_std_map, + .output_opt = TDA18271_OUTPUT_LT_OFF, }; static struct lgdt3305_config hauppauge_lgdt3305_config = { @@ -743,6 +747,7 @@ static int dvb_register(struct cx23885_tsport *port) } case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: + case CX23885_BOARD_COMPRO_VIDEOMATE_E800: i2c_bus = &dev->i2c_bus[0]; fe0->dvb.frontend = dvb_attach(zl10353_attach, diff --git a/drivers/media/video/cx23885/cx23885-video.c b/drivers/media/video/cx23885/cx23885-video.c index 5d6093336300..654cc253cd50 100644 --- a/drivers/media/video/cx23885/cx23885-video.c +++ b/drivers/media/video/cx23885/cx23885-video.c @@ -1521,11 +1521,11 @@ int cx23885_video_register(struct cx23885_dev *dev) if (dev->tuner_addr) sd = v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_bus[1].i2c_adap, - "tuner", "tuner", dev->tuner_addr); + "tuner", "tuner", dev->tuner_addr, NULL); else - sd = v4l2_i2c_new_probed_subdev(&dev->v4l2_dev, + sd = v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_bus[1].i2c_adap, - "tuner", "tuner", v4l2_i2c_tuner_addrs(ADDRS_TV)); + "tuner", "tuner", 0, v4l2_i2c_tuner_addrs(ADDRS_TV)); if (sd) { struct tuner_setup tun_setup; diff --git a/drivers/media/video/cx23885/cx23885.h b/drivers/media/video/cx23885/cx23885.h index 86f26947bb78..cc7a165561ff 100644 --- a/drivers/media/video/cx23885/cx23885.h +++ b/drivers/media/video/cx23885/cx23885.h @@ -78,6 +78,7 @@ #define CX23885_BOARD_MYGICA_X8506 22 #define CX23885_BOARD_MAGICPRO_PROHDTVE2 23 #define CX23885_BOARD_HAUPPAUGE_HVR1850 24 +#define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25 #define GPIO_0 0x00000001 #define GPIO_1 0x00000002 @@ -325,6 +326,7 @@ struct cx23885_dev { int nr; struct mutex lock; + struct mutex gpio_lock; /* board details */ unsigned int board; diff --git a/drivers/media/video/cx23885/netup-eeprom.c b/drivers/media/video/cx23885/netup-eeprom.c index 042bbbbd48f8..98a48f500684 100644 --- a/drivers/media/video/cx23885/netup-eeprom.c +++ b/drivers/media/video/cx23885/netup-eeprom.c @@ -97,11 +97,11 @@ void netup_get_card_info(struct i2c_adapter *i2c_adap, { int i, j; - cinfo->rev = netup_eeprom_read(i2c_adap, 13); + cinfo->rev = netup_eeprom_read(i2c_adap, 63); - for (i = 0, j = 0; i < 6; i++, j++) + for (i = 64, j = 0; i < 70; i++, j++) cinfo->port[0].mac[j] = netup_eeprom_read(i2c_adap, i); - for (i = 6, j = 0; i < 12; i++, j++) + for (i = 70, j = 0; i < 76; i++, j++) cinfo->port[1].mac[j] = netup_eeprom_read(i2c_adap, i); }; diff --git a/drivers/media/video/cx88/cx88-cards.c b/drivers/media/video/cx88/cx88-cards.c index e5f07fbd5a35..33be6369871a 100644 --- a/drivers/media/video/cx88/cx88-cards.c +++ b/drivers/media/video/cx88/cx88-cards.c @@ -3439,20 +3439,20 @@ struct cx88_core *cx88_core_create(struct pci_dev *pci, int nr) The radio_type is sometimes missing, or set to UNSET but later code configures a tea5767. */ - v4l2_i2c_new_probed_subdev(&core->v4l2_dev, &core->i2c_adap, + v4l2_i2c_new_subdev(&core->v4l2_dev, &core->i2c_adap, "tuner", "tuner", - v4l2_i2c_tuner_addrs(ADDRS_RADIO)); + 0, v4l2_i2c_tuner_addrs(ADDRS_RADIO)); if (has_demod) - v4l2_i2c_new_probed_subdev(&core->v4l2_dev, + v4l2_i2c_new_subdev(&core->v4l2_dev, &core->i2c_adap, "tuner", "tuner", - v4l2_i2c_tuner_addrs(ADDRS_DEMOD)); + 0, v4l2_i2c_tuner_addrs(ADDRS_DEMOD)); if (core->board.tuner_addr == ADDR_UNSET) { - v4l2_i2c_new_probed_subdev(&core->v4l2_dev, + v4l2_i2c_new_subdev(&core->v4l2_dev, &core->i2c_adap, "tuner", "tuner", - has_demod ? tv_addrs + 4 : tv_addrs); + 0, has_demod ? tv_addrs + 4 : tv_addrs); } else { v4l2_i2c_new_subdev(&core->v4l2_dev, &core->i2c_adap, - "tuner", "tuner", core->board.tuner_addr); + "tuner", "tuner", core->board.tuner_addr, NULL); } } diff --git a/drivers/media/video/cx88/cx88-video.c b/drivers/media/video/cx88/cx88-video.c index 2bb54c3ef5cd..81d2b5dea18e 100644 --- a/drivers/media/video/cx88/cx88-video.c +++ b/drivers/media/video/cx88/cx88-video.c @@ -1881,14 +1881,14 @@ static int __devinit cx8800_initdev(struct pci_dev *pci_dev, if (core->board.audio_chip == V4L2_IDENT_WM8775) v4l2_i2c_new_subdev(&core->v4l2_dev, &core->i2c_adap, - "wm8775", "wm8775", 0x36 >> 1); + "wm8775", "wm8775", 0x36 >> 1, NULL); if (core->board.audio_chip == V4L2_IDENT_TVAUDIO) { /* This probes for a tda9874 as is used on some Pixelview Ultra boards. */ - v4l2_i2c_new_probed_subdev_addr(&core->v4l2_dev, + v4l2_i2c_new_subdev(&core->v4l2_dev, &core->i2c_adap, - "tvaudio", "tvaudio", 0xb0 >> 1); + "tvaudio", "tvaudio", 0, I2C_ADDRS(0xb0 >> 1)); } switch (core->boardnr) { diff --git a/drivers/media/video/dabusb.c b/drivers/media/video/dabusb.c index 0664d111085f..ee43876adb06 100644 --- a/drivers/media/video/dabusb.c +++ b/drivers/media/video/dabusb.c @@ -748,14 +748,14 @@ static const struct file_operations dabusb_fops = .release = dabusb_release, }; -static char *dabusb_nodename(struct device *dev) +static char *dabusb_devnode(struct device *dev, mode_t *mode) { return kasprintf(GFP_KERNEL, "usb/%s", dev_name(dev)); } static struct usb_class_driver dabusb_class = { .name = "dabusb%d", - .nodename = dabusb_nodename, + .devnode = dabusb_devnode, .fops = &dabusb_fops, .minor_base = DABUSB_MINOR, }; diff --git a/drivers/media/video/davinci/Makefile b/drivers/media/video/davinci/Makefile new file mode 100644 index 000000000000..1a8b8f3f182e --- /dev/null +++ b/drivers/media/video/davinci/Makefile @@ -0,0 +1,17 @@ +# +# Makefile for the davinci video device drivers. +# + +# VPIF +obj-$(CONFIG_VIDEO_DAVINCI_VPIF) += vpif.o + +#DM646x EVM Display driver +obj-$(CONFIG_DISPLAY_DAVINCI_DM646X_EVM) += vpif_display.o +#DM646x EVM Capture driver +obj-$(CONFIG_CAPTURE_DAVINCI_DM646X_EVM) += vpif_capture.o + +# Capture: DM6446 and DM355 +obj-$(CONFIG_VIDEO_VPSS_SYSTEM) += vpss.o +obj-$(CONFIG_VIDEO_VPFE_CAPTURE) += vpfe_capture.o +obj-$(CONFIG_VIDEO_DM6446_CCDC) += dm644x_ccdc.o +obj-$(CONFIG_VIDEO_DM355_CCDC) += dm355_ccdc.o diff --git a/drivers/media/video/davinci/ccdc_hw_device.h b/drivers/media/video/davinci/ccdc_hw_device.h new file mode 100644 index 000000000000..86b9b3518965 --- /dev/null +++ b/drivers/media/video/davinci/ccdc_hw_device.h @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2008-2009 Texas Instruments Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * ccdc device API + */ +#ifndef _CCDC_HW_DEVICE_H +#define _CCDC_HW_DEVICE_H + +#ifdef __KERNEL__ +#include +#include +#include +#include + +/* + * ccdc hw operations + */ +struct ccdc_hw_ops { + /* Pointer to initialize function to initialize ccdc device */ + int (*open) (struct device *dev); + /* Pointer to deinitialize function */ + int (*close) (struct device *dev); + /* set ccdc base address */ + void (*set_ccdc_base)(void *base, int size); + /* Pointer to function to enable or disable ccdc */ + void (*enable) (int en); + /* reset sbl. only for 6446 */ + void (*reset) (void); + /* enable output to sdram */ + void (*enable_out_to_sdram) (int en); + /* Pointer to function to set hw parameters */ + int (*set_hw_if_params) (struct vpfe_hw_if_param *param); + /* get interface parameters */ + int (*get_hw_if_params) (struct vpfe_hw_if_param *param); + /* + * Pointer to function to set parameters. Used + * for implementing VPFE_S_CCDC_PARAMS + */ + int (*set_params) (void *params); + /* + * Pointer to function to get parameter. Used + * for implementing VPFE_G_CCDC_PARAMS + */ + int (*get_params) (void *params); + /* Pointer to function to configure ccdc */ + int (*configure) (void); + + /* Pointer to function to set buffer type */ + int (*set_buftype) (enum ccdc_buftype buf_type); + /* Pointer to function to get buffer type */ + enum ccdc_buftype (*get_buftype) (void); + /* Pointer to function to set frame format */ + int (*set_frame_format) (enum ccdc_frmfmt frm_fmt); + /* Pointer to function to get frame format */ + enum ccdc_frmfmt (*get_frame_format) (void); + /* enumerate hw pix formats */ + int (*enum_pix)(u32 *hw_pix, int i); + /* Pointer to function to set buffer type */ + u32 (*get_pixel_format) (void); + /* Pointer to function to get pixel format. */ + int (*set_pixel_format) (u32 pixfmt); + /* Pointer to function to set image window */ + int (*set_image_window) (struct v4l2_rect *win); + /* Pointer to function to set image window */ + void (*get_image_window) (struct v4l2_rect *win); + /* Pointer to function to get line length */ + unsigned int (*get_line_length) (void); + + /* Query CCDC control IDs */ + int (*queryctrl)(struct v4l2_queryctrl *qctrl); + /* Set CCDC control */ + int (*set_control)(struct v4l2_control *ctrl); + /* Get CCDC control */ + int (*get_control)(struct v4l2_control *ctrl); + + /* Pointer to function to set frame buffer address */ + void (*setfbaddr) (unsigned long addr); + /* Pointer to function to get field id */ + int (*getfid) (void); +}; + +struct ccdc_hw_device { + /* ccdc device name */ + char name[32]; + /* module owner */ + struct module *owner; + /* hw ops */ + struct ccdc_hw_ops hw_ops; +}; + +/* Used by CCDC module to register & unregister with vpfe capture driver */ +int vpfe_register_ccdc_device(struct ccdc_hw_device *dev); +void vpfe_unregister_ccdc_device(struct ccdc_hw_device *dev); + +#endif +#endif diff --git a/drivers/media/video/davinci/dm355_ccdc.c b/drivers/media/video/davinci/dm355_ccdc.c new file mode 100644 index 000000000000..4629cabe3f28 --- /dev/null +++ b/drivers/media/video/davinci/dm355_ccdc.c @@ -0,0 +1,978 @@ +/* + * Copyright (C) 2005-2009 Texas Instruments Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * CCDC hardware module for DM355 + * ------------------------------ + * + * This module is for configuring DM355 CCD controller of VPFE to capture + * Raw yuv or Bayer RGB data from a decoder. CCDC has several modules + * such as Defect Pixel Correction, Color Space Conversion etc to + * pre-process the Bayer RGB data, before writing it to SDRAM. This + * module also allows application to configure individual + * module parameters through VPFE_CMD_S_CCDC_RAW_PARAMS IOCTL. + * To do so, application include dm355_ccdc.h and vpfe_capture.h header + * files. The setparams() API is called by vpfe_capture driver + * to configure module parameters + * + * TODO: 1) Raw bayer parameter settings and bayer capture + * 2) Split module parameter structure to module specific ioctl structs + * 3) add support for lense shading correction + * 4) investigate if enum used for user space type definition + * to be replaced by #defines or integer + */ +#include +#include +#include +#include +#include +#include "dm355_ccdc_regs.h" +#include "ccdc_hw_device.h" + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("CCDC Driver for DM355"); +MODULE_AUTHOR("Texas Instruments"); + +static struct device *dev; + +/* Object for CCDC raw mode */ +static struct ccdc_params_raw ccdc_hw_params_raw = { + .pix_fmt = CCDC_PIXFMT_RAW, + .frm_fmt = CCDC_FRMFMT_PROGRESSIVE, + .win = CCDC_WIN_VGA, + .fid_pol = VPFE_PINPOL_POSITIVE, + .vd_pol = VPFE_PINPOL_POSITIVE, + .hd_pol = VPFE_PINPOL_POSITIVE, + .gain = { + .r_ye = 256, + .gb_g = 256, + .gr_cy = 256, + .b_mg = 256 + }, + .config_params = { + .datasft = 2, + .data_sz = CCDC_DATA_10BITS, + .mfilt1 = CCDC_NO_MEDIAN_FILTER1, + .mfilt2 = CCDC_NO_MEDIAN_FILTER2, + .alaw = { + .gama_wd = 2, + }, + .blk_clamp = { + .sample_pixel = 1, + .dc_sub = 25 + }, + .col_pat_field0 = { + .olop = CCDC_GREEN_BLUE, + .olep = CCDC_BLUE, + .elop = CCDC_RED, + .elep = CCDC_GREEN_RED + }, + .col_pat_field1 = { + .olop = CCDC_GREEN_BLUE, + .olep = CCDC_BLUE, + .elop = CCDC_RED, + .elep = CCDC_GREEN_RED + }, + }, +}; + + +/* Object for CCDC ycbcr mode */ +static struct ccdc_params_ycbcr ccdc_hw_params_ycbcr = { + .win = CCDC_WIN_PAL, + .pix_fmt = CCDC_PIXFMT_YCBCR_8BIT, + .frm_fmt = CCDC_FRMFMT_INTERLACED, + .fid_pol = VPFE_PINPOL_POSITIVE, + .vd_pol = VPFE_PINPOL_POSITIVE, + .hd_pol = VPFE_PINPOL_POSITIVE, + .bt656_enable = 1, + .pix_order = CCDC_PIXORDER_CBYCRY, + .buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED +}; + +static enum vpfe_hw_if_type ccdc_if_type; +static void *__iomem ccdc_base_addr; +static int ccdc_addr_size; + +/* Raw Bayer formats */ +static u32 ccdc_raw_bayer_pix_formats[] = + {V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16}; + +/* Raw YUV formats */ +static u32 ccdc_raw_yuv_pix_formats[] = + {V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV}; + +/* register access routines */ +static inline u32 regr(u32 offset) +{ + return __raw_readl(ccdc_base_addr + offset); +} + +static inline void regw(u32 val, u32 offset) +{ + __raw_writel(val, ccdc_base_addr + offset); +} + +static void ccdc_set_ccdc_base(void *addr, int size) +{ + ccdc_base_addr = addr; + ccdc_addr_size = size; +} + +static void ccdc_enable(int en) +{ + unsigned int temp; + temp = regr(SYNCEN); + temp &= (~CCDC_SYNCEN_VDHDEN_MASK); + temp |= (en & CCDC_SYNCEN_VDHDEN_MASK); + regw(temp, SYNCEN); +} + +static void ccdc_enable_output_to_sdram(int en) +{ + unsigned int temp; + temp = regr(SYNCEN); + temp &= (~(CCDC_SYNCEN_WEN_MASK)); + temp |= ((en << CCDC_SYNCEN_WEN_SHIFT) & CCDC_SYNCEN_WEN_MASK); + regw(temp, SYNCEN); +} + +static void ccdc_config_gain_offset(void) +{ + /* configure gain */ + regw(ccdc_hw_params_raw.gain.r_ye, RYEGAIN); + regw(ccdc_hw_params_raw.gain.gr_cy, GRCYGAIN); + regw(ccdc_hw_params_raw.gain.gb_g, GBGGAIN); + regw(ccdc_hw_params_raw.gain.b_mg, BMGGAIN); + /* configure offset */ + regw(ccdc_hw_params_raw.ccdc_offset, OFFSET); +} + +/* + * ccdc_restore_defaults() + * This function restore power on defaults in the ccdc registers + */ +static int ccdc_restore_defaults(void) +{ + int i; + + dev_dbg(dev, "\nstarting ccdc_restore_defaults..."); + /* set all registers to zero */ + for (i = 0; i <= CCDC_REG_LAST; i += 4) + regw(0, i); + + /* now override the values with power on defaults in registers */ + regw(MODESET_DEFAULT, MODESET); + /* no culling support */ + regw(CULH_DEFAULT, CULH); + regw(CULV_DEFAULT, CULV); + /* Set default Gain and Offset */ + ccdc_hw_params_raw.gain.r_ye = GAIN_DEFAULT; + ccdc_hw_params_raw.gain.gb_g = GAIN_DEFAULT; + ccdc_hw_params_raw.gain.gr_cy = GAIN_DEFAULT; + ccdc_hw_params_raw.gain.b_mg = GAIN_DEFAULT; + ccdc_config_gain_offset(); + regw(OUTCLIP_DEFAULT, OUTCLIP); + regw(LSCCFG2_DEFAULT, LSCCFG2); + /* select ccdc input */ + if (vpss_select_ccdc_source(VPSS_CCDCIN)) { + dev_dbg(dev, "\ncouldn't select ccdc input source"); + return -EFAULT; + } + /* select ccdc clock */ + if (vpss_enable_clock(VPSS_CCDC_CLOCK, 1) < 0) { + dev_dbg(dev, "\ncouldn't enable ccdc clock"); + return -EFAULT; + } + dev_dbg(dev, "\nEnd of ccdc_restore_defaults..."); + return 0; +} + +static int ccdc_open(struct device *device) +{ + dev = device; + return ccdc_restore_defaults(); +} + +static int ccdc_close(struct device *device) +{ + /* disable clock */ + vpss_enable_clock(VPSS_CCDC_CLOCK, 0); + /* do nothing for now */ + return 0; +} +/* + * ccdc_setwin() + * This function will configure the window size to + * be capture in CCDC reg. + */ +static void ccdc_setwin(struct v4l2_rect *image_win, + enum ccdc_frmfmt frm_fmt, int ppc) +{ + int horz_start, horz_nr_pixels; + int vert_start, vert_nr_lines; + int mid_img = 0; + + dev_dbg(dev, "\nStarting ccdc_setwin..."); + + /* + * ppc - per pixel count. indicates how many pixels per cell + * output to SDRAM. example, for ycbcr, it is one y and one c, so 2. + * raw capture this is 1 + */ + horz_start = image_win->left << (ppc - 1); + horz_nr_pixels = ((image_win->width) << (ppc - 1)) - 1; + + /* Writing the horizontal info into the registers */ + regw(horz_start, SPH); + regw(horz_nr_pixels, NPH); + vert_start = image_win->top; + + if (frm_fmt == CCDC_FRMFMT_INTERLACED) { + vert_nr_lines = (image_win->height >> 1) - 1; + vert_start >>= 1; + /* Since first line doesn't have any data */ + vert_start += 1; + /* configure VDINT0 and VDINT1 */ + regw(vert_start, VDINT0); + } else { + /* Since first line doesn't have any data */ + vert_start += 1; + vert_nr_lines = image_win->height - 1; + /* configure VDINT0 and VDINT1 */ + mid_img = vert_start + (image_win->height / 2); + regw(vert_start, VDINT0); + regw(mid_img, VDINT1); + } + regw(vert_start & CCDC_START_VER_ONE_MASK, SLV0); + regw(vert_start & CCDC_START_VER_TWO_MASK, SLV1); + regw(vert_nr_lines & CCDC_NUM_LINES_VER, NLV); + dev_dbg(dev, "\nEnd of ccdc_setwin..."); +} + +static int validate_ccdc_param(struct ccdc_config_params_raw *ccdcparam) +{ + if (ccdcparam->datasft < CCDC_DATA_NO_SHIFT || + ccdcparam->datasft > CCDC_DATA_SHIFT_6BIT) { + dev_dbg(dev, "Invalid value of data shift\n"); + return -EINVAL; + } + + if (ccdcparam->mfilt1 < CCDC_NO_MEDIAN_FILTER1 || + ccdcparam->mfilt1 > CCDC_MEDIAN_FILTER1) { + dev_dbg(dev, "Invalid value of median filter1\n"); + return -EINVAL; + } + + if (ccdcparam->mfilt2 < CCDC_NO_MEDIAN_FILTER2 || + ccdcparam->mfilt2 > CCDC_MEDIAN_FILTER2) { + dev_dbg(dev, "Invalid value of median filter2\n"); + return -EINVAL; + } + + if ((ccdcparam->med_filt_thres < 0) || + (ccdcparam->med_filt_thres > CCDC_MED_FILT_THRESH)) { + dev_dbg(dev, "Invalid value of median filter thresold\n"); + return -EINVAL; + } + + if (ccdcparam->data_sz < CCDC_DATA_16BITS || + ccdcparam->data_sz > CCDC_DATA_8BITS) { + dev_dbg(dev, "Invalid value of data size\n"); + return -EINVAL; + } + + if (ccdcparam->alaw.enable) { + if (ccdcparam->alaw.gama_wd < CCDC_GAMMA_BITS_13_4 || + ccdcparam->alaw.gama_wd > CCDC_GAMMA_BITS_09_0) { + dev_dbg(dev, "Invalid value of ALAW\n"); + return -EINVAL; + } + } + + if (ccdcparam->blk_clamp.b_clamp_enable) { + if (ccdcparam->blk_clamp.sample_pixel < CCDC_SAMPLE_1PIXELS || + ccdcparam->blk_clamp.sample_pixel > CCDC_SAMPLE_16PIXELS) { + dev_dbg(dev, "Invalid value of sample pixel\n"); + return -EINVAL; + } + if (ccdcparam->blk_clamp.sample_ln < CCDC_SAMPLE_1LINES || + ccdcparam->blk_clamp.sample_ln > CCDC_SAMPLE_16LINES) { + dev_dbg(dev, "Invalid value of sample lines\n"); + return -EINVAL; + } + } + return 0; +} + +/* Parameter operations */ +static int ccdc_set_params(void __user *params) +{ + struct ccdc_config_params_raw ccdc_raw_params; + int x; + + /* only raw module parameters can be set through the IOCTL */ + if (ccdc_if_type != VPFE_RAW_BAYER) + return -EINVAL; + + x = copy_from_user(&ccdc_raw_params, params, sizeof(ccdc_raw_params)); + if (x) { + dev_dbg(dev, "ccdc_set_params: error in copying ccdc" + "params, %d\n", x); + return -EFAULT; + } + + if (!validate_ccdc_param(&ccdc_raw_params)) { + memcpy(&ccdc_hw_params_raw.config_params, + &ccdc_raw_params, + sizeof(ccdc_raw_params)); + return 0; + } + return -EINVAL; +} + +/* This function will configure CCDC for YCbCr video capture */ +static void ccdc_config_ycbcr(void) +{ + struct ccdc_params_ycbcr *params = &ccdc_hw_params_ycbcr; + u32 temp; + + /* first set the CCDC power on defaults values in all registers */ + dev_dbg(dev, "\nStarting ccdc_config_ycbcr..."); + ccdc_restore_defaults(); + + /* configure pixel format & video frame format */ + temp = (((params->pix_fmt & CCDC_INPUT_MODE_MASK) << + CCDC_INPUT_MODE_SHIFT) | + ((params->frm_fmt & CCDC_FRM_FMT_MASK) << + CCDC_FRM_FMT_SHIFT)); + + /* setup BT.656 sync mode */ + if (params->bt656_enable) { + regw(CCDC_REC656IF_BT656_EN, REC656IF); + /* + * configure the FID, VD, HD pin polarity fld,hd pol positive, + * vd negative, 8-bit pack mode + */ + temp |= CCDC_VD_POL_NEGATIVE; + } else { /* y/c external sync mode */ + temp |= (((params->fid_pol & CCDC_FID_POL_MASK) << + CCDC_FID_POL_SHIFT) | + ((params->hd_pol & CCDC_HD_POL_MASK) << + CCDC_HD_POL_SHIFT) | + ((params->vd_pol & CCDC_VD_POL_MASK) << + CCDC_VD_POL_SHIFT)); + } + + /* pack the data to 8-bit */ + temp |= CCDC_DATA_PACK_ENABLE; + + regw(temp, MODESET); + + /* configure video window */ + ccdc_setwin(¶ms->win, params->frm_fmt, 2); + + /* configure the order of y cb cr in SD-RAM */ + temp = (params->pix_order << CCDC_Y8POS_SHIFT); + temp |= CCDC_LATCH_ON_VSYNC_DISABLE | CCDC_CCDCFG_FIDMD_NO_LATCH_VSYNC; + regw(temp, CCDCFG); + + /* + * configure the horizontal line offset. This is done by rounding up + * width to a multiple of 16 pixels and multiply by two to account for + * y:cb:cr 4:2:2 data + */ + regw(((params->win.width * 2 + 31) >> 5), HSIZE); + + /* configure the memory line offset */ + if (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED) { + /* two fields are interleaved in memory */ + regw(CCDC_SDOFST_FIELD_INTERLEAVED, SDOFST); + } + + dev_dbg(dev, "\nEnd of ccdc_config_ycbcr...\n"); +} + +/* + * ccdc_config_black_clamp() + * configure parameters for Optical Black Clamp + */ +static void ccdc_config_black_clamp(struct ccdc_black_clamp *bclamp) +{ + u32 val; + + if (!bclamp->b_clamp_enable) { + /* configure DCSub */ + regw(bclamp->dc_sub & CCDC_BLK_DC_SUB_MASK, DCSUB); + regw(0x0000, CLAMP); + return; + } + /* Enable the Black clamping, set sample lines and pixels */ + val = (bclamp->start_pixel & CCDC_BLK_ST_PXL_MASK) | + ((bclamp->sample_pixel & CCDC_BLK_SAMPLE_LN_MASK) << + CCDC_BLK_SAMPLE_LN_SHIFT) | CCDC_BLK_CLAMP_ENABLE; + regw(val, CLAMP); + + /* If Black clamping is enable then make dcsub 0 */ + val = (bclamp->sample_ln & CCDC_NUM_LINE_CALC_MASK) + << CCDC_NUM_LINE_CALC_SHIFT; + regw(val, DCSUB); +} + +/* + * ccdc_config_black_compense() + * configure parameters for Black Compensation + */ +static void ccdc_config_black_compense(struct ccdc_black_compensation *bcomp) +{ + u32 val; + + val = (bcomp->b & CCDC_BLK_COMP_MASK) | + ((bcomp->gb & CCDC_BLK_COMP_MASK) << + CCDC_BLK_COMP_GB_COMP_SHIFT); + regw(val, BLKCMP1); + + val = ((bcomp->gr & CCDC_BLK_COMP_MASK) << + CCDC_BLK_COMP_GR_COMP_SHIFT) | + ((bcomp->r & CCDC_BLK_COMP_MASK) << + CCDC_BLK_COMP_R_COMP_SHIFT); + regw(val, BLKCMP0); +} + +/* + * ccdc_write_dfc_entry() + * write an entry in the dfc table. + */ +int ccdc_write_dfc_entry(int index, struct ccdc_vertical_dft *dfc) +{ +/* TODO This is to be re-visited and adjusted */ +#define DFC_WRITE_WAIT_COUNT 1000 + u32 val, count = DFC_WRITE_WAIT_COUNT; + + regw(dfc->dft_corr_vert[index], DFCMEM0); + regw(dfc->dft_corr_horz[index], DFCMEM1); + regw(dfc->dft_corr_sub1[index], DFCMEM2); + regw(dfc->dft_corr_sub2[index], DFCMEM3); + regw(dfc->dft_corr_sub3[index], DFCMEM4); + /* set WR bit to write */ + val = regr(DFCMEMCTL) | CCDC_DFCMEMCTL_DFCMWR_MASK; + regw(val, DFCMEMCTL); + + /* + * Assume, it is very short. If we get an error, we need to + * adjust this value + */ + while (regr(DFCMEMCTL) & CCDC_DFCMEMCTL_DFCMWR_MASK) + count--; + /* + * TODO We expect the count to be non-zero to be successful. Adjust + * the count if write requires more time + */ + + if (count) { + dev_err(dev, "defect table write timeout !!!\n"); + return -1; + } + return 0; +} + +/* + * ccdc_config_vdfc() + * configure parameters for Vertical Defect Correction + */ +static int ccdc_config_vdfc(struct ccdc_vertical_dft *dfc) +{ + u32 val; + int i; + + /* Configure General Defect Correction. The table used is from IPIPE */ + val = dfc->gen_dft_en & CCDC_DFCCTL_GDFCEN_MASK; + + /* Configure Vertical Defect Correction if needed */ + if (!dfc->ver_dft_en) { + /* Enable only General Defect Correction */ + regw(val, DFCCTL); + return 0; + } + + if (dfc->table_size > CCDC_DFT_TABLE_SIZE) + return -EINVAL; + + val |= CCDC_DFCCTL_VDFC_DISABLE; + val |= (dfc->dft_corr_ctl.vdfcsl & CCDC_DFCCTL_VDFCSL_MASK) << + CCDC_DFCCTL_VDFCSL_SHIFT; + val |= (dfc->dft_corr_ctl.vdfcuda & CCDC_DFCCTL_VDFCUDA_MASK) << + CCDC_DFCCTL_VDFCUDA_SHIFT; + val |= (dfc->dft_corr_ctl.vdflsft & CCDC_DFCCTL_VDFLSFT_MASK) << + CCDC_DFCCTL_VDFLSFT_SHIFT; + regw(val , DFCCTL); + + /* clear address ptr to offset 0 */ + val = CCDC_DFCMEMCTL_DFCMARST_MASK << CCDC_DFCMEMCTL_DFCMARST_SHIFT; + + /* write defect table entries */ + for (i = 0; i < dfc->table_size; i++) { + /* increment address for non zero index */ + if (i != 0) + val = CCDC_DFCMEMCTL_INC_ADDR; + regw(val, DFCMEMCTL); + if (ccdc_write_dfc_entry(i, dfc) < 0) + return -EFAULT; + } + + /* update saturation level and enable dfc */ + regw(dfc->saturation_ctl & CCDC_VDC_DFCVSAT_MASK, DFCVSAT); + val = regr(DFCCTL) | (CCDC_DFCCTL_VDFCEN_MASK << + CCDC_DFCCTL_VDFCEN_SHIFT); + regw(val, DFCCTL); + return 0; +} + +/* + * ccdc_config_csc() + * configure parameters for color space conversion + * Each register CSCM0-7 has two values in S8Q5 format. + */ +static void ccdc_config_csc(struct ccdc_csc *csc) +{ + u32 val1, val2; + int i; + + if (!csc->enable) + return; + + /* Enable the CSC sub-module */ + regw(CCDC_CSC_ENABLE, CSCCTL); + + /* Converting the co-eff as per the format of the register */ + for (i = 0; i < CCDC_CSC_COEFF_TABLE_SIZE; i++) { + if ((i % 2) == 0) { + /* CSCM - LSB */ + val1 = (csc->coeff[i].integer & + CCDC_CSC_COEF_INTEG_MASK) + << CCDC_CSC_COEF_INTEG_SHIFT; + /* + * convert decimal part to binary. Use 2 decimal + * precision, user values range from .00 - 0.99 + */ + val1 |= (((csc->coeff[i].decimal & + CCDC_CSC_COEF_DECIMAL_MASK) * + CCDC_CSC_DEC_MAX) / 100); + } else { + + /* CSCM - MSB */ + val2 = (csc->coeff[i].integer & + CCDC_CSC_COEF_INTEG_MASK) + << CCDC_CSC_COEF_INTEG_SHIFT; + val2 |= (((csc->coeff[i].decimal & + CCDC_CSC_COEF_DECIMAL_MASK) * + CCDC_CSC_DEC_MAX) / 100); + val2 <<= CCDC_CSCM_MSB_SHIFT; + val2 |= val1; + regw(val2, (CSCM0 + ((i - 1) << 1))); + } + } +} + +/* + * ccdc_config_color_patterns() + * configure parameters for color patterns + */ +static void ccdc_config_color_patterns(struct ccdc_col_pat *pat0, + struct ccdc_col_pat *pat1) +{ + u32 val; + + val = (pat0->olop | (pat0->olep << 2) | (pat0->elop << 4) | + (pat0->elep << 6) | (pat1->olop << 8) | (pat1->olep << 10) | + (pat1->elop << 12) | (pat1->elep << 14)); + regw(val, COLPTN); +} + +/* This function will configure CCDC for Raw mode image capture */ +static int ccdc_config_raw(void) +{ + struct ccdc_params_raw *params = &ccdc_hw_params_raw; + struct ccdc_config_params_raw *config_params = + &ccdc_hw_params_raw.config_params; + unsigned int val; + + dev_dbg(dev, "\nStarting ccdc_config_raw..."); + + /* restore power on defaults to register */ + ccdc_restore_defaults(); + + /* CCDCFG register: + * set CCD Not to swap input since input is RAW data + * set FID detection function to Latch at V-Sync + * set WENLOG - ccdc valid area to AND + * set TRGSEL to WENBIT + * set EXTRG to DISABLE + * disable latching function on VSYNC - shadowed registers + */ + regw(CCDC_YCINSWP_RAW | CCDC_CCDCFG_FIDMD_LATCH_VSYNC | + CCDC_CCDCFG_WENLOG_AND | CCDC_CCDCFG_TRGSEL_WEN | + CCDC_CCDCFG_EXTRG_DISABLE | CCDC_LATCH_ON_VSYNC_DISABLE, CCDCFG); + + /* + * Set VDHD direction to input, input type to raw input + * normal data polarity, do not use external WEN + */ + val = (CCDC_VDHDOUT_INPUT | CCDC_RAW_IP_MODE | CCDC_DATAPOL_NORMAL | + CCDC_EXWEN_DISABLE); + + /* + * Configure the vertical sync polarity (MODESET.VDPOL), horizontal + * sync polarity (MODESET.HDPOL), field id polarity (MODESET.FLDPOL), + * frame format(progressive or interlace), & pixel format (Input mode) + */ + val |= (((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT) | + ((params->hd_pol & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT) | + ((params->fid_pol & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT) | + ((params->frm_fmt & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT) | + ((params->pix_fmt & CCDC_PIX_FMT_MASK) << CCDC_PIX_FMT_SHIFT)); + + /* set pack for alaw compression */ + if ((config_params->data_sz == CCDC_DATA_8BITS) || + config_params->alaw.enable) + val |= CCDC_DATA_PACK_ENABLE; + + /* Configure for LPF */ + if (config_params->lpf_enable) + val |= (config_params->lpf_enable & CCDC_LPF_MASK) << + CCDC_LPF_SHIFT; + + /* Configure the data shift */ + val |= (config_params->datasft & CCDC_DATASFT_MASK) << + CCDC_DATASFT_SHIFT; + regw(val , MODESET); + dev_dbg(dev, "\nWriting 0x%x to MODESET...\n", val); + + /* Configure the Median Filter threshold */ + regw((config_params->med_filt_thres) & CCDC_MED_FILT_THRESH, MEDFILT); + + /* Configure GAMMAWD register. defaur 11-2, and Mosaic cfa pattern */ + val = CCDC_GAMMA_BITS_11_2 << CCDC_GAMMAWD_INPUT_SHIFT | + CCDC_CFA_MOSAIC; + + /* Enable and configure aLaw register if needed */ + if (config_params->alaw.enable) { + val |= (CCDC_ALAW_ENABLE | + ((config_params->alaw.gama_wd & + CCDC_ALAW_GAMA_WD_MASK) << + CCDC_GAMMAWD_INPUT_SHIFT)); + } + + /* Configure Median filter1 & filter2 */ + val |= ((config_params->mfilt1 << CCDC_MFILT1_SHIFT) | + (config_params->mfilt2 << CCDC_MFILT2_SHIFT)); + + regw(val, GAMMAWD); + dev_dbg(dev, "\nWriting 0x%x to GAMMAWD...\n", val); + + /* configure video window */ + ccdc_setwin(¶ms->win, params->frm_fmt, 1); + + /* Optical Clamp Averaging */ + ccdc_config_black_clamp(&config_params->blk_clamp); + + /* Black level compensation */ + ccdc_config_black_compense(&config_params->blk_comp); + + /* Vertical Defect Correction if needed */ + if (ccdc_config_vdfc(&config_params->vertical_dft) < 0) + return -EFAULT; + + /* color space conversion */ + ccdc_config_csc(&config_params->csc); + + /* color pattern */ + ccdc_config_color_patterns(&config_params->col_pat_field0, + &config_params->col_pat_field1); + + /* Configure the Gain & offset control */ + ccdc_config_gain_offset(); + + dev_dbg(dev, "\nWriting %x to COLPTN...\n", val); + + /* Configure DATAOFST register */ + val = (config_params->data_offset.horz_offset & CCDC_DATAOFST_MASK) << + CCDC_DATAOFST_H_SHIFT; + val |= (config_params->data_offset.vert_offset & CCDC_DATAOFST_MASK) << + CCDC_DATAOFST_V_SHIFT; + regw(val, DATAOFST); + + /* configuring HSIZE register */ + val = (params->horz_flip_enable & CCDC_HSIZE_FLIP_MASK) << + CCDC_HSIZE_FLIP_SHIFT; + + /* If pack 8 is enable then 1 pixel will take 1 byte */ + if ((config_params->data_sz == CCDC_DATA_8BITS) || + config_params->alaw.enable) { + val |= (((params->win.width) + 31) >> 5) & + CCDC_HSIZE_VAL_MASK; + + /* adjust to multiple of 32 */ + dev_dbg(dev, "\nWriting 0x%x to HSIZE...\n", + (((params->win.width) + 31) >> 5) & + CCDC_HSIZE_VAL_MASK); + } else { + /* else one pixel will take 2 byte */ + val |= (((params->win.width * 2) + 31) >> 5) & + CCDC_HSIZE_VAL_MASK; + + dev_dbg(dev, "\nWriting 0x%x to HSIZE...\n", + (((params->win.width * 2) + 31) >> 5) & + CCDC_HSIZE_VAL_MASK); + } + regw(val, HSIZE); + + /* Configure SDOFST register */ + if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) { + if (params->image_invert_enable) { + /* For interlace inverse mode */ + regw(CCDC_SDOFST_INTERLACE_INVERSE, SDOFST); + dev_dbg(dev, "\nWriting %x to SDOFST...\n", + CCDC_SDOFST_INTERLACE_INVERSE); + } else { + /* For interlace non inverse mode */ + regw(CCDC_SDOFST_INTERLACE_NORMAL, SDOFST); + dev_dbg(dev, "\nWriting %x to SDOFST...\n", + CCDC_SDOFST_INTERLACE_NORMAL); + } + } else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) { + if (params->image_invert_enable) { + /* For progessive inverse mode */ + regw(CCDC_SDOFST_PROGRESSIVE_INVERSE, SDOFST); + dev_dbg(dev, "\nWriting %x to SDOFST...\n", + CCDC_SDOFST_PROGRESSIVE_INVERSE); + } else { + /* For progessive non inverse mode */ + regw(CCDC_SDOFST_PROGRESSIVE_NORMAL, SDOFST); + dev_dbg(dev, "\nWriting %x to SDOFST...\n", + CCDC_SDOFST_PROGRESSIVE_NORMAL); + } + } + dev_dbg(dev, "\nend of ccdc_config_raw..."); + return 0; +} + +static int ccdc_configure(void) +{ + if (ccdc_if_type == VPFE_RAW_BAYER) + return ccdc_config_raw(); + else + ccdc_config_ycbcr(); + return 0; +} + +static int ccdc_set_buftype(enum ccdc_buftype buf_type) +{ + if (ccdc_if_type == VPFE_RAW_BAYER) + ccdc_hw_params_raw.buf_type = buf_type; + else + ccdc_hw_params_ycbcr.buf_type = buf_type; + return 0; +} +static enum ccdc_buftype ccdc_get_buftype(void) +{ + if (ccdc_if_type == VPFE_RAW_BAYER) + return ccdc_hw_params_raw.buf_type; + return ccdc_hw_params_ycbcr.buf_type; +} + +static int ccdc_enum_pix(u32 *pix, int i) +{ + int ret = -EINVAL; + if (ccdc_if_type == VPFE_RAW_BAYER) { + if (i < ARRAY_SIZE(ccdc_raw_bayer_pix_formats)) { + *pix = ccdc_raw_bayer_pix_formats[i]; + ret = 0; + } + } else { + if (i < ARRAY_SIZE(ccdc_raw_yuv_pix_formats)) { + *pix = ccdc_raw_yuv_pix_formats[i]; + ret = 0; + } + } + return ret; +} + +static int ccdc_set_pixel_format(u32 pixfmt) +{ + struct ccdc_a_law *alaw = + &ccdc_hw_params_raw.config_params.alaw; + + if (ccdc_if_type == VPFE_RAW_BAYER) { + ccdc_hw_params_raw.pix_fmt = CCDC_PIXFMT_RAW; + if (pixfmt == V4L2_PIX_FMT_SBGGR8) + alaw->enable = 1; + else if (pixfmt != V4L2_PIX_FMT_SBGGR16) + return -EINVAL; + } else { + if (pixfmt == V4L2_PIX_FMT_YUYV) + ccdc_hw_params_ycbcr.pix_order = CCDC_PIXORDER_YCBYCR; + else if (pixfmt == V4L2_PIX_FMT_UYVY) + ccdc_hw_params_ycbcr.pix_order = CCDC_PIXORDER_CBYCRY; + else + return -EINVAL; + } + return 0; +} +static u32 ccdc_get_pixel_format(void) +{ + struct ccdc_a_law *alaw = + &ccdc_hw_params_raw.config_params.alaw; + u32 pixfmt; + + if (ccdc_if_type == VPFE_RAW_BAYER) + if (alaw->enable) + pixfmt = V4L2_PIX_FMT_SBGGR8; + else + pixfmt = V4L2_PIX_FMT_SBGGR16; + else { + if (ccdc_hw_params_ycbcr.pix_order == CCDC_PIXORDER_YCBYCR) + pixfmt = V4L2_PIX_FMT_YUYV; + else + pixfmt = V4L2_PIX_FMT_UYVY; + } + return pixfmt; +} +static int ccdc_set_image_window(struct v4l2_rect *win) +{ + if (ccdc_if_type == VPFE_RAW_BAYER) + ccdc_hw_params_raw.win = *win; + else + ccdc_hw_params_ycbcr.win = *win; + return 0; +} + +static void ccdc_get_image_window(struct v4l2_rect *win) +{ + if (ccdc_if_type == VPFE_RAW_BAYER) + *win = ccdc_hw_params_raw.win; + else + *win = ccdc_hw_params_ycbcr.win; +} + +static unsigned int ccdc_get_line_length(void) +{ + struct ccdc_config_params_raw *config_params = + &ccdc_hw_params_raw.config_params; + unsigned int len; + + if (ccdc_if_type == VPFE_RAW_BAYER) { + if ((config_params->alaw.enable) || + (config_params->data_sz == CCDC_DATA_8BITS)) + len = ccdc_hw_params_raw.win.width; + else + len = ccdc_hw_params_raw.win.width * 2; + } else + len = ccdc_hw_params_ycbcr.win.width * 2; + return ALIGN(len, 32); +} + +static int ccdc_set_frame_format(enum ccdc_frmfmt frm_fmt) +{ + if (ccdc_if_type == VPFE_RAW_BAYER) + ccdc_hw_params_raw.frm_fmt = frm_fmt; + else + ccdc_hw_params_ycbcr.frm_fmt = frm_fmt; + return 0; +} + +static enum ccdc_frmfmt ccdc_get_frame_format(void) +{ + if (ccdc_if_type == VPFE_RAW_BAYER) + return ccdc_hw_params_raw.frm_fmt; + else + return ccdc_hw_params_ycbcr.frm_fmt; +} + +static int ccdc_getfid(void) +{ + return (regr(MODESET) >> 15) & 1; +} + +/* misc operations */ +static inline void ccdc_setfbaddr(unsigned long addr) +{ + regw((addr >> 21) & 0x007f, STADRH); + regw((addr >> 5) & 0x0ffff, STADRL); +} + +static int ccdc_set_hw_if_params(struct vpfe_hw_if_param *params) +{ + ccdc_if_type = params->if_type; + + switch (params->if_type) { + case VPFE_BT656: + case VPFE_YCBCR_SYNC_16: + case VPFE_YCBCR_SYNC_8: + ccdc_hw_params_ycbcr.vd_pol = params->vdpol; + ccdc_hw_params_ycbcr.hd_pol = params->hdpol; + break; + default: + /* TODO add support for raw bayer here */ + return -EINVAL; + } + return 0; +} + +static struct ccdc_hw_device ccdc_hw_dev = { + .name = "DM355 CCDC", + .owner = THIS_MODULE, + .hw_ops = { + .open = ccdc_open, + .close = ccdc_close, + .set_ccdc_base = ccdc_set_ccdc_base, + .enable = ccdc_enable, + .enable_out_to_sdram = ccdc_enable_output_to_sdram, + .set_hw_if_params = ccdc_set_hw_if_params, + .set_params = ccdc_set_params, + .configure = ccdc_configure, + .set_buftype = ccdc_set_buftype, + .get_buftype = ccdc_get_buftype, + .enum_pix = ccdc_enum_pix, + .set_pixel_format = ccdc_set_pixel_format, + .get_pixel_format = ccdc_get_pixel_format, + .set_frame_format = ccdc_set_frame_format, + .get_frame_format = ccdc_get_frame_format, + .set_image_window = ccdc_set_image_window, + .get_image_window = ccdc_get_image_window, + .get_line_length = ccdc_get_line_length, + .setfbaddr = ccdc_setfbaddr, + .getfid = ccdc_getfid, + }, +}; + +static int dm355_ccdc_init(void) +{ + printk(KERN_NOTICE "dm355_ccdc_init\n"); + if (vpfe_register_ccdc_device(&ccdc_hw_dev) < 0) + return -1; + printk(KERN_NOTICE "%s is registered with vpfe.\n", + ccdc_hw_dev.name); + return 0; +} + +static void dm355_ccdc_exit(void) +{ + vpfe_unregister_ccdc_device(&ccdc_hw_dev); +} + +module_init(dm355_ccdc_init); +module_exit(dm355_ccdc_exit); diff --git a/drivers/media/video/davinci/dm355_ccdc_regs.h b/drivers/media/video/davinci/dm355_ccdc_regs.h new file mode 100644 index 000000000000..d6d2ef0533b5 --- /dev/null +++ b/drivers/media/video/davinci/dm355_ccdc_regs.h @@ -0,0 +1,310 @@ +/* + * Copyright (C) 2005-2009 Texas Instruments Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _DM355_CCDC_REGS_H +#define _DM355_CCDC_REGS_H + +/**************************************************************************\ +* Register OFFSET Definitions +\**************************************************************************/ +#define SYNCEN 0x00 +#define MODESET 0x04 +#define HDWIDTH 0x08 +#define VDWIDTH 0x0c +#define PPLN 0x10 +#define LPFR 0x14 +#define SPH 0x18 +#define NPH 0x1c +#define SLV0 0x20 +#define SLV1 0x24 +#define NLV 0x28 +#define CULH 0x2c +#define CULV 0x30 +#define HSIZE 0x34 +#define SDOFST 0x38 +#define STADRH 0x3c +#define STADRL 0x40 +#define CLAMP 0x44 +#define DCSUB 0x48 +#define COLPTN 0x4c +#define BLKCMP0 0x50 +#define BLKCMP1 0x54 +#define MEDFILT 0x58 +#define RYEGAIN 0x5c +#define GRCYGAIN 0x60 +#define GBGGAIN 0x64 +#define BMGGAIN 0x68 +#define OFFSET 0x6c +#define OUTCLIP 0x70 +#define VDINT0 0x74 +#define VDINT1 0x78 +#define RSV0 0x7c +#define GAMMAWD 0x80 +#define REC656IF 0x84 +#define CCDCFG 0x88 +#define FMTCFG 0x8c +#define FMTPLEN 0x90 +#define FMTSPH 0x94 +#define FMTLNH 0x98 +#define FMTSLV 0x9c +#define FMTLNV 0xa0 +#define FMTRLEN 0xa4 +#define FMTHCNT 0xa8 +#define FMT_ADDR_PTR_B 0xac +#define FMT_ADDR_PTR(i) (FMT_ADDR_PTR_B + (i * 4)) +#define FMTPGM_VF0 0xcc +#define FMTPGM_VF1 0xd0 +#define FMTPGM_AP0 0xd4 +#define FMTPGM_AP1 0xd8 +#define FMTPGM_AP2 0xdc +#define FMTPGM_AP3 0xe0 +#define FMTPGM_AP4 0xe4 +#define FMTPGM_AP5 0xe8 +#define FMTPGM_AP6 0xec +#define FMTPGM_AP7 0xf0 +#define LSCCFG1 0xf4 +#define LSCCFG2 0xf8 +#define LSCH0 0xfc +#define LSCV0 0x100 +#define LSCKH 0x104 +#define LSCKV 0x108 +#define LSCMEMCTL 0x10c +#define LSCMEMD 0x110 +#define LSCMEMQ 0x114 +#define DFCCTL 0x118 +#define DFCVSAT 0x11c +#define DFCMEMCTL 0x120 +#define DFCMEM0 0x124 +#define DFCMEM1 0x128 +#define DFCMEM2 0x12c +#define DFCMEM3 0x130 +#define DFCMEM4 0x134 +#define CSCCTL 0x138 +#define CSCM0 0x13c +#define CSCM1 0x140 +#define CSCM2 0x144 +#define CSCM3 0x148 +#define CSCM4 0x14c +#define CSCM5 0x150 +#define CSCM6 0x154 +#define CSCM7 0x158 +#define DATAOFST 0x15c +#define CCDC_REG_LAST DATAOFST +/************************************************************** +* Define for various register bit mask and shifts for CCDC +* +**************************************************************/ +#define CCDC_RAW_IP_MODE 0 +#define CCDC_VDHDOUT_INPUT 0 +#define CCDC_YCINSWP_RAW (0 << 4) +#define CCDC_EXWEN_DISABLE 0 +#define CCDC_DATAPOL_NORMAL 0 +#define CCDC_CCDCFG_FIDMD_LATCH_VSYNC 0 +#define CCDC_CCDCFG_FIDMD_NO_LATCH_VSYNC (1 << 6) +#define CCDC_CCDCFG_WENLOG_AND 0 +#define CCDC_CCDCFG_TRGSEL_WEN 0 +#define CCDC_CCDCFG_EXTRG_DISABLE 0 +#define CCDC_CFA_MOSAIC 0 +#define CCDC_Y8POS_SHIFT 11 + +#define CCDC_VDC_DFCVSAT_MASK 0x3fff +#define CCDC_DATAOFST_MASK 0x0ff +#define CCDC_DATAOFST_H_SHIFT 0 +#define CCDC_DATAOFST_V_SHIFT 8 +#define CCDC_GAMMAWD_CFA_MASK 1 +#define CCDC_GAMMAWD_CFA_SHIFT 5 +#define CCDC_GAMMAWD_INPUT_SHIFT 2 +#define CCDC_FID_POL_MASK 1 +#define CCDC_FID_POL_SHIFT 4 +#define CCDC_HD_POL_MASK 1 +#define CCDC_HD_POL_SHIFT 3 +#define CCDC_VD_POL_MASK 1 +#define CCDC_VD_POL_SHIFT 2 +#define CCDC_VD_POL_NEGATIVE (1 << 2) +#define CCDC_FRM_FMT_MASK 1 +#define CCDC_FRM_FMT_SHIFT 7 +#define CCDC_DATA_SZ_MASK 7 +#define CCDC_DATA_SZ_SHIFT 8 +#define CCDC_VDHDOUT_MASK 1 +#define CCDC_VDHDOUT_SHIFT 0 +#define CCDC_EXWEN_MASK 1 +#define CCDC_EXWEN_SHIFT 5 +#define CCDC_INPUT_MODE_MASK 3 +#define CCDC_INPUT_MODE_SHIFT 12 +#define CCDC_PIX_FMT_MASK 3 +#define CCDC_PIX_FMT_SHIFT 12 +#define CCDC_DATAPOL_MASK 1 +#define CCDC_DATAPOL_SHIFT 6 +#define CCDC_WEN_ENABLE (1 << 1) +#define CCDC_VDHDEN_ENABLE (1 << 16) +#define CCDC_LPF_ENABLE (1 << 14) +#define CCDC_ALAW_ENABLE 1 +#define CCDC_ALAW_GAMA_WD_MASK 7 +#define CCDC_REC656IF_BT656_EN 3 + +#define CCDC_FMTCFG_FMTMODE_MASK 3 +#define CCDC_FMTCFG_FMTMODE_SHIFT 1 +#define CCDC_FMTCFG_LNUM_MASK 3 +#define CCDC_FMTCFG_LNUM_SHIFT 4 +#define CCDC_FMTCFG_ADDRINC_MASK 7 +#define CCDC_FMTCFG_ADDRINC_SHIFT 8 + +#define CCDC_CCDCFG_FIDMD_SHIFT 6 +#define CCDC_CCDCFG_WENLOG_SHIFT 8 +#define CCDC_CCDCFG_TRGSEL_SHIFT 9 +#define CCDC_CCDCFG_EXTRG_SHIFT 10 +#define CCDC_CCDCFG_MSBINVI_SHIFT 13 + +#define CCDC_HSIZE_FLIP_SHIFT 12 +#define CCDC_HSIZE_FLIP_MASK 1 +#define CCDC_HSIZE_VAL_MASK 0xFFF +#define CCDC_SDOFST_FIELD_INTERLEAVED 0x249 +#define CCDC_SDOFST_INTERLACE_INVERSE 0x4B6D +#define CCDC_SDOFST_INTERLACE_NORMAL 0x0B6D +#define CCDC_SDOFST_PROGRESSIVE_INVERSE 0x4000 +#define CCDC_SDOFST_PROGRESSIVE_NORMAL 0 +#define CCDC_START_PX_HOR_MASK 0x7FFF +#define CCDC_NUM_PX_HOR_MASK 0x7FFF +#define CCDC_START_VER_ONE_MASK 0x7FFF +#define CCDC_START_VER_TWO_MASK 0x7FFF +#define CCDC_NUM_LINES_VER 0x7FFF + +#define CCDC_BLK_CLAMP_ENABLE (1 << 15) +#define CCDC_BLK_SGAIN_MASK 0x1F +#define CCDC_BLK_ST_PXL_MASK 0x1FFF +#define CCDC_BLK_SAMPLE_LN_MASK 3 +#define CCDC_BLK_SAMPLE_LN_SHIFT 13 + +#define CCDC_NUM_LINE_CALC_MASK 3 +#define CCDC_NUM_LINE_CALC_SHIFT 14 + +#define CCDC_BLK_DC_SUB_MASK 0x3FFF +#define CCDC_BLK_COMP_MASK 0xFF +#define CCDC_BLK_COMP_GB_COMP_SHIFT 8 +#define CCDC_BLK_COMP_GR_COMP_SHIFT 0 +#define CCDC_BLK_COMP_R_COMP_SHIFT 8 +#define CCDC_LATCH_ON_VSYNC_DISABLE (1 << 15) +#define CCDC_LATCH_ON_VSYNC_ENABLE (0 << 15) +#define CCDC_FPC_ENABLE (1 << 15) +#define CCDC_FPC_FPC_NUM_MASK 0x7FFF +#define CCDC_DATA_PACK_ENABLE (1 << 11) +#define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF +#define CCDC_FMT_HORZ_FMTSPH_MASK 0x1FFF +#define CCDC_FMT_HORZ_FMTSPH_SHIFT 16 +#define CCDC_FMT_VERT_FMTLNV_MASK 0x1FFF +#define CCDC_FMT_VERT_FMTSLV_MASK 0x1FFF +#define CCDC_FMT_VERT_FMTSLV_SHIFT 16 +#define CCDC_VP_OUT_VERT_NUM_MASK 0x3FFF +#define CCDC_VP_OUT_VERT_NUM_SHIFT 17 +#define CCDC_VP_OUT_HORZ_NUM_MASK 0x1FFF +#define CCDC_VP_OUT_HORZ_NUM_SHIFT 4 +#define CCDC_VP_OUT_HORZ_ST_MASK 0xF + +#define CCDC_CSC_COEF_INTEG_MASK 7 +#define CCDC_CSC_COEF_DECIMAL_MASK 0x1f +#define CCDC_CSC_COEF_INTEG_SHIFT 5 +#define CCDC_CSCM_MSB_SHIFT 8 +#define CCDC_CSC_ENABLE 1 +#define CCDC_CSC_DEC_MAX 32 + +#define CCDC_MFILT1_SHIFT 10 +#define CCDC_MFILT2_SHIFT 8 +#define CCDC_MED_FILT_THRESH 0x3FFF +#define CCDC_LPF_MASK 1 +#define CCDC_LPF_SHIFT 14 +#define CCDC_OFFSET_MASK 0x3FF +#define CCDC_DATASFT_MASK 7 +#define CCDC_DATASFT_SHIFT 8 + +#define CCDC_DF_ENABLE 1 + +#define CCDC_FMTPLEN_P0_MASK 0xF +#define CCDC_FMTPLEN_P1_MASK 0xF +#define CCDC_FMTPLEN_P2_MASK 7 +#define CCDC_FMTPLEN_P3_MASK 7 +#define CCDC_FMTPLEN_P0_SHIFT 0 +#define CCDC_FMTPLEN_P1_SHIFT 4 +#define CCDC_FMTPLEN_P2_SHIFT 8 +#define CCDC_FMTPLEN_P3_SHIFT 12 + +#define CCDC_FMTSPH_MASK 0x1FFF +#define CCDC_FMTLNH_MASK 0x1FFF +#define CCDC_FMTSLV_MASK 0x1FFF +#define CCDC_FMTLNV_MASK 0x7FFF +#define CCDC_FMTRLEN_MASK 0x1FFF +#define CCDC_FMTHCNT_MASK 0x1FFF + +#define CCDC_ADP_INIT_MASK 0x1FFF +#define CCDC_ADP_LINE_SHIFT 13 +#define CCDC_ADP_LINE_MASK 3 +#define CCDC_FMTPGN_APTR_MASK 7 + +#define CCDC_DFCCTL_GDFCEN_MASK 1 +#define CCDC_DFCCTL_VDFCEN_MASK 1 +#define CCDC_DFCCTL_VDFC_DISABLE (0 << 4) +#define CCDC_DFCCTL_VDFCEN_SHIFT 4 +#define CCDC_DFCCTL_VDFCSL_MASK 3 +#define CCDC_DFCCTL_VDFCSL_SHIFT 5 +#define CCDC_DFCCTL_VDFCUDA_MASK 1 +#define CCDC_DFCCTL_VDFCUDA_SHIFT 7 +#define CCDC_DFCCTL_VDFLSFT_MASK 3 +#define CCDC_DFCCTL_VDFLSFT_SHIFT 8 +#define CCDC_DFCMEMCTL_DFCMARST_MASK 1 +#define CCDC_DFCMEMCTL_DFCMARST_SHIFT 2 +#define CCDC_DFCMEMCTL_DFCMWR_MASK 1 +#define CCDC_DFCMEMCTL_DFCMWR_SHIFT 0 +#define CCDC_DFCMEMCTL_INC_ADDR (0 << 2) + +#define CCDC_LSCCFG_GFTSF_MASK 7 +#define CCDC_LSCCFG_GFTSF_SHIFT 1 +#define CCDC_LSCCFG_GFTINV_MASK 0xf +#define CCDC_LSCCFG_GFTINV_SHIFT 4 +#define CCDC_LSC_GFTABLE_SEL_MASK 3 +#define CCDC_LSC_GFTABLE_EPEL_SHIFT 8 +#define CCDC_LSC_GFTABLE_OPEL_SHIFT 10 +#define CCDC_LSC_GFTABLE_EPOL_SHIFT 12 +#define CCDC_LSC_GFTABLE_OPOL_SHIFT 14 +#define CCDC_LSC_GFMODE_MASK 3 +#define CCDC_LSC_GFMODE_SHIFT 4 +#define CCDC_LSC_DISABLE 0 +#define CCDC_LSC_ENABLE 1 +#define CCDC_LSC_TABLE1_SLC 0 +#define CCDC_LSC_TABLE2_SLC 1 +#define CCDC_LSC_TABLE3_SLC 2 +#define CCDC_LSC_MEMADDR_RESET (1 << 2) +#define CCDC_LSC_MEMADDR_INCR (0 << 2) +#define CCDC_LSC_FRAC_MASK_T1 0xFF +#define CCDC_LSC_INT_MASK 3 +#define CCDC_LSC_FRAC_MASK 0x3FFF +#define CCDC_LSC_CENTRE_MASK 0x3FFF +#define CCDC_LSC_COEF_MASK 0xff +#define CCDC_LSC_COEFL_SHIFT 0 +#define CCDC_LSC_COEFU_SHIFT 8 +#define CCDC_GAIN_MASK 0x7FF +#define CCDC_SYNCEN_VDHDEN_MASK (1 << 0) +#define CCDC_SYNCEN_WEN_MASK (1 << 1) +#define CCDC_SYNCEN_WEN_SHIFT 1 + +/* Power on Defaults in hardware */ +#define MODESET_DEFAULT 0x200 +#define CULH_DEFAULT 0xFFFF +#define CULV_DEFAULT 0xFF +#define GAIN_DEFAULT 256 +#define OUTCLIP_DEFAULT 0x3FFF +#define LSCCFG2_DEFAULT 0xE + +#endif diff --git a/drivers/media/video/davinci/dm644x_ccdc.c b/drivers/media/video/davinci/dm644x_ccdc.c new file mode 100644 index 000000000000..2f19a919f477 --- /dev/null +++ b/drivers/media/video/davinci/dm644x_ccdc.c @@ -0,0 +1,878 @@ +/* + * Copyright (C) 2006-2009 Texas Instruments Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * CCDC hardware module for DM6446 + * ------------------------------ + * + * This module is for configuring CCD controller of DM6446 VPFE to capture + * Raw yuv or Bayer RGB data from a decoder. CCDC has several modules + * such as Defect Pixel Correction, Color Space Conversion etc to + * pre-process the Raw Bayer RGB data, before writing it to SDRAM. This + * module also allows application to configure individual + * module parameters through VPFE_CMD_S_CCDC_RAW_PARAMS IOCTL. + * To do so, application includes dm644x_ccdc.h and vpfe_capture.h header + * files. The setparams() API is called by vpfe_capture driver + * to configure module parameters. This file is named DM644x so that other + * variants such DM6443 may be supported using the same module. + * + * TODO: Test Raw bayer parameter settings and bayer capture + * Split module parameter structure to module specific ioctl structs + * investigate if enum used for user space type definition + * to be replaced by #defines or integer + */ +#include +#include +#include +#include +#include +#include "dm644x_ccdc_regs.h" +#include "ccdc_hw_device.h" + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("CCDC Driver for DM6446"); +MODULE_AUTHOR("Texas Instruments"); + +static struct device *dev; + +/* Object for CCDC raw mode */ +static struct ccdc_params_raw ccdc_hw_params_raw = { + .pix_fmt = CCDC_PIXFMT_RAW, + .frm_fmt = CCDC_FRMFMT_PROGRESSIVE, + .win = CCDC_WIN_VGA, + .fid_pol = VPFE_PINPOL_POSITIVE, + .vd_pol = VPFE_PINPOL_POSITIVE, + .hd_pol = VPFE_PINPOL_POSITIVE, + .config_params = { + .data_sz = CCDC_DATA_10BITS, + }, +}; + +/* Object for CCDC ycbcr mode */ +static struct ccdc_params_ycbcr ccdc_hw_params_ycbcr = { + .pix_fmt = CCDC_PIXFMT_YCBCR_8BIT, + .frm_fmt = CCDC_FRMFMT_INTERLACED, + .win = CCDC_WIN_PAL, + .fid_pol = VPFE_PINPOL_POSITIVE, + .vd_pol = VPFE_PINPOL_POSITIVE, + .hd_pol = VPFE_PINPOL_POSITIVE, + .bt656_enable = 1, + .pix_order = CCDC_PIXORDER_CBYCRY, + .buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED +}; + +#define CCDC_MAX_RAW_YUV_FORMATS 2 + +/* Raw Bayer formats */ +static u32 ccdc_raw_bayer_pix_formats[] = + {V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16}; + +/* Raw YUV formats */ +static u32 ccdc_raw_yuv_pix_formats[] = + {V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV}; + +static void *__iomem ccdc_base_addr; +static int ccdc_addr_size; +static enum vpfe_hw_if_type ccdc_if_type; + +/* register access routines */ +static inline u32 regr(u32 offset) +{ + return __raw_readl(ccdc_base_addr + offset); +} + +static inline void regw(u32 val, u32 offset) +{ + __raw_writel(val, ccdc_base_addr + offset); +} + +static void ccdc_set_ccdc_base(void *addr, int size) +{ + ccdc_base_addr = addr; + ccdc_addr_size = size; +} + +static void ccdc_enable(int flag) +{ + regw(flag, CCDC_PCR); +} + +static void ccdc_enable_vport(int flag) +{ + if (flag) + /* enable video port */ + regw(CCDC_ENABLE_VIDEO_PORT, CCDC_FMTCFG); + else + regw(CCDC_DISABLE_VIDEO_PORT, CCDC_FMTCFG); +} + +/* + * ccdc_setwin() + * This function will configure the window size + * to be capture in CCDC reg + */ +void ccdc_setwin(struct v4l2_rect *image_win, + enum ccdc_frmfmt frm_fmt, + int ppc) +{ + int horz_start, horz_nr_pixels; + int vert_start, vert_nr_lines; + int val = 0, mid_img = 0; + + dev_dbg(dev, "\nStarting ccdc_setwin..."); + /* + * ppc - per pixel count. indicates how many pixels per cell + * output to SDRAM. example, for ycbcr, it is one y and one c, so 2. + * raw capture this is 1 + */ + horz_start = image_win->left << (ppc - 1); + horz_nr_pixels = (image_win->width << (ppc - 1)) - 1; + regw((horz_start << CCDC_HORZ_INFO_SPH_SHIFT) | horz_nr_pixels, + CCDC_HORZ_INFO); + + vert_start = image_win->top; + + if (frm_fmt == CCDC_FRMFMT_INTERLACED) { + vert_nr_lines = (image_win->height >> 1) - 1; + vert_start >>= 1; + /* Since first line doesn't have any data */ + vert_start += 1; + /* configure VDINT0 */ + val = (vert_start << CCDC_VDINT_VDINT0_SHIFT); + regw(val, CCDC_VDINT); + + } else { + /* Since first line doesn't have any data */ + vert_start += 1; + vert_nr_lines = image_win->height - 1; + /* + * configure VDINT0 and VDINT1. VDINT1 will be at half + * of image height + */ + mid_img = vert_start + (image_win->height / 2); + val = (vert_start << CCDC_VDINT_VDINT0_SHIFT) | + (mid_img & CCDC_VDINT_VDINT1_MASK); + regw(val, CCDC_VDINT); + + } + regw((vert_start << CCDC_VERT_START_SLV0_SHIFT) | vert_start, + CCDC_VERT_START); + regw(vert_nr_lines, CCDC_VERT_LINES); + dev_dbg(dev, "\nEnd of ccdc_setwin..."); +} + +static void ccdc_readregs(void) +{ + unsigned int val = 0; + + val = regr(CCDC_ALAW); + dev_notice(dev, "\nReading 0x%x to ALAW...\n", val); + val = regr(CCDC_CLAMP); + dev_notice(dev, "\nReading 0x%x to CLAMP...\n", val); + val = regr(CCDC_DCSUB); + dev_notice(dev, "\nReading 0x%x to DCSUB...\n", val); + val = regr(CCDC_BLKCMP); + dev_notice(dev, "\nReading 0x%x to BLKCMP...\n", val); + val = regr(CCDC_FPC_ADDR); + dev_notice(dev, "\nReading 0x%x to FPC_ADDR...\n", val); + val = regr(CCDC_FPC); + dev_notice(dev, "\nReading 0x%x to FPC...\n", val); + val = regr(CCDC_FMTCFG); + dev_notice(dev, "\nReading 0x%x to FMTCFG...\n", val); + val = regr(CCDC_COLPTN); + dev_notice(dev, "\nReading 0x%x to COLPTN...\n", val); + val = regr(CCDC_FMT_HORZ); + dev_notice(dev, "\nReading 0x%x to FMT_HORZ...\n", val); + val = regr(CCDC_FMT_VERT); + dev_notice(dev, "\nReading 0x%x to FMT_VERT...\n", val); + val = regr(CCDC_HSIZE_OFF); + dev_notice(dev, "\nReading 0x%x to HSIZE_OFF...\n", val); + val = regr(CCDC_SDOFST); + dev_notice(dev, "\nReading 0x%x to SDOFST...\n", val); + val = regr(CCDC_VP_OUT); + dev_notice(dev, "\nReading 0x%x to VP_OUT...\n", val); + val = regr(CCDC_SYN_MODE); + dev_notice(dev, "\nReading 0x%x to SYN_MODE...\n", val); + val = regr(CCDC_HORZ_INFO); + dev_notice(dev, "\nReading 0x%x to HORZ_INFO...\n", val); + val = regr(CCDC_VERT_START); + dev_notice(dev, "\nReading 0x%x to VERT_START...\n", val); + val = regr(CCDC_VERT_LINES); + dev_notice(dev, "\nReading 0x%x to VERT_LINES...\n", val); +} + +static int validate_ccdc_param(struct ccdc_config_params_raw *ccdcparam) +{ + if (ccdcparam->alaw.enable) { + if ((ccdcparam->alaw.gama_wd > CCDC_GAMMA_BITS_09_0) || + (ccdcparam->alaw.gama_wd < CCDC_GAMMA_BITS_15_6) || + (ccdcparam->alaw.gama_wd < ccdcparam->data_sz)) { + dev_dbg(dev, "\nInvalid data line select"); + return -1; + } + } + return 0; +} + +static int ccdc_update_raw_params(struct ccdc_config_params_raw *raw_params) +{ + struct ccdc_config_params_raw *config_params = + &ccdc_hw_params_raw.config_params; + unsigned int *fpc_virtaddr = NULL; + unsigned int *fpc_physaddr = NULL; + + memcpy(config_params, raw_params, sizeof(*raw_params)); + /* + * allocate memory for fault pixel table and copy the user + * values to the table + */ + if (!config_params->fault_pxl.enable) + return 0; + + fpc_physaddr = (unsigned int *)config_params->fault_pxl.fpc_table_addr; + fpc_virtaddr = (unsigned int *)phys_to_virt( + (unsigned long)fpc_physaddr); + /* + * Allocate memory for FPC table if current + * FPC table buffer is not big enough to + * accomodate FPC Number requested + */ + if (raw_params->fault_pxl.fp_num != config_params->fault_pxl.fp_num) { + if (fpc_physaddr != NULL) { + free_pages((unsigned long)fpc_physaddr, + get_order + (config_params->fault_pxl.fp_num * + FP_NUM_BYTES)); + } + + /* Allocate memory for FPC table */ + fpc_virtaddr = + (unsigned int *)__get_free_pages(GFP_KERNEL | GFP_DMA, + get_order(raw_params-> + fault_pxl.fp_num * + FP_NUM_BYTES)); + + if (fpc_virtaddr == NULL) { + dev_dbg(dev, + "\nUnable to allocate memory for FPC"); + return -EFAULT; + } + fpc_physaddr = + (unsigned int *)virt_to_phys((void *)fpc_virtaddr); + } + + /* Copy number of fault pixels and FPC table */ + config_params->fault_pxl.fp_num = raw_params->fault_pxl.fp_num; + if (copy_from_user(fpc_virtaddr, + (void __user *)raw_params->fault_pxl.fpc_table_addr, + config_params->fault_pxl.fp_num * FP_NUM_BYTES)) { + dev_dbg(dev, "\n copy_from_user failed"); + return -EFAULT; + } + config_params->fault_pxl.fpc_table_addr = (unsigned int)fpc_physaddr; + return 0; +} + +static int ccdc_close(struct device *dev) +{ + struct ccdc_config_params_raw *config_params = + &ccdc_hw_params_raw.config_params; + unsigned int *fpc_physaddr = NULL, *fpc_virtaddr = NULL; + + fpc_physaddr = (unsigned int *)config_params->fault_pxl.fpc_table_addr; + + if (fpc_physaddr != NULL) { + fpc_virtaddr = (unsigned int *) + phys_to_virt((unsigned long)fpc_physaddr); + free_pages((unsigned long)fpc_virtaddr, + get_order(config_params->fault_pxl.fp_num * + FP_NUM_BYTES)); + } + return 0; +} + +/* + * ccdc_restore_defaults() + * This function will write defaults to all CCDC registers + */ +static void ccdc_restore_defaults(void) +{ + int i; + + /* disable CCDC */ + ccdc_enable(0); + /* set all registers to default value */ + for (i = 4; i <= 0x94; i += 4) + regw(0, i); + regw(CCDC_NO_CULLING, CCDC_CULLING); + regw(CCDC_GAMMA_BITS_11_2, CCDC_ALAW); +} + +static int ccdc_open(struct device *device) +{ + dev = device; + ccdc_restore_defaults(); + if (ccdc_if_type == VPFE_RAW_BAYER) + ccdc_enable_vport(1); + return 0; +} + +static void ccdc_sbl_reset(void) +{ + vpss_clear_wbl_overflow(VPSS_PCR_CCDC_WBL_O); +} + +/* Parameter operations */ +static int ccdc_set_params(void __user *params) +{ + struct ccdc_config_params_raw ccdc_raw_params; + int x; + + if (ccdc_if_type != VPFE_RAW_BAYER) + return -EINVAL; + + x = copy_from_user(&ccdc_raw_params, params, sizeof(ccdc_raw_params)); + if (x) { + dev_dbg(dev, "ccdc_set_params: error in copying" + "ccdc params, %d\n", x); + return -EFAULT; + } + + if (!validate_ccdc_param(&ccdc_raw_params)) { + if (!ccdc_update_raw_params(&ccdc_raw_params)) + return 0; + } + return -EINVAL; +} + +/* + * ccdc_config_ycbcr() + * This function will configure CCDC for YCbCr video capture + */ +void ccdc_config_ycbcr(void) +{ + struct ccdc_params_ycbcr *params = &ccdc_hw_params_ycbcr; + u32 syn_mode; + + dev_dbg(dev, "\nStarting ccdc_config_ycbcr..."); + /* + * first restore the CCDC registers to default values + * This is important since we assume default values to be set in + * a lot of registers that we didn't touch + */ + ccdc_restore_defaults(); + + /* + * configure pixel format, frame format, configure video frame + * format, enable output to SDRAM, enable internal timing generator + * and 8bit pack mode + */ + syn_mode = (((params->pix_fmt & CCDC_SYN_MODE_INPMOD_MASK) << + CCDC_SYN_MODE_INPMOD_SHIFT) | + ((params->frm_fmt & CCDC_SYN_FLDMODE_MASK) << + CCDC_SYN_FLDMODE_SHIFT) | CCDC_VDHDEN_ENABLE | + CCDC_WEN_ENABLE | CCDC_DATA_PACK_ENABLE); + + /* setup BT.656 sync mode */ + if (params->bt656_enable) { + regw(CCDC_REC656IF_BT656_EN, CCDC_REC656IF); + + /* + * configure the FID, VD, HD pin polarity, + * fld,hd pol positive, vd negative, 8-bit data + */ + syn_mode |= CCDC_SYN_MODE_VD_POL_NEGATIVE | CCDC_SYN_MODE_8BITS; + } else { + /* y/c external sync mode */ + syn_mode |= (((params->fid_pol & CCDC_FID_POL_MASK) << + CCDC_FID_POL_SHIFT) | + ((params->hd_pol & CCDC_HD_POL_MASK) << + CCDC_HD_POL_SHIFT) | + ((params->vd_pol & CCDC_VD_POL_MASK) << + CCDC_VD_POL_SHIFT)); + } + regw(syn_mode, CCDC_SYN_MODE); + + /* configure video window */ + ccdc_setwin(¶ms->win, params->frm_fmt, 2); + + /* + * configure the order of y cb cr in SDRAM, and disable latch + * internal register on vsync + */ + regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) | + CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG); + + /* + * configure the horizontal line offset. This should be a + * on 32 byte bondary. So clear LSB 5 bits + */ + regw(((params->win.width * 2 + 31) & ~0x1f), CCDC_HSIZE_OFF); + + /* configure the memory line offset */ + if (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED) + /* two fields are interleaved in memory */ + regw(CCDC_SDOFST_FIELD_INTERLEAVED, CCDC_SDOFST); + + ccdc_sbl_reset(); + dev_dbg(dev, "\nEnd of ccdc_config_ycbcr...\n"); + ccdc_readregs(); +} + +static void ccdc_config_black_clamp(struct ccdc_black_clamp *bclamp) +{ + u32 val; + + if (!bclamp->enable) { + /* configure DCSub */ + val = (bclamp->dc_sub) & CCDC_BLK_DC_SUB_MASK; + regw(val, CCDC_DCSUB); + dev_dbg(dev, "\nWriting 0x%x to DCSUB...\n", val); + regw(CCDC_CLAMP_DEFAULT_VAL, CCDC_CLAMP); + dev_dbg(dev, "\nWriting 0x0000 to CLAMP...\n"); + return; + } + /* + * Configure gain, Start pixel, No of line to be avg, + * No of pixel/line to be avg, & Enable the Black clamping + */ + val = ((bclamp->sgain & CCDC_BLK_SGAIN_MASK) | + ((bclamp->start_pixel & CCDC_BLK_ST_PXL_MASK) << + CCDC_BLK_ST_PXL_SHIFT) | + ((bclamp->sample_ln & CCDC_BLK_SAMPLE_LINE_MASK) << + CCDC_BLK_SAMPLE_LINE_SHIFT) | + ((bclamp->sample_pixel & CCDC_BLK_SAMPLE_LN_MASK) << + CCDC_BLK_SAMPLE_LN_SHIFT) | CCDC_BLK_CLAMP_ENABLE); + regw(val, CCDC_CLAMP); + dev_dbg(dev, "\nWriting 0x%x to CLAMP...\n", val); + /* If Black clamping is enable then make dcsub 0 */ + regw(CCDC_DCSUB_DEFAULT_VAL, CCDC_DCSUB); + dev_dbg(dev, "\nWriting 0x00000000 to DCSUB...\n"); +} + +static void ccdc_config_black_compense(struct ccdc_black_compensation *bcomp) +{ + u32 val; + + val = ((bcomp->b & CCDC_BLK_COMP_MASK) | + ((bcomp->gb & CCDC_BLK_COMP_MASK) << + CCDC_BLK_COMP_GB_COMP_SHIFT) | + ((bcomp->gr & CCDC_BLK_COMP_MASK) << + CCDC_BLK_COMP_GR_COMP_SHIFT) | + ((bcomp->r & CCDC_BLK_COMP_MASK) << + CCDC_BLK_COMP_R_COMP_SHIFT)); + regw(val, CCDC_BLKCMP); +} + +static void ccdc_config_fpc(struct ccdc_fault_pixel *fpc) +{ + u32 val; + + /* Initially disable FPC */ + val = CCDC_FPC_DISABLE; + regw(val, CCDC_FPC); + + if (!fpc->enable) + return; + + /* Configure Fault pixel if needed */ + regw(fpc->fpc_table_addr, CCDC_FPC_ADDR); + dev_dbg(dev, "\nWriting 0x%x to FPC_ADDR...\n", + (fpc->fpc_table_addr)); + /* Write the FPC params with FPC disable */ + val = fpc->fp_num & CCDC_FPC_FPC_NUM_MASK; + regw(val, CCDC_FPC); + + dev_dbg(dev, "\nWriting 0x%x to FPC...\n", val); + /* read the FPC register */ + val = regr(CCDC_FPC) | CCDC_FPC_ENABLE; + regw(val, CCDC_FPC); + dev_dbg(dev, "\nWriting 0x%x to FPC...\n", val); +} + +/* + * ccdc_config_raw() + * This function will configure CCDC for Raw capture mode + */ +void ccdc_config_raw(void) +{ + struct ccdc_params_raw *params = &ccdc_hw_params_raw; + struct ccdc_config_params_raw *config_params = + &ccdc_hw_params_raw.config_params; + unsigned int syn_mode = 0; + unsigned int val; + + dev_dbg(dev, "\nStarting ccdc_config_raw..."); + + /* Reset CCDC */ + ccdc_restore_defaults(); + + /* Disable latching function registers on VSYNC */ + regw(CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG); + + /* + * Configure the vertical sync polarity(SYN_MODE.VDPOL), + * horizontal sync polarity (SYN_MODE.HDPOL), frame id polarity + * (SYN_MODE.FLDPOL), frame format(progressive or interlace), + * data size(SYNMODE.DATSIZ), &pixel format (Input mode), output + * SDRAM, enable internal timing generator + */ + syn_mode = + (((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT) | + ((params->hd_pol & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT) | + ((params->fid_pol & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT) | + ((params->frm_fmt & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT) | + ((config_params->data_sz & CCDC_DATA_SZ_MASK) << + CCDC_DATA_SZ_SHIFT) | + ((params->pix_fmt & CCDC_PIX_FMT_MASK) << CCDC_PIX_FMT_SHIFT) | + CCDC_WEN_ENABLE | CCDC_VDHDEN_ENABLE); + + /* Enable and configure aLaw register if needed */ + if (config_params->alaw.enable) { + val = ((config_params->alaw.gama_wd & + CCDC_ALAW_GAMA_WD_MASK) | CCDC_ALAW_ENABLE); + regw(val, CCDC_ALAW); + dev_dbg(dev, "\nWriting 0x%x to ALAW...\n", val); + } + + /* Configure video window */ + ccdc_setwin(¶ms->win, params->frm_fmt, CCDC_PPC_RAW); + + /* Configure Black Clamp */ + ccdc_config_black_clamp(&config_params->blk_clamp); + + /* Configure Black level compensation */ + ccdc_config_black_compense(&config_params->blk_comp); + + /* Configure Fault Pixel Correction */ + ccdc_config_fpc(&config_params->fault_pxl); + + /* If data size is 8 bit then pack the data */ + if ((config_params->data_sz == CCDC_DATA_8BITS) || + config_params->alaw.enable) + syn_mode |= CCDC_DATA_PACK_ENABLE; + +#ifdef CONFIG_DM644X_VIDEO_PORT_ENABLE + /* enable video port */ + val = CCDC_ENABLE_VIDEO_PORT; +#else + /* disable video port */ + val = CCDC_DISABLE_VIDEO_PORT; +#endif + + if (config_params->data_sz == CCDC_DATA_8BITS) + val |= (CCDC_DATA_10BITS & CCDC_FMTCFG_VPIN_MASK) + << CCDC_FMTCFG_VPIN_SHIFT; + else + val |= (config_params->data_sz & CCDC_FMTCFG_VPIN_MASK) + << CCDC_FMTCFG_VPIN_SHIFT; + /* Write value in FMTCFG */ + regw(val, CCDC_FMTCFG); + + dev_dbg(dev, "\nWriting 0x%x to FMTCFG...\n", val); + /* Configure the color pattern according to mt9t001 sensor */ + regw(CCDC_COLPTN_VAL, CCDC_COLPTN); + + dev_dbg(dev, "\nWriting 0xBB11BB11 to COLPTN...\n"); + /* + * Configure Data formatter(Video port) pixel selection + * (FMT_HORZ, FMT_VERT) + */ + val = ((params->win.left & CCDC_FMT_HORZ_FMTSPH_MASK) << + CCDC_FMT_HORZ_FMTSPH_SHIFT) | + (params->win.width & CCDC_FMT_HORZ_FMTLNH_MASK); + regw(val, CCDC_FMT_HORZ); + + dev_dbg(dev, "\nWriting 0x%x to FMT_HORZ...\n", val); + val = (params->win.top & CCDC_FMT_VERT_FMTSLV_MASK) + << CCDC_FMT_VERT_FMTSLV_SHIFT; + if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) + val |= (params->win.height) & CCDC_FMT_VERT_FMTLNV_MASK; + else + val |= (params->win.height >> 1) & CCDC_FMT_VERT_FMTLNV_MASK; + + dev_dbg(dev, "\nparams->win.height 0x%x ...\n", + params->win.height); + regw(val, CCDC_FMT_VERT); + + dev_dbg(dev, "\nWriting 0x%x to FMT_VERT...\n", val); + + dev_dbg(dev, "\nbelow regw(val, FMT_VERT)..."); + + /* + * Configure Horizontal offset register. If pack 8 is enabled then + * 1 pixel will take 1 byte + */ + if ((config_params->data_sz == CCDC_DATA_8BITS) || + config_params->alaw.enable) + regw((params->win.width + CCDC_32BYTE_ALIGN_VAL) & + CCDC_HSIZE_OFF_MASK, CCDC_HSIZE_OFF); + else + /* else one pixel will take 2 byte */ + regw(((params->win.width * CCDC_TWO_BYTES_PER_PIXEL) + + CCDC_32BYTE_ALIGN_VAL) & CCDC_HSIZE_OFF_MASK, + CCDC_HSIZE_OFF); + + /* Set value for SDOFST */ + if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) { + if (params->image_invert_enable) { + /* For intelace inverse mode */ + regw(CCDC_INTERLACED_IMAGE_INVERT, CCDC_SDOFST); + dev_dbg(dev, "\nWriting 0x4B6D to SDOFST...\n"); + } + + else { + /* For intelace non inverse mode */ + regw(CCDC_INTERLACED_NO_IMAGE_INVERT, CCDC_SDOFST); + dev_dbg(dev, "\nWriting 0x0249 to SDOFST...\n"); + } + } else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) { + regw(CCDC_PROGRESSIVE_NO_IMAGE_INVERT, CCDC_SDOFST); + dev_dbg(dev, "\nWriting 0x0000 to SDOFST...\n"); + } + + /* + * Configure video port pixel selection (VPOUT) + * Here -1 is to make the height value less than FMT_VERT.FMTLNV + */ + if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) + val = (((params->win.height - 1) & CCDC_VP_OUT_VERT_NUM_MASK)) + << CCDC_VP_OUT_VERT_NUM_SHIFT; + else + val = + ((((params->win.height >> CCDC_INTERLACED_HEIGHT_SHIFT) - + 1) & CCDC_VP_OUT_VERT_NUM_MASK)) << + CCDC_VP_OUT_VERT_NUM_SHIFT; + + val |= ((((params->win.width))) & CCDC_VP_OUT_HORZ_NUM_MASK) + << CCDC_VP_OUT_HORZ_NUM_SHIFT; + val |= (params->win.left) & CCDC_VP_OUT_HORZ_ST_MASK; + regw(val, CCDC_VP_OUT); + + dev_dbg(dev, "\nWriting 0x%x to VP_OUT...\n", val); + regw(syn_mode, CCDC_SYN_MODE); + dev_dbg(dev, "\nWriting 0x%x to SYN_MODE...\n", syn_mode); + + ccdc_sbl_reset(); + dev_dbg(dev, "\nend of ccdc_config_raw..."); + ccdc_readregs(); +} + +static int ccdc_configure(void) +{ + if (ccdc_if_type == VPFE_RAW_BAYER) + ccdc_config_raw(); + else + ccdc_config_ycbcr(); + return 0; +} + +static int ccdc_set_buftype(enum ccdc_buftype buf_type) +{ + if (ccdc_if_type == VPFE_RAW_BAYER) + ccdc_hw_params_raw.buf_type = buf_type; + else + ccdc_hw_params_ycbcr.buf_type = buf_type; + return 0; +} + +static enum ccdc_buftype ccdc_get_buftype(void) +{ + if (ccdc_if_type == VPFE_RAW_BAYER) + return ccdc_hw_params_raw.buf_type; + return ccdc_hw_params_ycbcr.buf_type; +} + +static int ccdc_enum_pix(u32 *pix, int i) +{ + int ret = -EINVAL; + if (ccdc_if_type == VPFE_RAW_BAYER) { + if (i < ARRAY_SIZE(ccdc_raw_bayer_pix_formats)) { + *pix = ccdc_raw_bayer_pix_formats[i]; + ret = 0; + } + } else { + if (i < ARRAY_SIZE(ccdc_raw_yuv_pix_formats)) { + *pix = ccdc_raw_yuv_pix_formats[i]; + ret = 0; + } + } + return ret; +} + +static int ccdc_set_pixel_format(u32 pixfmt) +{ + if (ccdc_if_type == VPFE_RAW_BAYER) { + ccdc_hw_params_raw.pix_fmt = CCDC_PIXFMT_RAW; + if (pixfmt == V4L2_PIX_FMT_SBGGR8) + ccdc_hw_params_raw.config_params.alaw.enable = 1; + else if (pixfmt != V4L2_PIX_FMT_SBGGR16) + return -EINVAL; + } else { + if (pixfmt == V4L2_PIX_FMT_YUYV) + ccdc_hw_params_ycbcr.pix_order = CCDC_PIXORDER_YCBYCR; + else if (pixfmt == V4L2_PIX_FMT_UYVY) + ccdc_hw_params_ycbcr.pix_order = CCDC_PIXORDER_CBYCRY; + else + return -EINVAL; + } + return 0; +} + +static u32 ccdc_get_pixel_format(void) +{ + struct ccdc_a_law *alaw = + &ccdc_hw_params_raw.config_params.alaw; + u32 pixfmt; + + if (ccdc_if_type == VPFE_RAW_BAYER) + if (alaw->enable) + pixfmt = V4L2_PIX_FMT_SBGGR8; + else + pixfmt = V4L2_PIX_FMT_SBGGR16; + else { + if (ccdc_hw_params_ycbcr.pix_order == CCDC_PIXORDER_YCBYCR) + pixfmt = V4L2_PIX_FMT_YUYV; + else + pixfmt = V4L2_PIX_FMT_UYVY; + } + return pixfmt; +} + +static int ccdc_set_image_window(struct v4l2_rect *win) +{ + if (ccdc_if_type == VPFE_RAW_BAYER) + ccdc_hw_params_raw.win = *win; + else + ccdc_hw_params_ycbcr.win = *win; + return 0; +} + +static void ccdc_get_image_window(struct v4l2_rect *win) +{ + if (ccdc_if_type == VPFE_RAW_BAYER) + *win = ccdc_hw_params_raw.win; + else + *win = ccdc_hw_params_ycbcr.win; +} + +static unsigned int ccdc_get_line_length(void) +{ + struct ccdc_config_params_raw *config_params = + &ccdc_hw_params_raw.config_params; + unsigned int len; + + if (ccdc_if_type == VPFE_RAW_BAYER) { + if ((config_params->alaw.enable) || + (config_params->data_sz == CCDC_DATA_8BITS)) + len = ccdc_hw_params_raw.win.width; + else + len = ccdc_hw_params_raw.win.width * 2; + } else + len = ccdc_hw_params_ycbcr.win.width * 2; + return ALIGN(len, 32); +} + +static int ccdc_set_frame_format(enum ccdc_frmfmt frm_fmt) +{ + if (ccdc_if_type == VPFE_RAW_BAYER) + ccdc_hw_params_raw.frm_fmt = frm_fmt; + else + ccdc_hw_params_ycbcr.frm_fmt = frm_fmt; + return 0; +} + +static enum ccdc_frmfmt ccdc_get_frame_format(void) +{ + if (ccdc_if_type == VPFE_RAW_BAYER) + return ccdc_hw_params_raw.frm_fmt; + else + return ccdc_hw_params_ycbcr.frm_fmt; +} + +static int ccdc_getfid(void) +{ + return (regr(CCDC_SYN_MODE) >> 15) & 1; +} + +/* misc operations */ +static inline void ccdc_setfbaddr(unsigned long addr) +{ + regw(addr & 0xffffffe0, CCDC_SDR_ADDR); +} + +static int ccdc_set_hw_if_params(struct vpfe_hw_if_param *params) +{ + ccdc_if_type = params->if_type; + + switch (params->if_type) { + case VPFE_BT656: + case VPFE_YCBCR_SYNC_16: + case VPFE_YCBCR_SYNC_8: + ccdc_hw_params_ycbcr.vd_pol = params->vdpol; + ccdc_hw_params_ycbcr.hd_pol = params->hdpol; + break; + default: + /* TODO add support for raw bayer here */ + return -EINVAL; + } + return 0; +} + +static struct ccdc_hw_device ccdc_hw_dev = { + .name = "DM6446 CCDC", + .owner = THIS_MODULE, + .hw_ops = { + .open = ccdc_open, + .close = ccdc_close, + .set_ccdc_base = ccdc_set_ccdc_base, + .reset = ccdc_sbl_reset, + .enable = ccdc_enable, + .set_hw_if_params = ccdc_set_hw_if_params, + .set_params = ccdc_set_params, + .configure = ccdc_configure, + .set_buftype = ccdc_set_buftype, + .get_buftype = ccdc_get_buftype, + .enum_pix = ccdc_enum_pix, + .set_pixel_format = ccdc_set_pixel_format, + .get_pixel_format = ccdc_get_pixel_format, + .set_frame_format = ccdc_set_frame_format, + .get_frame_format = ccdc_get_frame_format, + .set_image_window = ccdc_set_image_window, + .get_image_window = ccdc_get_image_window, + .get_line_length = ccdc_get_line_length, + .setfbaddr = ccdc_setfbaddr, + .getfid = ccdc_getfid, + }, +}; + +static int dm644x_ccdc_init(void) +{ + printk(KERN_NOTICE "dm644x_ccdc_init\n"); + if (vpfe_register_ccdc_device(&ccdc_hw_dev) < 0) + return -1; + printk(KERN_NOTICE "%s is registered with vpfe.\n", + ccdc_hw_dev.name); + return 0; +} + +static void dm644x_ccdc_exit(void) +{ + vpfe_unregister_ccdc_device(&ccdc_hw_dev); +} + +module_init(dm644x_ccdc_init); +module_exit(dm644x_ccdc_exit); diff --git a/drivers/media/video/davinci/dm644x_ccdc_regs.h b/drivers/media/video/davinci/dm644x_ccdc_regs.h new file mode 100644 index 000000000000..6e5d05324466 --- /dev/null +++ b/drivers/media/video/davinci/dm644x_ccdc_regs.h @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2006-2009 Texas Instruments Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _DM644X_CCDC_REGS_H +#define _DM644X_CCDC_REGS_H + +/**************************************************************************\ +* Register OFFSET Definitions +\**************************************************************************/ +#define CCDC_PID 0x0 +#define CCDC_PCR 0x4 +#define CCDC_SYN_MODE 0x8 +#define CCDC_HD_VD_WID 0xc +#define CCDC_PIX_LINES 0x10 +#define CCDC_HORZ_INFO 0x14 +#define CCDC_VERT_START 0x18 +#define CCDC_VERT_LINES 0x1c +#define CCDC_CULLING 0x20 +#define CCDC_HSIZE_OFF 0x24 +#define CCDC_SDOFST 0x28 +#define CCDC_SDR_ADDR 0x2c +#define CCDC_CLAMP 0x30 +#define CCDC_DCSUB 0x34 +#define CCDC_COLPTN 0x38 +#define CCDC_BLKCMP 0x3c +#define CCDC_FPC 0x40 +#define CCDC_FPC_ADDR 0x44 +#define CCDC_VDINT 0x48 +#define CCDC_ALAW 0x4c +#define CCDC_REC656IF 0x50 +#define CCDC_CCDCFG 0x54 +#define CCDC_FMTCFG 0x58 +#define CCDC_FMT_HORZ 0x5c +#define CCDC_FMT_VERT 0x60 +#define CCDC_FMT_ADDR0 0x64 +#define CCDC_FMT_ADDR1 0x68 +#define CCDC_FMT_ADDR2 0x6c +#define CCDC_FMT_ADDR3 0x70 +#define CCDC_FMT_ADDR4 0x74 +#define CCDC_FMT_ADDR5 0x78 +#define CCDC_FMT_ADDR6 0x7c +#define CCDC_FMT_ADDR7 0x80 +#define CCDC_PRGEVEN_0 0x84 +#define CCDC_PRGEVEN_1 0x88 +#define CCDC_PRGODD_0 0x8c +#define CCDC_PRGODD_1 0x90 +#define CCDC_VP_OUT 0x94 + + +/*************************************************************** +* Define for various register bit mask and shifts for CCDC +****************************************************************/ +#define CCDC_FID_POL_MASK 1 +#define CCDC_FID_POL_SHIFT 4 +#define CCDC_HD_POL_MASK 1 +#define CCDC_HD_POL_SHIFT 3 +#define CCDC_VD_POL_MASK 1 +#define CCDC_VD_POL_SHIFT 2 +#define CCDC_HSIZE_OFF_MASK 0xffffffe0 +#define CCDC_32BYTE_ALIGN_VAL 31 +#define CCDC_FRM_FMT_MASK 0x1 +#define CCDC_FRM_FMT_SHIFT 7 +#define CCDC_DATA_SZ_MASK 7 +#define CCDC_DATA_SZ_SHIFT 8 +#define CCDC_PIX_FMT_MASK 3 +#define CCDC_PIX_FMT_SHIFT 12 +#define CCDC_VP2SDR_DISABLE 0xFFFBFFFF +#define CCDC_WEN_ENABLE (1 << 17) +#define CCDC_SDR2RSZ_DISABLE 0xFFF7FFFF +#define CCDC_VDHDEN_ENABLE (1 << 16) +#define CCDC_LPF_ENABLE (1 << 14) +#define CCDC_ALAW_ENABLE (1 << 3) +#define CCDC_ALAW_GAMA_WD_MASK 7 +#define CCDC_BLK_CLAMP_ENABLE (1 << 31) +#define CCDC_BLK_SGAIN_MASK 0x1F +#define CCDC_BLK_ST_PXL_MASK 0x7FFF +#define CCDC_BLK_ST_PXL_SHIFT 10 +#define CCDC_BLK_SAMPLE_LN_MASK 7 +#define CCDC_BLK_SAMPLE_LN_SHIFT 28 +#define CCDC_BLK_SAMPLE_LINE_MASK 7 +#define CCDC_BLK_SAMPLE_LINE_SHIFT 25 +#define CCDC_BLK_DC_SUB_MASK 0x03FFF +#define CCDC_BLK_COMP_MASK 0xFF +#define CCDC_BLK_COMP_GB_COMP_SHIFT 8 +#define CCDC_BLK_COMP_GR_COMP_SHIFT 16 +#define CCDC_BLK_COMP_R_COMP_SHIFT 24 +#define CCDC_LATCH_ON_VSYNC_DISABLE (1 << 15) +#define CCDC_FPC_ENABLE (1 << 15) +#define CCDC_FPC_DISABLE 0 +#define CCDC_FPC_FPC_NUM_MASK 0x7FFF +#define CCDC_DATA_PACK_ENABLE (1 << 11) +#define CCDC_FMTCFG_VPIN_MASK 7 +#define CCDC_FMTCFG_VPIN_SHIFT 12 +#define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF +#define CCDC_FMT_HORZ_FMTSPH_MASK 0x1FFF +#define CCDC_FMT_HORZ_FMTSPH_SHIFT 16 +#define CCDC_FMT_VERT_FMTLNV_MASK 0x1FFF +#define CCDC_FMT_VERT_FMTSLV_MASK 0x1FFF +#define CCDC_FMT_VERT_FMTSLV_SHIFT 16 +#define CCDC_VP_OUT_VERT_NUM_MASK 0x3FFF +#define CCDC_VP_OUT_VERT_NUM_SHIFT 17 +#define CCDC_VP_OUT_HORZ_NUM_MASK 0x1FFF +#define CCDC_VP_OUT_HORZ_NUM_SHIFT 4 +#define CCDC_VP_OUT_HORZ_ST_MASK 0xF +#define CCDC_HORZ_INFO_SPH_SHIFT 16 +#define CCDC_VERT_START_SLV0_SHIFT 16 +#define CCDC_VDINT_VDINT0_SHIFT 16 +#define CCDC_VDINT_VDINT1_MASK 0xFFFF +#define CCDC_PPC_RAW 1 +#define CCDC_DCSUB_DEFAULT_VAL 0 +#define CCDC_CLAMP_DEFAULT_VAL 0 +#define CCDC_ENABLE_VIDEO_PORT 0x8000 +#define CCDC_DISABLE_VIDEO_PORT 0 +#define CCDC_COLPTN_VAL 0xBB11BB11 +#define CCDC_TWO_BYTES_PER_PIXEL 2 +#define CCDC_INTERLACED_IMAGE_INVERT 0x4B6D +#define CCDC_INTERLACED_NO_IMAGE_INVERT 0x0249 +#define CCDC_PROGRESSIVE_IMAGE_INVERT 0x4000 +#define CCDC_PROGRESSIVE_NO_IMAGE_INVERT 0 +#define CCDC_INTERLACED_HEIGHT_SHIFT 1 +#define CCDC_SYN_MODE_INPMOD_SHIFT 12 +#define CCDC_SYN_MODE_INPMOD_MASK 3 +#define CCDC_SYN_MODE_8BITS (7 << 8) +#define CCDC_SYN_FLDMODE_MASK 1 +#define CCDC_SYN_FLDMODE_SHIFT 7 +#define CCDC_REC656IF_BT656_EN 3 +#define CCDC_SYN_MODE_VD_POL_NEGATIVE (1 << 2) +#define CCDC_CCDCFG_Y8POS_SHIFT 11 +#define CCDC_SDOFST_FIELD_INTERLEAVED 0x249 +#define CCDC_NO_CULLING 0xffff00ff +#endif diff --git a/drivers/media/video/davinci/vpfe_capture.c b/drivers/media/video/davinci/vpfe_capture.c new file mode 100644 index 000000000000..402ce43ef38e --- /dev/null +++ b/drivers/media/video/davinci/vpfe_capture.c @@ -0,0 +1,2124 @@ +/* + * Copyright (C) 2008-2009 Texas Instruments Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Driver name : VPFE Capture driver + * VPFE Capture driver allows applications to capture and stream video + * frames on DaVinci SoCs (DM6446, DM355 etc) from a YUV source such as + * TVP5146 or Raw Bayer RGB image data from an image sensor + * such as Microns' MT9T001, MT9T031 etc. + * + * These SoCs have, in common, a Video Processing Subsystem (VPSS) that + * consists of a Video Processing Front End (VPFE) for capturing + * video/raw image data and Video Processing Back End (VPBE) for displaying + * YUV data through an in-built analog encoder or Digital LCD port. This + * driver is for capture through VPFE. A typical EVM using these SoCs have + * following high level configuration. + * + * + * decoder(TVP5146/ YUV/ + * MT9T001) --> Raw Bayer RGB ---> MUX -> VPFE (CCDC/ISIF) + * data input | | + * V | + * SDRAM | + * V + * Image Processor + * | + * V + * SDRAM + * The data flow happens from a decoder connected to the VPFE over a + * YUV embedded (BT.656/BT.1120) or separate sync or raw bayer rgb interface + * and to the input of VPFE through an optional MUX (if more inputs are + * to be interfaced on the EVM). The input data is first passed through + * CCDC (CCD Controller, a.k.a Image Sensor Interface, ISIF). The CCDC + * does very little or no processing on YUV data and does pre-process Raw + * Bayer RGB data through modules such as Defect Pixel Correction (DFC) + * Color Space Conversion (CSC), data gain/offset etc. After this, data + * can be written to SDRAM or can be connected to the image processing + * block such as IPIPE (on DM355 only). + * + * Features supported + * - MMAP IO + * - Capture using TVP5146 over BT.656 + * - support for interfacing decoders using sub device model + * - Work with DM355 or DM6446 CCDC to do Raw Bayer RGB/YUV + * data capture to SDRAM. + * TODO list + * - Support multiple REQBUF after open + * - Support for de-allocating buffers through REQBUF + * - Support for Raw Bayer RGB capture + * - Support for chaining Image Processor + * - Support for static allocation of buffers + * - Support for USERPTR IO + * - Support for STREAMON before QBUF + * - Support for control ioctls + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "ccdc_hw_device.h" + +static int debug; +static u32 numbuffers = 3; +static u32 bufsize = (720 * 576 * 2); + +module_param(numbuffers, uint, S_IRUGO); +module_param(bufsize, uint, S_IRUGO); +module_param(debug, int, 0644); + +MODULE_PARM_DESC(numbuffers, "buffer count (default:3)"); +MODULE_PARM_DESC(bufsize, "buffer size in bytes (default:720 x 576 x 2)"); +MODULE_PARM_DESC(debug, "Debug level 0-1"); + +MODULE_DESCRIPTION("VPFE Video for Linux Capture Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Texas Instruments"); + +/* standard information */ +struct vpfe_standard { + v4l2_std_id std_id; + unsigned int width; + unsigned int height; + struct v4l2_fract pixelaspect; + /* 0 - progressive, 1 - interlaced */ + int frame_format; +}; + +/* ccdc configuration */ +struct ccdc_config { + /* This make sure vpfe is probed and ready to go */ + int vpfe_probed; + /* name of ccdc device */ + char name[32]; + /* for storing mem maps for CCDC */ + int ccdc_addr_size; + void *__iomem ccdc_addr; +}; + +/* data structures */ +static struct vpfe_config_params config_params = { + .min_numbuffers = 3, + .numbuffers = 3, + .min_bufsize = 720 * 480 * 2, + .device_bufsize = 720 * 576 * 2, +}; + +/* ccdc device registered */ +static struct ccdc_hw_device *ccdc_dev; +/* lock for accessing ccdc information */ +static DEFINE_MUTEX(ccdc_lock); +/* ccdc configuration */ +static struct ccdc_config *ccdc_cfg; + +const struct vpfe_standard vpfe_standards[] = { + {V4L2_STD_525_60, 720, 480, {11, 10}, 1}, + {V4L2_STD_625_50, 720, 576, {54, 59}, 1}, +}; + +/* Used when raw Bayer image from ccdc is directly captured to SDRAM */ +static const struct vpfe_pixel_format vpfe_pix_fmts[] = { + { + .fmtdesc = { + .index = 0, + .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, + .description = "Bayer GrRBGb 8bit A-Law compr.", + .pixelformat = V4L2_PIX_FMT_SBGGR8, + }, + .bpp = 1, + }, + { + .fmtdesc = { + .index = 1, + .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, + .description = "Bayer GrRBGb - 16bit", + .pixelformat = V4L2_PIX_FMT_SBGGR16, + }, + .bpp = 2, + }, + { + .fmtdesc = { + .index = 2, + .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, + .description = "Bayer GrRBGb 8bit DPCM compr.", + .pixelformat = V4L2_PIX_FMT_SGRBG10DPCM8, + }, + .bpp = 1, + }, + { + .fmtdesc = { + .index = 3, + .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, + .description = "YCbCr 4:2:2 Interleaved UYVY", + .pixelformat = V4L2_PIX_FMT_UYVY, + }, + .bpp = 2, + }, + { + .fmtdesc = { + .index = 4, + .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, + .description = "YCbCr 4:2:2 Interleaved YUYV", + .pixelformat = V4L2_PIX_FMT_YUYV, + }, + .bpp = 2, + }, + { + .fmtdesc = { + .index = 5, + .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, + .description = "Y/CbCr 4:2:0 - Semi planar", + .pixelformat = V4L2_PIX_FMT_NV12, + }, + .bpp = 1, + }, +}; + +/* + * vpfe_lookup_pix_format() + * lookup an entry in the vpfe pix format table based on pix_format + */ +static const struct vpfe_pixel_format *vpfe_lookup_pix_format(u32 pix_format) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(vpfe_pix_fmts); i++) { + if (pix_format == vpfe_pix_fmts[i].fmtdesc.pixelformat) + return &vpfe_pix_fmts[i]; + } + return NULL; +} + +/* + * vpfe_register_ccdc_device. CCDC module calls this to + * register with vpfe capture + */ +int vpfe_register_ccdc_device(struct ccdc_hw_device *dev) +{ + int ret = 0; + printk(KERN_NOTICE "vpfe_register_ccdc_device: %s\n", dev->name); + + BUG_ON(!dev->hw_ops.open); + BUG_ON(!dev->hw_ops.enable); + BUG_ON(!dev->hw_ops.set_hw_if_params); + BUG_ON(!dev->hw_ops.configure); + BUG_ON(!dev->hw_ops.set_buftype); + BUG_ON(!dev->hw_ops.get_buftype); + BUG_ON(!dev->hw_ops.enum_pix); + BUG_ON(!dev->hw_ops.set_frame_format); + BUG_ON(!dev->hw_ops.get_frame_format); + BUG_ON(!dev->hw_ops.get_pixel_format); + BUG_ON(!dev->hw_ops.set_pixel_format); + BUG_ON(!dev->hw_ops.set_params); + BUG_ON(!dev->hw_ops.set_image_window); + BUG_ON(!dev->hw_ops.get_image_window); + BUG_ON(!dev->hw_ops.get_line_length); + BUG_ON(!dev->hw_ops.setfbaddr); + BUG_ON(!dev->hw_ops.getfid); + + mutex_lock(&ccdc_lock); + if (NULL == ccdc_cfg) { + /* + * TODO. Will this ever happen? if so, we need to fix it. + * Proabably we need to add the request to a linked list and + * walk through it during vpfe probe + */ + printk(KERN_ERR "vpfe capture not initialized\n"); + ret = -1; + goto unlock; + } + + if (strcmp(dev->name, ccdc_cfg->name)) { + /* ignore this ccdc */ + ret = -1; + goto unlock; + } + + if (ccdc_dev) { + printk(KERN_ERR "ccdc already registered\n"); + ret = -1; + goto unlock; + } + + ccdc_dev = dev; + dev->hw_ops.set_ccdc_base(ccdc_cfg->ccdc_addr, + ccdc_cfg->ccdc_addr_size); +unlock: + mutex_unlock(&ccdc_lock); + return ret; +} +EXPORT_SYMBOL(vpfe_register_ccdc_device); + +/* + * vpfe_unregister_ccdc_device. CCDC module calls this to + * unregister with vpfe capture + */ +void vpfe_unregister_ccdc_device(struct ccdc_hw_device *dev) +{ + if (NULL == dev) { + printk(KERN_ERR "invalid ccdc device ptr\n"); + return; + } + + printk(KERN_NOTICE "vpfe_unregister_ccdc_device, dev->name = %s\n", + dev->name); + + if (strcmp(dev->name, ccdc_cfg->name)) { + /* ignore this ccdc */ + return; + } + + mutex_lock(&ccdc_lock); + ccdc_dev = NULL; + mutex_unlock(&ccdc_lock); + return; +} +EXPORT_SYMBOL(vpfe_unregister_ccdc_device); + +/* + * vpfe_get_ccdc_image_format - Get image parameters based on CCDC settings + */ +static int vpfe_get_ccdc_image_format(struct vpfe_device *vpfe_dev, + struct v4l2_format *f) +{ + struct v4l2_rect image_win; + enum ccdc_buftype buf_type; + enum ccdc_frmfmt frm_fmt; + + memset(f, 0, sizeof(*f)); + f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT; + ccdc_dev->hw_ops.get_image_window(&image_win); + f->fmt.pix.width = image_win.width; + f->fmt.pix.height = image_win.height; + f->fmt.pix.bytesperline = ccdc_dev->hw_ops.get_line_length(); + f->fmt.pix.sizeimage = f->fmt.pix.bytesperline * + f->fmt.pix.height; + buf_type = ccdc_dev->hw_ops.get_buftype(); + f->fmt.pix.pixelformat = ccdc_dev->hw_ops.get_pixel_format(); + frm_fmt = ccdc_dev->hw_ops.get_frame_format(); + if (frm_fmt == CCDC_FRMFMT_PROGRESSIVE) + f->fmt.pix.field = V4L2_FIELD_NONE; + else if (frm_fmt == CCDC_FRMFMT_INTERLACED) { + if (buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED) + f->fmt.pix.field = V4L2_FIELD_INTERLACED; + else if (buf_type == CCDC_BUFTYPE_FLD_SEPARATED) + f->fmt.pix.field = V4L2_FIELD_SEQ_TB; + else { + v4l2_err(&vpfe_dev->v4l2_dev, "Invalid buf_type\n"); + return -EINVAL; + } + } else { + v4l2_err(&vpfe_dev->v4l2_dev, "Invalid frm_fmt\n"); + return -EINVAL; + } + return 0; +} + +/* + * vpfe_config_ccdc_image_format() + * For a pix format, configure ccdc to setup the capture + */ +static int vpfe_config_ccdc_image_format(struct vpfe_device *vpfe_dev) +{ + enum ccdc_frmfmt frm_fmt = CCDC_FRMFMT_INTERLACED; + int ret = 0; + + if (ccdc_dev->hw_ops.set_pixel_format( + vpfe_dev->fmt.fmt.pix.pixelformat) < 0) { + v4l2_err(&vpfe_dev->v4l2_dev, + "couldn't set pix format in ccdc\n"); + return -EINVAL; + } + /* configure the image window */ + ccdc_dev->hw_ops.set_image_window(&vpfe_dev->crop); + + switch (vpfe_dev->fmt.fmt.pix.field) { + case V4L2_FIELD_INTERLACED: + /* do nothing, since it is default */ + ret = ccdc_dev->hw_ops.set_buftype( + CCDC_BUFTYPE_FLD_INTERLEAVED); + break; + case V4L2_FIELD_NONE: + frm_fmt = CCDC_FRMFMT_PROGRESSIVE; + /* buffer type only applicable for interlaced scan */ + break; + case V4L2_FIELD_SEQ_TB: + ret = ccdc_dev->hw_ops.set_buftype( + CCDC_BUFTYPE_FLD_SEPARATED); + break; + default: + return -EINVAL; + } + + /* set the frame format */ + if (!ret) + ret = ccdc_dev->hw_ops.set_frame_format(frm_fmt); + return ret; +} +/* + * vpfe_config_image_format() + * For a given standard, this functions sets up the default + * pix format & crop values in the vpfe device and ccdc. It first + * starts with defaults based values from the standard table. + * It then checks if sub device support g_fmt and then override the + * values based on that.Sets crop values to match with scan resolution + * starting at 0,0. It calls vpfe_config_ccdc_image_format() set the + * values in ccdc + */ +static int vpfe_config_image_format(struct vpfe_device *vpfe_dev, + const v4l2_std_id *std_id) +{ + struct vpfe_subdev_info *sdinfo = vpfe_dev->current_subdev; + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(vpfe_standards); i++) { + if (vpfe_standards[i].std_id & *std_id) { + vpfe_dev->std_info.active_pixels = + vpfe_standards[i].width; + vpfe_dev->std_info.active_lines = + vpfe_standards[i].height; + vpfe_dev->std_info.frame_format = + vpfe_standards[i].frame_format; + vpfe_dev->std_index = i; + break; + } + } + + if (i == ARRAY_SIZE(vpfe_standards)) { + v4l2_err(&vpfe_dev->v4l2_dev, "standard not supported\n"); + return -EINVAL; + } + + vpfe_dev->crop.top = 0; + vpfe_dev->crop.left = 0; + vpfe_dev->crop.width = vpfe_dev->std_info.active_pixels; + vpfe_dev->crop.height = vpfe_dev->std_info.active_lines; + vpfe_dev->fmt.fmt.pix.width = vpfe_dev->crop.width; + vpfe_dev->fmt.fmt.pix.height = vpfe_dev->crop.height; + + /* first field and frame format based on standard frame format */ + if (vpfe_dev->std_info.frame_format) { + vpfe_dev->fmt.fmt.pix.field = V4L2_FIELD_INTERLACED; + /* assume V4L2_PIX_FMT_UYVY as default */ + vpfe_dev->fmt.fmt.pix.pixelformat = V4L2_PIX_FMT_UYVY; + } else { + vpfe_dev->fmt.fmt.pix.field = V4L2_FIELD_NONE; + /* assume V4L2_PIX_FMT_SBGGR8 */ + vpfe_dev->fmt.fmt.pix.pixelformat = V4L2_PIX_FMT_SBGGR8; + } + + /* if sub device supports g_fmt, override the defaults */ + ret = v4l2_device_call_until_err(&vpfe_dev->v4l2_dev, + sdinfo->grp_id, video, g_fmt, &vpfe_dev->fmt); + + if (ret && ret != -ENOIOCTLCMD) { + v4l2_err(&vpfe_dev->v4l2_dev, + "error in getting g_fmt from sub device\n"); + return ret; + } + + /* Sets the values in CCDC */ + ret = vpfe_config_ccdc_image_format(vpfe_dev); + if (ret) + return ret; + + /* Update the values of sizeimage and bytesperline */ + if (!ret) { + vpfe_dev->fmt.fmt.pix.bytesperline = + ccdc_dev->hw_ops.get_line_length(); + vpfe_dev->fmt.fmt.pix.sizeimage = + vpfe_dev->fmt.fmt.pix.bytesperline * + vpfe_dev->fmt.fmt.pix.height; + } + return ret; +} + +static int vpfe_initialize_device(struct vpfe_device *vpfe_dev) +{ + int ret = 0; + + /* set first input of current subdevice as the current input */ + vpfe_dev->current_input = 0; + + /* set default standard */ + vpfe_dev->std_index = 0; + + /* Configure the default format information */ + ret = vpfe_config_image_format(vpfe_dev, + &vpfe_standards[vpfe_dev->std_index].std_id); + if (ret) + return ret; + + /* now open the ccdc device to initialize it */ + mutex_lock(&ccdc_lock); + if (NULL == ccdc_dev) { + v4l2_err(&vpfe_dev->v4l2_dev, "ccdc device not registered\n"); + ret = -ENODEV; + goto unlock; + } + + if (!try_module_get(ccdc_dev->owner)) { + v4l2_err(&vpfe_dev->v4l2_dev, "Couldn't lock ccdc module\n"); + ret = -ENODEV; + goto unlock; + } + ret = ccdc_dev->hw_ops.open(vpfe_dev->pdev); + if (!ret) + vpfe_dev->initialized = 1; +unlock: + mutex_unlock(&ccdc_lock); + return ret; +} + +/* + * vpfe_open : It creates object of file handle structure and + * stores it in private_data member of filepointer + */ +static int vpfe_open(struct file *file) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + struct vpfe_fh *fh; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_open\n"); + + if (!vpfe_dev->cfg->num_subdevs) { + v4l2_err(&vpfe_dev->v4l2_dev, "No decoder registered\n"); + return -ENODEV; + } + + /* Allocate memory for the file handle object */ + fh = kmalloc(sizeof(struct vpfe_fh), GFP_KERNEL); + if (NULL == fh) { + v4l2_err(&vpfe_dev->v4l2_dev, + "unable to allocate memory for file handle object\n"); + return -ENOMEM; + } + /* store pointer to fh in private_data member of file */ + file->private_data = fh; + fh->vpfe_dev = vpfe_dev; + mutex_lock(&vpfe_dev->lock); + /* If decoder is not initialized. initialize it */ + if (!vpfe_dev->initialized) { + if (vpfe_initialize_device(vpfe_dev)) { + mutex_unlock(&vpfe_dev->lock); + return -ENODEV; + } + } + /* Increment device usrs counter */ + vpfe_dev->usrs++; + /* Set io_allowed member to false */ + fh->io_allowed = 0; + /* Initialize priority of this instance to default priority */ + fh->prio = V4L2_PRIORITY_UNSET; + v4l2_prio_open(&vpfe_dev->prio, &fh->prio); + mutex_unlock(&vpfe_dev->lock); + return 0; +} + +static void vpfe_schedule_next_buffer(struct vpfe_device *vpfe_dev) +{ + unsigned long addr; + + vpfe_dev->next_frm = list_entry(vpfe_dev->dma_queue.next, + struct videobuf_buffer, queue); + list_del(&vpfe_dev->next_frm->queue); + vpfe_dev->next_frm->state = VIDEOBUF_ACTIVE; + addr = videobuf_to_dma_contig(vpfe_dev->next_frm); + ccdc_dev->hw_ops.setfbaddr(addr); +} + +static void vpfe_process_buffer_complete(struct vpfe_device *vpfe_dev) +{ + struct timeval timevalue; + + do_gettimeofday(&timevalue); + vpfe_dev->cur_frm->ts = timevalue; + vpfe_dev->cur_frm->state = VIDEOBUF_DONE; + vpfe_dev->cur_frm->size = vpfe_dev->fmt.fmt.pix.sizeimage; + wake_up_interruptible(&vpfe_dev->cur_frm->done); + vpfe_dev->cur_frm = vpfe_dev->next_frm; +} + +/* ISR for VINT0*/ +static irqreturn_t vpfe_isr(int irq, void *dev_id) +{ + struct vpfe_device *vpfe_dev = dev_id; + enum v4l2_field field; + unsigned long addr; + int fid; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "\nStarting vpfe_isr...\n"); + field = vpfe_dev->fmt.fmt.pix.field; + + /* if streaming not started, don't do anything */ + if (!vpfe_dev->started) + return IRQ_HANDLED; + + /* only for 6446 this will be applicable */ + if (NULL != ccdc_dev->hw_ops.reset) + ccdc_dev->hw_ops.reset(); + + if (field == V4L2_FIELD_NONE) { + /* handle progressive frame capture */ + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, + "frame format is progressive...\n"); + if (vpfe_dev->cur_frm != vpfe_dev->next_frm) + vpfe_process_buffer_complete(vpfe_dev); + return IRQ_HANDLED; + } + + /* interlaced or TB capture check which field we are in hardware */ + fid = ccdc_dev->hw_ops.getfid(); + + /* switch the software maintained field id */ + vpfe_dev->field_id ^= 1; + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "field id = %x:%x.\n", + fid, vpfe_dev->field_id); + if (fid == vpfe_dev->field_id) { + /* we are in-sync here,continue */ + if (fid == 0) { + /* + * One frame is just being captured. If the next frame + * is available, release the current frame and move on + */ + if (vpfe_dev->cur_frm != vpfe_dev->next_frm) + vpfe_process_buffer_complete(vpfe_dev); + /* + * based on whether the two fields are stored + * interleavely or separately in memory, reconfigure + * the CCDC memory address + */ + if (field == V4L2_FIELD_SEQ_TB) { + addr = + videobuf_to_dma_contig(vpfe_dev->cur_frm); + addr += vpfe_dev->field_off; + ccdc_dev->hw_ops.setfbaddr(addr); + } + return IRQ_HANDLED; + } + /* + * if one field is just being captured configure + * the next frame get the next frame from the empty + * queue if no frame is available hold on to the + * current buffer + */ + spin_lock(&vpfe_dev->dma_queue_lock); + if (!list_empty(&vpfe_dev->dma_queue) && + vpfe_dev->cur_frm == vpfe_dev->next_frm) + vpfe_schedule_next_buffer(vpfe_dev); + spin_unlock(&vpfe_dev->dma_queue_lock); + } else if (fid == 0) { + /* + * out of sync. Recover from any hardware out-of-sync. + * May loose one frame + */ + vpfe_dev->field_id = fid; + } + return IRQ_HANDLED; +} + +/* vdint1_isr - isr handler for VINT1 interrupt */ +static irqreturn_t vdint1_isr(int irq, void *dev_id) +{ + struct vpfe_device *vpfe_dev = dev_id; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "\nInside vdint1_isr...\n"); + + /* if streaming not started, don't do anything */ + if (!vpfe_dev->started) + return IRQ_HANDLED; + + spin_lock(&vpfe_dev->dma_queue_lock); + if ((vpfe_dev->fmt.fmt.pix.field == V4L2_FIELD_NONE) && + !list_empty(&vpfe_dev->dma_queue) && + vpfe_dev->cur_frm == vpfe_dev->next_frm) + vpfe_schedule_next_buffer(vpfe_dev); + spin_unlock(&vpfe_dev->dma_queue_lock); + return IRQ_HANDLED; +} + +static void vpfe_detach_irq(struct vpfe_device *vpfe_dev) +{ + enum ccdc_frmfmt frame_format; + + frame_format = ccdc_dev->hw_ops.get_frame_format(); + if (frame_format == CCDC_FRMFMT_PROGRESSIVE) + free_irq(IRQ_VDINT1, vpfe_dev); +} + +static int vpfe_attach_irq(struct vpfe_device *vpfe_dev) +{ + enum ccdc_frmfmt frame_format; + + frame_format = ccdc_dev->hw_ops.get_frame_format(); + if (frame_format == CCDC_FRMFMT_PROGRESSIVE) { + return request_irq(vpfe_dev->ccdc_irq1, vdint1_isr, + IRQF_DISABLED, "vpfe_capture1", + vpfe_dev); + } + return 0; +} + +/* vpfe_stop_ccdc_capture: stop streaming in ccdc/isif */ +static void vpfe_stop_ccdc_capture(struct vpfe_device *vpfe_dev) +{ + vpfe_dev->started = 0; + ccdc_dev->hw_ops.enable(0); + if (ccdc_dev->hw_ops.enable_out_to_sdram) + ccdc_dev->hw_ops.enable_out_to_sdram(0); +} + +/* + * vpfe_release : This function deletes buffer queue, frees the + * buffers and the vpfe file handle + */ +static int vpfe_release(struct file *file) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + struct vpfe_fh *fh = file->private_data; + struct vpfe_subdev_info *sdinfo; + int ret; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_release\n"); + + /* Get the device lock */ + mutex_lock(&vpfe_dev->lock); + /* if this instance is doing IO */ + if (fh->io_allowed) { + if (vpfe_dev->started) { + sdinfo = vpfe_dev->current_subdev; + ret = v4l2_device_call_until_err(&vpfe_dev->v4l2_dev, + sdinfo->grp_id, + video, s_stream, 0); + if (ret && (ret != -ENOIOCTLCMD)) + v4l2_err(&vpfe_dev->v4l2_dev, + "stream off failed in subdev\n"); + vpfe_stop_ccdc_capture(vpfe_dev); + vpfe_detach_irq(vpfe_dev); + videobuf_streamoff(&vpfe_dev->buffer_queue); + } + vpfe_dev->io_usrs = 0; + vpfe_dev->numbuffers = config_params.numbuffers; + } + + /* Decrement device usrs counter */ + vpfe_dev->usrs--; + /* Close the priority */ + v4l2_prio_close(&vpfe_dev->prio, &fh->prio); + /* If this is the last file handle */ + if (!vpfe_dev->usrs) { + vpfe_dev->initialized = 0; + if (ccdc_dev->hw_ops.close) + ccdc_dev->hw_ops.close(vpfe_dev->pdev); + module_put(ccdc_dev->owner); + } + mutex_unlock(&vpfe_dev->lock); + file->private_data = NULL; + /* Free memory allocated to file handle object */ + kfree(fh); + return 0; +} + +/* + * vpfe_mmap : It is used to map kernel space buffers + * into user spaces + */ +static int vpfe_mmap(struct file *file, struct vm_area_struct *vma) +{ + /* Get the device object and file handle object */ + struct vpfe_device *vpfe_dev = video_drvdata(file); + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_mmap\n"); + + return videobuf_mmap_mapper(&vpfe_dev->buffer_queue, vma); +} + +/* + * vpfe_poll: It is used for select/poll system call + */ +static unsigned int vpfe_poll(struct file *file, poll_table *wait) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_poll\n"); + + if (vpfe_dev->started) + return videobuf_poll_stream(file, + &vpfe_dev->buffer_queue, wait); + return 0; +} + +/* vpfe capture driver file operations */ +static const struct v4l2_file_operations vpfe_fops = { + .owner = THIS_MODULE, + .open = vpfe_open, + .release = vpfe_release, + .unlocked_ioctl = video_ioctl2, + .mmap = vpfe_mmap, + .poll = vpfe_poll +}; + +/* + * vpfe_check_format() + * This function adjust the input pixel format as per hardware + * capabilities and update the same in pixfmt. + * Following algorithm used :- + * + * If given pixformat is not in the vpfe list of pix formats or not + * supported by the hardware, current value of pixformat in the device + * is used + * If given field is not supported, then current field is used. If field + * is different from current, then it is matched with that from sub device. + * Minimum height is 2 lines for interlaced or tb field and 1 line for + * progressive. Maximum height is clamped to active active lines of scan + * Minimum width is 32 bytes in memory and width is clamped to active + * pixels of scan. + * bytesperline is a multiple of 32. + */ +static const struct vpfe_pixel_format * + vpfe_check_format(struct vpfe_device *vpfe_dev, + struct v4l2_pix_format *pixfmt) +{ + u32 min_height = 1, min_width = 32, max_width, max_height; + const struct vpfe_pixel_format *vpfe_pix_fmt; + u32 pix; + int temp, found; + + vpfe_pix_fmt = vpfe_lookup_pix_format(pixfmt->pixelformat); + if (NULL == vpfe_pix_fmt) { + /* + * use current pixel format in the vpfe device. We + * will find this pix format in the table + */ + pixfmt->pixelformat = vpfe_dev->fmt.fmt.pix.pixelformat; + vpfe_pix_fmt = vpfe_lookup_pix_format(pixfmt->pixelformat); + } + + /* check if hw supports it */ + temp = 0; + found = 0; + while (ccdc_dev->hw_ops.enum_pix(&pix, temp) >= 0) { + if (vpfe_pix_fmt->fmtdesc.pixelformat == pix) { + found = 1; + break; + } + temp++; + } + + if (!found) { + /* use current pixel format */ + pixfmt->pixelformat = vpfe_dev->fmt.fmt.pix.pixelformat; + /* + * Since this is currently used in the vpfe device, we + * will find this pix format in the table + */ + vpfe_pix_fmt = vpfe_lookup_pix_format(pixfmt->pixelformat); + } + + /* check what field format is supported */ + if (pixfmt->field == V4L2_FIELD_ANY) { + /* if field is any, use current value as default */ + pixfmt->field = vpfe_dev->fmt.fmt.pix.field; + } + + /* + * if field is not same as current field in the vpfe device + * try matching the field with the sub device field + */ + if (vpfe_dev->fmt.fmt.pix.field != pixfmt->field) { + /* + * If field value is not in the supported fields, use current + * field used in the device as default + */ + switch (pixfmt->field) { + case V4L2_FIELD_INTERLACED: + case V4L2_FIELD_SEQ_TB: + /* if sub device is supporting progressive, use that */ + if (!vpfe_dev->std_info.frame_format) + pixfmt->field = V4L2_FIELD_NONE; + break; + case V4L2_FIELD_NONE: + if (vpfe_dev->std_info.frame_format) + pixfmt->field = V4L2_FIELD_INTERLACED; + break; + + default: + /* use current field as default */ + pixfmt->field = vpfe_dev->fmt.fmt.pix.field; + break; + } + } + + /* Now adjust image resolutions supported */ + if (pixfmt->field == V4L2_FIELD_INTERLACED || + pixfmt->field == V4L2_FIELD_SEQ_TB) + min_height = 2; + + max_width = vpfe_dev->std_info.active_pixels; + max_height = vpfe_dev->std_info.active_lines; + min_width /= vpfe_pix_fmt->bpp; + + v4l2_info(&vpfe_dev->v4l2_dev, "width = %d, height = %d, bpp = %d\n", + pixfmt->width, pixfmt->height, vpfe_pix_fmt->bpp); + + pixfmt->width = clamp((pixfmt->width), min_width, max_width); + pixfmt->height = clamp((pixfmt->height), min_height, max_height); + + /* If interlaced, adjust height to be a multiple of 2 */ + if (pixfmt->field == V4L2_FIELD_INTERLACED) + pixfmt->height &= (~1); + /* + * recalculate bytesperline and sizeimage since width + * and height might have changed + */ + pixfmt->bytesperline = (((pixfmt->width * vpfe_pix_fmt->bpp) + 31) + & ~31); + if (pixfmt->pixelformat == V4L2_PIX_FMT_NV12) + pixfmt->sizeimage = + pixfmt->bytesperline * pixfmt->height + + ((pixfmt->bytesperline * pixfmt->height) >> 1); + else + pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height; + + v4l2_info(&vpfe_dev->v4l2_dev, "adjusted width = %d, height =" + " %d, bpp = %d, bytesperline = %d, sizeimage = %d\n", + pixfmt->width, pixfmt->height, vpfe_pix_fmt->bpp, + pixfmt->bytesperline, pixfmt->sizeimage); + return vpfe_pix_fmt; +} + +static int vpfe_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_querycap\n"); + + cap->version = VPFE_CAPTURE_VERSION_CODE; + cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + strlcpy(cap->driver, CAPTURE_DRV_NAME, sizeof(cap->driver)); + strlcpy(cap->bus_info, "VPFE", sizeof(cap->bus_info)); + strlcpy(cap->card, vpfe_dev->cfg->card_name, sizeof(cap->card)); + return 0; +} + +static int vpfe_g_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *fmt) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + int ret = 0; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_g_fmt_vid_cap\n"); + /* Fill in the information about format */ + *fmt = vpfe_dev->fmt; + return ret; +} + +static int vpfe_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *fmt) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + const struct vpfe_pixel_format *pix_fmt; + int temp_index; + u32 pix; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_enum_fmt_vid_cap\n"); + + if (ccdc_dev->hw_ops.enum_pix(&pix, fmt->index) < 0) + return -EINVAL; + + /* Fill in the information about format */ + pix_fmt = vpfe_lookup_pix_format(pix); + if (NULL != pix_fmt) { + temp_index = fmt->index; + *fmt = pix_fmt->fmtdesc; + fmt->index = temp_index; + return 0; + } + return -EINVAL; +} + +static int vpfe_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *fmt) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + const struct vpfe_pixel_format *pix_fmts; + int ret = 0; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_s_fmt_vid_cap\n"); + + /* If streaming is started, return error */ + if (vpfe_dev->started) { + v4l2_err(&vpfe_dev->v4l2_dev, "Streaming is started\n"); + return -EBUSY; + } + + /* Check for valid frame format */ + pix_fmts = vpfe_check_format(vpfe_dev, &fmt->fmt.pix); + + if (NULL == pix_fmts) + return -EINVAL; + + /* store the pixel format in the device object */ + ret = mutex_lock_interruptible(&vpfe_dev->lock); + if (ret) + return ret; + + /* First detach any IRQ if currently attached */ + vpfe_detach_irq(vpfe_dev); + vpfe_dev->fmt = *fmt; + /* set image capture parameters in the ccdc */ + ret = vpfe_config_ccdc_image_format(vpfe_dev); + mutex_unlock(&vpfe_dev->lock); + return ret; +} + +static int vpfe_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + const struct vpfe_pixel_format *pix_fmts; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_try_fmt_vid_cap\n"); + + pix_fmts = vpfe_check_format(vpfe_dev, &f->fmt.pix); + if (NULL == pix_fmts) + return -EINVAL; + return 0; +} + +/* + * vpfe_get_subdev_input_index - Get subdev index and subdev input index for a + * given app input index + */ +static int vpfe_get_subdev_input_index(struct vpfe_device *vpfe_dev, + int *subdev_index, + int *subdev_input_index, + int app_input_index) +{ + struct vpfe_config *cfg = vpfe_dev->cfg; + struct vpfe_subdev_info *sdinfo; + int i, j = 0; + + for (i = 0; i < cfg->num_subdevs; i++) { + sdinfo = &cfg->sub_devs[i]; + if (app_input_index < (j + sdinfo->num_inputs)) { + *subdev_index = i; + *subdev_input_index = app_input_index - j; + return 0; + } + j += sdinfo->num_inputs; + } + return -EINVAL; +} + +/* + * vpfe_get_app_input - Get app input index for a given subdev input index + * driver stores the input index of the current sub device and translate it + * when application request the current input + */ +static int vpfe_get_app_input_index(struct vpfe_device *vpfe_dev, + int *app_input_index) +{ + struct vpfe_config *cfg = vpfe_dev->cfg; + struct vpfe_subdev_info *sdinfo; + int i, j = 0; + + for (i = 0; i < cfg->num_subdevs; i++) { + sdinfo = &cfg->sub_devs[i]; + if (!strcmp(sdinfo->name, vpfe_dev->current_subdev->name)) { + if (vpfe_dev->current_input >= sdinfo->num_inputs) + return -1; + *app_input_index = j + vpfe_dev->current_input; + return 0; + } + j += sdinfo->num_inputs; + } + return -EINVAL; +} + +static int vpfe_enum_input(struct file *file, void *priv, + struct v4l2_input *inp) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + struct vpfe_subdev_info *sdinfo; + int subdev, index ; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_enum_input\n"); + + if (vpfe_get_subdev_input_index(vpfe_dev, + &subdev, + &index, + inp->index) < 0) { + v4l2_err(&vpfe_dev->v4l2_dev, "input information not found" + " for the subdev\n"); + return -EINVAL; + } + sdinfo = &vpfe_dev->cfg->sub_devs[subdev]; + memcpy(inp, &sdinfo->inputs[index], sizeof(struct v4l2_input)); + return 0; +} + +static int vpfe_g_input(struct file *file, void *priv, unsigned int *index) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_g_input\n"); + + return vpfe_get_app_input_index(vpfe_dev, index); +} + + +static int vpfe_s_input(struct file *file, void *priv, unsigned int index) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + struct vpfe_subdev_info *sdinfo; + int subdev_index, inp_index; + struct vpfe_route *route; + u32 input = 0, output = 0; + int ret = -EINVAL; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_s_input\n"); + + ret = mutex_lock_interruptible(&vpfe_dev->lock); + if (ret) + return ret; + + /* + * If streaming is started return device busy + * error + */ + if (vpfe_dev->started) { + v4l2_err(&vpfe_dev->v4l2_dev, "Streaming is on\n"); + ret = -EBUSY; + goto unlock_out; + } + + if (vpfe_get_subdev_input_index(vpfe_dev, + &subdev_index, + &inp_index, + index) < 0) { + v4l2_err(&vpfe_dev->v4l2_dev, "invalid input index\n"); + goto unlock_out; + } + + sdinfo = &vpfe_dev->cfg->sub_devs[subdev_index]; + route = &sdinfo->routes[inp_index]; + if (route && sdinfo->can_route) { + input = route->input; + output = route->output; + } + + ret = v4l2_device_call_until_err(&vpfe_dev->v4l2_dev, sdinfo->grp_id, + video, s_routing, input, output, 0); + + if (ret) { + v4l2_err(&vpfe_dev->v4l2_dev, + "vpfe_doioctl:error in setting input in decoder\n"); + ret = -EINVAL; + goto unlock_out; + } + vpfe_dev->current_subdev = sdinfo; + vpfe_dev->current_input = index; + vpfe_dev->std_index = 0; + + /* set the bus/interface parameter for the sub device in ccdc */ + ret = ccdc_dev->hw_ops.set_hw_if_params(&sdinfo->ccdc_if_params); + if (ret) + goto unlock_out; + + /* set the default image parameters in the device */ + ret = vpfe_config_image_format(vpfe_dev, + &vpfe_standards[vpfe_dev->std_index].std_id); +unlock_out: + mutex_unlock(&vpfe_dev->lock); + return ret; +} + +static int vpfe_querystd(struct file *file, void *priv, v4l2_std_id *std_id) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + struct vpfe_subdev_info *sdinfo; + int ret = 0; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_querystd\n"); + + ret = mutex_lock_interruptible(&vpfe_dev->lock); + sdinfo = vpfe_dev->current_subdev; + if (ret) + return ret; + /* Call querystd function of decoder device */ + ret = v4l2_device_call_until_err(&vpfe_dev->v4l2_dev, sdinfo->grp_id, + video, querystd, std_id); + mutex_unlock(&vpfe_dev->lock); + return ret; +} + +static int vpfe_s_std(struct file *file, void *priv, v4l2_std_id *std_id) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + struct vpfe_subdev_info *sdinfo; + int ret = 0; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_s_std\n"); + + /* Call decoder driver function to set the standard */ + ret = mutex_lock_interruptible(&vpfe_dev->lock); + if (ret) + return ret; + + sdinfo = vpfe_dev->current_subdev; + /* If streaming is started, return device busy error */ + if (vpfe_dev->started) { + v4l2_err(&vpfe_dev->v4l2_dev, "streaming is started\n"); + ret = -EBUSY; + goto unlock_out; + } + + ret = v4l2_device_call_until_err(&vpfe_dev->v4l2_dev, sdinfo->grp_id, + core, s_std, *std_id); + if (ret < 0) { + v4l2_err(&vpfe_dev->v4l2_dev, "Failed to set standard\n"); + goto unlock_out; + } + ret = vpfe_config_image_format(vpfe_dev, std_id); + +unlock_out: + mutex_unlock(&vpfe_dev->lock); + return ret; +} + +static int vpfe_g_std(struct file *file, void *priv, v4l2_std_id *std_id) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_g_std\n"); + + *std_id = vpfe_standards[vpfe_dev->std_index].std_id; + return 0; +} +/* + * Videobuf operations + */ +static int vpfe_videobuf_setup(struct videobuf_queue *vq, + unsigned int *count, + unsigned int *size) +{ + struct vpfe_fh *fh = vq->priv_data; + struct vpfe_device *vpfe_dev = fh->vpfe_dev; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_buffer_setup\n"); + *size = config_params.device_bufsize; + + if (*count < config_params.min_numbuffers) + *count = config_params.min_numbuffers; + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, + "count=%d, size=%d\n", *count, *size); + return 0; +} + +static int vpfe_videobuf_prepare(struct videobuf_queue *vq, + struct videobuf_buffer *vb, + enum v4l2_field field) +{ + struct vpfe_fh *fh = vq->priv_data; + struct vpfe_device *vpfe_dev = fh->vpfe_dev; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_buffer_prepare\n"); + + /* If buffer is not initialized, initialize it */ + if (VIDEOBUF_NEEDS_INIT == vb->state) { + vb->width = vpfe_dev->fmt.fmt.pix.width; + vb->height = vpfe_dev->fmt.fmt.pix.height; + vb->size = vpfe_dev->fmt.fmt.pix.sizeimage; + vb->field = field; + } + vb->state = VIDEOBUF_PREPARED; + return 0; +} + +static void vpfe_videobuf_queue(struct videobuf_queue *vq, + struct videobuf_buffer *vb) +{ + /* Get the file handle object and device object */ + struct vpfe_fh *fh = vq->priv_data; + struct vpfe_device *vpfe_dev = fh->vpfe_dev; + unsigned long flags; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_buffer_queue\n"); + + /* add the buffer to the DMA queue */ + spin_lock_irqsave(&vpfe_dev->dma_queue_lock, flags); + list_add_tail(&vb->queue, &vpfe_dev->dma_queue); + spin_unlock_irqrestore(&vpfe_dev->dma_queue_lock, flags); + + /* Change state of the buffer */ + vb->state = VIDEOBUF_QUEUED; +} + +static void vpfe_videobuf_release(struct videobuf_queue *vq, + struct videobuf_buffer *vb) +{ + struct vpfe_fh *fh = vq->priv_data; + struct vpfe_device *vpfe_dev = fh->vpfe_dev; + unsigned long flags; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_videobuf_release\n"); + + /* + * We need to flush the buffer from the dma queue since + * they are de-allocated + */ + spin_lock_irqsave(&vpfe_dev->dma_queue_lock, flags); + INIT_LIST_HEAD(&vpfe_dev->dma_queue); + spin_unlock_irqrestore(&vpfe_dev->dma_queue_lock, flags); + videobuf_dma_contig_free(vq, vb); + vb->state = VIDEOBUF_NEEDS_INIT; +} + +static struct videobuf_queue_ops vpfe_videobuf_qops = { + .buf_setup = vpfe_videobuf_setup, + .buf_prepare = vpfe_videobuf_prepare, + .buf_queue = vpfe_videobuf_queue, + .buf_release = vpfe_videobuf_release, +}; + +/* + * vpfe_reqbufs. currently support REQBUF only once opening + * the device. + */ +static int vpfe_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *req_buf) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + struct vpfe_fh *fh = file->private_data; + int ret = 0; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_reqbufs\n"); + + if (V4L2_BUF_TYPE_VIDEO_CAPTURE != req_buf->type) { + v4l2_err(&vpfe_dev->v4l2_dev, "Invalid buffer type\n"); + return -EINVAL; + } + + if (V4L2_MEMORY_USERPTR == req_buf->memory) { + /* we don't support user ptr IO */ + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_reqbufs:" + " USERPTR IO not supported\n"); + return -EINVAL; + } + + ret = mutex_lock_interruptible(&vpfe_dev->lock); + if (ret) + return ret; + + if (vpfe_dev->io_usrs != 0) { + v4l2_err(&vpfe_dev->v4l2_dev, "Only one IO user allowed\n"); + ret = -EBUSY; + goto unlock_out; + } + + vpfe_dev->memory = req_buf->memory; + videobuf_queue_dma_contig_init(&vpfe_dev->buffer_queue, + &vpfe_videobuf_qops, + NULL, + &vpfe_dev->irqlock, + req_buf->type, + vpfe_dev->fmt.fmt.pix.field, + sizeof(struct videobuf_buffer), + fh); + + fh->io_allowed = 1; + vpfe_dev->io_usrs = 1; + INIT_LIST_HEAD(&vpfe_dev->dma_queue); + ret = videobuf_reqbufs(&vpfe_dev->buffer_queue, req_buf); +unlock_out: + mutex_unlock(&vpfe_dev->lock); + return ret; +} + +static int vpfe_querybuf(struct file *file, void *priv, + struct v4l2_buffer *buf) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_querybuf\n"); + + if (V4L2_BUF_TYPE_VIDEO_CAPTURE != buf->type) { + v4l2_err(&vpfe_dev->v4l2_dev, "Invalid buf type\n"); + return -EINVAL; + } + + if (vpfe_dev->memory != V4L2_MEMORY_MMAP) { + v4l2_err(&vpfe_dev->v4l2_dev, "Invalid memory\n"); + return -EINVAL; + } + /* Call videobuf_querybuf to get information */ + return videobuf_querybuf(&vpfe_dev->buffer_queue, buf); +} + +static int vpfe_qbuf(struct file *file, void *priv, + struct v4l2_buffer *p) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + struct vpfe_fh *fh = file->private_data; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_qbuf\n"); + + if (V4L2_BUF_TYPE_VIDEO_CAPTURE != p->type) { + v4l2_err(&vpfe_dev->v4l2_dev, "Invalid buf type\n"); + return -EINVAL; + } + + /* + * If this file handle is not allowed to do IO, + * return error + */ + if (!fh->io_allowed) { + v4l2_err(&vpfe_dev->v4l2_dev, "fh->io_allowed\n"); + return -EACCES; + } + return videobuf_qbuf(&vpfe_dev->buffer_queue, p); +} + +static int vpfe_dqbuf(struct file *file, void *priv, + struct v4l2_buffer *buf) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_dqbuf\n"); + + if (V4L2_BUF_TYPE_VIDEO_CAPTURE != buf->type) { + v4l2_err(&vpfe_dev->v4l2_dev, "Invalid buf type\n"); + return -EINVAL; + } + return videobuf_dqbuf(&vpfe_dev->buffer_queue, + buf, file->f_flags & O_NONBLOCK); +} + +/* + * vpfe_calculate_offsets : This function calculates buffers offset + * for top and bottom field + */ +static void vpfe_calculate_offsets(struct vpfe_device *vpfe_dev) +{ + struct v4l2_rect image_win; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_calculate_offsets\n"); + + ccdc_dev->hw_ops.get_image_window(&image_win); + vpfe_dev->field_off = image_win.height * image_win.width; +} + +/* vpfe_start_ccdc_capture: start streaming in ccdc/isif */ +static void vpfe_start_ccdc_capture(struct vpfe_device *vpfe_dev) +{ + ccdc_dev->hw_ops.enable(1); + if (ccdc_dev->hw_ops.enable_out_to_sdram) + ccdc_dev->hw_ops.enable_out_to_sdram(1); + vpfe_dev->started = 1; +} + +/* + * vpfe_streamon. Assume the DMA queue is not empty. + * application is expected to call QBUF before calling + * this ioctl. If not, driver returns error + */ +static int vpfe_streamon(struct file *file, void *priv, + enum v4l2_buf_type buf_type) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + struct vpfe_fh *fh = file->private_data; + struct vpfe_subdev_info *sdinfo; + unsigned long addr; + int ret = 0; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_streamon\n"); + + if (V4L2_BUF_TYPE_VIDEO_CAPTURE != buf_type) { + v4l2_err(&vpfe_dev->v4l2_dev, "Invalid buf type\n"); + return -EINVAL; + } + + /* If file handle is not allowed IO, return error */ + if (!fh->io_allowed) { + v4l2_err(&vpfe_dev->v4l2_dev, "fh->io_allowed\n"); + return -EACCES; + } + + sdinfo = vpfe_dev->current_subdev; + ret = v4l2_device_call_until_err(&vpfe_dev->v4l2_dev, sdinfo->grp_id, + video, s_stream, 1); + + if (ret && (ret != -ENOIOCTLCMD)) { + v4l2_err(&vpfe_dev->v4l2_dev, "stream on failed in subdev\n"); + return -EINVAL; + } + + /* If buffer queue is empty, return error */ + if (list_empty(&vpfe_dev->buffer_queue.stream)) { + v4l2_err(&vpfe_dev->v4l2_dev, "buffer queue is empty\n"); + return -EIO; + } + + /* Call videobuf_streamon to start streaming * in videobuf */ + ret = videobuf_streamon(&vpfe_dev->buffer_queue); + if (ret) + return ret; + + + ret = mutex_lock_interruptible(&vpfe_dev->lock); + if (ret) + goto streamoff; + /* Get the next frame from the buffer queue */ + vpfe_dev->next_frm = list_entry(vpfe_dev->dma_queue.next, + struct videobuf_buffer, queue); + vpfe_dev->cur_frm = vpfe_dev->next_frm; + /* Remove buffer from the buffer queue */ + list_del(&vpfe_dev->cur_frm->queue); + /* Mark state of the current frame to active */ + vpfe_dev->cur_frm->state = VIDEOBUF_ACTIVE; + /* Initialize field_id and started member */ + vpfe_dev->field_id = 0; + addr = videobuf_to_dma_contig(vpfe_dev->cur_frm); + + /* Calculate field offset */ + vpfe_calculate_offsets(vpfe_dev); + + if (vpfe_attach_irq(vpfe_dev) < 0) { + v4l2_err(&vpfe_dev->v4l2_dev, + "Error in attaching interrupt handle\n"); + ret = -EFAULT; + goto unlock_out; + } + if (ccdc_dev->hw_ops.configure() < 0) { + v4l2_err(&vpfe_dev->v4l2_dev, + "Error in configuring ccdc\n"); + ret = -EINVAL; + goto unlock_out; + } + ccdc_dev->hw_ops.setfbaddr((unsigned long)(addr)); + vpfe_start_ccdc_capture(vpfe_dev); + mutex_unlock(&vpfe_dev->lock); + return ret; +unlock_out: + mutex_unlock(&vpfe_dev->lock); +streamoff: + ret = videobuf_streamoff(&vpfe_dev->buffer_queue); + return ret; +} + +static int vpfe_streamoff(struct file *file, void *priv, + enum v4l2_buf_type buf_type) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + struct vpfe_fh *fh = file->private_data; + struct vpfe_subdev_info *sdinfo; + int ret = 0; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_streamoff\n"); + + if (V4L2_BUF_TYPE_VIDEO_CAPTURE != buf_type) { + v4l2_err(&vpfe_dev->v4l2_dev, "Invalid buf type\n"); + return -EINVAL; + } + + /* If io is allowed for this file handle, return error */ + if (!fh->io_allowed) { + v4l2_err(&vpfe_dev->v4l2_dev, "fh->io_allowed\n"); + return -EACCES; + } + + /* If streaming is not started, return error */ + if (!vpfe_dev->started) { + v4l2_err(&vpfe_dev->v4l2_dev, "device started\n"); + return -EINVAL; + } + + ret = mutex_lock_interruptible(&vpfe_dev->lock); + if (ret) + return ret; + + vpfe_stop_ccdc_capture(vpfe_dev); + vpfe_detach_irq(vpfe_dev); + + sdinfo = vpfe_dev->current_subdev; + ret = v4l2_device_call_until_err(&vpfe_dev->v4l2_dev, sdinfo->grp_id, + video, s_stream, 0); + + if (ret && (ret != -ENOIOCTLCMD)) + v4l2_err(&vpfe_dev->v4l2_dev, "stream off failed in subdev\n"); + ret = videobuf_streamoff(&vpfe_dev->buffer_queue); + mutex_unlock(&vpfe_dev->lock); + return ret; +} + +static int vpfe_cropcap(struct file *file, void *priv, + struct v4l2_cropcap *crop) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_cropcap\n"); + + if (vpfe_dev->std_index > ARRAY_SIZE(vpfe_standards)) + return -EINVAL; + + memset(crop, 0, sizeof(struct v4l2_cropcap)); + crop->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + crop->bounds.width = crop->defrect.width = + vpfe_standards[vpfe_dev->std_index].width; + crop->bounds.height = crop->defrect.height = + vpfe_standards[vpfe_dev->std_index].height; + crop->pixelaspect = vpfe_standards[vpfe_dev->std_index].pixelaspect; + return 0; +} + +static int vpfe_g_crop(struct file *file, void *priv, + struct v4l2_crop *crop) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_g_crop\n"); + + crop->c = vpfe_dev->crop; + return 0; +} + +static int vpfe_s_crop(struct file *file, void *priv, + struct v4l2_crop *crop) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + int ret = 0; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_s_crop\n"); + + if (vpfe_dev->started) { + /* make sure streaming is not started */ + v4l2_err(&vpfe_dev->v4l2_dev, + "Cannot change crop when streaming is ON\n"); + return -EBUSY; + } + + ret = mutex_lock_interruptible(&vpfe_dev->lock); + if (ret) + return ret; + + if (crop->c.top < 0 || crop->c.left < 0) { + v4l2_err(&vpfe_dev->v4l2_dev, + "doesn't support negative values for top & left\n"); + ret = -EINVAL; + goto unlock_out; + } + + /* adjust the width to 16 pixel boundry */ + crop->c.width = ((crop->c.width + 15) & ~0xf); + + /* make sure parameters are valid */ + if ((crop->c.left + crop->c.width > + vpfe_dev->std_info.active_pixels) || + (crop->c.top + crop->c.height > + vpfe_dev->std_info.active_lines)) { + v4l2_err(&vpfe_dev->v4l2_dev, "Error in S_CROP params\n"); + ret = -EINVAL; + goto unlock_out; + } + ccdc_dev->hw_ops.set_image_window(&crop->c); + vpfe_dev->fmt.fmt.pix.width = crop->c.width; + vpfe_dev->fmt.fmt.pix.height = crop->c.height; + vpfe_dev->fmt.fmt.pix.bytesperline = + ccdc_dev->hw_ops.get_line_length(); + vpfe_dev->fmt.fmt.pix.sizeimage = + vpfe_dev->fmt.fmt.pix.bytesperline * + vpfe_dev->fmt.fmt.pix.height; + vpfe_dev->crop = crop->c; +unlock_out: + mutex_unlock(&vpfe_dev->lock); + return ret; +} + + +static long vpfe_param_handler(struct file *file, void *priv, + int cmd, void *param) +{ + struct vpfe_device *vpfe_dev = video_drvdata(file); + int ret = 0; + + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_param_handler\n"); + + if (vpfe_dev->started) { + /* only allowed if streaming is not started */ + v4l2_err(&vpfe_dev->v4l2_dev, "device already started\n"); + return -EBUSY; + } + + ret = mutex_lock_interruptible(&vpfe_dev->lock); + if (ret) + return ret; + + switch (cmd) { + case VPFE_CMD_S_CCDC_RAW_PARAMS: + v4l2_warn(&vpfe_dev->v4l2_dev, + "VPFE_CMD_S_CCDC_RAW_PARAMS: experimental ioctl\n"); + ret = ccdc_dev->hw_ops.set_params(param); + if (ret) { + v4l2_err(&vpfe_dev->v4l2_dev, + "Error in setting parameters in CCDC\n"); + goto unlock_out; + } + if (vpfe_get_ccdc_image_format(vpfe_dev, &vpfe_dev->fmt) < 0) { + v4l2_err(&vpfe_dev->v4l2_dev, + "Invalid image format at CCDC\n"); + goto unlock_out; + } + break; + default: + ret = -EINVAL; + } +unlock_out: + mutex_unlock(&vpfe_dev->lock); + return ret; +} + + +/* vpfe capture ioctl operations */ +static const struct v4l2_ioctl_ops vpfe_ioctl_ops = { + .vidioc_querycap = vpfe_querycap, + .vidioc_g_fmt_vid_cap = vpfe_g_fmt_vid_cap, + .vidioc_enum_fmt_vid_cap = vpfe_enum_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vpfe_s_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vpfe_try_fmt_vid_cap, + .vidioc_enum_input = vpfe_enum_input, + .vidioc_g_input = vpfe_g_input, + .vidioc_s_input = vpfe_s_input, + .vidioc_querystd = vpfe_querystd, + .vidioc_s_std = vpfe_s_std, + .vidioc_g_std = vpfe_g_std, + .vidioc_reqbufs = vpfe_reqbufs, + .vidioc_querybuf = vpfe_querybuf, + .vidioc_qbuf = vpfe_qbuf, + .vidioc_dqbuf = vpfe_dqbuf, + .vidioc_streamon = vpfe_streamon, + .vidioc_streamoff = vpfe_streamoff, + .vidioc_cropcap = vpfe_cropcap, + .vidioc_g_crop = vpfe_g_crop, + .vidioc_s_crop = vpfe_s_crop, + .vidioc_default = vpfe_param_handler, +}; + +static struct vpfe_device *vpfe_initialize(void) +{ + struct vpfe_device *vpfe_dev; + + /* Default number of buffers should be 3 */ + if ((numbuffers > 0) && + (numbuffers < config_params.min_numbuffers)) + numbuffers = config_params.min_numbuffers; + + /* + * Set buffer size to min buffers size if invalid buffer size is + * given + */ + if (bufsize < config_params.min_bufsize) + bufsize = config_params.min_bufsize; + + config_params.numbuffers = numbuffers; + + if (numbuffers) + config_params.device_bufsize = bufsize; + + /* Allocate memory for device objects */ + vpfe_dev = kzalloc(sizeof(*vpfe_dev), GFP_KERNEL); + + return vpfe_dev; +} + +static void vpfe_disable_clock(struct vpfe_device *vpfe_dev) +{ + struct vpfe_config *vpfe_cfg = vpfe_dev->cfg; + + clk_disable(vpfe_cfg->vpssclk); + clk_put(vpfe_cfg->vpssclk); + clk_disable(vpfe_cfg->slaveclk); + clk_put(vpfe_cfg->slaveclk); + v4l2_info(vpfe_dev->pdev->driver, + "vpfe vpss master & slave clocks disabled\n"); +} + +static int vpfe_enable_clock(struct vpfe_device *vpfe_dev) +{ + struct vpfe_config *vpfe_cfg = vpfe_dev->cfg; + int ret = -ENOENT; + + vpfe_cfg->vpssclk = clk_get(vpfe_dev->pdev, "vpss_master"); + if (NULL == vpfe_cfg->vpssclk) { + v4l2_err(vpfe_dev->pdev->driver, "No clock defined for" + "vpss_master\n"); + return ret; + } + + if (clk_enable(vpfe_cfg->vpssclk)) { + v4l2_err(vpfe_dev->pdev->driver, + "vpfe vpss master clock not enabled\n"); + goto out; + } + v4l2_info(vpfe_dev->pdev->driver, + "vpfe vpss master clock enabled\n"); + + vpfe_cfg->slaveclk = clk_get(vpfe_dev->pdev, "vpss_slave"); + if (NULL == vpfe_cfg->slaveclk) { + v4l2_err(vpfe_dev->pdev->driver, + "No clock defined for vpss slave\n"); + goto out; + } + + if (clk_enable(vpfe_cfg->slaveclk)) { + v4l2_err(vpfe_dev->pdev->driver, + "vpfe vpss slave clock not enabled\n"); + goto out; + } + v4l2_info(vpfe_dev->pdev->driver, "vpfe vpss slave clock enabled\n"); + return 0; +out: + if (vpfe_cfg->vpssclk) + clk_put(vpfe_cfg->vpssclk); + if (vpfe_cfg->slaveclk) + clk_put(vpfe_cfg->slaveclk); + + return -1; +} + +/* + * vpfe_probe : This function creates device entries by register + * itself to the V4L2 driver and initializes fields of each + * device objects + */ +static __init int vpfe_probe(struct platform_device *pdev) +{ + struct vpfe_subdev_info *sdinfo; + struct vpfe_config *vpfe_cfg; + struct resource *res1; + struct vpfe_device *vpfe_dev; + struct i2c_adapter *i2c_adap; + struct video_device *vfd; + int ret = -ENOMEM, i, j; + int num_subdevs = 0; + + /* Get the pointer to the device object */ + vpfe_dev = vpfe_initialize(); + + if (!vpfe_dev) { + v4l2_err(pdev->dev.driver, + "Failed to allocate memory for vpfe_dev\n"); + return ret; + } + + vpfe_dev->pdev = &pdev->dev; + + if (NULL == pdev->dev.platform_data) { + v4l2_err(pdev->dev.driver, "Unable to get vpfe config\n"); + ret = -ENOENT; + goto probe_free_dev_mem; + } + + vpfe_cfg = pdev->dev.platform_data; + vpfe_dev->cfg = vpfe_cfg; + if (NULL == vpfe_cfg->ccdc || + NULL == vpfe_cfg->card_name || + NULL == vpfe_cfg->sub_devs) { + v4l2_err(pdev->dev.driver, "null ptr in vpfe_cfg\n"); + ret = -ENOENT; + goto probe_free_dev_mem; + } + + /* enable vpss clocks */ + ret = vpfe_enable_clock(vpfe_dev); + if (ret) + goto probe_free_dev_mem; + + mutex_lock(&ccdc_lock); + /* Allocate memory for ccdc configuration */ + ccdc_cfg = kmalloc(sizeof(struct ccdc_config), GFP_KERNEL); + if (NULL == ccdc_cfg) { + v4l2_err(pdev->dev.driver, + "Memory allocation failed for ccdc_cfg\n"); + goto probe_disable_clock; + } + + strncpy(ccdc_cfg->name, vpfe_cfg->ccdc, 32); + /* Get VINT0 irq resource */ + res1 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res1) { + v4l2_err(pdev->dev.driver, + "Unable to get interrupt for VINT0\n"); + ret = -ENOENT; + goto probe_disable_clock; + } + vpfe_dev->ccdc_irq0 = res1->start; + + /* Get VINT1 irq resource */ + res1 = platform_get_resource(pdev, + IORESOURCE_IRQ, 1); + if (!res1) { + v4l2_err(pdev->dev.driver, + "Unable to get interrupt for VINT1\n"); + ret = -ENOENT; + goto probe_disable_clock; + } + vpfe_dev->ccdc_irq1 = res1->start; + + /* Get address base of CCDC */ + res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res1) { + v4l2_err(pdev->dev.driver, + "Unable to get register address map\n"); + ret = -ENOENT; + goto probe_disable_clock; + } + + ccdc_cfg->ccdc_addr_size = res1->end - res1->start + 1; + if (!request_mem_region(res1->start, ccdc_cfg->ccdc_addr_size, + pdev->dev.driver->name)) { + v4l2_err(pdev->dev.driver, + "Failed request_mem_region for ccdc base\n"); + ret = -ENXIO; + goto probe_disable_clock; + } + ccdc_cfg->ccdc_addr = ioremap_nocache(res1->start, + ccdc_cfg->ccdc_addr_size); + if (!ccdc_cfg->ccdc_addr) { + v4l2_err(pdev->dev.driver, "Unable to ioremap ccdc addr\n"); + ret = -ENXIO; + goto probe_out_release_mem1; + } + + ret = request_irq(vpfe_dev->ccdc_irq0, vpfe_isr, IRQF_DISABLED, + "vpfe_capture0", vpfe_dev); + + if (0 != ret) { + v4l2_err(pdev->dev.driver, "Unable to request interrupt\n"); + goto probe_out_unmap1; + } + + /* Allocate memory for video device */ + vfd = video_device_alloc(); + if (NULL == vfd) { + ret = -ENOMEM; + v4l2_err(pdev->dev.driver, + "Unable to alloc video device\n"); + goto probe_out_release_irq; + } + + /* Initialize field of video device */ + vfd->release = video_device_release; + vfd->fops = &vpfe_fops; + vfd->ioctl_ops = &vpfe_ioctl_ops; + vfd->minor = -1; + vfd->tvnorms = 0; + vfd->current_norm = V4L2_STD_PAL; + vfd->v4l2_dev = &vpfe_dev->v4l2_dev; + snprintf(vfd->name, sizeof(vfd->name), + "%s_V%d.%d.%d", + CAPTURE_DRV_NAME, + (VPFE_CAPTURE_VERSION_CODE >> 16) & 0xff, + (VPFE_CAPTURE_VERSION_CODE >> 8) & 0xff, + (VPFE_CAPTURE_VERSION_CODE) & 0xff); + /* Set video_dev to the video device */ + vpfe_dev->video_dev = vfd; + + ret = v4l2_device_register(&pdev->dev, &vpfe_dev->v4l2_dev); + if (ret) { + v4l2_err(pdev->dev.driver, + "Unable to register v4l2 device.\n"); + goto probe_out_video_release; + } + v4l2_info(&vpfe_dev->v4l2_dev, "v4l2 device registered\n"); + spin_lock_init(&vpfe_dev->irqlock); + spin_lock_init(&vpfe_dev->dma_queue_lock); + mutex_init(&vpfe_dev->lock); + + /* Initialize field of the device objects */ + vpfe_dev->numbuffers = config_params.numbuffers; + + /* Initialize prio member of device object */ + v4l2_prio_init(&vpfe_dev->prio); + /* register video device */ + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, + "trying to register vpfe device.\n"); + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, + "video_dev=%x\n", (int)&vpfe_dev->video_dev); + vpfe_dev->fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + ret = video_register_device(vpfe_dev->video_dev, + VFL_TYPE_GRABBER, -1); + + if (ret) { + v4l2_err(pdev->dev.driver, + "Unable to register video device.\n"); + goto probe_out_v4l2_unregister; + } + + v4l2_info(&vpfe_dev->v4l2_dev, "video device registered\n"); + /* set the driver data in platform device */ + platform_set_drvdata(pdev, vpfe_dev); + /* set driver private data */ + video_set_drvdata(vpfe_dev->video_dev, vpfe_dev); + i2c_adap = i2c_get_adapter(1); + vpfe_cfg = pdev->dev.platform_data; + num_subdevs = vpfe_cfg->num_subdevs; + vpfe_dev->sd = kmalloc(sizeof(struct v4l2_subdev *) * num_subdevs, + GFP_KERNEL); + if (NULL == vpfe_dev->sd) { + v4l2_err(&vpfe_dev->v4l2_dev, + "unable to allocate memory for subdevice pointers\n"); + ret = -ENOMEM; + goto probe_out_video_unregister; + } + + for (i = 0; i < num_subdevs; i++) { + struct v4l2_input *inps; + + sdinfo = &vpfe_cfg->sub_devs[i]; + + /* Load up the subdevice */ + vpfe_dev->sd[i] = + v4l2_i2c_new_subdev_board(&vpfe_dev->v4l2_dev, + i2c_adap, + sdinfo->name, + &sdinfo->board_info, + NULL); + if (vpfe_dev->sd[i]) { + v4l2_info(&vpfe_dev->v4l2_dev, + "v4l2 sub device %s registered\n", + sdinfo->name); + vpfe_dev->sd[i]->grp_id = sdinfo->grp_id; + /* update tvnorms from the sub devices */ + for (j = 0; j < sdinfo->num_inputs; j++) { + inps = &sdinfo->inputs[j]; + vfd->tvnorms |= inps->std; + } + } else { + v4l2_info(&vpfe_dev->v4l2_dev, + "v4l2 sub device %s register fails\n", + sdinfo->name); + goto probe_sd_out; + } + } + + /* set first sub device as current one */ + vpfe_dev->current_subdev = &vpfe_cfg->sub_devs[0]; + + /* We have at least one sub device to work with */ + mutex_unlock(&ccdc_lock); + return 0; + +probe_sd_out: + kfree(vpfe_dev->sd); +probe_out_video_unregister: + video_unregister_device(vpfe_dev->video_dev); +probe_out_v4l2_unregister: + v4l2_device_unregister(&vpfe_dev->v4l2_dev); +probe_out_video_release: + if (vpfe_dev->video_dev->minor == -1) + video_device_release(vpfe_dev->video_dev); +probe_out_release_irq: + free_irq(vpfe_dev->ccdc_irq0, vpfe_dev); +probe_out_unmap1: + iounmap(ccdc_cfg->ccdc_addr); +probe_out_release_mem1: + release_mem_region(res1->start, res1->end - res1->start + 1); +probe_disable_clock: + vpfe_disable_clock(vpfe_dev); + mutex_unlock(&ccdc_lock); + kfree(ccdc_cfg); +probe_free_dev_mem: + kfree(vpfe_dev); + return ret; +} + +/* + * vpfe_remove : It un-register device from V4L2 driver + */ +static int vpfe_remove(struct platform_device *pdev) +{ + struct vpfe_device *vpfe_dev = platform_get_drvdata(pdev); + struct resource *res; + + v4l2_info(pdev->dev.driver, "vpfe_remove\n"); + + free_irq(vpfe_dev->ccdc_irq0, vpfe_dev); + kfree(vpfe_dev->sd); + v4l2_device_unregister(&vpfe_dev->v4l2_dev); + video_unregister_device(vpfe_dev->video_dev); + mutex_lock(&ccdc_lock); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, res->end - res->start + 1); + iounmap(ccdc_cfg->ccdc_addr); + mutex_unlock(&ccdc_lock); + vpfe_disable_clock(vpfe_dev); + kfree(vpfe_dev); + kfree(ccdc_cfg); + return 0; +} + +static int +vpfe_suspend(struct device *dev) +{ + /* add suspend code here later */ + return -1; +} + +static int +vpfe_resume(struct device *dev) +{ + /* add resume code here later */ + return -1; +} + +static struct dev_pm_ops vpfe_dev_pm_ops = { + .suspend = vpfe_suspend, + .resume = vpfe_resume, +}; + +static struct platform_driver vpfe_driver = { + .driver = { + .name = CAPTURE_DRV_NAME, + .owner = THIS_MODULE, + .pm = &vpfe_dev_pm_ops, + }, + .probe = vpfe_probe, + .remove = __devexit_p(vpfe_remove), +}; + +static __init int vpfe_init(void) +{ + printk(KERN_NOTICE "vpfe_init\n"); + /* Register driver to the kernel */ + return platform_driver_register(&vpfe_driver); +} + +/* + * vpfe_cleanup : This function un-registers device driver + */ +static void vpfe_cleanup(void) +{ + platform_driver_unregister(&vpfe_driver); +} + +module_init(vpfe_init); +module_exit(vpfe_cleanup); diff --git a/drivers/media/video/davinci/vpif.c b/drivers/media/video/davinci/vpif.c new file mode 100644 index 000000000000..3b8eac31ecae --- /dev/null +++ b/drivers/media/video/davinci/vpif.c @@ -0,0 +1,296 @@ +/* + * vpif - DM646x Video Port Interface driver + * VPIF is a receiver and transmitter for video data. It has two channels(0, 1) + * that receiveing video byte stream and two channels(2, 3) for video output. + * The hardware supports SDTV, HDTV formats, raw data capture. + * Currently, the driver supports NTSC and PAL standards. + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed .as is. WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "vpif.h" + +MODULE_DESCRIPTION("TI DaVinci Video Port Interface driver"); +MODULE_LICENSE("GPL"); + +#define VPIF_CH0_MAX_MODES (22) +#define VPIF_CH1_MAX_MODES (02) +#define VPIF_CH2_MAX_MODES (15) +#define VPIF_CH3_MAX_MODES (02) + +static resource_size_t res_len; +static struct resource *res; +spinlock_t vpif_lock; + +void __iomem *vpif_base; + +static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val) +{ + if (val) + vpif_set_bit(reg, bit); + else + vpif_clr_bit(reg, bit); +} + +/* This structure is used to keep track of VPIF size register's offsets */ +struct vpif_registers { + u32 h_cfg, v_cfg_00, v_cfg_01, v_cfg_02, v_cfg, ch_ctrl; + u32 line_offset, vanc0_strt, vanc0_size, vanc1_strt; + u32 vanc1_size, width_mask, len_mask; + u8 max_modes; +}; + +static const struct vpif_registers vpifregs[VPIF_NUM_CHANNELS] = { + /* Channel0 */ + { + VPIF_CH0_H_CFG, VPIF_CH0_V_CFG_00, VPIF_CH0_V_CFG_01, + VPIF_CH0_V_CFG_02, VPIF_CH0_V_CFG_03, VPIF_CH0_CTRL, + VPIF_CH0_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF, + VPIF_CH0_MAX_MODES, + }, + /* Channel1 */ + { + VPIF_CH1_H_CFG, VPIF_CH1_V_CFG_00, VPIF_CH1_V_CFG_01, + VPIF_CH1_V_CFG_02, VPIF_CH1_V_CFG_03, VPIF_CH1_CTRL, + VPIF_CH1_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF, + VPIF_CH1_MAX_MODES, + }, + /* Channel2 */ + { + VPIF_CH2_H_CFG, VPIF_CH2_V_CFG_00, VPIF_CH2_V_CFG_01, + VPIF_CH2_V_CFG_02, VPIF_CH2_V_CFG_03, VPIF_CH2_CTRL, + VPIF_CH2_IMG_ADD_OFST, VPIF_CH2_VANC0_STRT, VPIF_CH2_VANC0_SIZE, + VPIF_CH2_VANC1_STRT, VPIF_CH2_VANC1_SIZE, 0x7FF, 0x7FF, + VPIF_CH2_MAX_MODES + }, + /* Channel3 */ + { + VPIF_CH3_H_CFG, VPIF_CH3_V_CFG_00, VPIF_CH3_V_CFG_01, + VPIF_CH3_V_CFG_02, VPIF_CH3_V_CFG_03, VPIF_CH3_CTRL, + VPIF_CH3_IMG_ADD_OFST, VPIF_CH3_VANC0_STRT, VPIF_CH3_VANC0_SIZE, + VPIF_CH3_VANC1_STRT, VPIF_CH3_VANC1_SIZE, 0x7FF, 0x7FF, + VPIF_CH3_MAX_MODES + }, +}; + +/* vpif_set_mode_info: + * This function is used to set horizontal and vertical config parameters + * As per the standard in the channel, configure the values of L1, L3, + * L5, L7 L9, L11 in VPIF Register , also write width and height + */ +static void vpif_set_mode_info(const struct vpif_channel_config_params *config, + u8 channel_id, u8 config_channel_id) +{ + u32 value; + + value = (config->eav2sav & vpifregs[config_channel_id].width_mask); + value <<= VPIF_CH_LEN_SHIFT; + value |= (config->sav2eav & vpifregs[config_channel_id].width_mask); + regw(value, vpifregs[channel_id].h_cfg); + + value = (config->l1 & vpifregs[config_channel_id].len_mask); + value <<= VPIF_CH_LEN_SHIFT; + value |= (config->l3 & vpifregs[config_channel_id].len_mask); + regw(value, vpifregs[channel_id].v_cfg_00); + + value = (config->l5 & vpifregs[config_channel_id].len_mask); + value <<= VPIF_CH_LEN_SHIFT; + value |= (config->l7 & vpifregs[config_channel_id].len_mask); + regw(value, vpifregs[channel_id].v_cfg_01); + + value = (config->l9 & vpifregs[config_channel_id].len_mask); + value <<= VPIF_CH_LEN_SHIFT; + value |= (config->l11 & vpifregs[config_channel_id].len_mask); + regw(value, vpifregs[channel_id].v_cfg_02); + + value = (config->vsize & vpifregs[config_channel_id].len_mask); + regw(value, vpifregs[channel_id].v_cfg); +} + +/* config_vpif_params + * Function to set the parameters of a channel + * Mainly modifies the channel ciontrol register + * It sets frame format, yc mux mode + */ +static void config_vpif_params(struct vpif_params *vpifparams, + u8 channel_id, u8 found) +{ + const struct vpif_channel_config_params *config = &vpifparams->std_info; + u32 value, ch_nip, reg; + u8 start, end; + int i; + + start = channel_id; + end = channel_id + found; + + for (i = start; i < end; i++) { + reg = vpifregs[i].ch_ctrl; + if (channel_id < 2) + ch_nip = VPIF_CAPTURE_CH_NIP; + else + ch_nip = VPIF_DISPLAY_CH_NIP; + + vpif_wr_bit(reg, ch_nip, config->frm_fmt); + vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode); + vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT, + vpifparams->video_params.storage_mode); + + /* Set raster scanning SDR Format */ + vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT); + vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format); + + if (channel_id > 1) /* Set the Pixel enable bit */ + vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT); + else if (config->capture_format) { + /* Set the polarity of various pins */ + vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT, + vpifparams->iface.fid_pol); + vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT, + vpifparams->iface.vd_pol); + vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT, + vpifparams->iface.hd_pol); + + value = regr(reg); + /* Set data width */ + value &= ((~(unsigned int)(0x3)) << + VPIF_CH_DATA_WIDTH_BIT); + value |= ((vpifparams->params.data_sz) << + VPIF_CH_DATA_WIDTH_BIT); + regw(value, reg); + } + + /* Write the pitch in the driver */ + regw((vpifparams->video_params.hpitch), + vpifregs[i].line_offset); + } +} + +/* vpif_set_video_params + * This function is used to set video parameters in VPIF register + */ +int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id) +{ + const struct vpif_channel_config_params *config = &vpifparams->std_info; + int found = 1; + + vpif_set_mode_info(config, channel_id, channel_id); + if (!config->ycmux_mode) { + /* YC are on separate channels (HDTV formats) */ + vpif_set_mode_info(config, channel_id + 1, channel_id); + found = 2; + } + + config_vpif_params(vpifparams, channel_id, found); + + regw(0x80, VPIF_REQ_SIZE); + regw(0x01, VPIF_EMULATION_CTRL); + + return found; +} +EXPORT_SYMBOL(vpif_set_video_params); + +void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams, + u8 channel_id) +{ + u32 value; + + value = 0x3F8 & (vbiparams->hstart0); + value |= 0x3FFFFFF & ((vbiparams->vstart0) << 16); + regw(value, vpifregs[channel_id].vanc0_strt); + + value = 0x3F8 & (vbiparams->hstart1); + value |= 0x3FFFFFF & ((vbiparams->vstart1) << 16); + regw(value, vpifregs[channel_id].vanc1_strt); + + value = 0x3F8 & (vbiparams->hsize0); + value |= 0x3FFFFFF & ((vbiparams->vsize0) << 16); + regw(value, vpifregs[channel_id].vanc0_size); + + value = 0x3F8 & (vbiparams->hsize1); + value |= 0x3FFFFFF & ((vbiparams->vsize1) << 16); + regw(value, vpifregs[channel_id].vanc1_size); + +} +EXPORT_SYMBOL(vpif_set_vbi_display_params); + +int vpif_channel_getfid(u8 channel_id) +{ + return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK) + >> VPIF_CH_FID_SHIFT; +} +EXPORT_SYMBOL(vpif_channel_getfid); + +static int __init vpif_probe(struct platform_device *pdev) +{ + int status = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOENT; + + res_len = res->end - res->start + 1; + + res = request_mem_region(res->start, res_len, res->name); + if (!res) + return -EBUSY; + + vpif_base = ioremap(res->start, res_len); + if (!vpif_base) { + status = -EBUSY; + goto fail; + } + + spin_lock_init(&vpif_lock); + dev_info(&pdev->dev, "vpif probe success\n"); + return 0; + +fail: + release_mem_region(res->start, res_len); + return status; +} + +static int vpif_remove(struct platform_device *pdev) +{ + iounmap(vpif_base); + release_mem_region(res->start, res_len); + return 0; +} + +static struct platform_driver vpif_driver = { + .driver = { + .name = "vpif", + .owner = THIS_MODULE, + }, + .remove = __devexit_p(vpif_remove), + .probe = vpif_probe, +}; + +static void vpif_exit(void) +{ + platform_driver_unregister(&vpif_driver); +} + +static int __init vpif_init(void) +{ + return platform_driver_register(&vpif_driver); +} +subsys_initcall(vpif_init); +module_exit(vpif_exit); + diff --git a/drivers/media/video/davinci/vpif.h b/drivers/media/video/davinci/vpif.h new file mode 100644 index 000000000000..188841b476e0 --- /dev/null +++ b/drivers/media/video/davinci/vpif.h @@ -0,0 +1,642 @@ +/* + * VPIF header file + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed .as is. WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VPIF_H +#define VPIF_H + +#include +#include +#include +#include + +/* Maximum channel allowed */ +#define VPIF_NUM_CHANNELS (4) +#define VPIF_CAPTURE_NUM_CHANNELS (2) +#define VPIF_DISPLAY_NUM_CHANNELS (2) + +/* Macros to read/write registers */ +extern void __iomem *vpif_base; +extern spinlock_t vpif_lock; + +#define regr(reg) readl((reg) + vpif_base) +#define regw(value, reg) writel(value, (reg + vpif_base)) + +/* Register Addresss Offsets */ +#define VPIF_PID (0x0000) +#define VPIF_CH0_CTRL (0x0004) +#define VPIF_CH1_CTRL (0x0008) +#define VPIF_CH2_CTRL (0x000C) +#define VPIF_CH3_CTRL (0x0010) + +#define VPIF_INTEN (0x0020) +#define VPIF_INTEN_SET (0x0024) +#define VPIF_INTEN_CLR (0x0028) +#define VPIF_STATUS (0x002C) +#define VPIF_STATUS_CLR (0x0030) +#define VPIF_EMULATION_CTRL (0x0034) +#define VPIF_REQ_SIZE (0x0038) + +#define VPIF_CH0_TOP_STRT_ADD_LUMA (0x0040) +#define VPIF_CH0_BTM_STRT_ADD_LUMA (0x0044) +#define VPIF_CH0_TOP_STRT_ADD_CHROMA (0x0048) +#define VPIF_CH0_BTM_STRT_ADD_CHROMA (0x004c) +#define VPIF_CH0_TOP_STRT_ADD_HANC (0x0050) +#define VPIF_CH0_BTM_STRT_ADD_HANC (0x0054) +#define VPIF_CH0_TOP_STRT_ADD_VANC (0x0058) +#define VPIF_CH0_BTM_STRT_ADD_VANC (0x005c) +#define VPIF_CH0_SP_CFG (0x0060) +#define VPIF_CH0_IMG_ADD_OFST (0x0064) +#define VPIF_CH0_HANC_ADD_OFST (0x0068) +#define VPIF_CH0_H_CFG (0x006c) +#define VPIF_CH0_V_CFG_00 (0x0070) +#define VPIF_CH0_V_CFG_01 (0x0074) +#define VPIF_CH0_V_CFG_02 (0x0078) +#define VPIF_CH0_V_CFG_03 (0x007c) + +#define VPIF_CH1_TOP_STRT_ADD_LUMA (0x0080) +#define VPIF_CH1_BTM_STRT_ADD_LUMA (0x0084) +#define VPIF_CH1_TOP_STRT_ADD_CHROMA (0x0088) +#define VPIF_CH1_BTM_STRT_ADD_CHROMA (0x008c) +#define VPIF_CH1_TOP_STRT_ADD_HANC (0x0090) +#define VPIF_CH1_BTM_STRT_ADD_HANC (0x0094) +#define VPIF_CH1_TOP_STRT_ADD_VANC (0x0098) +#define VPIF_CH1_BTM_STRT_ADD_VANC (0x009c) +#define VPIF_CH1_SP_CFG (0x00a0) +#define VPIF_CH1_IMG_ADD_OFST (0x00a4) +#define VPIF_CH1_HANC_ADD_OFST (0x00a8) +#define VPIF_CH1_H_CFG (0x00ac) +#define VPIF_CH1_V_CFG_00 (0x00b0) +#define VPIF_CH1_V_CFG_01 (0x00b4) +#define VPIF_CH1_V_CFG_02 (0x00b8) +#define VPIF_CH1_V_CFG_03 (0x00bc) + +#define VPIF_CH2_TOP_STRT_ADD_LUMA (0x00c0) +#define VPIF_CH2_BTM_STRT_ADD_LUMA (0x00c4) +#define VPIF_CH2_TOP_STRT_ADD_CHROMA (0x00c8) +#define VPIF_CH2_BTM_STRT_ADD_CHROMA (0x00cc) +#define VPIF_CH2_TOP_STRT_ADD_HANC (0x00d0) +#define VPIF_CH2_BTM_STRT_ADD_HANC (0x00d4) +#define VPIF_CH2_TOP_STRT_ADD_VANC (0x00d8) +#define VPIF_CH2_BTM_STRT_ADD_VANC (0x00dc) +#define VPIF_CH2_SP_CFG (0x00e0) +#define VPIF_CH2_IMG_ADD_OFST (0x00e4) +#define VPIF_CH2_HANC_ADD_OFST (0x00e8) +#define VPIF_CH2_H_CFG (0x00ec) +#define VPIF_CH2_V_CFG_00 (0x00f0) +#define VPIF_CH2_V_CFG_01 (0x00f4) +#define VPIF_CH2_V_CFG_02 (0x00f8) +#define VPIF_CH2_V_CFG_03 (0x00fc) +#define VPIF_CH2_HANC0_STRT (0x0100) +#define VPIF_CH2_HANC0_SIZE (0x0104) +#define VPIF_CH2_HANC1_STRT (0x0108) +#define VPIF_CH2_HANC1_SIZE (0x010c) +#define VPIF_CH2_VANC0_STRT (0x0110) +#define VPIF_CH2_VANC0_SIZE (0x0114) +#define VPIF_CH2_VANC1_STRT (0x0118) +#define VPIF_CH2_VANC1_SIZE (0x011c) + +#define VPIF_CH3_TOP_STRT_ADD_LUMA (0x0140) +#define VPIF_CH3_BTM_STRT_ADD_LUMA (0x0144) +#define VPIF_CH3_TOP_STRT_ADD_CHROMA (0x0148) +#define VPIF_CH3_BTM_STRT_ADD_CHROMA (0x014c) +#define VPIF_CH3_TOP_STRT_ADD_HANC (0x0150) +#define VPIF_CH3_BTM_STRT_ADD_HANC (0x0154) +#define VPIF_CH3_TOP_STRT_ADD_VANC (0x0158) +#define VPIF_CH3_BTM_STRT_ADD_VANC (0x015c) +#define VPIF_CH3_SP_CFG (0x0160) +#define VPIF_CH3_IMG_ADD_OFST (0x0164) +#define VPIF_CH3_HANC_ADD_OFST (0x0168) +#define VPIF_CH3_H_CFG (0x016c) +#define VPIF_CH3_V_CFG_00 (0x0170) +#define VPIF_CH3_V_CFG_01 (0x0174) +#define VPIF_CH3_V_CFG_02 (0x0178) +#define VPIF_CH3_V_CFG_03 (0x017c) +#define VPIF_CH3_HANC0_STRT (0x0180) +#define VPIF_CH3_HANC0_SIZE (0x0184) +#define VPIF_CH3_HANC1_STRT (0x0188) +#define VPIF_CH3_HANC1_SIZE (0x018c) +#define VPIF_CH3_VANC0_STRT (0x0190) +#define VPIF_CH3_VANC0_SIZE (0x0194) +#define VPIF_CH3_VANC1_STRT (0x0198) +#define VPIF_CH3_VANC1_SIZE (0x019c) + +#define VPIF_IODFT_CTRL (0x01c0) + +/* Functions for bit Manipulation */ +static inline void vpif_set_bit(u32 reg, u32 bit) +{ + regw((regr(reg)) | (0x01 << bit), reg); +} + +static inline void vpif_clr_bit(u32 reg, u32 bit) +{ + regw(((regr(reg)) & ~(0x01 << bit)), reg); +} + +/* Macro for Generating mask */ +#ifdef GENERATE_MASK +#undef GENERATE_MASK +#endif + +#define GENERATE_MASK(bits, pos) \ + ((((0xFFFFFFFF) << (32 - bits)) >> (32 - bits)) << pos) + +/* Bit positions in the channel control registers */ +#define VPIF_CH_DATA_MODE_BIT (2) +#define VPIF_CH_YC_MUX_BIT (3) +#define VPIF_CH_SDR_FMT_BIT (4) +#define VPIF_CH_HANC_EN_BIT (8) +#define VPIF_CH_VANC_EN_BIT (9) + +#define VPIF_CAPTURE_CH_NIP (10) +#define VPIF_DISPLAY_CH_NIP (11) + +#define VPIF_DISPLAY_PIX_EN_BIT (10) + +#define VPIF_CH_INPUT_FIELD_FRAME_BIT (12) + +#define VPIF_CH_FID_POLARITY_BIT (15) +#define VPIF_CH_V_VALID_POLARITY_BIT (14) +#define VPIF_CH_H_VALID_POLARITY_BIT (13) +#define VPIF_CH_DATA_WIDTH_BIT (28) + +#define VPIF_CH_CLK_EDGE_CTRL_BIT (31) + +/* Mask various length */ +#define VPIF_CH_EAVSAV_MASK GENERATE_MASK(13, 0) +#define VPIF_CH_LEN_MASK GENERATE_MASK(12, 0) +#define VPIF_CH_WIDTH_MASK GENERATE_MASK(13, 0) +#define VPIF_CH_LEN_SHIFT (16) + +/* VPIF masks for registers */ +#define VPIF_REQ_SIZE_MASK (0x1ff) + +/* bit posotion of interrupt vpif_ch_intr register */ +#define VPIF_INTEN_FRAME_CH0 (0x00000001) +#define VPIF_INTEN_FRAME_CH1 (0x00000002) +#define VPIF_INTEN_FRAME_CH2 (0x00000004) +#define VPIF_INTEN_FRAME_CH3 (0x00000008) + +/* bit position of clock and channel enable in vpif_chn_ctrl register */ + +#define VPIF_CH0_CLK_EN (0x00000002) +#define VPIF_CH0_EN (0x00000001) +#define VPIF_CH1_CLK_EN (0x00000002) +#define VPIF_CH1_EN (0x00000001) +#define VPIF_CH2_CLK_EN (0x00000002) +#define VPIF_CH2_EN (0x00000001) +#define VPIF_CH3_CLK_EN (0x00000002) +#define VPIF_CH3_EN (0x00000001) +#define VPIF_CH_CLK_EN (0x00000002) +#define VPIF_CH_EN (0x00000001) + +#define VPIF_INT_TOP (0x00) +#define VPIF_INT_BOTTOM (0x01) +#define VPIF_INT_BOTH (0x02) + +#define VPIF_CH0_INT_CTRL_SHIFT (6) +#define VPIF_CH1_INT_CTRL_SHIFT (6) +#define VPIF_CH2_INT_CTRL_SHIFT (6) +#define VPIF_CH3_INT_CTRL_SHIFT (6) +#define VPIF_CH_INT_CTRL_SHIFT (6) + +/* enabled interrupt on both the fields on vpid_ch0_ctrl register */ +#define channel0_intr_assert() (regw((regr(VPIF_CH0_CTRL)|\ + (VPIF_INT_BOTH << VPIF_CH0_INT_CTRL_SHIFT)), VPIF_CH0_CTRL)) + +/* enabled interrupt on both the fields on vpid_ch1_ctrl register */ +#define channel1_intr_assert() (regw((regr(VPIF_CH1_CTRL)|\ + (VPIF_INT_BOTH << VPIF_CH1_INT_CTRL_SHIFT)), VPIF_CH1_CTRL)) + +/* enabled interrupt on both the fields on vpid_ch0_ctrl register */ +#define channel2_intr_assert() (regw((regr(VPIF_CH2_CTRL)|\ + (VPIF_INT_BOTH << VPIF_CH2_INT_CTRL_SHIFT)), VPIF_CH2_CTRL)) + +/* enabled interrupt on both the fields on vpid_ch1_ctrl register */ +#define channel3_intr_assert() (regw((regr(VPIF_CH3_CTRL)|\ + (VPIF_INT_BOTH << VPIF_CH3_INT_CTRL_SHIFT)), VPIF_CH3_CTRL)) + +#define VPIF_CH_FID_MASK (0x20) +#define VPIF_CH_FID_SHIFT (5) + +#define VPIF_NTSC_VBI_START_FIELD0 (1) +#define VPIF_NTSC_VBI_START_FIELD1 (263) +#define VPIF_PAL_VBI_START_FIELD0 (624) +#define VPIF_PAL_VBI_START_FIELD1 (311) + +#define VPIF_NTSC_HBI_START_FIELD0 (1) +#define VPIF_NTSC_HBI_START_FIELD1 (263) +#define VPIF_PAL_HBI_START_FIELD0 (624) +#define VPIF_PAL_HBI_START_FIELD1 (311) + +#define VPIF_NTSC_VBI_COUNT_FIELD0 (20) +#define VPIF_NTSC_VBI_COUNT_FIELD1 (19) +#define VPIF_PAL_VBI_COUNT_FIELD0 (24) +#define VPIF_PAL_VBI_COUNT_FIELD1 (25) + +#define VPIF_NTSC_HBI_COUNT_FIELD0 (263) +#define VPIF_NTSC_HBI_COUNT_FIELD1 (262) +#define VPIF_PAL_HBI_COUNT_FIELD0 (312) +#define VPIF_PAL_HBI_COUNT_FIELD1 (313) + +#define VPIF_NTSC_VBI_SAMPLES_PER_LINE (720) +#define VPIF_PAL_VBI_SAMPLES_PER_LINE (720) +#define VPIF_NTSC_HBI_SAMPLES_PER_LINE (268) +#define VPIF_PAL_HBI_SAMPLES_PER_LINE (280) + +#define VPIF_CH_VANC_EN (0x20) +#define VPIF_DMA_REQ_SIZE (0x080) +#define VPIF_EMULATION_DISABLE (0x01) + +extern u8 irq_vpif_capture_channel[VPIF_NUM_CHANNELS]; + +/* inline function to enable/disable channel0 */ +static inline void enable_channel0(int enable) +{ + if (enable) + regw((regr(VPIF_CH0_CTRL) | (VPIF_CH0_EN)), VPIF_CH0_CTRL); + else + regw((regr(VPIF_CH0_CTRL) & (~VPIF_CH0_EN)), VPIF_CH0_CTRL); +} + +/* inline function to enable/disable channel1 */ +static inline void enable_channel1(int enable) +{ + if (enable) + regw((regr(VPIF_CH1_CTRL) | (VPIF_CH1_EN)), VPIF_CH1_CTRL); + else + regw((regr(VPIF_CH1_CTRL) & (~VPIF_CH1_EN)), VPIF_CH1_CTRL); +} + +/* inline function to enable interrupt for channel0 */ +static inline void channel0_intr_enable(int enable) +{ + unsigned long flags; + + spin_lock_irqsave(&vpif_lock, flags); + + if (enable) { + regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); + regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); + + regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH0), VPIF_INTEN); + regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0), + VPIF_INTEN_SET); + } else { + regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH0)), VPIF_INTEN); + regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0), + VPIF_INTEN_SET); + } + spin_unlock_irqrestore(&vpif_lock, flags); +} + +/* inline function to enable interrupt for channel1 */ +static inline void channel1_intr_enable(int enable) +{ + unsigned long flags; + + spin_lock_irqsave(&vpif_lock, flags); + + if (enable) { + regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); + regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); + + regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH1), VPIF_INTEN); + regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1), + VPIF_INTEN_SET); + } else { + regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH1)), VPIF_INTEN); + regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1), + VPIF_INTEN_SET); + } + spin_unlock_irqrestore(&vpif_lock, flags); +} + +/* inline function to set buffer addresses in case of Y/C non mux mode */ +static inline void ch0_set_videobuf_addr_yc_nmux(unsigned long top_strt_luma, + unsigned long btm_strt_luma, + unsigned long top_strt_chroma, + unsigned long btm_strt_chroma) +{ + regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA); + regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA); + regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA); + regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA); +} + +/* inline function to set buffer addresses in VPIF registers for video data */ +static inline void ch0_set_videobuf_addr(unsigned long top_strt_luma, + unsigned long btm_strt_luma, + unsigned long top_strt_chroma, + unsigned long btm_strt_chroma) +{ + regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA); + regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA); + regw(top_strt_chroma, VPIF_CH0_TOP_STRT_ADD_CHROMA); + regw(btm_strt_chroma, VPIF_CH0_BTM_STRT_ADD_CHROMA); +} + +static inline void ch1_set_videobuf_addr(unsigned long top_strt_luma, + unsigned long btm_strt_luma, + unsigned long top_strt_chroma, + unsigned long btm_strt_chroma) +{ + + regw(top_strt_luma, VPIF_CH1_TOP_STRT_ADD_LUMA); + regw(btm_strt_luma, VPIF_CH1_BTM_STRT_ADD_LUMA); + regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA); + regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA); +} + +static inline void ch0_set_vbi_addr(unsigned long top_vbi, + unsigned long btm_vbi, unsigned long a, unsigned long b) +{ + regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_VANC); + regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_VANC); +} + +static inline void ch0_set_hbi_addr(unsigned long top_vbi, + unsigned long btm_vbi, unsigned long a, unsigned long b) +{ + regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_HANC); + regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_HANC); +} + +static inline void ch1_set_vbi_addr(unsigned long top_vbi, + unsigned long btm_vbi, unsigned long a, unsigned long b) +{ + regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_VANC); + regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_VANC); +} + +static inline void ch1_set_hbi_addr(unsigned long top_vbi, + unsigned long btm_vbi, unsigned long a, unsigned long b) +{ + regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_HANC); + regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_HANC); +} + +/* Inline function to enable raw vbi in the given channel */ +static inline void disable_raw_feature(u8 channel_id, u8 index) +{ + u32 ctrl_reg; + if (0 == channel_id) + ctrl_reg = VPIF_CH0_CTRL; + else + ctrl_reg = VPIF_CH1_CTRL; + + if (1 == index) + vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); + else + vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); +} + +static inline void enable_raw_feature(u8 channel_id, u8 index) +{ + u32 ctrl_reg; + if (0 == channel_id) + ctrl_reg = VPIF_CH0_CTRL; + else + ctrl_reg = VPIF_CH1_CTRL; + + if (1 == index) + vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); + else + vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); +} + +/* inline function to enable/disable channel2 */ +static inline void enable_channel2(int enable) +{ + if (enable) { + regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL); + regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_EN)), VPIF_CH2_CTRL); + } else { + regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL); + regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_EN)), VPIF_CH2_CTRL); + } +} + +/* inline function to enable/disable channel3 */ +static inline void enable_channel3(int enable) +{ + if (enable) { + regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL); + regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_EN)), VPIF_CH3_CTRL); + } else { + regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL); + regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_EN)), VPIF_CH3_CTRL); + } +} + +/* inline function to enable interrupt for channel2 */ +static inline void channel2_intr_enable(int enable) +{ + unsigned long flags; + + spin_lock_irqsave(&vpif_lock, flags); + + if (enable) { + regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); + regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); + regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH2), VPIF_INTEN); + regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2), + VPIF_INTEN_SET); + } else { + regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH2)), VPIF_INTEN); + regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2), + VPIF_INTEN_SET); + } + spin_unlock_irqrestore(&vpif_lock, flags); +} + +/* inline function to enable interrupt for channel3 */ +static inline void channel3_intr_enable(int enable) +{ + unsigned long flags; + + spin_lock_irqsave(&vpif_lock, flags); + + if (enable) { + regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); + regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); + + regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH3), VPIF_INTEN); + regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3), + VPIF_INTEN_SET); + } else { + regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH3)), VPIF_INTEN); + regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3), + VPIF_INTEN_SET); + } + spin_unlock_irqrestore(&vpif_lock, flags); +} + +/* inline function to enable raw vbi data for channel2 */ +static inline void channel2_raw_enable(int enable, u8 index) +{ + u32 mask; + + if (1 == index) + mask = VPIF_CH_VANC_EN_BIT; + else + mask = VPIF_CH_HANC_EN_BIT; + + if (enable) + vpif_set_bit(VPIF_CH2_CTRL, mask); + else + vpif_clr_bit(VPIF_CH2_CTRL, mask); +} + +/* inline function to enable raw vbi data for channel3*/ +static inline void channel3_raw_enable(int enable, u8 index) +{ + u32 mask; + + if (1 == index) + mask = VPIF_CH_VANC_EN_BIT; + else + mask = VPIF_CH_HANC_EN_BIT; + + if (enable) + vpif_set_bit(VPIF_CH3_CTRL, mask); + else + vpif_clr_bit(VPIF_CH3_CTRL, mask); +} + +/* inline function to set buffer addresses in case of Y/C non mux mode */ +static inline void ch2_set_videobuf_addr_yc_nmux(unsigned long top_strt_luma, + unsigned long btm_strt_luma, + unsigned long top_strt_chroma, + unsigned long btm_strt_chroma) +{ + regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA); + regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA); + regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA); + regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA); +} + +/* inline function to set buffer addresses in VPIF registers for video data */ +static inline void ch2_set_videobuf_addr(unsigned long top_strt_luma, + unsigned long btm_strt_luma, + unsigned long top_strt_chroma, + unsigned long btm_strt_chroma) +{ + regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA); + regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA); + regw(top_strt_chroma, VPIF_CH2_TOP_STRT_ADD_CHROMA); + regw(btm_strt_chroma, VPIF_CH2_BTM_STRT_ADD_CHROMA); +} + +static inline void ch3_set_videobuf_addr(unsigned long top_strt_luma, + unsigned long btm_strt_luma, + unsigned long top_strt_chroma, + unsigned long btm_strt_chroma) +{ + regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_LUMA); + regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_LUMA); + regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA); + regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA); +} + +/* inline function to set buffer addresses in VPIF registers for vbi data */ +static inline void ch2_set_vbi_addr(unsigned long top_strt_luma, + unsigned long btm_strt_luma, + unsigned long top_strt_chroma, + unsigned long btm_strt_chroma) +{ + regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_VANC); + regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_VANC); +} + +static inline void ch3_set_vbi_addr(unsigned long top_strt_luma, + unsigned long btm_strt_luma, + unsigned long top_strt_chroma, + unsigned long btm_strt_chroma) +{ + regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_VANC); + regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_VANC); +} + +#define VPIF_MAX_NAME (30) + +/* This structure will store size parameters as per the mode selected by user */ +struct vpif_channel_config_params { + char name[VPIF_MAX_NAME]; /* Name of the mode */ + u16 width; /* Indicates width of the image */ + u16 height; /* Indicates height of the image */ + u8 fps; + u8 frm_fmt; /* Indicates whether this is interlaced + * or progressive format */ + u8 ycmux_mode; /* Indicates whether this mode requires + * single or two channels */ + u16 eav2sav; /* length of sav 2 eav */ + u16 sav2eav; /* length of sav 2 eav */ + u16 l1, l3, l5, l7, l9, l11; /* Other parameter configurations */ + u16 vsize; /* Vertical size of the image */ + u8 capture_format; /* Indicates whether capture format + * is in BT or in CCD/CMOS */ + u8 vbi_supported; /* Indicates whether this mode + * supports capturing vbi or not */ + u8 hd_sd; + v4l2_std_id stdid; +}; + +struct vpif_video_params; +struct vpif_params; +struct vpif_vbi_params; + +int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id); +void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams, + u8 channel_id); +int vpif_channel_getfid(u8 channel_id); + +enum data_size { + _8BITS = 0, + _10BITS, + _12BITS, +}; + +/* Structure for vpif parameters for raw vbi data */ +struct vpif_vbi_params { + __u32 hstart0; /* Horizontal start of raw vbi data for first field */ + __u32 vstart0; /* Vertical start of raw vbi data for first field */ + __u32 hsize0; /* Horizontal size of raw vbi data for first field */ + __u32 vsize0; /* Vertical size of raw vbi data for first field */ + __u32 hstart1; /* Horizontal start of raw vbi data for second field */ + __u32 vstart1; /* Vertical start of raw vbi data for second field */ + __u32 hsize1; /* Horizontal size of raw vbi data for second field */ + __u32 vsize1; /* Vertical size of raw vbi data for second field */ +}; + +/* structure for vpif parameters */ +struct vpif_video_params { + __u8 storage_mode; /* Indicates field or frame mode */ + unsigned long hpitch; + v4l2_std_id stdid; +}; + +struct vpif_params { + struct vpif_interface iface; + struct vpif_video_params video_params; + struct vpif_channel_config_params std_info; + union param { + struct vpif_vbi_params vbi_params; + enum data_size data_sz; + } params; +}; + +#endif /* End of #ifndef VPIF_H */ + diff --git a/drivers/media/video/davinci/vpif_capture.c b/drivers/media/video/davinci/vpif_capture.c new file mode 100644 index 000000000000..d947ee5e4eb4 --- /dev/null +++ b/drivers/media/video/davinci/vpif_capture.c @@ -0,0 +1,2168 @@ +/* + * Copyright (C) 2009 Texas Instruments Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * TODO : add support for VBI & HBI data service + * add static buffer allocation + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vpif_capture.h" +#include "vpif.h" + +MODULE_DESCRIPTION("TI DaVinci VPIF Capture driver"); +MODULE_LICENSE("GPL"); + +#define vpif_err(fmt, arg...) v4l2_err(&vpif_obj.v4l2_dev, fmt, ## arg) +#define vpif_dbg(level, debug, fmt, arg...) \ + v4l2_dbg(level, debug, &vpif_obj.v4l2_dev, fmt, ## arg) + +static int debug = 1; +static u32 ch0_numbuffers = 3; +static u32 ch1_numbuffers = 3; +static u32 ch0_bufsize = 1920 * 1080 * 2; +static u32 ch1_bufsize = 720 * 576 * 2; + +module_param(debug, int, 0644); +module_param(ch0_numbuffers, uint, S_IRUGO); +module_param(ch1_numbuffers, uint, S_IRUGO); +module_param(ch0_bufsize, uint, S_IRUGO); +module_param(ch1_bufsize, uint, S_IRUGO); + +MODULE_PARM_DESC(debug, "Debug level 0-1"); +MODULE_PARM_DESC(ch2_numbuffers, "Channel0 buffer count (default:3)"); +MODULE_PARM_DESC(ch3_numbuffers, "Channel1 buffer count (default:3)"); +MODULE_PARM_DESC(ch2_bufsize, "Channel0 buffer size (default:1920 x 1080 x 2)"); +MODULE_PARM_DESC(ch3_bufsize, "Channel1 buffer size (default:720 x 576 x 2)"); + +static struct vpif_config_params config_params = { + .min_numbuffers = 3, + .numbuffers[0] = 3, + .numbuffers[1] = 3, + .min_bufsize[0] = 720 * 480 * 2, + .min_bufsize[1] = 720 * 480 * 2, + .channel_bufsize[0] = 1920 * 1080 * 2, + .channel_bufsize[1] = 720 * 576 * 2, +}; + +/* global variables */ +static struct vpif_device vpif_obj = { {NULL} }; +static struct device *vpif_dev; + +/** + * ch_params: video standard configuration parameters for vpif + */ +static const struct vpif_channel_config_params ch_params[] = { + { + "NTSC_M", 720, 480, 30, 0, 1, 268, 1440, 1, 23, 263, 266, + 286, 525, 525, 0, 1, 0, V4L2_STD_525_60, + }, + { + "PAL_BDGHIK", 720, 576, 25, 0, 1, 280, 1440, 1, 23, 311, 313, + 336, 624, 625, 0, 1, 0, V4L2_STD_625_50, + }, +}; + +/** + * vpif_uservirt_to_phys : translate user/virtual address to phy address + * @virtp: user/virtual address + * + * This inline function is used to convert user space virtual address to + * physical address. + */ +static inline u32 vpif_uservirt_to_phys(u32 virtp) +{ + unsigned long physp = 0; + struct mm_struct *mm = current->mm; + struct vm_area_struct *vma; + + vma = find_vma(mm, virtp); + + /* For kernel direct-mapped memory, take the easy way */ + if (virtp >= PAGE_OFFSET) + physp = virt_to_phys((void *)virtp); + else if (vma && (vma->vm_flags & VM_IO) && (vma->vm_pgoff)) + /** + * this will catch, kernel-allocated, mmaped-to-usermode + * addresses + */ + physp = (vma->vm_pgoff << PAGE_SHIFT) + (virtp - vma->vm_start); + else { + /* otherwise, use get_user_pages() for general userland pages */ + int res, nr_pages = 1; + struct page *pages; + + down_read(¤t->mm->mmap_sem); + + res = get_user_pages(current, current->mm, + virtp, nr_pages, 1, 0, &pages, NULL); + up_read(¤t->mm->mmap_sem); + + if (res == nr_pages) + physp = __pa(page_address(&pages[0]) + + (virtp & ~PAGE_MASK)); + else { + vpif_err("get_user_pages failed\n"); + return 0; + } + } + return physp; +} + +/** + * buffer_prepare : callback function for buffer prepare + * @q : buffer queue ptr + * @vb: ptr to video buffer + * @field: field info + * + * This is the callback function for buffer prepare when videobuf_qbuf() + * function is called. The buffer is prepared and user space virtual address + * or user address is converted into physical address + */ +static int vpif_buffer_prepare(struct videobuf_queue *q, + struct videobuf_buffer *vb, + enum v4l2_field field) +{ + /* Get the file handle object and channel object */ + struct vpif_fh *fh = q->priv_data; + struct channel_obj *ch = fh->channel; + struct common_obj *common; + unsigned long addr; + + + vpif_dbg(2, debug, "vpif_buffer_prepare\n"); + + common = &ch->common[VPIF_VIDEO_INDEX]; + + /* If buffer is not initialized, initialize it */ + if (VIDEOBUF_NEEDS_INIT == vb->state) { + vb->width = common->width; + vb->height = common->height; + vb->size = vb->width * vb->height; + vb->field = field; + } + vb->state = VIDEOBUF_PREPARED; + /** + * if user pointer memory mechanism is used, get the physical + * address of the buffer + */ + if (V4L2_MEMORY_USERPTR == common->memory) { + if (0 == vb->baddr) { + vpif_dbg(1, debug, "buffer address is 0\n"); + return -EINVAL; + + } + vb->boff = vpif_uservirt_to_phys(vb->baddr); + if (!IS_ALIGNED(vb->boff, 8)) + goto exit; + } + + addr = vb->boff; + if (q->streaming) { + if (!IS_ALIGNED((addr + common->ytop_off), 8) || + !IS_ALIGNED((addr + common->ybtm_off), 8) || + !IS_ALIGNED((addr + common->ctop_off), 8) || + !IS_ALIGNED((addr + common->cbtm_off), 8)) + goto exit; + } + return 0; +exit: + vpif_dbg(1, debug, "buffer_prepare:offset is not aligned to 8 bytes\n"); + return -EINVAL; +} + +/** + * vpif_buffer_setup : Callback function for buffer setup. + * @q: buffer queue ptr + * @count: number of buffers + * @size: size of the buffer + * + * This callback function is called when reqbuf() is called to adjust + * the buffer count and buffer size + */ +static int vpif_buffer_setup(struct videobuf_queue *q, unsigned int *count, + unsigned int *size) +{ + /* Get the file handle object and channel object */ + struct vpif_fh *fh = q->priv_data; + struct channel_obj *ch = fh->channel; + struct common_obj *common; + + common = &ch->common[VPIF_VIDEO_INDEX]; + + vpif_dbg(2, debug, "vpif_buffer_setup\n"); + + /* If memory type is not mmap, return */ + if (V4L2_MEMORY_MMAP != common->memory) + return 0; + + /* Calculate the size of the buffer */ + *size = config_params.channel_bufsize[ch->channel_id]; + + if (*count < config_params.min_numbuffers) + *count = config_params.min_numbuffers; + return 0; +} + +/** + * vpif_buffer_queue : Callback function to add buffer to DMA queue + * @q: ptr to videobuf_queue + * @vb: ptr to videobuf_buffer + */ +static void vpif_buffer_queue(struct videobuf_queue *q, + struct videobuf_buffer *vb) +{ + /* Get the file handle object and channel object */ + struct vpif_fh *fh = q->priv_data; + struct channel_obj *ch = fh->channel; + struct common_obj *common; + + common = &ch->common[VPIF_VIDEO_INDEX]; + + vpif_dbg(2, debug, "vpif_buffer_queue\n"); + + /* add the buffer to the DMA queue */ + list_add_tail(&vb->queue, &common->dma_queue); + /* Change state of the buffer */ + vb->state = VIDEOBUF_QUEUED; +} + +/** + * vpif_buffer_release : Callback function to free buffer + * @q: buffer queue ptr + * @vb: ptr to video buffer + * + * This function is called from the videobuf layer to free memory + * allocated to the buffers + */ +static void vpif_buffer_release(struct videobuf_queue *q, + struct videobuf_buffer *vb) +{ + /* Get the file handle object and channel object */ + struct vpif_fh *fh = q->priv_data; + struct channel_obj *ch = fh->channel; + struct common_obj *common; + + common = &ch->common[VPIF_VIDEO_INDEX]; + + videobuf_dma_contig_free(q, vb); + vb->state = VIDEOBUF_NEEDS_INIT; +} + +static struct videobuf_queue_ops video_qops = { + .buf_setup = vpif_buffer_setup, + .buf_prepare = vpif_buffer_prepare, + .buf_queue = vpif_buffer_queue, + .buf_release = vpif_buffer_release, +}; + +static u8 channel_first_int[VPIF_NUMBER_OF_OBJECTS][2] = + { {1, 1} }; + +/** + * vpif_process_buffer_complete: process a completed buffer + * @common: ptr to common channel object + * + * This function time stamp the buffer and mark it as DONE. It also + * wake up any process waiting on the QUEUE and set the next buffer + * as current + */ +static void vpif_process_buffer_complete(struct common_obj *common) +{ + do_gettimeofday(&common->cur_frm->ts); + common->cur_frm->state = VIDEOBUF_DONE; + wake_up_interruptible(&common->cur_frm->done); + /* Make curFrm pointing to nextFrm */ + common->cur_frm = common->next_frm; +} + +/** + * vpif_schedule_next_buffer: set next buffer address for capture + * @common : ptr to common channel object + * + * This function will get next buffer from the dma queue and + * set the buffer address in the vpif register for capture. + * the buffer is marked active + */ +static void vpif_schedule_next_buffer(struct common_obj *common) +{ + unsigned long addr = 0; + + common->next_frm = list_entry(common->dma_queue.next, + struct videobuf_buffer, queue); + /* Remove that buffer from the buffer queue */ + list_del(&common->next_frm->queue); + common->next_frm->state = VIDEOBUF_ACTIVE; + if (V4L2_MEMORY_USERPTR == common->memory) + addr = common->next_frm->boff; + else + addr = videobuf_to_dma_contig(common->next_frm); + + /* Set top and bottom field addresses in VPIF registers */ + common->set_addr(addr + common->ytop_off, + addr + common->ybtm_off, + addr + common->ctop_off, + addr + common->cbtm_off); +} + +/** + * vpif_channel_isr : ISR handler for vpif capture + * @irq: irq number + * @dev_id: dev_id ptr + * + * It changes status of the captured buffer, takes next buffer from the queue + * and sets its address in VPIF registers + */ +static irqreturn_t vpif_channel_isr(int irq, void *dev_id) +{ + struct vpif_device *dev = &vpif_obj; + struct common_obj *common; + struct channel_obj *ch; + enum v4l2_field field; + int channel_id = 0; + int fid = -1, i; + + channel_id = *(int *)(dev_id); + ch = dev->dev[channel_id]; + + field = ch->common[VPIF_VIDEO_INDEX].fmt.fmt.pix.field; + + for (i = 0; i < VPIF_NUMBER_OF_OBJECTS; i++) { + common = &ch->common[i]; + /* skip If streaming is not started in this channel */ + if (0 == common->started) + continue; + + /* Check the field format */ + if (1 == ch->vpifparams.std_info.frm_fmt) { + /* Progressive mode */ + if (list_empty(&common->dma_queue)) + continue; + + if (!channel_first_int[i][channel_id]) + vpif_process_buffer_complete(common); + + channel_first_int[i][channel_id] = 0; + + vpif_schedule_next_buffer(common); + + + channel_first_int[i][channel_id] = 0; + } else { + /** + * Interlaced mode. If it is first interrupt, ignore + * it + */ + if (channel_first_int[i][channel_id]) { + channel_first_int[i][channel_id] = 0; + continue; + } + if (0 == i) { + ch->field_id ^= 1; + /* Get field id from VPIF registers */ + fid = vpif_channel_getfid(ch->channel_id); + if (fid != ch->field_id) { + /** + * If field id does not match stored + * field id, make them in sync + */ + if (0 == fid) + ch->field_id = fid; + return IRQ_HANDLED; + } + } + /* device field id and local field id are in sync */ + if (0 == fid) { + /* this is even field */ + if (common->cur_frm == common->next_frm) + continue; + + /* mark the current buffer as done */ + vpif_process_buffer_complete(common); + } else if (1 == fid) { + /* odd field */ + if (list_empty(&common->dma_queue) || + (common->cur_frm != common->next_frm)) + continue; + + vpif_schedule_next_buffer(common); + } + } + } + return IRQ_HANDLED; +} + +/** + * vpif_update_std_info() - update standard related info + * @ch: ptr to channel object + * + * For a given standard selected by application, update values + * in the device data structures + */ +static int vpif_update_std_info(struct channel_obj *ch) +{ + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + struct vpif_params *vpifparams = &ch->vpifparams; + const struct vpif_channel_config_params *config; + struct vpif_channel_config_params *std_info; + struct video_obj *vid_ch = &ch->video; + int index; + + vpif_dbg(2, debug, "vpif_update_std_info\n"); + + std_info = &vpifparams->std_info; + + for (index = 0; index < ARRAY_SIZE(ch_params); index++) { + config = &ch_params[index]; + if (config->stdid & vid_ch->stdid) { + memcpy(std_info, config, sizeof(*config)); + break; + } + } + + /* standard not found */ + if (index == ARRAY_SIZE(ch_params)) + return -EINVAL; + + common->fmt.fmt.pix.width = std_info->width; + common->width = std_info->width; + common->fmt.fmt.pix.height = std_info->height; + common->height = std_info->height; + common->fmt.fmt.pix.bytesperline = std_info->width; + vpifparams->video_params.hpitch = std_info->width; + vpifparams->video_params.storage_mode = std_info->frm_fmt; + return 0; +} + +/** + * vpif_calculate_offsets : This function calculates buffers offsets + * @ch : ptr to channel object + * + * This function calculates buffer offsets for Y and C in the top and + * bottom field + */ +static void vpif_calculate_offsets(struct channel_obj *ch) +{ + unsigned int hpitch, vpitch, sizeimage; + struct video_obj *vid_ch = &(ch->video); + struct vpif_params *vpifparams = &ch->vpifparams; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + enum v4l2_field field = common->fmt.fmt.pix.field; + + vpif_dbg(2, debug, "vpif_calculate_offsets\n"); + + if (V4L2_FIELD_ANY == field) { + if (vpifparams->std_info.frm_fmt) + vid_ch->buf_field = V4L2_FIELD_NONE; + else + vid_ch->buf_field = V4L2_FIELD_INTERLACED; + } else + vid_ch->buf_field = common->fmt.fmt.pix.field; + + if (V4L2_MEMORY_USERPTR == common->memory) + sizeimage = common->fmt.fmt.pix.sizeimage; + else + sizeimage = config_params.channel_bufsize[ch->channel_id]; + + hpitch = common->fmt.fmt.pix.bytesperline; + vpitch = sizeimage / (hpitch * 2); + + if ((V4L2_FIELD_NONE == vid_ch->buf_field) || + (V4L2_FIELD_INTERLACED == vid_ch->buf_field)) { + /* Calculate offsets for Y top, Y Bottom, C top and C Bottom */ + common->ytop_off = 0; + common->ybtm_off = hpitch; + common->ctop_off = sizeimage / 2; + common->cbtm_off = sizeimage / 2 + hpitch; + } else if (V4L2_FIELD_SEQ_TB == vid_ch->buf_field) { + /* Calculate offsets for Y top, Y Bottom, C top and C Bottom */ + common->ytop_off = 0; + common->ybtm_off = sizeimage / 4; + common->ctop_off = sizeimage / 2; + common->cbtm_off = common->ctop_off + sizeimage / 4; + } else if (V4L2_FIELD_SEQ_BT == vid_ch->buf_field) { + /* Calculate offsets for Y top, Y Bottom, C top and C Bottom */ + common->ybtm_off = 0; + common->ytop_off = sizeimage / 4; + common->cbtm_off = sizeimage / 2; + common->ctop_off = common->cbtm_off + sizeimage / 4; + } + if ((V4L2_FIELD_NONE == vid_ch->buf_field) || + (V4L2_FIELD_INTERLACED == vid_ch->buf_field)) + vpifparams->video_params.storage_mode = 1; + else + vpifparams->video_params.storage_mode = 0; + + if (1 == vpifparams->std_info.frm_fmt) + vpifparams->video_params.hpitch = + common->fmt.fmt.pix.bytesperline; + else { + if ((field == V4L2_FIELD_ANY) + || (field == V4L2_FIELD_INTERLACED)) + vpifparams->video_params.hpitch = + common->fmt.fmt.pix.bytesperline * 2; + else + vpifparams->video_params.hpitch = + common->fmt.fmt.pix.bytesperline; + } + + ch->vpifparams.video_params.stdid = vpifparams->std_info.stdid; +} + +/** + * vpif_config_format: configure default frame format in the device + * ch : ptr to channel object + */ +static void vpif_config_format(struct channel_obj *ch) +{ + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + + vpif_dbg(2, debug, "vpif_config_format\n"); + + common->fmt.fmt.pix.field = V4L2_FIELD_ANY; + if (config_params.numbuffers[ch->channel_id] == 0) + common->memory = V4L2_MEMORY_USERPTR; + else + common->memory = V4L2_MEMORY_MMAP; + + common->fmt.fmt.pix.sizeimage + = config_params.channel_bufsize[ch->channel_id]; + + if (ch->vpifparams.iface.if_type == VPIF_IF_RAW_BAYER) + common->fmt.fmt.pix.pixelformat = V4L2_PIX_FMT_SBGGR8; + else + common->fmt.fmt.pix.pixelformat = V4L2_PIX_FMT_YUV422P; + common->fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; +} + +/** + * vpif_get_default_field() - Get default field type based on interface + * @vpif_params - ptr to vpif params + */ +static inline enum v4l2_field vpif_get_default_field( + struct vpif_interface *iface) +{ + return (iface->if_type == VPIF_IF_RAW_BAYER) ? V4L2_FIELD_NONE : + V4L2_FIELD_INTERLACED; +} + +/** + * vpif_check_format() - check given pixel format for compatibility + * @ch - channel ptr + * @pixfmt - Given pixel format + * @update - update the values as per hardware requirement + * + * Check the application pixel format for S_FMT and update the input + * values as per hardware limits for TRY_FMT. The default pixel and + * field format is selected based on interface type. + */ +static int vpif_check_format(struct channel_obj *ch, + struct v4l2_pix_format *pixfmt, + int update) +{ + struct common_obj *common = &(ch->common[VPIF_VIDEO_INDEX]); + struct vpif_params *vpif_params = &ch->vpifparams; + enum v4l2_field field = pixfmt->field; + u32 sizeimage, hpitch, vpitch; + int ret = -EINVAL; + + vpif_dbg(2, debug, "vpif_check_format\n"); + /** + * first check for the pixel format. If if_type is Raw bayer, + * only V4L2_PIX_FMT_SBGGR8 format is supported. Otherwise only + * V4L2_PIX_FMT_YUV422P is supported + */ + if (vpif_params->iface.if_type == VPIF_IF_RAW_BAYER) { + if (pixfmt->pixelformat != V4L2_PIX_FMT_SBGGR8) { + if (!update) { + vpif_dbg(2, debug, "invalid pix format\n"); + goto exit; + } + pixfmt->pixelformat = V4L2_PIX_FMT_SBGGR8; + } + } else { + if (pixfmt->pixelformat != V4L2_PIX_FMT_YUV422P) { + if (!update) { + vpif_dbg(2, debug, "invalid pixel format\n"); + goto exit; + } + pixfmt->pixelformat = V4L2_PIX_FMT_YUV422P; + } + } + + if (!(VPIF_VALID_FIELD(field))) { + if (!update) { + vpif_dbg(2, debug, "invalid field format\n"); + goto exit; + } + /** + * By default use FIELD_NONE for RAW Bayer capture + * and FIELD_INTERLACED for other interfaces + */ + field = vpif_get_default_field(&vpif_params->iface); + } else if (field == V4L2_FIELD_ANY) + /* unsupported field. Use default */ + field = vpif_get_default_field(&vpif_params->iface); + + /* validate the hpitch */ + hpitch = pixfmt->bytesperline; + if (hpitch < vpif_params->std_info.width) { + if (!update) { + vpif_dbg(2, debug, "invalid hpitch\n"); + goto exit; + } + hpitch = vpif_params->std_info.width; + } + + if (V4L2_MEMORY_USERPTR == common->memory) + sizeimage = pixfmt->sizeimage; + else + sizeimage = config_params.channel_bufsize[ch->channel_id]; + + vpitch = sizeimage / (hpitch * 2); + + /* validate the vpitch */ + if (vpitch < vpif_params->std_info.height) { + if (!update) { + vpif_dbg(2, debug, "Invalid vpitch\n"); + goto exit; + } + vpitch = vpif_params->std_info.height; + } + + /* Check for 8 byte alignment */ + if (!ALIGN(hpitch, 8)) { + if (!update) { + vpif_dbg(2, debug, "invalid pitch alignment\n"); + goto exit; + } + /* adjust to next 8 byte boundary */ + hpitch = (((hpitch + 7) / 8) * 8); + } + /* if update is set, modify the bytesperline and sizeimage */ + if (update) { + pixfmt->bytesperline = hpitch; + pixfmt->sizeimage = hpitch * vpitch * 2; + } + /** + * Image width and height is always based on current standard width and + * height + */ + pixfmt->width = common->fmt.fmt.pix.width; + pixfmt->height = common->fmt.fmt.pix.height; + return 0; +exit: + return ret; +} + +/** + * vpif_config_addr() - function to configure buffer address in vpif + * @ch - channel ptr + * @muxmode - channel mux mode + */ +static void vpif_config_addr(struct channel_obj *ch, int muxmode) +{ + struct common_obj *common; + + vpif_dbg(2, debug, "vpif_config_addr\n"); + + common = &(ch->common[VPIF_VIDEO_INDEX]); + + if (VPIF_CHANNEL1_VIDEO == ch->channel_id) + common->set_addr = ch1_set_videobuf_addr; + else if (2 == muxmode) + common->set_addr = ch0_set_videobuf_addr_yc_nmux; + else + common->set_addr = ch0_set_videobuf_addr; +} + +/** + * vpfe_mmap : It is used to map kernel space buffers into user spaces + * @filep: file pointer + * @vma: ptr to vm_area_struct + */ +static int vpif_mmap(struct file *filep, struct vm_area_struct *vma) +{ + /* Get the channel object and file handle object */ + struct vpif_fh *fh = filep->private_data; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &(ch->common[VPIF_VIDEO_INDEX]); + + vpif_dbg(2, debug, "vpif_mmap\n"); + + return videobuf_mmap_mapper(&common->buffer_queue, vma); +} + +/** + * vpif_poll: It is used for select/poll system call + * @filep: file pointer + * @wait: poll table to wait + */ +static unsigned int vpif_poll(struct file *filep, poll_table * wait) +{ + int err = 0; + struct vpif_fh *fh = filep->private_data; + struct channel_obj *channel = fh->channel; + struct common_obj *common = &(channel->common[VPIF_VIDEO_INDEX]); + + vpif_dbg(2, debug, "vpif_poll\n"); + + if (common->started) + err = videobuf_poll_stream(filep, &common->buffer_queue, wait); + + return 0; +} + +/** + * vpif_open : vpif open handler + * @filep: file ptr + * + * It creates object of file handle structure and stores it in private_data + * member of filepointer + */ +static int vpif_open(struct file *filep) +{ + struct vpif_capture_config *config = vpif_dev->platform_data; + struct video_device *vdev = video_devdata(filep); + struct common_obj *common; + struct video_obj *vid_ch; + struct channel_obj *ch; + struct vpif_fh *fh; + int i, ret = 0; + + vpif_dbg(2, debug, "vpif_open\n"); + + ch = video_get_drvdata(vdev); + + vid_ch = &ch->video; + common = &ch->common[VPIF_VIDEO_INDEX]; + + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + if (NULL == ch->curr_subdev_info) { + /** + * search through the sub device to see a registered + * sub device and make it as current sub device + */ + for (i = 0; i < config->subdev_count; i++) { + if (vpif_obj.sd[i]) { + /* the sub device is registered */ + ch->curr_subdev_info = &config->subdev_info[i]; + /* make first input as the current input */ + vid_ch->input_idx = 0; + break; + } + } + if (i == config->subdev_count) { + vpif_err("No sub device registered\n"); + ret = -ENOENT; + goto exit; + } + } + + /* Allocate memory for the file handle object */ + fh = kmalloc(sizeof(struct vpif_fh), GFP_KERNEL); + if (NULL == fh) { + vpif_err("unable to allocate memory for file handle object\n"); + ret = -ENOMEM; + goto exit; + } + + /* store pointer to fh in private_data member of filep */ + filep->private_data = fh; + fh->channel = ch; + fh->initialized = 0; + /* If decoder is not initialized. initialize it */ + if (!ch->initialized) { + fh->initialized = 1; + ch->initialized = 1; + memset(&(ch->vpifparams), 0, sizeof(struct vpif_params)); + } + /* Increment channel usrs counter */ + ch->usrs++; + /* Set io_allowed member to false */ + fh->io_allowed[VPIF_VIDEO_INDEX] = 0; + /* Initialize priority of this instance to default priority */ + fh->prio = V4L2_PRIORITY_UNSET; + v4l2_prio_open(&ch->prio, &fh->prio); +exit: + mutex_unlock(&common->lock); + return ret; +} + +/** + * vpif_release : function to clean up file close + * @filep: file pointer + * + * This function deletes buffer queue, frees the buffers and the vpfe file + * handle + */ +static int vpif_release(struct file *filep) +{ + struct vpif_fh *fh = filep->private_data; + struct channel_obj *ch = fh->channel; + struct common_obj *common; + + vpif_dbg(2, debug, "vpif_release\n"); + + common = &ch->common[VPIF_VIDEO_INDEX]; + + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + /* if this instance is doing IO */ + if (fh->io_allowed[VPIF_VIDEO_INDEX]) { + /* Reset io_usrs member of channel object */ + common->io_usrs = 0; + /* Disable channel as per its device type and channel id */ + if (VPIF_CHANNEL0_VIDEO == ch->channel_id) { + enable_channel0(0); + channel0_intr_enable(0); + } + if ((VPIF_CHANNEL1_VIDEO == ch->channel_id) || + (2 == common->started)) { + enable_channel1(0); + channel1_intr_enable(0); + } + common->started = 0; + /* Free buffers allocated */ + videobuf_queue_cancel(&common->buffer_queue); + videobuf_mmap_free(&common->buffer_queue); + } + + /* Decrement channel usrs counter */ + ch->usrs--; + + /* unlock mutex on channel object */ + mutex_unlock(&common->lock); + + /* Close the priority */ + v4l2_prio_close(&ch->prio, &fh->prio); + + if (fh->initialized) + ch->initialized = 0; + + filep->private_data = NULL; + kfree(fh); + return 0; +} + +/** + * vpif_reqbufs() - request buffer handler + * @file: file ptr + * @priv: file handle + * @reqbuf: request buffer structure ptr + */ +static int vpif_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *reqbuf) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common; + u8 index = 0; + int ret = 0; + + vpif_dbg(2, debug, "vpif_reqbufs\n"); + + /** + * This file handle has not initialized the channel, + * It is not allowed to do settings + */ + if ((VPIF_CHANNEL0_VIDEO == ch->channel_id) + || (VPIF_CHANNEL1_VIDEO == ch->channel_id)) { + if (!fh->initialized) { + vpif_dbg(1, debug, "Channel Busy\n"); + return -EBUSY; + } + } + + if (V4L2_BUF_TYPE_VIDEO_CAPTURE != reqbuf->type) + return -EINVAL; + + index = VPIF_VIDEO_INDEX; + + common = &ch->common[index]; + + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + if (0 != common->io_usrs) { + ret = -EBUSY; + goto reqbuf_exit; + } + + /* Initialize videobuf queue as per the buffer type */ + videobuf_queue_dma_contig_init(&common->buffer_queue, + &video_qops, NULL, + &common->irqlock, + reqbuf->type, + common->fmt.fmt.pix.field, + sizeof(struct videobuf_buffer), fh); + + /* Set io allowed member of file handle to TRUE */ + fh->io_allowed[index] = 1; + /* Increment io usrs member of channel object to 1 */ + common->io_usrs = 1; + /* Store type of memory requested in channel object */ + common->memory = reqbuf->memory; + INIT_LIST_HEAD(&common->dma_queue); + + /* Allocate buffers */ + ret = videobuf_reqbufs(&common->buffer_queue, reqbuf); + +reqbuf_exit: + mutex_unlock(&common->lock); + return ret; +} + +/** + * vpif_querybuf() - query buffer handler + * @file: file ptr + * @priv: file handle + * @buf: v4l2 buffer structure ptr + */ +static int vpif_querybuf(struct file *file, void *priv, + struct v4l2_buffer *buf) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + + vpif_dbg(2, debug, "vpif_querybuf\n"); + + if (common->fmt.type != buf->type) + return -EINVAL; + + if (common->memory != V4L2_MEMORY_MMAP) { + vpif_dbg(1, debug, "Invalid memory\n"); + return -EINVAL; + } + + return videobuf_querybuf(&common->buffer_queue, buf); +} + +/** + * vpif_qbuf() - query buffer handler + * @file: file ptr + * @priv: file handle + * @buf: v4l2 buffer structure ptr + */ +static int vpif_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf) +{ + + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + struct v4l2_buffer tbuf = *buf; + struct videobuf_buffer *buf1; + unsigned long addr = 0; + unsigned long flags; + int ret = 0; + + vpif_dbg(2, debug, "vpif_qbuf\n"); + + if (common->fmt.type != tbuf.type) { + vpif_err("invalid buffer type\n"); + return -EINVAL; + } + + if (!fh->io_allowed[VPIF_VIDEO_INDEX]) { + vpif_err("fh io not allowed \n"); + return -EACCES; + } + + if (!(list_empty(&common->dma_queue)) || + (common->cur_frm != common->next_frm) || + !common->started || + (common->started && (0 == ch->field_id))) + return videobuf_qbuf(&common->buffer_queue, buf); + + /* bufferqueue is empty store buffer address in VPIF registers */ + mutex_lock(&common->buffer_queue.vb_lock); + buf1 = common->buffer_queue.bufs[tbuf.index]; + + if ((buf1->state == VIDEOBUF_QUEUED) || + (buf1->state == VIDEOBUF_ACTIVE)) { + vpif_err("invalid state\n"); + goto qbuf_exit; + } + + switch (buf1->memory) { + case V4L2_MEMORY_MMAP: + if (buf1->baddr == 0) + goto qbuf_exit; + break; + + case V4L2_MEMORY_USERPTR: + if (tbuf.length < buf1->bsize) + goto qbuf_exit; + + if ((VIDEOBUF_NEEDS_INIT != buf1->state) + && (buf1->baddr != tbuf.m.userptr)) + vpif_buffer_release(&common->buffer_queue, buf1); + buf1->baddr = tbuf.m.userptr; + break; + + default: + goto qbuf_exit; + } + + local_irq_save(flags); + ret = vpif_buffer_prepare(&common->buffer_queue, buf1, + common->buffer_queue.field); + if (ret < 0) { + local_irq_restore(flags); + goto qbuf_exit; + } + + buf1->state = VIDEOBUF_ACTIVE; + + if (V4L2_MEMORY_USERPTR == common->memory) + addr = buf1->boff; + else + addr = videobuf_to_dma_contig(buf1); + + common->next_frm = buf1; + common->set_addr(addr + common->ytop_off, + addr + common->ybtm_off, + addr + common->ctop_off, + addr + common->cbtm_off); + + local_irq_restore(flags); + list_add_tail(&buf1->stream, &common->buffer_queue.stream); + mutex_unlock(&common->buffer_queue.vb_lock); + return 0; + +qbuf_exit: + mutex_unlock(&common->buffer_queue.vb_lock); + return -EINVAL; +} + +/** + * vpif_dqbuf() - query buffer handler + * @file: file ptr + * @priv: file handle + * @buf: v4l2 buffer structure ptr + */ +static int vpif_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + + vpif_dbg(2, debug, "vpif_dqbuf\n"); + + return videobuf_dqbuf(&common->buffer_queue, buf, + file->f_flags & O_NONBLOCK); +} + +/** + * vpif_streamon() - streamon handler + * @file: file ptr + * @priv: file handle + * @buftype: v4l2 buffer type + */ +static int vpif_streamon(struct file *file, void *priv, + enum v4l2_buf_type buftype) +{ + + struct vpif_capture_config *config = vpif_dev->platform_data; + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + struct channel_obj *oth_ch = vpif_obj.dev[!ch->channel_id]; + struct vpif_params *vpif; + unsigned long addr = 0; + int ret = 0; + + vpif_dbg(2, debug, "vpif_streamon\n"); + + vpif = &ch->vpifparams; + + if (buftype != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + vpif_dbg(1, debug, "buffer type not supported\n"); + return -EINVAL; + } + + /* If file handle is not allowed IO, return error */ + if (!fh->io_allowed[VPIF_VIDEO_INDEX]) { + vpif_dbg(1, debug, "io not allowed\n"); + return -EACCES; + } + + /* If Streaming is already started, return error */ + if (common->started) { + vpif_dbg(1, debug, "channel->started\n"); + return -EBUSY; + } + + if ((ch->channel_id == VPIF_CHANNEL0_VIDEO && + oth_ch->common[VPIF_VIDEO_INDEX].started && + vpif->std_info.ycmux_mode == 0) || + ((ch->channel_id == VPIF_CHANNEL1_VIDEO) && + (2 == oth_ch->common[VPIF_VIDEO_INDEX].started))) { + vpif_dbg(1, debug, "other channel is being used\n"); + return -EBUSY; + } + + ret = vpif_check_format(ch, &common->fmt.fmt.pix, 0); + if (ret) + return ret; + + /* Enable streamon on the sub device */ + ret = v4l2_subdev_call(vpif_obj.sd[ch->curr_sd_index], video, + s_stream, 1); + + if (ret && (ret != -ENOIOCTLCMD)) { + vpif_dbg(1, debug, "stream on failed in subdev\n"); + return ret; + } + + /* Call videobuf_streamon to start streaming in videobuf */ + ret = videobuf_streamon(&common->buffer_queue); + if (ret) { + vpif_dbg(1, debug, "videobuf_streamon\n"); + return ret; + } + + if (mutex_lock_interruptible(&common->lock)) { + ret = -ERESTARTSYS; + goto streamoff_exit; + } + + /* If buffer queue is empty, return error */ + if (list_empty(&common->dma_queue)) { + vpif_dbg(1, debug, "buffer queue is empty\n"); + ret = -EIO; + goto exit; + } + + /* Get the next frame from the buffer queue */ + common->cur_frm = list_entry(common->dma_queue.next, + struct videobuf_buffer, queue); + common->next_frm = common->cur_frm; + + /* Remove buffer from the buffer queue */ + list_del(&common->cur_frm->queue); + /* Mark state of the current frame to active */ + common->cur_frm->state = VIDEOBUF_ACTIVE; + /* Initialize field_id and started member */ + ch->field_id = 0; + common->started = 1; + + if (V4L2_MEMORY_USERPTR == common->memory) + addr = common->cur_frm->boff; + else + addr = videobuf_to_dma_contig(common->cur_frm); + + /* Calculate the offset for Y and C data in the buffer */ + vpif_calculate_offsets(ch); + + if ((vpif->std_info.frm_fmt && + ((common->fmt.fmt.pix.field != V4L2_FIELD_NONE) && + (common->fmt.fmt.pix.field != V4L2_FIELD_ANY))) || + (!vpif->std_info.frm_fmt && + (common->fmt.fmt.pix.field == V4L2_FIELD_NONE))) { + vpif_dbg(1, debug, "conflict in field format and std format\n"); + ret = -EINVAL; + goto exit; + } + + /* configure 1 or 2 channel mode */ + ret = config->setup_input_channel_mode(vpif->std_info.ycmux_mode); + + if (ret < 0) { + vpif_dbg(1, debug, "can't set vpif channel mode\n"); + goto exit; + } + + /* Call vpif_set_params function to set the parameters and addresses */ + ret = vpif_set_video_params(vpif, ch->channel_id); + + if (ret < 0) { + vpif_dbg(1, debug, "can't set video params\n"); + goto exit; + } + + common->started = ret; + vpif_config_addr(ch, ret); + + common->set_addr(addr + common->ytop_off, + addr + common->ybtm_off, + addr + common->ctop_off, + addr + common->cbtm_off); + + /** + * Set interrupt for both the fields in VPIF Register enable channel in + * VPIF register + */ + if ((VPIF_CHANNEL0_VIDEO == ch->channel_id)) { + channel0_intr_assert(); + channel0_intr_enable(1); + enable_channel0(1); + } + if ((VPIF_CHANNEL1_VIDEO == ch->channel_id) || + (common->started == 2)) { + channel1_intr_assert(); + channel1_intr_enable(1); + enable_channel1(1); + } + channel_first_int[VPIF_VIDEO_INDEX][ch->channel_id] = 1; + mutex_unlock(&common->lock); + return ret; + +exit: + mutex_unlock(&common->lock); +streamoff_exit: + ret = videobuf_streamoff(&common->buffer_queue); + return ret; +} + +/** + * vpif_streamoff() - streamoff handler + * @file: file ptr + * @priv: file handle + * @buftype: v4l2 buffer type + */ +static int vpif_streamoff(struct file *file, void *priv, + enum v4l2_buf_type buftype) +{ + + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + int ret; + + vpif_dbg(2, debug, "vpif_streamoff\n"); + + if (buftype != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + vpif_dbg(1, debug, "buffer type not supported\n"); + return -EINVAL; + } + + /* If io is allowed for this file handle, return error */ + if (!fh->io_allowed[VPIF_VIDEO_INDEX]) { + vpif_dbg(1, debug, "io not allowed\n"); + return -EACCES; + } + + /* If streaming is not started, return error */ + if (!common->started) { + vpif_dbg(1, debug, "channel->started\n"); + return -EINVAL; + } + + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + /* disable channel */ + if (VPIF_CHANNEL0_VIDEO == ch->channel_id) { + enable_channel0(0); + channel0_intr_enable(0); + } else { + enable_channel1(0); + channel1_intr_enable(0); + } + + common->started = 0; + + ret = v4l2_subdev_call(vpif_obj.sd[ch->curr_sd_index], video, + s_stream, 0); + + if (ret && (ret != -ENOIOCTLCMD)) + vpif_dbg(1, debug, "stream off failed in subdev\n"); + + mutex_unlock(&common->lock); + + return videobuf_streamoff(&common->buffer_queue); +} + +/** + * vpif_map_sub_device_to_input() - Maps sub device to input + * @ch - ptr to channel + * @config - ptr to capture configuration + * @input_index - Given input index from application + * @sub_device_index - index into sd table + * + * lookup the sub device information for a given input index. + * we report all the inputs to application. inputs table also + * has sub device name for the each input + */ +static struct vpif_subdev_info *vpif_map_sub_device_to_input( + struct channel_obj *ch, + struct vpif_capture_config *vpif_cfg, + int input_index, + int *sub_device_index) +{ + struct vpif_capture_chan_config *chan_cfg; + struct vpif_subdev_info *subdev_info = NULL; + const char *subdev_name = NULL; + int i; + + vpif_dbg(2, debug, "vpif_map_sub_device_to_input\n"); + + chan_cfg = &vpif_cfg->chan_config[ch->channel_id]; + + /** + * search through the inputs to find the sub device supporting + * the input + */ + for (i = 0; i < chan_cfg->input_count; i++) { + /* For each sub device, loop through input */ + if (i == input_index) { + subdev_name = chan_cfg->inputs[i].subdev_name; + break; + } + } + + /* if reached maximum. return null */ + if (i == chan_cfg->input_count || (NULL == subdev_name)) + return subdev_info; + + /* loop through the sub device list to get the sub device info */ + for (i = 0; i < vpif_cfg->subdev_count; i++) { + subdev_info = &vpif_cfg->subdev_info[i]; + if (!strcmp(subdev_info->name, subdev_name)) + break; + } + + if (i == vpif_cfg->subdev_count) + return subdev_info; + + /* check if the sub device is registered */ + if (NULL == vpif_obj.sd[i]) + return NULL; + + *sub_device_index = i; + return subdev_info; +} + +/** + * vpif_querystd() - querystd handler + * @file: file ptr + * @priv: file handle + * @std_id: ptr to std id + * + * This function is called to detect standard at the selected input + */ +static int vpif_querystd(struct file *file, void *priv, v4l2_std_id *std_id) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + int ret = 0; + + vpif_dbg(2, debug, "vpif_querystd\n"); + + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + /* Call querystd function of decoder device */ + ret = v4l2_subdev_call(vpif_obj.sd[ch->curr_sd_index], video, + querystd, std_id); + if (ret < 0) + vpif_dbg(1, debug, "Failed to set standard for sub devices\n"); + + mutex_unlock(&common->lock); + return ret; +} + +/** + * vpif_g_std() - get STD handler + * @file: file ptr + * @priv: file handle + * @std_id: ptr to std id + */ +static int vpif_g_std(struct file *file, void *priv, v4l2_std_id *std) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + + vpif_dbg(2, debug, "vpif_g_std\n"); + + *std = ch->video.stdid; + return 0; +} + +/** + * vpif_s_std() - set STD handler + * @file: file ptr + * @priv: file handle + * @std_id: ptr to std id + */ +static int vpif_s_std(struct file *file, void *priv, v4l2_std_id *std_id) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + int ret = 0; + + vpif_dbg(2, debug, "vpif_s_std\n"); + + if (common->started) { + vpif_err("streaming in progress\n"); + return -EBUSY; + } + + if ((VPIF_CHANNEL0_VIDEO == ch->channel_id) || + (VPIF_CHANNEL1_VIDEO == ch->channel_id)) { + if (!fh->initialized) { + vpif_dbg(1, debug, "Channel Busy\n"); + return -EBUSY; + } + } + + ret = v4l2_prio_check(&ch->prio, &fh->prio); + if (0 != ret) + return ret; + + fh->initialized = 1; + + /* Call encoder subdevice function to set the standard */ + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + ch->video.stdid = *std_id; + + /* Get the information about the standard */ + if (vpif_update_std_info(ch)) { + ret = -EINVAL; + vpif_err("Error getting the standard info\n"); + goto s_std_exit; + } + + /* Configure the default format information */ + vpif_config_format(ch); + + /* set standard in the sub device */ + ret = v4l2_subdev_call(vpif_obj.sd[ch->curr_sd_index], core, + s_std, *std_id); + if (ret < 0) + vpif_dbg(1, debug, "Failed to set standard for sub devices\n"); + +s_std_exit: + mutex_unlock(&common->lock); + return ret; +} + +/** + * vpif_enum_input() - ENUMINPUT handler + * @file: file ptr + * @priv: file handle + * @input: ptr to input structure + */ +static int vpif_enum_input(struct file *file, void *priv, + struct v4l2_input *input) +{ + + struct vpif_capture_config *config = vpif_dev->platform_data; + struct vpif_capture_chan_config *chan_cfg; + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + + chan_cfg = &config->chan_config[ch->channel_id]; + + if (input->index >= chan_cfg->input_count) { + vpif_dbg(1, debug, "Invalid input index\n"); + return -EINVAL; + } + + memcpy(input, &chan_cfg->inputs[input->index].input, + sizeof(*input)); + return 0; +} + +/** + * vpif_g_input() - Get INPUT handler + * @file: file ptr + * @priv: file handle + * @index: ptr to input index + */ +static int vpif_g_input(struct file *file, void *priv, unsigned int *index) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct video_obj *vid_ch = &ch->video; + + *index = vid_ch->input_idx; + + return 0; +} + +/** + * vpif_s_input() - Set INPUT handler + * @file: file ptr + * @priv: file handle + * @index: input index + */ +static int vpif_s_input(struct file *file, void *priv, unsigned int index) +{ + struct vpif_capture_config *config = vpif_dev->platform_data; + struct vpif_capture_chan_config *chan_cfg; + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + struct video_obj *vid_ch = &ch->video; + struct vpif_subdev_info *subdev_info; + int ret = 0, sd_index = 0; + u32 input = 0, output = 0; + + chan_cfg = &config->chan_config[ch->channel_id]; + + if (common->started) { + vpif_err("Streaming in progress\n"); + return -EBUSY; + } + + if ((VPIF_CHANNEL0_VIDEO == ch->channel_id) || + (VPIF_CHANNEL1_VIDEO == ch->channel_id)) { + if (!fh->initialized) { + vpif_dbg(1, debug, "Channel Busy\n"); + return -EBUSY; + } + } + + ret = v4l2_prio_check(&ch->prio, &fh->prio); + if (0 != ret) + return ret; + + fh->initialized = 1; + subdev_info = vpif_map_sub_device_to_input(ch, config, index, + &sd_index); + if (NULL == subdev_info) { + vpif_dbg(1, debug, + "couldn't lookup sub device for the input index\n"); + return -EINVAL; + } + + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + /* first setup input path from sub device to vpif */ + if (config->setup_input_path) { + ret = config->setup_input_path(ch->channel_id, + subdev_info->name); + if (ret < 0) { + vpif_dbg(1, debug, "couldn't setup input path for the" + " sub device %s, for input index %d\n", + subdev_info->name, index); + goto exit; + } + } + + if (subdev_info->can_route) { + input = subdev_info->input; + output = subdev_info->output; + ret = v4l2_subdev_call(vpif_obj.sd[sd_index], video, s_routing, + input, output, 0); + if (ret < 0) { + vpif_dbg(1, debug, "Failed to set input\n"); + goto exit; + } + } + vid_ch->input_idx = index; + ch->curr_subdev_info = subdev_info; + ch->curr_sd_index = sd_index; + /* copy interface parameters to vpif */ + ch->vpifparams.iface = subdev_info->vpif_if; + + /* update tvnorms from the sub device input info */ + ch->video_dev->tvnorms = chan_cfg->inputs[index].input.std; + +exit: + mutex_unlock(&common->lock); + return ret; +} + +/** + * vpif_enum_fmt_vid_cap() - ENUM_FMT handler + * @file: file ptr + * @priv: file handle + * @index: input index + */ +static int vpif_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *fmt) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + + if (fmt->index != 0) { + vpif_dbg(1, debug, "Invalid format index\n"); + return -EINVAL; + } + + /* Fill in the information about format */ + if (ch->vpifparams.iface.if_type == VPIF_IF_RAW_BAYER) { + fmt->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + strcpy(fmt->description, "Raw Mode -Bayer Pattern GrRBGb"); + fmt->pixelformat = V4L2_PIX_FMT_SBGGR8; + } else { + fmt->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + strcpy(fmt->description, "YCbCr4:2:2 YC Planar"); + fmt->pixelformat = V4L2_PIX_FMT_YUV422P; + } + return 0; +} + +/** + * vpif_try_fmt_vid_cap() - TRY_FMT handler + * @file: file ptr + * @priv: file handle + * @fmt: ptr to v4l2 format structure + */ +static int vpif_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *fmt) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct v4l2_pix_format *pixfmt = &fmt->fmt.pix; + + return vpif_check_format(ch, pixfmt, 1); +} + + +/** + * vpif_g_fmt_vid_cap() - Set INPUT handler + * @file: file ptr + * @priv: file handle + * @fmt: ptr to v4l2 format structure + */ +static int vpif_g_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *fmt) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + + /* Check the validity of the buffer type */ + if (common->fmt.type != fmt->type) + return -EINVAL; + + /* Fill in the information about format */ + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + *fmt = common->fmt; + mutex_unlock(&common->lock); + return 0; +} + +/** + * vpif_s_fmt_vid_cap() - Set FMT handler + * @file: file ptr + * @priv: file handle + * @fmt: ptr to v4l2 format structure + */ +static int vpif_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *fmt) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + struct v4l2_pix_format *pixfmt; + int ret = 0; + + vpif_dbg(2, debug, "VIDIOC_S_FMT\n"); + + /* If streaming is started, return error */ + if (common->started) { + vpif_dbg(1, debug, "Streaming is started\n"); + return -EBUSY; + } + + if ((VPIF_CHANNEL0_VIDEO == ch->channel_id) || + (VPIF_CHANNEL1_VIDEO == ch->channel_id)) { + if (!fh->initialized) { + vpif_dbg(1, debug, "Channel Busy\n"); + return -EBUSY; + } + } + + ret = v4l2_prio_check(&ch->prio, &fh->prio); + if (0 != ret) + return ret; + + fh->initialized = 1; + + pixfmt = &fmt->fmt.pix; + /* Check for valid field format */ + ret = vpif_check_format(ch, pixfmt, 0); + + if (ret) + return ret; + /* store the format in the channel object */ + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + common->fmt = *fmt; + mutex_unlock(&common->lock); + + return 0; +} + +/** + * vpif_querycap() - QUERYCAP handler + * @file: file ptr + * @priv: file handle + * @cap: ptr to v4l2_capability structure + */ +static int vpif_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct vpif_capture_config *config = vpif_dev->platform_data; + + cap->version = VPIF_CAPTURE_VERSION_CODE; + cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + strlcpy(cap->driver, "vpif capture", sizeof(cap->driver)); + strlcpy(cap->bus_info, "DM646x Platform", sizeof(cap->bus_info)); + strlcpy(cap->card, config->card_name, sizeof(cap->card)); + + return 0; +} + +/** + * vpif_g_priority() - get priority handler + * @file: file ptr + * @priv: file handle + * @prio: ptr to v4l2_priority structure + */ +static int vpif_g_priority(struct file *file, void *priv, + enum v4l2_priority *prio) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + + *prio = v4l2_prio_max(&ch->prio); + + return 0; +} + +/** + * vpif_s_priority() - set priority handler + * @file: file ptr + * @priv: file handle + * @prio: ptr to v4l2_priority structure + */ +static int vpif_s_priority(struct file *file, void *priv, enum v4l2_priority p) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + + return v4l2_prio_change(&ch->prio, &fh->prio, p); +} + +/** + * vpif_cropcap() - cropcap handler + * @file: file ptr + * @priv: file handle + * @crop: ptr to v4l2_cropcap structure + */ +static int vpif_cropcap(struct file *file, void *priv, + struct v4l2_cropcap *crop) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + + if (V4L2_BUF_TYPE_VIDEO_CAPTURE != crop->type) + return -EINVAL; + + crop->bounds.left = 0; + crop->bounds.top = 0; + crop->bounds.height = common->height; + crop->bounds.width = common->width; + crop->defrect = crop->bounds; + return 0; +} + +/* vpif capture ioctl operations */ +static const struct v4l2_ioctl_ops vpif_ioctl_ops = { + .vidioc_querycap = vpif_querycap, + .vidioc_g_priority = vpif_g_priority, + .vidioc_s_priority = vpif_s_priority, + .vidioc_enum_fmt_vid_cap = vpif_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vpif_g_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vpif_s_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vpif_try_fmt_vid_cap, + .vidioc_enum_input = vpif_enum_input, + .vidioc_s_input = vpif_s_input, + .vidioc_g_input = vpif_g_input, + .vidioc_reqbufs = vpif_reqbufs, + .vidioc_querybuf = vpif_querybuf, + .vidioc_querystd = vpif_querystd, + .vidioc_s_std = vpif_s_std, + .vidioc_g_std = vpif_g_std, + .vidioc_qbuf = vpif_qbuf, + .vidioc_dqbuf = vpif_dqbuf, + .vidioc_streamon = vpif_streamon, + .vidioc_streamoff = vpif_streamoff, + .vidioc_cropcap = vpif_cropcap, +}; + +/* vpif file operations */ +static struct v4l2_file_operations vpif_fops = { + .owner = THIS_MODULE, + .open = vpif_open, + .release = vpif_release, + .ioctl = video_ioctl2, + .mmap = vpif_mmap, + .poll = vpif_poll +}; + +/* vpif video template */ +static struct video_device vpif_video_template = { + .name = "vpif", + .fops = &vpif_fops, + .minor = -1, + .ioctl_ops = &vpif_ioctl_ops, +}; + +/** + * initialize_vpif() - Initialize vpif data structures + * + * Allocate memory for data structures and initialize them + */ +static int initialize_vpif(void) +{ + int err = 0, i, j; + int free_channel_objects_index; + + /* Default number of buffers should be 3 */ + if ((ch0_numbuffers > 0) && + (ch0_numbuffers < config_params.min_numbuffers)) + ch0_numbuffers = config_params.min_numbuffers; + if ((ch1_numbuffers > 0) && + (ch1_numbuffers < config_params.min_numbuffers)) + ch1_numbuffers = config_params.min_numbuffers; + + /* Set buffer size to min buffers size if it is invalid */ + if (ch0_bufsize < config_params.min_bufsize[VPIF_CHANNEL0_VIDEO]) + ch0_bufsize = + config_params.min_bufsize[VPIF_CHANNEL0_VIDEO]; + if (ch1_bufsize < config_params.min_bufsize[VPIF_CHANNEL1_VIDEO]) + ch1_bufsize = + config_params.min_bufsize[VPIF_CHANNEL1_VIDEO]; + + config_params.numbuffers[VPIF_CHANNEL0_VIDEO] = ch0_numbuffers; + config_params.numbuffers[VPIF_CHANNEL1_VIDEO] = ch1_numbuffers; + if (ch0_numbuffers) { + config_params.channel_bufsize[VPIF_CHANNEL0_VIDEO] + = ch0_bufsize; + } + if (ch1_numbuffers) { + config_params.channel_bufsize[VPIF_CHANNEL1_VIDEO] + = ch1_bufsize; + } + + /* Allocate memory for six channel objects */ + for (i = 0; i < VPIF_CAPTURE_MAX_DEVICES; i++) { + vpif_obj.dev[i] = + kzalloc(sizeof(*vpif_obj.dev[i]), GFP_KERNEL); + /* If memory allocation fails, return error */ + if (!vpif_obj.dev[i]) { + free_channel_objects_index = i; + err = -ENOMEM; + goto vpif_init_free_channel_objects; + } + } + return 0; + +vpif_init_free_channel_objects: + for (j = 0; j < free_channel_objects_index; j++) + kfree(vpif_obj.dev[j]); + return err; +} + +/** + * vpif_probe : This function probes the vpif capture driver + * @pdev: platform device pointer + * + * This creates device entries by register itself to the V4L2 driver and + * initializes fields of each channel objects + */ +static __init int vpif_probe(struct platform_device *pdev) +{ + struct vpif_subdev_info *subdevdata; + struct vpif_capture_config *config; + int i, j, k, m, q, err; + struct i2c_adapter *i2c_adap; + struct channel_obj *ch; + struct common_obj *common; + struct video_device *vfd; + struct resource *res; + int subdev_count; + + vpif_dev = &pdev->dev; + + err = initialize_vpif(); + if (err) { + v4l2_err(vpif_dev->driver, "Error initializing vpif\n"); + return err; + } + + k = 0; + while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, k))) { + for (i = res->start; i <= res->end; i++) { + if (request_irq(i, vpif_channel_isr, IRQF_DISABLED, + "DM646x_Capture", + (void *)(&vpif_obj.dev[k]->channel_id))) { + err = -EBUSY; + i--; + goto vpif_int_err; + } + } + k++; + } + + for (i = 0; i < VPIF_CAPTURE_MAX_DEVICES; i++) { + /* Get the pointer to the channel object */ + ch = vpif_obj.dev[i]; + /* Allocate memory for video device */ + vfd = video_device_alloc(); + if (NULL == vfd) { + for (j = 0; j < i; j++) { + ch = vpif_obj.dev[j]; + video_device_release(ch->video_dev); + } + err = -ENOMEM; + goto vpif_dev_alloc_err; + } + + /* Initialize field of video device */ + *vfd = vpif_video_template; + vfd->v4l2_dev = &vpif_obj.v4l2_dev; + vfd->release = video_device_release; + snprintf(vfd->name, sizeof(vfd->name), + "DM646x_VPIFCapture_DRIVER_V%d.%d.%d", + (VPIF_CAPTURE_VERSION_CODE >> 16) & 0xff, + (VPIF_CAPTURE_VERSION_CODE >> 8) & 0xff, + (VPIF_CAPTURE_VERSION_CODE) & 0xff); + /* Set video_dev to the video device */ + ch->video_dev = vfd; + } + + for (j = 0; j < VPIF_CAPTURE_MAX_DEVICES; j++) { + ch = vpif_obj.dev[j]; + ch->channel_id = j; + common = &(ch->common[VPIF_VIDEO_INDEX]); + spin_lock_init(&common->irqlock); + mutex_init(&common->lock); + /* Initialize prio member of channel object */ + v4l2_prio_init(&ch->prio); + err = video_register_device(ch->video_dev, + VFL_TYPE_GRABBER, (j ? 1 : 0)); + if (err) + goto probe_out; + + video_set_drvdata(ch->video_dev, ch); + + } + + i2c_adap = i2c_get_adapter(1); + config = pdev->dev.platform_data; + + subdev_count = config->subdev_count; + vpif_obj.sd = kmalloc(sizeof(struct v4l2_subdev *) * subdev_count, + GFP_KERNEL); + if (vpif_obj.sd == NULL) { + vpif_err("unable to allocate memory for subdevice pointers\n"); + err = -ENOMEM; + goto probe_out; + } + + err = v4l2_device_register(vpif_dev, &vpif_obj.v4l2_dev); + if (err) { + v4l2_err(vpif_dev->driver, "Error registering v4l2 device\n"); + goto probe_subdev_out; + } + + for (i = 0; i < subdev_count; i++) { + subdevdata = &config->subdev_info[i]; + vpif_obj.sd[i] = + v4l2_i2c_new_subdev_board(&vpif_obj.v4l2_dev, + i2c_adap, + subdevdata->name, + &subdevdata->board_info, + NULL); + + if (!vpif_obj.sd[i]) { + vpif_err("Error registering v4l2 subdevice\n"); + goto probe_subdev_out; + } + v4l2_info(&vpif_obj.v4l2_dev, "registered sub device %s\n", + subdevdata->name); + + if (vpif_obj.sd[i]) + vpif_obj.sd[i]->grp_id = 1 << i; + } + v4l2_info(&vpif_obj.v4l2_dev, "DM646x VPIF Capture driver" + " initialized\n"); + + return 0; + +probe_subdev_out: + /* free sub devices memory */ + kfree(vpif_obj.sd); + + j = VPIF_CAPTURE_MAX_DEVICES; +probe_out: + v4l2_device_unregister(&vpif_obj.v4l2_dev); + for (k = 0; k < j; k++) { + /* Get the pointer to the channel object */ + ch = vpif_obj.dev[k]; + /* Unregister video device */ + video_unregister_device(ch->video_dev); + } + +vpif_dev_alloc_err: + k = VPIF_CAPTURE_MAX_DEVICES-1; + res = platform_get_resource(pdev, IORESOURCE_IRQ, k); + i = res->end; + +vpif_int_err: + for (q = k; q >= 0; q--) { + for (m = i; m >= (int)res->start; m--) + free_irq(m, (void *)(&vpif_obj.dev[q]->channel_id)); + + res = platform_get_resource(pdev, IORESOURCE_IRQ, q-1); + if (res) + i = res->end; + } + return err; +} + +/** + * vpif_remove() - driver remove handler + * @device: ptr to platform device structure + * + * The vidoe device is unregistered + */ +static int vpif_remove(struct platform_device *device) +{ + int i; + struct channel_obj *ch; + + v4l2_device_unregister(&vpif_obj.v4l2_dev); + + /* un-register device */ + for (i = 0; i < VPIF_CAPTURE_MAX_DEVICES; i++) { + /* Get the pointer to the channel object */ + ch = vpif_obj.dev[i]; + /* Unregister video device */ + video_unregister_device(ch->video_dev); + } + return 0; +} + +/** + * vpif_suspend: vpif device suspend + * + * TODO: Add suspend code here + */ +static int +vpif_suspend(struct device *dev) +{ + return -1; +} + +/** + * vpif_resume: vpif device suspend + * + * TODO: Add resume code here + */ +static int +vpif_resume(struct device *dev) +{ + return -1; +} + +static struct dev_pm_ops vpif_dev_pm_ops = { + .suspend = vpif_suspend, + .resume = vpif_resume, +}; + +static struct platform_driver vpif_driver = { + .driver = { + .name = "vpif_capture", + .owner = THIS_MODULE, + .pm = &vpif_dev_pm_ops, + }, + .probe = vpif_probe, + .remove = vpif_remove, +}; + +/** + * vpif_init: initialize the vpif driver + * + * This function registers device and driver to the kernel, requests irq + * handler and allocates memory + * for channel objects + */ +static __init int vpif_init(void) +{ + return platform_driver_register(&vpif_driver); +} + +/** + * vpif_cleanup : This function clean up the vpif capture resources + * + * This will un-registers device and driver to the kernel, frees + * requested irq handler and de-allocates memory allocated for channel + * objects. + */ +static void vpif_cleanup(void) +{ + struct platform_device *pdev; + struct resource *res; + int irq_num; + int i = 0; + + pdev = container_of(vpif_dev, struct platform_device, dev); + while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, i))) { + for (irq_num = res->start; irq_num <= res->end; irq_num++) + free_irq(irq_num, + (void *)(&vpif_obj.dev[i]->channel_id)); + i++; + } + + platform_driver_unregister(&vpif_driver); + + kfree(vpif_obj.sd); + for (i = 0; i < VPIF_CAPTURE_MAX_DEVICES; i++) + kfree(vpif_obj.dev[i]); +} + +/* Function for module initialization and cleanup */ +module_init(vpif_init); +module_exit(vpif_cleanup); diff --git a/drivers/media/video/davinci/vpif_capture.h b/drivers/media/video/davinci/vpif_capture.h new file mode 100644 index 000000000000..4e12ec8cac6f --- /dev/null +++ b/drivers/media/video/davinci/vpif_capture.h @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2009 Texas Instruments Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef VPIF_CAPTURE_H +#define VPIF_CAPTURE_H + +#ifdef __KERNEL__ + +/* Header files */ +#include +#include +#include +#include +#include +#include +#include + +#include "vpif.h" + +/* Macros */ +#define VPIF_MAJOR_RELEASE 0 +#define VPIF_MINOR_RELEASE 0 +#define VPIF_BUILD 1 +#define VPIF_CAPTURE_VERSION_CODE ((VPIF_MAJOR_RELEASE << 16) | \ + (VPIF_MINOR_RELEASE << 8) | VPIF_BUILD) + +#define VPIF_VALID_FIELD(field) (((V4L2_FIELD_ANY == field) || \ + (V4L2_FIELD_NONE == field)) || \ + (((V4L2_FIELD_INTERLACED == field) || \ + (V4L2_FIELD_SEQ_TB == field)) || \ + (V4L2_FIELD_SEQ_BT == field))) + +#define VPIF_CAPTURE_MAX_DEVICES 2 +#define VPIF_VIDEO_INDEX 0 +#define VPIF_NUMBER_OF_OBJECTS 1 + +/* Enumerated data type to give id to each device per channel */ +enum vpif_channel_id { + VPIF_CHANNEL0_VIDEO = 0, + VPIF_CHANNEL1_VIDEO, +}; + +struct video_obj { + enum v4l2_field buf_field; + /* Currently selected or default standard */ + v4l2_std_id stdid; + /* This is to track the last input that is passed to application */ + u32 input_idx; +}; + +struct common_obj { + /* Pointer pointing to current v4l2_buffer */ + struct videobuf_buffer *cur_frm; + /* Pointer pointing to current v4l2_buffer */ + struct videobuf_buffer *next_frm; + /* + * This field keeps track of type of buffer exchange mechanism + * user has selected + */ + enum v4l2_memory memory; + /* Used to store pixel format */ + struct v4l2_format fmt; + /* Buffer queue used in video-buf */ + struct videobuf_queue buffer_queue; + /* Queue of filled frames */ + struct list_head dma_queue; + /* Used in video-buf */ + spinlock_t irqlock; + /* lock used to access this structure */ + struct mutex lock; + /* number of users performing IO */ + u32 io_usrs; + /* Indicates whether streaming started */ + u8 started; + /* Function pointer to set the addresses */ + void (*set_addr) (unsigned long, unsigned long, unsigned long, + unsigned long); + /* offset where Y top starts from the starting of the buffer */ + u32 ytop_off; + /* offset where Y bottom starts from the starting of the buffer */ + u32 ybtm_off; + /* offset where C top starts from the starting of the buffer */ + u32 ctop_off; + /* offset where C bottom starts from the starting of the buffer */ + u32 cbtm_off; + /* Indicates width of the image data */ + u32 width; + /* Indicates height of the image data */ + u32 height; +}; + +struct channel_obj { + /* Identifies video device for this channel */ + struct video_device *video_dev; + /* Used to keep track of state of the priority */ + struct v4l2_prio_state prio; + /* number of open instances of the channel */ + int usrs; + /* Indicates id of the field which is being displayed */ + u32 field_id; + /* flag to indicate whether decoder is initialized */ + u8 initialized; + /* Identifies channel */ + enum vpif_channel_id channel_id; + /* index into sd table */ + int curr_sd_index; + /* ptr to current sub device information */ + struct vpif_subdev_info *curr_subdev_info; + /* vpif configuration params */ + struct vpif_params vpifparams; + /* common object array */ + struct common_obj common[VPIF_NUMBER_OF_OBJECTS]; + /* video object */ + struct video_obj video; +}; + +/* File handle structure */ +struct vpif_fh { + /* pointer to channel object for opened device */ + struct channel_obj *channel; + /* Indicates whether this file handle is doing IO */ + u8 io_allowed[VPIF_NUMBER_OF_OBJECTS]; + /* Used to keep track priority of this instance */ + enum v4l2_priority prio; + /* Used to indicate channel is initialize or not */ + u8 initialized; +}; + +struct vpif_device { + struct v4l2_device v4l2_dev; + struct channel_obj *dev[VPIF_CAPTURE_NUM_CHANNELS]; + struct v4l2_subdev **sd; +}; + +struct vpif_config_params { + u8 min_numbuffers; + u8 numbuffers[VPIF_CAPTURE_NUM_CHANNELS]; + s8 device_type; + u32 min_bufsize[VPIF_CAPTURE_NUM_CHANNELS]; + u32 channel_bufsize[VPIF_CAPTURE_NUM_CHANNELS]; + u8 default_device[VPIF_CAPTURE_NUM_CHANNELS]; + u8 max_device_type; +}; +/* Struct which keeps track of the line numbers for the sliced vbi service */ +struct vpif_service_line { + u16 service_id; + u16 service_line[2]; +}; +#endif /* End of __KERNEL__ */ +#endif /* VPIF_CAPTURE_H */ diff --git a/drivers/media/video/davinci/vpif_display.c b/drivers/media/video/davinci/vpif_display.c new file mode 100644 index 000000000000..c015da813dda --- /dev/null +++ b/drivers/media/video/davinci/vpif_display.c @@ -0,0 +1,1656 @@ +/* + * vpif-display - VPIF display driver + * Display driver for TI DaVinci VPIF + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed .as is. WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include + +#include "vpif_display.h" +#include "vpif.h" + +MODULE_DESCRIPTION("TI DaVinci VPIF Display driver"); +MODULE_LICENSE("GPL"); + +#define DM646X_V4L2_STD (V4L2_STD_525_60 | V4L2_STD_625_50) + +#define vpif_err(fmt, arg...) v4l2_err(&vpif_obj.v4l2_dev, fmt, ## arg) +#define vpif_dbg(level, debug, fmt, arg...) \ + v4l2_dbg(level, debug, &vpif_obj.v4l2_dev, fmt, ## arg) + +static int debug = 1; +static u32 ch2_numbuffers = 3; +static u32 ch3_numbuffers = 3; +static u32 ch2_bufsize = 1920 * 1080 * 2; +static u32 ch3_bufsize = 720 * 576 * 2; + +module_param(debug, int, 0644); +module_param(ch2_numbuffers, uint, S_IRUGO); +module_param(ch3_numbuffers, uint, S_IRUGO); +module_param(ch2_bufsize, uint, S_IRUGO); +module_param(ch3_bufsize, uint, S_IRUGO); + +MODULE_PARM_DESC(debug, "Debug level 0-1"); +MODULE_PARM_DESC(ch2_numbuffers, "Channel2 buffer count (default:3)"); +MODULE_PARM_DESC(ch3_numbuffers, "Channel3 buffer count (default:3)"); +MODULE_PARM_DESC(ch2_bufsize, "Channel2 buffer size (default:1920 x 1080 x 2)"); +MODULE_PARM_DESC(ch3_bufsize, "Channel3 buffer size (default:720 x 576 x 2)"); + +static struct vpif_config_params config_params = { + .min_numbuffers = 3, + .numbuffers[0] = 3, + .numbuffers[1] = 3, + .min_bufsize[0] = 720 * 480 * 2, + .min_bufsize[1] = 720 * 480 * 2, + .channel_bufsize[0] = 1920 * 1080 * 2, + .channel_bufsize[1] = 720 * 576 * 2, +}; + +static struct vpif_device vpif_obj = { {NULL} }; +static struct device *vpif_dev; + +static const struct vpif_channel_config_params ch_params[] = { + { + "NTSC", 720, 480, 30, 0, 1, 268, 1440, 1, 23, 263, 266, + 286, 525, 525, 0, 1, 0, V4L2_STD_525_60, + }, + { + "PAL", 720, 576, 25, 0, 1, 280, 1440, 1, 23, 311, 313, + 336, 624, 625, 0, 1, 0, V4L2_STD_625_50, + }, +}; + +/* + * vpif_uservirt_to_phys: This function is used to convert user + * space virtual address to physical address. + */ +static u32 vpif_uservirt_to_phys(u32 virtp) +{ + struct mm_struct *mm = current->mm; + unsigned long physp = 0; + struct vm_area_struct *vma; + + vma = find_vma(mm, virtp); + + /* For kernel direct-mapped memory, take the easy way */ + if (virtp >= PAGE_OFFSET) { + physp = virt_to_phys((void *)virtp); + } else if (vma && (vma->vm_flags & VM_IO) && (vma->vm_pgoff)) { + /* this will catch, kernel-allocated, mmaped-to-usermode addr */ + physp = (vma->vm_pgoff << PAGE_SHIFT) + (virtp - vma->vm_start); + } else { + /* otherwise, use get_user_pages() for general userland pages */ + int res, nr_pages = 1; + struct page *pages; + down_read(¤t->mm->mmap_sem); + + res = get_user_pages(current, current->mm, + virtp, nr_pages, 1, 0, &pages, NULL); + up_read(¤t->mm->mmap_sem); + + if (res == nr_pages) { + physp = __pa(page_address(&pages[0]) + + (virtp & ~PAGE_MASK)); + } else { + vpif_err("get_user_pages failed\n"); + return 0; + } + } + + return physp; +} + +/* + * buffer_prepare: This is the callback function called from videobuf_qbuf() + * function the buffer is prepared and user space virtual address is converted + * into physical address + */ +static int vpif_buffer_prepare(struct videobuf_queue *q, + struct videobuf_buffer *vb, + enum v4l2_field field) +{ + struct vpif_fh *fh = q->priv_data; + struct common_obj *common; + unsigned long addr; + + common = &fh->channel->common[VPIF_VIDEO_INDEX]; + if (VIDEOBUF_NEEDS_INIT == vb->state) { + vb->width = common->width; + vb->height = common->height; + vb->size = vb->width * vb->height; + vb->field = field; + } + vb->state = VIDEOBUF_PREPARED; + + /* if user pointer memory mechanism is used, get the physical + * address of the buffer */ + if (V4L2_MEMORY_USERPTR == common->memory) { + if (!vb->baddr) { + vpif_err("buffer_address is 0\n"); + return -EINVAL; + } + + vb->boff = vpif_uservirt_to_phys(vb->baddr); + if (!ISALIGNED(vb->boff)) + goto buf_align_exit; + } + + addr = vb->boff; + if (q->streaming && (V4L2_BUF_TYPE_SLICED_VBI_OUTPUT != q->type)) { + if (!ISALIGNED(addr + common->ytop_off) || + !ISALIGNED(addr + common->ybtm_off) || + !ISALIGNED(addr + common->ctop_off) || + !ISALIGNED(addr + common->cbtm_off)) + goto buf_align_exit; + } + return 0; + +buf_align_exit: + vpif_err("buffer offset not aligned to 8 bytes\n"); + return -EINVAL; +} + +/* + * vpif_buffer_setup: This function allocates memory for the buffers + */ +static int vpif_buffer_setup(struct videobuf_queue *q, unsigned int *count, + unsigned int *size) +{ + struct vpif_fh *fh = q->priv_data; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + + if (V4L2_MEMORY_MMAP != common->memory) + return 0; + + *size = config_params.channel_bufsize[ch->channel_id]; + if (*count < config_params.min_numbuffers) + *count = config_params.min_numbuffers; + + return 0; +} + +/* + * vpif_buffer_queue: This function adds the buffer to DMA queue + */ +static void vpif_buffer_queue(struct videobuf_queue *q, + struct videobuf_buffer *vb) +{ + struct vpif_fh *fh = q->priv_data; + struct common_obj *common; + + common = &fh->channel->common[VPIF_VIDEO_INDEX]; + + /* add the buffer to the DMA queue */ + list_add_tail(&vb->queue, &common->dma_queue); + vb->state = VIDEOBUF_QUEUED; +} + +/* + * vpif_buffer_release: This function is called from the videobuf layer to + * free memory allocated to the buffers + */ +static void vpif_buffer_release(struct videobuf_queue *q, + struct videobuf_buffer *vb) +{ + struct vpif_fh *fh = q->priv_data; + struct channel_obj *ch = fh->channel; + struct common_obj *common; + unsigned int buf_size = 0; + + common = &ch->common[VPIF_VIDEO_INDEX]; + + videobuf_dma_contig_free(q, vb); + vb->state = VIDEOBUF_NEEDS_INIT; + + if (V4L2_MEMORY_MMAP != common->memory) + return; + + buf_size = config_params.channel_bufsize[ch->channel_id]; +} + +static struct videobuf_queue_ops video_qops = { + .buf_setup = vpif_buffer_setup, + .buf_prepare = vpif_buffer_prepare, + .buf_queue = vpif_buffer_queue, + .buf_release = vpif_buffer_release, +}; +static u8 channel_first_int[VPIF_NUMOBJECTS][2] = { {1, 1} }; + +static void process_progressive_mode(struct common_obj *common) +{ + unsigned long addr = 0; + + /* Get the next buffer from buffer queue */ + common->next_frm = list_entry(common->dma_queue.next, + struct videobuf_buffer, queue); + /* Remove that buffer from the buffer queue */ + list_del(&common->next_frm->queue); + /* Mark status of the buffer as active */ + common->next_frm->state = VIDEOBUF_ACTIVE; + + /* Set top and bottom field addrs in VPIF registers */ + addr = videobuf_to_dma_contig(common->next_frm); + common->set_addr(addr + common->ytop_off, + addr + common->ybtm_off, + addr + common->ctop_off, + addr + common->cbtm_off); +} + +static void process_interlaced_mode(int fid, struct common_obj *common) +{ + /* device field id and local field id are in sync */ + /* If this is even field */ + if (0 == fid) { + if (common->cur_frm == common->next_frm) + return; + + /* one frame is displayed If next frame is + * available, release cur_frm and move on */ + /* Copy frame display time */ + do_gettimeofday(&common->cur_frm->ts); + /* Change status of the cur_frm */ + common->cur_frm->state = VIDEOBUF_DONE; + /* unlock semaphore on cur_frm */ + wake_up_interruptible(&common->cur_frm->done); + /* Make cur_frm pointing to next_frm */ + common->cur_frm = common->next_frm; + + } else if (1 == fid) { /* odd field */ + if (list_empty(&common->dma_queue) + || (common->cur_frm != common->next_frm)) { + return; + } + /* one field is displayed configure the next + * frame if it is available else hold on current + * frame */ + /* Get next from the buffer queue */ + process_progressive_mode(common); + + } +} + +/* + * vpif_channel_isr: It changes status of the displayed buffer, takes next + * buffer from the queue and sets its address in VPIF registers + */ +static irqreturn_t vpif_channel_isr(int irq, void *dev_id) +{ + struct vpif_device *dev = &vpif_obj; + struct channel_obj *ch; + struct common_obj *common; + enum v4l2_field field; + int fid = -1, i; + int channel_id = 0; + + channel_id = *(int *)(dev_id); + ch = dev->dev[channel_id]; + field = ch->common[VPIF_VIDEO_INDEX].fmt.fmt.pix.field; + for (i = 0; i < VPIF_NUMOBJECTS; i++) { + common = &ch->common[i]; + /* If streaming is started in this channel */ + if (0 == common->started) + continue; + + if (1 == ch->vpifparams.std_info.frm_fmt) { + if (list_empty(&common->dma_queue)) + continue; + + /* Progressive mode */ + if (!channel_first_int[i][channel_id]) { + /* Mark status of the cur_frm to + * done and unlock semaphore on it */ + do_gettimeofday(&common->cur_frm->ts); + common->cur_frm->state = VIDEOBUF_DONE; + wake_up_interruptible(&common->cur_frm->done); + /* Make cur_frm pointing to next_frm */ + common->cur_frm = common->next_frm; + } + + channel_first_int[i][channel_id] = 0; + process_progressive_mode(common); + } else { + /* Interlaced mode */ + /* If it is first interrupt, ignore it */ + + if (channel_first_int[i][channel_id]) { + channel_first_int[i][channel_id] = 0; + continue; + } + + if (0 == i) { + ch->field_id ^= 1; + /* Get field id from VPIF registers */ + fid = vpif_channel_getfid(ch->channel_id + 2); + /* If fid does not match with stored field id */ + if (fid != ch->field_id) { + /* Make them in sync */ + if (0 == fid) + ch->field_id = fid; + + return IRQ_HANDLED; + } + } + process_interlaced_mode(fid, common); + } + } + + return IRQ_HANDLED; +} + +static int vpif_get_std_info(struct channel_obj *ch) +{ + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + struct video_obj *vid_ch = &ch->video; + struct vpif_params *vpifparams = &ch->vpifparams; + struct vpif_channel_config_params *std_info = &vpifparams->std_info; + const struct vpif_channel_config_params *config; + + int index; + + std_info->stdid = vid_ch->stdid; + if (!std_info) + return -1; + + for (index = 0; index < ARRAY_SIZE(ch_params); index++) { + config = &ch_params[index]; + if (config->stdid & std_info->stdid) { + memcpy(std_info, config, sizeof(*config)); + break; + } + } + + if (index == ARRAY_SIZE(ch_params)) + return -1; + + common->fmt.fmt.pix.width = std_info->width; + common->fmt.fmt.pix.height = std_info->height; + vpif_dbg(1, debug, "Pixel details: Width = %d,Height = %d\n", + common->fmt.fmt.pix.width, common->fmt.fmt.pix.height); + + /* Set height and width paramateres */ + ch->common[VPIF_VIDEO_INDEX].height = std_info->height; + ch->common[VPIF_VIDEO_INDEX].width = std_info->width; + + return 0; +} + +/* + * vpif_calculate_offsets: This function calculates buffers offset for Y and C + * in the top and bottom field + */ +static void vpif_calculate_offsets(struct channel_obj *ch) +{ + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + struct vpif_params *vpifparams = &ch->vpifparams; + enum v4l2_field field = common->fmt.fmt.pix.field; + struct video_obj *vid_ch = &ch->video; + unsigned int hpitch, vpitch, sizeimage; + + if (V4L2_FIELD_ANY == common->fmt.fmt.pix.field) { + if (ch->vpifparams.std_info.frm_fmt) + vid_ch->buf_field = V4L2_FIELD_NONE; + else + vid_ch->buf_field = V4L2_FIELD_INTERLACED; + } else { + vid_ch->buf_field = common->fmt.fmt.pix.field; + } + + if (V4L2_MEMORY_USERPTR == common->memory) + sizeimage = common->fmt.fmt.pix.sizeimage; + else + sizeimage = config_params.channel_bufsize[ch->channel_id]; + + hpitch = common->fmt.fmt.pix.bytesperline; + vpitch = sizeimage / (hpitch * 2); + if ((V4L2_FIELD_NONE == vid_ch->buf_field) || + (V4L2_FIELD_INTERLACED == vid_ch->buf_field)) { + common->ytop_off = 0; + common->ybtm_off = hpitch; + common->ctop_off = sizeimage / 2; + common->cbtm_off = sizeimage / 2 + hpitch; + } else if (V4L2_FIELD_SEQ_TB == vid_ch->buf_field) { + common->ytop_off = 0; + common->ybtm_off = sizeimage / 4; + common->ctop_off = sizeimage / 2; + common->cbtm_off = common->ctop_off + sizeimage / 4; + } else if (V4L2_FIELD_SEQ_BT == vid_ch->buf_field) { + common->ybtm_off = 0; + common->ytop_off = sizeimage / 4; + common->cbtm_off = sizeimage / 2; + common->ctop_off = common->cbtm_off + sizeimage / 4; + } + + if ((V4L2_FIELD_NONE == vid_ch->buf_field) || + (V4L2_FIELD_INTERLACED == vid_ch->buf_field)) { + vpifparams->video_params.storage_mode = 1; + } else { + vpifparams->video_params.storage_mode = 0; + } + + if (ch->vpifparams.std_info.frm_fmt == 1) { + vpifparams->video_params.hpitch = + common->fmt.fmt.pix.bytesperline; + } else { + if ((field == V4L2_FIELD_ANY) || + (field == V4L2_FIELD_INTERLACED)) + vpifparams->video_params.hpitch = + common->fmt.fmt.pix.bytesperline * 2; + else + vpifparams->video_params.hpitch = + common->fmt.fmt.pix.bytesperline; + } + + ch->vpifparams.video_params.stdid = ch->vpifparams.std_info.stdid; +} + +static void vpif_config_format(struct channel_obj *ch) +{ + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + + common->fmt.fmt.pix.field = V4L2_FIELD_ANY; + if (config_params.numbuffers[ch->channel_id] == 0) + common->memory = V4L2_MEMORY_USERPTR; + else + common->memory = V4L2_MEMORY_MMAP; + + common->fmt.fmt.pix.sizeimage = + config_params.channel_bufsize[ch->channel_id]; + common->fmt.fmt.pix.pixelformat = V4L2_PIX_FMT_YUV422P; + common->fmt.type = V4L2_BUF_TYPE_VIDEO_OUTPUT; +} + +static int vpif_check_format(struct channel_obj *ch, + struct v4l2_pix_format *pixfmt) +{ + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + enum v4l2_field field = pixfmt->field; + u32 sizeimage, hpitch, vpitch; + + if (pixfmt->pixelformat != V4L2_PIX_FMT_YUV422P) + goto invalid_fmt_exit; + + if (!(VPIF_VALID_FIELD(field))) + goto invalid_fmt_exit; + + if (pixfmt->bytesperline <= 0) + goto invalid_pitch_exit; + + if (V4L2_MEMORY_USERPTR == common->memory) + sizeimage = pixfmt->sizeimage; + else + sizeimage = config_params.channel_bufsize[ch->channel_id]; + + if (vpif_get_std_info(ch)) { + vpif_err("Error getting the standard info\n"); + return -EINVAL; + } + + hpitch = pixfmt->bytesperline; + vpitch = sizeimage / (hpitch * 2); + + /* Check for valid value of pitch */ + if ((hpitch < ch->vpifparams.std_info.width) || + (vpitch < ch->vpifparams.std_info.height)) + goto invalid_pitch_exit; + + /* Check for 8 byte alignment */ + if (!ISALIGNED(hpitch)) { + vpif_err("invalid pitch alignment\n"); + return -EINVAL; + } + pixfmt->width = common->fmt.fmt.pix.width; + pixfmt->height = common->fmt.fmt.pix.height; + + return 0; + +invalid_fmt_exit: + vpif_err("invalid field format\n"); + return -EINVAL; + +invalid_pitch_exit: + vpif_err("invalid pitch\n"); + return -EINVAL; +} + +static void vpif_config_addr(struct channel_obj *ch, int muxmode) +{ + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + + if (VPIF_CHANNEL3_VIDEO == ch->channel_id) { + common->set_addr = ch3_set_videobuf_addr; + } else { + if (2 == muxmode) + common->set_addr = ch2_set_videobuf_addr_yc_nmux; + else + common->set_addr = ch2_set_videobuf_addr; + } +} + +/* + * vpif_mmap: It is used to map kernel space buffers into user spaces + */ +static int vpif_mmap(struct file *filep, struct vm_area_struct *vma) +{ + struct vpif_fh *fh = filep->private_data; + struct common_obj *common = &fh->channel->common[VPIF_VIDEO_INDEX]; + + return videobuf_mmap_mapper(&common->buffer_queue, vma); +} + +/* + * vpif_poll: It is used for select/poll system call + */ +static unsigned int vpif_poll(struct file *filep, poll_table *wait) +{ + struct vpif_fh *fh = filep->private_data; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + + if (common->started) + return videobuf_poll_stream(filep, &common->buffer_queue, wait); + + return 0; +} + +/* + * vpif_open: It creates object of file handle structure and stores it in + * private_data member of filepointer + */ +static int vpif_open(struct file *filep) +{ + struct video_device *vdev = video_devdata(filep); + struct channel_obj *ch = NULL; + struct vpif_fh *fh = NULL; + + ch = video_get_drvdata(vdev); + /* Allocate memory for the file handle object */ + fh = kmalloc(sizeof(struct vpif_fh), GFP_KERNEL); + if (fh == NULL) { + vpif_err("unable to allocate memory for file handle object\n"); + return -ENOMEM; + } + + /* store pointer to fh in private_data member of filep */ + filep->private_data = fh; + fh->channel = ch; + fh->initialized = 0; + if (!ch->initialized) { + fh->initialized = 1; + ch->initialized = 1; + memset(&ch->vpifparams, 0, sizeof(ch->vpifparams)); + } + + /* Increment channel usrs counter */ + atomic_inc(&ch->usrs); + /* Set io_allowed[VPIF_VIDEO_INDEX] member to false */ + fh->io_allowed[VPIF_VIDEO_INDEX] = 0; + /* Initialize priority of this instance to default priority */ + fh->prio = V4L2_PRIORITY_UNSET; + v4l2_prio_open(&ch->prio, &fh->prio); + + return 0; +} + +/* + * vpif_release: This function deletes buffer queue, frees the buffers and + * the vpif file handle + */ +static int vpif_release(struct file *filep) +{ + struct vpif_fh *fh = filep->private_data; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + /* if this instance is doing IO */ + if (fh->io_allowed[VPIF_VIDEO_INDEX]) { + /* Reset io_usrs member of channel object */ + common->io_usrs = 0; + /* Disable channel */ + if (VPIF_CHANNEL2_VIDEO == ch->channel_id) { + enable_channel2(0); + channel2_intr_enable(0); + } + if ((VPIF_CHANNEL3_VIDEO == ch->channel_id) || + (2 == common->started)) { + enable_channel3(0); + channel3_intr_enable(0); + } + common->started = 0; + /* Free buffers allocated */ + videobuf_queue_cancel(&common->buffer_queue); + videobuf_mmap_free(&common->buffer_queue); + common->numbuffers = + config_params.numbuffers[ch->channel_id]; + } + + mutex_unlock(&common->lock); + + /* Decrement channel usrs counter */ + atomic_dec(&ch->usrs); + /* If this file handle has initialize encoder device, reset it */ + if (fh->initialized) + ch->initialized = 0; + + /* Close the priority */ + v4l2_prio_close(&ch->prio, &fh->prio); + filep->private_data = NULL; + fh->initialized = 0; + kfree(fh); + + return 0; +} + +/* functions implementing ioctls */ + +static int vpif_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct vpif_display_config *config = vpif_dev->platform_data; + + cap->version = VPIF_DISPLAY_VERSION_CODE; + cap->capabilities = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING; + strlcpy(cap->driver, "vpif display", sizeof(cap->driver)); + strlcpy(cap->bus_info, "Platform", sizeof(cap->bus_info)); + strlcpy(cap->card, config->card_name, sizeof(cap->card)); + + return 0; +} + +static int vpif_enum_fmt_vid_out(struct file *file, void *priv, + struct v4l2_fmtdesc *fmt) +{ + if (fmt->index != 0) { + vpif_err("Invalid format index\n"); + return -EINVAL; + } + + /* Fill in the information about format */ + fmt->type = V4L2_BUF_TYPE_VIDEO_OUTPUT; + strcpy(fmt->description, "YCbCr4:2:2 YC Planar"); + fmt->pixelformat = V4L2_PIX_FMT_YUV422P; + + return 0; +} + +static int vpif_g_fmt_vid_out(struct file *file, void *priv, + struct v4l2_format *fmt) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + + /* Check the validity of the buffer type */ + if (common->fmt.type != fmt->type) + return -EINVAL; + + /* Fill in the information about format */ + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + if (vpif_get_std_info(ch)) { + vpif_err("Error getting the standard info\n"); + return -EINVAL; + } + + *fmt = common->fmt; + mutex_unlock(&common->lock); + return 0; +} + +static int vpif_s_fmt_vid_out(struct file *file, void *priv, + struct v4l2_format *fmt) +{ + struct vpif_fh *fh = priv; + struct v4l2_pix_format *pixfmt; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + int ret = 0; + + if ((VPIF_CHANNEL2_VIDEO == ch->channel_id) + || (VPIF_CHANNEL3_VIDEO == ch->channel_id)) { + if (!fh->initialized) { + vpif_dbg(1, debug, "Channel Busy\n"); + return -EBUSY; + } + + /* Check for the priority */ + ret = v4l2_prio_check(&ch->prio, &fh->prio); + if (0 != ret) + return ret; + fh->initialized = 1; + } + + if (common->started) { + vpif_dbg(1, debug, "Streaming in progress\n"); + return -EBUSY; + } + + pixfmt = &fmt->fmt.pix; + /* Check for valid field format */ + ret = vpif_check_format(ch, pixfmt); + if (ret) + return ret; + + /* store the pix format in the channel object */ + common->fmt.fmt.pix = *pixfmt; + /* store the format in the channel object */ + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + common->fmt = *fmt; + mutex_unlock(&common->lock); + + return 0; +} + +static int vpif_try_fmt_vid_out(struct file *file, void *priv, + struct v4l2_format *fmt) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + struct v4l2_pix_format *pixfmt = &fmt->fmt.pix; + int ret = 0; + + ret = vpif_check_format(ch, pixfmt); + if (ret) { + *pixfmt = common->fmt.fmt.pix; + pixfmt->sizeimage = pixfmt->width * pixfmt->height * 2; + } + + return ret; +} + +static int vpif_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *reqbuf) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common; + enum v4l2_field field; + u8 index = 0; + int ret = 0; + + /* This file handle has not initialized the channel, + It is not allowed to do settings */ + if ((VPIF_CHANNEL2_VIDEO == ch->channel_id) + || (VPIF_CHANNEL3_VIDEO == ch->channel_id)) { + if (!fh->initialized) { + vpif_err("Channel Busy\n"); + return -EBUSY; + } + } + + if (V4L2_BUF_TYPE_VIDEO_OUTPUT != reqbuf->type) + return -EINVAL; + + index = VPIF_VIDEO_INDEX; + + common = &ch->common[index]; + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + if (common->fmt.type != reqbuf->type) { + ret = -EINVAL; + goto reqbuf_exit; + } + + if (0 != common->io_usrs) { + ret = -EBUSY; + goto reqbuf_exit; + } + + if (reqbuf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) { + if (common->fmt.fmt.pix.field == V4L2_FIELD_ANY) + field = V4L2_FIELD_INTERLACED; + else + field = common->fmt.fmt.pix.field; + } else { + field = V4L2_VBI_INTERLACED; + } + + /* Initialize videobuf queue as per the buffer type */ + videobuf_queue_dma_contig_init(&common->buffer_queue, + &video_qops, NULL, + &common->irqlock, + reqbuf->type, field, + sizeof(struct videobuf_buffer), fh); + + /* Set io allowed member of file handle to TRUE */ + fh->io_allowed[index] = 1; + /* Increment io usrs member of channel object to 1 */ + common->io_usrs = 1; + /* Store type of memory requested in channel object */ + common->memory = reqbuf->memory; + INIT_LIST_HEAD(&common->dma_queue); + + /* Allocate buffers */ + ret = videobuf_reqbufs(&common->buffer_queue, reqbuf); + +reqbuf_exit: + mutex_unlock(&common->lock); + return ret; +} + +static int vpif_querybuf(struct file *file, void *priv, + struct v4l2_buffer *tbuf) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + + if (common->fmt.type != tbuf->type) + return -EINVAL; + + return videobuf_querybuf(&common->buffer_queue, tbuf); +} + +static int vpif_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf) +{ + + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + struct v4l2_buffer tbuf = *buf; + struct videobuf_buffer *buf1; + unsigned long addr = 0; + unsigned long flags; + int ret = 0; + + if (common->fmt.type != tbuf.type) + return -EINVAL; + + if (!fh->io_allowed[VPIF_VIDEO_INDEX]) { + vpif_err("fh->io_allowed\n"); + return -EACCES; + } + + if (!(list_empty(&common->dma_queue)) || + (common->cur_frm != common->next_frm) || + !(common->started) || + (common->started && (0 == ch->field_id))) + return videobuf_qbuf(&common->buffer_queue, buf); + + /* bufferqueue is empty store buffer address in VPIF registers */ + mutex_lock(&common->buffer_queue.vb_lock); + buf1 = common->buffer_queue.bufs[tbuf.index]; + if (buf1->memory != tbuf.memory) { + vpif_err("invalid buffer type\n"); + goto qbuf_exit; + } + + if ((buf1->state == VIDEOBUF_QUEUED) || + (buf1->state == VIDEOBUF_ACTIVE)) { + vpif_err("invalid state\n"); + goto qbuf_exit; + } + + switch (buf1->memory) { + case V4L2_MEMORY_MMAP: + if (buf1->baddr == 0) + goto qbuf_exit; + break; + + case V4L2_MEMORY_USERPTR: + if (tbuf.length < buf1->bsize) + goto qbuf_exit; + + if ((VIDEOBUF_NEEDS_INIT != buf1->state) + && (buf1->baddr != tbuf.m.userptr)) + vpif_buffer_release(&common->buffer_queue, buf1); + buf1->baddr = tbuf.m.userptr; + break; + + default: + goto qbuf_exit; + } + + local_irq_save(flags); + ret = vpif_buffer_prepare(&common->buffer_queue, buf1, + common->buffer_queue.field); + if (ret < 0) { + local_irq_restore(flags); + goto qbuf_exit; + } + + buf1->state = VIDEOBUF_ACTIVE; + addr = buf1->boff; + common->next_frm = buf1; + if (tbuf.type != V4L2_BUF_TYPE_SLICED_VBI_OUTPUT) { + common->set_addr((addr + common->ytop_off), + (addr + common->ybtm_off), + (addr + common->ctop_off), + (addr + common->cbtm_off)); + } + + local_irq_restore(flags); + list_add_tail(&buf1->stream, &common->buffer_queue.stream); + mutex_unlock(&common->buffer_queue.vb_lock); + return 0; + +qbuf_exit: + mutex_unlock(&common->buffer_queue.vb_lock); + return -EINVAL; +} + +static int vpif_s_std(struct file *file, void *priv, v4l2_std_id *std_id) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + int ret = 0; + + if (!(*std_id & DM646X_V4L2_STD)) + return -EINVAL; + + if (common->started) { + vpif_err("streaming in progress\n"); + return -EBUSY; + } + + /* Call encoder subdevice function to set the standard */ + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + ch->video.stdid = *std_id; + /* Get the information about the standard */ + if (vpif_get_std_info(ch)) { + vpif_err("Error getting the standard info\n"); + return -EINVAL; + } + + if ((ch->vpifparams.std_info.width * + ch->vpifparams.std_info.height * 2) > + config_params.channel_bufsize[ch->channel_id]) { + vpif_err("invalid std for this size\n"); + ret = -EINVAL; + goto s_std_exit; + } + + common->fmt.fmt.pix.bytesperline = common->fmt.fmt.pix.width; + /* Configure the default format information */ + vpif_config_format(ch); + + ret = v4l2_device_call_until_err(&vpif_obj.v4l2_dev, 1, video, + s_std_output, *std_id); + if (ret < 0) { + vpif_err("Failed to set output standard\n"); + goto s_std_exit; + } + + ret = v4l2_device_call_until_err(&vpif_obj.v4l2_dev, 1, core, + s_std, *std_id); + if (ret < 0) + vpif_err("Failed to set standard for sub devices\n"); + +s_std_exit: + mutex_unlock(&common->lock); + return ret; +} + +static int vpif_g_std(struct file *file, void *priv, v4l2_std_id *std) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + + *std = ch->video.stdid; + return 0; +} + +static int vpif_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + + return videobuf_dqbuf(&common->buffer_queue, p, + (file->f_flags & O_NONBLOCK)); +} + +static int vpif_streamon(struct file *file, void *priv, + enum v4l2_buf_type buftype) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + struct channel_obj *oth_ch = vpif_obj.dev[!ch->channel_id]; + struct vpif_params *vpif = &ch->vpifparams; + struct vpif_display_config *vpif_config_data = + vpif_dev->platform_data; + unsigned long addr = 0; + int ret = 0; + + if (buftype != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + vpif_err("buffer type not supported\n"); + return -EINVAL; + } + + if (!fh->io_allowed[VPIF_VIDEO_INDEX]) { + vpif_err("fh->io_allowed\n"); + return -EACCES; + } + + /* If Streaming is already started, return error */ + if (common->started) { + vpif_err("channel->started\n"); + return -EBUSY; + } + + if ((ch->channel_id == VPIF_CHANNEL2_VIDEO + && oth_ch->common[VPIF_VIDEO_INDEX].started && + ch->vpifparams.std_info.ycmux_mode == 0) + || ((ch->channel_id == VPIF_CHANNEL3_VIDEO) + && (2 == oth_ch->common[VPIF_VIDEO_INDEX].started))) { + vpif_err("other channel is using\n"); + return -EBUSY; + } + + ret = vpif_check_format(ch, &common->fmt.fmt.pix); + if (ret < 0) + return ret; + + /* Call videobuf_streamon to start streaming in videobuf */ + ret = videobuf_streamon(&common->buffer_queue); + if (ret < 0) { + vpif_err("videobuf_streamon\n"); + return ret; + } + + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + /* If buffer queue is empty, return error */ + if (list_empty(&common->dma_queue)) { + vpif_err("buffer queue is empty\n"); + ret = -EIO; + goto streamon_exit; + } + + /* Get the next frame from the buffer queue */ + common->next_frm = common->cur_frm = + list_entry(common->dma_queue.next, + struct videobuf_buffer, queue); + + list_del(&common->cur_frm->queue); + /* Mark state of the current frame to active */ + common->cur_frm->state = VIDEOBUF_ACTIVE; + + /* Initialize field_id and started member */ + ch->field_id = 0; + common->started = 1; + if (buftype == V4L2_BUF_TYPE_VIDEO_OUTPUT) { + addr = common->cur_frm->boff; + /* Calculate the offset for Y and C data in the buffer */ + vpif_calculate_offsets(ch); + + if ((ch->vpifparams.std_info.frm_fmt && + ((common->fmt.fmt.pix.field != V4L2_FIELD_NONE) + && (common->fmt.fmt.pix.field != V4L2_FIELD_ANY))) + || (!ch->vpifparams.std_info.frm_fmt + && (common->fmt.fmt.pix.field == V4L2_FIELD_NONE))) { + vpif_err("conflict in field format and std format\n"); + ret = -EINVAL; + goto streamon_exit; + } + + /* clock settings */ + ret = + vpif_config_data->set_clock(ch->vpifparams.std_info.ycmux_mode, + ch->vpifparams.std_info.hd_sd); + if (ret < 0) { + vpif_err("can't set clock\n"); + goto streamon_exit; + } + + /* set the parameters and addresses */ + ret = vpif_set_video_params(vpif, ch->channel_id + 2); + if (ret < 0) + goto streamon_exit; + + common->started = ret; + vpif_config_addr(ch, ret); + common->set_addr((addr + common->ytop_off), + (addr + common->ybtm_off), + (addr + common->ctop_off), + (addr + common->cbtm_off)); + + /* Set interrupt for both the fields in VPIF + Register enable channel in VPIF register */ + if (VPIF_CHANNEL2_VIDEO == ch->channel_id) { + channel2_intr_assert(); + channel2_intr_enable(1); + enable_channel2(1); + } + + if ((VPIF_CHANNEL3_VIDEO == ch->channel_id) + || (common->started == 2)) { + channel3_intr_assert(); + channel3_intr_enable(1); + enable_channel3(1); + } + channel_first_int[VPIF_VIDEO_INDEX][ch->channel_id] = 1; + } + +streamon_exit: + mutex_unlock(&common->lock); + return ret; +} + +static int vpif_streamoff(struct file *file, void *priv, + enum v4l2_buf_type buftype) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + + if (buftype != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + vpif_err("buffer type not supported\n"); + return -EINVAL; + } + + if (!fh->io_allowed[VPIF_VIDEO_INDEX]) { + vpif_err("fh->io_allowed\n"); + return -EACCES; + } + + if (!common->started) { + vpif_err("channel->started\n"); + return -EINVAL; + } + + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + if (buftype == V4L2_BUF_TYPE_VIDEO_OUTPUT) { + /* disable channel */ + if (VPIF_CHANNEL2_VIDEO == ch->channel_id) { + enable_channel2(0); + channel2_intr_enable(0); + } + if ((VPIF_CHANNEL3_VIDEO == ch->channel_id) || + (2 == common->started)) { + enable_channel3(0); + channel3_intr_enable(0); + } + } + + common->started = 0; + mutex_unlock(&common->lock); + + return videobuf_streamoff(&common->buffer_queue); +} + +static int vpif_cropcap(struct file *file, void *priv, + struct v4l2_cropcap *crop) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + if (V4L2_BUF_TYPE_VIDEO_OUTPUT != crop->type) + return -EINVAL; + + crop->bounds.left = crop->bounds.top = 0; + crop->defrect.left = crop->defrect.top = 0; + crop->defrect.height = crop->bounds.height = common->height; + crop->defrect.width = crop->bounds.width = common->width; + + return 0; +} + +static int vpif_enum_output(struct file *file, void *fh, + struct v4l2_output *output) +{ + + struct vpif_display_config *config = vpif_dev->platform_data; + + if (output->index >= config->output_count) { + vpif_dbg(1, debug, "Invalid output index\n"); + return -EINVAL; + } + + strcpy(output->name, config->output[output->index]); + output->type = V4L2_OUTPUT_TYPE_ANALOG; + output->std = DM646X_V4L2_STD; + + return 0; +} + +static int vpif_s_output(struct file *file, void *priv, unsigned int i) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct video_obj *vid_ch = &ch->video; + struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX]; + int ret = 0; + + if (mutex_lock_interruptible(&common->lock)) + return -ERESTARTSYS; + + if (common->started) { + vpif_err("Streaming in progress\n"); + ret = -EBUSY; + goto s_output_exit; + } + + ret = v4l2_device_call_until_err(&vpif_obj.v4l2_dev, 1, video, + s_routing, 0, i, 0); + + if (ret < 0) + vpif_err("Failed to set output standard\n"); + + vid_ch->output_id = i; + +s_output_exit: + mutex_unlock(&common->lock); + return ret; +} + +static int vpif_g_output(struct file *file, void *priv, unsigned int *i) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + struct video_obj *vid_ch = &ch->video; + + *i = vid_ch->output_id; + + return 0; +} + +static int vpif_g_priority(struct file *file, void *priv, enum v4l2_priority *p) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + + *p = v4l2_prio_max(&ch->prio); + + return 0; +} + +static int vpif_s_priority(struct file *file, void *priv, enum v4l2_priority p) +{ + struct vpif_fh *fh = priv; + struct channel_obj *ch = fh->channel; + + return v4l2_prio_change(&ch->prio, &fh->prio, p); +} + +/* vpif display ioctl operations */ +static const struct v4l2_ioctl_ops vpif_ioctl_ops = { + .vidioc_querycap = vpif_querycap, + .vidioc_g_priority = vpif_g_priority, + .vidioc_s_priority = vpif_s_priority, + .vidioc_enum_fmt_vid_out = vpif_enum_fmt_vid_out, + .vidioc_g_fmt_vid_out = vpif_g_fmt_vid_out, + .vidioc_s_fmt_vid_out = vpif_s_fmt_vid_out, + .vidioc_try_fmt_vid_out = vpif_try_fmt_vid_out, + .vidioc_reqbufs = vpif_reqbufs, + .vidioc_querybuf = vpif_querybuf, + .vidioc_qbuf = vpif_qbuf, + .vidioc_dqbuf = vpif_dqbuf, + .vidioc_streamon = vpif_streamon, + .vidioc_streamoff = vpif_streamoff, + .vidioc_s_std = vpif_s_std, + .vidioc_g_std = vpif_g_std, + .vidioc_enum_output = vpif_enum_output, + .vidioc_s_output = vpif_s_output, + .vidioc_g_output = vpif_g_output, + .vidioc_cropcap = vpif_cropcap, +}; + +static const struct v4l2_file_operations vpif_fops = { + .owner = THIS_MODULE, + .open = vpif_open, + .release = vpif_release, + .ioctl = video_ioctl2, + .mmap = vpif_mmap, + .poll = vpif_poll +}; + +static struct video_device vpif_video_template = { + .name = "vpif", + .fops = &vpif_fops, + .minor = -1, + .ioctl_ops = &vpif_ioctl_ops, + .tvnorms = DM646X_V4L2_STD, + .current_norm = V4L2_STD_625_50, + +}; + +/*Configure the channels, buffer sizei, request irq */ +static int initialize_vpif(void) +{ + int free_channel_objects_index; + int free_buffer_channel_index; + int free_buffer_index; + int err = 0, i, j; + + /* Default number of buffers should be 3 */ + if ((ch2_numbuffers > 0) && + (ch2_numbuffers < config_params.min_numbuffers)) + ch2_numbuffers = config_params.min_numbuffers; + if ((ch3_numbuffers > 0) && + (ch3_numbuffers < config_params.min_numbuffers)) + ch3_numbuffers = config_params.min_numbuffers; + + /* Set buffer size to min buffers size if invalid buffer size is + * given */ + if (ch2_bufsize < config_params.min_bufsize[VPIF_CHANNEL2_VIDEO]) + ch2_bufsize = + config_params.min_bufsize[VPIF_CHANNEL2_VIDEO]; + if (ch3_bufsize < config_params.min_bufsize[VPIF_CHANNEL3_VIDEO]) + ch3_bufsize = + config_params.min_bufsize[VPIF_CHANNEL3_VIDEO]; + + config_params.numbuffers[VPIF_CHANNEL2_VIDEO] = ch2_numbuffers; + + if (ch2_numbuffers) { + config_params.channel_bufsize[VPIF_CHANNEL2_VIDEO] = + ch2_bufsize; + } + config_params.numbuffers[VPIF_CHANNEL3_VIDEO] = ch3_numbuffers; + + if (ch3_numbuffers) { + config_params.channel_bufsize[VPIF_CHANNEL3_VIDEO] = + ch3_bufsize; + } + + /* Allocate memory for six channel objects */ + for (i = 0; i < VPIF_DISPLAY_MAX_DEVICES; i++) { + vpif_obj.dev[i] = + kmalloc(sizeof(struct channel_obj), GFP_KERNEL); + /* If memory allocation fails, return error */ + if (!vpif_obj.dev[i]) { + free_channel_objects_index = i; + err = -ENOMEM; + goto vpif_init_free_channel_objects; + } + } + + free_channel_objects_index = VPIF_DISPLAY_MAX_DEVICES; + free_buffer_channel_index = VPIF_DISPLAY_NUM_CHANNELS; + free_buffer_index = config_params.numbuffers[i - 1]; + + return 0; + +vpif_init_free_channel_objects: + for (j = 0; j < free_channel_objects_index; j++) + kfree(vpif_obj.dev[j]); + return err; +} + +/* + * vpif_probe: This function creates device entries by register itself to the + * V4L2 driver and initializes fields of each channel objects + */ +static __init int vpif_probe(struct platform_device *pdev) +{ + struct vpif_subdev_info *subdevdata; + struct vpif_display_config *config; + int i, j = 0, k, q, m, err = 0; + struct i2c_adapter *i2c_adap; + struct vpif_config *config; + struct common_obj *common; + struct channel_obj *ch; + struct video_device *vfd; + struct resource *res; + int subdev_count; + + vpif_dev = &pdev->dev; + + err = initialize_vpif(); + + if (err) { + v4l2_err(vpif_dev->driver, "Error initializing vpif\n"); + return err; + } + + err = v4l2_device_register(vpif_dev, &vpif_obj.v4l2_dev); + if (err) { + v4l2_err(vpif_dev->driver, "Error registering v4l2 device\n"); + return err; + } + + k = 0; + while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, k))) { + for (i = res->start; i <= res->end; i++) { + if (request_irq(i, vpif_channel_isr, IRQF_DISABLED, + "DM646x_Display", + (void *)(&vpif_obj.dev[k]->channel_id))) { + err = -EBUSY; + goto vpif_int_err; + } + } + k++; + } + + for (i = 0; i < VPIF_DISPLAY_MAX_DEVICES; i++) { + + /* Get the pointer to the channel object */ + ch = vpif_obj.dev[i]; + + /* Allocate memory for video device */ + vfd = video_device_alloc(); + if (vfd == NULL) { + for (j = 0; j < i; j++) { + ch = vpif_obj.dev[j]; + video_device_release(ch->video_dev); + } + err = -ENOMEM; + goto vpif_int_err; + } + + /* Initialize field of video device */ + *vfd = vpif_video_template; + vfd->v4l2_dev = &vpif_obj.v4l2_dev; + vfd->release = video_device_release; + snprintf(vfd->name, sizeof(vfd->name), + "DM646x_VPIFDisplay_DRIVER_V%d.%d.%d", + (VPIF_DISPLAY_VERSION_CODE >> 16) & 0xff, + (VPIF_DISPLAY_VERSION_CODE >> 8) & 0xff, + (VPIF_DISPLAY_VERSION_CODE) & 0xff); + + /* Set video_dev to the video device */ + ch->video_dev = vfd; + } + + for (j = 0; j < VPIF_DISPLAY_MAX_DEVICES; j++) { + ch = vpif_obj.dev[j]; + /* Initialize field of the channel objects */ + atomic_set(&ch->usrs, 0); + for (k = 0; k < VPIF_NUMOBJECTS; k++) { + ch->common[k].numbuffers = 0; + common = &ch->common[k]; + common->io_usrs = 0; + common->started = 0; + spin_lock_init(&common->irqlock); + mutex_init(&common->lock); + common->numbuffers = 0; + common->set_addr = NULL; + common->ytop_off = common->ybtm_off = 0; + common->ctop_off = common->cbtm_off = 0; + common->cur_frm = common->next_frm = NULL; + memset(&common->fmt, 0, sizeof(common->fmt)); + common->numbuffers = config_params.numbuffers[k]; + + } + ch->initialized = 0; + ch->channel_id = j; + if (j < 2) + ch->common[VPIF_VIDEO_INDEX].numbuffers = + config_params.numbuffers[ch->channel_id]; + else + ch->common[VPIF_VIDEO_INDEX].numbuffers = 0; + + memset(&ch->vpifparams, 0, sizeof(ch->vpifparams)); + + /* Initialize prio member of channel object */ + v4l2_prio_init(&ch->prio); + ch->common[VPIF_VIDEO_INDEX].fmt.type = + V4L2_BUF_TYPE_VIDEO_OUTPUT; + + /* register video device */ + vpif_dbg(1, debug, "channel=%x,channel->video_dev=%x\n", + (int)ch, (int)&ch->video_dev); + + err = video_register_device(ch->video_dev, + VFL_TYPE_GRABBER, (j ? 3 : 2)); + if (err < 0) + goto probe_out; + + video_set_drvdata(ch->video_dev, ch); + } + + i2c_adap = i2c_get_adapter(1); + config = pdev->dev.platform_data; + subdev_count = config->subdev_count; + subdevdata = config->subdevinfo; + vpif_obj.sd = kmalloc(sizeof(struct v4l2_subdev *) * subdev_count, + GFP_KERNEL); + if (vpif_obj.sd == NULL) { + vpif_err("unable to allocate memory for subdevice pointers\n"); + err = -ENOMEM; + goto probe_out; + } + + for (i = 0; i < subdev_count; i++) { + vpif_obj.sd[i] = v4l2_i2c_new_subdev_board(&vpif_obj.v4l2_dev, + i2c_adap, subdevdata[i].name, + &subdevdata[i].board_info, + NULL); + if (!vpif_obj.sd[i]) { + vpif_err("Error registering v4l2 subdevice\n"); + goto probe_subdev_out; + } + + if (vpif_obj.sd[i]) + vpif_obj.sd[i]->grp_id = 1 << i; + } + + return 0; + +probe_subdev_out: + kfree(vpif_obj.sd); +probe_out: + for (k = 0; k < j; k++) { + ch = vpif_obj.dev[k]; + video_unregister_device(ch->video_dev); + video_device_release(ch->video_dev); + ch->video_dev = NULL; + } +vpif_int_err: + v4l2_device_unregister(&vpif_obj.v4l2_dev); + vpif_err("VPIF IRQ request failed\n"); + for (q = k; k >= 0; k--) { + for (m = i; m >= res->start; m--) + free_irq(m, (void *)(&vpif_obj.dev[k]->channel_id)); + res = platform_get_resource(pdev, IORESOURCE_IRQ, k-1); + m = res->end; + } + + return err; +} + +/* + * vpif_remove: It un-register channels from V4L2 driver + */ +static int vpif_remove(struct platform_device *device) +{ + struct channel_obj *ch; + int i; + + v4l2_device_unregister(&vpif_obj.v4l2_dev); + + /* un-register device */ + for (i = 0; i < VPIF_DISPLAY_MAX_DEVICES; i++) { + /* Get the pointer to the channel object */ + ch = vpif_obj.dev[i]; + /* Unregister video device */ + video_unregister_device(ch->video_dev); + + ch->video_dev = NULL; + } + + return 0; +} + +static struct platform_driver vpif_driver = { + .driver = { + .name = "vpif_display", + .owner = THIS_MODULE, + }, + .probe = vpif_probe, + .remove = vpif_remove, +}; + +static __init int vpif_init(void) +{ + return platform_driver_register(&vpif_driver); +} + +/* + * vpif_cleanup: This function un-registers device and driver to the kernel, + * frees requested irq handler and de-allocates memory allocated for channel + * objects. + */ +static void vpif_cleanup(void) +{ + struct platform_device *pdev; + struct resource *res; + int irq_num; + int i = 0; + + pdev = container_of(vpif_dev, struct platform_device, dev); + + while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, i))) { + for (irq_num = res->start; irq_num <= res->end; irq_num++) + free_irq(irq_num, + (void *)(&vpif_obj.dev[i]->channel_id)); + i++; + } + + platform_driver_unregister(&vpif_driver); + kfree(vpif_obj.sd); + for (i = 0; i < VPIF_DISPLAY_MAX_DEVICES; i++) + kfree(vpif_obj.dev[i]); +} + +module_init(vpif_init); +module_exit(vpif_cleanup); diff --git a/drivers/media/video/davinci/vpif_display.h b/drivers/media/video/davinci/vpif_display.h new file mode 100644 index 000000000000..a2a7cd166bbf --- /dev/null +++ b/drivers/media/video/davinci/vpif_display.h @@ -0,0 +1,175 @@ +/* + * DM646x display header file + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed .as is. WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DAVINCIHD_DISPLAY_H +#define DAVINCIHD_DISPLAY_H + +/* Header files */ +#include +#include +#include +#include +#include +#include + +#include "vpif.h" + +/* Macros */ +#define VPIF_MAJOR_RELEASE (0) +#define VPIF_MINOR_RELEASE (0) +#define VPIF_BUILD (1) + +#define VPIF_DISPLAY_VERSION_CODE \ + ((VPIF_MAJOR_RELEASE << 16) | (VPIF_MINOR_RELEASE << 8) | VPIF_BUILD) + +#define VPIF_VALID_FIELD(field) \ + (((V4L2_FIELD_ANY == field) || (V4L2_FIELD_NONE == field)) || \ + (((V4L2_FIELD_INTERLACED == field) || (V4L2_FIELD_SEQ_TB == field)) || \ + (V4L2_FIELD_SEQ_BT == field))) + +#define VPIF_DISPLAY_MAX_DEVICES (2) +#define VPIF_SLICED_BUF_SIZE (256) +#define VPIF_SLICED_MAX_SERVICES (3) +#define VPIF_VIDEO_INDEX (0) +#define VPIF_VBI_INDEX (1) +#define VPIF_HBI_INDEX (2) + +/* Setting it to 1 as HBI/VBI support yet to be added , else 3*/ +#define VPIF_NUMOBJECTS (1) + +/* Macros */ +#define ISALIGNED(a) (0 == ((a) & 7)) + +/* enumerated data types */ +/* Enumerated data type to give id to each device per channel */ +enum vpif_channel_id { + VPIF_CHANNEL2_VIDEO = 0, /* Channel2 Video */ + VPIF_CHANNEL3_VIDEO, /* Channel3 Video */ +}; + +/* structures */ + +struct video_obj { + enum v4l2_field buf_field; + u32 latest_only; /* indicate whether to return + * most recent displayed frame only */ + v4l2_std_id stdid; /* Currently selected or default + * standard */ + u32 output_id; /* Current output id */ +}; + +struct vbi_obj { + int num_services; + struct vpif_vbi_params vbiparams; /* vpif parameters for the raw + * vbi data */ +}; + +struct common_obj { + /* Buffer specific parameters */ + u8 *fbuffers[VIDEO_MAX_FRAME]; /* List of buffer pointers for + * storing frames */ + u32 numbuffers; /* number of buffers */ + struct videobuf_buffer *cur_frm; /* Pointer pointing to current + * videobuf_buffer */ + struct videobuf_buffer *next_frm; /* Pointer pointing to next + * videobuf_buffer */ + enum v4l2_memory memory; /* This field keeps track of + * type of buffer exchange + * method user has selected */ + struct v4l2_format fmt; /* Used to store the format */ + struct videobuf_queue buffer_queue; /* Buffer queue used in + * video-buf */ + struct list_head dma_queue; /* Queue of filled frames */ + spinlock_t irqlock; /* Used in video-buf */ + + /* channel specific parameters */ + struct mutex lock; /* lock used to access this + * structure */ + u32 io_usrs; /* number of users performing + * IO */ + u8 started; /* Indicates whether streaming + * started */ + u32 ytop_off; /* offset of Y top from the + * starting of the buffer */ + u32 ybtm_off; /* offset of Y bottom from the + * starting of the buffer */ + u32 ctop_off; /* offset of C top from the + * starting of the buffer */ + u32 cbtm_off; /* offset of C bottom from the + * starting of the buffer */ + /* Function pointer to set the addresses */ + void (*set_addr) (unsigned long, unsigned long, + unsigned long, unsigned long); + u32 height; + u32 width; +}; + +struct channel_obj { + /* V4l2 specific parameters */ + struct video_device *video_dev; /* Identifies video device for + * this channel */ + struct v4l2_prio_state prio; /* Used to keep track of state of + * the priority */ + atomic_t usrs; /* number of open instances of + * the channel */ + u32 field_id; /* Indicates id of the field + * which is being displayed */ + u8 initialized; /* flag to indicate whether + * encoder is initialized */ + + enum vpif_channel_id channel_id;/* Identifies channel */ + struct vpif_params vpifparams; + struct common_obj common[VPIF_NUMOBJECTS]; + struct video_obj video; + struct vbi_obj vbi; +}; + +/* File handle structure */ +struct vpif_fh { + struct channel_obj *channel; /* pointer to channel object for + * opened device */ + u8 io_allowed[VPIF_NUMOBJECTS]; /* Indicates whether this file handle + * is doing IO */ + enum v4l2_priority prio; /* Used to keep track priority of + * this instance */ + u8 initialized; /* Used to keep track of whether this + * file handle has initialized + * channel or not */ +}; + +/* vpif device structure */ +struct vpif_device { + struct v4l2_device v4l2_dev; + struct channel_obj *dev[VPIF_DISPLAY_NUM_CHANNELS]; + struct v4l2_subdev **sd; + +}; + +struct vpif_config_params { + u32 min_bufsize[VPIF_DISPLAY_NUM_CHANNELS]; + u32 channel_bufsize[VPIF_DISPLAY_NUM_CHANNELS]; + u8 numbuffers[VPIF_DISPLAY_NUM_CHANNELS]; + u8 min_numbuffers; +}; + +/* Struct which keeps track of the line numbers for the sliced vbi service */ +struct vpif_service_line { + u16 service_id; + u16 service_line[2]; + u16 enc_service_id; + u8 bytestowrite; +}; + +#endif /* DAVINCIHD_DISPLAY_H */ diff --git a/drivers/media/video/davinci/vpss.c b/drivers/media/video/davinci/vpss.c new file mode 100644 index 000000000000..6d709ca8cfb0 --- /dev/null +++ b/drivers/media/video/davinci/vpss.c @@ -0,0 +1,301 @@ +/* + * Copyright (C) 2009 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * common vpss driver for all video drivers. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("VPSS Driver"); +MODULE_AUTHOR("Texas Instruments"); + +/* DM644x defines */ +#define DM644X_SBL_PCR_VPSS (4) + +/* vpss BL register offsets */ +#define DM355_VPSSBL_CCDCMUX 0x1c +/* vpss CLK register offsets */ +#define DM355_VPSSCLK_CLKCTRL 0x04 +/* masks and shifts */ +#define VPSS_HSSISEL_SHIFT 4 + +/* + * vpss operations. Depends on platform. Not all functions are available + * on all platforms. The api, first check if a functio is available before + * invoking it. In the probe, the function ptrs are intialized based on + * vpss name. vpss name can be "dm355_vpss", "dm644x_vpss" etc. + */ +struct vpss_hw_ops { + /* enable clock */ + int (*enable_clock)(enum vpss_clock_sel clock_sel, int en); + /* select input to ccdc */ + void (*select_ccdc_source)(enum vpss_ccdc_source_sel src_sel); + /* clear wbl overlflow bit */ + int (*clear_wbl_overflow)(enum vpss_wbl_sel wbl_sel); +}; + +/* vpss configuration */ +struct vpss_oper_config { + __iomem void *vpss_bl_regs_base; + __iomem void *vpss_regs_base; + struct resource *r1; + resource_size_t len1; + struct resource *r2; + resource_size_t len2; + char vpss_name[32]; + spinlock_t vpss_lock; + struct vpss_hw_ops hw_ops; +}; + +static struct vpss_oper_config oper_cfg; + +/* register access routines */ +static inline u32 bl_regr(u32 offset) +{ + return __raw_readl(oper_cfg.vpss_bl_regs_base + offset); +} + +static inline void bl_regw(u32 val, u32 offset) +{ + __raw_writel(val, oper_cfg.vpss_bl_regs_base + offset); +} + +static inline u32 vpss_regr(u32 offset) +{ + return __raw_readl(oper_cfg.vpss_regs_base + offset); +} + +static inline void vpss_regw(u32 val, u32 offset) +{ + __raw_writel(val, oper_cfg.vpss_regs_base + offset); +} + +static void dm355_select_ccdc_source(enum vpss_ccdc_source_sel src_sel) +{ + bl_regw(src_sel << VPSS_HSSISEL_SHIFT, DM355_VPSSBL_CCDCMUX); +} + +int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel) +{ + if (!oper_cfg.hw_ops.select_ccdc_source) + return -1; + + dm355_select_ccdc_source(src_sel); + return 0; +} +EXPORT_SYMBOL(vpss_select_ccdc_source); + +static int dm644x_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel) +{ + u32 mask = 1, val; + + if (wbl_sel < VPSS_PCR_AEW_WBL_0 || + wbl_sel > VPSS_PCR_CCDC_WBL_O) + return -1; + + /* writing a 0 clear the overflow */ + mask = ~(mask << wbl_sel); + val = bl_regr(DM644X_SBL_PCR_VPSS) & mask; + bl_regw(val, DM644X_SBL_PCR_VPSS); + return 0; +} + +int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel) +{ + if (!oper_cfg.hw_ops.clear_wbl_overflow) + return -1; + + return oper_cfg.hw_ops.clear_wbl_overflow(wbl_sel); +} +EXPORT_SYMBOL(vpss_clear_wbl_overflow); + +/* + * dm355_enable_clock - Enable VPSS Clock + * @clock_sel: CLock to be enabled/disabled + * @en: enable/disable flag + * + * This is called to enable or disable a vpss clock + */ +static int dm355_enable_clock(enum vpss_clock_sel clock_sel, int en) +{ + unsigned long flags; + u32 utemp, mask = 0x1, shift = 0; + + switch (clock_sel) { + case VPSS_VPBE_CLOCK: + /* nothing since lsb */ + break; + case VPSS_VENC_CLOCK_SEL: + shift = 2; + break; + case VPSS_CFALD_CLOCK: + shift = 3; + break; + case VPSS_H3A_CLOCK: + shift = 4; + break; + case VPSS_IPIPE_CLOCK: + shift = 5; + break; + case VPSS_CCDC_CLOCK: + shift = 6; + break; + default: + printk(KERN_ERR "dm355_enable_clock:" + " Invalid selector: %d\n", clock_sel); + return -1; + } + + spin_lock_irqsave(&oper_cfg.vpss_lock, flags); + utemp = vpss_regr(DM355_VPSSCLK_CLKCTRL); + if (!en) + utemp &= ~(mask << shift); + else + utemp |= (mask << shift); + + vpss_regw(utemp, DM355_VPSSCLK_CLKCTRL); + spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags); + return 0; +} + +int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en) +{ + if (!oper_cfg.hw_ops.enable_clock) + return -1; + + return oper_cfg.hw_ops.enable_clock(clock_sel, en); +} +EXPORT_SYMBOL(vpss_enable_clock); + +static int __init vpss_probe(struct platform_device *pdev) +{ + int status, dm355 = 0; + + if (!pdev->dev.platform_data) { + dev_err(&pdev->dev, "no platform data\n"); + return -ENOENT; + } + strcpy(oper_cfg.vpss_name, pdev->dev.platform_data); + + if (!strcmp(oper_cfg.vpss_name, "dm355_vpss")) + dm355 = 1; + else if (strcmp(oper_cfg.vpss_name, "dm644x_vpss")) { + dev_err(&pdev->dev, "vpss driver not supported on" + " this platform\n"); + return -ENODEV; + } + + dev_info(&pdev->dev, "%s vpss probed\n", oper_cfg.vpss_name); + oper_cfg.r1 = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!oper_cfg.r1) + return -ENOENT; + + oper_cfg.len1 = oper_cfg.r1->end - oper_cfg.r1->start + 1; + + oper_cfg.r1 = request_mem_region(oper_cfg.r1->start, oper_cfg.len1, + oper_cfg.r1->name); + if (!oper_cfg.r1) + return -EBUSY; + + oper_cfg.vpss_bl_regs_base = ioremap(oper_cfg.r1->start, oper_cfg.len1); + if (!oper_cfg.vpss_bl_regs_base) { + status = -EBUSY; + goto fail1; + } + + if (dm355) { + oper_cfg.r2 = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!oper_cfg.r2) { + status = -ENOENT; + goto fail2; + } + oper_cfg.len2 = oper_cfg.r2->end - oper_cfg.r2->start + 1; + oper_cfg.r2 = request_mem_region(oper_cfg.r2->start, + oper_cfg.len2, + oper_cfg.r2->name); + if (!oper_cfg.r2) { + status = -EBUSY; + goto fail2; + } + + oper_cfg.vpss_regs_base = ioremap(oper_cfg.r2->start, + oper_cfg.len2); + if (!oper_cfg.vpss_regs_base) { + status = -EBUSY; + goto fail3; + } + } + + if (dm355) { + oper_cfg.hw_ops.enable_clock = dm355_enable_clock; + oper_cfg.hw_ops.select_ccdc_source = dm355_select_ccdc_source; + } else + oper_cfg.hw_ops.clear_wbl_overflow = dm644x_clear_wbl_overflow; + + spin_lock_init(&oper_cfg.vpss_lock); + dev_info(&pdev->dev, "%s vpss probe success\n", oper_cfg.vpss_name); + return 0; + +fail3: + release_mem_region(oper_cfg.r2->start, oper_cfg.len2); +fail2: + iounmap(oper_cfg.vpss_bl_regs_base); +fail1: + release_mem_region(oper_cfg.r1->start, oper_cfg.len1); + return status; +} + +static int vpss_remove(struct platform_device *pdev) +{ + iounmap(oper_cfg.vpss_bl_regs_base); + release_mem_region(oper_cfg.r1->start, oper_cfg.len1); + if (!strcmp(oper_cfg.vpss_name, "dm355_vpss")) { + iounmap(oper_cfg.vpss_regs_base); + release_mem_region(oper_cfg.r2->start, oper_cfg.len2); + } + return 0; +} + +static struct platform_driver vpss_driver = { + .driver = { + .name = "vpss", + .owner = THIS_MODULE, + }, + .remove = __devexit_p(vpss_remove), + .probe = vpss_probe, +}; + +static void vpss_exit(void) +{ + platform_driver_unregister(&vpss_driver); +} + +static int __init vpss_init(void) +{ + return platform_driver_register(&vpss_driver); +} +subsys_initcall(vpss_init); +module_exit(vpss_exit); diff --git a/drivers/media/video/em28xx/Kconfig b/drivers/media/video/em28xx/Kconfig index 6524b493e033..c7be0e097828 100644 --- a/drivers/media/video/em28xx/Kconfig +++ b/drivers/media/video/em28xx/Kconfig @@ -36,6 +36,7 @@ config VIDEO_EM28XX_DVB depends on VIDEO_EM28XX && DVB_CORE select DVB_LGDT330X if !DVB_FE_CUSTOMISE select DVB_ZL10353 if !DVB_FE_CUSTOMISE + select DVB_TDA10023 if !DVB_FE_CUSTOMISE select VIDEOBUF_DVB ---help--- This adds support for DVB cards based on the diff --git a/drivers/media/video/em28xx/Makefile b/drivers/media/video/em28xx/Makefile index 8137a8c94bfc..d0f093d1d0df 100644 --- a/drivers/media/video/em28xx/Makefile +++ b/drivers/media/video/em28xx/Makefile @@ -1,5 +1,5 @@ em28xx-objs := em28xx-video.o em28xx-i2c.o em28xx-cards.o em28xx-core.o \ - em28xx-input.o + em28xx-input.o em28xx-vbi.o em28xx-alsa-objs := em28xx-audio.o diff --git a/drivers/media/video/em28xx/em28xx-cards.c b/drivers/media/video/em28xx/em28xx-cards.c index 7e3c78239fa9..bdb249bd9d5d 100644 --- a/drivers/media/video/em28xx/em28xx-cards.c +++ b/drivers/media/video/em28xx/em28xx-cards.c @@ -170,6 +170,19 @@ static struct em28xx_reg_seq pinnacle_hybrid_pro_digital[] = { { -1, -1, -1, -1}, }; +/* eb1a:2868 Reddo DVB-C USB TV Box + GPIO4 - CU1216L NIM + Other GPIOs seems to be don't care. */ +static struct em28xx_reg_seq reddo_dvb_c_usb_box[] = { + {EM28XX_R08_GPIO, 0xfe, 0xff, 10}, + {EM28XX_R08_GPIO, 0xde, 0xff, 10}, + {EM28XX_R08_GPIO, 0xfe, 0xff, 10}, + {EM28XX_R08_GPIO, 0xff, 0xff, 10}, + {EM28XX_R08_GPIO, 0x7f, 0xff, 10}, + {EM28XX_R08_GPIO, 0x6f, 0xff, 10}, + {EM28XX_R08_GPIO, 0xff, 0xff, 10}, + {-1, -1, -1, -1}, +}; /* Callback for the most boards */ static struct em28xx_reg_seq default_tuner_gpio[] = { @@ -1566,6 +1579,14 @@ struct em28xx_board em28xx_boards[] = { .gpio = evga_indtube_analog, } }, }, + /* eb1a:2868 Empia EM2870 + Philips CU1216L NIM (Philips TDA10023 + + Infineon TUA6034) */ + [EM2870_BOARD_REDDO_DVB_C_USB_BOX] = { + .name = "Reddo DVB-C USB TV Box", + .tuner_type = TUNER_ABSENT, + .has_dvb = 1, + .dvb_gpio = reddo_dvb_c_usb_box, + }, }; const unsigned int em28xx_bcount = ARRAY_SIZE(em28xx_boards); @@ -1593,6 +1614,8 @@ struct usb_device_id em28xx_id_table[] = { .driver_info = EM2820_BOARD_UNKNOWN }, { USB_DEVICE(0xeb1a, 0x2883), .driver_info = EM2820_BOARD_UNKNOWN }, + { USB_DEVICE(0xeb1a, 0x2868), + .driver_info = EM2820_BOARD_UNKNOWN }, { USB_DEVICE(0xeb1a, 0xe300), .driver_info = EM2861_BOARD_KWORLD_PVRTV_300U }, { USB_DEVICE(0xeb1a, 0xe303), @@ -1696,6 +1719,7 @@ static struct em28xx_hash_table em28xx_eeprom_hash[] = { {0x166a0441, EM2880_BOARD_EMPIRE_DUAL_TV, TUNER_XC2028}, {0xcee44a99, EM2882_BOARD_EVGA_INDTUBE, TUNER_XC2028}, {0xb8846b20, EM2881_BOARD_PINNACLE_HYBRID_PRO, TUNER_XC2028}, + {0x63f653bd, EM2870_BOARD_REDDO_DVB_C_USB_BOX, TUNER_ABSENT}, }; /* I2C devicelist hash table for devices with generic USB IDs */ @@ -2348,55 +2372,55 @@ void em28xx_card_setup(struct em28xx *dev) /* request some modules */ if (dev->board.has_msp34xx) - v4l2_i2c_new_probed_subdev(&dev->v4l2_dev, &dev->i2c_adap, - "msp3400", "msp3400", msp3400_addrs); + v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, + "msp3400", "msp3400", 0, msp3400_addrs); if (dev->board.decoder == EM28XX_SAA711X) - v4l2_i2c_new_probed_subdev(&dev->v4l2_dev, &dev->i2c_adap, - "saa7115", "saa7115_auto", saa711x_addrs); + v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, + "saa7115", "saa7115_auto", 0, saa711x_addrs); if (dev->board.decoder == EM28XX_TVP5150) - v4l2_i2c_new_probed_subdev(&dev->v4l2_dev, &dev->i2c_adap, - "tvp5150", "tvp5150", tvp5150_addrs); + v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, + "tvp5150", "tvp5150", 0, tvp5150_addrs); if (dev->em28xx_sensor == EM28XX_MT9V011) { struct v4l2_subdev *sd; - sd = v4l2_i2c_new_probed_subdev(&dev->v4l2_dev, - &dev->i2c_adap, "mt9v011", "mt9v011", mt9v011_addrs); + sd = v4l2_i2c_new_subdev(&dev->v4l2_dev, + &dev->i2c_adap, "mt9v011", "mt9v011", 0, mt9v011_addrs); v4l2_subdev_call(sd, core, s_config, 0, &dev->sensor_xtal); } if (dev->board.adecoder == EM28XX_TVAUDIO) v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, - "tvaudio", "tvaudio", dev->board.tvaudio_addr); + "tvaudio", "tvaudio", dev->board.tvaudio_addr, NULL); if (dev->board.tuner_type != TUNER_ABSENT) { int has_demod = (dev->tda9887_conf & TDA9887_PRESENT); if (dev->board.radio.type) v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, - "tuner", "tuner", dev->board.radio_addr); + "tuner", "tuner", dev->board.radio_addr, NULL); if (has_demod) - v4l2_i2c_new_probed_subdev(&dev->v4l2_dev, + v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, "tuner", "tuner", - v4l2_i2c_tuner_addrs(ADDRS_DEMOD)); + 0, v4l2_i2c_tuner_addrs(ADDRS_DEMOD)); if (dev->tuner_addr == 0) { enum v4l2_i2c_tuner_type type = has_demod ? ADDRS_TV_WITH_DEMOD : ADDRS_TV; struct v4l2_subdev *sd; - sd = v4l2_i2c_new_probed_subdev(&dev->v4l2_dev, + sd = v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, "tuner", "tuner", - v4l2_i2c_tuner_addrs(type)); + 0, v4l2_i2c_tuner_addrs(type)); if (sd) dev->tuner_addr = v4l2_i2c_subdev_addr(sd); } else { v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, - "tuner", "tuner", dev->tuner_addr); + "tuner", "tuner", dev->tuner_addr, NULL); } } @@ -2570,7 +2594,8 @@ static int em28xx_init_dev(struct em28xx **devhandle, struct usb_device *udev, * Default format, used for tvp5150 or saa711x output formats */ dev->vinmode = 0x10; - dev->vinctl = 0x11; + dev->vinctl = EM28XX_VINCTRL_INTERLACED | + EM28XX_VINCTRL_CCIR656_ENABLE; /* Do board specific init and eeprom reading */ em28xx_card_setup(dev); @@ -2589,6 +2614,8 @@ static int em28xx_init_dev(struct em28xx **devhandle, struct usb_device *udev, /* init video dma queues */ INIT_LIST_HEAD(&dev->vidq.active); INIT_LIST_HEAD(&dev->vidq.queued); + INIT_LIST_HEAD(&dev->vbiq.active); + INIT_LIST_HEAD(&dev->vbiq.queued); if (dev->board.has_msp34xx) { diff --git a/drivers/media/video/em28xx/em28xx-core.c b/drivers/media/video/em28xx/em28xx-core.c index 98e140b5d95e..a88257a7d94f 100644 --- a/drivers/media/video/em28xx/em28xx-core.c +++ b/drivers/media/video/em28xx/em28xx-core.c @@ -54,6 +54,10 @@ static int alt = EM28XX_PINOUT; module_param(alt, int, 0644); MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint"); +static unsigned int disable_vbi; +module_param(disable_vbi, int, 0644); +MODULE_PARM_DESC(disable_vbi, "disable vbi support"); + /* FIXME */ #define em28xx_isocdbg(fmt, arg...) do {\ if (core_debug) \ @@ -648,9 +652,24 @@ int em28xx_capture_start(struct em28xx *dev, int start) return rc; } +int em28xx_vbi_supported(struct em28xx *dev) +{ + /* Modprobe option to manually disable */ + if (disable_vbi == 1) + return 0; + + if (dev->chip_id == CHIP_ID_EM2860 || + dev->chip_id == CHIP_ID_EM2883) + return 1; + + /* Version of em28xx that does not support VBI */ + return 0; +} + int em28xx_set_outfmt(struct em28xx *dev) { int ret; + u8 vinctrl; ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT, dev->format->reg | 0x20, 0xff); @@ -661,7 +680,16 @@ int em28xx_set_outfmt(struct em28xx *dev) if (ret < 0) return ret; - return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, dev->vinctl); + vinctrl = dev->vinctl; + if (em28xx_vbi_supported(dev) == 1) { + vinctrl |= EM28XX_VINCTRL_VBI_RAW; + em28xx_write_reg(dev, EM28XX_R34_VBI_START_H, 0x00); + em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x09); + em28xx_write_reg(dev, EM28XX_R36_VBI_WIDTH, 0xb4); + em28xx_write_reg(dev, EM28XX_R37_VBI_HEIGHT, 0x0c); + } + + return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, vinctrl); } static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax, @@ -732,7 +760,14 @@ int em28xx_resolution_set(struct em28xx *dev) em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2); - em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2); + + /* If we don't set the start position to 4 in VBI mode, we end up + with line 21 being YUYV encoded instead of being in 8-bit + greyscale */ + if (em28xx_vbi_supported(dev) == 1) + em28xx_capture_area_set(dev, 0, 4, width >> 2, height >> 2); + else + em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2); return em28xx_scaler_set(dev, dev->hscale, dev->vscale); } @@ -844,8 +879,7 @@ EXPORT_SYMBOL_GPL(em28xx_set_mode); */ static void em28xx_irq_callback(struct urb *urb) { - struct em28xx_dmaqueue *dma_q = urb->context; - struct em28xx *dev = container_of(dma_q, struct em28xx, vidq); + struct em28xx *dev = urb->context; int rc, i; switch (urb->status) { @@ -930,6 +964,7 @@ int em28xx_init_isoc(struct em28xx *dev, int max_packets, int (*isoc_copy) (struct em28xx *dev, struct urb *urb)) { struct em28xx_dmaqueue *dma_q = &dev->vidq; + struct em28xx_dmaqueue *vbi_dma_q = &dev->vbiq; int i; int sb_size, pipe; struct urb *urb; @@ -959,7 +994,8 @@ int em28xx_init_isoc(struct em28xx *dev, int max_packets, } dev->isoc_ctl.max_pkt_size = max_pkt_size; - dev->isoc_ctl.buf = NULL; + dev->isoc_ctl.vid_buf = NULL; + dev->isoc_ctl.vbi_buf = NULL; sb_size = max_packets * dev->isoc_ctl.max_pkt_size; @@ -994,7 +1030,7 @@ int em28xx_init_isoc(struct em28xx *dev, int max_packets, usb_fill_int_urb(urb, dev->udev, pipe, dev->isoc_ctl.transfer_buffer[i], sb_size, - em28xx_irq_callback, dma_q, 1); + em28xx_irq_callback, dev, 1); urb->number_of_packets = max_packets; urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP; @@ -1009,6 +1045,7 @@ int em28xx_init_isoc(struct em28xx *dev, int max_packets, } init_waitqueue_head(&dma_q->wq); + init_waitqueue_head(&vbi_dma_q->wq); em28xx_capture_start(dev, 1); @@ -1094,7 +1131,7 @@ struct em28xx *em28xx_get_device(int minor, list_for_each_entry(h, &em28xx_devlist, devlist) { if (h->vdev->minor == minor) dev = h; - if (h->vbi_dev->minor == minor) { + if (h->vbi_dev && h->vbi_dev->minor == minor) { dev = h; *fh_type = V4L2_BUF_TYPE_VBI_CAPTURE; } diff --git a/drivers/media/video/em28xx/em28xx-dvb.c b/drivers/media/video/em28xx/em28xx-dvb.c index d603575431b4..db749461e5c6 100644 --- a/drivers/media/video/em28xx/em28xx-dvb.c +++ b/drivers/media/video/em28xx/em28xx-dvb.c @@ -33,6 +33,7 @@ #include "s5h1409.h" #include "mt352.h" #include "mt352_priv.h" /* FIXME */ +#include "tda1002x.h" MODULE_DESCRIPTION("driver for em28xx based DVB cards"); MODULE_AUTHOR("Mauro Carvalho Chehab "); @@ -295,6 +296,11 @@ static struct mt352_config terratec_xs_mt352_cfg = { .demod_init = mt352_terratec_xs_init, }; +static struct tda10023_config em28xx_tda10023_config = { + .demod_address = 0x0c, + .invert = 1, +}; + /* ------------------------------------------------------------------ */ static int attach_xc3028(u8 addr, struct em28xx *dev) @@ -549,6 +555,19 @@ static int dvb_init(struct em28xx *dev) } break; #endif + case EM2870_BOARD_REDDO_DVB_C_USB_BOX: + /* Philips CU1216L NIM (Philips TDA10023 + Infineon TUA6034) */ + dvb->frontend = dvb_attach(tda10023_attach, + &em28xx_tda10023_config, + &dev->i2c_adap, 0x48); + if (dvb->frontend) { + if (!dvb_attach(simple_tuner_attach, dvb->frontend, + &dev->i2c_adap, 0x60, TUNER_PHILIPS_CU1216L)) { + result = -EINVAL; + goto out_free; + } + } + break; default: printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card" " isn't supported yet\n", diff --git a/drivers/media/video/em28xx/em28xx-reg.h b/drivers/media/video/em28xx/em28xx-reg.h index 6bf84bd787df..ed12e7ffcbd0 100644 --- a/drivers/media/video/em28xx/em28xx-reg.h +++ b/drivers/media/video/em28xx/em28xx-reg.h @@ -86,7 +86,19 @@ #define EM28XX_XCLK_FREQUENCY_24MHZ 0x0b #define EM28XX_R10_VINMODE 0x10 + #define EM28XX_R11_VINCTRL 0x11 + +/* em28xx Video Input Control Register 0x11 */ +#define EM28XX_VINCTRL_VBI_SLICED 0x80 +#define EM28XX_VINCTRL_VBI_RAW 0x40 +#define EM28XX_VINCTRL_VOUT_MODE_IN 0x20 /* HREF,VREF,VACT in output */ +#define EM28XX_VINCTRL_CCIR656_ENABLE 0x10 +#define EM28XX_VINCTRL_VBI_16BIT_RAW 0x08 /* otherwise 8-bit raw */ +#define EM28XX_VINCTRL_FID_ON_HREF 0x04 +#define EM28XX_VINCTRL_DUAL_EDGE_STROBE 0x02 +#define EM28XX_VINCTRL_INTERLACED 0x01 + #define EM28XX_R12_VINENABLE 0x12 /* */ #define EM28XX_R14_GAMMA 0x14 @@ -135,6 +147,10 @@ #define EM28XX_R31_HSCALEHIGH 0x31 #define EM28XX_R32_VSCALELOW 0x32 #define EM28XX_R33_VSCALEHIGH 0x33 +#define EM28XX_R34_VBI_START_H 0x34 +#define EM28XX_R35_VBI_START_V 0x35 +#define EM28XX_R36_VBI_WIDTH 0x36 +#define EM28XX_R37_VBI_HEIGHT 0x37 #define EM28XX_R40_AC97LSB 0x40 #define EM28XX_R41_AC97MSB 0x41 diff --git a/drivers/media/video/em28xx/em28xx-vbi.c b/drivers/media/video/em28xx/em28xx-vbi.c new file mode 100644 index 000000000000..94943e5a1529 --- /dev/null +++ b/drivers/media/video/em28xx/em28xx-vbi.c @@ -0,0 +1,142 @@ +/* + em28xx-vbi.c - VBI driver for em28xx + + Copyright (C) 2009 Devin Heitmueller + + This work was sponsored by EyeMagnet Limited. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. + */ + +#include +#include +#include +#include + +#include "em28xx.h" + +static unsigned int vbibufs = 5; +module_param(vbibufs, int, 0644); +MODULE_PARM_DESC(vbibufs, "number of vbi buffers, range 2-32"); + +static unsigned int vbi_debug; +module_param(vbi_debug, int, 0644); +MODULE_PARM_DESC(vbi_debug, "enable debug messages [vbi]"); + +#define dprintk(level, fmt, arg...) if (vbi_debug >= level) \ + printk(KERN_DEBUG "%s: " fmt, dev->core->name , ## arg) + +/* ------------------------------------------------------------------ */ + +static void +free_buffer(struct videobuf_queue *vq, struct em28xx_buffer *buf) +{ + struct em28xx_fh *fh = vq->priv_data; + struct em28xx *dev = fh->dev; + unsigned long flags = 0; + if (in_interrupt()) + BUG(); + + /* We used to wait for the buffer to finish here, but this didn't work + because, as we were keeping the state as VIDEOBUF_QUEUED, + videobuf_queue_cancel marked it as finished for us. + (Also, it could wedge forever if the hardware was misconfigured.) + + This should be safe; by the time we get here, the buffer isn't + queued anymore. If we ever start marking the buffers as + VIDEOBUF_ACTIVE, it won't be, though. + */ + spin_lock_irqsave(&dev->slock, flags); + if (dev->isoc_ctl.vbi_buf == buf) + dev->isoc_ctl.vbi_buf = NULL; + spin_unlock_irqrestore(&dev->slock, flags); + + videobuf_vmalloc_free(&buf->vb); + buf->vb.state = VIDEOBUF_NEEDS_INIT; +} + +static int +vbi_setup(struct videobuf_queue *q, unsigned int *count, unsigned int *size) +{ + *size = 720 * 12 * 2; + if (0 == *count) + *count = vbibufs; + if (*count < 2) + *count = 2; + if (*count > 32) + *count = 32; + return 0; +} + +static int +vbi_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb, + enum v4l2_field field) +{ + struct em28xx_buffer *buf = container_of(vb, struct em28xx_buffer, vb); + int rc = 0; + unsigned int size; + + size = 720 * 12 * 2; + + buf->vb.size = size; + + if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size) + return -EINVAL; + + buf->vb.width = 720; + buf->vb.height = 12; + buf->vb.field = field; + + if (VIDEOBUF_NEEDS_INIT == buf->vb.state) { + rc = videobuf_iolock(q, &buf->vb, NULL); + if (rc < 0) + goto fail; + } + + buf->vb.state = VIDEOBUF_PREPARED; + return 0; + +fail: + free_buffer(q, buf); + return rc; +} + +static void +vbi_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct em28xx_buffer *buf = container_of(vb, + struct em28xx_buffer, + vb); + struct em28xx_fh *fh = vq->priv_data; + struct em28xx *dev = fh->dev; + struct em28xx_dmaqueue *vbiq = &dev->vbiq; + + buf->vb.state = VIDEOBUF_QUEUED; + list_add_tail(&buf->vb.queue, &vbiq->active); +} + +static void vbi_release(struct videobuf_queue *q, struct videobuf_buffer *vb) +{ + struct em28xx_buffer *buf = container_of(vb, struct em28xx_buffer, vb); + free_buffer(q, buf); +} + +struct videobuf_queue_ops em28xx_vbi_qops = { + .buf_setup = vbi_setup, + .buf_prepare = vbi_prepare, + .buf_queue = vbi_queue, + .buf_release = vbi_release, +}; diff --git a/drivers/media/video/em28xx/em28xx-video.c b/drivers/media/video/em28xx/em28xx-video.c index a6bdbc21410e..3a1dfb7726f8 100644 --- a/drivers/media/video/em28xx/em28xx-video.c +++ b/drivers/media/video/em28xx/em28xx-video.c @@ -163,7 +163,24 @@ static inline void buffer_filled(struct em28xx *dev, buf->vb.field_count++; do_gettimeofday(&buf->vb.ts); - dev->isoc_ctl.buf = NULL; + dev->isoc_ctl.vid_buf = NULL; + + list_del(&buf->vb.queue); + wake_up(&buf->vb.done); +} + +static inline void vbi_buffer_filled(struct em28xx *dev, + struct em28xx_dmaqueue *dma_q, + struct em28xx_buffer *buf) +{ + /* Advice that buffer was filled */ + em28xx_isocdbg("[%p/%d] wakeup\n", buf, buf->vb.i); + + buf->vb.state = VIDEOBUF_DONE; + buf->vb.field_count++; + do_gettimeofday(&buf->vb.ts); + + dev->isoc_ctl.vbi_buf = NULL; list_del(&buf->vb.queue); wake_up(&buf->vb.done); @@ -239,7 +256,8 @@ static void em28xx_copy_video(struct em28xx *dev, if ((char *)startwrite + lencopy > (char *)outp + buf->vb.size) { - em28xx_isocdbg("Overflow of %zi bytes past buffer end (2)\n", + em28xx_isocdbg("Overflow of %zi bytes past buffer end" + "(2)\n", ((char *)startwrite + lencopy) - ((char *)outp + buf->vb.size)); lencopy = remain = (char *)outp + buf->vb.size - @@ -256,6 +274,63 @@ static void em28xx_copy_video(struct em28xx *dev, dma_q->pos += len; } +static void em28xx_copy_vbi(struct em28xx *dev, + struct em28xx_dmaqueue *dma_q, + struct em28xx_buffer *buf, + unsigned char *p, + unsigned char *outp, unsigned long len) +{ + void *startwrite, *startread; + int offset; + int bytesperline = 720; + + if (dev == NULL) { + em28xx_isocdbg("dev is null\n"); + return; + } + + if (dma_q == NULL) { + em28xx_isocdbg("dma_q is null\n"); + return; + } + if (buf == NULL) { + return; + } + if (p == NULL) { + em28xx_isocdbg("p is null\n"); + return; + } + if (outp == NULL) { + em28xx_isocdbg("outp is null\n"); + return; + } + + if (dma_q->pos + len > buf->vb.size) + len = buf->vb.size - dma_q->pos; + + if ((p[0] == 0x33 && p[1] == 0x95) || + (p[0] == 0x88 && p[1] == 0x88)) { + /* Header field, advance past it */ + p += 4; + } else { + len += 4; + } + + startread = p; + + startwrite = outp + dma_q->pos; + offset = dma_q->pos; + + /* Make sure the bottom field populates the second half of the frame */ + if (buf->top_field == 0) { + startwrite += bytesperline * 0x0c; + offset += bytesperline * 0x0c; + } + + memcpy(startwrite, startread, len); + dma_q->pos += len; +} + static inline void print_err_status(struct em28xx *dev, int packet, int status) { @@ -306,7 +381,7 @@ static inline void get_next_buf(struct em28xx_dmaqueue *dma_q, if (list_empty(&dma_q->active)) { em28xx_isocdbg("No active queue to serve\n"); - dev->isoc_ctl.buf = NULL; + dev->isoc_ctl.vid_buf = NULL; *buf = NULL; return; } @@ -318,7 +393,34 @@ static inline void get_next_buf(struct em28xx_dmaqueue *dma_q, outp = videobuf_to_vmalloc(&(*buf)->vb); memset(outp, 0, (*buf)->vb.size); - dev->isoc_ctl.buf = *buf; + dev->isoc_ctl.vid_buf = *buf; + + return; +} + +/* + * video-buf generic routine to get the next available VBI buffer + */ +static inline void vbi_get_next_buf(struct em28xx_dmaqueue *dma_q, + struct em28xx_buffer **buf) +{ + struct em28xx *dev = container_of(dma_q, struct em28xx, vbiq); + char *outp; + + if (list_empty(&dma_q->active)) { + em28xx_isocdbg("No active queue to serve\n"); + dev->isoc_ctl.vbi_buf = NULL; + *buf = NULL; + return; + } + + /* Get the next buffer */ + *buf = list_entry(dma_q->active.next, struct em28xx_buffer, vb.queue); + /* Cleans up buffer - Usefull for testing for frame/URB loss */ + outp = videobuf_to_vmalloc(&(*buf)->vb); + memset(outp, 0x00, (*buf)->vb.size); + + dev->isoc_ctl.vbi_buf = *buf; return; } @@ -329,7 +431,7 @@ static inline void get_next_buf(struct em28xx_dmaqueue *dma_q, static inline int em28xx_isoc_copy(struct em28xx *dev, struct urb *urb) { struct em28xx_buffer *buf; - struct em28xx_dmaqueue *dma_q = urb->context; + struct em28xx_dmaqueue *dma_q = &dev->vidq; unsigned char *outp = NULL; int i, len = 0, rc = 1; unsigned char *p; @@ -346,7 +448,7 @@ static inline int em28xx_isoc_copy(struct em28xx *dev, struct urb *urb) return 0; } - buf = dev->isoc_ctl.buf; + buf = dev->isoc_ctl.vid_buf; if (buf != NULL) outp = videobuf_to_vmalloc(&buf->vb); @@ -410,6 +512,153 @@ static inline int em28xx_isoc_copy(struct em28xx *dev, struct urb *urb) return rc; } +/* Version of isoc handler that takes into account a mixture of video and + VBI data */ +static inline int em28xx_isoc_copy_vbi(struct em28xx *dev, struct urb *urb) +{ + struct em28xx_buffer *buf, *vbi_buf; + struct em28xx_dmaqueue *dma_q = &dev->vidq; + struct em28xx_dmaqueue *vbi_dma_q = &dev->vbiq; + unsigned char *outp = NULL; + unsigned char *vbioutp = NULL; + int i, len = 0, rc = 1; + unsigned char *p; + int vbi_size; + + if (!dev) + return 0; + + if ((dev->state & DEV_DISCONNECTED) || (dev->state & DEV_MISCONFIGURED)) + return 0; + + if (urb->status < 0) { + print_err_status(dev, -1, urb->status); + if (urb->status == -ENOENT) + return 0; + } + + buf = dev->isoc_ctl.vid_buf; + if (buf != NULL) + outp = videobuf_to_vmalloc(&buf->vb); + + vbi_buf = dev->isoc_ctl.vbi_buf; + if (vbi_buf != NULL) + vbioutp = videobuf_to_vmalloc(&vbi_buf->vb); + + for (i = 0; i < urb->number_of_packets; i++) { + int status = urb->iso_frame_desc[i].status; + + if (status < 0) { + print_err_status(dev, i, status); + if (urb->iso_frame_desc[i].status != -EPROTO) + continue; + } + + len = urb->iso_frame_desc[i].actual_length - 4; + + if (urb->iso_frame_desc[i].actual_length <= 0) { + /* em28xx_isocdbg("packet %d is empty",i); - spammy */ + continue; + } + if (urb->iso_frame_desc[i].actual_length > + dev->max_pkt_size) { + em28xx_isocdbg("packet bigger than packet size"); + continue; + } + + p = urb->transfer_buffer + urb->iso_frame_desc[i].offset; + + /* capture type 0 = vbi start + capture type 1 = video start + capture type 2 = video in progress */ + if (p[0] == 0x33 && p[1] == 0x95) { + dev->capture_type = 0; + dev->vbi_read = 0; + em28xx_isocdbg("VBI START HEADER!!!\n"); + dev->cur_field = p[2]; + } + + /* FIXME: get rid of hard-coded value */ + vbi_size = 720 * 0x0c; + + if (dev->capture_type == 0) { + if (dev->vbi_read >= vbi_size) { + /* We've already read all the VBI data, so + treat the rest as video */ + em28xx_isocdbg("dev->vbi_read > vbi_size\n"); + } else if ((dev->vbi_read + len) < vbi_size) { + /* This entire frame is VBI data */ + if (dev->vbi_read == 0 && + (!(dev->cur_field & 1))) { + /* Brand new frame */ + if (vbi_buf != NULL) + vbi_buffer_filled(dev, + vbi_dma_q, + vbi_buf); + vbi_get_next_buf(vbi_dma_q, &vbi_buf); + if (vbi_buf == NULL) + vbioutp = NULL; + else + vbioutp = videobuf_to_vmalloc( + &vbi_buf->vb); + } + + if (dev->vbi_read == 0) { + vbi_dma_q->pos = 0; + if (vbi_buf != NULL) { + if (dev->cur_field & 1) + vbi_buf->top_field = 0; + else + vbi_buf->top_field = 1; + } + } + + dev->vbi_read += len; + em28xx_copy_vbi(dev, vbi_dma_q, vbi_buf, p, + vbioutp, len); + } else { + /* Some of this frame is VBI data and some is + video data */ + int vbi_data_len = vbi_size - dev->vbi_read; + dev->vbi_read += vbi_data_len; + em28xx_copy_vbi(dev, vbi_dma_q, vbi_buf, p, + vbioutp, vbi_data_len); + dev->capture_type = 1; + p += vbi_data_len; + len -= vbi_data_len; + } + } + + if (dev->capture_type == 1) { + dev->capture_type = 2; + em28xx_isocdbg("Video frame %d, length=%i, %s\n", p[2], + len, (p[2] & 1) ? "odd" : "even"); + + if (dev->progressive || !(dev->cur_field & 1)) { + if (buf != NULL) + buffer_filled(dev, dma_q, buf); + get_next_buf(dma_q, &buf); + if (buf == NULL) + outp = NULL; + else + outp = videobuf_to_vmalloc(&buf->vb); + } + if (buf != NULL) { + if (dev->cur_field & 1) + buf->top_field = 0; + else + buf->top_field = 1; + } + + dma_q->pos = 0; + } + if (buf != NULL && dev->capture_type == 2) + em28xx_copy_video(dev, dma_q, buf, p, outp, len); + } + return rc; +} + + /* ------------------------------------------------------------------ Videobuf operations ------------------------------------------------------------------*/ @@ -421,7 +670,8 @@ buffer_setup(struct videobuf_queue *vq, unsigned int *count, unsigned int *size) struct em28xx *dev = fh->dev; struct v4l2_frequency f; - *size = (fh->dev->width * fh->dev->height * dev->format->depth + 7) >> 3; + *size = (fh->dev->width * fh->dev->height * dev->format->depth + 7) + >> 3; if (0 == *count) *count = EM28XX_DEF_BUF; @@ -458,8 +708,8 @@ static void free_buffer(struct videobuf_queue *vq, struct em28xx_buffer *buf) VIDEOBUF_ACTIVE, it won't be, though. */ spin_lock_irqsave(&dev->slock, flags); - if (dev->isoc_ctl.buf == buf) - dev->isoc_ctl.buf = NULL; + if (dev->isoc_ctl.vid_buf == buf) + dev->isoc_ctl.vid_buf = NULL; spin_unlock_irqrestore(&dev->slock, flags); videobuf_vmalloc_free(&buf->vb); @@ -475,7 +725,8 @@ buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb, struct em28xx *dev = fh->dev; int rc = 0, urb_init = 0; - buf->vb.size = (fh->dev->width * fh->dev->height * dev->format->depth + 7) >> 3; + buf->vb.size = (fh->dev->width * fh->dev->height * dev->format->depth + + 7) >> 3; if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size) return -EINVAL; @@ -494,9 +745,16 @@ buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb, urb_init = 1; if (urb_init) { - rc = em28xx_init_isoc(dev, EM28XX_NUM_PACKETS, - EM28XX_NUM_BUFS, dev->max_pkt_size, - em28xx_isoc_copy); + if (em28xx_vbi_supported(dev) == 1) + rc = em28xx_init_isoc(dev, EM28XX_NUM_PACKETS, + EM28XX_NUM_BUFS, + dev->max_pkt_size, + em28xx_isoc_copy_vbi); + else + rc = em28xx_init_isoc(dev, EM28XX_NUM_PACKETS, + EM28XX_NUM_BUFS, + dev->max_pkt_size, + em28xx_isoc_copy); if (rc < 0) goto fail; } @@ -578,34 +836,63 @@ static void video_mux(struct em28xx *dev, int index) } /* Usage lock check functions */ -static int res_get(struct em28xx_fh *fh) +static int res_get(struct em28xx_fh *fh, unsigned int bit) { struct em28xx *dev = fh->dev; - int rc = 0; - /* This instance already has stream_on */ - if (fh->stream_on) - return rc; + if (fh->resources & bit) + /* have it already allocated */ + return 1; - if (dev->stream_on) - return -EBUSY; + /* is it free? */ + mutex_lock(&dev->lock); + if (dev->resources & bit) { + /* no, someone else uses it */ + mutex_unlock(&dev->lock); + return 0; + } + /* it's free, grab it */ + fh->resources |= bit; + dev->resources |= bit; + em28xx_videodbg("res: get %d\n", bit); + mutex_unlock(&dev->lock); + return 1; +} - dev->stream_on = 1; - fh->stream_on = 1; - return rc; +static int res_check(struct em28xx_fh *fh, unsigned int bit) +{ + return fh->resources & bit; } -static int res_check(struct em28xx_fh *fh) +static int res_locked(struct em28xx *dev, unsigned int bit) { - return fh->stream_on; + return dev->resources & bit; } -static void res_free(struct em28xx_fh *fh) +static void res_free(struct em28xx_fh *fh, unsigned int bits) { struct em28xx *dev = fh->dev; - fh->stream_on = 0; - dev->stream_on = 0; + BUG_ON((fh->resources & bits) != bits); + + mutex_lock(&dev->lock); + fh->resources &= ~bits; + dev->resources &= ~bits; + em28xx_videodbg("res: put %d\n", bits); + mutex_unlock(&dev->lock); +} + +static int get_ressource(struct em28xx_fh *fh) +{ + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + return EM28XX_RESOURCE_VIDEO; + case V4L2_BUF_TYPE_VBI_CAPTURE: + return EM28XX_RESOURCE_VBI; + default: + BUG(); + return 0; + } } /* @@ -782,7 +1069,8 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, } else { /* width must even because of the YUYV format height must be even because of interlacing */ - v4l_bound_align_image(&width, 48, maxw, 1, &height, 32, maxh, 1, 0); + v4l_bound_align_image(&width, 48, maxw, 1, &height, 32, maxh, + 1, 0); } get_scale(dev, width, height, &hscale, &vscale); @@ -848,12 +1136,6 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, goto out; } - if (dev->stream_on && !fh->stream_on) { - em28xx_errdev("%s device in use by another fh\n", __func__); - rc = -EBUSY; - goto out; - } - rc = em28xx_set_video_format(dev, f->fmt.pix.pixelformat, f->fmt.pix.width, f->fmt.pix.height); @@ -862,6 +1144,21 @@ out: return rc; } +static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *norm) +{ + struct em28xx_fh *fh = priv; + struct em28xx *dev = fh->dev; + int rc; + + rc = check_dev(dev); + if (rc < 0) + return rc; + + *norm = dev->norm; + + return 0; +} + static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *norm) { struct em28xx_fh *fh = priv; @@ -1413,20 +1710,25 @@ static int vidioc_streamon(struct file *file, void *priv, { struct em28xx_fh *fh = priv; struct em28xx *dev = fh->dev; - int rc; + int rc = -EINVAL; rc = check_dev(dev); if (rc < 0) return rc; + if (unlikely(type != fh->type)) + return -EINVAL; - mutex_lock(&dev->lock); - rc = res_get(fh); + em28xx_videodbg("vidioc_streamon fh=%p t=%d fh->res=%d dev->res=%d\n", + fh, type, fh->resources, dev->resources); - if (likely(rc >= 0)) - rc = videobuf_streamon(&fh->vb_vidq); + if (unlikely(!res_get(fh, get_ressource(fh)))) + return -EBUSY; - mutex_unlock(&dev->lock); + if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + rc = videobuf_streamon(&fh->vb_vidq); + else if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE) + rc = videobuf_streamon(&fh->vb_vbiq); return rc; } @@ -1442,17 +1744,22 @@ static int vidioc_streamoff(struct file *file, void *priv, if (rc < 0) return rc; - if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && + fh->type != V4L2_BUF_TYPE_VBI_CAPTURE) return -EINVAL; if (type != fh->type) return -EINVAL; - mutex_lock(&dev->lock); + em28xx_videodbg("vidioc_streamoff fh=%p t=%d fh->res=%d dev->res=%d\n", + fh, type, fh->resources, dev->resources); - videobuf_streamoff(&fh->vb_vidq); - res_free(fh); - - mutex_unlock(&dev->lock); + if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) { + videobuf_streamoff(&fh->vb_vidq); + res_free(fh, EM28XX_RESOURCE_VIDEO); + } else if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE) { + videobuf_streamoff(&fh->vb_vbiq); + res_free(fh, EM28XX_RESOURCE_VBI); + } return 0; } @@ -1474,6 +1781,9 @@ static int vidioc_querycap(struct file *file, void *priv, V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | V4L2_CAP_STREAMING; + if (dev->vbi_dev) + cap->capabilities |= V4L2_CAP_VBI_CAPTURE; + if (dev->audio_mode.has_audio) cap->capabilities |= V4L2_CAP_AUDIO; @@ -1541,6 +1851,45 @@ static int vidioc_try_set_sliced_vbi_cap(struct file *file, void *priv, return 0; } +/* RAW VBI ioctls */ + +static int vidioc_g_fmt_vbi_cap(struct file *file, void *priv, + struct v4l2_format *format) +{ + format->fmt.vbi.samples_per_line = 720; + format->fmt.vbi.sample_format = V4L2_PIX_FMT_GREY; + format->fmt.vbi.offset = 0; + format->fmt.vbi.flags = 0; + + /* Varies by video standard (NTSC, PAL, etc.) */ + /* FIXME: hard-coded for NTSC support */ + format->fmt.vbi.sampling_rate = 6750000 * 4 / 2; /* FIXME: ??? */ + format->fmt.vbi.count[0] = 12; + format->fmt.vbi.count[1] = 12; + format->fmt.vbi.start[0] = 10; + format->fmt.vbi.start[1] = 273; + + return 0; +} + +static int vidioc_s_fmt_vbi_cap(struct file *file, void *priv, + struct v4l2_format *format) +{ + format->fmt.vbi.samples_per_line = 720; + format->fmt.vbi.sample_format = V4L2_PIX_FMT_GREY; + format->fmt.vbi.offset = 0; + format->fmt.vbi.flags = 0; + + /* Varies by video standard (NTSC, PAL, etc.) */ + /* FIXME: hard-coded for NTSC support */ + format->fmt.vbi.sampling_rate = 6750000 * 4 / 2; /* FIXME: ??? */ + format->fmt.vbi.count[0] = 12; + format->fmt.vbi.count[1] = 12; + format->fmt.vbi.start[0] = 10; + format->fmt.vbi.start[1] = 273; + + return 0; +} static int vidioc_reqbufs(struct file *file, void *priv, struct v4l2_requestbuffers *rb) @@ -1553,7 +1902,10 @@ static int vidioc_reqbufs(struct file *file, void *priv, if (rc < 0) return rc; - return videobuf_reqbufs(&fh->vb_vidq, rb); + if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + return videobuf_reqbufs(&fh->vb_vidq, rb); + else + return videobuf_reqbufs(&fh->vb_vbiq, rb); } static int vidioc_querybuf(struct file *file, void *priv, @@ -1567,7 +1919,18 @@ static int vidioc_querybuf(struct file *file, void *priv, if (rc < 0) return rc; - return videobuf_querybuf(&fh->vb_vidq, b); + if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + return videobuf_querybuf(&fh->vb_vidq, b); + else { + /* FIXME: I'm not sure yet whether this is a bug in zvbi or + the videobuf framework, but we probably shouldn't be + returning a buffer larger than that which was asked for. + At a minimum, it causes a crash in zvbi since it does + a memcpy based on the source buffer length */ + int result = videobuf_querybuf(&fh->vb_vbiq, b); + b->length = 17280; + return result; + } } static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *b) @@ -1580,7 +1943,10 @@ static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *b) if (rc < 0) return rc; - return videobuf_qbuf(&fh->vb_vidq, b); + if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + return videobuf_qbuf(&fh->vb_vidq, b); + else + return videobuf_qbuf(&fh->vb_vbiq, b); } static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b) @@ -1593,7 +1959,12 @@ static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b) if (rc < 0) return rc; - return videobuf_dqbuf(&fh->vb_vidq, b, file->f_flags & O_NONBLOCK); + if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + return videobuf_dqbuf(&fh->vb_vidq, b, file->f_flags & + O_NONBLOCK); + else + return videobuf_dqbuf(&fh->vb_vbiq, b, file->f_flags & + O_NONBLOCK); } #ifdef CONFIG_VIDEO_V4L1_COMPAT @@ -1601,7 +1972,10 @@ static int vidiocgmbuf(struct file *file, void *priv, struct video_mbuf *mbuf) { struct em28xx_fh *fh = priv; - return videobuf_cgmbuf(&fh->vb_vidq, mbuf, 8); + if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + return videobuf_cgmbuf(&fh->vb_vidq, mbuf, 8); + else + return videobuf_cgmbuf(&fh->vb_vbiq, mbuf, 8); } #endif @@ -1766,8 +2140,15 @@ static int em28xx_v4l2_open(struct file *filp) field = V4L2_FIELD_INTERLACED; videobuf_queue_vmalloc_init(&fh->vb_vidq, &em28xx_video_qops, - NULL, &dev->slock, fh->type, field, - sizeof(struct em28xx_buffer), fh); + NULL, &dev->slock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, field, + sizeof(struct em28xx_buffer), fh); + + videobuf_queue_vmalloc_init(&fh->vb_vbiq, &em28xx_vbi_qops, + NULL, &dev->slock, + V4L2_BUF_TYPE_VBI_CAPTURE, + V4L2_FIELD_SEQ_TB, + sizeof(struct em28xx_buffer), fh); mutex_unlock(&dev->lock); @@ -1824,20 +2205,21 @@ static int em28xx_v4l2_close(struct file *filp) em28xx_videodbg("users=%d\n", dev->users); + if (res_check(fh, EM28XX_RESOURCE_VIDEO)) { + videobuf_stop(&fh->vb_vidq); + res_free(fh, EM28XX_RESOURCE_VIDEO); + } - mutex_lock(&dev->lock); - if (res_check(fh)) - res_free(fh); + if (res_check(fh, EM28XX_RESOURCE_VBI)) { + videobuf_stop(&fh->vb_vbiq); + res_free(fh, EM28XX_RESOURCE_VBI); + } if (dev->users == 1) { - videobuf_stop(&fh->vb_vidq); - videobuf_mmap_free(&fh->vb_vidq); - /* the device is already disconnect, free the remaining resources */ if (dev->state & DEV_DISCONNECTED) { em28xx_release_resources(dev); - mutex_unlock(&dev->lock); kfree(dev); return 0; } @@ -1858,10 +2240,12 @@ static int em28xx_v4l2_close(struct file *filp) "0 (error=%i)\n", errCode); } } + + videobuf_mmap_free(&fh->vb_vidq); + videobuf_mmap_free(&fh->vb_vbiq); kfree(fh); dev->users--; wake_up_interruptible_nr(&dev->open, 1); - mutex_unlock(&dev->lock); return 0; } @@ -1886,16 +2270,22 @@ em28xx_v4l2_read(struct file *filp, char __user *buf, size_t count, */ if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) { - mutex_lock(&dev->lock); - rc = res_get(fh); - mutex_unlock(&dev->lock); - - if (unlikely(rc < 0)) - return rc; + if (res_locked(dev, EM28XX_RESOURCE_VIDEO)) + return -EBUSY; return videobuf_read_stream(&fh->vb_vidq, buf, count, pos, 0, filp->f_flags & O_NONBLOCK); } + + + if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE) { + if (!res_get(fh, EM28XX_RESOURCE_VBI)) + return -EBUSY; + + return videobuf_read_stream(&fh->vb_vbiq, buf, count, pos, 0, + filp->f_flags & O_NONBLOCK); + } + return 0; } @@ -1913,17 +2303,17 @@ static unsigned int em28xx_v4l2_poll(struct file *filp, poll_table *wait) if (rc < 0) return rc; - mutex_lock(&dev->lock); - rc = res_get(fh); - mutex_unlock(&dev->lock); - - if (unlikely(rc < 0)) - return POLLERR; - - if (V4L2_BUF_TYPE_VIDEO_CAPTURE != fh->type) + if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) { + if (!res_get(fh, EM28XX_RESOURCE_VIDEO)) + return POLLERR; + return videobuf_poll_stream(filp, &fh->vb_vidq, wait); + } else if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE) { + if (!res_get(fh, EM28XX_RESOURCE_VBI)) + return POLLERR; + return videobuf_poll_stream(filp, &fh->vb_vbiq, wait); + } else { return POLLERR; - - return videobuf_poll_stream(filp, &fh->vb_vidq, wait); + } } /* @@ -1939,14 +2329,10 @@ static int em28xx_v4l2_mmap(struct file *filp, struct vm_area_struct *vma) if (rc < 0) return rc; - mutex_lock(&dev->lock); - rc = res_get(fh); - mutex_unlock(&dev->lock); - - if (unlikely(rc < 0)) - return rc; - - rc = videobuf_mmap_mapper(&fh->vb_vidq, vma); + if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + rc = videobuf_mmap_mapper(&fh->vb_vidq, vma); + else if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE) + rc = videobuf_mmap_mapper(&fh->vb_vbiq, vma); em28xx_videodbg("vma start=0x%08lx, size=%ld, ret=%d\n", (unsigned long)vma->vm_start, @@ -1972,6 +2358,8 @@ static const struct v4l2_ioctl_ops video_ioctl_ops = { .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_g_fmt_vbi_cap = vidioc_g_fmt_vbi_cap, + .vidioc_s_fmt_vbi_cap = vidioc_s_fmt_vbi_cap, .vidioc_g_audio = vidioc_g_audio, .vidioc_s_audio = vidioc_s_audio, .vidioc_cropcap = vidioc_cropcap, @@ -1984,6 +2372,7 @@ static const struct v4l2_ioctl_ops video_ioctl_ops = { .vidioc_querybuf = vidioc_querybuf, .vidioc_qbuf = vidioc_qbuf, .vidioc_dqbuf = vidioc_dqbuf, + .vidioc_g_std = vidioc_g_std, .vidioc_s_std = vidioc_s_std, .vidioc_g_parm = vidioc_g_parm, .vidioc_s_parm = vidioc_s_parm, @@ -2105,13 +2494,10 @@ int em28xx_register_analog_devices(struct em28xx *dev) dev->mute = 1; dev->volume = 0x1f; - /* enable vbi capturing */ - /* em28xx_write_reg(dev, EM28XX_R0E_AUDIOSRC, 0xc0); audio register */ val = (u8)em28xx_read_reg(dev, EM28XX_R0F_XCLK); em28xx_write_reg(dev, EM28XX_R0F_XCLK, (EM28XX_XCLK_AUDIO_UNMUTE | val)); - em28xx_write_reg(dev, EM28XX_R11_VINCTRL, 0x51); em28xx_set_outfmt(dev); em28xx_colorlevels_set_default(dev); @@ -2134,14 +2520,17 @@ int em28xx_register_analog_devices(struct em28xx *dev) } /* Allocate and fill vbi video_device struct */ - dev->vbi_dev = em28xx_vdev_init(dev, &em28xx_video_template, "vbi"); + if (em28xx_vbi_supported(dev) == 1) { + dev->vbi_dev = em28xx_vdev_init(dev, &em28xx_video_template, + "vbi"); - /* register v4l2 vbi video_device */ - ret = video_register_device(dev->vbi_dev, VFL_TYPE_VBI, - vbi_nr[dev->devno]); - if (ret < 0) { - em28xx_errdev("unable to register vbi device\n"); - return ret; + /* register v4l2 vbi video_device */ + ret = video_register_device(dev->vbi_dev, VFL_TYPE_VBI, + vbi_nr[dev->devno]); + if (ret < 0) { + em28xx_errdev("unable to register vbi device\n"); + return ret; + } } if (em28xx_boards[dev->model].radio.type == EM28XX_RADIO) { @@ -2161,8 +2550,12 @@ int em28xx_register_analog_devices(struct em28xx *dev) dev->radio_dev->num); } - em28xx_info("V4L2 device registered as /dev/video%d and /dev/vbi%d\n", - dev->vdev->num, dev->vbi_dev->num); + em28xx_info("V4L2 video device registered as /dev/video%d\n", + dev->vdev->num); + + if (dev->vbi_dev) + em28xx_info("V4L2 VBI device registered as /dev/vbi%d\n", + dev->vbi_dev->num); return 0; } diff --git a/drivers/media/video/em28xx/em28xx.h b/drivers/media/video/em28xx/em28xx.h index 0f2ba9a40d17..0a73e8bf0d6e 100644 --- a/drivers/media/video/em28xx/em28xx.h +++ b/drivers/media/video/em28xx/em28xx.h @@ -109,6 +109,7 @@ #define EM2882_BOARD_EVGA_INDTUBE 70 #define EM2820_BOARD_SILVERCREST_WEBCAM 71 #define EM2861_BOARD_GADMEI_UTV330PLUS 72 +#define EM2870_BOARD_REDDO_DVB_C_USB_BOX 73 /* Limits minimum and default number of buffers */ #define EM28XX_MIN_BUF 4 @@ -214,7 +215,8 @@ struct em28xx_usb_isoc_ctl { int tmp_buf_len; /* Stores already requested buffers */ - struct em28xx_buffer *buf; + struct em28xx_buffer *vid_buf; + struct em28xx_buffer *vbi_buf; /* Stores the number of received fields */ int nfields; @@ -443,6 +445,10 @@ enum em28xx_dev_state { #define EM28XX_AUDIO 0x10 #define EM28XX_DVB 0x20 +/* em28xx resource types (used for res_get/res_lock etc */ +#define EM28XX_RESOURCE_VIDEO 0x01 +#define EM28XX_RESOURCE_VBI 0x02 + struct em28xx_audio { char name[50]; char *transfer_buffer[EM28XX_AUDIO_BUFS]; @@ -463,10 +469,11 @@ struct em28xx; struct em28xx_fh { struct em28xx *dev; - unsigned int stream_on:1; /* Locks streams */ int radio; + unsigned int resources; struct videobuf_queue vb_vidq; + struct videobuf_queue vb_vbiq; enum v4l2_buf_type type; }; @@ -493,7 +500,6 @@ struct em28xx { /* Vinmode/Vinctl used at the driver */ int vinmode, vinctl; - unsigned int stream_on:1; /* Locks streams */ unsigned int has_audio_class:1; unsigned int has_alsa_audio:1; @@ -544,6 +550,12 @@ struct em28xx { enum em28xx_dev_state state; enum em28xx_io_method io; + /* vbi related state tracking */ + int capture_type; + int vbi_read; + unsigned char cur_field; + + struct work_struct request_module_wk; /* locks */ @@ -555,10 +567,14 @@ struct em28xx { struct video_device *vbi_dev; struct video_device *radio_dev; + /* resources in use */ + unsigned int resources; + unsigned char eedata[256]; /* Isoc control struct */ struct em28xx_dmaqueue vidq; + struct em28xx_dmaqueue vbiq; struct em28xx_usb_isoc_ctl isoc_ctl; spinlock_t slock; @@ -639,6 +655,7 @@ int em28xx_audio_setup(struct em28xx *dev); int em28xx_colorlevels_set_default(struct em28xx *dev); int em28xx_capture_start(struct em28xx *dev, int start); +int em28xx_vbi_supported(struct em28xx *dev); int em28xx_set_outfmt(struct em28xx *dev); int em28xx_resolution_set(struct em28xx *dev); int em28xx_set_alternate(struct em28xx *dev); @@ -686,6 +703,9 @@ void em28xx_deregister_snapshot_button(struct em28xx *dev); int em28xx_ir_init(struct em28xx *dev); int em28xx_ir_fini(struct em28xx *dev); +/* Provided by em28xx-vbi.c */ +extern struct videobuf_queue_ops em28xx_vbi_qops; + /* printk macros */ #define em28xx_err(fmt, arg...) do {\ diff --git a/drivers/media/video/et61x251/et61x251_core.c b/drivers/media/video/et61x251/et61x251_core.c index d1c1e457f0b9..74092f436be6 100644 --- a/drivers/media/video/et61x251/et61x251_core.c +++ b/drivers/media/video/et61x251/et61x251_core.c @@ -1379,8 +1379,10 @@ et61x251_read(struct file* filp, char __user * buf, (!list_empty(&cam->outqueue)) || (cam->state & DEV_DISCONNECTED) || (cam->state & DEV_MISCONFIGURED), - cam->module_param.frame_timeout * - 1000 * msecs_to_jiffies(1) ); + msecs_to_jiffies( + cam->module_param.frame_timeout * 1000 + ) + ); if (timeout < 0) { mutex_unlock(&cam->fileop_mutex); return timeout; diff --git a/drivers/media/video/gspca/Kconfig b/drivers/media/video/gspca/Kconfig index 8897283b0bb4..fe2e490ebc52 100644 --- a/drivers/media/video/gspca/Kconfig +++ b/drivers/media/video/gspca/Kconfig @@ -19,6 +19,7 @@ if USB_GSPCA && VIDEO_V4L2 source "drivers/media/video/gspca/m5602/Kconfig" source "drivers/media/video/gspca/stv06xx/Kconfig" +source "drivers/media/video/gspca/gl860/Kconfig" config USB_GSPCA_CONEX tristate "Conexant Camera Driver" diff --git a/drivers/media/video/gspca/Makefile b/drivers/media/video/gspca/Makefile index 035616b5e867..b7420818037e 100644 --- a/drivers/media/video/gspca/Makefile +++ b/drivers/media/video/gspca/Makefile @@ -58,3 +58,4 @@ gspca_zc3xx-objs := zc3xx.o obj-$(CONFIG_USB_M5602) += m5602/ obj-$(CONFIG_USB_STV06XX) += stv06xx/ +obj-$(CONFIG_USB_GL860) += gl860/ diff --git a/drivers/media/video/gspca/gl860/Kconfig b/drivers/media/video/gspca/gl860/Kconfig new file mode 100644 index 000000000000..22772f53ec7b --- /dev/null +++ b/drivers/media/video/gspca/gl860/Kconfig @@ -0,0 +1,8 @@ +config USB_GL860 + tristate "GL860 USB Camera Driver" + depends on VIDEO_V4L2 && USB_GSPCA + help + Say Y here if you want support for cameras based on the GL860 chip. + + To compile this driver as a module, choose M here: the + module will be called gspca_gl860. diff --git a/drivers/media/video/gspca/gl860/Makefile b/drivers/media/video/gspca/gl860/Makefile new file mode 100644 index 000000000000..13c9403cc87d --- /dev/null +++ b/drivers/media/video/gspca/gl860/Makefile @@ -0,0 +1,10 @@ +obj-$(CONFIG_USB_GL860) += gspca_gl860.o + +gspca_gl860-objs := gl860.o \ + gl860-mi1320.o \ + gl860-ov2640.o \ + gl860-ov9655.o \ + gl860-mi2020.o + +EXTRA_CFLAGS += -Idrivers/media/video/gspca + diff --git a/drivers/media/video/gspca/gl860/gl860-mi1320.c b/drivers/media/video/gspca/gl860/gl860-mi1320.c new file mode 100644 index 000000000000..39f6261c1a0c --- /dev/null +++ b/drivers/media/video/gspca/gl860/gl860-mi1320.c @@ -0,0 +1,537 @@ +/* @file gl860-mi1320.c + * @author Olivier LORIN from my logs + * @date 2009-08-27 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Sensor : MI1320 */ + +#include "gl860.h" + +static struct validx tbl_common[] = { + {0xba00, 0x00f0}, {0xba00, 0x00f1}, {0xba51, 0x0066}, {0xba02, 0x00f1}, + {0xba05, 0x0067}, {0xba05, 0x00f1}, {0xbaa0, 0x0065}, {0xba00, 0x00f1}, + {0xffff, 0xffff}, + {0xba00, 0x00f0}, {0xba02, 0x00f1}, {0xbafa, 0x0028}, {0xba02, 0x00f1}, + {0xba00, 0x00f0}, {0xba01, 0x00f1}, {0xbaf0, 0x0006}, {0xba0e, 0x00f1}, + {0xba70, 0x0006}, {0xba0e, 0x00f1}, + {0xffff, 0xffff}, + {0xba74, 0x0006}, {0xba0e, 0x00f1}, + {0xffff, 0xffff}, + {0x0061, 0x0000}, {0x0068, 0x000d}, +}; + +static struct validx tbl_init_at_startup[] = { + {0x0000, 0x0000}, {0x0010, 0x0010}, + {35, 0xffff}, + {0x0008, 0x00c0}, {0x0001, 0x00c1}, {0x0001, 0x00c2}, {0x0020, 0x0006}, + {0x006a, 0x000d}, +}; + +static struct validx tbl_sensor_settings_common[] = { + {0x0010, 0x0010}, {0x0003, 0x00c1}, {0x0042, 0x00c2}, {0x0040, 0x0000}, + {0x006a, 0x0007}, {0x006a, 0x000d}, {0x0063, 0x0006}, +}; +static struct validx tbl_sensor_settings_1280[] = { + {0xba00, 0x00f0}, {0xba00, 0x00f1}, {0xba5a, 0x0066}, {0xba02, 0x00f1}, + {0xba05, 0x0067}, {0xba05, 0x00f1}, {0xba20, 0x0065}, {0xba00, 0x00f1}, +}; +static struct validx tbl_sensor_settings_800[] = { + {0xba00, 0x00f0}, {0xba00, 0x00f1}, {0xba5a, 0x0066}, {0xba02, 0x00f1}, + {0xba05, 0x0067}, {0xba05, 0x00f1}, {0xba20, 0x0065}, {0xba00, 0x00f1}, +}; +static struct validx tbl_sensor_settings_640[] = { + {0xba00, 0x00f0}, {0xba00, 0x00f1}, {0xbaa0, 0x0065}, {0xba00, 0x00f1}, + {0xba51, 0x0066}, {0xba02, 0x00f1}, {0xba05, 0x0067}, {0xba05, 0x00f1}, + {0xba20, 0x0065}, {0xba00, 0x00f1}, +}; +static struct validx tbl_post_unset_alt[] = { + {0xba00, 0x00f0}, {0xba00, 0x00f1}, {0xbaa0, 0x0065}, {0xba00, 0x00f1}, + {0x0061, 0x0000}, {0x0068, 0x000d}, +}; + +static u8 *tbl_1280[] = { + "\x0d\x80\xf1\x08\x03\x04\xf1\x00" "\x04\x05\xf1\x02\x05\x00\xf1\xf1" + "\x06\x00\xf1\x0d\x20\x01\xf1\x00" "\x21\x84\xf1\x00\x0d\x00\xf1\x08" + "\xf0\x00\xf1\x01\x34\x00\xf1\x00" "\x9b\x43\xf1\x00\xa6\x05\xf1\x00" + "\xa9\x04\xf1\x00\xa1\x05\xf1\x00" "\xa4\x04\xf1\x00\xae\x0a\xf1\x08" + , + "\xf0\x00\xf1\x02\x3a\x05\xf1\xf1" "\x3c\x05\xf1\xf1\x59\x01\xf1\x47" + "\x5a\x01\xf1\x88\x5c\x0a\xf1\x06" "\x5d\x0e\xf1\x0a\x64\x5e\xf1\x1c" + "\xd2\x00\xf1\xcf\xcb\x00\xf1\x01" + , + "\xd3\x02\xd4\x28\xd5\x01\xd0\x02" "\xd1\x18\xd2\xc1" +}; + +static u8 *tbl_800[] = { + "\x0d\x80\xf1\x08\x03\x03\xf1\xc0" "\x04\x05\xf1\x02\x05\x00\xf1\xf1" + "\x06\x00\xf1\x0d\x20\x01\xf1\x00" "\x21\x84\xf1\x00\x0d\x00\xf1\x08" + "\xf0\x00\xf1\x01\x34\x00\xf1\x00" "\x9b\x43\xf1\x00\xa6\x05\xf1\x00" + "\xa9\x03\xf1\xc0\xa1\x03\xf1\x20" "\xa4\x02\xf1\x5a\xae\x0a\xf1\x08" + , + "\xf0\x00\xf1\x02\x3a\x05\xf1\xf1" "\x3c\x05\xf1\xf1\x59\x01\xf1\x47" + "\x5a\x01\xf1\x88\x5c\x0a\xf1\x06" "\x5d\x0e\xf1\x0a\x64\x5e\xf1\x1c" + "\xd2\x00\xf1\xcf\xcb\x00\xf1\x01" + , + "\xd3\x02\xd4\x18\xd5\x21\xd0\x02" "\xd1\x10\xd2\x59" +}; + +static u8 *tbl_640[] = { + "\x0d\x80\xf1\x08\x03\x04\xf1\x04" "\x04\x05\xf1\x02\x07\x01\xf1\x7c" + "\x08\x00\xf1\x0e\x21\x80\xf1\x00" "\x0d\x00\xf1\x08\xf0\x00\xf1\x01" + "\x34\x10\xf1\x10\x3a\x43\xf1\x00" "\xa6\x05\xf1\x02\xa9\x04\xf1\x04" + "\xa7\x02\xf1\x81\xaa\x01\xf1\xe2" "\xae\x0c\xf1\x09" + , + "\xf0\x00\xf1\x02\x39\x03\xf1\xfc" "\x3b\x04\xf1\x04\x57\x01\xf1\xb6" + "\x58\x02\xf1\x0d\x5c\x1f\xf1\x19" "\x5d\x24\xf1\x1e\x64\x5e\xf1\x1c" + "\xd2\x00\xf1\x00\xcb\x00\xf1\x01" + , + "\xd3\x02\xd4\x10\xd5\x81\xd0\x02" "\xd1\x08\xd2\xe1" +}; + +static s32 tbl_sat[] = {0x25, 0x1d, 0x15, 0x0d, 0x05, 0x4d, 0x55, 0x5d, 0x2d}; +static s32 tbl_bright[] = {0, 8, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70}; +static s32 tbl_backlight[] = {0x0e, 0x06, 0x02}; + +static s32 tbl_cntr1[] = { + 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, 0xe0, 0xf0}; +static s32 tbl_cntr2[] = { + 0x70, 0x68, 0x60, 0x58, 0x50, 0x48, 0x40, 0x38, 0x30, 0x20, 0x10}; + +static u8 dat_wbalNL[] = + "\xf0\x00\xf1\x01\x05\x00\xf1\x06" "\x3b\x04\xf1\x2a\x47\x10\xf1\x10" + "\x9d\x3c\xf1\xae\xaf\x10\xf1\x00" "\xf0\x00\xf1\x02\x2f\x91\xf1\x20" + "\x9c\x91\xf1\x20\x37\x03\xf1\x00" "\x9d\xc5\xf1\x0f\xf0\x00\xf1\x00"; + +static u8 dat_wbalLL[] = + "\xf0\x00\xf1\x01\x05\x00\xf1\x0c" "\x3b\x04\xf1\x2a\x47\x40\xf1\x40" + "\x9d\x20\xf1\xae\xaf\x10\xf1\x00" "\xf0\x00\xf1\x02\x2f\xd1\xf1\x00" + "\x9c\xd1\xf1\x00\x37\x03\xf1\x00" "\x9d\xc5\xf1\x3f\xf0\x00\xf1\x00"; + +static u8 dat_wbalBL[] = + "\xf0\x00\xf1\x01\x05\x00\xf1\x06" "\x47\x10\xf1\x30\x9d\x3c\xf1\xae" + "\xaf\x10\xf1\x00\xf0\x00\xf1\x02" "\x2f\x91\xf1\x20\x9c\x91\xf1\x20" + "\x37\x03\xf1\x00\x9d\xc5\xf1\x2f" "\xf0\x00\xf1\x00"; + +static u8 dat_hvflip1[] = {0xf0, 0x00, 0xf1, 0x00}; + +static u8 s000[] = + "\x00\x01\x07\x6a\x06\x63\x0d\x6a" "\xc0\x00\x10\x10\xc1\x03\xc2\x42" + "\xd8\x04\x58\x00\x04\x02"; +static u8 s001[] = + "\x0d\x00\xf1\x0b\x0d\x00\xf1\x08" "\x35\x00\xf1\x22\x68\x00\xf1\x5d" + "\xf0\x00\xf1\x01\x06\x70\xf1\x0e" "\xf0\x00\xf1\x02\xdd\x18\xf1\xe0"; +static u8 s002[] = + "\x05\x01\xf1\x84\x06\x00\xf1\x44" "\x07\x00\xf1\xbe\x08\x00\xf1\x1e" + "\x20\x01\xf1\x03\x21\x84\xf1\x00" "\x22\x0d\xf1\x0f\x24\x80\xf1\x00" + "\x34\x18\xf1\x2d\x35\x00\xf1\x22" "\x43\x83\xf1\x83\x59\x00\xf1\xff"; +static u8 s003[] = + "\xf0\x00\xf1\x02\x39\x06\xf1\x8c" "\x3a\x06\xf1\x8c\x3b\x03\xf1\xda" + "\x3c\x05\xf1\x30\x57\x01\xf1\x0c" "\x58\x01\xf1\x42\x59\x01\xf1\x0c" + "\x5a\x01\xf1\x42\x5c\x13\xf1\x0e" "\x5d\x17\xf1\x12\x64\x1e\xf1\x1c"; +static u8 s004[] = + "\xf0\x00\xf1\x02\x24\x5f\xf1\x20" "\x28\xea\xf1\x02\x5f\x41\xf1\x43"; +static u8 s005[] = + "\x02\x00\xf1\xee\x03\x29\xf1\x1a" "\x04\x02\xf1\xa4\x09\x00\xf1\x68" + "\x0a\x00\xf1\x2a\x0b\x00\xf1\x04" "\x0c\x00\xf1\x93\x0d\x00\xf1\x82" + "\x0e\x00\xf1\x40\x0f\x00\xf1\x5f" "\x10\x00\xf1\x4e\x11\x00\xf1\x5b"; +static u8 s006[] = + "\x15\x00\xf1\xc9\x16\x00\xf1\x5e" "\x17\x00\xf1\x9d\x18\x00\xf1\x06" + "\x19\x00\xf1\x89\x1a\x00\xf1\x12" "\x1b\x00\xf1\xa1\x1c\x00\xf1\xe4" + "\x1d\x00\xf1\x7a\x1e\x00\xf1\x64" "\xf6\x00\xf1\x5f"; +static u8 s007[] = + "\xf0\x00\xf1\x01\x53\x09\xf1\x03" "\x54\x3d\xf1\x1c\x55\x99\xf1\x72" + "\x56\xc1\xf1\xb1\x57\xd8\xf1\xce" "\x58\xe0\xf1\x00\xdc\x0a\xf1\x03" + "\xdd\x45\xf1\x20\xde\xae\xf1\x82" "\xdf\xdc\xf1\xc9\xe0\xf6\xf1\xea" + "\xe1\xff\xf1\x00"; +static u8 s008[] = + "\xf0\x00\xf1\x01\x80\x00\xf1\x06" "\x81\xf6\xf1\x08\x82\xfb\xf1\xf7" + "\x83\x00\xf1\xfe\xb6\x07\xf1\x03" "\xb7\x18\xf1\x0c\x84\xfb\xf1\x06" + "\x85\xfb\xf1\xf9\x86\x00\xf1\xff" "\xb8\x07\xf1\x04\xb9\x16\xf1\x0a"; +static u8 s009[] = + "\x87\xfa\xf1\x05\x88\xfc\xf1\xf9" "\x89\x00\xf1\xff\xba\x06\xf1\x03" + "\xbb\x17\xf1\x09\x8a\xe8\xf1\x14" "\x8b\xf7\xf1\xf0\x8c\xfd\xf1\xfa" + "\x8d\x00\xf1\x00\xbc\x05\xf1\x01" "\xbd\x0c\xf1\x08\xbe\x00\xf1\x14"; +static u8 s010[] = + "\x8e\xea\xf1\x13\x8f\xf7\xf1\xf2" "\x90\xfd\xf1\xfa\x91\x00\xf1\x00" + "\xbf\x05\xf1\x01\xc0\x0a\xf1\x08" "\xc1\x00\xf1\x0c\x92\xed\xf1\x0f" + "\x93\xf9\xf1\xf4\x94\xfe\xf1\xfb" "\x95\x00\xf1\x00\xc2\x04\xf1\x01" + "\xc3\x0a\xf1\x07\xc4\x00\xf1\x10"; +static u8 s011[] = + "\xf0\x00\xf1\x01\x05\x00\xf1\x06" "\x25\x00\xf1\x55\x34\x10\xf1\x10" + "\x35\xf0\xf1\x10\x3a\x02\xf1\x03" "\x3b\x04\xf1\x2a\x9b\x43\xf1\x00" + "\xa4\x03\xf1\xc0\xa7\x02\xf1\x81"; + +static int mi1320_init_at_startup(struct gspca_dev *gspca_dev); +static int mi1320_configure_alt(struct gspca_dev *gspca_dev); +static int mi1320_init_pre_alt(struct gspca_dev *gspca_dev); +static int mi1320_init_post_alt(struct gspca_dev *gspca_dev); +static void mi1320_post_unset_alt(struct gspca_dev *gspca_dev); +static int mi1320_sensor_settings(struct gspca_dev *gspca_dev); +static int mi1320_camera_settings(struct gspca_dev *gspca_dev); +/*==========================================================================*/ + +void mi1320_init_settings(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + sd->vcur.backlight = 0; + sd->vcur.brightness = 0; + sd->vcur.sharpness = 6; + sd->vcur.contrast = 10; + sd->vcur.gamma = 20; + sd->vcur.hue = 0; + sd->vcur.saturation = 6; + sd->vcur.whitebal = 0; + sd->vcur.mirror = 0; + sd->vcur.flip = 0; + sd->vcur.AC50Hz = 1; + + sd->vmax.backlight = 2; + sd->vmax.brightness = 8; + sd->vmax.sharpness = 7; + sd->vmax.contrast = 0; /* 10 but not working with tihs driver */ + sd->vmax.gamma = 40; + sd->vmax.hue = 5 + 1; + sd->vmax.saturation = 8; + sd->vmax.whitebal = 2; + sd->vmax.mirror = 1; + sd->vmax.flip = 1; + sd->vmax.AC50Hz = 1; + + sd->dev_camera_settings = mi1320_camera_settings; + sd->dev_init_at_startup = mi1320_init_at_startup; + sd->dev_configure_alt = mi1320_configure_alt; + sd->dev_init_pre_alt = mi1320_init_pre_alt; + sd->dev_post_unset_alt = mi1320_post_unset_alt; +} + +/*==========================================================================*/ + +static void common(struct gspca_dev *gspca_dev) +{ + s32 n; /* reserved for FETCH macros */ + + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, 22, s000); + ctrl_out(gspca_dev, 0x40, 1, 0x0041, 0x0000, 0, NULL); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 32, s001); + n = fetch_validx(gspca_dev, tbl_common, ARRAY_SIZE(tbl_common)); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 48, s002); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 48, s003); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 16, s004); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 48, s005); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 44, s006); + keep_on_fetching_validx(gspca_dev, tbl_common, + ARRAY_SIZE(tbl_common), n); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 52, s007); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 48, s008); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 48, s009); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 56, s010); + keep_on_fetching_validx(gspca_dev, tbl_common, + ARRAY_SIZE(tbl_common), n); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 40, s011); + keep_on_fetching_validx(gspca_dev, tbl_common, + ARRAY_SIZE(tbl_common), n); +} + +static int mi1320_init_at_startup(struct gspca_dev *gspca_dev) +{ + fetch_validx(gspca_dev, tbl_init_at_startup, + ARRAY_SIZE(tbl_init_at_startup)); + + common(gspca_dev); + +/* ctrl_out(gspca_dev, 0x40, 11, 0x0000, 0x0000, 0, NULL); */ + + return 0; +} + +static int mi1320_init_pre_alt(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + sd->mirrorMask = 0; + + sd->vold.backlight = -1; + sd->vold.brightness = -1; + sd->vold.sharpness = -1; + sd->vold.contrast = -1; + sd->vold.saturation = -1; + sd->vold.gamma = -1; + sd->vold.hue = -1; + sd->vold.whitebal = -1; + sd->vold.mirror = -1; + sd->vold.flip = -1; + sd->vold.AC50Hz = -1; + + common(gspca_dev); + + mi1320_sensor_settings(gspca_dev); + + mi1320_init_post_alt(gspca_dev); + + return 0; +} + +static int mi1320_init_post_alt(struct gspca_dev *gspca_dev) +{ + mi1320_camera_settings(gspca_dev); + + return 0; +} + +static int mi1320_sensor_settings(struct gspca_dev *gspca_dev) +{ + s32 reso = gspca_dev->cam.cam_mode[(s32) gspca_dev->curr_mode].priv; + + ctrl_out(gspca_dev, 0x40, 5, 0x0001, 0x0000, 0, NULL); + + fetch_validx(gspca_dev, tbl_sensor_settings_common, + ARRAY_SIZE(tbl_sensor_settings_common)); + + switch (reso) { + case IMAGE_1280: + fetch_validx(gspca_dev, tbl_sensor_settings_1280, + ARRAY_SIZE(tbl_sensor_settings_1280)); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 64, tbl_1280[0]); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 40, tbl_1280[1]); + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, 12, tbl_1280[2]); + break; + + case IMAGE_800: + fetch_validx(gspca_dev, tbl_sensor_settings_800, + ARRAY_SIZE(tbl_sensor_settings_800)); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 64, tbl_800[0]); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 40, tbl_800[1]); + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, 12, tbl_800[2]); + break; + + default: + fetch_validx(gspca_dev, tbl_sensor_settings_640, + ARRAY_SIZE(tbl_sensor_settings_640)); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 60, tbl_640[0]); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 40, tbl_640[1]); + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, 12, tbl_640[2]); + break; + } + return 0; +} + +static int mi1320_configure_alt(struct gspca_dev *gspca_dev) +{ + s32 reso = gspca_dev->cam.cam_mode[(s32) gspca_dev->curr_mode].priv; + + switch (reso) { + case IMAGE_640: + gspca_dev->alt = 3 + 1; + break; + + case IMAGE_800: + case IMAGE_1280: + gspca_dev->alt = 1 + 1; + break; + } + return 0; +} + +int mi1320_camera_settings(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + s32 backlight = sd->vcur.backlight; + s32 bright = sd->vcur.brightness; + s32 sharp = sd->vcur.sharpness; + s32 cntr = sd->vcur.contrast; + s32 gam = sd->vcur.gamma; + s32 hue = sd->vcur.hue; + s32 sat = sd->vcur.saturation; + s32 wbal = sd->vcur.whitebal; + s32 mirror = (((sd->vcur.mirror > 0) ^ sd->mirrorMask) > 0); + s32 flip = (((sd->vcur.flip > 0) ^ sd->mirrorMask) > 0); + s32 freq = (sd->vcur.AC50Hz > 0); + s32 i; + + if (freq != sd->vold.AC50Hz) { + sd->vold.AC50Hz = freq; + + freq = 2 * (freq == 0); + ctrl_out(gspca_dev, 0x40, 1, 0xba00, 0x00f0, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba02, 0x00f1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba00 , 0x005b, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba01 + freq, 0x00f1, 0, NULL); + } + + if (wbal != sd->vold.whitebal) { + sd->vold.whitebal = wbal; + if (wbal < 0 || wbal > sd->vmax.whitebal) + wbal = 0; + + for (i = 0; i < 2; i++) { + if (wbal == 0) { /* Normal light */ + ctrl_out(gspca_dev, 0x40, 1, + 0x0010, 0x0010, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, + 0x0003, 0x00c1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, + 0x0042, 0x00c2, 0, NULL); + ctrl_out(gspca_dev, 0x40, 3, + 0xba00, 0x0200, 48, dat_wbalNL); + } + + if (wbal == 1) { /* Low light */ + ctrl_out(gspca_dev, 0x40, 1, + 0x0010, 0x0010, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, + 0x0004, 0x00c1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, + 0x0043, 0x00c2, 0, NULL); + ctrl_out(gspca_dev, 0x40, 3, + 0xba00, 0x0200, 48, dat_wbalLL); + } + + if (wbal == 2) { /* Back light */ + ctrl_out(gspca_dev, 0x40, 1, + 0x0010, 0x0010, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, + 0x0003, 0x00c1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, + 0x0042, 0x00c2, 0, NULL); + ctrl_out(gspca_dev, 0x40, 3, + 0xba00, 0x0200, 44, dat_wbalBL); + } + } + } + + if (bright != sd->vold.brightness) { + sd->vold.brightness = bright; + if (bright < 0 || bright > sd->vmax.brightness) + bright = 0; + + bright = tbl_bright[bright]; + ctrl_out(gspca_dev, 0x40, 1, 0xba00, 0x00f0, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba01, 0x00f1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba00 + bright, 0x0034, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba00 + bright, 0x00f1, 0, NULL); + } + + if (sat != sd->vold.saturation) { + sd->vold.saturation = sat; + if (sat < 0 || sat > sd->vmax.saturation) + sat = 0; + + sat = tbl_sat[sat]; + ctrl_out(gspca_dev, 0x40, 1, 0xba00, 0x00f0, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba01, 0x00f1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba00 , 0x0025, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba00 + sat, 0x00f1, 0, NULL); + } + + if (sharp != sd->vold.sharpness) { + sd->vold.sharpness = sharp; + if (sharp < 0 || sharp > sd->vmax.sharpness) + sharp = 0; + + ctrl_out(gspca_dev, 0x40, 1, 0xba00, 0x00f0, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba01, 0x00f1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba00 , 0x0005, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba00 + sharp, 0x00f1, 0, NULL); + } + + if (hue != sd->vold.hue) { + /* 0=normal 1=NB 2="sepia" 3=negative 4=other 5=other2 */ + if (hue < 0 || hue > sd->vmax.hue) + hue = 0; + if (hue == sd->vmax.hue) + sd->swapRB = 1; + else + sd->swapRB = 0; + + ctrl_out(gspca_dev, 0x40, 1, 0xba00, 0x00f0, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba01, 0x00f1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba70, 0x00e2, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba00 + hue * (hue < 6), 0x00f1, + 0, NULL); + } + + if (backlight != sd->vold.backlight) { + sd->vold.backlight = backlight; + if (backlight < 0 || backlight > sd->vmax.backlight) + backlight = 0; + + backlight = tbl_backlight[backlight]; + for (i = 0; i < 2; i++) { + ctrl_out(gspca_dev, 0x40, 1, 0xba00, 0x00f0, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba01, 0x00f1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba74, 0x0006, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba80 + backlight, 0x00f1, + 0, NULL); + } + } + + if (hue != sd->vold.hue) { + sd->vold.hue = hue; + + ctrl_out(gspca_dev, 0x40, 1, 0xba00, 0x00f0, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba01, 0x00f1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba70, 0x00e2, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba00 + hue * (hue < 6), 0x00f1, + 0, NULL); + } + + if (mirror != sd->vold.mirror || flip != sd->vold.flip) { + u8 dat_hvflip2[4] = {0x20, 0x01, 0xf1, 0x00}; + sd->vold.mirror = mirror; + sd->vold.flip = flip; + + dat_hvflip2[3] = flip + 2 * mirror; + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 4, dat_hvflip1); + ctrl_out(gspca_dev, 0x40, 3, 0xba00, 0x0200, 4, dat_hvflip2); + } + + if (gam != sd->vold.gamma) { + sd->vold.gamma = gam; + if (gam < 0 || gam > sd->vmax.gamma) + gam = 0; + + gam = 2 * gam; + ctrl_out(gspca_dev, 0x40, 1, 0xba00, 0x00f0, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba01, 0x00f1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba04 , 0x003b, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba02 + gam, 0x00f1, 0, NULL); + } + + if (cntr != sd->vold.contrast) { + sd->vold.contrast = cntr; + if (cntr < 0 || cntr > sd->vmax.contrast) + cntr = 0; + + ctrl_out(gspca_dev, 0x40, 1, 0xba00, 0x00f0, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba01, 0x00f1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba00 + tbl_cntr1[cntr], 0x0035, + 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0xba00 + tbl_cntr2[cntr], 0x00f1, + 0, NULL); + } + + return 0; +} + +static void mi1320_post_unset_alt(struct gspca_dev *gspca_dev) +{ + ctrl_out(gspca_dev, 0x40, 5, 0x0000, 0x0000, 0, NULL); + + fetch_validx(gspca_dev, tbl_post_unset_alt, + ARRAY_SIZE(tbl_post_unset_alt)); +} diff --git a/drivers/media/video/gspca/gl860/gl860-mi2020.c b/drivers/media/video/gspca/gl860/gl860-mi2020.c new file mode 100644 index 000000000000..ffb09fed3e8c --- /dev/null +++ b/drivers/media/video/gspca/gl860/gl860-mi2020.c @@ -0,0 +1,937 @@ +/* @file gl860-mi2020.c + * @author Olivier LORIN, from Ice/Soro2005's logs(A), Fret_saw/Hulkie's + * logs(B) and Tricid"s logs(C). With the help of Kytrix/BUGabundo/Blazercist. + * @date 2009-08-27 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Sensor : MI2020 */ + +#include "gl860.h" + +static u8 dat_bright1[] = {0x8c, 0xa2, 0x06}; +static u8 dat_bright3[] = {0x8c, 0xa1, 0x02}; +static u8 dat_bright4[] = {0x90, 0x00, 0x0f}; +static u8 dat_bright5[] = {0x8c, 0xa1, 0x03}; +static u8 dat_bright6[] = {0x90, 0x00, 0x05}; + +static u8 dat_dummy1[] = {0x90, 0x00, 0x06}; +/*static u8 dummy2[] = {0x8c, 0xa1, 0x02};*/ +/*static u8 dummy3[] = {0x90, 0x00, 0x1f};*/ + +static u8 dat_hvflip1[] = {0x8c, 0x27, 0x19}; +static u8 dat_hvflip3[] = {0x8c, 0x27, 0x3b}; +static u8 dat_hvflip5[] = {0x8c, 0xa1, 0x03}; +static u8 dat_hvflip6[] = {0x90, 0x00, 0x06}; + +static u8 dat_freq1[] = { 0x8c, 0xa4, 0x04 }; + +static u8 dat_multi5[] = { 0x8c, 0xa1, 0x03 }; +static u8 dat_multi6[] = { 0x90, 0x00, 0x05 }; + +static struct validx tbl_common_a[] = { + {0x0000, 0x0000}, + {1, 0xffff}, /* msleep(35); */ + {0x006a, 0x0007}, {0x0063, 0x0006}, {0x006a, 0x000d}, {0x0000, 0x00c0}, + {0x0010, 0x0010}, {0x0003, 0x00c1}, {0x0042, 0x00c2}, {0x0004, 0x00d8}, + {0x0000, 0x0058}, {0x0002, 0x0004}, {0x0041, 0x0000}, +}; + +static struct validx tbl_common_b[] = { + {0x006a, 0x0007}, + {35, 0xffff}, + {0x00ef, 0x0006}, + {35, 0xffff}, + {0x006a, 0x000d}, + {35, 0xffff}, + {0x0000, 0x00c0}, {0x0010, 0x0010}, {0x0003, 0x00c1}, {0x0042, 0x00c2}, + {0x0004, 0x00d8}, {0x0000, 0x0058}, {0x0041, 0x0000}, +}; + +static struct idxdata tbl_common_c[] = { + {0x32, "\x02\x00\x08"}, {0x33, "\xf4\x03\x1d"}, + {6, "\xff\xff\xff"}, /* 12 */ + {0x34, "\x1e\x8f\x09"}, {0x34, "\x1c\x01\x28"}, {0x34, "\x1e\x8f\x09"}, + {2, "\xff\xff\xff"}, /* - */ + {0x34, "\x1e\x8f\x09"}, {0x32, "\x14\x06\xe6"}, {0x33, "\x8c\x22\x23"}, + {0x33, "\x90\x00\x00"}, {0x33, "\x8c\xa2\x0f"}, {0x33, "\x90\x00\x0d"}, + {0x33, "\x8c\xa2\x10"}, {0x33, "\x90\x00\x0b"}, {0x33, "\x8c\xa2\x11"}, + {0x33, "\x90\x00\x07"}, {0x33, "\xf4\x03\x1d"}, {0x35, "\xa2\x00\xe2"}, + {0x33, "\x8c\xab\x05"}, {0x33, "\x90\x00\x01"}, {0x32, "\x6e\x00\x86"}, + {0x32, "\x70\x0f\xaa"}, {0x32, "\x72\x0f\xe4"}, {0x33, "\x8c\xa3\x4a"}, + {0x33, "\x90\x00\x5a"}, {0x33, "\x8c\xa3\x4b"}, {0x33, "\x90\x00\xa6"}, + {0x33, "\x8c\xa3\x61"}, {0x33, "\x90\x00\xc8"}, {0x33, "\x8c\xa3\x62"}, + {0x33, "\x90\x00\xe1"}, {0x34, "\xce\x01\xa8"}, {0x34, "\xd0\x66\x33"}, + {0x34, "\xd2\x31\x9a"}, {0x34, "\xd4\x94\x63"}, {0x34, "\xd6\x4b\x25"}, + {0x34, "\xd8\x26\x70"}, {0x34, "\xda\x72\x4c"}, {0x34, "\xdc\xff\x04"}, + {0x34, "\xde\x01\x5b"}, {0x34, "\xe6\x01\x13"}, {0x34, "\xee\x0b\xf0"}, + {0x34, "\xf6\x0b\xa4"}, {0x35, "\x00\xf6\xe7"}, {0x35, "\x08\x0d\xfd"}, + {0x35, "\x10\x25\x63"}, {0x35, "\x18\x35\x6c"}, {0x35, "\x20\x42\x7e"}, + {0x35, "\x28\x19\x44"}, {0x35, "\x30\x39\xd4"}, {0x35, "\x38\xf5\xa8"}, + {0x35, "\x4c\x07\x90"}, {0x35, "\x44\x07\xb8"}, {0x35, "\x5c\x06\x88"}, + {0x35, "\x54\x07\xff"}, {0x34, "\xe0\x01\x52"}, {0x34, "\xe8\x00\xcc"}, + {0x34, "\xf0\x0d\x83"}, {0x34, "\xf8\x0c\xb3"}, {0x35, "\x02\xfe\xba"}, + {0x35, "\x0a\x04\xe0"}, {0x35, "\x12\x1c\x63"}, {0x35, "\x1a\x2b\x5a"}, + {0x35, "\x22\x32\x5e"}, {0x35, "\x2a\x0d\x28"}, {0x35, "\x32\x2c\x02"}, + {0x35, "\x3a\xf4\xfa"}, {0x35, "\x4e\x07\xef"}, {0x35, "\x46\x07\x88"}, + {0x35, "\x5e\x07\xc1"}, {0x35, "\x56\x04\x64"}, {0x34, "\xe4\x01\x15"}, + {0x34, "\xec\x00\x82"}, {0x34, "\xf4\x0c\xce"}, {0x34, "\xfc\x0c\xba"}, + {0x35, "\x06\x1f\x02"}, {0x35, "\x0e\x02\xe3"}, {0x35, "\x16\x1a\x50"}, + {0x35, "\x1e\x24\x39"}, {0x35, "\x26\x23\x4c"}, {0x35, "\x2e\xf9\x1b"}, + {0x35, "\x36\x23\x19"}, {0x35, "\x3e\x12\x08"}, {0x35, "\x52\x07\x22"}, + {0x35, "\x4a\x03\xd3"}, {0x35, "\x62\x06\x54"}, {0x35, "\x5a\x04\x5d"}, + {0x34, "\xe2\x01\x04"}, {0x34, "\xea\x00\xa0"}, {0x34, "\xf2\x0c\xbc"}, + {0x34, "\xfa\x0c\x5b"}, {0x35, "\x04\x17\xf2"}, {0x35, "\x0c\x02\x08"}, + {0x35, "\x14\x28\x43"}, {0x35, "\x1c\x28\x62"}, {0x35, "\x24\x2b\x60"}, + {0x35, "\x2c\x07\x33"}, {0x35, "\x34\x1f\xb0"}, {0x35, "\x3c\xed\xcd"}, + {0x35, "\x50\x00\x06"}, {0x35, "\x48\x07\xff"}, {0x35, "\x60\x05\x89"}, + {0x35, "\x58\x07\xff"}, {0x35, "\x40\x00\xa0"}, {0x35, "\x42\x00\x00"}, + {0x32, "\x10\x01\xfc"}, {0x33, "\x8c\xa1\x18"}, {0x33, "\x90\x00\x3c"}, + {1, "\xff\xff\xff"}, + {0x33, "\x78\x00\x00"}, + {1, "\xff\xff\xff"}, + {0x35, "\xb8\x1f\x20"}, {0x33, "\x8c\xa2\x06"}, {0x33, "\x90\x00\x10"}, + {0x33, "\x8c\xa2\x07"}, {0x33, "\x90\x00\x08"}, {0x33, "\x8c\xa2\x42"}, + {0x33, "\x90\x00\x0b"}, {0x33, "\x8c\xa2\x4a"}, {0x33, "\x90\x00\x8c"}, + {0x35, "\xba\xfa\x08"}, {0x33, "\x8c\xa2\x02"}, {0x33, "\x90\x00\x22"}, + {0x33, "\x8c\xa2\x03"}, {0x33, "\x90\x00\xbb"}, +}; + +static struct idxdata tbl_common_d[] = { + {0x33, "\x8c\x22\x2e"}, {0x33, "\x90\x00\xa0"}, {0x33, "\x8c\xa4\x08"}, + {0x33, "\x90\x00\x1f"}, {0x33, "\x8c\xa4\x09"}, {0x33, "\x90\x00\x21"}, + {0x33, "\x8c\xa4\x0a"}, {0x33, "\x90\x00\x25"}, {0x33, "\x8c\xa4\x0b"}, + {0x33, "\x90\x00\x27"}, {0x33, "\x8c\x24\x11"}, {0x33, "\x90\x00\xa0"}, + {0x33, "\x8c\x24\x13"}, {0x33, "\x90\x00\xc0"}, {0x33, "\x8c\x24\x15"}, + {0x33, "\x90\x00\xa0"}, {0x33, "\x8c\x24\x17"}, {0x33, "\x90\x00\xc0"}, +}; + +static struct idxdata tbl_common_e[] = { + {0x33, "\x8c\xa4\x04"}, {0x33, "\x90\x00\x80"}, {0x33, "\x8c\xa7\x9d"}, + {0x33, "\x90\x00\x00"}, {0x33, "\x8c\xa7\x9e"}, {0x33, "\x90\x00\x00"}, + {0x33, "\x8c\xa2\x0c"}, {0x33, "\x90\x00\x17"}, {0x33, "\x8c\xa2\x15"}, + {0x33, "\x90\x00\x04"}, {0x33, "\x8c\xa2\x14"}, {0x33, "\x90\x00\x20"}, + {0x33, "\x8c\xa1\x03"}, {0x33, "\x90\x00\x00"}, {0x33, "\x8c\x27\x17"}, + /* msleep(53); */ + {0x33, "\x90\x21\x11"}, {0x33, "\x8c\x27\x1b"}, {0x33, "\x90\x02\x4f"}, + {0x33, "\x8c\x27\x25"}, {0x33, "\x90\x06\x0f"}, {0x33, "\x8c\x27\x39"}, + {0x33, "\x90\x21\x11"}, {0x33, "\x8c\x27\x3d"}, {0x33, "\x90\x01\x20"}, + {0x33, "\x8c\x27\x47"}, {0x33, "\x90\x09\x4c"}, {0x33, "\x8c\x27\x03"}, + {0x33, "\x90\x02\x84"}, {0x33, "\x8c\x27\x05"}, {0x33, "\x90\x01\xe2"}, + {0x33, "\x8c\x27\x07"}, {0x33, "\x90\x06\x40"}, {0x33, "\x8c\x27\x09"}, + {0x33, "\x90\x04\xb0"}, {0x33, "\x8c\x27\x0d"}, {0x33, "\x90\x00\x00"}, + {0x33, "\x8c\x27\x0f"}, {0x33, "\x90\x00\x00"}, {0x33, "\x8c\x27\x11"}, + {0x33, "\x90\x04\xbd"}, {0x33, "\x8c\x27\x13"}, {0x33, "\x90\x06\x4d"}, + {0x33, "\x8c\x27\x15"}, {0x33, "\x90\x00\x00"}, {0x33, "\x8c\x27\x17"}, + {0x33, "\x90\x21\x11"}, {0x33, "\x8c\x27\x19"}, {0x33, "\x90\x04\x6c"}, + {0x33, "\x8c\x27\x1b"}, {0x33, "\x90\x02\x4f"}, {0x33, "\x8c\x27\x1d"}, + {0x33, "\x90\x01\x02"}, {0x33, "\x8c\x27\x1f"}, {0x33, "\x90\x02\x79"}, + {0x33, "\x8c\x27\x21"}, {0x33, "\x90\x01\x55"}, {0x33, "\x8c\x27\x23"}, + {0x33, "\x90\x02\x85"}, {0x33, "\x8c\x27\x25"}, {0x33, "\x90\x06\x0f"}, + {0x33, "\x8c\x27\x27"}, {0x33, "\x90\x20\x20"}, {0x33, "\x8c\x27\x29"}, + {0x33, "\x90\x20\x20"}, {0x33, "\x8c\x27\x2b"}, {0x33, "\x90\x10\x20"}, + {0x33, "\x8c\x27\x2d"}, {0x33, "\x90\x20\x07"}, {0x33, "\x8c\x27\x2f"}, + {0x33, "\x90\x00\x04"}, {0x33, "\x8c\x27\x31"}, {0x33, "\x90\x00\x04"}, + {0x33, "\x8c\x27\x33"}, {0x33, "\x90\x04\xbb"}, {0x33, "\x8c\x27\x35"}, + {0x33, "\x90\x06\x4b"}, {0x33, "\x8c\x27\x37"}, {0x33, "\x90\x00\x00"}, + {0x33, "\x8c\x27\x39"}, {0x33, "\x90\x21\x11"}, {0x33, "\x8c\x27\x3b"}, + {0x33, "\x90\x00\x24"}, {0x33, "\x8c\x27\x3d"}, {0x33, "\x90\x01\x20"}, + {0x33, "\x8c\x27\x41"}, {0x33, "\x90\x01\x69"}, {0x33, "\x8c\x27\x45"}, + {0x33, "\x90\x04\xed"}, {0x33, "\x8c\x27\x47"}, {0x33, "\x90\x09\x4c"}, + {0x33, "\x8c\x27\x51"}, {0x33, "\x90\x00\x00"}, {0x33, "\x8c\x27\x53"}, + {0x33, "\x90\x03\x20"}, {0x33, "\x8c\x27\x55"}, {0x33, "\x90\x00\x00"}, + {0x33, "\x8c\x27\x57"}, {0x33, "\x90\x02\x58"}, {0x33, "\x8c\x27\x5f"}, + {0x33, "\x90\x00\x00"}, {0x33, "\x8c\x27\x61"}, {0x33, "\x90\x06\x40"}, + {0x33, "\x8c\x27\x63"}, {0x33, "\x90\x00\x00"}, {0x33, "\x8c\x27\x65"}, + {0x33, "\x90\x04\xb0"}, {0x33, "\x8c\x22\x2e"}, {0x33, "\x90\x00\xa1"}, + {0x33, "\x8c\xa4\x08"}, {0x33, "\x90\x00\x1f"}, {0x33, "\x8c\xa4\x09"}, + {0x33, "\x90\x00\x21"}, {0x33, "\x8c\xa4\x0a"}, {0x33, "\x90\x00\x25"}, + {0x33, "\x8c\xa4\x0b"}, {0x33, "\x90\x00\x27"}, {0x33, "\x8c\x24\x11"}, + {0x33, "\x90\x00\xa1"}, {0x33, "\x8c\x24\x13"}, {0x33, "\x90\x00\xc1"}, + {0x33, "\x8c\x24\x15"}, +}; + +static struct validx tbl_init_at_startup[] = { + {0x0000, 0x0000}, + {53, 0xffff}, + {0x0010, 0x0010}, + {53, 0xffff}, + {0x0008, 0x00c0}, + {53, 0xffff}, + {0x0001, 0x00c1}, + {53, 0xffff}, + {0x0001, 0x00c2}, + {53, 0xffff}, + {0x0020, 0x0006}, + {53, 0xffff}, + {0x006a, 0x000d}, + {53, 0xffff}, +}; + +static struct idxdata tbl_init_post_alt_low_a[] = { + {0x33, "\x8c\x27\x15"}, {0x33, "\x90\x00\x25"}, {0x33, "\x8c\x22\x2e"}, + {0x33, "\x90\x00\x81"}, {0x33, "\x8c\xa4\x08"}, {0x33, "\x90\x00\x17"}, + {0x33, "\x8c\xa4\x09"}, {0x33, "\x90\x00\x1a"}, {0x33, "\x8c\xa4\x0a"}, + {0x33, "\x90\x00\x1d"}, {0x33, "\x8c\xa4\x0b"}, {0x33, "\x90\x00\x20"}, + {0x33, "\x8c\x24\x11"}, {0x33, "\x90\x00\x81"}, {0x33, "\x8c\x24\x13"}, + {0x33, "\x90\x00\x9b"}, +}; + +static struct idxdata tbl_init_post_alt_low_b[] = { + {0x33, "\x8c\x27\x03"}, {0x33, "\x90\x03\x24"}, {0x33, "\x8c\x27\x05"}, + {0x33, "\x90\x02\x58"}, {0x33, "\x8c\xa1\x03"}, {0x33, "\x90\x00\x05"}, + {2, "\xff\xff\xff"}, + {0x33, "\x8c\xa1\x03"}, {0x33, "\x90\x00\x06"}, + {2, "\xff\xff\xff"}, +}; + +static struct idxdata tbl_init_post_alt_low_c[] = { + {0x34, "\x1e\x8f\x09"}, {0x34, "\x1c\x01\x28"}, {0x34, "\x1e\x8f\x09"}, + {2, "\xff\xff\xff"}, + {0x34, "\x1e\x8f\x09"}, {0x32, "\x14\x06\xe6"}, {0x33, "\x8c\xa1\x20"}, + {0x33, "\x90\x00\x00"}, {0x33, "\x8c\xa1\x03"}, {0x33, "\x90\x00\x01"}, + {0x33, "\x2e\x01\x00"}, {0x34, "\x04\x00\x2a"}, {0x33, "\x8c\xa7\x02"}, + {0x33, "\x90\x00\x00"}, {0x33, "\x8c\x27\x95"}, {0x33, "\x90\x01\x00"}, + {2, "\xff\xff\xff"}, + {0x33, "\x8c\xa1\x20"}, {0x33, "\x90\x00\x72"}, {0x33, "\x8c\xa1\x03"}, + {0x33, "\x90\x00\x02"}, {0x33, "\x8c\xa7\x02"}, {0x33, "\x90\x00\x01"}, + {2, "\xff\xff\xff"}, + {0x33, "\x8c\xa1\x20"}, {0x33, "\x90\x00\x00"}, {0x33, "\x8c\xa1\x03"}, + {0x33, "\x90\x00\x01"}, {0x33, "\x8c\xa7\x02"}, {0x33, "\x90\x00\x00"}, + {2, "\xff\xff\xff"}, /* - * */ + {0x33, "\x8c\xa1\x03"}, {0x33, "\x90\x00\x05"}, + {2, "\xff\xff\xff"}, + {0x33, "\x8c\xa1\x03"}, {0x33, "\x90\x00\x06"}, + {2, "\xff\xff\xff"}, + {0x33, "\x8c\xa1\x03"}, {0x33, "\x90\x00\x05"}, + {2, "\xff\xff\xff"}, + {0x33, "\x8c\xa1\x03"}, {0x33, "\x90\x00\x06"}, + {1, "\xff\xff\xff"}, +}; + +static struct idxdata tbl_init_post_alt_low_d[] = { + {0x32, "\x10\x01\xf8"}, {0x34, "\xce\x01\xa8"}, {0x34, "\xd0\x66\x33"}, + {0x34, "\xd2\x31\x9a"}, {0x34, "\xd4\x94\x63"}, {0x34, "\xd6\x4b\x25"}, + {0x34, "\xd8\x26\x70"}, {0x34, "\xda\x72\x4c"}, {0x34, "\xdc\xff\x04"}, + {0x34, "\xde\x01\x5b"}, {0x34, "\xe6\x01\x13"}, {0x34, "\xee\x0b\xf0"}, + {0x34, "\xf6\x0b\xa4"}, {0x35, "\x00\xf6\xe7"}, {0x35, "\x08\x0d\xfd"}, + {0x35, "\x10\x25\x63"}, {0x35, "\x18\x35\x6c"}, {0x35, "\x20\x42\x7e"}, + {0x35, "\x28\x19\x44"}, {0x35, "\x30\x39\xd4"}, {0x35, "\x38\xf5\xa8"}, + {0x35, "\x4c\x07\x90"}, {0x35, "\x44\x07\xb8"}, {0x35, "\x5c\x06\x88"}, + {0x35, "\x54\x07\xff"}, {0x34, "\xe0\x01\x52"}, {0x34, "\xe8\x00\xcc"}, + {0x34, "\xf0\x0d\x83"}, {0x34, "\xf8\x0c\xb3"}, {0x35, "\x02\xfe\xba"}, + {0x35, "\x0a\x04\xe0"}, {0x35, "\x12\x1c\x63"}, {0x35, "\x1a\x2b\x5a"}, + {0x35, "\x22\x32\x5e"}, {0x35, "\x2a\x0d\x28"}, {0x35, "\x32\x2c\x02"}, + {0x35, "\x3a\xf4\xfa"}, {0x35, "\x4e\x07\xef"}, {0x35, "\x46\x07\x88"}, + {0x35, "\x5e\x07\xc1"}, {0x35, "\x56\x04\x64"}, {0x34, "\xe4\x01\x15"}, + {0x34, "\xec\x00\x82"}, {0x34, "\xf4\x0c\xce"}, {0x34, "\xfc\x0c\xba"}, + {0x35, "\x06\x1f\x02"}, {0x35, "\x0e\x02\xe3"}, {0x35, "\x16\x1a\x50"}, + {0x35, "\x1e\x24\x39"}, {0x35, "\x26\x23\x4c"}, {0x35, "\x2e\xf9\x1b"}, + {0x35, "\x36\x23\x19"}, {0x35, "\x3e\x12\x08"}, {0x35, "\x52\x07\x22"}, + {0x35, "\x4a\x03\xd3"}, {0x35, "\x62\x06\x54"}, {0x35, "\x5a\x04\x5d"}, + {0x34, "\xe2\x01\x04"}, {0x34, "\xea\x00\xa0"}, {0x34, "\xf2\x0c\xbc"}, + {0x34, "\xfa\x0c\x5b"}, {0x35, "\x04\x17\xf2"}, {0x35, "\x0c\x02\x08"}, + {0x35, "\x14\x28\x43"}, {0x35, "\x1c\x28\x62"}, {0x35, "\x24\x2b\x60"}, + {0x35, "\x2c\x07\x33"}, {0x35, "\x34\x1f\xb0"}, {0x35, "\x3c\xed\xcd"}, + {0x35, "\x50\x00\x06"}, {0x35, "\x48\x07\xff"}, {0x35, "\x60\x05\x89"}, + {0x35, "\x58\x07\xff"}, {0x35, "\x40\x00\xa0"}, {0x35, "\x42\x00\x00"}, + {0x32, "\x10\x01\xfc"}, {0x33, "\x8c\xa1\x18"}, + /* Flip/Mirror h/v=1 */ + {0x33, "\x90\x00\x3c"}, {0x33, "\x8c\x27\x19"}, {0x33, "\x90\x04\x6c"}, + {0x33, "\x8c\x27\x3b"}, {0x33, "\x90\x00\x24"}, {0x33, "\x8c\xa1\x03"}, + {0x33, "\x90\x00\x06"}, + {130, "\xff\xff\xff"}, + {0x33, "\x90\x00\x06"}, {0x33, "\x90\x00\x06"}, {0x33, "\x90\x00\x06"}, + {0x33, "\x90\x00\x06"}, {0x33, "\x90\x00\x06"}, {0x33, "\x90\x00\x06"}, + {100, "\xff\xff\xff"}, + /* ?? */ + {0x33, "\x8c\xa1\x02"}, {0x33, "\x90\x00\x1f"}, {0x33, "\x8c\xa1\x02"}, + {0x33, "\x90\x00\x1f"}, {0x33, "\x8c\xa1\x02"}, {0x33, "\x90\x00\x1f"}, + {0x33, "\x8c\xa1\x02"}, {0x33, "\x90\x00\x1f"}, + /* Brigthness=70 */ + {0x33, "\x8c\xa2\x06"}, {0x33, "\x90\x00\x46"}, {0x33, "\x8c\xa1\x02"}, + {0x33, "\x90\x00\x0f"}, {0x33, "\x8c\xa1\x03"}, {0x33, "\x90\x00\x05"}, + /* Sharpness=20 */ + {0x32, "\x6c\x14\x08"}, +}; + +static struct idxdata tbl_init_post_alt_big_a[] = { + {0x33, "\x8c\xa1\x03"}, {0x33, "\x90\x00\x05"}, + {2, "\xff\xff\xff"}, + {0x33, "\x8c\xa1\x03"}, {0x33, "\x90\x00\x06"}, + {2, "\xff\xff\xff"}, + {0x34, "\x1e\x8f\x09"}, {0x34, "\x1c\x01\x28"}, {0x34, "\x1e\x8f\x09"}, + {0x34, "\x1e\x8f\x09"}, {0x32, "\x14\x06\xe6"}, {0x33, "\x8c\xa1\x03"}, + {0x33, "\x90\x00\x05"}, + {2, "\xff\xff\xff"}, + {0x33, "\x8c\xa1\x03"}, {0x33, "\x90\x00\x06"}, + {2, "\xff\xff\xff"}, + {0x33, "\x8c\xa1\x03"}, {0x33, "\x90\x00\x05"}, + {2, "\xff\xff\xff"}, + {0x33, "\x8c\xa1\x03"}, {0x33, "\x90\x00\x06"}, {0x33, "\x8c\xa1\x20"}, + {0x33, "\x90\x00\x72"}, {0x33, "\x8c\xa1\x30"}, {0x33, "\x90\x00\x03"}, + {0x33, "\x8c\xa1\x31"}, {0x33, "\x90\x00\x02"}, {0x33, "\x8c\xa1\x32"}, + {0x33, "\x90\x00\x03"}, {0x33, "\x8c\xa1\x34"}, {0x33, "\x90\x00\x03"}, + {0x33, "\x8c\xa1\x03"}, {0x33, "\x90\x00\x02"}, {0x33, "\x2e\x01\x00"}, + {0x34, "\x04\x00\x2a"}, {0x33, "\x8c\xa7\x02"}, {0x33, "\x90\x00\x01"}, +}; + +static struct idxdata tbl_init_post_alt_big_b[] = { + {0x32, "\x10\x01\xf8"}, {0x34, "\xce\x01\xa8"}, {0x34, "\xd0\x66\x33"}, + {0x34, "\xd2\x31\x9a"}, {0x34, "\xd4\x94\x63"}, {0x34, "\xd6\x4b\x25"}, + {0x34, "\xd8\x26\x70"}, {0x34, "\xda\x72\x4c"}, {0x34, "\xdc\xff\x04"}, + {0x34, "\xde\x01\x5b"}, {0x34, "\xe6\x01\x13"}, {0x34, "\xee\x0b\xf0"}, + {0x34, "\xf6\x0b\xa4"}, {0x35, "\x00\xf6\xe7"}, {0x35, "\x08\x0d\xfd"}, + {0x35, "\x10\x25\x63"}, {0x35, "\x18\x35\x6c"}, {0x35, "\x20\x42\x7e"}, + {0x35, "\x28\x19\x44"}, {0x35, "\x30\x39\xd4"}, {0x35, "\x38\xf5\xa8"}, + {0x35, "\x4c\x07\x90"}, {0x35, "\x44\x07\xb8"}, {0x35, "\x5c\x06\x88"}, + {0x35, "\x54\x07\xff"}, {0x34, "\xe0\x01\x52"}, {0x34, "\xe8\x00\xcc"}, + {0x34, "\xf0\x0d\x83"}, {0x34, "\xf8\x0c\xb3"}, {0x35, "\x02\xfe\xba"}, + {0x35, "\x0a\x04\xe0"}, {0x35, "\x12\x1c\x63"}, {0x35, "\x1a\x2b\x5a"}, + {0x35, "\x22\x32\x5e"}, {0x35, "\x2a\x0d\x28"}, {0x35, "\x32\x2c\x02"}, + {0x35, "\x3a\xf4\xfa"}, {0x35, "\x4e\x07\xef"}, {0x35, "\x46\x07\x88"}, + {0x35, "\x5e\x07\xc1"}, {0x35, "\x56\x04\x64"}, {0x34, "\xe4\x01\x15"}, + {0x34, "\xec\x00\x82"}, {0x34, "\xf4\x0c\xce"}, {0x34, "\xfc\x0c\xba"}, + {0x35, "\x06\x1f\x02"}, {0x35, "\x0e\x02\xe3"}, {0x35, "\x16\x1a\x50"}, + {0x35, "\x1e\x24\x39"}, {0x35, "\x26\x23\x4c"}, {0x35, "\x2e\xf9\x1b"}, + {0x35, "\x36\x23\x19"}, {0x35, "\x3e\x12\x08"}, {0x35, "\x52\x07\x22"}, + {0x35, "\x4a\x03\xd3"}, {0x35, "\x62\x06\x54"}, {0x35, "\x5a\x04\x5d"}, + {0x34, "\xe2\x01\x04"}, {0x34, "\xea\x00\xa0"}, {0x34, "\xf2\x0c\xbc"}, + {0x34, "\xfa\x0c\x5b"}, {0x35, "\x04\x17\xf2"}, {0x35, "\x0c\x02\x08"}, + {0x35, "\x14\x28\x43"}, {0x35, "\x1c\x28\x62"}, {0x35, "\x24\x2b\x60"}, + {0x35, "\x2c\x07\x33"}, {0x35, "\x34\x1f\xb0"}, {0x35, "\x3c\xed\xcd"}, + {0x35, "\x50\x00\x06"}, {0x35, "\x48\x07\xff"}, {0x35, "\x60\x05\x89"}, + {0x35, "\x58\x07\xff"}, {0x35, "\x40\x00\xa0"}, {0x35, "\x42\x00\x00"}, + {0x32, "\x10\x01\xfc"}, {0x33, "\x8c\xa1\x18"}, {0x33, "\x90\x00\x3c"}, +}; + +static struct idxdata tbl_init_post_alt_big_c[] = { + {0x33, "\x8c\xa1\x02"}, + {0x33, "\x90\x00\x1f"}, + {0x33, "\x8c\xa1\x02"}, + {0x33, "\x90\x00\x1f"}, + {0x33, "\x8c\xa1\x02"}, + {0x33, "\x90\x00\x1f"}, + {0x33, "\x8c\xa1\x02"}, + {0x33, "\x90\x00\x1f"}, +}; + +static u8 *dat_640 = "\xd0\x02\xd1\x08\xd2\xe1\xd3\x02\xd4\x10\xd5\x81"; +static u8 *dat_800 = "\xd0\x02\xd1\x10\xd2\x57\xd3\x02\xd4\x18\xd5\x21"; +static u8 *dat_1280 = "\xd0\x02\xd1\x20\xd2\x01\xd3\x02\xd4\x28\xd5\x01"; +static u8 *dat_1600 = "\xd0\x02\xd1\x20\xd2\xaf\xd3\x02\xd4\x30\xd5\x41"; + +static int mi2020_init_at_startup(struct gspca_dev *gspca_dev); +static int mi2020_configure_alt(struct gspca_dev *gspca_dev); +static int mi2020_init_pre_alt(struct gspca_dev *gspca_dev); +static int mi2020_init_post_alt(struct gspca_dev *gspca_dev); +static void mi2020_post_unset_alt(struct gspca_dev *gspca_dev); +static int mi2020_camera_settings(struct gspca_dev *gspca_dev); +/*==========================================================================*/ + +void mi2020_init_settings(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + sd->vcur.backlight = 0; + sd->vcur.brightness = 70; + sd->vcur.sharpness = 20; + sd->vcur.contrast = 0; + sd->vcur.gamma = 0; + sd->vcur.hue = 0; + sd->vcur.saturation = 60; + sd->vcur.whitebal = 50; + sd->vcur.mirror = 0; + sd->vcur.flip = 0; + sd->vcur.AC50Hz = 1; + + sd->vmax.backlight = 64; + sd->vmax.brightness = 128; + sd->vmax.sharpness = 40; + sd->vmax.contrast = 3; + sd->vmax.gamma = 2; + sd->vmax.hue = 0 + 1; /* 200 */ + sd->vmax.saturation = 0; /* 100 */ + sd->vmax.whitebal = 0; /* 100 */ + sd->vmax.mirror = 1; + sd->vmax.flip = 1; + sd->vmax.AC50Hz = 1; + if (_MI2020b_) { + sd->vmax.contrast = 0; + sd->vmax.gamma = 0; + sd->vmax.backlight = 0; + } + + sd->dev_camera_settings = mi2020_camera_settings; + sd->dev_init_at_startup = mi2020_init_at_startup; + sd->dev_configure_alt = mi2020_configure_alt; + sd->dev_init_pre_alt = mi2020_init_pre_alt; + sd->dev_post_unset_alt = mi2020_post_unset_alt; +} + +/*==========================================================================*/ + +static void common(struct gspca_dev *gspca_dev) +{ + s32 reso = gspca_dev->cam.cam_mode[(s32) gspca_dev->curr_mode].priv; + + if (_MI2020b_) { + fetch_validx(gspca_dev, tbl_common_a, ARRAY_SIZE(tbl_common_a)); + } else { + if (_MI2020_) + ctrl_out(gspca_dev, 0x40, 1, 0x0008, 0x0004, 0, NULL); + else + ctrl_out(gspca_dev, 0x40, 1, 0x0002, 0x0004, 0, NULL); + msleep(35); + fetch_validx(gspca_dev, tbl_common_b, ARRAY_SIZE(tbl_common_b)); + } + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x86\x25\x01"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x86\x25\x00"); + msleep(2); /* - * */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0030, 3, "\x1a\x0a\xcc"); + if (reso == IMAGE_1600) + msleep(2); /* 1600 */ + fetch_idxdata(gspca_dev, tbl_common_c, ARRAY_SIZE(tbl_common_c)); + + if (_MI2020b_ || _MI2020_) + fetch_idxdata(gspca_dev, tbl_common_d, + ARRAY_SIZE(tbl_common_d)); + + fetch_idxdata(gspca_dev, tbl_common_e, ARRAY_SIZE(tbl_common_e)); + if (_MI2020b_ || _MI2020_) { + /* Different from fret */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x78"); + /* Same as fret */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\x24\x17"); + /* Different from fret */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x90"); + } else { + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x6a"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\x24\x17"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x80"); + } + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\xa1\x03"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x05"); + msleep(2); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\xa1\x03"); + if (reso == IMAGE_1600) + msleep(14); /* 1600 */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x06"); + msleep(2); +} + +static int mi2020_init_at_startup(struct gspca_dev *gspca_dev) +{ + u8 c; + + ctrl_in(gspca_dev, 0xc0, 2, 0x0000, 0x0004, 1, &c); + ctrl_in(gspca_dev, 0xc0, 2, 0x0000, 0x0004, 1, &c); + + fetch_validx(gspca_dev, tbl_init_at_startup, + ARRAY_SIZE(tbl_init_at_startup)); + + common(gspca_dev); + + return 0; +} + +static int mi2020_init_pre_alt(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + sd->mirrorMask = 0; + + sd->vold.backlight = -1; + sd->vold.brightness = -1; + sd->vold.sharpness = -1; + sd->vold.contrast = -1; + sd->vold.gamma = -1; + sd->vold.hue = -1; + sd->vold.mirror = -1; + sd->vold.flip = -1; + sd->vold.AC50Hz = -1; + + mi2020_init_post_alt(gspca_dev); + + return 0; +} + +static int mi2020_init_post_alt(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + s32 reso = gspca_dev->cam.cam_mode[(s32) gspca_dev->curr_mode].priv; + + s32 backlight = sd->vcur.backlight; + s32 mirror = (((sd->vcur.mirror > 0) ^ sd->mirrorMask) > 0); + s32 flip = (((sd->vcur.flip > 0) ^ sd->mirrorMask) > 0); + s32 freq = (sd->vcur.AC50Hz > 0); + + u8 dat_freq2[] = {0x90, 0x00, 0x80}; + u8 dat_multi1[] = {0x8c, 0xa7, 0x00}; + u8 dat_multi2[] = {0x90, 0x00, 0x00}; + u8 dat_multi3[] = {0x8c, 0xa7, 0x00}; + u8 dat_multi4[] = {0x90, 0x00, 0x00}; + u8 dat_hvflip2[] = {0x90, 0x04, 0x6c}; + u8 dat_hvflip4[] = {0x90, 0x00, 0x24}; + u8 c; + + sd->nbIm = -1; + + dat_freq2[2] = freq ? 0xc0 : 0x80; + dat_multi1[2] = 0x9d; + dat_multi3[2] = dat_multi1[2] + 1; + dat_multi4[2] = dat_multi2[2] = backlight; + dat_hvflip2[2] = 0x6c + 2 * (1 - flip) + (1 - mirror); + dat_hvflip4[2] = 0x24 + 2 * (1 - flip) + (1 - mirror); + + msleep(200); + + ctrl_out(gspca_dev, 0x40, 5, 0x0001, 0x0000, 0, NULL); + msleep(3); /* 35 * */ + + common(gspca_dev); + + ctrl_out(gspca_dev, 0x40, 1, 0x0041, 0x0000, 0, NULL); + msleep(70); + + if (_MI2020b_) + ctrl_out(gspca_dev, 0x40, 1, 0x0040, 0x0000, 0, NULL); + + ctrl_out(gspca_dev, 0x40, 1, 0x0010, 0x0010, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x0003, 0x00c1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x0042, 0x00c2, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x006a, 0x000d, 0, NULL); + + switch (reso) { + case IMAGE_640: + case IMAGE_800: + if (reso != IMAGE_800) + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, + 12, dat_640); + else + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, + 12, dat_800); + + if (_MI2020c_) + fetch_idxdata(gspca_dev, tbl_init_post_alt_low_a, + ARRAY_SIZE(tbl_init_post_alt_low_a)); + + if (reso == IMAGE_800) + fetch_idxdata(gspca_dev, tbl_init_post_alt_low_b, + ARRAY_SIZE(tbl_init_post_alt_low_b)); + + fetch_idxdata(gspca_dev, tbl_init_post_alt_low_c, + ARRAY_SIZE(tbl_init_post_alt_low_c)); + + if (_MI2020b_) { + ctrl_out(gspca_dev, 0x40, 1, 0x0001, 0x0010, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x0000, 0x00c1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x0041, 0x00c2, 0, NULL); + msleep(150); + } else if (_MI2020c_) { + ctrl_out(gspca_dev, 0x40, 1, 0x0010, 0x0010, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x0000, 0x00c1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x0041, 0x00c2, 0, NULL); + msleep(120); + ctrl_out(gspca_dev, 0x40, 1, 0x0040, 0x0000, 0, NULL); + msleep(30); + } else if (_MI2020_) { + ctrl_out(gspca_dev, 0x40, 1, 0x0001, 0x0010, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x0000, 0x00c1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x0041, 0x00c2, 0, NULL); + msleep(120); + ctrl_out(gspca_dev, 0x40, 1, 0x0040, 0x0000, 0, NULL); + msleep(30); + } + + /* AC power frequency */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_freq1); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_freq2); + msleep(20); + /* backlight */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi1); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi2); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi3); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi4); + /* at init time but not after */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\xa2\x0c"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x17"); + /* finish the backlight */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi5); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi6); + msleep(5);/* " */ + + if (_MI2020c_) { + fetch_idxdata(gspca_dev, tbl_init_post_alt_low_d, + ARRAY_SIZE(tbl_init_post_alt_low_d)); + } else { + ctrl_in(gspca_dev, 0xc0, 2, 0x0000, 0x0000, 1, &c); + msleep(14); /* 0xd8 */ + + /* flip/mirror */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, dat_hvflip1); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, dat_hvflip2); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, dat_hvflip3); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, dat_hvflip4); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, dat_hvflip5); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, dat_hvflip6); + msleep(21); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, dat_dummy1); + msleep(5); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, dat_dummy1); + msleep(5); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, dat_dummy1); + msleep(5); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, dat_dummy1); + msleep(5); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, dat_dummy1); + msleep(5); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, dat_dummy1); + /* end of flip/mirror main part */ + msleep(246); /* 146 */ + + sd->nbIm = 0; + } + break; + + case IMAGE_1280: + case IMAGE_1600: + if (reso == IMAGE_1280) { + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, + 12, dat_1280); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, "\x8c\x27\x07"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, "\x90\x05\x04"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, "\x8c\x27\x09"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, "\x90\x04\x02"); + } else { + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, + 12, dat_1600); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, "\x8c\x27\x07"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, "\x90\x06\x40"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, "\x8c\x27\x09"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, + 3, "\x90\x04\xb0"); + } + + fetch_idxdata(gspca_dev, tbl_init_post_alt_big_a, + ARRAY_SIZE(tbl_init_post_alt_big_a)); + + if (reso == IMAGE_1600) + msleep(13); /* 1600 */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\x27\x97"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x01\x00"); + msleep(53); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\xa1\x20"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x00"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\xa1\x03"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x01"); + if (reso == IMAGE_1600) + msleep(13); /* 1600 */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\xa7\x02"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x00"); + msleep(53); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\xa1\x20"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x72"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\xa1\x03"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x02"); + if (reso == IMAGE_1600) + msleep(13); /* 1600 */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\xa7\x02"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x01"); + msleep(53); + + if (_MI2020b_) { + ctrl_out(gspca_dev, 0x40, 1, 0x0001, 0x0010, 0, NULL); + if (reso == IMAGE_1600) + msleep(500); /* 1600 */ + ctrl_out(gspca_dev, 0x40, 1, 0x0000, 0x00c1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x0041, 0x00c2, 0, NULL); + msleep(1850); + } else if (_MI2020c_ || _MI2020_) { + ctrl_out(gspca_dev, 0x40, 1, 0x0001, 0x0010, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x0000, 0x00c1, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x0041, 0x00c2, 0, NULL); + msleep(1850); + ctrl_out(gspca_dev, 0x40, 1, 0x0040, 0x0000, 0, NULL); + msleep(30); + } + + /* AC power frequency */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_freq1); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_freq2); + msleep(20); + /* backlight */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi1); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi2); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi3); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi4); + /* at init time but not after */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\xa2\x0c"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x17"); + /* finish the backlight */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi5); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi6); + msleep(6); /* " */ + + ctrl_in(gspca_dev, 0xc0, 2, 0x0000, 0x0000, 1, &c); + msleep(14); + + if (_MI2020c_) + fetch_idxdata(gspca_dev, tbl_init_post_alt_big_b, + ARRAY_SIZE(tbl_init_post_alt_big_b)); + + /* flip/mirror */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_hvflip1); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_hvflip2); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_hvflip3); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_hvflip4); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_hvflip5); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_hvflip6); + /* end of flip/mirror main part */ + msleep(16); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\xa1\x03"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x01"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\xa1\x20"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x00"); + if (reso == IMAGE_1600) + msleep(25); /* 1600 */ + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\xa7\x02"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x00"); + msleep(103); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\xa1\x03"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x02"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\xa1\x20"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x72"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x8c\xa7\x02"); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, "\x90\x00\x01"); + sd->nbIm = 0; + + if (_MI2020c_) + fetch_idxdata(gspca_dev, tbl_init_post_alt_big_c, + ARRAY_SIZE(tbl_init_post_alt_big_c)); + } + + sd->vold.mirror = mirror; + sd->vold.flip = flip; + sd->vold.AC50Hz = freq; + sd->vold.backlight = backlight; + + mi2020_camera_settings(gspca_dev); + + return 0; +} + +static int mi2020_configure_alt(struct gspca_dev *gspca_dev) +{ + s32 reso = gspca_dev->cam.cam_mode[(s32) gspca_dev->curr_mode].priv; + + switch (reso) { + case IMAGE_640: + gspca_dev->alt = 3 + 1; + break; + + case IMAGE_800: + case IMAGE_1280: + case IMAGE_1600: + gspca_dev->alt = 1 + 1; + break; + } + return 0; +} + +int mi2020_camera_settings(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + s32 backlight = sd->vcur.backlight; + s32 bright = sd->vcur.brightness; + s32 sharp = sd->vcur.sharpness; + s32 cntr = sd->vcur.contrast; + s32 gam = sd->vcur.gamma; + s32 hue = (sd->vcur.hue > 0); + s32 mirror = (((sd->vcur.mirror > 0) ^ sd->mirrorMask) > 0); + s32 flip = (((sd->vcur.flip > 0) ^ sd->mirrorMask) > 0); + s32 freq = (sd->vcur.AC50Hz > 0); + + u8 dat_sharp[] = {0x6c, 0x00, 0x08}; + u8 dat_bright2[] = {0x90, 0x00, 0x00}; + u8 dat_freq2[] = {0x90, 0x00, 0x80}; + u8 dat_multi1[] = {0x8c, 0xa7, 0x00}; + u8 dat_multi2[] = {0x90, 0x00, 0x00}; + u8 dat_multi3[] = {0x8c, 0xa7, 0x00}; + u8 dat_multi4[] = {0x90, 0x00, 0x00}; + u8 dat_hvflip2[] = {0x90, 0x04, 0x6c}; + u8 dat_hvflip4[] = {0x90, 0x00, 0x24}; + + /* Less than 4 images received -> too early to set the settings */ + if (sd->nbIm < 4) { + sd->waitSet = 1; + return 0; + } + sd->waitSet = 0; + + if (freq != sd->vold.AC50Hz) { + sd->vold.AC50Hz = freq; + + dat_freq2[2] = freq ? 0xc0 : 0x80; + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_freq1); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_freq2); + msleep(20); + } + + if (mirror != sd->vold.mirror || flip != sd->vold.flip) { + sd->vold.mirror = mirror; + sd->vold.flip = flip; + + dat_hvflip2[2] = 0x6c + 2 * (1 - flip) + (1 - mirror); + dat_hvflip4[2] = 0x24 + 2 * (1 - flip) + (1 - mirror); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_hvflip1); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_hvflip2); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_hvflip3); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_hvflip4); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_hvflip5); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_hvflip6); + msleep(130); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_dummy1); + msleep(6); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_dummy1); + msleep(6); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_dummy1); + msleep(6); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_dummy1); + msleep(6); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_dummy1); + msleep(6); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_dummy1); + msleep(6); + + /* Sometimes present, sometimes not, useful? */ + /* ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dummy2); + * ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dummy3); + * ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dummy2); + * ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dummy3); + * ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dummy2); + * ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dummy3); + * ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dummy2); + * ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dummy3);*/ + } + + if (backlight != sd->vold.backlight) { + sd->vold.backlight = backlight; + if (backlight < 0 || backlight > sd->vmax.backlight) + backlight = 0; + + dat_multi1[2] = 0x9d; + dat_multi3[2] = dat_multi1[2] + 1; + dat_multi4[2] = dat_multi2[2] = backlight; + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi1); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi2); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi3); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi4); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi5); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi6); + } + + if (gam != sd->vold.gamma) { + sd->vold.gamma = gam; + if (gam < 0 || gam > sd->vmax.gamma) + gam = 0; + + dat_multi1[2] = 0x6d; + dat_multi3[2] = dat_multi1[2] + 1; + dat_multi4[2] = dat_multi2[2] = 0x40 + gam; + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi1); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi2); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi3); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi4); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi5); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi6); + } + + if (cntr != sd->vold.contrast) { + sd->vold.contrast = cntr; + if (cntr < 0 || cntr > sd->vmax.contrast) + cntr = 0; + + dat_multi1[2] = 0x6d; + dat_multi3[2] = dat_multi1[2] + 1; + dat_multi4[2] = dat_multi2[2] = 0x12 + 16 * cntr; + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi1); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi2); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi3); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi4); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi5); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_multi6); + } + + if (bright != sd->vold.brightness) { + sd->vold.brightness = bright; + if (bright < 0 || bright > sd->vmax.brightness) + bright = 0; + + dat_bright2[2] = bright; + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_bright1); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_bright2); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_bright3); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_bright4); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_bright5); + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0033, 3, dat_bright6); + } + + if (sharp != sd->vold.sharpness) { + sd->vold.sharpness = sharp; + if (sharp < 0 || sharp > sd->vmax.sharpness) + sharp = 0; + + dat_sharp[1] = sharp; + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, 0x0032, 3, dat_sharp); + } + + if (hue != sd->vold.hue) { + sd->swapRB = hue; + sd->vold.hue = hue; + } + + return 0; +} + +static void mi2020_post_unset_alt(struct gspca_dev *gspca_dev) +{ + ctrl_out(gspca_dev, 0x40, 5, 0x0000, 0x0000, 0, NULL); + msleep(20); + if (_MI2020c_ || _MI2020_) + ctrl_out(gspca_dev, 0x40, 1, 0x0001, 0x0000, 0, NULL); + else + ctrl_out(gspca_dev, 0x40, 1, 0x0041, 0x0000, 0, NULL); +} diff --git a/drivers/media/video/gspca/gl860/gl860-ov2640.c b/drivers/media/video/gspca/gl860/gl860-ov2640.c new file mode 100644 index 000000000000..14b9c373f9f7 --- /dev/null +++ b/drivers/media/video/gspca/gl860/gl860-ov2640.c @@ -0,0 +1,505 @@ +/* @file gl860-ov2640.c + * @author Olivier LORIN, from Malmostoso's logs + * @date 2009-08-27 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Sensor : OV2640 */ + +#include "gl860.h" + +static u8 dat_init1[] = "\x00\x41\x07\x6a\x06\x61\x0d\x6a" "\x10\x10\xc1\x01"; +static u8 dat_init2[] = {0x61}; /* expected */ +static u8 dat_init3[] = {0x51}; /* expected */ + +static u8 dat_post[] = + "\x00\x41\x07\x6a\x06\xef\x0d\x6a" "\x10\x10\xc1\x01"; + +static u8 dat_640[] = "\xd0\x01\xd1\x08\xd2\xe0\xd3\x02\xd4\x10\xd5\x81"; +static u8 dat_800[] = "\xd0\x01\xd1\x10\xd2\x58\xd3\x02\xd4\x18\xd5\x21"; +static u8 dat_1280[] = "\xd0\x01\xd1\x18\xd2\xc0\xd3\x02\xd4\x28\xd5\x01"; +static u8 dat_1600[] = "\xd0\x01\xd1\x20\xd2\xb0\xd3\x02\xd4\x30\xd5\x41"; + +static u8 c50[] = {0x50}; /* expected */ +static u8 c28[] = {0x28}; /* expected */ +static u8 ca8[] = {0xa8}; /* expected */ + +static struct validx tbl_init_at_startup[] = { + {0x0000, 0x0000}, {0x0010, 0x0010}, {0x0008, 0x00c0}, {0x0001, 0x00c1}, + {0x0001, 0x00c2}, {0x0020, 0x0006}, {0x006a, 0x000d}, + {0x0050, 0x0000}, {0x0041, 0x0000}, {0x006a, 0x0007}, {0x0061, 0x0006}, + {0x006a, 0x000d}, {0x0000, 0x00c0}, {0x0010, 0x0010}, {0x0001, 0x00c1}, + {0x0041, 0x00c2}, {0x0004, 0x00d8}, {0x0012, 0x0004}, {0x0000, 0x0058}, + {0x0041, 0x0000}, {0x0061, 0x0000}, +}; + +static struct validx tbl_common[] = { + {0x6000, 0x00ff}, {0x60ff, 0x002c}, {0x60df, 0x002e}, {0x6001, 0x00ff}, + {0x6080, 0x0012}, {0x6000, 0x0000}, {0x6000, 0x0045}, {0x6000, 0x0010}, + {0x6035, 0x003c}, {0x6000, 0x0011}, {0x6028, 0x0004}, {0x60e5, 0x0013}, + {0x6088, 0x0014}, {0x600c, 0x002c}, {0x6078, 0x0033}, {0x60f7, 0x003b}, + {0x6000, 0x003e}, {0x6011, 0x0043}, {0x6010, 0x0016}, {0x6082, 0x0039}, + {0x6088, 0x0035}, {0x600a, 0x0022}, {0x6040, 0x0037}, {0x6000, 0x0023}, + {0x60a0, 0x0034}, {0x601a, 0x0036}, {0x6002, 0x0006}, {0x60c0, 0x0007}, + {0x60b7, 0x000d}, {0x6001, 0x000e}, {0x6000, 0x004c}, {0x6081, 0x004a}, + {0x6099, 0x0021}, {0x6002, 0x0009}, {0x603e, 0x0024}, {0x6034, 0x0025}, + {0x6081, 0x0026}, {0x6000, 0x0000}, {0x6000, 0x0045}, {0x6000, 0x0010}, + {0x6000, 0x005c}, {0x6000, 0x0063}, {0x6000, 0x007c}, {0x6070, 0x0061}, + {0x6080, 0x0062}, {0x6080, 0x0020}, {0x6030, 0x0028}, {0x6000, 0x006c}, + {0x6000, 0x006e}, {0x6002, 0x0070}, {0x6094, 0x0071}, {0x60c1, 0x0073}, + {0x6034, 0x003d}, {0x6057, 0x005a}, {0x60bb, 0x004f}, {0x609c, 0x0050}, + {0x6080, 0x006d}, {0x6002, 0x0039}, {0x6033, 0x003a}, {0x60f1, 0x003b}, + {0x6031, 0x003c}, {0x6000, 0x00ff}, {0x6014, 0x00e0}, {0x60ff, 0x0076}, + {0x60a0, 0x0033}, {0x6020, 0x0042}, {0x6018, 0x0043}, {0x6000, 0x004c}, + {0x60d0, 0x0087}, {0x600f, 0x0088}, {0x6003, 0x00d7}, {0x6010, 0x00d9}, + {0x6005, 0x00da}, {0x6082, 0x00d3}, {0x60c0, 0x00f9}, {0x6006, 0x0044}, + {0x6007, 0x00d1}, {0x6002, 0x00d2}, {0x6000, 0x00d2}, {0x6011, 0x00d8}, + {0x6008, 0x00c8}, {0x6080, 0x00c9}, {0x6008, 0x007c}, {0x6020, 0x007d}, + {0x6020, 0x007d}, {0x6000, 0x0090}, {0x600e, 0x0091}, {0x601a, 0x0091}, + {0x6031, 0x0091}, {0x605a, 0x0091}, {0x6069, 0x0091}, {0x6075, 0x0091}, + {0x607e, 0x0091}, {0x6088, 0x0091}, {0x608f, 0x0091}, {0x6096, 0x0091}, + {0x60a3, 0x0091}, {0x60af, 0x0091}, {0x60c4, 0x0091}, {0x60d7, 0x0091}, + {0x60e8, 0x0091}, {0x6020, 0x0091}, {0x6000, 0x0092}, {0x6006, 0x0093}, + {0x60e3, 0x0093}, {0x6005, 0x0093}, {0x6005, 0x0093}, {0x6000, 0x0093}, + {0x6004, 0x0093}, {0x6000, 0x0093}, {0x6000, 0x0093}, {0x6000, 0x0093}, + {0x6000, 0x0093}, {0x6000, 0x0093}, {0x6000, 0x0093}, {0x6000, 0x0093}, + {0x6000, 0x0096}, {0x6008, 0x0097}, {0x6019, 0x0097}, {0x6002, 0x0097}, + {0x600c, 0x0097}, {0x6024, 0x0097}, {0x6030, 0x0097}, {0x6028, 0x0097}, + {0x6026, 0x0097}, {0x6002, 0x0097}, {0x6098, 0x0097}, {0x6080, 0x0097}, + {0x6000, 0x0097}, {0x6000, 0x0097}, {0x60ed, 0x00c3}, {0x609a, 0x00c4}, + {0x6000, 0x00a4}, {0x6011, 0x00c5}, {0x6051, 0x00c6}, {0x6010, 0x00c7}, + {0x6066, 0x00b6}, {0x60a5, 0x00b8}, {0x6064, 0x00b7}, {0x607c, 0x00b9}, + {0x60af, 0x00b3}, {0x6097, 0x00b4}, {0x60ff, 0x00b5}, {0x60c5, 0x00b0}, + {0x6094, 0x00b1}, {0x600f, 0x00b2}, {0x605c, 0x00c4}, {0x6000, 0x00a8}, + {0x60c8, 0x00c0}, {0x6096, 0x00c1}, {0x601d, 0x0086}, {0x6000, 0x0050}, + {0x6090, 0x0051}, {0x6018, 0x0052}, {0x6000, 0x0053}, {0x6000, 0x0054}, + {0x6088, 0x0055}, {0x6000, 0x0057}, {0x6090, 0x005a}, {0x6018, 0x005b}, + {0x6005, 0x005c}, {0x60ed, 0x00c3}, {0x6000, 0x007f}, {0x6005, 0x00da}, + {0x601f, 0x00e5}, {0x6067, 0x00e1}, {0x6000, 0x00e0}, {0x60ff, 0x00dd}, + {0x6000, 0x0005}, {0x6001, 0x00ff}, {0x6000, 0x0000}, {0x6000, 0x0045}, + {0x6000, 0x0010}, +}; + +static struct validx tbl_sensor_settings_common_a[] = { + {0x0041, 0x0000}, {0x006a, 0x0007}, {0x00ef, 0x0006}, {0x006a, 0x000d}, + {0x0000, 0x00c0}, {0x0010, 0x0010}, {0x0001, 0x00c1}, {0x0041, 0x00c2}, + {0x0004, 0x00d8}, {0x0012, 0x0004}, {0x0000, 0x0058}, {0x0041, 0x0000}, + {50, 0xffff}, + {0x0061, 0x0000}, + {0xffff, 0xffff}, + {0x6000, 0x00ff}, {0x6000, 0x007c}, {0x6007, 0x007d}, + {30, 0xffff}, + {0x0040, 0x0000}, +}; + +static struct validx tbl_sensor_settings_common_b[] = { + {0x6001, 0x00ff}, {0x6038, 0x000c}, + {10, 0xffff}, + {0x6000, 0x0011}, + /* backlight=31/64 */ + {0x6001, 0x00ff}, {0x603e, 0x0024}, {0x6034, 0x0025}, + /* bright=0/256 */ + {0x6000, 0x00ff}, {0x6009, 0x007c}, {0x6000, 0x007d}, + /* wbal=64/128 */ + {0x6000, 0x00ff}, {0x6003, 0x007c}, {0x6040, 0x007d}, + /* cntr=0/256 */ + {0x6000, 0x00ff}, {0x6007, 0x007c}, {0x6000, 0x007d}, + /* sat=128/256 */ + {0x6000, 0x00ff}, {0x6001, 0x007c}, {0x6080, 0x007d}, + /* sharpness=0/32 */ + {0x6000, 0x00ff}, {0x6001, 0x0092}, {0x60c0, 0x0093}, + /* hue=0/256 */ + {0x6000, 0x00ff}, {0x6002, 0x007c}, {0x6000, 0x007d}, + /* gam=32/64 */ + {0x6000, 0x00ff}, {0x6008, 0x007c}, {0x6020, 0x007d}, + /* image right up */ + {0xffff, 0xffff}, + {15, 0xffff}, + {0x6001, 0x00ff}, {0x6000, 0x8004}, + {0xffff, 0xffff}, + {0x60a8, 0x0004}, + {15, 0xffff}, + {0x6001, 0x00ff}, {0x6000, 0x8004}, + {0xffff, 0xffff}, + {0x60f8, 0x0004}, + /* image right up */ + {0xffff, 0xffff}, + /* backlight=31/64 */ + {0x6001, 0x00ff}, {0x603e, 0x0024}, {0x6034, 0x0025}, +}; + +static struct validx tbl_640[] = { + {0x6000, 0x00ff}, {0x60f1, 0x00dd}, {0x6004, 0x00e0}, {0x6067, 0x00e1}, + {0x6004, 0x00da}, {0x6000, 0x00ff}, {0x60f1, 0x00dd}, {0x6004, 0x00e0}, + {0x6001, 0x00ff}, {0x6000, 0x0012}, {0x6000, 0x0011}, {0x6011, 0x0017}, + {0x6075, 0x0018}, {0x6001, 0x0019}, {0x6097, 0x001a}, {0x6036, 0x0032}, + {0x60bb, 0x004f}, {0x6057, 0x005a}, {0x609c, 0x0050}, {0x6080, 0x006d}, + {0x6092, 0x0026}, {0x60ff, 0x0020}, {0x6000, 0x0027}, {0x6000, 0x00ff}, + {0x60c8, 0x00c0}, {0x6096, 0x00c1}, {0x6000, 0x008c}, {0x603d, 0x0086}, + {0x6089, 0x0050}, {0x6090, 0x0051}, {0x602c, 0x0052}, {0x6000, 0x0053}, + {0x6000, 0x0054}, {0x6088, 0x0055}, {0x6000, 0x0057}, {0x60a0, 0x005a}, + {0x6078, 0x005b}, {0x6000, 0x005c}, {0x6004, 0x00d3}, {0x6000, 0x00e0}, + {0x60ff, 0x00dd}, {0x60a1, 0x005a}, +}; + +static struct validx tbl_800[] = { + {0x6000, 0x00ff}, {0x60f1, 0x00dd}, {0x6004, 0x00e0}, {0x6067, 0x00e1}, + {0x6004, 0x00da}, {0x6000, 0x00ff}, {0x60f1, 0x00dd}, {0x6004, 0x00e0}, + {0x6001, 0x00ff}, {0x6040, 0x0012}, {0x6000, 0x0011}, {0x6011, 0x0017}, + {0x6043, 0x0018}, {0x6000, 0x0019}, {0x604b, 0x001a}, {0x6009, 0x0032}, + {0x60ca, 0x004f}, {0x60a8, 0x0050}, {0x6000, 0x006d}, {0x6038, 0x003d}, + {0x60c8, 0x0035}, {0x6000, 0x0022}, {0x6092, 0x0026}, {0x60ff, 0x0020}, + {0x6000, 0x0027}, {0x6000, 0x00ff}, {0x6064, 0x00c0}, {0x604b, 0x00c1}, + {0x6000, 0x008c}, {0x601d, 0x0086}, {0x6082, 0x00d3}, {0x6000, 0x00e0}, + {0x60ff, 0x00dd}, {0x6020, 0x008c}, {0x6001, 0x00ff}, {0x6044, 0x0018}, +}; + +static struct validx tbl_big_a[] = { + {0x0002, 0x00c1}, {0x6000, 0x00ff}, {0x60f1, 0x00dd}, {0x6004, 0x00e0}, + {0x6001, 0x00ff}, {0x6000, 0x0012}, {0x6000, 0x0000}, {0x6000, 0x0045}, + {0x6000, 0x0010}, {0x6000, 0x0011}, {0x6011, 0x0017}, {0x6075, 0x0018}, + {0x6001, 0x0019}, {0x6097, 0x001a}, {0x6036, 0x0032}, {0x60bb, 0x004f}, + {0x609c, 0x0050}, {0x6057, 0x005a}, {0x6080, 0x006d}, {0x6043, 0x000f}, + {0x608f, 0x0003}, {0x6005, 0x007c}, {0x6081, 0x0026}, {0x6000, 0x00ff}, + {0x60c8, 0x00c0}, {0x6096, 0x00c1}, {0x6000, 0x008c}, +}; + +static struct validx tbl_big_b[] = { + {0x603d, 0x0086}, {0x6000, 0x0050}, {0x6090, 0x0051}, {0x602c, 0x0052}, + {0x6000, 0x0053}, {0x6000, 0x0054}, {0x6088, 0x0055}, {0x6000, 0x0057}, + {0x6040, 0x005a}, {0x60f0, 0x005b}, {0x6001, 0x005c}, {0x6082, 0x00d3}, + {0x6000, 0x008e}, +}; + +static struct validx tbl_big_c[] = { + {0x6004, 0x00da}, {0x6000, 0x00e0}, {0x6067, 0x00e1}, {0x60ff, 0x00dd}, + {0x6001, 0x00ff}, {0x6000, 0x00ff}, {0x60f1, 0x00dd}, {0x6004, 0x00e0}, + {0x6001, 0x00ff}, {0x6000, 0x0011}, {0x6000, 0x00ff}, {0x6010, 0x00c7}, + {0x6000, 0x0092}, {0x6006, 0x0093}, {0x60e3, 0x0093}, {0x6005, 0x0093}, + {0x6005, 0x0093}, {0x60ed, 0x00c3}, {0x6000, 0x00a4}, {0x60d0, 0x0087}, + {0x6003, 0x0096}, {0x600c, 0x0097}, {0x6024, 0x0097}, {0x6030, 0x0097}, + {0x6028, 0x0097}, {0x6026, 0x0097}, {0x6002, 0x0097}, {0x6001, 0x00ff}, + {0x6043, 0x000f}, {0x608f, 0x0003}, {0x6000, 0x002d}, {0x6000, 0x002e}, + {0x600a, 0x0022}, {0x6002, 0x0070}, {0x6008, 0x0014}, {0x6048, 0x0014}, + {0x6000, 0x00ff}, {0x6000, 0x00e0}, {0x60ff, 0x00dd}, +}; + +static struct validx tbl_post_unset_alt[] = { + {0x006a, 0x000d}, {0x6001, 0x00ff}, {0x6081, 0x0026}, {0x6000, 0x0000}, + {0x6000, 0x0045}, {0x6000, 0x0010}, {0x6068, 0x000d}, + {50, 0xffff}, + {0x0021, 0x0000}, +}; + +static int ov2640_init_at_startup(struct gspca_dev *gspca_dev); +static int ov2640_configure_alt(struct gspca_dev *gspca_dev); +static int ov2640_init_pre_alt(struct gspca_dev *gspca_dev); +static int ov2640_init_post_alt(struct gspca_dev *gspca_dev); +static void ov2640_post_unset_alt(struct gspca_dev *gspca_dev); +static int ov2640_camera_settings(struct gspca_dev *gspca_dev); +/*==========================================================================*/ + +void ov2640_init_settings(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + sd->vcur.backlight = 32; + sd->vcur.brightness = 0; + sd->vcur.sharpness = 6; + sd->vcur.contrast = 0; + sd->vcur.gamma = 32; + sd->vcur.hue = 0; + sd->vcur.saturation = 128; + sd->vcur.whitebal = 64; + + sd->vmax.backlight = 64; + sd->vmax.brightness = 255; + sd->vmax.sharpness = 31; + sd->vmax.contrast = 255; + sd->vmax.gamma = 64; + sd->vmax.hue = 255 + 1; + sd->vmax.saturation = 255; + sd->vmax.whitebal = 128; + sd->vmax.mirror = 0; + sd->vmax.flip = 0; + sd->vmax.AC50Hz = 0; + + sd->dev_camera_settings = ov2640_camera_settings; + sd->dev_init_at_startup = ov2640_init_at_startup; + sd->dev_configure_alt = ov2640_configure_alt; + sd->dev_init_pre_alt = ov2640_init_pre_alt; + sd->dev_post_unset_alt = ov2640_post_unset_alt; +} + +/*==========================================================================*/ + +static void common(struct gspca_dev *gspca_dev) +{ + fetch_validx(gspca_dev, tbl_common, ARRAY_SIZE(tbl_common)); +} + +static int ov2640_init_at_startup(struct gspca_dev *gspca_dev) +{ + fetch_validx(gspca_dev, tbl_init_at_startup, + ARRAY_SIZE(tbl_init_at_startup)); + + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, 12, dat_init1); + + common(gspca_dev); + + ctrl_in(gspca_dev, 0xc0, 2, 0x0000, 0x0006, 1, dat_init2); + + ctrl_out(gspca_dev, 0x40, 1, 0x00ef, 0x0006, 0, NULL); + + ctrl_in(gspca_dev, 0xc0, 2, 0x0000, 0x0000, 1, dat_init3); + + ctrl_out(gspca_dev, 0x40, 1, 0x0051, 0x0000, 0, NULL); +/* ctrl_out(gspca_dev, 0x40, 11, 0x0000, 0x0000, 0, NULL); */ + + return 0; +} + +static int ov2640_init_pre_alt(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + sd->vold.backlight = -1; + sd->vold.brightness = -1; + sd->vold.sharpness = -1; + sd->vold.contrast = -1; + sd->vold.saturation = -1; + sd->vold.gamma = -1; + sd->vold.hue = -1; + sd->vold.whitebal = -1; + + ov2640_init_post_alt(gspca_dev); + + return 0; +} + +static int ov2640_init_post_alt(struct gspca_dev *gspca_dev) +{ + s32 reso = gspca_dev->cam.cam_mode[(s32) gspca_dev->curr_mode].priv; + s32 n; /* reserved for FETCH macros */ + + ctrl_out(gspca_dev, 0x40, 5, 0x0001, 0x0000, 0, NULL); + + n = fetch_validx(gspca_dev, tbl_sensor_settings_common_a, + ARRAY_SIZE(tbl_sensor_settings_common_a)); + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, 12, dat_post); + common(gspca_dev); + keep_on_fetching_validx(gspca_dev, tbl_sensor_settings_common_a, + ARRAY_SIZE(tbl_sensor_settings_common_a), n); + + switch (reso) { + case IMAGE_640: + n = fetch_validx(gspca_dev, tbl_640, ARRAY_SIZE(tbl_640)); + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, 12, dat_640); + break; + + case IMAGE_800: + n = fetch_validx(gspca_dev, tbl_800, ARRAY_SIZE(tbl_800)); + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, 12, dat_800); + break; + + case IMAGE_1600: + case IMAGE_1280: + n = fetch_validx(gspca_dev, tbl_big_a, ARRAY_SIZE(tbl_big_a)); + + if (reso == IMAGE_1280) { + n = fetch_validx(gspca_dev, tbl_big_b, + ARRAY_SIZE(tbl_big_b)); + } else { + ctrl_out(gspca_dev, 0x40, 1, 0x601d, 0x0086, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6001, 0x00d7, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6082, 0x00d3, 0, NULL); + } + + n = fetch_validx(gspca_dev, tbl_big_c, ARRAY_SIZE(tbl_big_c)); + + if (reso == IMAGE_1280) { + ctrl_out(gspca_dev, 0x40, 1, 0x6001, 0x00ff, 0, NULL); + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, + 12, dat_1280); + } else { + ctrl_out(gspca_dev, 0x40, 1, 0x6020, 0x008c, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6001, 0x00ff, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6076, 0x0018, 0, NULL); + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, + 12, dat_1600); + } + break; + } + + n = fetch_validx(gspca_dev, tbl_sensor_settings_common_b, + ARRAY_SIZE(tbl_sensor_settings_common_b)); + ctrl_in(gspca_dev, 0xc0, 2, 0x0000, 0x0000, 1, c50); + keep_on_fetching_validx(gspca_dev, tbl_sensor_settings_common_b, + ARRAY_SIZE(tbl_sensor_settings_common_b), n); + ctrl_in(gspca_dev, 0xc0, 2, 0x6000, 0x8004, 1, c28); + keep_on_fetching_validx(gspca_dev, tbl_sensor_settings_common_b, + ARRAY_SIZE(tbl_sensor_settings_common_b), n); + ctrl_in(gspca_dev, 0xc0, 2, 0x6000, 0x8004, 1, ca8); + keep_on_fetching_validx(gspca_dev, tbl_sensor_settings_common_b, + ARRAY_SIZE(tbl_sensor_settings_common_b), n); + ctrl_in(gspca_dev, 0xc0, 2, 0x0000, 0x0000, 1, c50); + keep_on_fetching_validx(gspca_dev, tbl_sensor_settings_common_b, + ARRAY_SIZE(tbl_sensor_settings_common_b), n); + + ov2640_camera_settings(gspca_dev); + + return 0; +} + +static int ov2640_configure_alt(struct gspca_dev *gspca_dev) +{ + s32 reso = gspca_dev->cam.cam_mode[(s32) gspca_dev->curr_mode].priv; + + switch (reso) { + case IMAGE_640: + gspca_dev->alt = 3 + 1; + break; + + case IMAGE_800: + case IMAGE_1280: + case IMAGE_1600: + gspca_dev->alt = 1 + 1; + break; + } + return 0; +} + +static int ov2640_camera_settings(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + s32 backlight = sd->vcur.backlight; + s32 bright = sd->vcur.brightness; + s32 sharp = sd->vcur.sharpness; + s32 gam = sd->vcur.gamma; + s32 cntr = sd->vcur.contrast; + s32 sat = sd->vcur.saturation; + s32 hue = sd->vcur.hue; + s32 wbal = sd->vcur.whitebal; + + if (backlight != sd->vold.backlight) { + if (backlight < 0 || backlight > sd->vmax.backlight) + backlight = 0; + + ctrl_out(gspca_dev, 0x40, 1, 0x6001 , 0x00ff, + 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x601f + backlight , 0x0024, + 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x601f + backlight - 10, 0x0025, + 0, NULL); + /* No sd->vold.backlight=backlight; (to be done again later) */ + } + + if (bright != sd->vold.brightness) { + sd->vold.brightness = bright; + if (bright < 0 || bright > sd->vmax.brightness) + bright = 0; + + ctrl_out(gspca_dev, 0x40, 1, 0x6000 , 0x00ff, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6009 , 0x007c, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6000 + bright, 0x007d, 0, NULL); + } + + if (wbal != sd->vold.whitebal) { + sd->vold.whitebal = wbal; + if (wbal < 0 || wbal > sd->vmax.whitebal) + wbal = 0; + + ctrl_out(gspca_dev, 0x40, 1, 0x6000 , 0x00ff, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6003 , 0x007c, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6000 + wbal, 0x007d, 0, NULL); + } + + if (cntr != sd->vold.contrast) { + sd->vold.contrast = cntr; + if (cntr < 0 || cntr > sd->vmax.contrast) + cntr = 0; + + ctrl_out(gspca_dev, 0x40, 1, 0x6000 , 0x00ff, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6007 , 0x007c, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6000 + cntr, 0x007d, 0, NULL); + } + + if (sat != sd->vold.saturation) { + sd->vold.saturation = sat; + if (sat < 0 || sat > sd->vmax.saturation) + sat = 0; + + ctrl_out(gspca_dev, 0x40, 1, 0x6000 , 0x00ff, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6001 , 0x007c, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6000 + sat, 0x007d, 0, NULL); + } + + if (sharp != sd->vold.sharpness) { + sd->vold.sharpness = sharp; + if (sharp < 0 || sharp > sd->vmax.sharpness) + sharp = 0; + + ctrl_out(gspca_dev, 0x40, 1, 0x6000 , 0x00ff, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6001 , 0x0092, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x60c0 + sharp, 0x0093, 0, NULL); + } + + if (hue != sd->vold.hue) { + sd->vold.hue = hue; + if (hue < 0 || hue > sd->vmax.hue) + hue = 0; + + ctrl_out(gspca_dev, 0x40, 1, 0x6000 , 0x00ff, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6002 , 0x007c, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6000 + hue * (hue < 255), 0x007d, + 0, NULL); + if (hue >= sd->vmax.hue) + sd->swapRB = 1; + else + sd->swapRB = 0; + } + + if (gam != sd->vold.gamma) { + sd->vold.gamma = gam; + if (gam < 0 || gam > sd->vmax.gamma) + gam = 0; + + ctrl_out(gspca_dev, 0x40, 1, 0x6000 , 0x00ff, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6008 , 0x007c, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x6000 + gam, 0x007d, 0, NULL); + } + + if (backlight != sd->vold.backlight) { + sd->vold.backlight = backlight; + + ctrl_out(gspca_dev, 0x40, 1, 0x6001 , 0x00ff, + 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x601f + backlight , 0x0024, + 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x601f + backlight - 10, 0x0025, + 0, NULL); + } + + return 0; +} + +static void ov2640_post_unset_alt(struct gspca_dev *gspca_dev) +{ + ctrl_out(gspca_dev, 0x40, 5, 0x0000, 0x0000, 0, NULL); + msleep(20); + fetch_validx(gspca_dev, tbl_post_unset_alt, + ARRAY_SIZE(tbl_post_unset_alt)); +} diff --git a/drivers/media/video/gspca/gl860/gl860-ov9655.c b/drivers/media/video/gspca/gl860/gl860-ov9655.c new file mode 100644 index 000000000000..eda3346f939c --- /dev/null +++ b/drivers/media/video/gspca/gl860/gl860-ov9655.c @@ -0,0 +1,337 @@ +/* @file gl860-ov9655.c + * @author Olivier LORIN, from logs done by Simon (Sur3) and Almighurt + * on dsd's weblog + * @date 2009-08-27 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Sensor : OV9655 */ + +#include "gl860.h" + +static struct validx tbl_init_at_startup[] = { + {0x0000, 0x0000}, {0x0010, 0x0010}, {0x0008, 0x00c0}, {0x0001, 0x00c1}, + {0x0001, 0x00c2}, {0x0020, 0x0006}, {0x006a, 0x000d}, + + {0x0040, 0x0000}, +}; + +static struct validx tbl_commmon[] = { + {0x0041, 0x0000}, {0x006a, 0x0007}, {0x0063, 0x0006}, {0x006a, 0x000d}, + {0x0000, 0x00c0}, {0x0010, 0x0010}, {0x0001, 0x00c1}, {0x0041, 0x00c2}, + {0x0004, 0x00d8}, {0x0012, 0x0004}, {0x0000, 0x0058}, {0x0040, 0x0000}, + {0x00f3, 0x0006}, {0x0058, 0x0000}, {0x0048, 0x0000}, {0x0061, 0x0000}, +}; + +static s32 tbl_length[] = {12, 56, 52, 54, 56, 42, 32, 12}; + +static u8 *tbl_640[] = { + "\x00\x40\x07\x6a\x06\xf3\x0d\x6a" "\x10\x10\xc1\x01" + , + "\x12\x80\x00\x00\x01\x98\x02\x80" "\x03\x12\x04\x03\x0b\x57\x0e\x61" + "\x0f\x42\x11\x01\x12\x60\x13\x00" "\x14\x3a\x16\x24\x17\x14\x18\x00" + "\x19\x01\x1a\x3d\x1e\x04\x24\x3c" "\x25\x36\x26\x72\x27\x08\x28\x08" + "\x29\x15\x2a\x00\x2b\x00\x2c\x08" + , + "\x32\xff\x33\x00\x34\x3d\x35\x00" "\x36\xfa\x38\x72\x39\x57\x3a\x00" + "\x3b\x0c\x3d\x99\x3e\x0c\x3f\xc1" "\x40\xc0\x41\x00\x42\xc0\x43\x0a" + "\x44\xf0\x45\x46\x46\x62\x47\x2a" "\x48\x3c\x4a\xee\x4b\xe7\x4c\xe7" + "\x4d\xe7\x4e\xe7" + , + "\x4f\x98\x50\x98\x51\x00\x52\x28" "\x53\x70\x54\x98\x58\x1a\x59\x85" + "\x5a\xa9\x5b\x64\x5c\x84\x5d\x53" "\x5e\x0e\x5f\xf0\x60\xf0\x61\xf0" + "\x62\x00\x63\x00\x64\x02\x65\x20" "\x66\x00\x69\x0a\x6b\x5a\x6c\x04" + "\x6d\x55\x6e\x00\x6f\x9d" + , + "\x70\x15\x71\x78\x72\x00\x73\x00" "\x74\x3a\x75\x35\x76\x01\x77\x02" + "\x7a\x24\x7b\x04\x7c\x07\x7d\x10" "\x7e\x28\x7f\x36\x80\x44\x81\x52" + "\x82\x60\x83\x6c\x84\x78\x85\x8c" "\x86\x9e\x87\xbb\x88\xd2\x89\xe5" + "\x8a\x23\x8c\x8d\x90\x7c\x91\x7b" + , + "\x9d\x02\x9e\x02\x9f\x74\xa0\x73" "\xa1\x40\xa4\x50\xa5\x68\xa6\x70" + "\xa8\xc1\xa9\xef\xaa\x92\xab\x04" "\xac\x80\xad\x80\xae\x80\xaf\x80" + "\xb2\xf2\xb3\x20\xb4\x20\xb5\x00" "\xb6\xaf" + , + "\xbb\xae\xbc\x4f\xbd\x4e\xbe\x6a" "\xbf\x68\xc0\xaa\xc1\xc0\xc2\x01" + "\xc3\x4e\xc6\x85\xc7\x81\xc9\xe0" "\xca\xe8\xcb\xf0\xcc\xd8\xcd\x93" + , + "\xd0\x01\xd1\x08\xd2\xe0\xd3\x01" "\xd4\x10\xd5\x80" +}; + +static u8 *tbl_800[] = { + "\x00\x40\x07\x6a\x06\xf3\x0d\x6a" "\x10\x10\xc1\x01" + , + "\x12\x80\x00\x00\x01\x98\x02\x80" "\x03\x12\x04\x01\x0b\x57\x0e\x61" + "\x0f\x42\x11\x00\x12\x00\x13\x00" "\x14\x3a\x16\x24\x17\x1b\x18\xbb" + "\x19\x01\x1a\x81\x1e\x04\x24\x3c" "\x25\x36\x26\x72\x27\x08\x28\x08" + "\x29\x15\x2a\x00\x2b\x00\x2c\x08" + , + "\x32\xa4\x33\x00\x34\x3d\x35\x00" "\x36\xf8\x38\x72\x39\x57\x3a\x00" + "\x3b\x0c\x3d\x99\x3e\x0c\x3f\xc2" "\x40\xc0\x41\x00\x42\xc0\x43\x0a" + "\x44\xf0\x45\x46\x46\x62\x47\x2a" "\x48\x3c\x4a\xec\x4b\xe8\x4c\xe8" + "\x4d\xe8\x4e\xe8" + , + "\x4f\x98\x50\x98\x51\x00\x52\x28" "\x53\x70\x54\x98\x58\x1a\x59\x85" + "\x5a\xa9\x5b\x64\x5c\x84\x5d\x53" "\x5e\x0e\x5f\xf0\x60\xf0\x61\xf0" + "\x62\x00\x63\x00\x64\x02\x65\x20" "\x66\x00\x69\x02\x6b\x5a\x6c\x04" + "\x6d\x55\x6e\x00\x6f\x9d" + , + "\x70\x08\x71\x78\x72\x00\x73\x01" "\x74\x3a\x75\x35\x76\x01\x77\x02" + "\x7a\x24\x7b\x04\x7c\x07\x7d\x10" "\x7e\x28\x7f\x36\x80\x44\x81\x52" + "\x82\x60\x83\x6c\x84\x78\x85\x8c" "\x86\x9e\x87\xbb\x88\xd2\x89\xe5" + "\x8a\x23\x8c\x0d\x90\x90\x91\x90" + , + "\x9d\x02\x9e\x02\x9f\x94\xa0\x94" "\xa1\x01\xa4\x50\xa5\x68\xa6\x70" + "\xa8\xc1\xa9\xef\xaa\x92\xab\x04" "\xac\x80\xad\x80\xae\x80\xaf\x80" + "\xb2\xf2\xb3\x20\xb4\x20\xb5\x00" "\xb6\xaf" + , + "\xbb\xae\xbc\x38\xbd\x39\xbe\x01" "\xbf\x01\xc0\xe2\xc1\xc0\xc2\x01" + "\xc3\x4e\xc6\x85\xc7\x81\xc9\xe0" "\xca\xe8\xcb\xf0\xcc\xd8\xcd\x93" + , + "\xd0\x21\xd1\x18\xd2\xe0\xd3\x01" "\xd4\x28\xd5\x00" +}; + +static u8 c04[] = {0x04}; +static u8 dat_post_1[] = "\x04\x00\x10\x20\xa1\x00\x00\x02"; +static u8 dat_post_2[] = "\x10\x10\xc1\x02"; +static u8 dat_post_3[] = "\x04\x00\x10\x7c\xa1\x00\x00\x04"; +static u8 dat_post_4[] = "\x10\x02\xc1\x06"; +static u8 dat_post_5[] = "\x04\x00\x10\x7b\xa1\x00\x00\x08"; +static u8 dat_post_6[] = "\x10\x10\xc1\x05"; +static u8 dat_post_7[] = "\x04\x00\x10\x7c\xa1\x00\x00\x08"; +static u8 dat_post_8[] = "\x04\x00\x10\x7c\xa1\x00\x00\x09"; + +static struct validx tbl_init_post_alt[] = { + {0x6032, 0x00ff}, {0x6032, 0x00ff}, {0x6032, 0x00ff}, {0x603c, 0x00ff}, + {0x6003, 0x00ff}, {0x6032, 0x00ff}, {0x6032, 0x00ff}, {0x6001, 0x00ff}, + {0x6000, 0x801e}, + {0xffff, 0xffff}, + {0x6004, 0x001e}, {0x6000, 0x801e}, + {0xffff, 0xffff}, + {0x6004, 0x001e}, {0x6012, 0x0003}, {0x6000, 0x801e}, + {0xffff, 0xffff}, + {0x6004, 0x001e}, {0x6000, 0x801e}, + {0xffff, 0xffff}, + {0x6004, 0x001e}, {0x6012, 0x0003}, + {0xffff, 0xffff}, + {0x6000, 0x801e}, + {0xffff, 0xffff}, + {0x6004, 0x001e}, {0x6000, 0x801e}, + {0xffff, 0xffff}, + {0x6004, 0x001e}, {0x6012, 0x0003}, {0x6000, 0x801e}, + {0xffff, 0xffff}, + {0x6004, 0x001e}, {0x6000, 0x801e}, + {0xffff, 0xffff}, + {0x6004, 0x001e}, {0x6012, 0x0003}, + {0xffff, 0xffff}, + {0x6000, 0x801e}, + {0xffff, 0xffff}, + {0x6004, 0x001e}, {0x6000, 0x801e}, + {0xffff, 0xffff}, + {0x6004, 0x001e}, {0x6012, 0x0003}, +}; + +static int ov9655_init_at_startup(struct gspca_dev *gspca_dev); +static int ov9655_configure_alt(struct gspca_dev *gspca_dev); +static int ov9655_init_pre_alt(struct gspca_dev *gspca_dev); +static int ov9655_init_post_alt(struct gspca_dev *gspca_dev); +static void ov9655_post_unset_alt(struct gspca_dev *gspca_dev); +static int ov9655_camera_settings(struct gspca_dev *gspca_dev); +/*==========================================================================*/ + +void ov9655_init_settings(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + sd->vcur.backlight = 0; + sd->vcur.brightness = 128; + sd->vcur.sharpness = 0; + sd->vcur.contrast = 0; + sd->vcur.gamma = 0; + sd->vcur.hue = 0; + sd->vcur.saturation = 0; + sd->vcur.whitebal = 0; + + sd->vmax.backlight = 0; + sd->vmax.brightness = 255; + sd->vmax.sharpness = 0; + sd->vmax.contrast = 0; + sd->vmax.gamma = 0; + sd->vmax.hue = 0 + 1; + sd->vmax.saturation = 0; + sd->vmax.whitebal = 0; + sd->vmax.mirror = 0; + sd->vmax.flip = 0; + sd->vmax.AC50Hz = 0; + + sd->dev_camera_settings = ov9655_camera_settings; + sd->dev_init_at_startup = ov9655_init_at_startup; + sd->dev_configure_alt = ov9655_configure_alt; + sd->dev_init_pre_alt = ov9655_init_pre_alt; + sd->dev_post_unset_alt = ov9655_post_unset_alt; +} + +/*==========================================================================*/ + +static int ov9655_init_at_startup(struct gspca_dev *gspca_dev) +{ + fetch_validx(gspca_dev, tbl_init_at_startup, + ARRAY_SIZE(tbl_init_at_startup)); + fetch_validx(gspca_dev, tbl_commmon, ARRAY_SIZE(tbl_commmon)); +/* ctrl_out(gspca_dev, 0x40, 11, 0x0000, 0x0000, 0, NULL);*/ + + return 0; +} + +static int ov9655_init_pre_alt(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + sd->vold.brightness = -1; + sd->vold.hue = -1; + + fetch_validx(gspca_dev, tbl_commmon, ARRAY_SIZE(tbl_commmon)); + + ov9655_init_post_alt(gspca_dev); + + return 0; +} + +static int ov9655_init_post_alt(struct gspca_dev *gspca_dev) +{ + s32 reso = gspca_dev->cam.cam_mode[(s32) gspca_dev->curr_mode].priv; + s32 n; /* reserved for FETCH macros */ + s32 i; + u8 **tbl; + + ctrl_out(gspca_dev, 0x40, 5, 0x0001, 0x0000, 0, NULL); + + tbl = (reso == IMAGE_640) ? tbl_640 : tbl_800; + + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, + tbl_length[0], tbl[0]); + for (i = 1; i < 7; i++) + ctrl_out(gspca_dev, 0x40, 3, 0x6000, 0x0200, + tbl_length[i], tbl[i]); + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, + tbl_length[7], tbl[7]); + + n = fetch_validx(gspca_dev, tbl_init_post_alt, + ARRAY_SIZE(tbl_init_post_alt)); + + ctrl_in(gspca_dev, 0xc0, 2, 0x6000, 0x801e, 1, c04); + keep_on_fetching_validx(gspca_dev, tbl_init_post_alt, + ARRAY_SIZE(tbl_init_post_alt), n); + ctrl_in(gspca_dev, 0xc0, 2, 0x6000, 0x801e, 1, c04); + keep_on_fetching_validx(gspca_dev, tbl_init_post_alt, + ARRAY_SIZE(tbl_init_post_alt), n); + ctrl_in(gspca_dev, 0xc0, 2, 0x6000, 0x801e, 1, c04); + keep_on_fetching_validx(gspca_dev, tbl_init_post_alt, + ARRAY_SIZE(tbl_init_post_alt), n); + ctrl_in(gspca_dev, 0xc0, 2, 0x6000, 0x801e, 1, c04); + keep_on_fetching_validx(gspca_dev, tbl_init_post_alt, + ARRAY_SIZE(tbl_init_post_alt), n); + ctrl_out(gspca_dev, 0x40, 3, 0x6000, 0x0200, 8, dat_post_1); + keep_on_fetching_validx(gspca_dev, tbl_init_post_alt, + ARRAY_SIZE(tbl_init_post_alt), n); + + ctrl_in(gspca_dev, 0xc0, 2, 0x6000, 0x801e, 1, c04); + keep_on_fetching_validx(gspca_dev, tbl_init_post_alt, + ARRAY_SIZE(tbl_init_post_alt), n); + ctrl_in(gspca_dev, 0xc0, 2, 0x6000, 0x801e, 1, c04); + keep_on_fetching_validx(gspca_dev, tbl_init_post_alt, + ARRAY_SIZE(tbl_init_post_alt), n); + ctrl_in(gspca_dev, 0xc0, 2, 0x6000, 0x801e, 1, c04); + keep_on_fetching_validx(gspca_dev, tbl_init_post_alt, + ARRAY_SIZE(tbl_init_post_alt), n); + ctrl_in(gspca_dev, 0xc0, 2, 0x6000, 0x801e, 1, c04); + keep_on_fetching_validx(gspca_dev, tbl_init_post_alt, + ARRAY_SIZE(tbl_init_post_alt), n); + ctrl_out(gspca_dev, 0x40, 3, 0x6000, 0x0200, 8, dat_post_1); + keep_on_fetching_validx(gspca_dev, tbl_init_post_alt, + ARRAY_SIZE(tbl_init_post_alt), n); + + ctrl_in(gspca_dev, 0xc0, 2, 0x6000, 0x801e, 1, c04); + keep_on_fetching_validx(gspca_dev, tbl_init_post_alt, + ARRAY_SIZE(tbl_init_post_alt), n); + ctrl_in(gspca_dev, 0xc0, 2, 0x6000, 0x801e, 1, c04); + keep_on_fetching_validx(gspca_dev, tbl_init_post_alt, + ARRAY_SIZE(tbl_init_post_alt), n); + + ctrl_out(gspca_dev, 0x40, 3, 0x6000, 0x0200, 8, dat_post_1); + + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, 4, dat_post_2); + ctrl_out(gspca_dev, 0x40, 3, 0x6000, 0x0200, 8, dat_post_3); + + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, 4, dat_post_4); + ctrl_out(gspca_dev, 0x40, 3, 0x6000, 0x0200, 8, dat_post_5); + + ctrl_out(gspca_dev, 0x40, 3, 0x0000, 0x0200, 4, dat_post_6); + ctrl_out(gspca_dev, 0x40, 3, 0x6000, 0x0200, 8, dat_post_7); + + ctrl_out(gspca_dev, 0x40, 3, 0x6000, 0x0200, 8, dat_post_8); + + ov9655_camera_settings(gspca_dev); + + return 0; +} + +static int ov9655_configure_alt(struct gspca_dev *gspca_dev) +{ + s32 reso = gspca_dev->cam.cam_mode[(s32) gspca_dev->curr_mode].priv; + + switch (reso) { + case IMAGE_640: + gspca_dev->alt = 1 + 1; + break; + + default: + gspca_dev->alt = 1 + 1; + break; + } + return 0; +} + +static int ov9655_camera_settings(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + u8 dat_bright[] = "\x04\x00\x10\x7c\xa1\x00\x00\x70"; + + s32 bright = sd->vcur.brightness; + s32 hue = sd->vcur.hue; + + if (bright != sd->vold.brightness) { + sd->vold.brightness = bright; + if (bright < 0 || bright > sd->vmax.brightness) + bright = 0; + + dat_bright[3] = bright; + ctrl_out(gspca_dev, 0x40, 3, 0x6000, 0x0200, 8, dat_bright); + } + + if (hue != sd->vold.hue) { + sd->vold.hue = hue; + sd->swapRB = (hue != 0); + } + + return 0; +} + +static void ov9655_post_unset_alt(struct gspca_dev *gspca_dev) +{ + ctrl_out(gspca_dev, 0x40, 5, 0x0000, 0x0000, 0, NULL); + ctrl_out(gspca_dev, 0x40, 1, 0x0061, 0x0000, 0, NULL); +} diff --git a/drivers/media/video/gspca/gl860/gl860.c b/drivers/media/video/gspca/gl860/gl860.c new file mode 100644 index 000000000000..6ef59ac7f502 --- /dev/null +++ b/drivers/media/video/gspca/gl860/gl860.c @@ -0,0 +1,785 @@ +/* @file gl860.c + * @date 2009-08-27 + * + * Genesys Logic webcam with gl860 subdrivers + * + * Driver by Olivier Lorin + * GSPCA by Jean-Francois Moine + * Thanks BUGabundo and Malmostoso for your amazing help! + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#include "gspca.h" +#include "gl860.h" + +MODULE_AUTHOR("Olivier Lorin "); +MODULE_DESCRIPTION("GSPCA/Genesys Logic GL860 USB Camera Driver"); +MODULE_LICENSE("GPL"); + +/*======================== static function declarations ====================*/ + +static void (*dev_init_settings)(struct gspca_dev *gspca_dev); + +static int sd_config(struct gspca_dev *gspca_dev, + const struct usb_device_id *id); +static int sd_init(struct gspca_dev *gspca_dev); +static int sd_isoc_init(struct gspca_dev *gspca_dev); +static int sd_start(struct gspca_dev *gspca_dev); +static void sd_stop0(struct gspca_dev *gspca_dev); +static void sd_pkt_scan(struct gspca_dev *gspca_dev, + struct gspca_frame *frame, u8 *data, s32 len); +static void sd_callback(struct gspca_dev *gspca_dev); + +static int gl860_guess_sensor(struct gspca_dev *gspca_dev, + s32 vendor_id, s32 product_id); + +/*============================ driver options ==============================*/ + +static s32 AC50Hz = 0xff; +module_param(AC50Hz, int, 0644); +MODULE_PARM_DESC(AC50Hz, " Does AC power frequency is 50Hz? (0/1)"); + +static char sensor[7]; +module_param_string(sensor, sensor, sizeof(sensor), 0644); +MODULE_PARM_DESC(sensor, + " Driver sensor ('MI1320'/'MI2020'/'OV9655'/'OV2640'/'')"); + +/*============================ webcam controls =============================*/ + +/* Functions to get and set a control value */ +#define SD_SETGET(thename) \ +static int sd_set_##thename(struct gspca_dev *gspca_dev, s32 val)\ +{\ + struct sd *sd = (struct sd *) gspca_dev;\ +\ + sd->vcur.thename = val;\ + if (gspca_dev->streaming)\ + sd->dev_camera_settings(gspca_dev);\ + return 0;\ +} \ +static int sd_get_##thename(struct gspca_dev *gspca_dev, s32 *val)\ +{\ + struct sd *sd = (struct sd *) gspca_dev;\ +\ + *val = sd->vcur.thename;\ + return 0;\ +} + +SD_SETGET(mirror) +SD_SETGET(flip) +SD_SETGET(AC50Hz) +SD_SETGET(backlight) +SD_SETGET(brightness) +SD_SETGET(gamma) +SD_SETGET(hue) +SD_SETGET(saturation) +SD_SETGET(sharpness) +SD_SETGET(whitebal) +SD_SETGET(contrast) + +#define GL860_NCTRLS 11 + +/* control table */ +static struct ctrl sd_ctrls_mi1320[GL860_NCTRLS]; +static struct ctrl sd_ctrls_mi2020[GL860_NCTRLS]; +static struct ctrl sd_ctrls_mi2020b[GL860_NCTRLS]; +static struct ctrl sd_ctrls_ov2640[GL860_NCTRLS]; +static struct ctrl sd_ctrls_ov9655[GL860_NCTRLS]; + +#define SET_MY_CTRL(theid, \ + thetype, thelabel, thename) \ + if (sd->vmax.thename != 0) {\ + sd_ctrls[nCtrls].qctrl.id = theid;\ + sd_ctrls[nCtrls].qctrl.type = thetype;\ + strcpy(sd_ctrls[nCtrls].qctrl.name, thelabel);\ + sd_ctrls[nCtrls].qctrl.minimum = 0;\ + sd_ctrls[nCtrls].qctrl.maximum = sd->vmax.thename;\ + sd_ctrls[nCtrls].qctrl.default_value = sd->vcur.thename;\ + sd_ctrls[nCtrls].qctrl.step = \ + (sd->vmax.thename < 16) ? 1 : sd->vmax.thename/16;\ + sd_ctrls[nCtrls].set = sd_set_##thename;\ + sd_ctrls[nCtrls].get = sd_get_##thename;\ + nCtrls++;\ + } + +static int gl860_build_control_table(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + struct ctrl *sd_ctrls; + int nCtrls = 0; + + if (_MI1320_) + sd_ctrls = sd_ctrls_mi1320; + else if (_MI2020_) + sd_ctrls = sd_ctrls_mi2020; + else if (_MI2020b_) + sd_ctrls = sd_ctrls_mi2020b; + else if (_OV2640_) + sd_ctrls = sd_ctrls_ov2640; + else if (_OV9655_) + sd_ctrls = sd_ctrls_ov9655; + else + return 0; + + memset(sd_ctrls, 0, GL860_NCTRLS * sizeof(struct ctrl)); + + SET_MY_CTRL(V4L2_CID_BRIGHTNESS, + V4L2_CTRL_TYPE_INTEGER, "Brightness", brightness) + SET_MY_CTRL(V4L2_CID_SHARPNESS, + V4L2_CTRL_TYPE_INTEGER, "Sharpness", sharpness) + SET_MY_CTRL(V4L2_CID_CONTRAST, + V4L2_CTRL_TYPE_INTEGER, "Contrast", contrast) + SET_MY_CTRL(V4L2_CID_GAMMA, + V4L2_CTRL_TYPE_INTEGER, "Gamma", gamma) + SET_MY_CTRL(V4L2_CID_HUE, + V4L2_CTRL_TYPE_INTEGER, "Palette", hue) + SET_MY_CTRL(V4L2_CID_SATURATION, + V4L2_CTRL_TYPE_INTEGER, "Saturation", saturation) + SET_MY_CTRL(V4L2_CID_WHITE_BALANCE_TEMPERATURE, + V4L2_CTRL_TYPE_INTEGER, "White Bal.", whitebal) + SET_MY_CTRL(V4L2_CID_BACKLIGHT_COMPENSATION, + V4L2_CTRL_TYPE_INTEGER, "Backlight" , backlight) + + SET_MY_CTRL(V4L2_CID_HFLIP, + V4L2_CTRL_TYPE_BOOLEAN, "Mirror", mirror) + SET_MY_CTRL(V4L2_CID_VFLIP, + V4L2_CTRL_TYPE_BOOLEAN, "Flip", flip) + SET_MY_CTRL(V4L2_CID_POWER_LINE_FREQUENCY, + V4L2_CTRL_TYPE_BOOLEAN, "50Hz", AC50Hz) + + return nCtrls; +} + +/*==================== sud-driver structure initialisation =================*/ + +static struct sd_desc sd_desc_mi1320 = { + .name = MODULE_NAME, + .ctrls = sd_ctrls_mi1320, + .nctrls = GL860_NCTRLS, + .config = sd_config, + .init = sd_init, + .isoc_init = sd_isoc_init, + .start = sd_start, + .stop0 = sd_stop0, + .pkt_scan = sd_pkt_scan, + .dq_callback = sd_callback, +}; + +static struct sd_desc sd_desc_mi2020 = { + .name = MODULE_NAME, + .ctrls = sd_ctrls_mi2020, + .nctrls = GL860_NCTRLS, + .config = sd_config, + .init = sd_init, + .isoc_init = sd_isoc_init, + .start = sd_start, + .stop0 = sd_stop0, + .pkt_scan = sd_pkt_scan, + .dq_callback = sd_callback, +}; + +static struct sd_desc sd_desc_mi2020b = { + .name = MODULE_NAME, + .ctrls = sd_ctrls_mi2020b, + .nctrls = GL860_NCTRLS, + .config = sd_config, + .init = sd_init, + .isoc_init = sd_isoc_init, + .start = sd_start, + .stop0 = sd_stop0, + .pkt_scan = sd_pkt_scan, + .dq_callback = sd_callback, +}; + +static struct sd_desc sd_desc_ov2640 = { + .name = MODULE_NAME, + .ctrls = sd_ctrls_ov2640, + .nctrls = GL860_NCTRLS, + .config = sd_config, + .init = sd_init, + .isoc_init = sd_isoc_init, + .start = sd_start, + .stop0 = sd_stop0, + .pkt_scan = sd_pkt_scan, + .dq_callback = sd_callback, +}; + +static struct sd_desc sd_desc_ov9655 = { + .name = MODULE_NAME, + .ctrls = sd_ctrls_ov9655, + .nctrls = GL860_NCTRLS, + .config = sd_config, + .init = sd_init, + .isoc_init = sd_isoc_init, + .start = sd_start, + .stop0 = sd_stop0, + .pkt_scan = sd_pkt_scan, + .dq_callback = sd_callback, +}; + +/*=========================== sub-driver image sizes =======================*/ + +static struct v4l2_pix_format mi2020_mode[] = { + { 640, 480, V4L2_PIX_FMT_SGBRG8, V4L2_FIELD_NONE, + .bytesperline = 640, + .sizeimage = 640 * 480, + .colorspace = V4L2_COLORSPACE_SRGB, + .priv = 0 + }, + { 800, 600, V4L2_PIX_FMT_SGBRG8, V4L2_FIELD_NONE, + .bytesperline = 800, + .sizeimage = 800 * 600, + .colorspace = V4L2_COLORSPACE_SRGB, + .priv = 1 + }, + {1280, 1024, V4L2_PIX_FMT_SGBRG8, V4L2_FIELD_NONE, + .bytesperline = 1280, + .sizeimage = 1280 * 1024, + .colorspace = V4L2_COLORSPACE_SRGB, + .priv = 2 + }, + {1600, 1200, V4L2_PIX_FMT_SGBRG8, V4L2_FIELD_NONE, + .bytesperline = 1600, + .sizeimage = 1600 * 1200, + .colorspace = V4L2_COLORSPACE_SRGB, + .priv = 3 + }, +}; + +static struct v4l2_pix_format ov2640_mode[] = { + { 640, 480, V4L2_PIX_FMT_SGBRG8, V4L2_FIELD_NONE, + .bytesperline = 640, + .sizeimage = 640 * 480, + .colorspace = V4L2_COLORSPACE_SRGB, + .priv = 0 + }, + { 800, 600, V4L2_PIX_FMT_SGBRG8, V4L2_FIELD_NONE, + .bytesperline = 800, + .sizeimage = 800 * 600, + .colorspace = V4L2_COLORSPACE_SRGB, + .priv = 1 + }, + {1280, 960, V4L2_PIX_FMT_SGBRG8, V4L2_FIELD_NONE, + .bytesperline = 1280, + .sizeimage = 1280 * 960, + .colorspace = V4L2_COLORSPACE_SRGB, + .priv = 2 + }, + {1600, 1200, V4L2_PIX_FMT_SGBRG8, V4L2_FIELD_NONE, + .bytesperline = 1600, + .sizeimage = 1600 * 1200, + .colorspace = V4L2_COLORSPACE_SRGB, + .priv = 3 + }, +}; + +static struct v4l2_pix_format mi1320_mode[] = { + { 640, 480, V4L2_PIX_FMT_SGBRG8, V4L2_FIELD_NONE, + .bytesperline = 640, + .sizeimage = 640 * 480, + .colorspace = V4L2_COLORSPACE_SRGB, + .priv = 0 + }, + { 800, 600, V4L2_PIX_FMT_SGBRG8, V4L2_FIELD_NONE, + .bytesperline = 800, + .sizeimage = 800 * 600, + .colorspace = V4L2_COLORSPACE_SRGB, + .priv = 1 + }, + {1280, 960, V4L2_PIX_FMT_SGBRG8, V4L2_FIELD_NONE, + .bytesperline = 1280, + .sizeimage = 1280 * 960, + .colorspace = V4L2_COLORSPACE_SRGB, + .priv = 2 + }, +}; + +static struct v4l2_pix_format ov9655_mode[] = { + { 640, 480, V4L2_PIX_FMT_SGBRG8, V4L2_FIELD_NONE, + .bytesperline = 640, + .sizeimage = 640 * 480, + .colorspace = V4L2_COLORSPACE_SRGB, + .priv = 0 + }, + {1280, 960, V4L2_PIX_FMT_SGBRG8, V4L2_FIELD_NONE, + .bytesperline = 1280, + .sizeimage = 1280 * 960, + .colorspace = V4L2_COLORSPACE_SRGB, + .priv = 1 + }, +}; + +/*========================= sud-driver functions ===========================*/ + +/* This function is called at probe time */ +static int sd_config(struct gspca_dev *gspca_dev, + const struct usb_device_id *id) +{ + struct sd *sd = (struct sd *) gspca_dev; + struct cam *cam; + s32 vendor_id, product_id; + + /* Get USB VendorID and ProductID */ + vendor_id = le16_to_cpu(id->idVendor); + product_id = le16_to_cpu(id->idProduct); + + sd->nbRightUp = 1; + sd->nbIm = -1; + + sd->sensor = 0xff; + if (strcmp(sensor, "MI1320") == 0) + sd->sensor = ID_MI1320; + else if (strcmp(sensor, "OV2640") == 0) + sd->sensor = ID_OV2640; + else if (strcmp(sensor, "OV9655") == 0) + sd->sensor = ID_OV9655; + else if (strcmp(sensor, "MI2020") == 0) + sd->sensor = ID_MI2020; + else if (strcmp(sensor, "MI2020b") == 0) + sd->sensor = ID_MI2020b; + + /* Get sensor and set the suitable init/start/../stop functions */ + if (gl860_guess_sensor(gspca_dev, vendor_id, product_id) == -1) + return -1; + + cam = &gspca_dev->cam; + gspca_dev->nbalt = 4; + + switch (sd->sensor) { + case ID_MI1320: + gspca_dev->sd_desc = &sd_desc_mi1320; + cam->cam_mode = mi1320_mode; + cam->nmodes = ARRAY_SIZE(mi1320_mode); + dev_init_settings = mi1320_init_settings; + break; + + case ID_MI2020: + gspca_dev->sd_desc = &sd_desc_mi2020; + cam->cam_mode = mi2020_mode; + cam->nmodes = ARRAY_SIZE(mi2020_mode); + dev_init_settings = mi2020_init_settings; + break; + + case ID_MI2020b: + gspca_dev->sd_desc = &sd_desc_mi2020b; + cam->cam_mode = mi2020_mode; + cam->nmodes = ARRAY_SIZE(mi2020_mode); + dev_init_settings = mi2020_init_settings; + break; + + case ID_OV2640: + gspca_dev->sd_desc = &sd_desc_ov2640; + cam->cam_mode = ov2640_mode; + cam->nmodes = ARRAY_SIZE(ov2640_mode); + dev_init_settings = ov2640_init_settings; + break; + + case ID_OV9655: + gspca_dev->sd_desc = &sd_desc_ov9655; + cam->cam_mode = ov9655_mode; + cam->nmodes = ARRAY_SIZE(ov9655_mode); + dev_init_settings = ov9655_init_settings; + break; + } + + dev_init_settings(gspca_dev); + if (AC50Hz != 0xff) + ((struct sd *) gspca_dev)->vcur.AC50Hz = AC50Hz; + gl860_build_control_table(gspca_dev); + + return 0; +} + +/* This function is called at probe time after sd_config */ +static int sd_init(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + return sd->dev_init_at_startup(gspca_dev); +} + +/* This function is called before to choose the alt setting */ +static int sd_isoc_init(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + return sd->dev_configure_alt(gspca_dev); +} + +/* This function is called to start the webcam */ +static int sd_start(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + return sd->dev_init_pre_alt(gspca_dev); +} + +/* This function is called to stop the webcam */ +static void sd_stop0(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + return sd->dev_post_unset_alt(gspca_dev); +} + +/* This function is called when an image is being received */ +static void sd_pkt_scan(struct gspca_dev *gspca_dev, + struct gspca_frame *frame, u8 *data, s32 len) +{ + struct sd *sd = (struct sd *) gspca_dev; + static s32 nSkipped; + + s32 mode = (s32) gspca_dev->curr_mode; + s32 nToSkip = + sd->swapRB * (gspca_dev->cam.cam_mode[mode].bytesperline + 1); + + /* Test only against 0202h, so endianess does not matter */ + switch (*(s16 *) data) { + case 0x0202: /* End of frame, start a new one */ + frame = gspca_frame_add(gspca_dev, LAST_PACKET, frame, data, 0); + nSkipped = 0; + if (sd->nbIm >= 0 && sd->nbIm < 10) + sd->nbIm++; + gspca_frame_add(gspca_dev, FIRST_PACKET, frame, data, 0); + break; + + default: + data += 2; + len -= 2; + if (nSkipped + len <= nToSkip) + nSkipped += len; + else { + if (nSkipped < nToSkip && nSkipped + len > nToSkip) { + data += nToSkip - nSkipped; + len -= nToSkip - nSkipped; + nSkipped = nToSkip + 1; + } + gspca_frame_add(gspca_dev, + INTER_PACKET, frame, data, len); + } + break; + } +} + +/* This function is called when an image has been read */ +/* This function is used to monitor webcam orientation */ +static void sd_callback(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + if (!_OV9655_) { + u8 state; + u8 upsideDown; + + /* Probe sensor orientation */ + ctrl_in(gspca_dev, 0xc0, 2, 0x0000, 0x0000, 1, (void *)&state); + + /* C8/40 means upside-down (looking backwards) */ + /* D8/50 means right-up (looking onwards) */ + upsideDown = (state == 0xc8 || state == 0x40); + + if (upsideDown && sd->nbRightUp > -4) { + if (sd->nbRightUp > 0) + sd->nbRightUp = 0; + if (sd->nbRightUp == -3) { + sd->mirrorMask = 1; + sd->waitSet = 1; + } + sd->nbRightUp--; + } + if (!upsideDown && sd->nbRightUp < 4) { + if (sd->nbRightUp < 0) + sd->nbRightUp = 0; + if (sd->nbRightUp == 3) { + sd->mirrorMask = 0; + sd->waitSet = 1; + } + sd->nbRightUp++; + } + } + + if (sd->waitSet) + sd->dev_camera_settings(gspca_dev); +} + +/*=================== USB driver structure initialisation ==================*/ + +static const __devinitdata struct usb_device_id device_table[] = { + {USB_DEVICE(0x05e3, 0x0503)}, + {USB_DEVICE(0x05e3, 0xf191)}, + {} +}; + +MODULE_DEVICE_TABLE(usb, device_table); + +static int sd_probe(struct usb_interface *intf, + const struct usb_device_id *id) +{ + struct gspca_dev *gspca_dev; + s32 ret; + + ret = gspca_dev_probe(intf, id, + &sd_desc_mi1320, sizeof(struct sd), THIS_MODULE); + + if (ret >= 0) { + gspca_dev = usb_get_intfdata(intf); + + PDEBUG(D_PROBE, + "Camera is now controlling video device /dev/video%d", + gspca_dev->vdev.minor); + } + + return ret; +} + +static void sd_disconnect(struct usb_interface *intf) +{ + gspca_disconnect(intf); +} + +static struct usb_driver sd_driver = { + .name = MODULE_NAME, + .id_table = device_table, + .probe = sd_probe, + .disconnect = sd_disconnect, +#ifdef CONFIG_PM + .suspend = gspca_suspend, + .resume = gspca_resume, +#endif +}; + +/*====================== Init and Exit module functions ====================*/ + +static int __init sd_mod_init(void) +{ + PDEBUG(D_PROBE, "driver startup - version %s", DRIVER_VERSION); + + if (usb_register(&sd_driver) < 0) + return -1; + PDEBUG(D_PROBE, "driver registered"); + + return 0; +} + +static void __exit sd_mod_exit(void) +{ + usb_deregister(&sd_driver); + PDEBUG(D_PROBE, "driver deregistered"); +} + +module_init(sd_mod_init); +module_exit(sd_mod_exit); + +/*==========================================================================*/ + +int gl860_RTx(struct gspca_dev *gspca_dev, + unsigned char pref, u32 req, u16 val, u16 index, + s32 len, void *pdata) +{ + struct usb_device *udev = gspca_dev->dev; + s32 r = 0; + + if (pref == 0x40) { /* Send */ + if (len > 0) { + memcpy(gspca_dev->usb_buf, pdata, len); + r = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), + req, pref, val, index, + gspca_dev->usb_buf, + len, 400 + 200 * (len > 1)); + } else { + r = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), + req, pref, val, index, NULL, len, 400); + } + } else { /* Receive */ + if (len > 0) { + r = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), + req, pref, val, index, + gspca_dev->usb_buf, + len, 400 + 200 * (len > 1)); + memcpy(pdata, gspca_dev->usb_buf, len); + } else { + r = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), + req, pref, val, index, NULL, len, 400); + } + } + + if (r < 0) + PDEBUG(D_ERR, + "ctrl transfer failed %4d " + "[p%02x r%d v%04x i%04x len%d]", + r, pref, req, val, index, len); + else if (len > 1 && r < len) + PDEBUG(D_ERR, "short ctrl transfer %d/%d", r, len); + + if ((_MI2020_ || _MI2020b_ || _MI2020c_) && (val || index)) + msleep(1); + if (_OV2640_) + msleep(1); + + return r; +} + +int fetch_validx(struct gspca_dev *gspca_dev, struct validx *tbl, int len) +{ + int n; + + for (n = 0; n < len; n++) { + if (tbl[n].idx != 0xffff) + ctrl_out(gspca_dev, 0x40, 1, tbl[n].val, + tbl[n].idx, 0, NULL); + else if (tbl[n].val == 0xffff) + break; + else + msleep(tbl[n].val); + } + return n; +} + +int keep_on_fetching_validx(struct gspca_dev *gspca_dev, struct validx *tbl, + int len, int n) +{ + while (++n < len) { + if (tbl[n].idx != 0xffff) + ctrl_out(gspca_dev, 0x40, 1, tbl[n].val, tbl[n].idx, + 0, NULL); + else if (tbl[n].val == 0xffff) + break; + else + msleep(tbl[n].val); + } + return n; +} + +void fetch_idxdata(struct gspca_dev *gspca_dev, struct idxdata *tbl, int len) +{ + int n; + + for (n = 0; n < len; n++) { + if (memcmp(tbl[n].data, "\xff\xff\xff", 3) != 0) + ctrl_out(gspca_dev, 0x40, 3, 0x7a00, tbl[n].idx, + 3, tbl[n].data); + else + msleep(tbl[n].idx); + } +} + +static int gl860_guess_sensor(struct gspca_dev *gspca_dev, + s32 vendor_id, s32 product_id) +{ + struct sd *sd = (struct sd *) gspca_dev; + u8 probe, nb26, nb96, nOV, ntry; + + if (product_id == 0xf191) + sd->sensor = ID_MI1320; + + if (sd->sensor == 0xff) { + ctrl_in(gspca_dev, 0xc0, 2, 0x0000, 0x0004, 1, &probe); + ctrl_in(gspca_dev, 0xc0, 2, 0x0000, 0x0004, 1, &probe); + + ctrl_out(gspca_dev, 0x40, 1, 0x0000, 0x0000, 0, NULL); + msleep(3); + ctrl_out(gspca_dev, 0x40, 1, 0x0010, 0x0010, 0, NULL); + msleep(3); + ctrl_out(gspca_dev, 0x40, 1, 0x0008, 0x00c0, 0, NULL); + msleep(3); + ctrl_out(gspca_dev, 0x40, 1, 0x0001, 0x00c1, 0, NULL); + msleep(3); + ctrl_out(gspca_dev, 0x40, 1, 0x0001, 0x00c2, 0, NULL); + msleep(3); + ctrl_out(gspca_dev, 0x40, 1, 0x0020, 0x0006, 0, NULL); + msleep(3); + ctrl_out(gspca_dev, 0x40, 1, 0x006a, 0x000d, 0, NULL); + msleep(56); + + nOV = 0; + for (ntry = 0; ntry < 4; ntry++) { + ctrl_out(gspca_dev, 0x40, 1, 0x0040, 0x0000, 0, NULL); + msleep(3); + ctrl_out(gspca_dev, 0x40, 1, 0x0063, 0x0006, 0, NULL); + msleep(3); + ctrl_out(gspca_dev, 0x40, 1, 0x7a00, 0x8030, 0, NULL); + msleep(10); + ctrl_in(gspca_dev, 0xc0, 2, 0x7a00, 0x8030, 1, &probe); + PDEBUG(D_PROBE, "1st probe=%02x", probe); + if (probe == 0xff) + nOV++; + } + + if (nOV) { + PDEBUG(D_PROBE, "0xff -> sensor OVXXXX"); + PDEBUG(D_PROBE, "Probing for sensor OV2640 or OV9655"); + + nb26 = nb96 = 0; + for (ntry = 0; ntry < 4; ntry++) { + ctrl_out(gspca_dev, 0x40, 1, 0x0040, 0x0000, + 0, NULL); + msleep(3); + ctrl_out(gspca_dev, 0x40, 1, 0x6000, 0x800a, + 0, NULL); + msleep(10); + /* Wait for 26(OV2640) or 96(OV9655) */ + ctrl_in(gspca_dev, 0xc0, 2, 0x6000, 0x800a, + 1, &probe); + + PDEBUG(D_PROBE, "2nd probe=%02x", probe); + if (probe == 0x00) + nb26++; + if (probe == 0x26 || probe == 0x40) { + sd->sensor = ID_OV2640; + nb26 += 4; + break; + } + if (probe == 0x96 || probe == 0x55) { + sd->sensor = ID_OV9655; + nb96 += 4; + break; + } + if (probe == 0xff) + nb96++; + msleep(3); + } + if (nb26 < 4 && nb96 < 4) { + PDEBUG(D_PROBE, "No relevant answer "); + PDEBUG(D_PROBE, "* 1.3Mpixels -> use OV9655"); + PDEBUG(D_PROBE, "* 2.0Mpixels -> use OV2640"); + PDEBUG(D_PROBE, + "To force a sensor, add that line to " + "/etc/modprobe.d/options.conf:"); + PDEBUG(D_PROBE, "options gspca_gl860 " + "sensor=\"OV2640\" or \"OV9655\""); + return -1; + } + } else { /* probe = 0 */ + PDEBUG(D_PROBE, "No 0xff -> sensor MI2020"); + sd->sensor = ID_MI2020; + } + } + + if (_MI1320_) { + PDEBUG(D_PROBE, "05e3:f191 sensor MI1320 (1.3M)"); + } else if (_MI2020_) { + PDEBUG(D_PROBE, "05e3:0503 sensor MI2020 (2.0M)"); + } else if (_MI2020b_) { + PDEBUG(D_PROBE, "05e3:0503 sensor MI2020 alt. driver (2.0M)"); + } else if (_OV9655_) { + PDEBUG(D_PROBE, "05e3:0503 sensor OV9655 (1.3M)"); + } else if (_OV2640_) { + PDEBUG(D_PROBE, "05e3:0503 sensor OV2640 (2.0M)"); + } else { + PDEBUG(D_PROBE, "***** Unknown sensor *****"); + return -1; + } + + return 0; +} diff --git a/drivers/media/video/gspca/gl860/gl860.h b/drivers/media/video/gspca/gl860/gl860.h new file mode 100644 index 000000000000..cef4e24c1e61 --- /dev/null +++ b/drivers/media/video/gspca/gl860/gl860.h @@ -0,0 +1,108 @@ +/* @file gl860.h + * @author Olivier LORIN, tiré du pilote Syntek par Nicolas VIVIEN + * @date 2009-08-27 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef GL860_DEV_H +#define GL860_DEV_H +#include + +#include "gspca.h" + +#define MODULE_NAME "gspca_gl860" +#define DRIVER_VERSION "0.9d10" + +#define ctrl_in gl860_RTx +#define ctrl_out gl860_RTx + +#define ID_MI1320 1 +#define ID_OV2640 2 +#define ID_OV9655 4 +#define ID_MI2020 8 +#define ID_MI2020b 16 + +#define _MI1320_ (((struct sd *) gspca_dev)->sensor == ID_MI1320) +#define _MI2020_ (((struct sd *) gspca_dev)->sensor == ID_MI2020) +#define _MI2020b_ (((struct sd *) gspca_dev)->sensor == ID_MI2020b) +#define _MI2020c_ 0 +#define _OV2640_ (((struct sd *) gspca_dev)->sensor == ID_OV2640) +#define _OV9655_ (((struct sd *) gspca_dev)->sensor == ID_OV9655) + +#define IMAGE_640 0 +#define IMAGE_800 1 +#define IMAGE_1280 2 +#define IMAGE_1600 3 + +struct sd_gl860 { + u16 backlight; + u16 brightness; + u16 sharpness; + u16 contrast; + u16 gamma; + u16 hue; + u16 saturation; + u16 whitebal; + u8 mirror; + u8 flip; + u8 AC50Hz; +}; + +/* Specific webcam descriptor */ +struct sd { + struct gspca_dev gspca_dev; /* !! must be the first item */ + + struct sd_gl860 vcur; + struct sd_gl860 vold; + struct sd_gl860 vmax; + + int (*dev_configure_alt) (struct gspca_dev *); + int (*dev_init_at_startup)(struct gspca_dev *); + int (*dev_init_pre_alt) (struct gspca_dev *); + void (*dev_post_unset_alt) (struct gspca_dev *); + int (*dev_camera_settings)(struct gspca_dev *); + + u8 swapRB; + u8 mirrorMask; + u8 sensor; + s32 nbIm; + s32 nbRightUp; + u8 waitSet; +}; + +struct validx { + u16 val; + u16 idx; +}; + +struct idxdata { + u8 idx; + u8 data[3]; +}; + +int fetch_validx(struct gspca_dev *gspca_dev, struct validx *tbl, int len); +int keep_on_fetching_validx(struct gspca_dev *gspca_dev, struct validx *tbl, + int len, int n); +void fetch_idxdata(struct gspca_dev *gspca_dev, struct idxdata *tbl, int len); + +int gl860_RTx(struct gspca_dev *gspca_dev, + unsigned char pref, u32 req, u16 val, u16 index, + s32 len, void *pdata); + +void mi1320_init_settings(struct gspca_dev *); +void ov2640_init_settings(struct gspca_dev *); +void ov9655_init_settings(struct gspca_dev *); +void mi2020_init_settings(struct gspca_dev *); + +#endif diff --git a/drivers/media/video/gspca/jeilinj.c b/drivers/media/video/gspca/jeilinj.c index dbfa3ed6e8ef..a11c97ebeb0f 100644 --- a/drivers/media/video/gspca/jeilinj.c +++ b/drivers/media/video/gspca/jeilinj.c @@ -312,6 +312,8 @@ static int sd_start(struct gspca_dev *gspca_dev) /* create the JPEG header */ dev->jpeg_hdr = kmalloc(JPEG_HDR_SZ, GFP_KERNEL); + if (dev->jpeg_hdr == NULL) + return -ENOMEM; jpeg_define(dev->jpeg_hdr, gspca_dev->height, gspca_dev->width, 0x21); /* JPEG 422 */ jpeg_set_qual(dev->jpeg_hdr, dev->quality); diff --git a/drivers/media/video/gspca/m5602/m5602_ov7660.c b/drivers/media/video/gspca/m5602/m5602_ov7660.c index 7aafeb7cfa07..2a28b74cb3f9 100644 --- a/drivers/media/video/gspca/m5602/m5602_ov7660.c +++ b/drivers/media/video/gspca/m5602/m5602_ov7660.c @@ -20,6 +20,18 @@ static int ov7660_get_gain(struct gspca_dev *gspca_dev, __s32 *val); static int ov7660_set_gain(struct gspca_dev *gspca_dev, __s32 val); +static int ov7660_get_auto_white_balance(struct gspca_dev *gspca_dev, + __s32 *val); +static int ov7660_set_auto_white_balance(struct gspca_dev *gspca_dev, + __s32 val); +static int ov7660_get_auto_gain(struct gspca_dev *gspca_dev, __s32 *val); +static int ov7660_set_auto_gain(struct gspca_dev *gspca_dev, __s32 val); +static int ov7660_get_auto_exposure(struct gspca_dev *gspca_dev, __s32 *val); +static int ov7660_set_auto_exposure(struct gspca_dev *gspca_dev, __s32 val); +static int ov7660_get_hflip(struct gspca_dev *gspca_dev, __s32 *val); +static int ov7660_set_hflip(struct gspca_dev *gspca_dev, __s32 val); +static int ov7660_get_vflip(struct gspca_dev *gspca_dev, __s32 *val); +static int ov7660_set_vflip(struct gspca_dev *gspca_dev, __s32 val); const static struct ctrl ov7660_ctrls[] = { #define GAIN_IDX 1 @@ -37,6 +49,79 @@ const static struct ctrl ov7660_ctrls[] = { .set = ov7660_set_gain, .get = ov7660_get_gain }, +#define BLUE_BALANCE_IDX 2 +#define RED_BALANCE_IDX 3 +#define AUTO_WHITE_BALANCE_IDX 4 + { + { + .id = V4L2_CID_AUTO_WHITE_BALANCE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "auto white balance", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 1 + }, + .set = ov7660_set_auto_white_balance, + .get = ov7660_get_auto_white_balance + }, +#define AUTO_GAIN_CTRL_IDX 5 + { + { + .id = V4L2_CID_AUTOGAIN, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "auto gain control", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 1 + }, + .set = ov7660_set_auto_gain, + .get = ov7660_get_auto_gain + }, +#define AUTO_EXPOSURE_IDX 6 + { + { + .id = V4L2_CID_EXPOSURE_AUTO, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "auto exposure", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 1 + }, + .set = ov7660_set_auto_exposure, + .get = ov7660_get_auto_exposure + }, +#define HFLIP_IDX 7 + { + { + .id = V4L2_CID_HFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "horizontal flip", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0 + }, + .set = ov7660_set_hflip, + .get = ov7660_get_hflip + }, +#define VFLIP_IDX 8 + { + { + .id = V4L2_CID_VFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "vertical flip", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0 + }, + .set = ov7660_set_vflip, + .get = ov7660_get_vflip + }, + }; static struct v4l2_pix_format ov7660_modes[] = { @@ -137,7 +222,7 @@ int ov7660_init(struct sd *sd) } else { data[0] = init_ov7660[i][2]; err = m5602_write_sensor(sd, - init_ov7660[i][1], data, 1); + init_ov7660[i][1], data, 1); } } @@ -148,6 +233,28 @@ int ov7660_init(struct sd *sd) if (err < 0) return err; + err = ov7660_set_auto_white_balance(&sd->gspca_dev, + sensor_settings[AUTO_WHITE_BALANCE_IDX]); + if (err < 0) + return err; + + err = ov7660_set_auto_gain(&sd->gspca_dev, + sensor_settings[AUTO_GAIN_CTRL_IDX]); + if (err < 0) + return err; + + err = ov7660_set_auto_exposure(&sd->gspca_dev, + sensor_settings[AUTO_EXPOSURE_IDX]); + if (err < 0) + return err; + err = ov7660_set_hflip(&sd->gspca_dev, + sensor_settings[HFLIP_IDX]); + if (err < 0) + return err; + + err = ov7660_set_vflip(&sd->gspca_dev, + sensor_settings[VFLIP_IDX]); + return err; } @@ -194,6 +301,159 @@ static int ov7660_set_gain(struct gspca_dev *gspca_dev, __s32 val) return err; } + +static int ov7660_get_auto_white_balance(struct gspca_dev *gspca_dev, + __s32 *val) +{ + struct sd *sd = (struct sd *) gspca_dev; + s32 *sensor_settings = sd->sensor_priv; + + *val = sensor_settings[AUTO_WHITE_BALANCE_IDX]; + return 0; +} + +static int ov7660_set_auto_white_balance(struct gspca_dev *gspca_dev, + __s32 val) +{ + int err; + u8 i2c_data; + struct sd *sd = (struct sd *) gspca_dev; + s32 *sensor_settings = sd->sensor_priv; + + PDEBUG(D_V4L2, "Set auto white balance to %d", val); + + sensor_settings[AUTO_WHITE_BALANCE_IDX] = val; + err = m5602_read_sensor(sd, OV7660_COM8, &i2c_data, 1); + if (err < 0) + return err; + + i2c_data = ((i2c_data & 0xfd) | ((val & 0x01) << 1)); + err = m5602_write_sensor(sd, OV7660_COM8, &i2c_data, 1); + + return err; +} + +static int ov7660_get_auto_gain(struct gspca_dev *gspca_dev, __s32 *val) +{ + struct sd *sd = (struct sd *) gspca_dev; + s32 *sensor_settings = sd->sensor_priv; + + *val = sensor_settings[AUTO_GAIN_CTRL_IDX]; + PDEBUG(D_V4L2, "Read auto gain control %d", *val); + return 0; +} + +static int ov7660_set_auto_gain(struct gspca_dev *gspca_dev, __s32 val) +{ + int err; + u8 i2c_data; + struct sd *sd = (struct sd *) gspca_dev; + s32 *sensor_settings = sd->sensor_priv; + + PDEBUG(D_V4L2, "Set auto gain control to %d", val); + + sensor_settings[AUTO_GAIN_CTRL_IDX] = val; + err = m5602_read_sensor(sd, OV7660_COM8, &i2c_data, 1); + if (err < 0) + return err; + + i2c_data = ((i2c_data & 0xfb) | ((val & 0x01) << 2)); + + return m5602_write_sensor(sd, OV7660_COM8, &i2c_data, 1); +} + +static int ov7660_get_auto_exposure(struct gspca_dev *gspca_dev, __s32 *val) +{ + struct sd *sd = (struct sd *) gspca_dev; + s32 *sensor_settings = sd->sensor_priv; + + *val = sensor_settings[AUTO_EXPOSURE_IDX]; + PDEBUG(D_V4L2, "Read auto exposure control %d", *val); + return 0; +} + +static int ov7660_set_auto_exposure(struct gspca_dev *gspca_dev, + __s32 val) +{ + int err; + u8 i2c_data; + struct sd *sd = (struct sd *) gspca_dev; + s32 *sensor_settings = sd->sensor_priv; + + PDEBUG(D_V4L2, "Set auto exposure control to %d", val); + + sensor_settings[AUTO_EXPOSURE_IDX] = val; + err = m5602_read_sensor(sd, OV7660_COM8, &i2c_data, 1); + if (err < 0) + return err; + + i2c_data = ((i2c_data & 0xfe) | ((val & 0x01) << 0)); + + return m5602_write_sensor(sd, OV7660_COM8, &i2c_data, 1); +} + +static int ov7660_get_hflip(struct gspca_dev *gspca_dev, __s32 *val) +{ + struct sd *sd = (struct sd *) gspca_dev; + s32 *sensor_settings = sd->sensor_priv; + + *val = sensor_settings[HFLIP_IDX]; + PDEBUG(D_V4L2, "Read horizontal flip %d", *val); + return 0; +} + +static int ov7660_set_hflip(struct gspca_dev *gspca_dev, __s32 val) +{ + int err; + u8 i2c_data; + struct sd *sd = (struct sd *) gspca_dev; + s32 *sensor_settings = sd->sensor_priv; + + PDEBUG(D_V4L2, "Set horizontal flip to %d", val); + + sensor_settings[HFLIP_IDX] = val; + + i2c_data = ((val & 0x01) << 5) | + (sensor_settings[VFLIP_IDX] << 4); + + err = m5602_write_sensor(sd, OV7660_MVFP, &i2c_data, 1); + + return err; +} + +static int ov7660_get_vflip(struct gspca_dev *gspca_dev, __s32 *val) +{ + struct sd *sd = (struct sd *) gspca_dev; + s32 *sensor_settings = sd->sensor_priv; + + *val = sensor_settings[VFLIP_IDX]; + PDEBUG(D_V4L2, "Read vertical flip %d", *val); + + return 0; +} + +static int ov7660_set_vflip(struct gspca_dev *gspca_dev, __s32 val) +{ + int err; + u8 i2c_data; + struct sd *sd = (struct sd *) gspca_dev; + s32 *sensor_settings = sd->sensor_priv; + + PDEBUG(D_V4L2, "Set vertical flip to %d", val); + sensor_settings[VFLIP_IDX] = val; + + i2c_data = ((val & 0x01) << 4) | (sensor_settings[VFLIP_IDX] << 5); + err = m5602_write_sensor(sd, OV7660_MVFP, &i2c_data, 1); + if (err < 0) + return err; + + /* When vflip is toggled we need to readjust the bridge hsync/vsync */ + if (gspca_dev->streaming) + err = ov7660_start(sd); + + return err; +} + static void ov7660_dump_registers(struct sd *sd) { int address; diff --git a/drivers/media/video/gspca/m5602/m5602_ov7660.h b/drivers/media/video/gspca/m5602/m5602_ov7660.h index 3f2c169a93ea..f5588ebe667c 100644 --- a/drivers/media/video/gspca/m5602/m5602_ov7660.h +++ b/drivers/media/video/gspca/m5602/m5602_ov7660.h @@ -66,23 +66,23 @@ #define OV7660_RBIAS 0x2c #define OV7660_HREF 0x32 #define OV7660_ADC 0x37 -#define OV7660_OFON 0x39 -#define OV7660_TSLB 0x3a -#define OV7660_COM12 0x3c -#define OV7660_COM13 0x3d +#define OV7660_OFON 0x39 +#define OV7660_TSLB 0x3a +#define OV7660_COM12 0x3c +#define OV7660_COM13 0x3d #define OV7660_LCC1 0x62 #define OV7660_LCC2 0x63 #define OV7660_LCC3 0x64 #define OV7660_LCC4 0x65 #define OV7660_LCC5 0x66 -#define OV7660_HV 0x69 -#define OV7660_RSVDA1 0xa1 +#define OV7660_HV 0x69 +#define OV7660_RSVDA1 0xa1 #define OV7660_DEFAULT_GAIN 0x0e -#define OV7660_DEFAULT_RED_GAIN 0x80 +#define OV7660_DEFAULT_RED_GAIN 0x80 #define OV7660_DEFAULT_BLUE_GAIN 0x80 #define OV7660_DEFAULT_SATURATION 0x00 -#define OV7660_DEFAULT_EXPOSURE 0x20 +#define OV7660_DEFAULT_EXPOSURE 0x20 /* Kernel module parameters */ extern int force_sensor; @@ -149,45 +149,8 @@ static const unsigned char init_ov7660[][4] = {BRIDGE, M5602_XB_ADC_CTRL, 0xc0}, {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0d}, {BRIDGE, M5602_XB_SENSOR_CTRL, 0x00}, - {BRIDGE, M5602_XB_GPIO_DIR, 0x03}, - {BRIDGE, M5602_XB_GPIO_DIR, 0x03}, - {BRIDGE, M5602_XB_ADC_CTRL, 0xc0}, - {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c}, - - {SENSOR, OV7660_OFON, 0x0c}, - {SENSOR, OV7660_COM2, 0x11}, - {SENSOR, OV7660_COM7, 0x05}, - {BRIDGE, M5602_XB_GPIO_DIR, 0x01}, - {BRIDGE, M5602_XB_GPIO_DAT, 0x04}, - {BRIDGE, M5602_XB_GPIO_EN_H, 0x06}, - {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06}, - {BRIDGE, M5602_XB_GPIO_DAT_H, 0x00}, - {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x08}, - {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0}, - {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00}, - {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0}, - {BRIDGE, M5602_XB_ADC_CTRL, 0xc0}, - {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c}, - {BRIDGE, M5602_XB_GPIO_DIR, 0x05}, - {BRIDGE, M5602_XB_GPIO_DAT, 0x00}, - {BRIDGE, M5602_XB_GPIO_EN_H, 0x06}, - {BRIDGE, M5602_XB_GPIO_EN_L, 0x00}, - - {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x02}, - {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0}, - - {SENSOR, OV7660_AECH, OV7660_DEFAULT_EXPOSURE}, - {SENSOR, OV7660_COM1, 0x00}, - {BRIDGE, M5602_XB_GPIO_DIR, 0x01}, - {BRIDGE, M5602_XB_GPIO_DAT, 0x04}, - {BRIDGE, M5602_XB_GPIO_EN_H, 0x06}, - {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06}, - {BRIDGE, M5602_XB_GPIO_DAT_H, 0x00}, - {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x08}, - {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0}, - {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00}, {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0}, {BRIDGE, M5602_XB_ADC_CTRL, 0xc0}, @@ -196,11 +159,8 @@ static const unsigned char init_ov7660[][4] = {BRIDGE, M5602_XB_GPIO_DAT, 0x00}, {BRIDGE, M5602_XB_GPIO_EN_H, 0x06}, {BRIDGE, M5602_XB_GPIO_EN_L, 0x00}, - {SENSOR, OV7660_COM7, 0x80}, {SENSOR, OV7660_CLKRC, 0x80}, - {SENSOR, OV7660_BLUE_GAIN, 0x80}, - {SENSOR, OV7660_RED_GAIN, 0x80}, {SENSOR, OV7660_COM9, 0x4c}, {SENSOR, OV7660_OFON, 0x43}, {SENSOR, OV7660_COM12, 0x28}, @@ -212,17 +172,17 @@ static const unsigned char init_ov7660[][4] = {SENSOR, OV7660_PSHFT, 0x0b}, {SENSOR, OV7660_VSTART, 0x01}, {SENSOR, OV7660_VSTOP, 0x7a}, - {SENSOR, OV7660_VREF, 0x00}, + {SENSOR, OV7660_VSTOP, 0x00}, {SENSOR, OV7660_COM7, 0x05}, - {SENSOR, OV7660_COM6, 0x4b}, - {SENSOR, OV7660_BBIAS, 0x98}, - {SENSOR, OV7660_GbBIAS, 0x98}, - {SENSOR, OV7660_RSVD29, 0x98}, - {SENSOR, OV7660_RBIAS, 0x98}, + {SENSOR, OV7660_COM6, 0x42}, + {SENSOR, OV7660_BBIAS, 0x94}, + {SENSOR, OV7660_GbBIAS, 0x94}, + {SENSOR, OV7660_RSVD29, 0x94}, + {SENSOR, OV7660_RBIAS, 0x94}, {SENSOR, OV7660_COM1, 0x00}, {SENSOR, OV7660_AECH, 0x00}, {SENSOR, OV7660_AECHH, 0x00}, - {SENSOR, OV7660_ADC, 0x04}, + {SENSOR, OV7660_ADC, 0x05}, {SENSOR, OV7660_COM13, 0x00}, {SENSOR, OV7660_RSVDA1, 0x23}, {SENSOR, OV7660_TSLB, 0x0d}, @@ -233,6 +193,47 @@ static const unsigned char init_ov7660[][4] = {SENSOR, OV7660_LCC4, 0x40}, {SENSOR, OV7660_LCC5, 0x01}, + {SENSOR, OV7660_AECH, 0x20}, + {SENSOR, OV7660_COM1, 0x00}, + {SENSOR, OV7660_OFON, 0x0c}, + {SENSOR, OV7660_COM2, 0x11}, + {SENSOR, OV7660_COM7, 0x05}, + {BRIDGE, M5602_XB_GPIO_DIR, 0x01}, + {BRIDGE, M5602_XB_GPIO_DAT, 0x04}, + {BRIDGE, M5602_XB_GPIO_EN_H, 0x06}, + {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06}, + {BRIDGE, M5602_XB_GPIO_DAT_H, 0x00}, + {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x08}, + {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0}, + {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00}, + {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0}, + {BRIDGE, M5602_XB_ADC_CTRL, 0xc0}, + {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c}, + {BRIDGE, M5602_XB_GPIO_DIR, 0x05}, + {BRIDGE, M5602_XB_GPIO_DAT, 0x00}, + {BRIDGE, M5602_XB_GPIO_EN_H, 0x06}, + {BRIDGE, M5602_XB_GPIO_EN_L, 0x00}, + {SENSOR, OV7660_AECH, 0x5f}, + {SENSOR, OV7660_COM1, 0x03}, + {SENSOR, OV7660_OFON, 0x0c}, + {SENSOR, OV7660_COM2, 0x11}, + {SENSOR, OV7660_COM7, 0x05}, + {BRIDGE, M5602_XB_GPIO_DIR, 0x01}, + {BRIDGE, M5602_XB_GPIO_DAT, 0x04}, + {BRIDGE, M5602_XB_GPIO_EN_H, 0x06}, + {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06}, + {BRIDGE, M5602_XB_GPIO_DAT_H, 0x00}, + {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x08}, + {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0}, + {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00}, + {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0}, + {BRIDGE, M5602_XB_ADC_CTRL, 0xc0}, + {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c}, + {BRIDGE, M5602_XB_GPIO_DIR, 0x05}, + {BRIDGE, M5602_XB_GPIO_DAT, 0x00}, + {BRIDGE, M5602_XB_GPIO_EN_H, 0x06}, + {BRIDGE, M5602_XB_GPIO_EN_L, 0x00}, + {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06}, {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0}, {BRIDGE, M5602_XB_ADC_CTRL, 0xc0}, @@ -245,35 +246,18 @@ static const unsigned char init_ov7660[][4] = {BRIDGE, M5602_XB_VSYNC_PARA, 0x00}, {BRIDGE, M5602_XB_VSYNC_PARA, 0x00}, {BRIDGE, M5602_XB_VSYNC_PARA, 0x01}, - {BRIDGE, M5602_XB_VSYNC_PARA, 0xe0}, /* 480 */ + {BRIDGE, M5602_XB_VSYNC_PARA, 0xec}, {BRIDGE, M5602_XB_VSYNC_PARA, 0x00}, {BRIDGE, M5602_XB_VSYNC_PARA, 0x00}, {BRIDGE, M5602_XB_SIG_INI, 0x00}, {BRIDGE, M5602_XB_SIG_INI, 0x02}, - {BRIDGE, M5602_XB_VSYNC_PARA, 0x00}, - {BRIDGE, M5602_XB_VSYNC_PARA, 0x27}, /* 39 */ - {BRIDGE, M5602_XB_VSYNC_PARA, 0x02}, - {BRIDGE, M5602_XB_VSYNC_PARA, 0xa7}, /* 679 */ + {BRIDGE, M5602_XB_HSYNC_PARA, 0x00}, + {BRIDGE, M5602_XB_HSYNC_PARA, 0x27}, + {BRIDGE, M5602_XB_HSYNC_PARA, 0x02}, + {BRIDGE, M5602_XB_HSYNC_PARA, 0xa7}, {BRIDGE, M5602_XB_SIG_INI, 0x00}, - {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00}, {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0}, - - {SENSOR, OV7660_AECH, 0x20}, - {SENSOR, OV7660_COM1, 0x00}, - {SENSOR, OV7660_OFON, 0x0c}, - {SENSOR, OV7660_COM2, 0x11}, - {SENSOR, OV7660_COM7, 0x05}, - {SENSOR, OV7660_BLUE_GAIN, 0x80}, - {SENSOR, OV7660_RED_GAIN, 0x80}, - - {BRIDGE, M5602_XB_GPIO_DIR, 0x01}, - {BRIDGE, M5602_XB_GPIO_DAT, 0x04}, - {BRIDGE, M5602_XB_GPIO_EN_H, 0x06}, - {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06}, - {BRIDGE, M5602_XB_GPIO_DAT_H, 0x00}, - {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x08}, - {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0} }; #endif diff --git a/drivers/media/video/gspca/m5602/m5602_s5k4aa.c b/drivers/media/video/gspca/m5602/m5602_s5k4aa.c index 0163903d1c0f..59400e858965 100644 --- a/drivers/media/video/gspca/m5602/m5602_s5k4aa.c +++ b/drivers/media/video/gspca/m5602/m5602_s5k4aa.c @@ -46,6 +46,12 @@ static DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"), DMI_MATCH(DMI_PRODUCT_NAME, "AMILO Xi 2550") } + }, { + .ident = "Fujitsu-Siemens Amilo Pa 2548", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"), + DMI_MATCH(DMI_PRODUCT_NAME, "AMILO Pa 2548") + } }, { .ident = "MSI GX700", .matches = { @@ -53,6 +59,13 @@ static DMI_MATCH(DMI_PRODUCT_NAME, "GX700"), DMI_MATCH(DMI_BIOS_DATE, "07/26/2007") } + }, { + .ident = "MSI GX700", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Micro-Star International"), + DMI_MATCH(DMI_PRODUCT_NAME, "GX700"), + DMI_MATCH(DMI_BIOS_DATE, "07/19/2007") + } }, { .ident = "MSI GX700/GX705/EX700", .matches = { diff --git a/drivers/media/video/gspca/stv06xx/stv06xx.c b/drivers/media/video/gspca/stv06xx/stv06xx.c index 7af511b5e9c2..65489d6b0d89 100644 --- a/drivers/media/video/gspca/stv06xx/stv06xx.c +++ b/drivers/media/video/gspca/stv06xx/stv06xx.c @@ -50,7 +50,6 @@ int stv06xx_write_bridge(struct sd *sd, u16 address, u16 i2c_data) 0x04, 0x40, address, 0, buf, len, STV06XX_URB_MSG_TIMEOUT); - PDEBUG(D_CONF, "Written 0x%x to address 0x%x, status: %d", i2c_data, address, err); @@ -69,7 +68,7 @@ int stv06xx_read_bridge(struct sd *sd, u16 address, u8 *i2c_data) *i2c_data = buf[0]; - PDEBUG(D_CONF, "Read 0x%x from address 0x%x, status %d", + PDEBUG(D_CONF, "Reading 0x%x from address 0x%x, status %d", *i2c_data, address, err); return (err < 0) ? err : 0; @@ -111,14 +110,14 @@ int stv06xx_write_sensor_bytes(struct sd *sd, const u8 *data, u8 len) struct usb_device *udev = sd->gspca_dev.dev; __u8 *buf = sd->gspca_dev.usb_buf; - PDEBUG(D_USBO, "I2C: Command buffer contains %d entries", len); + PDEBUG(D_CONF, "I2C: Command buffer contains %d entries", len); for (i = 0; i < len;) { /* Build the command buffer */ memset(buf, 0, I2C_BUFFER_LENGTH); for (j = 0; j < I2C_MAX_BYTES && i < len; j++, i++) { buf[j] = data[2*i]; buf[0x10 + j] = data[2*i+1]; - PDEBUG(D_USBO, "I2C: Writing 0x%02x to reg 0x%02x", + PDEBUG(D_CONF, "I2C: Writing 0x%02x to reg 0x%02x", data[2*i+1], data[2*i]); } buf[0x20] = sd->sensor->i2c_addr; @@ -128,8 +127,8 @@ int stv06xx_write_sensor_bytes(struct sd *sd, const u8 *data, u8 len) 0x04, 0x40, 0x0400, 0, buf, I2C_BUFFER_LENGTH, STV06XX_URB_MSG_TIMEOUT); - if (err < 0) - return err; + if (err < 0) + return err; } return stv06xx_write_sensor_finish(sd); } @@ -140,7 +139,7 @@ int stv06xx_write_sensor_words(struct sd *sd, const u16 *data, u8 len) struct usb_device *udev = sd->gspca_dev.dev; __u8 *buf = sd->gspca_dev.usb_buf; - PDEBUG(D_USBO, "I2C: Command buffer contains %d entries", len); + PDEBUG(D_CONF, "I2C: Command buffer contains %d entries", len); for (i = 0; i < len;) { /* Build the command buffer */ @@ -149,7 +148,7 @@ int stv06xx_write_sensor_words(struct sd *sd, const u16 *data, u8 len) buf[j] = data[2*i]; buf[0x10 + j * 2] = data[2*i+1]; buf[0x10 + j * 2 + 1] = data[2*i+1] >> 8; - PDEBUG(D_USBO, "I2C: Writing 0x%04x to reg 0x%02x", + PDEBUG(D_CONF, "I2C: Writing 0x%04x to reg 0x%02x", data[2*i+1], data[2*i]); } buf[0x20] = sd->sensor->i2c_addr; @@ -189,7 +188,7 @@ int stv06xx_read_sensor(struct sd *sd, const u8 address, u16 *value) 0x04, 0x40, 0x1400, 0, buf, I2C_BUFFER_LENGTH, STV06XX_URB_MSG_TIMEOUT); if (err < 0) { - PDEBUG(D_ERR, "I2C Read: error writing address: %d", err); + PDEBUG(D_ERR, "I2C: Read error writing address: %d", err); return err; } @@ -201,7 +200,7 @@ int stv06xx_read_sensor(struct sd *sd, const u8 address, u16 *value) else *value = buf[0]; - PDEBUG(D_USBO, "I2C: Read 0x%x from address 0x%x, status: %d", + PDEBUG(D_CONF, "I2C: Read 0x%x from address 0x%x, status: %d", *value, address, err); return (err < 0) ? err : 0; diff --git a/drivers/media/video/gspca/stv06xx/stv06xx_hdcs.c b/drivers/media/video/gspca/stv06xx/stv06xx_hdcs.c index e5024c8496ef..706e08dc5254 100644 --- a/drivers/media/video/gspca/stv06xx/stv06xx_hdcs.c +++ b/drivers/media/video/gspca/stv06xx/stv06xx_hdcs.c @@ -37,7 +37,7 @@ static const struct ctrl hdcs1x00_ctrl[] = { .type = V4L2_CTRL_TYPE_INTEGER, .name = "exposure", .minimum = 0x00, - .maximum = 0xffff, + .maximum = 0xff, .step = 0x1, .default_value = HDCS_DEFAULT_EXPOSURE, .flags = V4L2_CTRL_FLAG_SLIDER @@ -74,7 +74,35 @@ static struct v4l2_pix_format hdcs1x00_mode[] = { } }; -static const struct ctrl hdcs1020_ctrl[] = {}; +static const struct ctrl hdcs1020_ctrl[] = { + { + { + .id = V4L2_CID_EXPOSURE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .minimum = 0x00, + .maximum = 0xffff, + .step = 0x1, + .default_value = HDCS_DEFAULT_EXPOSURE, + .flags = V4L2_CTRL_FLAG_SLIDER + }, + .set = hdcs_set_exposure, + .get = hdcs_get_exposure + }, { + { + .id = V4L2_CID_GAIN, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "gain", + .minimum = 0x00, + .maximum = 0xff, + .step = 0x1, + .default_value = HDCS_DEFAULT_GAIN, + .flags = V4L2_CTRL_FLAG_SLIDER + }, + .set = hdcs_set_gain, + .get = hdcs_get_gain + } +}; static struct v4l2_pix_format hdcs1020_mode[] = { { @@ -120,6 +148,7 @@ struct hdcs { } exp; int psmp; + u8 exp_cache, gain_cache; }; static int hdcs_reg_write_seq(struct sd *sd, u8 reg, u8 *vals, u8 len) @@ -205,34 +234,8 @@ static int hdcs_get_exposure(struct gspca_dev *gspca_dev, __s32 *val) struct sd *sd = (struct sd *) gspca_dev; struct hdcs *hdcs = sd->sensor_priv; - /* Column time period */ - int ct; - /* Column processing period */ - int cp; - /* Row processing period */ - int rp; - int cycles; - int err; - int rowexp; - u16 data[2]; - - err = stv06xx_read_sensor(sd, HDCS_ROWEXPL, &data[0]); - if (err < 0) - return err; - - err = stv06xx_read_sensor(sd, HDCS_ROWEXPH, &data[1]); - if (err < 0) - return err; - - rowexp = (data[1] << 8) | data[0]; - - ct = hdcs->exp.cto + hdcs->psmp + (HDCS_ADC_START_SIG_DUR + 2); - cp = hdcs->exp.cto + (hdcs->w * ct / 2); - rp = hdcs->exp.rs + cp; + *val = hdcs->exp_cache; - cycles = rp * rowexp; - *val = cycles / HDCS_CLK_FREQ_MHZ; - PDEBUG(D_V4L2, "Read exposure %d", *val); return 0; } @@ -252,9 +255,12 @@ static int hdcs_set_exposure(struct gspca_dev *gspca_dev, __s32 val) within the column processing period */ int mnct; int cycles, err; - u8 exp[4]; + u8 exp[14]; - cycles = val * HDCS_CLK_FREQ_MHZ; + val &= 0xff; + hdcs->exp_cache = val; + + cycles = val * HDCS_CLK_FREQ_MHZ * 257; ct = hdcs->exp.cto + hdcs->psmp + (HDCS_ADC_START_SIG_DUR + 2); cp = hdcs->exp.cto + (hdcs->w * ct / 2); @@ -288,73 +294,79 @@ static int hdcs_set_exposure(struct gspca_dev *gspca_dev, __s32 val) srowexp = max_srowexp; if (IS_1020(sd)) { - exp[0] = rowexp & 0xff; - exp[1] = rowexp >> 8; - exp[2] = (srowexp >> 2) & 0xff; - /* this clears exposure error flag */ - exp[3] = 0x1; - err = hdcs_reg_write_seq(sd, HDCS_ROWEXPL, exp, 4); + exp[0] = HDCS20_CONTROL; + exp[1] = 0x00; /* Stop streaming */ + exp[2] = HDCS_ROWEXPL; + exp[3] = rowexp & 0xff; + exp[4] = HDCS_ROWEXPH; + exp[5] = rowexp >> 8; + exp[6] = HDCS20_SROWEXP; + exp[7] = (srowexp >> 2) & 0xff; + exp[8] = HDCS20_ERROR; + exp[9] = 0x10; /* Clear exposure error flag*/ + exp[10] = HDCS20_CONTROL; + exp[11] = 0x04; /* Restart streaming */ + err = stv06xx_write_sensor_bytes(sd, exp, 6); } else { - exp[0] = rowexp & 0xff; - exp[1] = rowexp >> 8; - exp[2] = srowexp & 0xff; - exp[3] = srowexp >> 8; - err = hdcs_reg_write_seq(sd, HDCS_ROWEXPL, exp, 4); + exp[0] = HDCS00_CONTROL; + exp[1] = 0x00; /* Stop streaming */ + exp[2] = HDCS_ROWEXPL; + exp[3] = rowexp & 0xff; + exp[4] = HDCS_ROWEXPH; + exp[5] = rowexp >> 8; + exp[6] = HDCS00_SROWEXPL; + exp[7] = srowexp & 0xff; + exp[8] = HDCS00_SROWEXPH; + exp[9] = srowexp >> 8; + exp[10] = HDCS_STATUS; + exp[11] = 0x10; /* Clear exposure error flag*/ + exp[12] = HDCS00_CONTROL; + exp[13] = 0x04; /* Restart streaming */ + err = stv06xx_write_sensor_bytes(sd, exp, 7); if (err < 0) return err; - - /* clear exposure error flag */ - err = stv06xx_write_sensor(sd, - HDCS_STATUS, BIT(4)); } PDEBUG(D_V4L2, "Writing exposure %d, rowexp %d, srowexp %d", val, rowexp, srowexp); return err; } -static int hdcs_set_gains(struct sd *sd, u8 r, u8 g, u8 b) +static int hdcs_set_gains(struct sd *sd, u8 g) { + struct hdcs *hdcs = sd->sensor_priv; + int err; u8 gains[4]; + hdcs->gain_cache = g; + /* the voltage gain Av = (1 + 19 * val / 127) * (1 + bit7) */ - if (r > 127) - r = 0x80 | (r / 2); if (g > 127) g = 0x80 | (g / 2); - if (b > 127) - b = 0x80 | (b / 2); gains[0] = g; - gains[1] = r; - gains[2] = b; + gains[1] = g; + gains[2] = g; gains[3] = g; - return hdcs_reg_write_seq(sd, HDCS_ERECPGA, gains, 4); + err = hdcs_reg_write_seq(sd, HDCS_ERECPGA, gains, 4); + return err; } static int hdcs_get_gain(struct gspca_dev *gspca_dev, __s32 *val) { struct sd *sd = (struct sd *) gspca_dev; - int err; - u16 data; - - err = stv06xx_read_sensor(sd, HDCS_ERECPGA, &data); + struct hdcs *hdcs = sd->sensor_priv; - /* Bit 7 doubles the gain */ - if (data & 0x80) - *val = (data & 0x7f) * 2; - else - *val = data; + *val = hdcs->gain_cache; - PDEBUG(D_V4L2, "Read gain %d", *val); - return err; + return 0; } static int hdcs_set_gain(struct gspca_dev *gspca_dev, __s32 val) { PDEBUG(D_V4L2, "Writing gain %d", val); return hdcs_set_gains((struct sd *) gspca_dev, - val & 0xff, val & 0xff, val & 0xff); + val & 0xff); } static int hdcs_set_size(struct sd *sd, @@ -572,16 +584,15 @@ static int hdcs_init(struct sd *sd) if (err < 0) return err; - err = hdcs_set_gains(sd, HDCS_DEFAULT_GAIN, HDCS_DEFAULT_GAIN, - HDCS_DEFAULT_GAIN); + err = hdcs_set_gains(sd, HDCS_DEFAULT_GAIN); if (err < 0) return err; - err = hdcs_set_exposure(&sd->gspca_dev, HDCS_DEFAULT_EXPOSURE); + err = hdcs_set_size(sd, hdcs->array.width, hdcs->array.height); if (err < 0) return err; - err = hdcs_set_size(sd, hdcs->array.width, hdcs->array.height); + err = hdcs_set_exposure(&sd->gspca_dev, HDCS_DEFAULT_EXPOSURE); return err; } diff --git a/drivers/media/video/gspca/stv06xx/stv06xx_hdcs.h b/drivers/media/video/gspca/stv06xx/stv06xx_hdcs.h index 412f06cf3d5c..37b31c99d956 100644 --- a/drivers/media/video/gspca/stv06xx/stv06xx_hdcs.h +++ b/drivers/media/video/gspca/stv06xx/stv06xx_hdcs.h @@ -124,7 +124,7 @@ #define HDCS_RUN_ENABLE (1 << 2) #define HDCS_SLEEP_MODE (1 << 1) -#define HDCS_DEFAULT_EXPOSURE 5000 +#define HDCS_DEFAULT_EXPOSURE 48 #define HDCS_DEFAULT_GAIN 128 static int hdcs_probe_1x00(struct sd *sd); diff --git a/drivers/media/video/gspca/stv06xx/stv06xx_st6422.c b/drivers/media/video/gspca/stv06xx/stv06xx_st6422.c index 87cb5b9ddfa7..c11f06e4ae76 100644 --- a/drivers/media/video/gspca/stv06xx/stv06xx_st6422.c +++ b/drivers/media/video/gspca/stv06xx/stv06xx_st6422.c @@ -166,7 +166,7 @@ static int st6422_init(struct sd *sd) /* 10 compressed? */ { 0x1439, 0x00 }, -/* antiflimmer?? 0xa2 ger perfekt bild mot monitor */ +/* anti-noise? 0xa2 gives a perfect image */ { 0x143b, 0x05 }, { 0x143c, 0x00 }, /* 0x00-0x01 - ??? */ @@ -197,15 +197,14 @@ static int st6422_init(struct sd *sd) { 0x1500, 0x50 }, /* 0x00 - 0xFF 0x80 == compr ? */ { 0x1501, 0xaf }, -/* high val-> ljus area blir morkare. */ -/* low val -> ljus area blir ljusare. */ +/* high val-> light area gets darker */ +/* low val -> light area gets lighter */ { 0x1502, 0xc2 }, -/* high val-> ljus area blir morkare. */ -/* low val -> ljus area blir ljusare. */ +/* high val-> light area gets darker */ +/* low val -> light area gets lighter */ { 0x1503, 0x45 }, -/* high val-> ljus area blir morkare. */ -/* low val -> ljus area blir ljusare. */ - +/* high val-> light area gets darker */ +/* low val -> light area gets lighter */ { 0x1505, 0x02 }, /* 2 : 324x248 80352 bytes */ /* 7 : 248x162 40176 bytes */ diff --git a/drivers/media/video/gspca/vc032x.c b/drivers/media/video/gspca/vc032x.c index 619250e70718..589042f6adbe 100644 --- a/drivers/media/video/gspca/vc032x.c +++ b/drivers/media/video/gspca/vc032x.c @@ -2946,7 +2946,8 @@ static int sd_start(struct gspca_dev *gspca_dev) reg_w(gspca_dev->dev, 0x89, 0x058c, 0x0000); break; default: - reg_w(gspca_dev->dev, 0x89, 0xffff, 0xfdff); + if (!(sd->flags & FL_SAMSUNG)) + reg_w(gspca_dev->dev, 0x89, 0xffff, 0xfdff); break; } msleep(100); @@ -2964,7 +2965,7 @@ static void sd_stopN(struct gspca_dev *gspca_dev) if (sd->sensor == SENSOR_MI1310_SOC) reg_w(dev, 0x89, 0x058c, 0x00ff); - else + else if (!(sd->flags & FL_SAMSUNG)) reg_w(dev, 0x89, 0xffff, 0xffff); reg_w(dev, 0xa0, 0x01, 0xb301); reg_w(dev, 0xa0, 0x09, 0xb003); @@ -2981,7 +2982,7 @@ static void sd_stop0(struct gspca_dev *gspca_dev) /*fixme: is this useful?*/ if (sd->sensor == SENSOR_MI1310_SOC) reg_w(dev, 0x89, 0x058c, 0x00ff); - else + else if (!(sd->flags & FL_SAMSUNG)) reg_w(dev, 0x89, 0xffff, 0xffff); } diff --git a/drivers/media/video/ivtv/ivtv-driver.c b/drivers/media/video/ivtv/ivtv-driver.c index 63ea0fb66063..463ec3457d7b 100644 --- a/drivers/media/video/ivtv/ivtv-driver.c +++ b/drivers/media/video/ivtv/ivtv-driver.c @@ -246,7 +246,7 @@ MODULE_PARM_DESC(newi2c, "\t\t\t-1 is autodetect, 0 is off, 1 is on\n" "\t\t\tDefault is autodetect"); -MODULE_PARM_DESC(ivtv_first_minor, "Set kernel number assigned to first card"); +MODULE_PARM_DESC(ivtv_first_minor, "Set device node number assigned to first card"); MODULE_AUTHOR("Kevin Thayer, Chris Kennedy, Hans Verkuil"); MODULE_DESCRIPTION("CX23415/CX23416 driver"); diff --git a/drivers/media/video/ivtv/ivtv-i2c.c b/drivers/media/video/ivtv/ivtv-i2c.c index 8f15a31d3f66..b9c71e61f7d6 100644 --- a/drivers/media/video/ivtv/ivtv-i2c.c +++ b/drivers/media/video/ivtv/ivtv-i2c.c @@ -161,19 +161,19 @@ int ivtv_i2c_register(struct ivtv *itv, unsigned idx) return -1; if (hw == IVTV_HW_TUNER) { /* special tuner handling */ - sd = v4l2_i2c_new_probed_subdev(&itv->v4l2_dev, + sd = v4l2_i2c_new_subdev(&itv->v4l2_dev, adap, mod, type, - itv->card_i2c->radio); + 0, itv->card_i2c->radio); if (sd) sd->grp_id = 1 << idx; - sd = v4l2_i2c_new_probed_subdev(&itv->v4l2_dev, + sd = v4l2_i2c_new_subdev(&itv->v4l2_dev, adap, mod, type, - itv->card_i2c->demod); + 0, itv->card_i2c->demod); if (sd) sd->grp_id = 1 << idx; - sd = v4l2_i2c_new_probed_subdev(&itv->v4l2_dev, + sd = v4l2_i2c_new_subdev(&itv->v4l2_dev, adap, mod, type, - itv->card_i2c->tv); + 0, itv->card_i2c->tv); if (sd) sd->grp_id = 1 << idx; return sd ? 0 : -1; @@ -181,11 +181,11 @@ int ivtv_i2c_register(struct ivtv *itv, unsigned idx) if (!hw_addrs[idx]) return -1; if (hw == IVTV_HW_UPD64031A || hw == IVTV_HW_UPD6408X) { - sd = v4l2_i2c_new_probed_subdev_addr(&itv->v4l2_dev, - adap, mod, type, hw_addrs[idx]); + sd = v4l2_i2c_new_subdev(&itv->v4l2_dev, + adap, mod, type, 0, I2C_ADDRS(hw_addrs[idx])); } else { sd = v4l2_i2c_new_subdev(&itv->v4l2_dev, - adap, mod, type, hw_addrs[idx]); + adap, mod, type, hw_addrs[idx], NULL); } if (sd) sd->grp_id = 1 << idx; diff --git a/drivers/media/video/ivtv/ivtv-streams.c b/drivers/media/video/ivtv/ivtv-streams.c index 15da01710efc..67699e3f2aaa 100644 --- a/drivers/media/video/ivtv/ivtv-streams.c +++ b/drivers/media/video/ivtv/ivtv-streams.c @@ -261,8 +261,8 @@ static int ivtv_reg_dev(struct ivtv *itv, int type) video_set_drvdata(s->vdev, s); /* Register device. First try the desired minor, then any free one. */ - if (video_register_device(s->vdev, vfl_type, num)) { - IVTV_ERR("Couldn't register v4l2 device for %s kernel number %d\n", + if (video_register_device_no_warn(s->vdev, vfl_type, num)) { + IVTV_ERR("Couldn't register v4l2 device for %s (device node number %d)\n", s->name, num); video_device_release(s->vdev); s->vdev = NULL; diff --git a/drivers/media/video/mt9m001.c b/drivers/media/video/mt9m001.c index 4d794b42d6cd..45388d2ce2fd 100644 --- a/drivers/media/video/mt9m001.c +++ b/drivers/media/video/mt9m001.c @@ -13,13 +13,13 @@ #include #include -#include +#include #include #include /* mt9m001 i2c address 0x5d - * The platform has to define i2c_board_info - * and call i2c_register_board_info() */ + * The platform has to define ctruct i2c_board_info objects and link to them + * from struct soc_camera_link */ /* mt9m001 selected register addresses */ #define MT9M001_CHIP_VERSION 0x00 @@ -39,6 +39,13 @@ #define MT9M001_GLOBAL_GAIN 0x35 #define MT9M001_CHIP_ENABLE 0xF1 +#define MT9M001_MAX_WIDTH 1280 +#define MT9M001_MAX_HEIGHT 1024 +#define MT9M001_MIN_WIDTH 48 +#define MT9M001_MIN_HEIGHT 32 +#define MT9M001_COLUMN_SKIP 20 +#define MT9M001_ROW_SKIP 12 + static const struct soc_camera_data_format mt9m001_colour_formats[] = { /* Order important: first natively supported, * second supported with a GPIO extender */ @@ -69,12 +76,20 @@ static const struct soc_camera_data_format mt9m001_monochrome_formats[] = { }; struct mt9m001 { - struct i2c_client *client; - struct soc_camera_device icd; + struct v4l2_subdev subdev; + struct v4l2_rect rect; /* Sensor window */ + __u32 fourcc; int model; /* V4L2_IDENT_MT9M001* codes from v4l2-chip-ident.h */ + unsigned int gain; + unsigned int exposure; unsigned char autoexposure; }; +static struct mt9m001 *to_mt9m001(const struct i2c_client *client) +{ + return container_of(i2c_get_clientdata(client), struct mt9m001, subdev); +} + static int reg_read(struct i2c_client *client, const u8 reg) { s32 data = i2c_smbus_read_word_data(client, reg); @@ -109,35 +124,20 @@ static int reg_clear(struct i2c_client *client, const u8 reg, return reg_write(client, reg, ret & ~data); } -static int mt9m001_init(struct soc_camera_device *icd) +static int mt9m001_init(struct i2c_client *client) { - struct i2c_client *client = to_i2c_client(icd->control); - struct soc_camera_link *icl = client->dev.platform_data; int ret; - dev_dbg(icd->vdev->parent, "%s\n", __func__); + dev_dbg(&client->dev, "%s\n", __func__); - if (icl->power) { - ret = icl->power(&client->dev, 1); - if (ret < 0) { - dev_err(icd->vdev->parent, - "Platform failed to power-on the camera.\n"); - return ret; - } - } - - /* The camera could have been already on, we reset it additionally */ - if (icl->reset) - ret = icl->reset(&client->dev); - else - ret = -ENODEV; + /* + * We don't know, whether platform provides reset, issue a soft reset + * too. This returns all registers to their default values. + */ + ret = reg_write(client, MT9M001_RESET, 1); + if (!ret) + ret = reg_write(client, MT9M001_RESET, 0); - if (ret < 0) { - /* Either no platform reset, or platform reset failed */ - ret = reg_write(client, MT9M001_RESET, 1); - if (!ret) - ret = reg_write(client, MT9M001_RESET, 0); - } /* Disable chip, synchronous option update */ if (!ret) ret = reg_write(client, MT9M001_OUTPUT_CONTROL, 0); @@ -145,36 +145,12 @@ static int mt9m001_init(struct soc_camera_device *icd) return ret; } -static int mt9m001_release(struct soc_camera_device *icd) +static int mt9m001_s_stream(struct v4l2_subdev *sd, int enable) { - struct i2c_client *client = to_i2c_client(icd->control); - struct soc_camera_link *icl = client->dev.platform_data; - - /* Disable the chip */ - reg_write(client, MT9M001_OUTPUT_CONTROL, 0); - - if (icl->power) - icl->power(&client->dev, 0); - - return 0; -} + struct i2c_client *client = sd->priv; -static int mt9m001_start_capture(struct soc_camera_device *icd) -{ - struct i2c_client *client = to_i2c_client(icd->control); - - /* Switch to master "normal" mode */ - if (reg_write(client, MT9M001_OUTPUT_CONTROL, 2) < 0) - return -EIO; - return 0; -} - -static int mt9m001_stop_capture(struct soc_camera_device *icd) -{ - struct i2c_client *client = to_i2c_client(icd->control); - - /* Stop sensor readout */ - if (reg_write(client, MT9M001_OUTPUT_CONTROL, 0) < 0) + /* Switch to master "normal" mode or stop sensor readout */ + if (reg_write(client, MT9M001_OUTPUT_CONTROL, enable ? 2 : 0) < 0) return -EIO; return 0; } @@ -182,8 +158,7 @@ static int mt9m001_stop_capture(struct soc_camera_device *icd) static int mt9m001_set_bus_param(struct soc_camera_device *icd, unsigned long flags) { - struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd); - struct soc_camera_link *icl = mt9m001->client->dev.platform_data; + struct soc_camera_link *icl = to_soc_camera_link(icd); unsigned long width_flag = flags & SOCAM_DATAWIDTH_MASK; /* Only one width bit may be set */ @@ -205,8 +180,7 @@ static int mt9m001_set_bus_param(struct soc_camera_device *icd, static unsigned long mt9m001_query_bus_param(struct soc_camera_device *icd) { - struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd); - struct soc_camera_link *icl = mt9m001->client->dev.platform_data; + struct soc_camera_link *icl = to_soc_camera_link(icd); /* MT9M001 has all capture_format parameters fixed */ unsigned long flags = SOCAM_PCLK_SAMPLE_FALLING | SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_VSYNC_ACTIVE_HIGH | @@ -220,13 +194,35 @@ static unsigned long mt9m001_query_bus_param(struct soc_camera_device *icd) return soc_camera_apply_sensor_flags(icl, flags); } -static int mt9m001_set_crop(struct soc_camera_device *icd, - struct v4l2_rect *rect) +static int mt9m001_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd); + struct i2c_client *client = sd->priv; + struct mt9m001 *mt9m001 = to_mt9m001(client); + struct v4l2_rect rect = a->c; + struct soc_camera_device *icd = client->dev.platform_data; int ret; const u16 hblank = 9, vblank = 25; + unsigned int total_h; + + if (mt9m001->fourcc == V4L2_PIX_FMT_SBGGR8 || + mt9m001->fourcc == V4L2_PIX_FMT_SBGGR16) + /* + * Bayer format - even number of rows for simplicity, + * but let the user play with the top row. + */ + rect.height = ALIGN(rect.height, 2); + + /* Datasheet requirement: see register description */ + rect.width = ALIGN(rect.width, 2); + rect.left = ALIGN(rect.left, 2); + + soc_camera_limit_side(&rect.left, &rect.width, + MT9M001_COLUMN_SKIP, MT9M001_MIN_WIDTH, MT9M001_MAX_WIDTH); + + soc_camera_limit_side(&rect.top, &rect.height, + MT9M001_ROW_SKIP, MT9M001_MIN_HEIGHT, MT9M001_MAX_HEIGHT); + + total_h = rect.height + icd->y_skip_top + vblank; /* Blanking and start values - default... */ ret = reg_write(client, MT9M001_HORIZONTAL_BLANKING, hblank); @@ -236,66 +232,126 @@ static int mt9m001_set_crop(struct soc_camera_device *icd, /* The caller provides a supported format, as verified per * call to icd->try_fmt() */ if (!ret) - ret = reg_write(client, MT9M001_COLUMN_START, rect->left); + ret = reg_write(client, MT9M001_COLUMN_START, rect.left); if (!ret) - ret = reg_write(client, MT9M001_ROW_START, rect->top); + ret = reg_write(client, MT9M001_ROW_START, rect.top); if (!ret) - ret = reg_write(client, MT9M001_WINDOW_WIDTH, rect->width - 1); + ret = reg_write(client, MT9M001_WINDOW_WIDTH, rect.width - 1); if (!ret) ret = reg_write(client, MT9M001_WINDOW_HEIGHT, - rect->height + icd->y_skip_top - 1); + rect.height + icd->y_skip_top - 1); if (!ret && mt9m001->autoexposure) { - ret = reg_write(client, MT9M001_SHUTTER_WIDTH, - rect->height + icd->y_skip_top + vblank); + ret = reg_write(client, MT9M001_SHUTTER_WIDTH, total_h); if (!ret) { const struct v4l2_queryctrl *qctrl = soc_camera_find_qctrl(icd->ops, V4L2_CID_EXPOSURE); - icd->exposure = (524 + (rect->height + icd->y_skip_top + - vblank - 1) * - (qctrl->maximum - qctrl->minimum)) / + mt9m001->exposure = (524 + (total_h - 1) * + (qctrl->maximum - qctrl->minimum)) / 1048 + qctrl->minimum; } } + if (!ret) + mt9m001->rect = rect; + return ret; } -static int mt9m001_set_fmt(struct soc_camera_device *icd, - struct v4l2_format *f) +static int mt9m001_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) +{ + struct i2c_client *client = sd->priv; + struct mt9m001 *mt9m001 = to_mt9m001(client); + + a->c = mt9m001->rect; + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + return 0; +} + +static int mt9m001_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) +{ + a->bounds.left = MT9M001_COLUMN_SKIP; + a->bounds.top = MT9M001_ROW_SKIP; + a->bounds.width = MT9M001_MAX_WIDTH; + a->bounds.height = MT9M001_MAX_HEIGHT; + a->defrect = a->bounds; + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + a->pixelaspect.numerator = 1; + a->pixelaspect.denominator = 1; + + return 0; +} + +static int mt9m001_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) { - struct v4l2_rect rect = { - .left = icd->x_current, - .top = icd->y_current, - .width = f->fmt.pix.width, - .height = f->fmt.pix.height, + struct i2c_client *client = sd->priv; + struct mt9m001 *mt9m001 = to_mt9m001(client); + struct v4l2_pix_format *pix = &f->fmt.pix; + + pix->width = mt9m001->rect.width; + pix->height = mt9m001->rect.height; + pix->pixelformat = mt9m001->fourcc; + pix->field = V4L2_FIELD_NONE; + pix->colorspace = V4L2_COLORSPACE_SRGB; + + return 0; +} + +static int mt9m001_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) +{ + struct i2c_client *client = sd->priv; + struct mt9m001 *mt9m001 = to_mt9m001(client); + struct v4l2_pix_format *pix = &f->fmt.pix; + struct v4l2_crop a = { + .c = { + .left = mt9m001->rect.left, + .top = mt9m001->rect.top, + .width = pix->width, + .height = pix->height, + }, }; + int ret; /* No support for scaling so far, just crop. TODO: use skipping */ - return mt9m001_set_crop(icd, &rect); + ret = mt9m001_s_crop(sd, &a); + if (!ret) { + pix->width = mt9m001->rect.width; + pix->height = mt9m001->rect.height; + mt9m001->fourcc = pix->pixelformat; + } + + return ret; } -static int mt9m001_try_fmt(struct soc_camera_device *icd, - struct v4l2_format *f) +static int mt9m001_try_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) { + struct i2c_client *client = sd->priv; + struct soc_camera_device *icd = client->dev.platform_data; struct v4l2_pix_format *pix = &f->fmt.pix; - v4l_bound_align_image(&pix->width, 48, 1280, 1, - &pix->height, 32 + icd->y_skip_top, - 1024 + icd->y_skip_top, 0, 0); + v4l_bound_align_image(&pix->width, MT9M001_MIN_WIDTH, + MT9M001_MAX_WIDTH, 1, + &pix->height, MT9M001_MIN_HEIGHT + icd->y_skip_top, + MT9M001_MAX_HEIGHT + icd->y_skip_top, 0, 0); + + if (pix->pixelformat == V4L2_PIX_FMT_SBGGR8 || + pix->pixelformat == V4L2_PIX_FMT_SBGGR16) + pix->height = ALIGN(pix->height - 1, 2); return 0; } -static int mt9m001_get_chip_id(struct soc_camera_device *icd, - struct v4l2_dbg_chip_ident *id) +static int mt9m001_g_chip_ident(struct v4l2_subdev *sd, + struct v4l2_dbg_chip_ident *id) { - struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd); + struct i2c_client *client = sd->priv; + struct mt9m001 *mt9m001 = to_mt9m001(client); if (id->match.type != V4L2_CHIP_MATCH_I2C_ADDR) return -EINVAL; - if (id->match.addr != mt9m001->client->addr) + if (id->match.addr != client->addr) return -ENODEV; id->ident = mt9m001->model; @@ -305,10 +361,10 @@ static int mt9m001_get_chip_id(struct soc_camera_device *icd, } #ifdef CONFIG_VIDEO_ADV_DEBUG -static int mt9m001_get_register(struct soc_camera_device *icd, - struct v4l2_dbg_register *reg) +static int mt9m001_g_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) { - struct i2c_client *client = to_i2c_client(icd->control); + struct i2c_client *client = sd->priv; if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff) return -EINVAL; @@ -325,10 +381,10 @@ static int mt9m001_get_register(struct soc_camera_device *icd, return 0; } -static int mt9m001_set_register(struct soc_camera_device *icd, - struct v4l2_dbg_register *reg) +static int mt9m001_s_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) { - struct i2c_client *client = to_i2c_client(icd->control); + struct i2c_client *client = sd->priv; if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff) return -EINVAL; @@ -381,39 +437,17 @@ static const struct v4l2_queryctrl mt9m001_controls[] = { } }; -static int mt9m001_video_probe(struct soc_camera_device *); -static void mt9m001_video_remove(struct soc_camera_device *); -static int mt9m001_get_control(struct soc_camera_device *, struct v4l2_control *); -static int mt9m001_set_control(struct soc_camera_device *, struct v4l2_control *); - static struct soc_camera_ops mt9m001_ops = { - .owner = THIS_MODULE, - .probe = mt9m001_video_probe, - .remove = mt9m001_video_remove, - .init = mt9m001_init, - .release = mt9m001_release, - .start_capture = mt9m001_start_capture, - .stop_capture = mt9m001_stop_capture, - .set_crop = mt9m001_set_crop, - .set_fmt = mt9m001_set_fmt, - .try_fmt = mt9m001_try_fmt, .set_bus_param = mt9m001_set_bus_param, .query_bus_param = mt9m001_query_bus_param, .controls = mt9m001_controls, .num_controls = ARRAY_SIZE(mt9m001_controls), - .get_control = mt9m001_get_control, - .set_control = mt9m001_set_control, - .get_chip_id = mt9m001_get_chip_id, -#ifdef CONFIG_VIDEO_ADV_DEBUG - .get_register = mt9m001_get_register, - .set_register = mt9m001_set_register, -#endif }; -static int mt9m001_get_control(struct soc_camera_device *icd, struct v4l2_control *ctrl) +static int mt9m001_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd); + struct i2c_client *client = sd->priv; + struct mt9m001 *mt9m001 = to_mt9m001(client); int data; switch (ctrl->id) { @@ -426,14 +460,21 @@ static int mt9m001_get_control(struct soc_camera_device *icd, struct v4l2_contro case V4L2_CID_EXPOSURE_AUTO: ctrl->value = mt9m001->autoexposure; break; + case V4L2_CID_GAIN: + ctrl->value = mt9m001->gain; + break; + case V4L2_CID_EXPOSURE: + ctrl->value = mt9m001->exposure; + break; } return 0; } -static int mt9m001_set_control(struct soc_camera_device *icd, struct v4l2_control *ctrl) +static int mt9m001_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd); + struct i2c_client *client = sd->priv; + struct mt9m001 *mt9m001 = to_mt9m001(client); + struct soc_camera_device *icd = client->dev.platform_data; const struct v4l2_queryctrl *qctrl; int data; @@ -460,7 +501,7 @@ static int mt9m001_set_control(struct soc_camera_device *icd, struct v4l2_contro unsigned long range = qctrl->default_value - qctrl->minimum; data = ((ctrl->value - qctrl->minimum) * 8 + range / 2) / range; - dev_dbg(&icd->dev, "Setting gain %d\n", data); + dev_dbg(&client->dev, "Setting gain %d\n", data); data = reg_write(client, MT9M001_GLOBAL_GAIN, data); if (data < 0) return -EIO; @@ -478,7 +519,7 @@ static int mt9m001_set_control(struct soc_camera_device *icd, struct v4l2_contro else data = ((gain - 64) * 7 + 28) / 56 + 96; - dev_dbg(&icd->dev, "Setting gain from %d to %d\n", + dev_dbg(&client->dev, "Setting gain from %d to %d\n", reg_read(client, MT9M001_GLOBAL_GAIN), data); data = reg_write(client, MT9M001_GLOBAL_GAIN, data); if (data < 0) @@ -486,7 +527,7 @@ static int mt9m001_set_control(struct soc_camera_device *icd, struct v4l2_contro } /* Success */ - icd->gain = ctrl->value; + mt9m001->gain = ctrl->value; break; case V4L2_CID_EXPOSURE: /* mt9m001 has maximum == default */ @@ -497,23 +538,27 @@ static int mt9m001_set_control(struct soc_camera_device *icd, struct v4l2_contro unsigned long shutter = ((ctrl->value - qctrl->minimum) * 1048 + range / 2) / range + 1; - dev_dbg(&icd->dev, "Setting shutter width from %d to %lu\n", - reg_read(client, MT9M001_SHUTTER_WIDTH), shutter); + dev_dbg(&client->dev, + "Setting shutter width from %d to %lu\n", + reg_read(client, MT9M001_SHUTTER_WIDTH), + shutter); if (reg_write(client, MT9M001_SHUTTER_WIDTH, shutter) < 0) return -EIO; - icd->exposure = ctrl->value; + mt9m001->exposure = ctrl->value; mt9m001->autoexposure = 0; } break; case V4L2_CID_EXPOSURE_AUTO: if (ctrl->value) { const u16 vblank = 25; - if (reg_write(client, MT9M001_SHUTTER_WIDTH, icd->height + - icd->y_skip_top + vblank) < 0) + unsigned int total_h = mt9m001->rect.height + + icd->y_skip_top + vblank; + if (reg_write(client, MT9M001_SHUTTER_WIDTH, + total_h) < 0) return -EIO; qctrl = soc_camera_find_qctrl(icd->ops, V4L2_CID_EXPOSURE); - icd->exposure = (524 + (icd->height + icd->y_skip_top + vblank - 1) * - (qctrl->maximum - qctrl->minimum)) / + mt9m001->exposure = (524 + (total_h - 1) * + (qctrl->maximum - qctrl->minimum)) / 1048 + qctrl->minimum; mt9m001->autoexposure = 1; } else @@ -525,14 +570,14 @@ static int mt9m001_set_control(struct soc_camera_device *icd, struct v4l2_contro /* Interface active, can use i2c. If it fails, it can indeed mean, that * this wasn't our capture interface, so, we wait for the right one */ -static int mt9m001_video_probe(struct soc_camera_device *icd) +static int mt9m001_video_probe(struct soc_camera_device *icd, + struct i2c_client *client) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd); - struct soc_camera_link *icl = client->dev.platform_data; + struct mt9m001 *mt9m001 = to_mt9m001(client); + struct soc_camera_link *icl = to_soc_camera_link(icd); s32 data; - int ret; unsigned long flags; + int ret; /* We must have a parent by now. And it cannot be a wrong one. * So this entire test is completely redundant. */ @@ -542,7 +587,7 @@ static int mt9m001_video_probe(struct soc_camera_device *icd) /* Enable the chip */ data = reg_write(client, MT9M001_CHIP_ENABLE, 1); - dev_dbg(&icd->dev, "write: %d\n", data); + dev_dbg(&client->dev, "write: %d\n", data); /* Read out the chip version register */ data = reg_read(client, MT9M001_CHIP_VERSION); @@ -559,10 +604,9 @@ static int mt9m001_video_probe(struct soc_camera_device *icd) icd->formats = mt9m001_monochrome_formats; break; default: - ret = -ENODEV; - dev_err(&icd->dev, + dev_err(&client->dev, "No MT9M001 chip detected, register read %x\n", data); - goto ei2c; + return -ENODEV; } icd->num_formats = 0; @@ -585,42 +629,72 @@ static int mt9m001_video_probe(struct soc_camera_device *icd) if (flags & SOCAM_DATAWIDTH_8) icd->num_formats++; - dev_info(&icd->dev, "Detected a MT9M001 chip ID %x (%s)\n", data, + mt9m001->fourcc = icd->formats->fourcc; + + dev_info(&client->dev, "Detected a MT9M001 chip ID %x (%s)\n", data, data == 0x8431 ? "C12STM" : "C12ST"); - /* Now that we know the model, we can start video */ - ret = soc_camera_video_start(icd); - if (ret) - goto eisis; + ret = mt9m001_init(client); + if (ret < 0) + dev_err(&client->dev, "Failed to initialise the camera\n"); - return 0; + /* mt9m001_init() has reset the chip, returning registers to defaults */ + mt9m001->gain = 64; + mt9m001->exposure = 255; -eisis: -ei2c: return ret; } static void mt9m001_video_remove(struct soc_camera_device *icd) { - struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd); - struct soc_camera_link *icl = mt9m001->client->dev.platform_data; + struct soc_camera_link *icl = to_soc_camera_link(icd); - dev_dbg(&icd->dev, "Video %x removed: %p, %p\n", mt9m001->client->addr, + dev_dbg(&icd->dev, "Video removed: %p, %p\n", icd->dev.parent, icd->vdev); - soc_camera_video_stop(icd); if (icl->free_bus) icl->free_bus(icl); } +static struct v4l2_subdev_core_ops mt9m001_subdev_core_ops = { + .g_ctrl = mt9m001_g_ctrl, + .s_ctrl = mt9m001_s_ctrl, + .g_chip_ident = mt9m001_g_chip_ident, +#ifdef CONFIG_VIDEO_ADV_DEBUG + .g_register = mt9m001_g_register, + .s_register = mt9m001_s_register, +#endif +}; + +static struct v4l2_subdev_video_ops mt9m001_subdev_video_ops = { + .s_stream = mt9m001_s_stream, + .s_fmt = mt9m001_s_fmt, + .g_fmt = mt9m001_g_fmt, + .try_fmt = mt9m001_try_fmt, + .s_crop = mt9m001_s_crop, + .g_crop = mt9m001_g_crop, + .cropcap = mt9m001_cropcap, +}; + +static struct v4l2_subdev_ops mt9m001_subdev_ops = { + .core = &mt9m001_subdev_core_ops, + .video = &mt9m001_subdev_video_ops, +}; + static int mt9m001_probe(struct i2c_client *client, const struct i2c_device_id *did) { struct mt9m001 *mt9m001; - struct soc_camera_device *icd; + struct soc_camera_device *icd = client->dev.platform_data; struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); - struct soc_camera_link *icl = client->dev.platform_data; + struct soc_camera_link *icl; int ret; + if (!icd) { + dev_err(&client->dev, "MT9M001: missing soc-camera data!\n"); + return -EINVAL; + } + + icl = to_soc_camera_link(icd); if (!icl) { dev_err(&client->dev, "MT9M001 driver needs platform data\n"); return -EINVAL; @@ -636,43 +710,40 @@ static int mt9m001_probe(struct i2c_client *client, if (!mt9m001) return -ENOMEM; - mt9m001->client = client; - i2c_set_clientdata(client, mt9m001); + v4l2_i2c_subdev_init(&mt9m001->subdev, client, &mt9m001_subdev_ops); /* Second stage probe - when a capture adapter is there */ - icd = &mt9m001->icd; - icd->ops = &mt9m001_ops; - icd->control = &client->dev; - icd->x_min = 20; - icd->y_min = 12; - icd->x_current = 20; - icd->y_current = 12; - icd->width_min = 48; - icd->width_max = 1280; - icd->height_min = 32; - icd->height_max = 1024; - icd->y_skip_top = 1; - icd->iface = icl->bus_id; + icd->ops = &mt9m001_ops; + icd->y_skip_top = 0; + + mt9m001->rect.left = MT9M001_COLUMN_SKIP; + mt9m001->rect.top = MT9M001_ROW_SKIP; + mt9m001->rect.width = MT9M001_MAX_WIDTH; + mt9m001->rect.height = MT9M001_MAX_HEIGHT; + /* Simulated autoexposure. If enabled, we calculate shutter width * ourselves in the driver based on vertical blanking and frame width */ mt9m001->autoexposure = 1; - ret = soc_camera_device_register(icd); - if (ret) - goto eisdr; - - return 0; + ret = mt9m001_video_probe(icd, client); + if (ret) { + icd->ops = NULL; + i2c_set_clientdata(client, NULL); + kfree(mt9m001); + } -eisdr: - kfree(mt9m001); return ret; } static int mt9m001_remove(struct i2c_client *client) { - struct mt9m001 *mt9m001 = i2c_get_clientdata(client); + struct mt9m001 *mt9m001 = to_mt9m001(client); + struct soc_camera_device *icd = client->dev.platform_data; - soc_camera_device_unregister(&mt9m001->icd); + icd->ops = NULL; + mt9m001_video_remove(icd); + i2c_set_clientdata(client, NULL); + client->driver = NULL; kfree(mt9m001); return 0; diff --git a/drivers/media/video/mt9m111.c b/drivers/media/video/mt9m111.c index fc5e2de03766..90da699601ea 100644 --- a/drivers/media/video/mt9m111.c +++ b/drivers/media/video/mt9m111.c @@ -148,12 +148,12 @@ enum mt9m111_context { }; struct mt9m111 { - struct i2c_client *client; - struct soc_camera_device icd; + struct v4l2_subdev subdev; int model; /* V4L2_IDENT_MT9M11x* codes from v4l2-chip-ident.h */ enum mt9m111_context context; struct v4l2_rect rect; u32 pixfmt; + unsigned int gain; unsigned char autoexposure; unsigned char datawidth; unsigned int powered:1; @@ -166,6 +166,11 @@ struct mt9m111 { unsigned int autowhitebalance:1; }; +static struct mt9m111 *to_mt9m111(const struct i2c_client *client) +{ + return container_of(i2c_get_clientdata(client), struct mt9m111, subdev); +} + static int reg_page_map_set(struct i2c_client *client, const u16 reg) { int ret; @@ -190,7 +195,7 @@ static int mt9m111_reg_read(struct i2c_client *client, const u16 reg) ret = reg_page_map_set(client, reg); if (!ret) - ret = swab16(i2c_smbus_read_word_data(client, (reg & 0xff))); + ret = swab16(i2c_smbus_read_word_data(client, reg & 0xff)); dev_dbg(&client->dev, "read reg.%03x -> %04x\n", reg, ret); return ret; @@ -203,7 +208,7 @@ static int mt9m111_reg_write(struct i2c_client *client, const u16 reg, ret = reg_page_map_set(client, reg); if (!ret) - ret = i2c_smbus_write_word_data(client, (reg & 0xff), + ret = i2c_smbus_write_word_data(client, reg & 0xff, swab16(data)); dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret); return ret; @@ -229,10 +234,9 @@ static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg, return mt9m111_reg_write(client, reg, ret & ~data); } -static int mt9m111_set_context(struct soc_camera_device *icd, +static int mt9m111_set_context(struct i2c_client *client, enum mt9m111_context ctxt) { - struct i2c_client *client = to_i2c_client(icd->control); int valB = MT9M111_CTXT_CTRL_RESTART | MT9M111_CTXT_CTRL_DEFECTCOR_B | MT9M111_CTXT_CTRL_RESIZE_B | MT9M111_CTXT_CTRL_CTRL2_B | MT9M111_CTXT_CTRL_GAMMA_B | MT9M111_CTXT_CTRL_READ_MODE_B @@ -246,17 +250,16 @@ static int mt9m111_set_context(struct soc_camera_device *icd, return reg_write(CONTEXT_CONTROL, valA); } -static int mt9m111_setup_rect(struct soc_camera_device *icd, +static int mt9m111_setup_rect(struct i2c_client *client, struct v4l2_rect *rect) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); + struct mt9m111 *mt9m111 = to_mt9m111(client); int ret, is_raw_format; int width = rect->width; int height = rect->height; - if ((mt9m111->pixfmt == V4L2_PIX_FMT_SBGGR8) - || (mt9m111->pixfmt == V4L2_PIX_FMT_SBGGR16)) + if (mt9m111->pixfmt == V4L2_PIX_FMT_SBGGR8 || + mt9m111->pixfmt == V4L2_PIX_FMT_SBGGR16) is_raw_format = 1; else is_raw_format = 0; @@ -292,9 +295,8 @@ static int mt9m111_setup_rect(struct soc_camera_device *icd, return ret; } -static int mt9m111_setup_pixfmt(struct soc_camera_device *icd, u16 outfmt) +static int mt9m111_setup_pixfmt(struct i2c_client *client, u16 outfmt) { - struct i2c_client *client = to_i2c_client(icd->control); int ret; ret = reg_write(OUTPUT_FORMAT_CTRL2_A, outfmt); @@ -303,19 +305,19 @@ static int mt9m111_setup_pixfmt(struct soc_camera_device *icd, u16 outfmt) return ret; } -static int mt9m111_setfmt_bayer8(struct soc_camera_device *icd) +static int mt9m111_setfmt_bayer8(struct i2c_client *client) { - return mt9m111_setup_pixfmt(icd, MT9M111_OUTFMT_PROCESSED_BAYER); + return mt9m111_setup_pixfmt(client, MT9M111_OUTFMT_PROCESSED_BAYER); } -static int mt9m111_setfmt_bayer10(struct soc_camera_device *icd) +static int mt9m111_setfmt_bayer10(struct i2c_client *client) { - return mt9m111_setup_pixfmt(icd, MT9M111_OUTFMT_BYPASS_IFP); + return mt9m111_setup_pixfmt(client, MT9M111_OUTFMT_BYPASS_IFP); } -static int mt9m111_setfmt_rgb565(struct soc_camera_device *icd) +static int mt9m111_setfmt_rgb565(struct i2c_client *client) { - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); + struct mt9m111 *mt9m111 = to_mt9m111(client); int val = 0; if (mt9m111->swap_rgb_red_blue) @@ -324,12 +326,12 @@ static int mt9m111_setfmt_rgb565(struct soc_camera_device *icd) val |= MT9M111_OUTFMT_SWAP_RGB_EVEN; val |= MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565; - return mt9m111_setup_pixfmt(icd, val); + return mt9m111_setup_pixfmt(client, val); } -static int mt9m111_setfmt_rgb555(struct soc_camera_device *icd) +static int mt9m111_setfmt_rgb555(struct i2c_client *client) { - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); + struct mt9m111 *mt9m111 = to_mt9m111(client); int val = 0; if (mt9m111->swap_rgb_red_blue) @@ -338,12 +340,12 @@ static int mt9m111_setfmt_rgb555(struct soc_camera_device *icd) val |= MT9M111_OUTFMT_SWAP_RGB_EVEN; val |= MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555; - return mt9m111_setup_pixfmt(icd, val); + return mt9m111_setup_pixfmt(client, val); } -static int mt9m111_setfmt_yuv(struct soc_camera_device *icd) +static int mt9m111_setfmt_yuv(struct i2c_client *client) { - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); + struct mt9m111 *mt9m111 = to_mt9m111(client); int val = 0; if (mt9m111->swap_yuv_cb_cr) @@ -351,52 +353,22 @@ static int mt9m111_setfmt_yuv(struct soc_camera_device *icd) if (mt9m111->swap_yuv_y_chromas) val |= MT9M111_OUTFMT_SWAP_YCbCr_C_Y; - return mt9m111_setup_pixfmt(icd, val); + return mt9m111_setup_pixfmt(client, val); } -static int mt9m111_enable(struct soc_camera_device *icd) +static int mt9m111_enable(struct i2c_client *client) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); - struct soc_camera_link *icl = client->dev.platform_data; + struct mt9m111 *mt9m111 = to_mt9m111(client); int ret; - if (icl->power) { - ret = icl->power(&client->dev, 1); - if (ret < 0) { - dev_err(icd->vdev->parent, - "Platform failed to power-on the camera.\n"); - return ret; - } - } - ret = reg_set(RESET, MT9M111_RESET_CHIP_ENABLE); if (!ret) mt9m111->powered = 1; return ret; } -static int mt9m111_disable(struct soc_camera_device *icd) -{ - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); - struct soc_camera_link *icl = client->dev.platform_data; - int ret; - - ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE); - if (!ret) - mt9m111->powered = 0; - - if (icl->power) - icl->power(&client->dev, 0); - - return ret; -} - -static int mt9m111_reset(struct soc_camera_device *icd) +static int mt9m111_reset(struct i2c_client *client) { - struct i2c_client *client = to_i2c_client(icd->control); - struct soc_camera_link *icl = client->dev.platform_data; int ret; ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); @@ -406,26 +378,12 @@ static int mt9m111_reset(struct soc_camera_device *icd) ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE | MT9M111_RESET_RESET_SOC); - if (icl->reset) - icl->reset(&client->dev); - return ret; } -static int mt9m111_start_capture(struct soc_camera_device *icd) -{ - return 0; -} - -static int mt9m111_stop_capture(struct soc_camera_device *icd) -{ - return 0; -} - static unsigned long mt9m111_query_bus_param(struct soc_camera_device *icd) { - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); - struct soc_camera_link *icl = mt9m111->client->dev.platform_data; + struct soc_camera_link *icl = to_soc_camera_link(icd); unsigned long flags = SOCAM_MASTER | SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_DATA_ACTIVE_HIGH | SOCAM_DATAWIDTH_8; @@ -438,62 +396,126 @@ static int mt9m111_set_bus_param(struct soc_camera_device *icd, unsigned long f) return 0; } -static int mt9m111_set_crop(struct soc_camera_device *icd, - struct v4l2_rect *rect) +static int mt9m111_make_rect(struct i2c_client *client, + struct v4l2_rect *rect) { - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); + struct mt9m111 *mt9m111 = to_mt9m111(client); + + if (mt9m111->pixfmt == V4L2_PIX_FMT_SBGGR8 || + mt9m111->pixfmt == V4L2_PIX_FMT_SBGGR16) { + /* Bayer format - even size lengths */ + rect->width = ALIGN(rect->width, 2); + rect->height = ALIGN(rect->height, 2); + /* Let the user play with the starting pixel */ + } + + /* FIXME: the datasheet doesn't specify minimum sizes */ + soc_camera_limit_side(&rect->left, &rect->width, + MT9M111_MIN_DARK_COLS, 2, MT9M111_MAX_WIDTH); + + soc_camera_limit_side(&rect->top, &rect->height, + MT9M111_MIN_DARK_ROWS, 2, MT9M111_MAX_HEIGHT); + + return mt9m111_setup_rect(client, rect); +} + +static int mt9m111_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) +{ + struct v4l2_rect rect = a->c; + struct i2c_client *client = sd->priv; + struct mt9m111 *mt9m111 = to_mt9m111(client); int ret; - dev_dbg(&icd->dev, "%s left=%d, top=%d, width=%d, height=%d\n", - __func__, rect->left, rect->top, rect->width, - rect->height); + dev_dbg(&client->dev, "%s left=%d, top=%d, width=%d, height=%d\n", + __func__, rect.left, rect.top, rect.width, rect.height); - ret = mt9m111_setup_rect(icd, rect); + ret = mt9m111_make_rect(client, &rect); if (!ret) - mt9m111->rect = *rect; + mt9m111->rect = rect; return ret; } -static int mt9m111_set_pixfmt(struct soc_camera_device *icd, u32 pixfmt) +static int mt9m111_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) { - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); + struct i2c_client *client = sd->priv; + struct mt9m111 *mt9m111 = to_mt9m111(client); + + a->c = mt9m111->rect; + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + return 0; +} + +static int mt9m111_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) +{ + a->bounds.left = MT9M111_MIN_DARK_COLS; + a->bounds.top = MT9M111_MIN_DARK_ROWS; + a->bounds.width = MT9M111_MAX_WIDTH; + a->bounds.height = MT9M111_MAX_HEIGHT; + a->defrect = a->bounds; + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + a->pixelaspect.numerator = 1; + a->pixelaspect.denominator = 1; + + return 0; +} + +static int mt9m111_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) +{ + struct i2c_client *client = sd->priv; + struct mt9m111 *mt9m111 = to_mt9m111(client); + struct v4l2_pix_format *pix = &f->fmt.pix; + + pix->width = mt9m111->rect.width; + pix->height = mt9m111->rect.height; + pix->pixelformat = mt9m111->pixfmt; + pix->field = V4L2_FIELD_NONE; + pix->colorspace = V4L2_COLORSPACE_SRGB; + + return 0; +} + +static int mt9m111_set_pixfmt(struct i2c_client *client, u32 pixfmt) +{ + struct mt9m111 *mt9m111 = to_mt9m111(client); int ret; switch (pixfmt) { case V4L2_PIX_FMT_SBGGR8: - ret = mt9m111_setfmt_bayer8(icd); + ret = mt9m111_setfmt_bayer8(client); break; case V4L2_PIX_FMT_SBGGR16: - ret = mt9m111_setfmt_bayer10(icd); + ret = mt9m111_setfmt_bayer10(client); break; case V4L2_PIX_FMT_RGB555: - ret = mt9m111_setfmt_rgb555(icd); + ret = mt9m111_setfmt_rgb555(client); break; case V4L2_PIX_FMT_RGB565: - ret = mt9m111_setfmt_rgb565(icd); + ret = mt9m111_setfmt_rgb565(client); break; case V4L2_PIX_FMT_UYVY: mt9m111->swap_yuv_y_chromas = 0; mt9m111->swap_yuv_cb_cr = 0; - ret = mt9m111_setfmt_yuv(icd); + ret = mt9m111_setfmt_yuv(client); break; case V4L2_PIX_FMT_VYUY: mt9m111->swap_yuv_y_chromas = 0; mt9m111->swap_yuv_cb_cr = 1; - ret = mt9m111_setfmt_yuv(icd); + ret = mt9m111_setfmt_yuv(client); break; case V4L2_PIX_FMT_YUYV: mt9m111->swap_yuv_y_chromas = 1; mt9m111->swap_yuv_cb_cr = 0; - ret = mt9m111_setfmt_yuv(icd); + ret = mt9m111_setfmt_yuv(client); break; case V4L2_PIX_FMT_YVYU: mt9m111->swap_yuv_y_chromas = 1; mt9m111->swap_yuv_cb_cr = 1; - ret = mt9m111_setfmt_yuv(icd); + ret = mt9m111_setfmt_yuv(client); break; default: - dev_err(&icd->dev, "Pixel format not handled : %x\n", pixfmt); + dev_err(&client->dev, "Pixel format not handled : %x\n", + pixfmt); ret = -EINVAL; } @@ -503,10 +525,10 @@ static int mt9m111_set_pixfmt(struct soc_camera_device *icd, u32 pixfmt) return ret; } -static int mt9m111_set_fmt(struct soc_camera_device *icd, - struct v4l2_format *f) +static int mt9m111_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) { - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); + struct i2c_client *client = sd->priv; + struct mt9m111 *mt9m111 = to_mt9m111(client); struct v4l2_pix_format *pix = &f->fmt.pix; struct v4l2_rect rect = { .left = mt9m111->rect.left, @@ -516,40 +538,56 @@ static int mt9m111_set_fmt(struct soc_camera_device *icd, }; int ret; - dev_dbg(&icd->dev, "%s fmt=%x left=%d, top=%d, width=%d, height=%d\n", - __func__, pix->pixelformat, rect.left, rect.top, rect.width, - rect.height); + dev_dbg(&client->dev, + "%s fmt=%x left=%d, top=%d, width=%d, height=%d\n", __func__, + pix->pixelformat, rect.left, rect.top, rect.width, rect.height); - ret = mt9m111_setup_rect(icd, &rect); + ret = mt9m111_make_rect(client, &rect); if (!ret) - ret = mt9m111_set_pixfmt(icd, pix->pixelformat); + ret = mt9m111_set_pixfmt(client, pix->pixelformat); if (!ret) mt9m111->rect = rect; return ret; } -static int mt9m111_try_fmt(struct soc_camera_device *icd, - struct v4l2_format *f) +static int mt9m111_try_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) { struct v4l2_pix_format *pix = &f->fmt.pix; + bool bayer = pix->pixelformat == V4L2_PIX_FMT_SBGGR8 || + pix->pixelformat == V4L2_PIX_FMT_SBGGR16; + + /* + * With Bayer format enforce even side lengths, but let the user play + * with the starting pixel + */ if (pix->height > MT9M111_MAX_HEIGHT) pix->height = MT9M111_MAX_HEIGHT; + else if (pix->height < 2) + pix->height = 2; + else if (bayer) + pix->height = ALIGN(pix->height, 2); + if (pix->width > MT9M111_MAX_WIDTH) pix->width = MT9M111_MAX_WIDTH; + else if (pix->width < 2) + pix->width = 2; + else if (bayer) + pix->width = ALIGN(pix->width, 2); return 0; } -static int mt9m111_get_chip_id(struct soc_camera_device *icd, - struct v4l2_dbg_chip_ident *id) +static int mt9m111_g_chip_ident(struct v4l2_subdev *sd, + struct v4l2_dbg_chip_ident *id) { - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); + struct i2c_client *client = sd->priv; + struct mt9m111 *mt9m111 = to_mt9m111(client); if (id->match.type != V4L2_CHIP_MATCH_I2C_ADDR) return -EINVAL; - if (id->match.addr != mt9m111->client->addr) + if (id->match.addr != client->addr) return -ENODEV; id->ident = mt9m111->model; @@ -559,11 +597,11 @@ static int mt9m111_get_chip_id(struct soc_camera_device *icd, } #ifdef CONFIG_VIDEO_ADV_DEBUG -static int mt9m111_get_register(struct soc_camera_device *icd, - struct v4l2_dbg_register *reg) +static int mt9m111_g_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) { + struct i2c_client *client = sd->priv; int val; - struct i2c_client *client = to_i2c_client(icd->control); if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0x2ff) return -EINVAL; @@ -580,10 +618,10 @@ static int mt9m111_get_register(struct soc_camera_device *icd, return 0; } -static int mt9m111_set_register(struct soc_camera_device *icd, - struct v4l2_dbg_register *reg) +static int mt9m111_s_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) { - struct i2c_client *client = to_i2c_client(icd->control); + struct i2c_client *client = sd->priv; if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0x2ff) return -EINVAL; @@ -635,45 +673,21 @@ static const struct v4l2_queryctrl mt9m111_controls[] = { } }; -static int mt9m111_video_probe(struct soc_camera_device *); -static void mt9m111_video_remove(struct soc_camera_device *); -static int mt9m111_get_control(struct soc_camera_device *, - struct v4l2_control *); -static int mt9m111_set_control(struct soc_camera_device *, - struct v4l2_control *); static int mt9m111_resume(struct soc_camera_device *icd); -static int mt9m111_init(struct soc_camera_device *icd); -static int mt9m111_release(struct soc_camera_device *icd); +static int mt9m111_suspend(struct soc_camera_device *icd, pm_message_t state); static struct soc_camera_ops mt9m111_ops = { - .owner = THIS_MODULE, - .probe = mt9m111_video_probe, - .remove = mt9m111_video_remove, - .init = mt9m111_init, + .suspend = mt9m111_suspend, .resume = mt9m111_resume, - .release = mt9m111_release, - .start_capture = mt9m111_start_capture, - .stop_capture = mt9m111_stop_capture, - .set_crop = mt9m111_set_crop, - .set_fmt = mt9m111_set_fmt, - .try_fmt = mt9m111_try_fmt, .query_bus_param = mt9m111_query_bus_param, .set_bus_param = mt9m111_set_bus_param, .controls = mt9m111_controls, .num_controls = ARRAY_SIZE(mt9m111_controls), - .get_control = mt9m111_get_control, - .set_control = mt9m111_set_control, - .get_chip_id = mt9m111_get_chip_id, -#ifdef CONFIG_VIDEO_ADV_DEBUG - .get_register = mt9m111_get_register, - .set_register = mt9m111_set_register, -#endif }; -static int mt9m111_set_flip(struct soc_camera_device *icd, int flip, int mask) +static int mt9m111_set_flip(struct i2c_client *client, int flip, int mask) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); + struct mt9m111 *mt9m111 = to_mt9m111(client); int ret; if (mt9m111->context == HIGHPOWER) { @@ -691,9 +705,8 @@ static int mt9m111_set_flip(struct soc_camera_device *icd, int flip, int mask) return ret; } -static int mt9m111_get_global_gain(struct soc_camera_device *icd) +static int mt9m111_get_global_gain(struct i2c_client *client) { - struct i2c_client *client = to_i2c_client(icd->control); int data; data = reg_read(GLOBAL_GAIN); @@ -703,15 +716,15 @@ static int mt9m111_get_global_gain(struct soc_camera_device *icd) return data; } -static int mt9m111_set_global_gain(struct soc_camera_device *icd, int gain) +static int mt9m111_set_global_gain(struct i2c_client *client, int gain) { - struct i2c_client *client = to_i2c_client(icd->control); + struct mt9m111 *mt9m111 = to_mt9m111(client); u16 val; if (gain > 63 * 2 * 2) return -EINVAL; - icd->gain = gain; + mt9m111->gain = gain; if ((gain >= 64 * 2) && (gain < 63 * 2 * 2)) val = (1 << 10) | (1 << 9) | (gain / 4); else if ((gain >= 64) && (gain < 64 * 2)) @@ -722,10 +735,9 @@ static int mt9m111_set_global_gain(struct soc_camera_device *icd, int gain) return reg_write(GLOBAL_GAIN, val); } -static int mt9m111_set_autoexposure(struct soc_camera_device *icd, int on) +static int mt9m111_set_autoexposure(struct i2c_client *client, int on) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); + struct mt9m111 *mt9m111 = to_mt9m111(client); int ret; if (on) @@ -739,10 +751,9 @@ static int mt9m111_set_autoexposure(struct soc_camera_device *icd, int on) return ret; } -static int mt9m111_set_autowhitebalance(struct soc_camera_device *icd, int on) +static int mt9m111_set_autowhitebalance(struct i2c_client *client, int on) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); + struct mt9m111 *mt9m111 = to_mt9m111(client); int ret; if (on) @@ -756,11 +767,10 @@ static int mt9m111_set_autowhitebalance(struct soc_camera_device *icd, int on) return ret; } -static int mt9m111_get_control(struct soc_camera_device *icd, - struct v4l2_control *ctrl) +static int mt9m111_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); + struct i2c_client *client = sd->priv; + struct mt9m111 *mt9m111 = to_mt9m111(client); int data; switch (ctrl->id) { @@ -785,7 +795,7 @@ static int mt9m111_get_control(struct soc_camera_device *icd, ctrl->value = !!(data & MT9M111_RMB_MIRROR_COLS); break; case V4L2_CID_GAIN: - data = mt9m111_get_global_gain(icd); + data = mt9m111_get_global_gain(client); if (data < 0) return data; ctrl->value = data; @@ -800,37 +810,36 @@ static int mt9m111_get_control(struct soc_camera_device *icd, return 0; } -static int mt9m111_set_control(struct soc_camera_device *icd, - struct v4l2_control *ctrl) +static int mt9m111_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) { - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); + struct i2c_client *client = sd->priv; + struct mt9m111 *mt9m111 = to_mt9m111(client); const struct v4l2_queryctrl *qctrl; int ret; qctrl = soc_camera_find_qctrl(&mt9m111_ops, ctrl->id); - if (!qctrl) return -EINVAL; switch (ctrl->id) { case V4L2_CID_VFLIP: mt9m111->vflip = ctrl->value; - ret = mt9m111_set_flip(icd, ctrl->value, + ret = mt9m111_set_flip(client, ctrl->value, MT9M111_RMB_MIRROR_ROWS); break; case V4L2_CID_HFLIP: mt9m111->hflip = ctrl->value; - ret = mt9m111_set_flip(icd, ctrl->value, + ret = mt9m111_set_flip(client, ctrl->value, MT9M111_RMB_MIRROR_COLS); break; case V4L2_CID_GAIN: - ret = mt9m111_set_global_gain(icd, ctrl->value); + ret = mt9m111_set_global_gain(client, ctrl->value); break; case V4L2_CID_EXPOSURE_AUTO: - ret = mt9m111_set_autoexposure(icd, ctrl->value); + ret = mt9m111_set_autoexposure(client, ctrl->value); break; case V4L2_CID_AUTO_WHITE_BALANCE: - ret = mt9m111_set_autowhitebalance(icd, ctrl->value); + ret = mt9m111_set_autowhitebalance(client, ctrl->value); break; default: ret = -EINVAL; @@ -839,62 +848,62 @@ static int mt9m111_set_control(struct soc_camera_device *icd, return ret; } -static int mt9m111_restore_state(struct soc_camera_device *icd) +static int mt9m111_suspend(struct soc_camera_device *icd, pm_message_t state) { - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); - - mt9m111_set_context(icd, mt9m111->context); - mt9m111_set_pixfmt(icd, mt9m111->pixfmt); - mt9m111_setup_rect(icd, &mt9m111->rect); - mt9m111_set_flip(icd, mt9m111->hflip, MT9M111_RMB_MIRROR_COLS); - mt9m111_set_flip(icd, mt9m111->vflip, MT9M111_RMB_MIRROR_ROWS); - mt9m111_set_global_gain(icd, icd->gain); - mt9m111_set_autoexposure(icd, mt9m111->autoexposure); - mt9m111_set_autowhitebalance(icd, mt9m111->autowhitebalance); + struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd)); + struct mt9m111 *mt9m111 = to_mt9m111(client); + + mt9m111->gain = mt9m111_get_global_gain(client); + + return 0; +} + +static int mt9m111_restore_state(struct i2c_client *client) +{ + struct mt9m111 *mt9m111 = to_mt9m111(client); + + mt9m111_set_context(client, mt9m111->context); + mt9m111_set_pixfmt(client, mt9m111->pixfmt); + mt9m111_setup_rect(client, &mt9m111->rect); + mt9m111_set_flip(client, mt9m111->hflip, MT9M111_RMB_MIRROR_COLS); + mt9m111_set_flip(client, mt9m111->vflip, MT9M111_RMB_MIRROR_ROWS); + mt9m111_set_global_gain(client, mt9m111->gain); + mt9m111_set_autoexposure(client, mt9m111->autoexposure); + mt9m111_set_autowhitebalance(client, mt9m111->autowhitebalance); return 0; } static int mt9m111_resume(struct soc_camera_device *icd) { - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); + struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd)); + struct mt9m111 *mt9m111 = to_mt9m111(client); int ret = 0; if (mt9m111->powered) { - ret = mt9m111_enable(icd); + ret = mt9m111_enable(client); if (!ret) - ret = mt9m111_reset(icd); + ret = mt9m111_reset(client); if (!ret) - ret = mt9m111_restore_state(icd); + ret = mt9m111_restore_state(client); } return ret; } -static int mt9m111_init(struct soc_camera_device *icd) +static int mt9m111_init(struct i2c_client *client) { - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); + struct mt9m111 *mt9m111 = to_mt9m111(client); int ret; mt9m111->context = HIGHPOWER; - ret = mt9m111_enable(icd); + ret = mt9m111_enable(client); if (!ret) - ret = mt9m111_reset(icd); + ret = mt9m111_reset(client); if (!ret) - ret = mt9m111_set_context(icd, mt9m111->context); + ret = mt9m111_set_context(client, mt9m111->context); if (!ret) - ret = mt9m111_set_autoexposure(icd, mt9m111->autoexposure); + ret = mt9m111_set_autoexposure(client, mt9m111->autoexposure); if (ret) - dev_err(&icd->dev, "mt9m11x init failed: %d\n", ret); - return ret; -} - -static int mt9m111_release(struct soc_camera_device *icd) -{ - int ret; - - ret = mt9m111_disable(icd); - if (ret < 0) - dev_err(&icd->dev, "mt9m11x release failed: %d\n", ret); - + dev_err(&client->dev, "mt9m11x init failed: %d\n", ret); return ret; } @@ -902,10 +911,10 @@ static int mt9m111_release(struct soc_camera_device *icd) * Interface active, can use i2c. If it fails, it can indeed mean, that * this wasn't our capture interface, so, we wait for the right one */ -static int mt9m111_video_probe(struct soc_camera_device *icd) +static int mt9m111_video_probe(struct soc_camera_device *icd, + struct i2c_client *client) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); + struct mt9m111 *mt9m111 = to_mt9m111(client); s32 data; int ret; @@ -917,10 +926,13 @@ static int mt9m111_video_probe(struct soc_camera_device *icd) to_soc_camera_host(icd->dev.parent)->nr != icd->iface) return -ENODEV; - ret = mt9m111_enable(icd); - if (ret) - goto ei2c; - ret = mt9m111_reset(icd); + mt9m111->autoexposure = 1; + mt9m111->autowhitebalance = 1; + + mt9m111->swap_rgb_even_odd = 1; + mt9m111->swap_rgb_red_blue = 1; + + ret = mt9m111_init(client); if (ret) goto ei2c; @@ -935,7 +947,7 @@ static int mt9m111_video_probe(struct soc_camera_device *icd) break; default: ret = -ENODEV; - dev_err(&icd->dev, + dev_err(&client->dev, "No MT9M11x chip detected, register read %x\n", data); goto ei2c; } @@ -943,42 +955,51 @@ static int mt9m111_video_probe(struct soc_camera_device *icd) icd->formats = mt9m111_colour_formats; icd->num_formats = ARRAY_SIZE(mt9m111_colour_formats); - dev_info(&icd->dev, "Detected a MT9M11x chip ID %x\n", data); + dev_info(&client->dev, "Detected a MT9M11x chip ID %x\n", data); - ret = soc_camera_video_start(icd); - if (ret) - goto eisis; - - mt9m111->autoexposure = 1; - mt9m111->autowhitebalance = 1; - - mt9m111->swap_rgb_even_odd = 1; - mt9m111->swap_rgb_red_blue = 1; - - return 0; -eisis: ei2c: return ret; } -static void mt9m111_video_remove(struct soc_camera_device *icd) -{ - struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd); +static struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = { + .g_ctrl = mt9m111_g_ctrl, + .s_ctrl = mt9m111_s_ctrl, + .g_chip_ident = mt9m111_g_chip_ident, +#ifdef CONFIG_VIDEO_ADV_DEBUG + .g_register = mt9m111_g_register, + .s_register = mt9m111_s_register, +#endif +}; - dev_dbg(&icd->dev, "Video %x removed: %p, %p\n", mt9m111->client->addr, - mt9m111->icd.dev.parent, mt9m111->icd.vdev); - soc_camera_video_stop(&mt9m111->icd); -} +static struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = { + .s_fmt = mt9m111_s_fmt, + .g_fmt = mt9m111_g_fmt, + .try_fmt = mt9m111_try_fmt, + .s_crop = mt9m111_s_crop, + .g_crop = mt9m111_g_crop, + .cropcap = mt9m111_cropcap, +}; + +static struct v4l2_subdev_ops mt9m111_subdev_ops = { + .core = &mt9m111_subdev_core_ops, + .video = &mt9m111_subdev_video_ops, +}; static int mt9m111_probe(struct i2c_client *client, const struct i2c_device_id *did) { struct mt9m111 *mt9m111; - struct soc_camera_device *icd; + struct soc_camera_device *icd = client->dev.platform_data; struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); - struct soc_camera_link *icl = client->dev.platform_data; + struct soc_camera_link *icl; int ret; + if (!icd) { + dev_err(&client->dev, "MT9M11x: missing soc-camera data!\n"); + return -EINVAL; + } + + icl = to_soc_camera_link(icd); if (!icl) { dev_err(&client->dev, "MT9M11x driver needs platform data\n"); return -EINVAL; @@ -994,38 +1015,35 @@ static int mt9m111_probe(struct i2c_client *client, if (!mt9m111) return -ENOMEM; - mt9m111->client = client; - i2c_set_clientdata(client, mt9m111); + v4l2_i2c_subdev_init(&mt9m111->subdev, client, &mt9m111_subdev_ops); /* Second stage probe - when a capture adapter is there */ - icd = &mt9m111->icd; - icd->ops = &mt9m111_ops; - icd->control = &client->dev; - icd->x_min = MT9M111_MIN_DARK_COLS; - icd->y_min = MT9M111_MIN_DARK_ROWS; - icd->x_current = icd->x_min; - icd->y_current = icd->y_min; - icd->width_min = MT9M111_MIN_DARK_ROWS; - icd->width_max = MT9M111_MAX_WIDTH; - icd->height_min = MT9M111_MIN_DARK_COLS; - icd->height_max = MT9M111_MAX_HEIGHT; - icd->y_skip_top = 0; - icd->iface = icl->bus_id; - - ret = soc_camera_device_register(icd); - if (ret) - goto eisdr; - return 0; + icd->ops = &mt9m111_ops; + icd->y_skip_top = 0; + + mt9m111->rect.left = MT9M111_MIN_DARK_COLS; + mt9m111->rect.top = MT9M111_MIN_DARK_ROWS; + mt9m111->rect.width = MT9M111_MAX_WIDTH; + mt9m111->rect.height = MT9M111_MAX_HEIGHT; + + ret = mt9m111_video_probe(icd, client); + if (ret) { + icd->ops = NULL; + i2c_set_clientdata(client, NULL); + kfree(mt9m111); + } -eisdr: - kfree(mt9m111); return ret; } static int mt9m111_remove(struct i2c_client *client) { - struct mt9m111 *mt9m111 = i2c_get_clientdata(client); - soc_camera_device_unregister(&mt9m111->icd); + struct mt9m111 *mt9m111 = to_mt9m111(client); + struct soc_camera_device *icd = client->dev.platform_data; + + icd->ops = NULL; + i2c_set_clientdata(client, NULL); + client->driver = NULL; kfree(mt9m111); return 0; diff --git a/drivers/media/video/mt9t031.c b/drivers/media/video/mt9t031.c index 4207fb342670..6966f644977e 100644 --- a/drivers/media/video/mt9t031.c +++ b/drivers/media/video/mt9t031.c @@ -13,13 +13,13 @@ #include #include -#include +#include #include #include /* mt9t031 i2c address 0x5d - * The platform has to define i2c_board_info - * and call i2c_register_board_info() */ + * The platform has to define i2c_board_info and link to it from + * struct soc_camera_link */ /* mt9t031 selected register addresses */ #define MT9T031_CHIP_VERSION 0x00 @@ -47,7 +47,7 @@ #define MT9T031_MAX_HEIGHT 1536 #define MT9T031_MAX_WIDTH 2048 #define MT9T031_MIN_HEIGHT 2 -#define MT9T031_MIN_WIDTH 2 +#define MT9T031_MIN_WIDTH 18 #define MT9T031_HORIZONTAL_BLANK 142 #define MT9T031_VERTICAL_BLANK 25 #define MT9T031_COLUMN_SKIP 32 @@ -68,14 +68,21 @@ static const struct soc_camera_data_format mt9t031_colour_formats[] = { }; struct mt9t031 { - struct i2c_client *client; - struct soc_camera_device icd; + struct v4l2_subdev subdev; + struct v4l2_rect rect; /* Sensor window */ int model; /* V4L2_IDENT_MT9T031* codes from v4l2-chip-ident.h */ - unsigned char autoexposure; u16 xskip; u16 yskip; + unsigned int gain; + unsigned int exposure; + unsigned char autoexposure; }; +static struct mt9t031 *to_mt9t031(const struct i2c_client *client) +{ + return container_of(i2c_get_clientdata(client), struct mt9t031, subdev); +} + static int reg_read(struct i2c_client *client, const u8 reg) { s32 data = i2c_smbus_read_word_data(client, reg); @@ -136,21 +143,10 @@ static int get_shutter(struct i2c_client *client, u32 *data) return ret < 0 ? ret : 0; } -static int mt9t031_init(struct soc_camera_device *icd) +static int mt9t031_idle(struct i2c_client *client) { - struct i2c_client *client = to_i2c_client(icd->control); - struct soc_camera_link *icl = client->dev.platform_data; int ret; - if (icl->power) { - ret = icl->power(&client->dev, 1); - if (ret < 0) { - dev_err(icd->vdev->parent, - "Platform failed to power-on the camera.\n"); - return ret; - } - } - /* Disable chip output, synchronous option update */ ret = reg_write(client, MT9T031_RESET, 1); if (ret >= 0) @@ -158,50 +154,39 @@ static int mt9t031_init(struct soc_camera_device *icd) if (ret >= 0) ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 2); - if (ret < 0 && icl->power) - icl->power(&client->dev, 0); - return ret >= 0 ? 0 : -EIO; } -static int mt9t031_release(struct soc_camera_device *icd) +static int mt9t031_disable(struct i2c_client *client) { - struct i2c_client *client = to_i2c_client(icd->control); - struct soc_camera_link *icl = client->dev.platform_data; - /* Disable the chip */ reg_clear(client, MT9T031_OUTPUT_CONTROL, 2); - if (icl->power) - icl->power(&client->dev, 0); - return 0; } -static int mt9t031_start_capture(struct soc_camera_device *icd) +static int mt9t031_s_stream(struct v4l2_subdev *sd, int enable) { - struct i2c_client *client = to_i2c_client(icd->control); - - /* Switch to master "normal" mode */ - if (reg_set(client, MT9T031_OUTPUT_CONTROL, 2) < 0) - return -EIO; - return 0; -} + struct i2c_client *client = sd->priv; + int ret; -static int mt9t031_stop_capture(struct soc_camera_device *icd) -{ - struct i2c_client *client = to_i2c_client(icd->control); + if (enable) + /* Switch to master "normal" mode */ + ret = reg_set(client, MT9T031_OUTPUT_CONTROL, 2); + else + /* Stop sensor readout */ + ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 2); - /* Stop sensor readout */ - if (reg_clear(client, MT9T031_OUTPUT_CONTROL, 2) < 0) + if (ret < 0) return -EIO; + return 0; } static int mt9t031_set_bus_param(struct soc_camera_device *icd, unsigned long flags) { - struct i2c_client *client = to_i2c_client(icd->control); + struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd)); /* The caller should have queried our parameters, check anyway */ if (flags & ~MT9T031_BUS_PARAM) @@ -217,69 +202,73 @@ static int mt9t031_set_bus_param(struct soc_camera_device *icd, static unsigned long mt9t031_query_bus_param(struct soc_camera_device *icd) { - struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd); - struct soc_camera_link *icl = mt9t031->client->dev.platform_data; + struct soc_camera_link *icl = to_soc_camera_link(icd); return soc_camera_apply_sensor_flags(icl, MT9T031_BUS_PARAM); } -/* Round up minima and round down maxima */ -static void recalculate_limits(struct soc_camera_device *icd, - u16 xskip, u16 yskip) +/* target must be _even_ */ +static u16 mt9t031_skip(s32 *source, s32 target, s32 max) { - icd->x_min = (MT9T031_COLUMN_SKIP + xskip - 1) / xskip; - icd->y_min = (MT9T031_ROW_SKIP + yskip - 1) / yskip; - icd->width_min = (MT9T031_MIN_WIDTH + xskip - 1) / xskip; - icd->height_min = (MT9T031_MIN_HEIGHT + yskip - 1) / yskip; - icd->width_max = MT9T031_MAX_WIDTH / xskip; - icd->height_max = MT9T031_MAX_HEIGHT / yskip; + unsigned int skip; + + if (*source < target + target / 2) { + *source = target; + return 1; + } + + skip = min(max, *source + target / 2) / target; + if (skip > 8) + skip = 8; + *source = target * skip; + + return skip; } +/* rect is the sensor rectangle, the caller guarantees parameter validity */ static int mt9t031_set_params(struct soc_camera_device *icd, struct v4l2_rect *rect, u16 xskip, u16 yskip) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd); + struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd)); + struct mt9t031 *mt9t031 = to_mt9t031(client); int ret; - u16 xbin, ybin, width, height, left, top; + u16 xbin, ybin; const u16 hblank = MT9T031_HORIZONTAL_BLANK, vblank = MT9T031_VERTICAL_BLANK; - /* Make sure we don't exceed sensor limits */ - if (rect->left + rect->width > icd->width_max) - rect->left = (icd->width_max - rect->width) / 2 + icd->x_min; - - if (rect->top + rect->height > icd->height_max) - rect->top = (icd->height_max - rect->height) / 2 + icd->y_min; - - width = rect->width * xskip; - height = rect->height * yskip; - left = rect->left * xskip; - top = rect->top * yskip; - xbin = min(xskip, (u16)3); ybin = min(yskip, (u16)3); - dev_dbg(&icd->dev, "xskip %u, width %u/%u, yskip %u, height %u/%u\n", - xskip, width, rect->width, yskip, height, rect->height); - - /* Could just do roundup(rect->left, [xy]bin * 2); but this is cheaper */ + /* + * Could just do roundup(rect->left, [xy]bin * 2); but this is cheaper. + * There is always a valid suitably aligned value. The worst case is + * xbin = 3, width = 2048. Then we will start at 36, the last read out + * pixel will be 2083, which is < 2085 - first black pixel. + * + * MT9T031 datasheet imposes window left border alignment, depending on + * the selected xskip. Failing to conform to this requirement produces + * dark horizontal stripes in the image. However, even obeying to this + * requirement doesn't eliminate the stripes in all configurations. They + * appear "locally reproducibly," but can differ between tests under + * different lighting conditions. + */ switch (xbin) { - case 2: - left = (left + 3) & ~3; + case 1: + rect->left &= ~1; break; - case 3: - left = roundup(left, 6); - } - - switch (ybin) { case 2: - top = (top + 3) & ~3; + rect->left &= ~3; break; case 3: - top = roundup(top, 6); + rect->left = rect->left > roundup(MT9T031_COLUMN_SKIP, 6) ? + (rect->left / 6) * 6 : roundup(MT9T031_COLUMN_SKIP, 6); } + rect->top &= ~1; + + dev_dbg(&client->dev, "skip %u:%u, rect %ux%u@%u:%u\n", + xskip, yskip, rect->width, rect->height, rect->left, rect->top); + /* Disable register update, reconfigure atomically */ ret = reg_set(client, MT9T031_OUTPUT_CONTROL, 1); if (ret < 0) @@ -299,29 +288,30 @@ static int mt9t031_set_params(struct soc_camera_device *icd, ret = reg_write(client, MT9T031_ROW_ADDRESS_MODE, ((ybin - 1) << 4) | (yskip - 1)); } - dev_dbg(&icd->dev, "new physical left %u, top %u\n", left, top); + dev_dbg(&client->dev, "new physical left %u, top %u\n", + rect->left, rect->top); /* The caller provides a supported format, as guaranteed by * icd->try_fmt_cap(), soc_camera_s_crop() and soc_camera_cropcap() */ if (ret >= 0) - ret = reg_write(client, MT9T031_COLUMN_START, left); + ret = reg_write(client, MT9T031_COLUMN_START, rect->left); if (ret >= 0) - ret = reg_write(client, MT9T031_ROW_START, top); + ret = reg_write(client, MT9T031_ROW_START, rect->top); if (ret >= 0) - ret = reg_write(client, MT9T031_WINDOW_WIDTH, width - 1); + ret = reg_write(client, MT9T031_WINDOW_WIDTH, rect->width - 1); if (ret >= 0) ret = reg_write(client, MT9T031_WINDOW_HEIGHT, - height + icd->y_skip_top - 1); + rect->height + icd->y_skip_top - 1); if (ret >= 0 && mt9t031->autoexposure) { - ret = set_shutter(client, height + icd->y_skip_top + vblank); + unsigned int total_h = rect->height + icd->y_skip_top + vblank; + ret = set_shutter(client, total_h); if (ret >= 0) { const u32 shutter_max = MT9T031_MAX_HEIGHT + vblank; const struct v4l2_queryctrl *qctrl = soc_camera_find_qctrl(icd->ops, V4L2_CID_EXPOSURE); - icd->exposure = (shutter_max / 2 + (height + - icd->y_skip_top + vblank - 1) * - (qctrl->maximum - qctrl->minimum)) / + mt9t031->exposure = (shutter_max / 2 + (total_h - 1) * + (qctrl->maximum - qctrl->minimum)) / shutter_max + qctrl->minimum; } } @@ -330,58 +320,99 @@ static int mt9t031_set_params(struct soc_camera_device *icd, if (ret >= 0) ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 1); + if (ret >= 0) { + mt9t031->rect = *rect; + mt9t031->xskip = xskip; + mt9t031->yskip = yskip; + } + return ret < 0 ? ret : 0; } -static int mt9t031_set_crop(struct soc_camera_device *icd, - struct v4l2_rect *rect) +static int mt9t031_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) { - struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd); + struct v4l2_rect rect = a->c; + struct i2c_client *client = sd->priv; + struct mt9t031 *mt9t031 = to_mt9t031(client); + struct soc_camera_device *icd = client->dev.platform_data; + + rect.width = ALIGN(rect.width, 2); + rect.height = ALIGN(rect.height, 2); + + soc_camera_limit_side(&rect.left, &rect.width, + MT9T031_COLUMN_SKIP, MT9T031_MIN_WIDTH, MT9T031_MAX_WIDTH); + + soc_camera_limit_side(&rect.top, &rect.height, + MT9T031_ROW_SKIP, MT9T031_MIN_HEIGHT, MT9T031_MAX_HEIGHT); - /* CROP - no change in scaling, or in limits */ - return mt9t031_set_params(icd, rect, mt9t031->xskip, mt9t031->yskip); + return mt9t031_set_params(icd, &rect, mt9t031->xskip, mt9t031->yskip); } -static int mt9t031_set_fmt(struct soc_camera_device *icd, - struct v4l2_format *f) +static int mt9t031_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) { - struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd); - int ret; - u16 xskip, yskip; - struct v4l2_rect rect = { - .left = icd->x_current, - .top = icd->y_current, - .width = f->fmt.pix.width, - .height = f->fmt.pix.height, - }; + struct i2c_client *client = sd->priv; + struct mt9t031 *mt9t031 = to_mt9t031(client); - /* - * try_fmt has put rectangle within limits. - * S_FMT - use binning and skipping for scaling, recalculate - * limits, used for cropping - */ - /* Is this more optimal than just a division? */ - for (xskip = 8; xskip > 1; xskip--) - if (rect.width * xskip <= MT9T031_MAX_WIDTH) - break; + a->c = mt9t031->rect; + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - for (yskip = 8; yskip > 1; yskip--) - if (rect.height * yskip <= MT9T031_MAX_HEIGHT) - break; + return 0; +} - recalculate_limits(icd, xskip, yskip); +static int mt9t031_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) +{ + a->bounds.left = MT9T031_COLUMN_SKIP; + a->bounds.top = MT9T031_ROW_SKIP; + a->bounds.width = MT9T031_MAX_WIDTH; + a->bounds.height = MT9T031_MAX_HEIGHT; + a->defrect = a->bounds; + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + a->pixelaspect.numerator = 1; + a->pixelaspect.denominator = 1; - ret = mt9t031_set_params(icd, &rect, xskip, yskip); - if (!ret) { - mt9t031->xskip = xskip; - mt9t031->yskip = yskip; - } + return 0; +} - return ret; +static int mt9t031_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) +{ + struct i2c_client *client = sd->priv; + struct mt9t031 *mt9t031 = to_mt9t031(client); + struct v4l2_pix_format *pix = &f->fmt.pix; + + pix->width = mt9t031->rect.width / mt9t031->xskip; + pix->height = mt9t031->rect.height / mt9t031->yskip; + pix->pixelformat = V4L2_PIX_FMT_SGRBG10; + pix->field = V4L2_FIELD_NONE; + pix->colorspace = V4L2_COLORSPACE_SRGB; + + return 0; +} + +static int mt9t031_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) +{ + struct i2c_client *client = sd->priv; + struct mt9t031 *mt9t031 = to_mt9t031(client); + struct soc_camera_device *icd = client->dev.platform_data; + struct v4l2_pix_format *pix = &f->fmt.pix; + u16 xskip, yskip; + struct v4l2_rect rect = mt9t031->rect; + + /* + * try_fmt has put width and height within limits. + * S_FMT: use binning and skipping for scaling + */ + xskip = mt9t031_skip(&rect.width, pix->width, MT9T031_MAX_WIDTH); + yskip = mt9t031_skip(&rect.height, pix->height, MT9T031_MAX_HEIGHT); + + /* mt9t031_set_params() doesn't change width and height */ + return mt9t031_set_params(icd, &rect, xskip, yskip); } -static int mt9t031_try_fmt(struct soc_camera_device *icd, - struct v4l2_format *f) +/* + * If a user window larger than sensor window is requested, we'll increase the + * sensor window. + */ +static int mt9t031_try_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) { struct v4l2_pix_format *pix = &f->fmt.pix; @@ -392,15 +423,16 @@ static int mt9t031_try_fmt(struct soc_camera_device *icd, return 0; } -static int mt9t031_get_chip_id(struct soc_camera_device *icd, - struct v4l2_dbg_chip_ident *id) +static int mt9t031_g_chip_ident(struct v4l2_subdev *sd, + struct v4l2_dbg_chip_ident *id) { - struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd); + struct i2c_client *client = sd->priv; + struct mt9t031 *mt9t031 = to_mt9t031(client); if (id->match.type != V4L2_CHIP_MATCH_I2C_ADDR) return -EINVAL; - if (id->match.addr != mt9t031->client->addr) + if (id->match.addr != client->addr) return -ENODEV; id->ident = mt9t031->model; @@ -410,10 +442,10 @@ static int mt9t031_get_chip_id(struct soc_camera_device *icd, } #ifdef CONFIG_VIDEO_ADV_DEBUG -static int mt9t031_get_register(struct soc_camera_device *icd, - struct v4l2_dbg_register *reg) +static int mt9t031_g_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) { - struct i2c_client *client = to_i2c_client(icd->control); + struct i2c_client *client = sd->priv; if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff) return -EINVAL; @@ -429,10 +461,10 @@ static int mt9t031_get_register(struct soc_camera_device *icd, return 0; } -static int mt9t031_set_register(struct soc_camera_device *icd, - struct v4l2_dbg_register *reg) +static int mt9t031_s_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) { - struct i2c_client *client = to_i2c_client(icd->control); + struct i2c_client *client = sd->priv; if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff) return -EINVAL; @@ -493,39 +525,17 @@ static const struct v4l2_queryctrl mt9t031_controls[] = { } }; -static int mt9t031_video_probe(struct soc_camera_device *); -static void mt9t031_video_remove(struct soc_camera_device *); -static int mt9t031_get_control(struct soc_camera_device *, struct v4l2_control *); -static int mt9t031_set_control(struct soc_camera_device *, struct v4l2_control *); - static struct soc_camera_ops mt9t031_ops = { - .owner = THIS_MODULE, - .probe = mt9t031_video_probe, - .remove = mt9t031_video_remove, - .init = mt9t031_init, - .release = mt9t031_release, - .start_capture = mt9t031_start_capture, - .stop_capture = mt9t031_stop_capture, - .set_crop = mt9t031_set_crop, - .set_fmt = mt9t031_set_fmt, - .try_fmt = mt9t031_try_fmt, .set_bus_param = mt9t031_set_bus_param, .query_bus_param = mt9t031_query_bus_param, .controls = mt9t031_controls, .num_controls = ARRAY_SIZE(mt9t031_controls), - .get_control = mt9t031_get_control, - .set_control = mt9t031_set_control, - .get_chip_id = mt9t031_get_chip_id, -#ifdef CONFIG_VIDEO_ADV_DEBUG - .get_register = mt9t031_get_register, - .set_register = mt9t031_set_register, -#endif }; -static int mt9t031_get_control(struct soc_camera_device *icd, struct v4l2_control *ctrl) +static int mt9t031_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd); + struct i2c_client *client = sd->priv; + struct mt9t031 *mt9t031 = to_mt9t031(client); int data; switch (ctrl->id) { @@ -544,14 +554,21 @@ static int mt9t031_get_control(struct soc_camera_device *icd, struct v4l2_contro case V4L2_CID_EXPOSURE_AUTO: ctrl->value = mt9t031->autoexposure; break; + case V4L2_CID_GAIN: + ctrl->value = mt9t031->gain; + break; + case V4L2_CID_EXPOSURE: + ctrl->value = mt9t031->exposure; + break; } return 0; } -static int mt9t031_set_control(struct soc_camera_device *icd, struct v4l2_control *ctrl) +static int mt9t031_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd); + struct i2c_client *client = sd->priv; + struct mt9t031 *mt9t031 = to_mt9t031(client); + struct soc_camera_device *icd = client->dev.platform_data; const struct v4l2_queryctrl *qctrl; int data; @@ -586,7 +603,7 @@ static int mt9t031_set_control(struct soc_camera_device *icd, struct v4l2_contro unsigned long range = qctrl->default_value - qctrl->minimum; data = ((ctrl->value - qctrl->minimum) * 8 + range / 2) / range; - dev_dbg(&icd->dev, "Setting gain %d\n", data); + dev_dbg(&client->dev, "Setting gain %d\n", data); data = reg_write(client, MT9T031_GLOBAL_GAIN, data); if (data < 0) return -EIO; @@ -606,7 +623,7 @@ static int mt9t031_set_control(struct soc_camera_device *icd, struct v4l2_contro /* calculated gain 65..1024 -> (1..120) << 8 + 0x60 */ data = (((gain - 64 + 7) * 32) & 0xff00) | 0x60; - dev_dbg(&icd->dev, "Setting gain from 0x%x to 0x%x\n", + dev_dbg(&client->dev, "Set gain from 0x%x to 0x%x\n", reg_read(client, MT9T031_GLOBAL_GAIN), data); data = reg_write(client, MT9T031_GLOBAL_GAIN, data); if (data < 0) @@ -614,7 +631,7 @@ static int mt9t031_set_control(struct soc_camera_device *icd, struct v4l2_contro } /* Success */ - icd->gain = ctrl->value; + mt9t031->gain = ctrl->value; break; case V4L2_CID_EXPOSURE: /* mt9t031 has maximum == default */ @@ -627,11 +644,11 @@ static int mt9t031_set_control(struct soc_camera_device *icd, struct v4l2_contro u32 old; get_shutter(client, &old); - dev_dbg(&icd->dev, "Setting shutter width from %u to %u\n", + dev_dbg(&client->dev, "Set shutter from %u to %u\n", old, shutter); if (set_shutter(client, shutter) < 0) return -EIO; - icd->exposure = ctrl->value; + mt9t031->exposure = ctrl->value; mt9t031->autoexposure = 0; } break; @@ -639,13 +656,14 @@ static int mt9t031_set_control(struct soc_camera_device *icd, struct v4l2_contro if (ctrl->value) { const u16 vblank = MT9T031_VERTICAL_BLANK; const u32 shutter_max = MT9T031_MAX_HEIGHT + vblank; - if (set_shutter(client, icd->height + - icd->y_skip_top + vblank) < 0) + unsigned int total_h = mt9t031->rect.height + + icd->y_skip_top + vblank; + + if (set_shutter(client, total_h) < 0) return -EIO; qctrl = soc_camera_find_qctrl(icd->ops, V4L2_CID_EXPOSURE); - icd->exposure = (shutter_max / 2 + (icd->height + - icd->y_skip_top + vblank - 1) * - (qctrl->maximum - qctrl->minimum)) / + mt9t031->exposure = (shutter_max / 2 + (total_h - 1) * + (qctrl->maximum - qctrl->minimum)) / shutter_max + qctrl->minimum; mt9t031->autoexposure = 1; } else @@ -657,22 +675,16 @@ static int mt9t031_set_control(struct soc_camera_device *icd, struct v4l2_contro /* Interface active, can use i2c. If it fails, it can indeed mean, that * this wasn't our capture interface, so, we wait for the right one */ -static int mt9t031_video_probe(struct soc_camera_device *icd) +static int mt9t031_video_probe(struct i2c_client *client) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd); + struct soc_camera_device *icd = client->dev.platform_data; + struct mt9t031 *mt9t031 = to_mt9t031(client); s32 data; int ret; - /* We must have a parent by now. And it cannot be a wrong one. - * So this entire test is completely redundant. */ - if (!icd->dev.parent || - to_soc_camera_host(icd->dev.parent)->nr != icd->iface) - return -ENODEV; - /* Enable the chip */ data = reg_write(client, MT9T031_CHIP_ENABLE, 1); - dev_dbg(&icd->dev, "write: %d\n", data); + dev_dbg(&client->dev, "write: %d\n", data); /* Read out the chip version register */ data = reg_read(client, MT9T031_CHIP_VERSION); @@ -684,44 +696,64 @@ static int mt9t031_video_probe(struct soc_camera_device *icd) icd->num_formats = ARRAY_SIZE(mt9t031_colour_formats); break; default: - ret = -ENODEV; - dev_err(&icd->dev, + dev_err(&client->dev, "No MT9T031 chip detected, register read %x\n", data); - goto ei2c; + return -ENODEV; } - dev_info(&icd->dev, "Detected a MT9T031 chip ID %x\n", data); + dev_info(&client->dev, "Detected a MT9T031 chip ID %x\n", data); - /* Now that we know the model, we can start video */ - ret = soc_camera_video_start(icd); - if (ret) - goto evstart; + ret = mt9t031_idle(client); + if (ret < 0) + dev_err(&client->dev, "Failed to initialise the camera\n"); - return 0; + /* mt9t031_idle() has reset the chip to default. */ + mt9t031->exposure = 255; + mt9t031->gain = 64; -evstart: -ei2c: return ret; } -static void mt9t031_video_remove(struct soc_camera_device *icd) -{ - struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd); +static struct v4l2_subdev_core_ops mt9t031_subdev_core_ops = { + .g_ctrl = mt9t031_g_ctrl, + .s_ctrl = mt9t031_s_ctrl, + .g_chip_ident = mt9t031_g_chip_ident, +#ifdef CONFIG_VIDEO_ADV_DEBUG + .g_register = mt9t031_g_register, + .s_register = mt9t031_s_register, +#endif +}; - dev_dbg(&icd->dev, "Video %x removed: %p, %p\n", mt9t031->client->addr, - icd->dev.parent, icd->vdev); - soc_camera_video_stop(icd); -} +static struct v4l2_subdev_video_ops mt9t031_subdev_video_ops = { + .s_stream = mt9t031_s_stream, + .s_fmt = mt9t031_s_fmt, + .g_fmt = mt9t031_g_fmt, + .try_fmt = mt9t031_try_fmt, + .s_crop = mt9t031_s_crop, + .g_crop = mt9t031_g_crop, + .cropcap = mt9t031_cropcap, +}; + +static struct v4l2_subdev_ops mt9t031_subdev_ops = { + .core = &mt9t031_subdev_core_ops, + .video = &mt9t031_subdev_video_ops, +}; static int mt9t031_probe(struct i2c_client *client, const struct i2c_device_id *did) { struct mt9t031 *mt9t031; - struct soc_camera_device *icd; + struct soc_camera_device *icd = client->dev.platform_data; struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); - struct soc_camera_link *icl = client->dev.platform_data; + struct soc_camera_link *icl; int ret; + if (!icd) { + dev_err(&client->dev, "MT9T031: missing soc-camera data!\n"); + return -EINVAL; + } + + icl = to_soc_camera_link(icd); if (!icl) { dev_err(&client->dev, "MT9T031 driver needs platform data\n"); return -EINVAL; @@ -737,23 +769,17 @@ static int mt9t031_probe(struct i2c_client *client, if (!mt9t031) return -ENOMEM; - mt9t031->client = client; - i2c_set_clientdata(client, mt9t031); + v4l2_i2c_subdev_init(&mt9t031->subdev, client, &mt9t031_subdev_ops); /* Second stage probe - when a capture adapter is there */ - icd = &mt9t031->icd; - icd->ops = &mt9t031_ops; - icd->control = &client->dev; - icd->x_min = MT9T031_COLUMN_SKIP; - icd->y_min = MT9T031_ROW_SKIP; - icd->x_current = icd->x_min; - icd->y_current = icd->y_min; - icd->width_min = MT9T031_MIN_WIDTH; - icd->width_max = MT9T031_MAX_WIDTH; - icd->height_min = MT9T031_MIN_HEIGHT; - icd->height_max = MT9T031_MAX_HEIGHT; - icd->y_skip_top = 0; - icd->iface = icl->bus_id; + icd->ops = &mt9t031_ops; + icd->y_skip_top = 0; + + mt9t031->rect.left = MT9T031_COLUMN_SKIP; + mt9t031->rect.top = MT9T031_ROW_SKIP; + mt9t031->rect.width = MT9T031_MAX_WIDTH; + mt9t031->rect.height = MT9T031_MAX_HEIGHT; + /* Simulated autoexposure. If enabled, we calculate shutter width * ourselves in the driver based on vertical blanking and frame width */ mt9t031->autoexposure = 1; @@ -761,24 +787,29 @@ static int mt9t031_probe(struct i2c_client *client, mt9t031->xskip = 1; mt9t031->yskip = 1; - ret = soc_camera_device_register(icd); - if (ret) - goto eisdr; + mt9t031_idle(client); - return 0; + ret = mt9t031_video_probe(client); + + mt9t031_disable(client); + + if (ret) { + icd->ops = NULL; + i2c_set_clientdata(client, NULL); + kfree(mt9t031); + } -eisdr: - i2c_set_clientdata(client, NULL); - kfree(mt9t031); return ret; } static int mt9t031_remove(struct i2c_client *client) { - struct mt9t031 *mt9t031 = i2c_get_clientdata(client); + struct mt9t031 *mt9t031 = to_mt9t031(client); + struct soc_camera_device *icd = client->dev.platform_data; - soc_camera_device_unregister(&mt9t031->icd); + icd->ops = NULL; i2c_set_clientdata(client, NULL); + client->driver = NULL; kfree(mt9t031); return 0; diff --git a/drivers/media/video/mt9v022.c b/drivers/media/video/mt9v022.c index dbdcc86ae50d..995607f9d3ba 100644 --- a/drivers/media/video/mt9v022.c +++ b/drivers/media/video/mt9v022.c @@ -14,13 +14,13 @@ #include #include -#include +#include #include #include /* mt9v022 i2c address 0x48, 0x4c, 0x58, 0x5c - * The platform has to define i2c_board_info - * and call i2c_register_board_info() */ + * The platform has to define ctruct i2c_board_info objects and link to them + * from struct soc_camera_link */ static char *sensor_type; module_param(sensor_type, charp, S_IRUGO); @@ -45,7 +45,7 @@ MODULE_PARM_DESC(sensor_type, "Sensor type: \"colour\" or \"monochrome\""); #define MT9V022_PIXEL_OPERATION_MODE 0x0f #define MT9V022_LED_OUT_CONTROL 0x1b #define MT9V022_ADC_MODE_CONTROL 0x1c -#define MT9V022_ANALOG_GAIN 0x34 +#define MT9V022_ANALOG_GAIN 0x35 #define MT9V022_BLACK_LEVEL_CALIB_CTRL 0x47 #define MT9V022_PIXCLK_FV_LV 0x74 #define MT9V022_DIGITAL_TEST_PATTERN 0x7f @@ -55,6 +55,13 @@ MODULE_PARM_DESC(sensor_type, "Sensor type: \"colour\" or \"monochrome\""); /* Progressive scan, master, defaults */ #define MT9V022_CHIP_CONTROL_DEFAULT 0x188 +#define MT9V022_MAX_WIDTH 752 +#define MT9V022_MAX_HEIGHT 480 +#define MT9V022_MIN_WIDTH 48 +#define MT9V022_MIN_HEIGHT 32 +#define MT9V022_COLUMN_SKIP 1 +#define MT9V022_ROW_SKIP 4 + static const struct soc_camera_data_format mt9v022_colour_formats[] = { /* Order important: first natively supported, * second supported with a GPIO extender */ @@ -85,12 +92,18 @@ static const struct soc_camera_data_format mt9v022_monochrome_formats[] = { }; struct mt9v022 { - struct i2c_client *client; - struct soc_camera_device icd; + struct v4l2_subdev subdev; + struct v4l2_rect rect; /* Sensor window */ + __u32 fourcc; int model; /* V4L2_IDENT_MT9V022* codes from v4l2-chip-ident.h */ u16 chip_control; }; +static struct mt9v022 *to_mt9v022(const struct i2c_client *client) +{ + return container_of(i2c_get_clientdata(client), struct mt9v022, subdev); +} + static int reg_read(struct i2c_client *client, const u8 reg) { s32 data = i2c_smbus_read_word_data(client, reg); @@ -125,29 +138,11 @@ static int reg_clear(struct i2c_client *client, const u8 reg, return reg_write(client, reg, ret & ~data); } -static int mt9v022_init(struct soc_camera_device *icd) +static int mt9v022_init(struct i2c_client *client) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd); - struct soc_camera_link *icl = client->dev.platform_data; + struct mt9v022 *mt9v022 = to_mt9v022(client); int ret; - if (icl->power) { - ret = icl->power(&client->dev, 1); - if (ret < 0) { - dev_err(icd->vdev->parent, - "Platform failed to power-on the camera.\n"); - return ret; - } - } - - /* - * The camera could have been already on, we hard-reset it additionally, - * if available. Soft reset is done in video_probe(). - */ - if (icl->reset) - icl->reset(&client->dev); - /* Almost the default mode: master, parallel, simultaneous, and an * undocumented bit 0x200, which is present in table 7, but not in 8, * plus snapshot mode to disable scan for now */ @@ -160,6 +155,10 @@ static int mt9v022_init(struct soc_camera_device *icd) if (!ret) /* AEC, AGC on */ ret = reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x3); + if (!ret) + ret = reg_write(client, MT9V022_ANALOG_GAIN, 16); + if (!ret) + ret = reg_write(client, MT9V022_TOTAL_SHUTTER_WIDTH, 480); if (!ret) ret = reg_write(client, MT9V022_MAX_TOTAL_SHUTTER_WIDTH, 480); if (!ret) @@ -171,37 +170,19 @@ static int mt9v022_init(struct soc_camera_device *icd) return ret; } -static int mt9v022_release(struct soc_camera_device *icd) +static int mt9v022_s_stream(struct v4l2_subdev *sd, int enable) { - struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd); - struct soc_camera_link *icl = mt9v022->client->dev.platform_data; - - if (icl->power) - icl->power(&mt9v022->client->dev, 0); - - return 0; -} + struct i2c_client *client = sd->priv; + struct mt9v022 *mt9v022 = to_mt9v022(client); -static int mt9v022_start_capture(struct soc_camera_device *icd) -{ - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd); - /* Switch to master "normal" mode */ - mt9v022->chip_control &= ~0x10; - if (reg_write(client, MT9V022_CHIP_CONTROL, - mt9v022->chip_control) < 0) - return -EIO; - return 0; -} + if (enable) + /* Switch to master "normal" mode */ + mt9v022->chip_control &= ~0x10; + else + /* Switch to snapshot mode */ + mt9v022->chip_control |= 0x10; -static int mt9v022_stop_capture(struct soc_camera_device *icd) -{ - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd); - /* Switch to snapshot mode */ - mt9v022->chip_control |= 0x10; - if (reg_write(client, MT9V022_CHIP_CONTROL, - mt9v022->chip_control) < 0) + if (reg_write(client, MT9V022_CHIP_CONTROL, mt9v022->chip_control) < 0) return -EIO; return 0; } @@ -209,9 +190,9 @@ static int mt9v022_stop_capture(struct soc_camera_device *icd) static int mt9v022_set_bus_param(struct soc_camera_device *icd, unsigned long flags) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd); - struct soc_camera_link *icl = client->dev.platform_data; + struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd)); + struct mt9v022 *mt9v022 = to_mt9v022(client); + struct soc_camera_link *icl = to_soc_camera_link(icd); unsigned int width_flag = flags & SOCAM_DATAWIDTH_MASK; int ret; u16 pixclk = 0; @@ -255,7 +236,7 @@ static int mt9v022_set_bus_param(struct soc_camera_device *icd, if (ret < 0) return ret; - dev_dbg(&icd->dev, "Calculated pixclk 0x%x, chip control 0x%x\n", + dev_dbg(&client->dev, "Calculated pixclk 0x%x, chip control 0x%x\n", pixclk, mt9v022->chip_control); return 0; @@ -263,8 +244,7 @@ static int mt9v022_set_bus_param(struct soc_camera_device *icd, static unsigned long mt9v022_query_bus_param(struct soc_camera_device *icd) { - struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd); - struct soc_camera_link *icl = mt9v022->client->dev.platform_data; + struct soc_camera_link *icl = to_soc_camera_link(icd); unsigned int width_flag; if (icl->query_bus_param) @@ -280,60 +260,121 @@ static unsigned long mt9v022_query_bus_param(struct soc_camera_device *icd) width_flag; } -static int mt9v022_set_crop(struct soc_camera_device *icd, - struct v4l2_rect *rect) +static int mt9v022_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) { - struct i2c_client *client = to_i2c_client(icd->control); + struct i2c_client *client = sd->priv; + struct mt9v022 *mt9v022 = to_mt9v022(client); + struct v4l2_rect rect = a->c; + struct soc_camera_device *icd = client->dev.platform_data; int ret; + /* Bayer format - even size lengths */ + if (mt9v022->fourcc == V4L2_PIX_FMT_SBGGR8 || + mt9v022->fourcc == V4L2_PIX_FMT_SBGGR16) { + rect.width = ALIGN(rect.width, 2); + rect.height = ALIGN(rect.height, 2); + /* Let the user play with the starting pixel */ + } + + soc_camera_limit_side(&rect.left, &rect.width, + MT9V022_COLUMN_SKIP, MT9V022_MIN_WIDTH, MT9V022_MAX_WIDTH); + + soc_camera_limit_side(&rect.top, &rect.height, + MT9V022_ROW_SKIP, MT9V022_MIN_HEIGHT, MT9V022_MAX_HEIGHT); + /* Like in example app. Contradicts the datasheet though */ ret = reg_read(client, MT9V022_AEC_AGC_ENABLE); if (ret >= 0) { if (ret & 1) /* Autoexposure */ ret = reg_write(client, MT9V022_MAX_TOTAL_SHUTTER_WIDTH, - rect->height + icd->y_skip_top + 43); + rect.height + icd->y_skip_top + 43); else ret = reg_write(client, MT9V022_TOTAL_SHUTTER_WIDTH, - rect->height + icd->y_skip_top + 43); + rect.height + icd->y_skip_top + 43); } /* Setup frame format: defaults apart from width and height */ if (!ret) - ret = reg_write(client, MT9V022_COLUMN_START, rect->left); + ret = reg_write(client, MT9V022_COLUMN_START, rect.left); if (!ret) - ret = reg_write(client, MT9V022_ROW_START, rect->top); + ret = reg_write(client, MT9V022_ROW_START, rect.top); if (!ret) /* Default 94, Phytec driver says: * "width + horizontal blank >= 660" */ ret = reg_write(client, MT9V022_HORIZONTAL_BLANKING, - rect->width > 660 - 43 ? 43 : - 660 - rect->width); + rect.width > 660 - 43 ? 43 : + 660 - rect.width); if (!ret) ret = reg_write(client, MT9V022_VERTICAL_BLANKING, 45); if (!ret) - ret = reg_write(client, MT9V022_WINDOW_WIDTH, rect->width); + ret = reg_write(client, MT9V022_WINDOW_WIDTH, rect.width); if (!ret) ret = reg_write(client, MT9V022_WINDOW_HEIGHT, - rect->height + icd->y_skip_top); + rect.height + icd->y_skip_top); if (ret < 0) return ret; - dev_dbg(&icd->dev, "Frame %ux%u pixel\n", rect->width, rect->height); + dev_dbg(&client->dev, "Frame %ux%u pixel\n", rect.width, rect.height); + + mt9v022->rect = rect; + + return 0; +} + +static int mt9v022_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) +{ + struct i2c_client *client = sd->priv; + struct mt9v022 *mt9v022 = to_mt9v022(client); + + a->c = mt9v022->rect; + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; return 0; } -static int mt9v022_set_fmt(struct soc_camera_device *icd, - struct v4l2_format *f) +static int mt9v022_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) { - struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd); + a->bounds.left = MT9V022_COLUMN_SKIP; + a->bounds.top = MT9V022_ROW_SKIP; + a->bounds.width = MT9V022_MAX_WIDTH; + a->bounds.height = MT9V022_MAX_HEIGHT; + a->defrect = a->bounds; + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + a->pixelaspect.numerator = 1; + a->pixelaspect.denominator = 1; + + return 0; +} + +static int mt9v022_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) +{ + struct i2c_client *client = sd->priv; + struct mt9v022 *mt9v022 = to_mt9v022(client); struct v4l2_pix_format *pix = &f->fmt.pix; - struct v4l2_rect rect = { - .left = icd->x_current, - .top = icd->y_current, - .width = pix->width, - .height = pix->height, + + pix->width = mt9v022->rect.width; + pix->height = mt9v022->rect.height; + pix->pixelformat = mt9v022->fourcc; + pix->field = V4L2_FIELD_NONE; + pix->colorspace = V4L2_COLORSPACE_SRGB; + + return 0; +} + +static int mt9v022_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) +{ + struct i2c_client *client = sd->priv; + struct mt9v022 *mt9v022 = to_mt9v022(client); + struct v4l2_pix_format *pix = &f->fmt.pix; + struct v4l2_crop a = { + .c = { + .left = mt9v022->rect.left, + .top = mt9v022->rect.top, + .width = pix->width, + .height = pix->height, + }, }; + int ret; /* The caller provides a supported format, as verified per call to * icd->try_fmt(), datawidth is from our supported format list */ @@ -356,30 +397,42 @@ static int mt9v022_set_fmt(struct soc_camera_device *icd, } /* No support for scaling on this camera, just crop. */ - return mt9v022_set_crop(icd, &rect); + ret = mt9v022_s_crop(sd, &a); + if (!ret) { + pix->width = mt9v022->rect.width; + pix->height = mt9v022->rect.height; + mt9v022->fourcc = pix->pixelformat; + } + + return ret; } -static int mt9v022_try_fmt(struct soc_camera_device *icd, - struct v4l2_format *f) +static int mt9v022_try_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) { + struct i2c_client *client = sd->priv; + struct soc_camera_device *icd = client->dev.platform_data; struct v4l2_pix_format *pix = &f->fmt.pix; + int align = pix->pixelformat == V4L2_PIX_FMT_SBGGR8 || + pix->pixelformat == V4L2_PIX_FMT_SBGGR16; - v4l_bound_align_image(&pix->width, 48, 752, 2 /* ? */, - &pix->height, 32 + icd->y_skip_top, - 480 + icd->y_skip_top, 0, 0); + v4l_bound_align_image(&pix->width, MT9V022_MIN_WIDTH, + MT9V022_MAX_WIDTH, align, + &pix->height, MT9V022_MIN_HEIGHT + icd->y_skip_top, + MT9V022_MAX_HEIGHT + icd->y_skip_top, align, 0); return 0; } -static int mt9v022_get_chip_id(struct soc_camera_device *icd, - struct v4l2_dbg_chip_ident *id) +static int mt9v022_g_chip_ident(struct v4l2_subdev *sd, + struct v4l2_dbg_chip_ident *id) { - struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd); + struct i2c_client *client = sd->priv; + struct mt9v022 *mt9v022 = to_mt9v022(client); if (id->match.type != V4L2_CHIP_MATCH_I2C_ADDR) return -EINVAL; - if (id->match.addr != mt9v022->client->addr) + if (id->match.addr != client->addr) return -ENODEV; id->ident = mt9v022->model; @@ -389,10 +442,10 @@ static int mt9v022_get_chip_id(struct soc_camera_device *icd, } #ifdef CONFIG_VIDEO_ADV_DEBUG -static int mt9v022_get_register(struct soc_camera_device *icd, - struct v4l2_dbg_register *reg) +static int mt9v022_g_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) { - struct i2c_client *client = to_i2c_client(icd->control); + struct i2c_client *client = sd->priv; if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff) return -EINVAL; @@ -409,10 +462,10 @@ static int mt9v022_get_register(struct soc_camera_device *icd, return 0; } -static int mt9v022_set_register(struct soc_camera_device *icd, - struct v4l2_dbg_register *reg) +static int mt9v022_s_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) { - struct i2c_client *client = to_i2c_client(icd->control); + struct i2c_client *client = sd->priv; if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff) return -EINVAL; @@ -481,41 +534,22 @@ static const struct v4l2_queryctrl mt9v022_controls[] = { } }; -static int mt9v022_video_probe(struct soc_camera_device *); -static void mt9v022_video_remove(struct soc_camera_device *); -static int mt9v022_get_control(struct soc_camera_device *, struct v4l2_control *); -static int mt9v022_set_control(struct soc_camera_device *, struct v4l2_control *); - static struct soc_camera_ops mt9v022_ops = { - .owner = THIS_MODULE, - .probe = mt9v022_video_probe, - .remove = mt9v022_video_remove, - .init = mt9v022_init, - .release = mt9v022_release, - .start_capture = mt9v022_start_capture, - .stop_capture = mt9v022_stop_capture, - .set_crop = mt9v022_set_crop, - .set_fmt = mt9v022_set_fmt, - .try_fmt = mt9v022_try_fmt, .set_bus_param = mt9v022_set_bus_param, .query_bus_param = mt9v022_query_bus_param, .controls = mt9v022_controls, .num_controls = ARRAY_SIZE(mt9v022_controls), - .get_control = mt9v022_get_control, - .set_control = mt9v022_set_control, - .get_chip_id = mt9v022_get_chip_id, -#ifdef CONFIG_VIDEO_ADV_DEBUG - .get_register = mt9v022_get_register, - .set_register = mt9v022_set_register, -#endif }; -static int mt9v022_get_control(struct soc_camera_device *icd, - struct v4l2_control *ctrl) +static int mt9v022_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) { - struct i2c_client *client = to_i2c_client(icd->control); + struct i2c_client *client = sd->priv; + const struct v4l2_queryctrl *qctrl; + unsigned long range; int data; + qctrl = soc_camera_find_qctrl(&mt9v022_ops, ctrl->id); + switch (ctrl->id) { case V4L2_CID_VFLIP: data = reg_read(client, MT9V022_READ_MODE); @@ -540,20 +574,36 @@ static int mt9v022_get_control(struct soc_camera_device *icd, if (data < 0) return -EIO; ctrl->value = !!(data & 0x2); + break; + case V4L2_CID_GAIN: + data = reg_read(client, MT9V022_ANALOG_GAIN); + if (data < 0) + return -EIO; + + range = qctrl->maximum - qctrl->minimum; + ctrl->value = ((data - 16) * range + 24) / 48 + qctrl->minimum; + + break; + case V4L2_CID_EXPOSURE: + data = reg_read(client, MT9V022_TOTAL_SHUTTER_WIDTH); + if (data < 0) + return -EIO; + + range = qctrl->maximum - qctrl->minimum; + ctrl->value = ((data - 1) * range + 239) / 479 + qctrl->minimum; + break; } return 0; } -static int mt9v022_set_control(struct soc_camera_device *icd, - struct v4l2_control *ctrl) +static int mt9v022_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) { int data; - struct i2c_client *client = to_i2c_client(icd->control); + struct i2c_client *client = sd->priv; const struct v4l2_queryctrl *qctrl; qctrl = soc_camera_find_qctrl(&mt9v022_ops, ctrl->id); - if (!qctrl) return -EINVAL; @@ -580,12 +630,9 @@ static int mt9v022_set_control(struct soc_camera_device *icd, return -EINVAL; else { unsigned long range = qctrl->maximum - qctrl->minimum; - /* Datasheet says 16 to 64. autogain only works properly - * after setting gain to maximum 14. Larger values - * produce "white fly" noise effect. On the whole, - * manually setting analog gain does no good. */ + /* Valid values 16 to 64, 32 to 64 must be even. */ unsigned long gain = ((ctrl->value - qctrl->minimum) * - 10 + range / 2) / range + 4; + 48 + range / 2) / range + 16; if (gain >= 32) gain &= ~1; /* The user wants to set gain manually, hope, she @@ -594,11 +641,10 @@ static int mt9v022_set_control(struct soc_camera_device *icd, if (reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x2) < 0) return -EIO; - dev_info(&icd->dev, "Setting gain from %d to %lu\n", - reg_read(client, MT9V022_ANALOG_GAIN), gain); + dev_dbg(&client->dev, "Setting gain from %d to %lu\n", + reg_read(client, MT9V022_ANALOG_GAIN), gain); if (reg_write(client, MT9V022_ANALOG_GAIN, gain) < 0) return -EIO; - icd->gain = ctrl->value; } break; case V4L2_CID_EXPOSURE: @@ -615,13 +661,12 @@ static int mt9v022_set_control(struct soc_camera_device *icd, if (reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x1) < 0) return -EIO; - dev_dbg(&icd->dev, "Shutter width from %d to %lu\n", + dev_dbg(&client->dev, "Shutter width from %d to %lu\n", reg_read(client, MT9V022_TOTAL_SHUTTER_WIDTH), shutter); if (reg_write(client, MT9V022_TOTAL_SHUTTER_WIDTH, shutter) < 0) return -EIO; - icd->exposure = ctrl->value; } break; case V4L2_CID_AUTOGAIN: @@ -646,11 +691,11 @@ static int mt9v022_set_control(struct soc_camera_device *icd, /* Interface active, can use i2c. If it fails, it can indeed mean, that * this wasn't our capture interface, so, we wait for the right one */ -static int mt9v022_video_probe(struct soc_camera_device *icd) +static int mt9v022_video_probe(struct soc_camera_device *icd, + struct i2c_client *client) { - struct i2c_client *client = to_i2c_client(icd->control); - struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd); - struct soc_camera_link *icl = client->dev.platform_data; + struct mt9v022 *mt9v022 = to_mt9v022(client); + struct soc_camera_link *icl = to_soc_camera_link(icd); s32 data; int ret; unsigned long flags; @@ -665,7 +710,7 @@ static int mt9v022_video_probe(struct soc_camera_device *icd) /* must be 0x1311 or 0x1313 */ if (data != 0x1311 && data != 0x1313) { ret = -ENODEV; - dev_info(&icd->dev, "No MT9V022 detected, ID register 0x%x\n", + dev_info(&client->dev, "No MT9V022 found, ID register 0x%x\n", data); goto ei2c; } @@ -677,7 +722,9 @@ static int mt9v022_video_probe(struct soc_camera_device *icd) /* 15 clock cycles */ udelay(200); if (reg_read(client, MT9V022_RESET)) { - dev_err(&icd->dev, "Resetting MT9V022 failed!\n"); + dev_err(&client->dev, "Resetting MT9V022 failed!\n"); + if (ret > 0) + ret = -EIO; goto ei2c; } @@ -694,7 +741,7 @@ static int mt9v022_video_probe(struct soc_camera_device *icd) } if (ret < 0) - goto eisis; + goto ei2c; icd->num_formats = 0; @@ -716,42 +763,70 @@ static int mt9v022_video_probe(struct soc_camera_device *icd) if (flags & SOCAM_DATAWIDTH_8) icd->num_formats++; - ret = soc_camera_video_start(icd); - if (ret < 0) - goto eisis; + mt9v022->fourcc = icd->formats->fourcc; - dev_info(&icd->dev, "Detected a MT9V022 chip ID %x, %s sensor\n", + dev_info(&client->dev, "Detected a MT9V022 chip ID %x, %s sensor\n", data, mt9v022->model == V4L2_IDENT_MT9V022IX7ATM ? "monochrome" : "colour"); - return 0; + ret = mt9v022_init(client); + if (ret < 0) + dev_err(&client->dev, "Failed to initialise the camera\n"); -eisis: ei2c: return ret; } static void mt9v022_video_remove(struct soc_camera_device *icd) { - struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd); - struct soc_camera_link *icl = mt9v022->client->dev.platform_data; + struct soc_camera_link *icl = to_soc_camera_link(icd); - dev_dbg(&icd->dev, "Video %x removed: %p, %p\n", mt9v022->client->addr, + dev_dbg(&icd->dev, "Video removed: %p, %p\n", icd->dev.parent, icd->vdev); - soc_camera_video_stop(icd); if (icl->free_bus) icl->free_bus(icl); } +static struct v4l2_subdev_core_ops mt9v022_subdev_core_ops = { + .g_ctrl = mt9v022_g_ctrl, + .s_ctrl = mt9v022_s_ctrl, + .g_chip_ident = mt9v022_g_chip_ident, +#ifdef CONFIG_VIDEO_ADV_DEBUG + .g_register = mt9v022_g_register, + .s_register = mt9v022_s_register, +#endif +}; + +static struct v4l2_subdev_video_ops mt9v022_subdev_video_ops = { + .s_stream = mt9v022_s_stream, + .s_fmt = mt9v022_s_fmt, + .g_fmt = mt9v022_g_fmt, + .try_fmt = mt9v022_try_fmt, + .s_crop = mt9v022_s_crop, + .g_crop = mt9v022_g_crop, + .cropcap = mt9v022_cropcap, +}; + +static struct v4l2_subdev_ops mt9v022_subdev_ops = { + .core = &mt9v022_subdev_core_ops, + .video = &mt9v022_subdev_video_ops, +}; + static int mt9v022_probe(struct i2c_client *client, const struct i2c_device_id *did) { struct mt9v022 *mt9v022; - struct soc_camera_device *icd; + struct soc_camera_device *icd = client->dev.platform_data; struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); - struct soc_camera_link *icl = client->dev.platform_data; + struct soc_camera_link *icl; int ret; + if (!icd) { + dev_err(&client->dev, "MT9V022: missing soc-camera data!\n"); + return -EINVAL; + } + + icl = to_soc_camera_link(icd); if (!icl) { dev_err(&client->dev, "MT9V022 driver needs platform data\n"); return -EINVAL; @@ -767,40 +842,41 @@ static int mt9v022_probe(struct i2c_client *client, if (!mt9v022) return -ENOMEM; + v4l2_i2c_subdev_init(&mt9v022->subdev, client, &mt9v022_subdev_ops); + mt9v022->chip_control = MT9V022_CHIP_CONTROL_DEFAULT; - mt9v022->client = client; - i2c_set_clientdata(client, mt9v022); - - icd = &mt9v022->icd; - icd->ops = &mt9v022_ops; - icd->control = &client->dev; - icd->x_min = 1; - icd->y_min = 4; - icd->x_current = 1; - icd->y_current = 4; - icd->width_min = 48; - icd->width_max = 752; - icd->height_min = 32; - icd->height_max = 480; - icd->y_skip_top = 1; - icd->iface = icl->bus_id; - - ret = soc_camera_device_register(icd); - if (ret) - goto eisdr; - return 0; + icd->ops = &mt9v022_ops; + /* + * MT9V022 _really_ corrupts the first read out line. + * TODO: verify on i.MX31 + */ + icd->y_skip_top = 1; + + mt9v022->rect.left = MT9V022_COLUMN_SKIP; + mt9v022->rect.top = MT9V022_ROW_SKIP; + mt9v022->rect.width = MT9V022_MAX_WIDTH; + mt9v022->rect.height = MT9V022_MAX_HEIGHT; + + ret = mt9v022_video_probe(icd, client); + if (ret) { + icd->ops = NULL; + i2c_set_clientdata(client, NULL); + kfree(mt9v022); + } -eisdr: - kfree(mt9v022); return ret; } static int mt9v022_remove(struct i2c_client *client) { - struct mt9v022 *mt9v022 = i2c_get_clientdata(client); + struct mt9v022 *mt9v022 = to_mt9v022(client); + struct soc_camera_device *icd = client->dev.platform_data; - soc_camera_device_unregister(&mt9v022->icd); + icd->ops = NULL; + mt9v022_video_remove(icd); + i2c_set_clientdata(client, NULL); + client->driver = NULL; kfree(mt9v022); return 0; diff --git a/drivers/media/video/mx1_camera.c b/drivers/media/video/mx1_camera.c index 736c31d23194..5f37952c75cf 100644 --- a/drivers/media/video/mx1_camera.c +++ b/drivers/media/video/mx1_camera.c @@ -126,7 +126,7 @@ static int mx1_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, { struct soc_camera_device *icd = vq->priv_data; - *size = icd->width * icd->height * + *size = icd->user_width * icd->user_height * ((icd->current_fmt->depth + 7) >> 3); if (!*count) @@ -135,7 +135,7 @@ static int mx1_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, while (*size * *count > MAX_VIDEO_MEM * 1024 * 1024) (*count)--; - dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); + dev_dbg(icd->dev.parent, "count=%d, size=%d\n", *count, *size); return 0; } @@ -147,7 +147,7 @@ static void free_buffer(struct videobuf_queue *vq, struct mx1_buffer *buf) BUG_ON(in_interrupt()); - dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb, vb->baddr, vb->bsize); /* This waits until this buffer is out of danger, i.e., until it is no @@ -165,7 +165,7 @@ static int mx1_videobuf_prepare(struct videobuf_queue *vq, struct mx1_buffer *buf = container_of(vb, struct mx1_buffer, vb); int ret; - dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb, vb->baddr, vb->bsize); /* Added list head initialization on alloc */ @@ -178,12 +178,12 @@ static int mx1_videobuf_prepare(struct videobuf_queue *vq, buf->inwork = 1; if (buf->fmt != icd->current_fmt || - vb->width != icd->width || - vb->height != icd->height || + vb->width != icd->user_width || + vb->height != icd->user_height || vb->field != field) { buf->fmt = icd->current_fmt; - vb->width = icd->width; - vb->height = icd->height; + vb->width = icd->user_width; + vb->height = icd->user_height; vb->field = field; vb->state = VIDEOBUF_NEEDS_INIT; } @@ -216,10 +216,11 @@ out: static int mx1_camera_setup_dma(struct mx1_camera_dev *pcdev) { struct videobuf_buffer *vbuf = &pcdev->active->vb; + struct device *dev = pcdev->icd->dev.parent; int ret; if (unlikely(!pcdev->active)) { - dev_err(pcdev->soc_host.dev, "DMA End IRQ with no active buffer\n"); + dev_err(dev, "DMA End IRQ with no active buffer\n"); return -EFAULT; } @@ -229,7 +230,7 @@ static int mx1_camera_setup_dma(struct mx1_camera_dev *pcdev) vbuf->size, pcdev->res->start + CSIRXR, DMA_MODE_READ); if (unlikely(ret)) - dev_err(pcdev->soc_host.dev, "Failed to setup DMA sg list\n"); + dev_err(dev, "Failed to setup DMA sg list\n"); return ret; } @@ -243,7 +244,7 @@ static void mx1_videobuf_queue(struct videobuf_queue *vq, struct mx1_camera_dev *pcdev = ici->priv; struct mx1_buffer *buf = container_of(vb, struct mx1_buffer, vb); - dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb, vb->baddr, vb->bsize); list_add_tail(&vb->queue, &pcdev->capture); @@ -270,22 +271,23 @@ static void mx1_videobuf_release(struct videobuf_queue *vq, struct mx1_buffer *buf = container_of(vb, struct mx1_buffer, vb); #ifdef DEBUG struct soc_camera_device *icd = vq->priv_data; + struct device *dev = icd->dev.parent; - dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb, vb->baddr, vb->bsize); switch (vb->state) { case VIDEOBUF_ACTIVE: - dev_dbg(&icd->dev, "%s (active)\n", __func__); + dev_dbg(dev, "%s (active)\n", __func__); break; case VIDEOBUF_QUEUED: - dev_dbg(&icd->dev, "%s (queued)\n", __func__); + dev_dbg(dev, "%s (queued)\n", __func__); break; case VIDEOBUF_PREPARED: - dev_dbg(&icd->dev, "%s (prepared)\n", __func__); + dev_dbg(dev, "%s (prepared)\n", __func__); break; default: - dev_dbg(&icd->dev, "%s (unknown)\n", __func__); + dev_dbg(dev, "%s (unknown)\n", __func__); break; } #endif @@ -325,6 +327,7 @@ static void mx1_camera_wakeup(struct mx1_camera_dev *pcdev, static void mx1_camera_dma_irq(int channel, void *data) { struct mx1_camera_dev *pcdev = data; + struct device *dev = pcdev->icd->dev.parent; struct mx1_buffer *buf; struct videobuf_buffer *vb; unsigned long flags; @@ -334,14 +337,14 @@ static void mx1_camera_dma_irq(int channel, void *data) imx_dma_disable(channel); if (unlikely(!pcdev->active)) { - dev_err(pcdev->soc_host.dev, "DMA End IRQ with no active buffer\n"); + dev_err(dev, "DMA End IRQ with no active buffer\n"); goto out; } vb = &pcdev->active->vb; buf = container_of(vb, struct mx1_buffer, vb); WARN_ON(buf->inwork || list_empty(&vb->queue)); - dev_dbg(pcdev->soc_host.dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb, vb->baddr, vb->bsize); mx1_camera_wakeup(pcdev, vb, buf); @@ -362,7 +365,7 @@ static void mx1_camera_init_videobuf(struct videobuf_queue *q, struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); struct mx1_camera_dev *pcdev = ici->priv; - videobuf_queue_dma_contig_init(q, &mx1_videobuf_ops, ici->dev, + videobuf_queue_dma_contig_init(q, &mx1_videobuf_ops, icd->dev.parent, &pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE, @@ -381,8 +384,9 @@ static int mclk_get_divisor(struct mx1_camera_dev *pcdev) * they get a nice Oops */ div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; - dev_dbg(pcdev->soc_host.dev, "System clock %lukHz, target freq %dkHz, " - "divisor %lu\n", lcdclk / 1000, mclk / 1000, div); + dev_dbg(pcdev->icd->dev.parent, + "System clock %lukHz, target freq %dkHz, divisor %lu\n", + lcdclk / 1000, mclk / 1000, div); return div; } @@ -391,7 +395,7 @@ static void mx1_camera_activate(struct mx1_camera_dev *pcdev) { unsigned int csicr1 = CSICR1_EN; - dev_dbg(pcdev->soc_host.dev, "Activate device\n"); + dev_dbg(pcdev->icd->dev.parent, "Activate device\n"); clk_enable(pcdev->clk); @@ -407,7 +411,7 @@ static void mx1_camera_activate(struct mx1_camera_dev *pcdev) static void mx1_camera_deactivate(struct mx1_camera_dev *pcdev) { - dev_dbg(pcdev->soc_host.dev, "Deactivate device\n"); + dev_dbg(pcdev->icd->dev.parent, "Deactivate device\n"); /* Disable all CSI interface */ __raw_writel(0x00, pcdev->base + CSICR1); @@ -428,14 +432,12 @@ static int mx1_camera_add_device(struct soc_camera_device *icd) goto ebusy; } - dev_info(&icd->dev, "MX1 Camera driver attached to camera %d\n", + dev_info(icd->dev.parent, "MX1 Camera driver attached to camera %d\n", icd->devnum); mx1_camera_activate(pcdev); - ret = icd->ops->init(icd); - if (!ret) - pcdev->icd = icd; + pcdev->icd = icd; ebusy: return ret; @@ -456,20 +458,20 @@ static void mx1_camera_remove_device(struct soc_camera_device *icd) /* Stop DMA engine */ imx_dma_disable(pcdev->dma_chan); - dev_info(&icd->dev, "MX1 Camera driver detached from camera %d\n", + dev_info(icd->dev.parent, "MX1 Camera driver detached from camera %d\n", icd->devnum); - icd->ops->release(icd); - mx1_camera_deactivate(pcdev); pcdev->icd = NULL; } static int mx1_camera_set_crop(struct soc_camera_device *icd, - struct v4l2_rect *rect) + struct v4l2_crop *a) { - return icd->ops->set_crop(icd, rect); + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + + return v4l2_subdev_call(sd, video, s_crop, a); } static int mx1_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) @@ -539,18 +541,19 @@ static int mx1_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) static int mx1_camera_set_fmt(struct soc_camera_device *icd, struct v4l2_format *f) { - struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); const struct soc_camera_format_xlate *xlate; struct v4l2_pix_format *pix = &f->fmt.pix; int ret; xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); if (!xlate) { - dev_warn(ici->dev, "Format %x not found\n", pix->pixelformat); + dev_warn(icd->dev.parent, "Format %x not found\n", + pix->pixelformat); return -EINVAL; } - ret = icd->ops->set_fmt(icd, f); + ret = v4l2_subdev_call(sd, video, s_fmt, f); if (!ret) { icd->buswidth = xlate->buswidth; icd->current_fmt = xlate->host_fmt; @@ -562,10 +565,11 @@ static int mx1_camera_set_fmt(struct soc_camera_device *icd, static int mx1_camera_try_fmt(struct soc_camera_device *icd, struct v4l2_format *f) { + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); /* TODO: limit to mx1 hardware capabilities */ /* limit to sensor capabilities */ - return icd->ops->try_fmt(icd, f); + return v4l2_subdev_call(sd, video, try_fmt, f); } static int mx1_camera_reqbufs(struct soc_camera_file *icf, @@ -737,7 +741,7 @@ static int __init mx1_camera_probe(struct platform_device *pdev) pcdev->soc_host.drv_name = DRIVER_NAME; pcdev->soc_host.ops = &mx1_soc_camera_host_ops; pcdev->soc_host.priv = pcdev; - pcdev->soc_host.dev = &pdev->dev; + pcdev->soc_host.v4l2_dev.dev = &pdev->dev; pcdev->soc_host.nr = pdev->id; err = soc_camera_host_register(&pcdev->soc_host); if (err) diff --git a/drivers/media/video/mx3_camera.c b/drivers/media/video/mx3_camera.c index 9770cb7932ca..dff2e5e2d8c6 100644 --- a/drivers/media/video/mx3_camera.c +++ b/drivers/media/video/mx3_camera.c @@ -178,7 +178,7 @@ static void free_buffer(struct videobuf_queue *vq, struct mx3_camera_buffer *buf BUG_ON(in_interrupt()); - dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb, vb->baddr, vb->bsize); /* @@ -220,7 +220,7 @@ static int mx3_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, if (!mx3_cam->idmac_channel[0]) return -EINVAL; - *size = icd->width * icd->height * bpp; + *size = icd->user_width * icd->user_height * bpp; if (!*count) *count = 32; @@ -241,7 +241,7 @@ static int mx3_videobuf_prepare(struct videobuf_queue *vq, struct mx3_camera_buffer *buf = container_of(vb, struct mx3_camera_buffer, vb); /* current_fmt _must_ always be set */ - size_t new_size = icd->width * icd->height * + size_t new_size = icd->user_width * icd->user_height * ((icd->current_fmt->depth + 7) >> 3); int ret; @@ -251,12 +251,12 @@ static int mx3_videobuf_prepare(struct videobuf_queue *vq, */ if (buf->fmt != icd->current_fmt || - vb->width != icd->width || - vb->height != icd->height || + vb->width != icd->user_width || + vb->height != icd->user_height || vb->field != field) { buf->fmt = icd->current_fmt; - vb->width = icd->width; - vb->height = icd->height; + vb->width = icd->user_width; + vb->height = icd->user_height; vb->field = field; if (vb->state != VIDEOBUF_NEEDS_INIT) free_buffer(vq, buf); @@ -354,9 +354,9 @@ static void mx3_videobuf_queue(struct videobuf_queue *vq, /* This is the configuration of one sg-element */ video->out_pixel_fmt = fourcc_to_ipu_pix(data_fmt->fourcc); - video->out_width = icd->width; - video->out_height = icd->height; - video->out_stride = icd->width; + video->out_width = icd->user_width; + video->out_height = icd->user_height; + video->out_stride = icd->user_width; #ifdef DEBUG /* helps to see what DMA actually has written */ @@ -375,7 +375,8 @@ static void mx3_videobuf_queue(struct videobuf_queue *vq, spin_unlock_irq(&mx3_cam->lock); cookie = txd->tx_submit(txd); - dev_dbg(&icd->dev, "Submitted cookie %d DMA 0x%08x\n", cookie, sg_dma_address(&buf->sg)); + dev_dbg(icd->dev.parent, "Submitted cookie %d DMA 0x%08x\n", + cookie, sg_dma_address(&buf->sg)); spin_lock_irq(&mx3_cam->lock); @@ -402,9 +403,10 @@ static void mx3_videobuf_release(struct videobuf_queue *vq, container_of(vb, struct mx3_camera_buffer, vb); unsigned long flags; - dev_dbg(&icd->dev, "Release%s DMA 0x%08x (state %d), queue %sempty\n", + dev_dbg(icd->dev.parent, + "Release%s DMA 0x%08x (state %d), queue %sempty\n", mx3_cam->active == buf ? " active" : "", sg_dma_address(&buf->sg), - vb->state, list_empty(&vb->queue) ? "" : "not "); + vb->state, list_empty(&vb->queue) ? "" : "not "); spin_lock_irqsave(&mx3_cam->lock, flags); if ((vb->state == VIDEOBUF_ACTIVE || vb->state == VIDEOBUF_QUEUED) && !list_empty(&vb->queue)) { @@ -431,7 +433,7 @@ static void mx3_camera_init_videobuf(struct videobuf_queue *q, struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); struct mx3_camera_dev *mx3_cam = ici->priv; - videobuf_queue_dma_contig_init(q, &mx3_videobuf_ops, ici->dev, + videobuf_queue_dma_contig_init(q, &mx3_videobuf_ops, icd->dev.parent, &mx3_cam->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE, @@ -484,7 +486,7 @@ static void mx3_camera_activate(struct mx3_camera_dev *mx3_cam, clk_enable(mx3_cam->clk); rate = clk_round_rate(mx3_cam->clk, mx3_cam->mclk); - dev_dbg(&icd->dev, "Set SENS_CONF to %x, rate %ld\n", conf, rate); + dev_dbg(icd->dev.parent, "Set SENS_CONF to %x, rate %ld\n", conf, rate); if (rate) clk_set_rate(mx3_cam->clk, rate); } @@ -494,29 +496,18 @@ static int mx3_camera_add_device(struct soc_camera_device *icd) { struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); struct mx3_camera_dev *mx3_cam = ici->priv; - int ret; - if (mx3_cam->icd) { - ret = -EBUSY; - goto ebusy; - } + if (mx3_cam->icd) + return -EBUSY; mx3_camera_activate(mx3_cam, icd); - ret = icd->ops->init(icd); - if (ret < 0) { - clk_disable(mx3_cam->clk); - goto einit; - } mx3_cam->icd = icd; -einit: -ebusy: - if (!ret) - dev_info(&icd->dev, "MX3 Camera driver attached to camera %d\n", - icd->devnum); + dev_info(icd->dev.parent, "MX3 Camera driver attached to camera %d\n", + icd->devnum); - return ret; + return 0; } /* Called with .video_lock held */ @@ -533,13 +524,11 @@ static void mx3_camera_remove_device(struct soc_camera_device *icd) *ichan = NULL; } - icd->ops->release(icd); - clk_disable(mx3_cam->clk); mx3_cam->icd = NULL; - dev_info(&icd->dev, "MX3 Camera driver detached from camera %d\n", + dev_info(icd->dev.parent, "MX3 Camera driver detached from camera %d\n", icd->devnum); } @@ -551,7 +540,8 @@ static bool channel_change_requested(struct soc_camera_device *icd, struct idmac_channel *ichan = mx3_cam->idmac_channel[0]; /* Do buffers have to be re-allocated or channel re-configured? */ - return ichan && rect->width * rect->height > icd->width * icd->height; + return ichan && rect->width * rect->height > + icd->user_width * icd->user_height; } static int test_platform_param(struct mx3_camera_dev *mx3_cam, @@ -599,8 +589,8 @@ static int test_platform_param(struct mx3_camera_dev *mx3_cam, *flags |= SOCAM_DATAWIDTH_4; break; default: - dev_info(mx3_cam->soc_host.dev, "Unsupported bus width %d\n", - buswidth); + dev_warn(mx3_cam->soc_host.v4l2_dev.dev, + "Unsupported bus width %d\n", buswidth); return -EINVAL; } @@ -615,7 +605,7 @@ static int mx3_camera_try_bus_param(struct soc_camera_device *icd, unsigned long bus_flags, camera_flags; int ret = test_platform_param(mx3_cam, depth, &bus_flags); - dev_dbg(ici->dev, "requested bus width %d bit: %d\n", depth, ret); + dev_dbg(icd->dev.parent, "request bus width %d bit: %d\n", depth, ret); if (ret < 0) return ret; @@ -624,7 +614,8 @@ static int mx3_camera_try_bus_param(struct soc_camera_device *icd, ret = soc_camera_bus_param_compatible(camera_flags, bus_flags); if (ret < 0) - dev_warn(&icd->dev, "Flags incompatible: camera %lx, host %lx\n", + dev_warn(icd->dev.parent, + "Flags incompatible: camera %lx, host %lx\n", camera_flags, bus_flags); return ret; @@ -638,7 +629,7 @@ static bool chan_filter(struct dma_chan *chan, void *arg) if (!rq) return false; - pdata = rq->mx3_cam->soc_host.dev->platform_data; + pdata = rq->mx3_cam->soc_host.v4l2_dev.dev->platform_data; return rq->id == chan->chan_id && pdata->dma_dev == chan->device->dev; @@ -698,7 +689,8 @@ static int mx3_camera_get_formats(struct soc_camera_device *icd, int idx, xlate->cam_fmt = icd->formats + idx; xlate->buswidth = buswidth; xlate++; - dev_dbg(ici->dev, "Providing format %s using %s\n", + dev_dbg(icd->dev.parent, + "Providing format %s using %s\n", mx3_camera_formats[0].name, icd->formats[idx].name); } @@ -710,7 +702,8 @@ static int mx3_camera_get_formats(struct soc_camera_device *icd, int idx, xlate->cam_fmt = icd->formats + idx; xlate->buswidth = buswidth; xlate++; - dev_dbg(ici->dev, "Providing format %s using %s\n", + dev_dbg(icd->dev.parent, + "Providing format %s using %s\n", mx3_camera_formats[0].name, icd->formats[idx].name); } @@ -723,7 +716,7 @@ passthrough: xlate->cam_fmt = icd->formats + idx; xlate->buswidth = buswidth; xlate++; - dev_dbg(ici->dev, + dev_dbg(icd->dev.parent, "Providing format %s in pass-through mode\n", icd->formats[idx].name); } @@ -733,13 +726,13 @@ passthrough: } static void configure_geometry(struct mx3_camera_dev *mx3_cam, - struct v4l2_rect *rect) + unsigned int width, unsigned int height) { u32 ctrl, width_field, height_field; /* Setup frame size - this cannot be changed on-the-fly... */ - width_field = rect->width - 1; - height_field = rect->height - 1; + width_field = width - 1; + height_field = height - 1; csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_SENS_FRM_SIZE); csi_reg_write(mx3_cam, width_field << 16, CSI_FLASH_STROBE_1); @@ -751,11 +744,6 @@ static void configure_geometry(struct mx3_camera_dev *mx3_cam, ctrl = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000; /* Sensor does the cropping */ csi_reg_write(mx3_cam, ctrl | 0 | (0 << 8), CSI_OUT_FRM_CTRL); - - /* - * No need to free resources here if we fail, we'll see if we need to - * do this next time we are called - */ } static int acquire_dma_channel(struct mx3_camera_dev *mx3_cam) @@ -792,25 +780,74 @@ static int acquire_dma_channel(struct mx3_camera_dev *mx3_cam) return 0; } +/* + * FIXME: learn to use stride != width, then we can keep stride properly aligned + * and support arbitrary (even) widths. + */ +static inline void stride_align(__s32 *width) +{ + if (((*width + 7) & ~7) < 4096) + *width = (*width + 7) & ~7; + else + *width = *width & ~7; +} + +/* + * As long as we don't implement host-side cropping and scaling, we can use + * default g_crop and cropcap from soc_camera.c + */ static int mx3_camera_set_crop(struct soc_camera_device *icd, - struct v4l2_rect *rect) + struct v4l2_crop *a) { + struct v4l2_rect *rect = &a->c; struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); struct mx3_camera_dev *mx3_cam = ici->priv; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + struct v4l2_format f = {.type = V4L2_BUF_TYPE_VIDEO_CAPTURE}; + struct v4l2_pix_format *pix = &f.fmt.pix; + int ret; - /* - * We now know pixel formats and can decide upon DMA-channel(s) - * So far only direct camera-to-memory is supported - */ - if (channel_change_requested(icd, rect)) { - int ret = acquire_dma_channel(mx3_cam); + soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096); + soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096); + + ret = v4l2_subdev_call(sd, video, s_crop, a); + if (ret < 0) + return ret; + + /* The capture device might have changed its output */ + ret = v4l2_subdev_call(sd, video, g_fmt, &f); + if (ret < 0) + return ret; + + if (pix->width & 7) { + /* Ouch! We can only handle 8-byte aligned width... */ + stride_align(&pix->width); + ret = v4l2_subdev_call(sd, video, s_fmt, &f); if (ret < 0) return ret; } - configure_geometry(mx3_cam, rect); + if (pix->width != icd->user_width || pix->height != icd->user_height) { + /* + * We now know pixel formats and can decide upon DMA-channel(s) + * So far only direct camera-to-memory is supported + */ + if (channel_change_requested(icd, rect)) { + int ret = acquire_dma_channel(mx3_cam); + if (ret < 0) + return ret; + } + + configure_geometry(mx3_cam, pix->width, pix->height); + } + + dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n", + pix->width, pix->height); - return icd->ops->set_crop(icd, rect); + icd->user_width = pix->width; + icd->user_height = pix->height; + + return ret; } static int mx3_camera_set_fmt(struct soc_camera_device *icd, @@ -818,22 +855,21 @@ static int mx3_camera_set_fmt(struct soc_camera_device *icd, { struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); struct mx3_camera_dev *mx3_cam = ici->priv; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); const struct soc_camera_format_xlate *xlate; struct v4l2_pix_format *pix = &f->fmt.pix; - struct v4l2_rect rect = { - .left = icd->x_current, - .top = icd->y_current, - .width = pix->width, - .height = pix->height, - }; int ret; xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); if (!xlate) { - dev_warn(ici->dev, "Format %x not found\n", pix->pixelformat); + dev_warn(icd->dev.parent, "Format %x not found\n", + pix->pixelformat); return -EINVAL; } + stride_align(&pix->width); + dev_dbg(icd->dev.parent, "Set format %dx%d\n", pix->width, pix->height); + ret = acquire_dma_channel(mx3_cam); if (ret < 0) return ret; @@ -844,21 +880,23 @@ static int mx3_camera_set_fmt(struct soc_camera_device *icd, * mxc_v4l2_s_fmt() */ - configure_geometry(mx3_cam, &rect); + configure_geometry(mx3_cam, pix->width, pix->height); - ret = icd->ops->set_fmt(icd, f); + ret = v4l2_subdev_call(sd, video, s_fmt, f); if (!ret) { icd->buswidth = xlate->buswidth; icd->current_fmt = xlate->host_fmt; } + dev_dbg(icd->dev.parent, "Sensor set %dx%d\n", pix->width, pix->height); + return ret; } static int mx3_camera_try_fmt(struct soc_camera_device *icd, struct v4l2_format *f) { - struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); const struct soc_camera_format_xlate *xlate; struct v4l2_pix_format *pix = &f->fmt.pix; __u32 pixfmt = pix->pixelformat; @@ -867,7 +905,7 @@ static int mx3_camera_try_fmt(struct soc_camera_device *icd, xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); if (pixfmt && !xlate) { - dev_warn(ici->dev, "Format %x not found\n", pixfmt); + dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt); return -EINVAL; } @@ -884,7 +922,7 @@ static int mx3_camera_try_fmt(struct soc_camera_device *icd, /* camera has to see its format, but the user the original one */ pix->pixelformat = xlate->cam_fmt->fourcc; /* limit to sensor capabilities */ - ret = icd->ops->try_fmt(icd, f); + ret = v4l2_subdev_call(sd, video, try_fmt, f); pix->pixelformat = xlate->host_fmt->fourcc; field = pix->field; @@ -892,7 +930,7 @@ static int mx3_camera_try_fmt(struct soc_camera_device *icd, if (field == V4L2_FIELD_ANY) { pix->field = V4L2_FIELD_NONE; } else if (field != V4L2_FIELD_NONE) { - dev_err(&icd->dev, "Field type %d unsupported.\n", field); + dev_err(icd->dev.parent, "Field type %d unsupported.\n", field); return -EINVAL; } @@ -931,14 +969,15 @@ static int mx3_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) u32 dw, sens_conf; int ret = test_platform_param(mx3_cam, icd->buswidth, &bus_flags); const struct soc_camera_format_xlate *xlate; + struct device *dev = icd->dev.parent; xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); if (!xlate) { - dev_warn(ici->dev, "Format %x not found\n", pixfmt); + dev_warn(dev, "Format %x not found\n", pixfmt); return -EINVAL; } - dev_dbg(ici->dev, "requested bus width %d bit: %d\n", + dev_dbg(dev, "requested bus width %d bit: %d\n", icd->buswidth, ret); if (ret < 0) @@ -947,9 +986,10 @@ static int mx3_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) camera_flags = icd->ops->query_bus_param(icd); common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags); + dev_dbg(dev, "Flags cam: 0x%lx host: 0x%lx common: 0x%lx\n", + camera_flags, bus_flags, common_flags); if (!common_flags) { - dev_dbg(ici->dev, "no common flags: camera %lx, host %lx\n", - camera_flags, bus_flags); + dev_dbg(dev, "no common flags"); return -EINVAL; } @@ -1002,8 +1042,11 @@ static int mx3_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) SOCAM_DATAWIDTH_4; ret = icd->ops->set_bus_param(icd, common_flags); - if (ret < 0) + if (ret < 0) { + dev_dbg(dev, "camera set_bus_param(%lx) returned %d\n", + common_flags, ret); return ret; + } /* * So far only gated clock mode is supported. Add a line @@ -1055,7 +1098,7 @@ static int mx3_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) csi_reg_write(mx3_cam, sens_conf | dw, CSI_SENS_CONF); - dev_dbg(ici->dev, "Set SENS_CONF to %x\n", sens_conf | dw); + dev_dbg(dev, "Set SENS_CONF to %x\n", sens_conf | dw); return 0; } @@ -1127,8 +1170,9 @@ static int __devinit mx3_camera_probe(struct platform_device *pdev) INIT_LIST_HEAD(&mx3_cam->capture); spin_lock_init(&mx3_cam->lock); - base = ioremap(res->start, res->end - res->start + 1); + base = ioremap(res->start, resource_size(res)); if (!base) { + pr_err("Couldn't map %x@%x\n", resource_size(res), res->start); err = -ENOMEM; goto eioremap; } @@ -1139,7 +1183,7 @@ static int __devinit mx3_camera_probe(struct platform_device *pdev) soc_host->drv_name = MX3_CAM_DRV_NAME; soc_host->ops = &mx3_soc_camera_host_ops; soc_host->priv = mx3_cam; - soc_host->dev = &pdev->dev; + soc_host->v4l2_dev.dev = &pdev->dev; soc_host->nr = pdev->id; err = soc_camera_host_register(soc_host); @@ -1215,3 +1259,4 @@ module_exit(mx3_camera_exit); MODULE_DESCRIPTION("i.MX3x SoC Camera Host driver"); MODULE_AUTHOR("Guennadi Liakhovetski "); MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" MX3_CAM_DRV_NAME); diff --git a/drivers/media/video/mxb.c b/drivers/media/video/mxb.c index 35890e8b2431..3454070e63f0 100644 --- a/drivers/media/video/mxb.c +++ b/drivers/media/video/mxb.c @@ -186,19 +186,19 @@ static int mxb_probe(struct saa7146_dev *dev) } mxb->saa7111a = v4l2_i2c_new_subdev(&dev->v4l2_dev, &mxb->i2c_adapter, - "saa7115", "saa7111", I2C_SAA7111A); + "saa7115", "saa7111", I2C_SAA7111A, NULL); mxb->tea6420_1 = v4l2_i2c_new_subdev(&dev->v4l2_dev, &mxb->i2c_adapter, - "tea6420", "tea6420", I2C_TEA6420_1); + "tea6420", "tea6420", I2C_TEA6420_1, NULL); mxb->tea6420_2 = v4l2_i2c_new_subdev(&dev->v4l2_dev, &mxb->i2c_adapter, - "tea6420", "tea6420", I2C_TEA6420_2); + "tea6420", "tea6420", I2C_TEA6420_2, NULL); mxb->tea6415c = v4l2_i2c_new_subdev(&dev->v4l2_dev, &mxb->i2c_adapter, - "tea6415c", "tea6415c", I2C_TEA6415C); + "tea6415c", "tea6415c", I2C_TEA6415C, NULL); mxb->tda9840 = v4l2_i2c_new_subdev(&dev->v4l2_dev, &mxb->i2c_adapter, - "tda9840", "tda9840", I2C_TDA9840); + "tda9840", "tda9840", I2C_TDA9840, NULL); mxb->tuner = v4l2_i2c_new_subdev(&dev->v4l2_dev, &mxb->i2c_adapter, - "tuner", "tuner", I2C_TUNER); + "tuner", "tuner", I2C_TUNER, NULL); if (v4l2_i2c_new_subdev(&dev->v4l2_dev, &mxb->i2c_adapter, - "saa5246a", "saa5246a", I2C_SAA5246A)) { + "saa5246a", "saa5246a", I2C_SAA5246A, NULL)) { printk(KERN_INFO "mxb: found teletext decoder\n"); } diff --git a/drivers/media/video/ov772x.c b/drivers/media/video/ov772x.c index 0bce255168bd..eccb40ab7fec 100644 --- a/drivers/media/video/ov772x.c +++ b/drivers/media/video/ov772x.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include @@ -382,11 +382,10 @@ struct regval_list { }; struct ov772x_color_format { - char *name; - __u32 fourcc; - u8 dsp3; - u8 com3; - u8 com7; + const struct soc_camera_data_format *format; + u8 dsp3; + u8 com3; + u8 com7; }; struct ov772x_win_size { @@ -398,14 +397,15 @@ struct ov772x_win_size { }; struct ov772x_priv { + struct v4l2_subdev subdev; struct ov772x_camera_info *info; - struct i2c_client *client; - struct soc_camera_device icd; const struct ov772x_color_format *fmt; const struct ov772x_win_size *win; int model; - unsigned int flag_vflip:1; - unsigned int flag_hflip:1; + unsigned short flag_vflip:1; + unsigned short flag_hflip:1; + /* band_filter = COM8[5] ? 256 - BDBASE : 0 */ + unsigned short band_filter; }; #define ENDMARKER { 0xff, 0xff } @@ -481,43 +481,43 @@ static const struct soc_camera_data_format ov772x_fmt_lists[] = { */ static const struct ov772x_color_format ov772x_cfmts[] = { { - SETFOURCC(YUYV), + .format = &ov772x_fmt_lists[0], .dsp3 = 0x0, .com3 = SWAP_YUV, .com7 = OFMT_YUV, }, { - SETFOURCC(YVYU), + .format = &ov772x_fmt_lists[1], .dsp3 = UV_ON, .com3 = SWAP_YUV, .com7 = OFMT_YUV, }, { - SETFOURCC(UYVY), + .format = &ov772x_fmt_lists[2], .dsp3 = 0x0, .com3 = 0x0, .com7 = OFMT_YUV, }, { - SETFOURCC(RGB555), + .format = &ov772x_fmt_lists[3], .dsp3 = 0x0, .com3 = SWAP_RGB, .com7 = FMT_RGB555 | OFMT_RGB, }, { - SETFOURCC(RGB555X), + .format = &ov772x_fmt_lists[4], .dsp3 = 0x0, .com3 = 0x0, .com7 = FMT_RGB555 | OFMT_RGB, }, { - SETFOURCC(RGB565), + .format = &ov772x_fmt_lists[5], .dsp3 = 0x0, .com3 = SWAP_RGB, .com7 = FMT_RGB565 | OFMT_RGB, }, { - SETFOURCC(RGB565X), + .format = &ov772x_fmt_lists[6], .dsp3 = 0x0, .com3 = 0x0, .com7 = FMT_RGB565 | OFMT_RGB, @@ -570,6 +570,15 @@ static const struct v4l2_queryctrl ov772x_controls[] = { .step = 1, .default_value = 0, }, + { + .id = V4L2_CID_BAND_STOP_FILTER, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Band-stop filter", + .minimum = 0, + .maximum = 256, + .step = 1, + .default_value = 0, + }, }; @@ -577,6 +586,12 @@ static const struct v4l2_queryctrl ov772x_controls[] = { * general function */ +static struct ov772x_priv *to_ov772x(const struct i2c_client *client) +{ + return container_of(i2c_get_clientdata(client), struct ov772x_priv, + subdev); +} + static int ov772x_write_array(struct i2c_client *client, const struct regval_list *vals) { @@ -617,58 +632,29 @@ static int ov772x_reset(struct i2c_client *client) * soc_camera_ops function */ -static int ov772x_init(struct soc_camera_device *icd) +static int ov772x_s_stream(struct v4l2_subdev *sd, int enable) { - struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); - int ret = 0; + struct i2c_client *client = sd->priv; + struct ov772x_priv *priv = to_ov772x(client); - if (priv->info->link.power) { - ret = priv->info->link.power(&priv->client->dev, 1); - if (ret < 0) - return ret; + if (!enable) { + ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, SOFT_SLEEP_MODE); + return 0; } - if (priv->info->link.reset) - ret = priv->info->link.reset(&priv->client->dev); - - return ret; -} - -static int ov772x_release(struct soc_camera_device *icd) -{ - struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); - int ret = 0; - - if (priv->info->link.power) - ret = priv->info->link.power(&priv->client->dev, 0); - - return ret; -} - -static int ov772x_start_capture(struct soc_camera_device *icd) -{ - struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); - if (!priv->win || !priv->fmt) { - dev_err(&icd->dev, "norm or win select error\n"); + dev_err(&client->dev, "norm or win select error\n"); return -EPERM; } - ov772x_mask_set(priv->client, COM2, SOFT_SLEEP_MODE, 0); + ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, 0); - dev_dbg(&icd->dev, - "format %s, win %s\n", priv->fmt->name, priv->win->name); + dev_dbg(&client->dev, "format %s, win %s\n", + priv->fmt->format->name, priv->win->name); return 0; } -static int ov772x_stop_capture(struct soc_camera_device *icd) -{ - struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); - ov772x_mask_set(priv->client, COM2, SOFT_SLEEP_MODE, SOFT_SLEEP_MODE); - return 0; -} - static int ov772x_set_bus_param(struct soc_camera_device *icd, unsigned long flags) { @@ -677,8 +663,9 @@ static int ov772x_set_bus_param(struct soc_camera_device *icd, static unsigned long ov772x_query_bus_param(struct soc_camera_device *icd) { - struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); - struct soc_camera_link *icl = &priv->info->link; + struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd)); + struct ov772x_priv *priv = i2c_get_clientdata(client); + struct soc_camera_link *icl = to_soc_camera_link(icd); unsigned long flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_MASTER | SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_DATA_ACTIVE_HIGH | priv->info->buswidth; @@ -686,10 +673,10 @@ static unsigned long ov772x_query_bus_param(struct soc_camera_device *icd) return soc_camera_apply_sensor_flags(icl, flags); } -static int ov772x_get_control(struct soc_camera_device *icd, - struct v4l2_control *ctrl) +static int ov772x_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) { - struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); + struct i2c_client *client = sd->priv; + struct ov772x_priv *priv = to_ov772x(client); switch (ctrl->id) { case V4L2_CID_VFLIP: @@ -698,14 +685,17 @@ static int ov772x_get_control(struct soc_camera_device *icd, case V4L2_CID_HFLIP: ctrl->value = priv->flag_hflip; break; + case V4L2_CID_BAND_STOP_FILTER: + ctrl->value = priv->band_filter; + break; } return 0; } -static int ov772x_set_control(struct soc_camera_device *icd, - struct v4l2_control *ctrl) +static int ov772x_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) { - struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); + struct i2c_client *client = sd->priv; + struct ov772x_priv *priv = to_ov772x(client); int ret = 0; u8 val; @@ -715,24 +705,48 @@ static int ov772x_set_control(struct soc_camera_device *icd, priv->flag_vflip = ctrl->value; if (priv->info->flags & OV772X_FLAG_VFLIP) val ^= VFLIP_IMG; - ret = ov772x_mask_set(priv->client, COM3, VFLIP_IMG, val); + ret = ov772x_mask_set(client, COM3, VFLIP_IMG, val); break; case V4L2_CID_HFLIP: val = ctrl->value ? HFLIP_IMG : 0x00; priv->flag_hflip = ctrl->value; if (priv->info->flags & OV772X_FLAG_HFLIP) val ^= HFLIP_IMG; - ret = ov772x_mask_set(priv->client, COM3, HFLIP_IMG, val); + ret = ov772x_mask_set(client, COM3, HFLIP_IMG, val); + break; + case V4L2_CID_BAND_STOP_FILTER: + if ((unsigned)ctrl->value > 256) + ctrl->value = 256; + if (ctrl->value == priv->band_filter) + break; + if (!ctrl->value) { + /* Switch the filter off, it is on now */ + ret = ov772x_mask_set(client, BDBASE, 0xff, 0xff); + if (!ret) + ret = ov772x_mask_set(client, COM8, + BNDF_ON_OFF, 0); + } else { + /* Switch the filter on, set AEC low limit */ + val = 256 - ctrl->value; + ret = ov772x_mask_set(client, COM8, + BNDF_ON_OFF, BNDF_ON_OFF); + if (!ret) + ret = ov772x_mask_set(client, BDBASE, + 0xff, val); + } + if (!ret) + priv->band_filter = ctrl->value; break; } return ret; } -static int ov772x_get_chip_id(struct soc_camera_device *icd, - struct v4l2_dbg_chip_ident *id) +static int ov772x_g_chip_ident(struct v4l2_subdev *sd, + struct v4l2_dbg_chip_ident *id) { - struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); + struct i2c_client *client = sd->priv; + struct ov772x_priv *priv = to_ov772x(client); id->ident = priv->model; id->revision = 0; @@ -741,17 +755,17 @@ static int ov772x_get_chip_id(struct soc_camera_device *icd, } #ifdef CONFIG_VIDEO_ADV_DEBUG -static int ov772x_get_register(struct soc_camera_device *icd, - struct v4l2_dbg_register *reg) +static int ov772x_g_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) { - struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); - int ret; + struct i2c_client *client = sd->priv; + int ret; reg->size = 1; if (reg->reg > 0xff) return -EINVAL; - ret = i2c_smbus_read_byte_data(priv->client, reg->reg); + ret = i2c_smbus_read_byte_data(client, reg->reg); if (ret < 0) return ret; @@ -760,21 +774,20 @@ static int ov772x_get_register(struct soc_camera_device *icd, return 0; } -static int ov772x_set_register(struct soc_camera_device *icd, - struct v4l2_dbg_register *reg) +static int ov772x_s_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) { - struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); + struct i2c_client *client = sd->priv; if (reg->reg > 0xff || reg->val > 0xff) return -EINVAL; - return i2c_smbus_write_byte_data(priv->client, reg->reg, reg->val); + return i2c_smbus_write_byte_data(client, reg->reg, reg->val); } #endif -static const struct ov772x_win_size* -ov772x_select_win(u32 width, u32 height) +static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height) { __u32 diff; const struct ov772x_win_size *win; @@ -793,9 +806,10 @@ ov772x_select_win(u32 width, u32 height) return win; } -static int ov772x_set_params(struct ov772x_priv *priv, u32 width, u32 height, - u32 pixfmt) +static int ov772x_set_params(struct i2c_client *client, + u32 *width, u32 *height, u32 pixfmt) { + struct ov772x_priv *priv = to_ov772x(client); int ret = -EINVAL; u8 val; int i; @@ -805,7 +819,7 @@ static int ov772x_set_params(struct ov772x_priv *priv, u32 width, u32 height, */ priv->fmt = NULL; for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) { - if (pixfmt == ov772x_cfmts[i].fourcc) { + if (pixfmt == ov772x_cfmts[i].format->fourcc) { priv->fmt = ov772x_cfmts + i; break; } @@ -816,12 +830,12 @@ static int ov772x_set_params(struct ov772x_priv *priv, u32 width, u32 height, /* * select win */ - priv->win = ov772x_select_win(width, height); + priv->win = ov772x_select_win(*width, *height); /* * reset hardware */ - ov772x_reset(priv->client); + ov772x_reset(client); /* * Edge Ctrl @@ -835,17 +849,17 @@ static int ov772x_set_params(struct ov772x_priv *priv, u32 width, u32 height, * Remove it when manual mode. */ - ret = ov772x_mask_set(priv->client, DSPAUTO, EDGE_ACTRL, 0x00); + ret = ov772x_mask_set(client, DSPAUTO, EDGE_ACTRL, 0x00); if (ret < 0) goto ov772x_set_fmt_error; - ret = ov772x_mask_set(priv->client, + ret = ov772x_mask_set(client, EDGE_TRSHLD, EDGE_THRESHOLD_MASK, priv->info->edgectrl.threshold); if (ret < 0) goto ov772x_set_fmt_error; - ret = ov772x_mask_set(priv->client, + ret = ov772x_mask_set(client, EDGE_STRNGT, EDGE_STRENGTH_MASK, priv->info->edgectrl.strength); if (ret < 0) @@ -857,13 +871,13 @@ static int ov772x_set_params(struct ov772x_priv *priv, u32 width, u32 height, * * set upper and lower limit */ - ret = ov772x_mask_set(priv->client, + ret = ov772x_mask_set(client, EDGE_UPPER, EDGE_UPPER_MASK, priv->info->edgectrl.upper); if (ret < 0) goto ov772x_set_fmt_error; - ret = ov772x_mask_set(priv->client, + ret = ov772x_mask_set(client, EDGE_LOWER, EDGE_LOWER_MASK, priv->info->edgectrl.lower); if (ret < 0) @@ -873,7 +887,7 @@ static int ov772x_set_params(struct ov772x_priv *priv, u32 width, u32 height, /* * set size format */ - ret = ov772x_write_array(priv->client, priv->win->regs); + ret = ov772x_write_array(client, priv->win->regs); if (ret < 0) goto ov772x_set_fmt_error; @@ -882,7 +896,7 @@ static int ov772x_set_params(struct ov772x_priv *priv, u32 width, u32 height, */ val = priv->fmt->dsp3; if (val) { - ret = ov772x_mask_set(priv->client, + ret = ov772x_mask_set(client, DSP_CTRL3, UV_MASK, val); if (ret < 0) goto ov772x_set_fmt_error; @@ -901,7 +915,7 @@ static int ov772x_set_params(struct ov772x_priv *priv, u32 width, u32 height, if (priv->flag_hflip) val ^= HFLIP_IMG; - ret = ov772x_mask_set(priv->client, + ret = ov772x_mask_set(client, COM3, SWAP_MASK | IMG_MASK, val); if (ret < 0) goto ov772x_set_fmt_error; @@ -910,47 +924,99 @@ static int ov772x_set_params(struct ov772x_priv *priv, u32 width, u32 height, * set COM7 */ val = priv->win->com7_bit | priv->fmt->com7; - ret = ov772x_mask_set(priv->client, + ret = ov772x_mask_set(client, COM7, (SLCT_MASK | FMT_MASK | OFMT_MASK), val); if (ret < 0) goto ov772x_set_fmt_error; + /* + * set COM8 + */ + if (priv->band_filter) { + ret = ov772x_mask_set(client, COM8, BNDF_ON_OFF, 1); + if (!ret) + ret = ov772x_mask_set(client, BDBASE, + 0xff, 256 - priv->band_filter); + if (ret < 0) + goto ov772x_set_fmt_error; + } + + *width = priv->win->width; + *height = priv->win->height; + return ret; ov772x_set_fmt_error: - ov772x_reset(priv->client); + ov772x_reset(client); priv->win = NULL; priv->fmt = NULL; return ret; } -static int ov772x_set_crop(struct soc_camera_device *icd, - struct v4l2_rect *rect) +static int ov772x_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) { - struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); + a->c.left = 0; + a->c.top = 0; + a->c.width = VGA_WIDTH; + a->c.height = VGA_HEIGHT; + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - if (!priv->fmt) - return -EINVAL; + return 0; +} - return ov772x_set_params(priv, rect->width, rect->height, - priv->fmt->fourcc); +static int ov772x_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) +{ + a->bounds.left = 0; + a->bounds.top = 0; + a->bounds.width = VGA_WIDTH; + a->bounds.height = VGA_HEIGHT; + a->defrect = a->bounds; + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + a->pixelaspect.numerator = 1; + a->pixelaspect.denominator = 1; + + return 0; } -static int ov772x_set_fmt(struct soc_camera_device *icd, - struct v4l2_format *f) +static int ov772x_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) +{ + struct i2c_client *client = sd->priv; + struct ov772x_priv *priv = to_ov772x(client); + struct v4l2_pix_format *pix = &f->fmt.pix; + + if (!priv->win || !priv->fmt) { + u32 width = VGA_WIDTH, height = VGA_HEIGHT; + int ret = ov772x_set_params(client, &width, &height, + V4L2_PIX_FMT_YUYV); + if (ret < 0) + return ret; + } + + f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + pix->width = priv->win->width; + pix->height = priv->win->height; + pix->pixelformat = priv->fmt->format->fourcc; + pix->colorspace = priv->fmt->format->colorspace; + pix->field = V4L2_FIELD_NONE; + + return 0; +} + +static int ov772x_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) { - struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); + struct i2c_client *client = sd->priv; struct v4l2_pix_format *pix = &f->fmt.pix; - return ov772x_set_params(priv, pix->width, pix->height, + return ov772x_set_params(client, &pix->width, &pix->height, pix->pixelformat); } -static int ov772x_try_fmt(struct soc_camera_device *icd, - struct v4l2_format *f) +static int ov772x_try_fmt(struct v4l2_subdev *sd, + struct v4l2_format *f) { struct v4l2_pix_format *pix = &f->fmt.pix; const struct ov772x_win_size *win; @@ -967,9 +1033,10 @@ static int ov772x_try_fmt(struct soc_camera_device *icd, return 0; } -static int ov772x_video_probe(struct soc_camera_device *icd) +static int ov772x_video_probe(struct soc_camera_device *icd, + struct i2c_client *client) { - struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); + struct ov772x_priv *priv = to_ov772x(client); u8 pid, ver; const char *devname; @@ -986,7 +1053,7 @@ static int ov772x_video_probe(struct soc_camera_device *icd) */ if (SOCAM_DATAWIDTH_10 != priv->info->buswidth && SOCAM_DATAWIDTH_8 != priv->info->buswidth) { - dev_err(&icd->dev, "bus width error\n"); + dev_err(&client->dev, "bus width error\n"); return -ENODEV; } @@ -996,8 +1063,8 @@ static int ov772x_video_probe(struct soc_camera_device *icd) /* * check and show product ID and manufacturer ID */ - pid = i2c_smbus_read_byte_data(priv->client, PID); - ver = i2c_smbus_read_byte_data(priv->client, VER); + pid = i2c_smbus_read_byte_data(client, PID); + ver = i2c_smbus_read_byte_data(client, VER); switch (VERSION(pid, ver)) { case OV7720: @@ -1009,69 +1076,77 @@ static int ov772x_video_probe(struct soc_camera_device *icd) priv->model = V4L2_IDENT_OV7725; break; default: - dev_err(&icd->dev, + dev_err(&client->dev, "Product ID error %x:%x\n", pid, ver); return -ENODEV; } - dev_info(&icd->dev, + dev_info(&client->dev, "%s Product ID %0x:%0x Manufacturer ID %x:%x\n", devname, pid, ver, - i2c_smbus_read_byte_data(priv->client, MIDH), - i2c_smbus_read_byte_data(priv->client, MIDL)); - - return soc_camera_video_start(icd); -} + i2c_smbus_read_byte_data(client, MIDH), + i2c_smbus_read_byte_data(client, MIDL)); -static void ov772x_video_remove(struct soc_camera_device *icd) -{ - soc_camera_video_stop(icd); + return 0; } static struct soc_camera_ops ov772x_ops = { - .owner = THIS_MODULE, - .probe = ov772x_video_probe, - .remove = ov772x_video_remove, - .init = ov772x_init, - .release = ov772x_release, - .start_capture = ov772x_start_capture, - .stop_capture = ov772x_stop_capture, - .set_crop = ov772x_set_crop, - .set_fmt = ov772x_set_fmt, - .try_fmt = ov772x_try_fmt, .set_bus_param = ov772x_set_bus_param, .query_bus_param = ov772x_query_bus_param, .controls = ov772x_controls, .num_controls = ARRAY_SIZE(ov772x_controls), - .get_control = ov772x_get_control, - .set_control = ov772x_set_control, - .get_chip_id = ov772x_get_chip_id, +}; + +static struct v4l2_subdev_core_ops ov772x_subdev_core_ops = { + .g_ctrl = ov772x_g_ctrl, + .s_ctrl = ov772x_s_ctrl, + .g_chip_ident = ov772x_g_chip_ident, #ifdef CONFIG_VIDEO_ADV_DEBUG - .get_register = ov772x_get_register, - .set_register = ov772x_set_register, + .g_register = ov772x_g_register, + .s_register = ov772x_s_register, #endif }; +static struct v4l2_subdev_video_ops ov772x_subdev_video_ops = { + .s_stream = ov772x_s_stream, + .g_fmt = ov772x_g_fmt, + .s_fmt = ov772x_s_fmt, + .try_fmt = ov772x_try_fmt, + .cropcap = ov772x_cropcap, + .g_crop = ov772x_g_crop, +}; + +static struct v4l2_subdev_ops ov772x_subdev_ops = { + .core = &ov772x_subdev_core_ops, + .video = &ov772x_subdev_video_ops, +}; + /* * i2c_driver function */ static int ov772x_probe(struct i2c_client *client, - const struct i2c_device_id *did) + const struct i2c_device_id *did) { struct ov772x_priv *priv; struct ov772x_camera_info *info; - struct soc_camera_device *icd; + struct soc_camera_device *icd = client->dev.platform_data; struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); + struct soc_camera_link *icl; int ret; - if (!client->dev.platform_data) + if (!icd) { + dev_err(&client->dev, "OV772X: missing soc-camera data!\n"); return -EINVAL; + } - info = container_of(client->dev.platform_data, - struct ov772x_camera_info, link); + icl = to_soc_camera_link(icd); + if (!icl) + return -EINVAL; + + info = container_of(icl, struct ov772x_camera_info, link); if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { dev_err(&adapter->dev, @@ -1084,20 +1159,15 @@ static int ov772x_probe(struct i2c_client *client, if (!priv) return -ENOMEM; - priv->info = info; - priv->client = client; - i2c_set_clientdata(client, priv); + priv->info = info; - icd = &priv->icd; - icd->ops = &ov772x_ops; - icd->control = &client->dev; - icd->width_max = MAX_WIDTH; - icd->height_max = MAX_HEIGHT; - icd->iface = priv->info->link.bus_id; + v4l2_i2c_subdev_init(&priv->subdev, client, &ov772x_subdev_ops); - ret = soc_camera_device_register(icd); + icd->ops = &ov772x_ops; + ret = ov772x_video_probe(icd, client); if (ret) { + icd->ops = NULL; i2c_set_clientdata(client, NULL); kfree(priv); } @@ -1107,9 +1177,10 @@ static int ov772x_probe(struct i2c_client *client, static int ov772x_remove(struct i2c_client *client) { - struct ov772x_priv *priv = i2c_get_clientdata(client); + struct ov772x_priv *priv = to_ov772x(client); + struct soc_camera_device *icd = client->dev.platform_data; - soc_camera_device_unregister(&priv->icd); + icd->ops = NULL; i2c_set_clientdata(client, NULL); kfree(priv); return 0; diff --git a/drivers/media/video/pvrusb2/pvrusb2-devattr.c b/drivers/media/video/pvrusb2/pvrusb2-devattr.c index 336a20eded0f..e4d7c13cab87 100644 --- a/drivers/media/video/pvrusb2/pvrusb2-devattr.c +++ b/drivers/media/video/pvrusb2/pvrusb2-devattr.c @@ -298,6 +298,7 @@ static struct tda829x_config tda829x_no_probe = { static struct tda18271_config hauppauge_tda18271_dvb_config = { .gate = TDA18271_GATE_ANALOG, + .output_opt = TDA18271_OUTPUT_LT_OFF, }; static int pvr2_tda10048_attach(struct pvr2_dvb_adapter *adap) @@ -393,6 +394,7 @@ static struct tda18271_std_map hauppauge_tda18271_std_map = { static struct tda18271_config hauppauge_tda18271_config = { .std_map = &hauppauge_tda18271_std_map, .gate = TDA18271_GATE_ANALOG, + .output_opt = TDA18271_OUTPUT_LT_OFF, }; static int pvr2_s5h1409_attach(struct pvr2_dvb_adapter *adap) diff --git a/drivers/media/video/pvrusb2/pvrusb2-hdw.c b/drivers/media/video/pvrusb2/pvrusb2-hdw.c index cbc388729d77..13639b302700 100644 --- a/drivers/media/video/pvrusb2/pvrusb2-hdw.c +++ b/drivers/media/video/pvrusb2/pvrusb2-hdw.c @@ -2063,8 +2063,8 @@ static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw, return -EINVAL; } - /* Note how the 2nd and 3rd arguments are the same for both - * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev(). Why? + /* Note how the 2nd and 3rd arguments are the same for + * v4l2_i2c_new_subdev(). Why? * Well the 2nd argument is the module name to load, while the 3rd * argument is documented in the framework as being the "chipid" - * and every other place where I can find examples of this, the @@ -2077,15 +2077,15 @@ static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw, mid, i2caddr[0]); sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap, fname, fname, - i2caddr[0]); + i2caddr[0], NULL); } else { pvr2_trace(PVR2_TRACE_INIT, "Module ID %u:" " Setting up with address probe list", mid); - sd = v4l2_i2c_new_probed_subdev(&hdw->v4l2_dev, &hdw->i2c_adap, + sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap, fname, fname, - i2caddr); + 0, i2caddr); } if (!sd) { diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c index 016bb45ba0c3..6952e9602d5d 100644 --- a/drivers/media/video/pxa_camera.c +++ b/drivers/media/video/pxa_camera.c @@ -225,6 +225,10 @@ struct pxa_camera_dev { u32 save_cicr[5]; }; +struct pxa_cam { + unsigned long flags; +}; + static const char *pxa_cam_driver_description = "PXA_Camera"; static unsigned int vid_limit = 16; /* Video memory limit, in Mb */ @@ -237,9 +241,9 @@ static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, { struct soc_camera_device *icd = vq->priv_data; - dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); + dev_dbg(icd->dev.parent, "count=%d, size=%d\n", *count, *size); - *size = roundup(icd->width * icd->height * + *size = roundup(icd->user_width * icd->user_height * ((icd->current_fmt->depth + 7) >> 3), 8); if (0 == *count) @@ -259,7 +263,7 @@ static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf) BUG_ON(in_interrupt()); - dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__, &buf->vb, buf->vb.baddr, buf->vb.bsize); /* This waits until this buffer is out of danger, i.e., until it is no @@ -270,7 +274,8 @@ static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf) for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) { if (buf->dmas[i].sg_cpu) - dma_free_coherent(ici->dev, buf->dmas[i].sg_size, + dma_free_coherent(ici->v4l2_dev.dev, + buf->dmas[i].sg_size, buf->dmas[i].sg_cpu, buf->dmas[i].sg_dma); buf->dmas[i].sg_cpu = NULL; @@ -325,19 +330,20 @@ static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, struct scatterlist **sg_first, int *sg_first_ofs) { struct pxa_cam_dma *pxa_dma = &buf->dmas[channel]; + struct device *dev = pcdev->soc_host.v4l2_dev.dev; struct scatterlist *sg; int i, offset, sglen; int dma_len = 0, xfer_len = 0; if (pxa_dma->sg_cpu) - dma_free_coherent(pcdev->soc_host.dev, pxa_dma->sg_size, + dma_free_coherent(dev, pxa_dma->sg_size, pxa_dma->sg_cpu, pxa_dma->sg_dma); sglen = calculate_dma_sglen(*sg_first, dma->sglen, *sg_first_ofs, size); pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc); - pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->soc_host.dev, pxa_dma->sg_size, + pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size, &pxa_dma->sg_dma, GFP_KERNEL); if (!pxa_dma->sg_cpu) return -ENOMEM; @@ -345,7 +351,7 @@ static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, pxa_dma->sglen = sglen; offset = *sg_first_ofs; - dev_dbg(pcdev->soc_host.dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n", + dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n", *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma); @@ -368,7 +374,7 @@ static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, pxa_dma->sg_cpu[i].ddadr = pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc); - dev_vdbg(pcdev->soc_host.dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n", + dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n", pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc), sg_dma_address(sg) + offset, xfer_len); offset = 0; @@ -418,11 +424,12 @@ static int pxa_videobuf_prepare(struct videobuf_queue *vq, struct soc_camera_device *icd = vq->priv_data; struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); struct pxa_camera_dev *pcdev = ici->priv; + struct device *dev = pcdev->soc_host.v4l2_dev.dev; struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); int ret; int size_y, size_u = 0, size_v = 0; - dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb, vb->baddr, vb->bsize); /* Added list head initialization on alloc */ @@ -441,12 +448,12 @@ static int pxa_videobuf_prepare(struct videobuf_queue *vq, buf->inwork = 1; if (buf->fmt != icd->current_fmt || - vb->width != icd->width || - vb->height != icd->height || + vb->width != icd->user_width || + vb->height != icd->user_height || vb->field != field) { buf->fmt = icd->current_fmt; - vb->width = icd->width; - vb->height = icd->height; + vb->width = icd->user_width; + vb->height = icd->user_height; vb->field = field; vb->state = VIDEOBUF_NEEDS_INIT; } @@ -480,8 +487,7 @@ static int pxa_videobuf_prepare(struct videobuf_queue *vq, ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y, &sg, &next_ofs); if (ret) { - dev_err(pcdev->soc_host.dev, - "DMA initialization for Y/RGB failed\n"); + dev_err(dev, "DMA initialization for Y/RGB failed\n"); goto fail; } @@ -490,8 +496,7 @@ static int pxa_videobuf_prepare(struct videobuf_queue *vq, ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1, size_u, &sg, &next_ofs); if (ret) { - dev_err(pcdev->soc_host.dev, - "DMA initialization for U failed\n"); + dev_err(dev, "DMA initialization for U failed\n"); goto fail_u; } @@ -500,8 +505,7 @@ static int pxa_videobuf_prepare(struct videobuf_queue *vq, ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2, size_v, &sg, &next_ofs); if (ret) { - dev_err(pcdev->soc_host.dev, - "DMA initialization for V failed\n"); + dev_err(dev, "DMA initialization for V failed\n"); goto fail_v; } @@ -514,10 +518,10 @@ static int pxa_videobuf_prepare(struct videobuf_queue *vq, return 0; fail_v: - dma_free_coherent(pcdev->soc_host.dev, buf->dmas[1].sg_size, + dma_free_coherent(dev, buf->dmas[1].sg_size, buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma); fail_u: - dma_free_coherent(pcdev->soc_host.dev, buf->dmas[0].sg_size, + dma_free_coherent(dev, buf->dmas[0].sg_size, buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma); fail: free_buffer(vq, buf); @@ -541,7 +545,8 @@ static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev) active = pcdev->active; for (i = 0; i < pcdev->channels; i++) { - dev_dbg(pcdev->soc_host.dev, "%s (channel=%d) ddadr=%08x\n", __func__, + dev_dbg(pcdev->soc_host.v4l2_dev.dev, + "%s (channel=%d) ddadr=%08x\n", __func__, i, active->dmas[i].sg_dma); DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma; DCSR(pcdev->dma_chans[i]) = DCSR_RUN; @@ -553,7 +558,8 @@ static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev) int i; for (i = 0; i < pcdev->channels; i++) { - dev_dbg(pcdev->soc_host.dev, "%s (channel=%d)\n", __func__, i); + dev_dbg(pcdev->soc_host.v4l2_dev.dev, + "%s (channel=%d)\n", __func__, i); DCSR(pcdev->dma_chans[i]) = 0; } } @@ -589,7 +595,7 @@ static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev) { unsigned long cicr0, cifr; - dev_dbg(pcdev->soc_host.dev, "%s\n", __func__); + dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__); /* Reset the FIFOs */ cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; __raw_writel(cifr, pcdev->base + CIFR); @@ -609,7 +615,7 @@ static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev) __raw_writel(cicr0, pcdev->base + CICR0); pcdev->active = NULL; - dev_dbg(pcdev->soc_host.dev, "%s\n", __func__); + dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__); } /* Called under spinlock_irqsave(&pcdev->lock, ...) */ @@ -621,8 +627,8 @@ static void pxa_videobuf_queue(struct videobuf_queue *vq, struct pxa_camera_dev *pcdev = ici->priv; struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); - dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d active=%p\n", __func__, - vb, vb->baddr, vb->bsize, pcdev->active); + dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n", + __func__, vb, vb->baddr, vb->bsize, pcdev->active); list_add_tail(&vb->queue, &pcdev->capture); @@ -639,22 +645,23 @@ static void pxa_videobuf_release(struct videobuf_queue *vq, struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); #ifdef DEBUG struct soc_camera_device *icd = vq->priv_data; + struct device *dev = icd->dev.parent; - dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb, vb->baddr, vb->bsize); switch (vb->state) { case VIDEOBUF_ACTIVE: - dev_dbg(&icd->dev, "%s (active)\n", __func__); + dev_dbg(dev, "%s (active)\n", __func__); break; case VIDEOBUF_QUEUED: - dev_dbg(&icd->dev, "%s (queued)\n", __func__); + dev_dbg(dev, "%s (queued)\n", __func__); break; case VIDEOBUF_PREPARED: - dev_dbg(&icd->dev, "%s (prepared)\n", __func__); + dev_dbg(dev, "%s (prepared)\n", __func__); break; default: - dev_dbg(&icd->dev, "%s (unknown)\n", __func__); + dev_dbg(dev, "%s (unknown)\n", __func__); break; } #endif @@ -674,7 +681,8 @@ static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, do_gettimeofday(&vb->ts); vb->field_count++; wake_up(&vb->done); - dev_dbg(pcdev->soc_host.dev, "%s dequeud buffer (vb=0x%p)\n", __func__, vb); + dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n", + __func__, vb); if (list_empty(&pcdev->capture)) { pxa_camera_stop_capture(pcdev); @@ -710,7 +718,8 @@ static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev) for (i = 0; i < pcdev->channels; i++) if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP) is_dma_stopped = 0; - dev_dbg(pcdev->soc_host.dev, "%s : top queued buffer=%p, dma_stopped=%d\n", + dev_dbg(pcdev->soc_host.v4l2_dev.dev, + "%s : top queued buffer=%p, dma_stopped=%d\n", __func__, pcdev->active, is_dma_stopped); if (pcdev->active && is_dma_stopped) pxa_camera_start_capture(pcdev); @@ -719,6 +728,7 @@ static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev) static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev, enum pxa_camera_active_dma act_dma) { + struct device *dev = pcdev->soc_host.v4l2_dev.dev; struct pxa_buffer *buf; unsigned long flags; u32 status, camera_status, overrun; @@ -735,13 +745,13 @@ static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev, overrun |= CISR_IFO_1 | CISR_IFO_2; if (status & DCSR_BUSERR) { - dev_err(pcdev->soc_host.dev, "DMA Bus Error IRQ!\n"); + dev_err(dev, "DMA Bus Error IRQ!\n"); goto out; } if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) { - dev_err(pcdev->soc_host.dev, "Unknown DMA IRQ source, " - "status: 0x%08x\n", status); + dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n", + status); goto out; } @@ -764,7 +774,7 @@ static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev, buf = container_of(vb, struct pxa_buffer, vb); WARN_ON(buf->inwork || list_empty(&vb->queue)); - dev_dbg(pcdev->soc_host.dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n", + dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n", __func__, channel, status & DCSR_STARTINTR ? "SOF " : "", status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel)); @@ -775,7 +785,7 @@ static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev, */ if (camera_status & overrun && !list_is_last(pcdev->capture.next, &pcdev->capture)) { - dev_dbg(pcdev->soc_host.dev, "FIFO overrun! CISR: %x\n", + dev_dbg(dev, "FIFO overrun! CISR: %x\n", camera_status); pxa_camera_stop_capture(pcdev); pxa_camera_start_capture(pcdev); @@ -830,9 +840,11 @@ static void pxa_camera_init_videobuf(struct videobuf_queue *q, sizeof(struct pxa_buffer), icd); } -static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev) +static u32 mclk_get_divisor(struct platform_device *pdev, + struct pxa_camera_dev *pcdev) { unsigned long mclk = pcdev->mclk; + struct device *dev = &pdev->dev; u32 div; unsigned long lcdclk; @@ -842,7 +854,7 @@ static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev) /* mclk <= ciclk / 4 (27.4.2) */ if (mclk > lcdclk / 4) { mclk = lcdclk / 4; - dev_warn(pcdev->soc_host.dev, "Limiting master clock to %lu\n", mclk); + dev_warn(dev, "Limiting master clock to %lu\n", mclk); } /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ @@ -852,8 +864,8 @@ static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev) if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) pcdev->mclk = lcdclk / (2 * (div + 1)); - dev_dbg(pcdev->soc_host.dev, "LCD clock %luHz, target freq %luHz, " - "divisor %u\n", lcdclk, mclk, div); + dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n", + lcdclk, mclk, div); return div; } @@ -870,14 +882,15 @@ static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev, static void pxa_camera_activate(struct pxa_camera_dev *pcdev) { struct pxacamera_platform_data *pdata = pcdev->pdata; + struct device *dev = pcdev->soc_host.v4l2_dev.dev; u32 cicr4 = 0; - dev_dbg(pcdev->soc_host.dev, "Registered platform device at %p data %p\n", + dev_dbg(dev, "Registered platform device at %p data %p\n", pcdev, pdata); if (pdata && pdata->init) { - dev_dbg(pcdev->soc_host.dev, "%s: Init gpios\n", __func__); - pdata->init(pcdev->soc_host.dev); + dev_dbg(dev, "%s: Init gpios\n", __func__); + pdata->init(dev); } /* disable all interrupts */ @@ -919,7 +932,8 @@ static irqreturn_t pxa_camera_irq(int irq, void *data) struct videobuf_buffer *vb; status = __raw_readl(pcdev->base + CISR); - dev_dbg(pcdev->soc_host.dev, "Camera interrupt status 0x%lx\n", status); + dev_dbg(pcdev->soc_host.v4l2_dev.dev, + "Camera interrupt status 0x%lx\n", status); if (!status) return IRQ_NONE; @@ -951,24 +965,18 @@ static int pxa_camera_add_device(struct soc_camera_device *icd) { struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); struct pxa_camera_dev *pcdev = ici->priv; - int ret; - if (pcdev->icd) { - ret = -EBUSY; - goto ebusy; - } - - dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n", - icd->devnum); + if (pcdev->icd) + return -EBUSY; pxa_camera_activate(pcdev); - ret = icd->ops->init(icd); - if (!ret) - pcdev->icd = icd; + pcdev->icd = icd; -ebusy: - return ret; + dev_info(icd->dev.parent, "PXA Camera driver attached to camera %d\n", + icd->devnum); + + return 0; } /* Called with .video_lock held */ @@ -979,7 +987,7 @@ static void pxa_camera_remove_device(struct soc_camera_device *icd) BUG_ON(icd != pcdev->icd); - dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n", + dev_info(icd->dev.parent, "PXA Camera driver detached from camera %d\n", icd->devnum); /* disable capture, disable interrupts */ @@ -990,8 +998,6 @@ static void pxa_camera_remove_device(struct soc_camera_device *icd) DCSR(pcdev->dma_chans[1]) = 0; DCSR(pcdev->dma_chans[2]) = 0; - icd->ops->release(icd); - pxa_camera_deactivate(pcdev); pcdev->icd = NULL; @@ -1039,57 +1045,17 @@ static int test_platform_param(struct pxa_camera_dev *pcdev, return 0; } -static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) +static void pxa_camera_setup_cicr(struct soc_camera_device *icd, + unsigned long flags, __u32 pixfmt) { struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); struct pxa_camera_dev *pcdev = ici->priv; - unsigned long dw, bpp, bus_flags, camera_flags, common_flags; + unsigned long dw, bpp; u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0; - int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags); - - if (ret < 0) - return ret; - - camera_flags = icd->ops->query_bus_param(icd); - - common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags); - if (!common_flags) - return -EINVAL; - - pcdev->channels = 1; - - /* Make choises, based on platform preferences */ - if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && - (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { - if (pcdev->platform_flags & PXA_CAMERA_HSP) - common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; - else - common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; - } - - if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) && - (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) { - if (pcdev->platform_flags & PXA_CAMERA_VSP) - common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH; - else - common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW; - } - - if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && - (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { - if (pcdev->platform_flags & PXA_CAMERA_PCP) - common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; - else - common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; - } - - ret = icd->ops->set_bus_param(icd, common_flags); - if (ret < 0) - return ret; /* Datawidth is now guaranteed to be equal to one of the three values. * We fix bit-per-pixel equal to data-width... */ - switch (common_flags & SOCAM_DATAWIDTH_MASK) { + switch (flags & SOCAM_DATAWIDTH_MASK) { case SOCAM_DATAWIDTH_10: dw = 4; bpp = 0x40; @@ -1110,18 +1076,18 @@ static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) cicr4 |= CICR4_PCLK_EN; if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) cicr4 |= CICR4_MCLK_EN; - if (common_flags & SOCAM_PCLK_SAMPLE_FALLING) + if (flags & SOCAM_PCLK_SAMPLE_FALLING) cicr4 |= CICR4_PCP; - if (common_flags & SOCAM_HSYNC_ACTIVE_LOW) + if (flags & SOCAM_HSYNC_ACTIVE_LOW) cicr4 |= CICR4_HSP; - if (common_flags & SOCAM_VSYNC_ACTIVE_LOW) + if (flags & SOCAM_VSYNC_ACTIVE_LOW) cicr4 |= CICR4_VSP; cicr0 = __raw_readl(pcdev->base + CICR0); if (cicr0 & CICR0_ENB) __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); - cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw; + cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw; switch (pixfmt) { case V4L2_PIX_FMT_YUV422P: @@ -1150,7 +1116,7 @@ static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) } cicr2 = 0; - cicr3 = CICR3_LPF_VAL(icd->height - 1) | + cicr3 = CICR3_LPF_VAL(icd->user_height - 1) | CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top)); cicr4 |= pcdev->mclk_divisor; @@ -1164,6 +1130,59 @@ static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)); cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK; __raw_writel(cicr0, pcdev->base + CICR0); +} + +static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct pxa_camera_dev *pcdev = ici->priv; + unsigned long bus_flags, camera_flags, common_flags; + int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags); + struct pxa_cam *cam = icd->host_priv; + + if (ret < 0) + return ret; + + camera_flags = icd->ops->query_bus_param(icd); + + common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags); + if (!common_flags) + return -EINVAL; + + pcdev->channels = 1; + + /* Make choises, based on platform preferences */ + if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && + (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { + if (pcdev->platform_flags & PXA_CAMERA_HSP) + common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; + else + common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; + } + + if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) && + (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) { + if (pcdev->platform_flags & PXA_CAMERA_VSP) + common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH; + else + common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW; + } + + if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && + (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { + if (pcdev->platform_flags & PXA_CAMERA_PCP) + common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; + else + common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; + } + + cam->flags = common_flags; + + ret = icd->ops->set_bus_param(icd, common_flags); + if (ret < 0) + return ret; + + pxa_camera_setup_cicr(icd, common_flags, pixfmt); return 0; } @@ -1227,8 +1246,9 @@ static int required_buswidth(const struct soc_camera_data_format *fmt) static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx, struct soc_camera_format_xlate *xlate) { - struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct device *dev = icd->dev.parent; int formats = 0, buswidth, ret; + struct pxa_cam *cam; buswidth = required_buswidth(icd->formats + idx); @@ -1239,6 +1259,16 @@ static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx, if (ret < 0) return 0; + if (!icd->host_priv) { + cam = kzalloc(sizeof(*cam), GFP_KERNEL); + if (!cam) + return -ENOMEM; + + icd->host_priv = cam; + } else { + cam = icd->host_priv; + } + switch (icd->formats[idx].fourcc) { case V4L2_PIX_FMT_UYVY: formats++; @@ -1247,7 +1277,7 @@ static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx, xlate->cam_fmt = icd->formats + idx; xlate->buswidth = buswidth; xlate++; - dev_dbg(ici->dev, "Providing format %s using %s\n", + dev_dbg(dev, "Providing format %s using %s\n", pxa_camera_formats[0].name, icd->formats[idx].name); } @@ -1262,7 +1292,7 @@ static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx, xlate->cam_fmt = icd->formats + idx; xlate->buswidth = buswidth; xlate++; - dev_dbg(ici->dev, "Providing format %s packed\n", + dev_dbg(dev, "Providing format %s packed\n", icd->formats[idx].name); } break; @@ -1274,7 +1304,7 @@ static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx, xlate->cam_fmt = icd->formats + idx; xlate->buswidth = icd->formats[idx].depth; xlate++; - dev_dbg(ici->dev, + dev_dbg(dev, "Providing format %s in pass-through mode\n", icd->formats[idx].name); } @@ -1283,31 +1313,80 @@ static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx, return formats; } +static void pxa_camera_put_formats(struct soc_camera_device *icd) +{ + kfree(icd->host_priv); + icd->host_priv = NULL; +} + +static int pxa_camera_check_frame(struct v4l2_pix_format *pix) +{ + /* limit to pxa hardware capabilities */ + return pix->height < 32 || pix->height > 2048 || pix->width < 48 || + pix->width > 2048 || (pix->width & 0x01); +} + static int pxa_camera_set_crop(struct soc_camera_device *icd, - struct v4l2_rect *rect) + struct v4l2_crop *a) { + struct v4l2_rect *rect = &a->c; struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); struct pxa_camera_dev *pcdev = ici->priv; + struct device *dev = icd->dev.parent; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); struct soc_camera_sense sense = { .master_clock = pcdev->mclk, .pixel_clock_max = pcdev->ciclk / 4, }; + struct v4l2_format f; + struct v4l2_pix_format *pix = &f.fmt.pix, pix_tmp; + struct pxa_cam *cam = icd->host_priv; int ret; /* If PCLK is used to latch data from the sensor, check sense */ if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) icd->sense = &sense; - ret = icd->ops->set_crop(icd, rect); + ret = v4l2_subdev_call(sd, video, s_crop, a); icd->sense = NULL; if (ret < 0) { - dev_warn(ici->dev, "Failed to crop to %ux%u@%u:%u\n", + dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n", rect->width, rect->height, rect->left, rect->top); - } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { + return ret; + } + + f.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + ret = v4l2_subdev_call(sd, video, g_fmt, &f); + if (ret < 0) + return ret; + + pix_tmp = *pix; + if (pxa_camera_check_frame(pix)) { + /* + * Camera cropping produced a frame beyond our capabilities. + * FIXME: just extract a subframe, that we can process. + */ + v4l_bound_align_image(&pix->width, 48, 2048, 1, + &pix->height, 32, 2048, 0, + icd->current_fmt->fourcc == V4L2_PIX_FMT_YUV422P ? + 4 : 0); + ret = v4l2_subdev_call(sd, video, s_fmt, &f); + if (ret < 0) + return ret; + + if (pxa_camera_check_frame(pix)) { + dev_warn(icd->dev.parent, + "Inconsistent state. Use S_FMT to repair\n"); + return -EINVAL; + } + } + + if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { if (sense.pixel_clock > sense.pixel_clock_max) { - dev_err(ici->dev, + dev_err(dev, "pixel clock %lu set by the camera too high!", sense.pixel_clock); return -EIO; @@ -1315,6 +1394,11 @@ static int pxa_camera_set_crop(struct soc_camera_device *icd, recalculate_fifo_timeout(pcdev, sense.pixel_clock); } + icd->user_width = pix->width; + icd->user_height = pix->height; + + pxa_camera_setup_cicr(icd, cam->flags, icd->current_fmt->fourcc); + return ret; } @@ -1323,6 +1407,8 @@ static int pxa_camera_set_fmt(struct soc_camera_device *icd, { struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); struct pxa_camera_dev *pcdev = ici->priv; + struct device *dev = icd->dev.parent; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); const struct soc_camera_data_format *cam_fmt = NULL; const struct soc_camera_format_xlate *xlate = NULL; struct soc_camera_sense sense = { @@ -1335,7 +1421,7 @@ static int pxa_camera_set_fmt(struct soc_camera_device *icd, xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); if (!xlate) { - dev_warn(ici->dev, "Format %x not found\n", pix->pixelformat); + dev_warn(dev, "Format %x not found\n", pix->pixelformat); return -EINVAL; } @@ -1346,16 +1432,21 @@ static int pxa_camera_set_fmt(struct soc_camera_device *icd, icd->sense = &sense; cam_f.fmt.pix.pixelformat = cam_fmt->fourcc; - ret = icd->ops->set_fmt(icd, &cam_f); + ret = v4l2_subdev_call(sd, video, s_fmt, f); icd->sense = NULL; if (ret < 0) { - dev_warn(ici->dev, "Failed to configure for format %x\n", + dev_warn(dev, "Failed to configure for format %x\n", pix->pixelformat); + } else if (pxa_camera_check_frame(pix)) { + dev_warn(dev, + "Camera driver produced an unsupported frame %dx%d\n", + pix->width, pix->height); + ret = -EINVAL; } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { if (sense.pixel_clock > sense.pixel_clock_max) { - dev_err(ici->dev, + dev_err(dev, "pixel clock %lu set by the camera too high!", sense.pixel_clock); return -EIO; @@ -1375,6 +1466,7 @@ static int pxa_camera_try_fmt(struct soc_camera_device *icd, struct v4l2_format *f) { struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); const struct soc_camera_format_xlate *xlate; struct v4l2_pix_format *pix = &f->fmt.pix; __u32 pixfmt = pix->pixelformat; @@ -1383,7 +1475,7 @@ static int pxa_camera_try_fmt(struct soc_camera_device *icd, xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); if (!xlate) { - dev_warn(ici->dev, "Format %x not found\n", pixfmt); + dev_warn(ici->v4l2_dev.dev, "Format %x not found\n", pixfmt); return -EINVAL; } @@ -1395,7 +1487,7 @@ static int pxa_camera_try_fmt(struct soc_camera_device *icd, */ v4l_bound_align_image(&pix->width, 48, 2048, 1, &pix->height, 32, 2048, 0, - xlate->host_fmt->fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0); + pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0); pix->bytesperline = pix->width * DIV_ROUND_UP(xlate->host_fmt->depth, 8); @@ -1404,15 +1496,15 @@ static int pxa_camera_try_fmt(struct soc_camera_device *icd, /* camera has to see its format, but the user the original one */ pix->pixelformat = xlate->cam_fmt->fourcc; /* limit to sensor capabilities */ - ret = icd->ops->try_fmt(icd, f); - pix->pixelformat = xlate->host_fmt->fourcc; + ret = v4l2_subdev_call(sd, video, try_fmt, f); + pix->pixelformat = pixfmt; field = pix->field; if (field == V4L2_FIELD_ANY) { pix->field = V4L2_FIELD_NONE; } else if (field != V4L2_FIELD_NONE) { - dev_err(&icd->dev, "Field type %d unsupported.\n", field); + dev_err(icd->dev.parent, "Field type %d unsupported.\n", field); return -EINVAL; } @@ -1518,6 +1610,7 @@ static struct soc_camera_host_ops pxa_soc_camera_host_ops = { .resume = pxa_camera_resume, .set_crop = pxa_camera_set_crop, .get_formats = pxa_camera_get_formats, + .put_formats = pxa_camera_put_formats, .set_fmt = pxa_camera_set_fmt, .try_fmt = pxa_camera_try_fmt, .init_videobuf = pxa_camera_init_videobuf, @@ -1575,8 +1668,7 @@ static int __devinit pxa_camera_probe(struct platform_device *pdev) pcdev->mclk = 20000000; } - pcdev->soc_host.dev = &pdev->dev; - pcdev->mclk_divisor = mclk_get_divisor(pcdev); + pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev); INIT_LIST_HEAD(&pcdev->capture); spin_lock_init(&pcdev->lock); @@ -1641,6 +1733,7 @@ static int __devinit pxa_camera_probe(struct platform_device *pdev) pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME; pcdev->soc_host.ops = &pxa_soc_camera_host_ops; pcdev->soc_host.priv = pcdev; + pcdev->soc_host.v4l2_dev.dev = &pdev->dev; pcdev->soc_host.nr = pdev->id; err = soc_camera_host_register(&pcdev->soc_host); @@ -1722,3 +1815,4 @@ module_exit(pxa_camera_exit); MODULE_DESCRIPTION("PXA27x SoC Camera Host driver"); MODULE_AUTHOR("Guennadi Liakhovetski "); MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME); diff --git a/drivers/media/video/saa7134/saa7134-cards.c b/drivers/media/video/saa7134/saa7134-cards.c index 1b29487fd254..71145bff94fa 100644 --- a/drivers/media/video/saa7134/saa7134-cards.c +++ b/drivers/media/video/saa7134/saa7134-cards.c @@ -4164,7 +4164,7 @@ struct saa7134_board saa7134_boards[] = { /*Dmitry Belimov */ .name = "Beholder BeholdTV 505 RDS", .audio_clock = 0x00200000, - .tuner_type = TUNER_PHILIPS_FM1216ME_MK3, /* FIXME to MK5 */ + .tuner_type = TUNER_PHILIPS_FM1216MK5, .radio_type = UNSET, .tuner_addr = ADDR_UNSET, .radio_addr = ADDR_UNSET, @@ -4229,7 +4229,7 @@ struct saa7134_board saa7134_boards[] = { /*Dmitry Belimov */ .name = "Beholder BeholdTV 507 RDS", .audio_clock = 0x00187de7, - .tuner_type = TUNER_PHILIPS_FM1216ME_MK3, /* FIXME to MK5 */ + .tuner_type = TUNER_PHILIPS_FM1216MK5, .radio_type = UNSET, .tuner_addr = ADDR_UNSET, .radio_addr = ADDR_UNSET, @@ -4380,7 +4380,7 @@ struct saa7134_board saa7134_boards[] = { /* Andrey Melnikoff */ .name = "Beholder BeholdTV 607 FM", .audio_clock = 0x00187de7, - .tuner_type = TUNER_PHILIPS_FM1216ME_MK3, /* FIXME to MK5 */ + .tuner_type = TUNER_PHILIPS_FM1216MK5, .radio_type = UNSET, .tuner_addr = ADDR_UNSET, .radio_addr = ADDR_UNSET, @@ -4408,7 +4408,7 @@ struct saa7134_board saa7134_boards[] = { /* Andrey Melnikoff */ .name = "Beholder BeholdTV 609 FM", .audio_clock = 0x00187de7, - .tuner_type = TUNER_PHILIPS_FM1216ME_MK3, /* FIXME to MK5 */ + .tuner_type = TUNER_PHILIPS_FM1216MK5, .radio_type = UNSET, .tuner_addr = ADDR_UNSET, .radio_addr = ADDR_UNSET, @@ -4494,7 +4494,7 @@ struct saa7134_board saa7134_boards[] = { /* Andrey Melnikoff */ .name = "Beholder BeholdTV 607 RDS", .audio_clock = 0x00187de7, - .tuner_type = TUNER_PHILIPS_FM1216ME_MK3, /* FIXME to MK5 */ + .tuner_type = TUNER_PHILIPS_FM1216MK5, .radio_type = UNSET, .tuner_addr = ADDR_UNSET, .radio_addr = ADDR_UNSET, @@ -4523,7 +4523,7 @@ struct saa7134_board saa7134_boards[] = { /* Andrey Melnikoff */ .name = "Beholder BeholdTV 609 RDS", .audio_clock = 0x00187de7, - .tuner_type = TUNER_PHILIPS_FM1216ME_MK3, /* FIXME to MK5 */ + .tuner_type = TUNER_PHILIPS_FM1216MK5, .radio_type = UNSET, .tuner_addr = ADDR_UNSET, .radio_addr = ADDR_UNSET, @@ -4630,7 +4630,7 @@ struct saa7134_board saa7134_boards[] = { /* Alexey Osipov */ .name = "Beholder BeholdTV M6 Extra", .audio_clock = 0x00187de7, - .tuner_type = TUNER_PHILIPS_FM1216ME_MK3, /* FIXME to MK5 */ + .tuner_type = TUNER_PHILIPS_FM1216MK5, .radio_type = UNSET, .tuner_addr = ADDR_UNSET, .radio_addr = ADDR_UNSET, @@ -5257,6 +5257,27 @@ struct saa7134_board saa7134_boards[] = { .amux = TV, }, }, + [SAA7134_BOARD_ZOLID_HYBRID_PCI] = { + .name = "Zolid Hybrid TV Tuner PCI", + .audio_clock = 0x00187de7, + .tuner_type = TUNER_PHILIPS_TDA8290, + .radio_type = UNSET, + .tuner_addr = ADDR_UNSET, + .radio_addr = ADDR_UNSET, + .tuner_config = 0, + .mpeg = SAA7134_MPEG_DVB, + .ts_type = SAA7134_MPEG_TS_PARALLEL, + .inputs = {{ + .name = name_tv, + .vmux = 1, + .amux = TV, + .tv = 1, + } }, + .radio = { /* untested */ + .name = name_radio, + .amux = TV, + }, + }, }; @@ -6389,6 +6410,12 @@ struct pci_device_id saa7134_pci_tbl[] = { .subvendor = 0x19d1, /* RoverMedia */ .subdevice = 0x0138, /* LifeView FlyTV Prime30 OEM */ .driver_data = SAA7134_BOARD_ROVERMEDIA_LINK_PRO_FM, + }, { + .vendor = PCI_VENDOR_ID_PHILIPS, + .device = PCI_DEVICE_ID_PHILIPS_SAA7133, + .subvendor = PCI_VENDOR_ID_PHILIPS, + .subdevice = 0x2004, + .driver_data = SAA7134_BOARD_ZOLID_HYBRID_PCI, }, { /* --- boards without eeprom + subsystem ID --- */ .vendor = PCI_VENDOR_ID_PHILIPS, @@ -7208,22 +7235,22 @@ int saa7134_board_init2(struct saa7134_dev *dev) if (dev->radio_type != UNSET) v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, "tuner", "tuner", - dev->radio_addr); + dev->radio_addr, NULL); if (has_demod) - v4l2_i2c_new_probed_subdev(&dev->v4l2_dev, + v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, "tuner", "tuner", - v4l2_i2c_tuner_addrs(ADDRS_DEMOD)); + 0, v4l2_i2c_tuner_addrs(ADDRS_DEMOD)); if (dev->tuner_addr == ADDR_UNSET) { enum v4l2_i2c_tuner_type type = has_demod ? ADDRS_TV_WITH_DEMOD : ADDRS_TV; - v4l2_i2c_new_probed_subdev(&dev->v4l2_dev, + v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, "tuner", "tuner", - v4l2_i2c_tuner_addrs(type)); + 0, v4l2_i2c_tuner_addrs(type)); } else { v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, "tuner", "tuner", - dev->tuner_addr); + dev->tuner_addr, NULL); } } diff --git a/drivers/media/video/saa7134/saa7134-core.c b/drivers/media/video/saa7134/saa7134-core.c index cb78c956d810..f87757fccc72 100644 --- a/drivers/media/video/saa7134/saa7134-core.c +++ b/drivers/media/video/saa7134/saa7134-core.c @@ -1000,7 +1000,7 @@ static int __devinit saa7134_initdev(struct pci_dev *pci_dev, struct v4l2_subdev *sd = v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, "saa6752hs", "saa6752hs", - saa7134_boards[dev->board].empress_addr); + saa7134_boards[dev->board].empress_addr, NULL); if (sd) sd->grp_id = GRP_EMPRESS; @@ -1009,9 +1009,9 @@ static int __devinit saa7134_initdev(struct pci_dev *pci_dev, if (saa7134_boards[dev->board].rds_addr) { struct v4l2_subdev *sd; - sd = v4l2_i2c_new_probed_subdev_addr(&dev->v4l2_dev, + sd = v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, "saa6588", "saa6588", - saa7134_boards[dev->board].rds_addr); + 0, I2C_ADDRS(saa7134_boards[dev->board].rds_addr)); if (sd) { printk(KERN_INFO "%s: found RDS decoder\n", dev->name); dev->has_rds = 1; diff --git a/drivers/media/video/saa7134/saa7134-dvb.c b/drivers/media/video/saa7134/saa7134-dvb.c index ebde21dba7e3..a26e997a9ce6 100644 --- a/drivers/media/video/saa7134/saa7134-dvb.c +++ b/drivers/media/video/saa7134/saa7134-dvb.c @@ -1007,12 +1007,29 @@ static struct tda18271_config hcw_tda18271_config = { .std_map = &hauppauge_tda18271_std_map, .gate = TDA18271_GATE_ANALOG, .config = 3, + .output_opt = TDA18271_OUTPUT_LT_OFF, }; static struct tda829x_config tda829x_no_probe = { .probe_tuner = TDA829X_DONT_PROBE, }; +static struct tda10048_config zolid_tda10048_config = { + .demod_address = 0x10 >> 1, + .output_mode = TDA10048_PARALLEL_OUTPUT, + .fwbulkwritelen = TDA10048_BULKWRITE_200, + .inversion = TDA10048_INVERSION_ON, + .dtv6_if_freq_khz = TDA10048_IF_3300, + .dtv7_if_freq_khz = TDA10048_IF_3500, + .dtv8_if_freq_khz = TDA10048_IF_4000, + .clk_freq_khz = TDA10048_CLK_16000, + .disable_gate_access = 1, +}; + +static struct tda18271_config zolid_tda18271_config = { + .gate = TDA18271_GATE_ANALOG, +}; + /* ================================================================== * Core code */ @@ -1487,6 +1504,19 @@ static int dvb_init(struct saa7134_dev *dev) wprintk("%s: No zl10039 found!\n", __func__); + break; + case SAA7134_BOARD_ZOLID_HYBRID_PCI: + fe0->dvb.frontend = dvb_attach(tda10048_attach, + &zolid_tda10048_config, + &dev->i2c_adap); + if (fe0->dvb.frontend != NULL) { + dvb_attach(tda829x_attach, fe0->dvb.frontend, + &dev->i2c_adap, 0x4b, + &tda829x_no_probe); + dvb_attach(tda18271_attach, fe0->dvb.frontend, + 0x60, &dev->i2c_adap, + &zolid_tda18271_config); + } break; default: wprintk("Huh? unknown DVB card?\n"); diff --git a/drivers/media/video/saa7134/saa7134-input.c b/drivers/media/video/saa7134/saa7134-input.c index e1e83c7b966e..a0e8c62e6ae1 100644 --- a/drivers/media/video/saa7134/saa7134-input.c +++ b/drivers/media/video/saa7134/saa7134-input.c @@ -251,6 +251,10 @@ static int get_key_beholdm6xx(struct IR_i2c *ir, u32 *ir_key, u32 *ir_raw) if (data[10] != 0x6b && data[11] != 0x86 && disable_other_ir) return 0; + /* Wrong data decode fix */ + if (data[9] != (unsigned char)(~data[8])) + return 0; + *ir_key = data[9]; *ir_raw = data[9]; diff --git a/drivers/media/video/saa7134/saa7134.h b/drivers/media/video/saa7134/saa7134.h index d18bb9643856..6ee3e9b7769e 100644 --- a/drivers/media/video/saa7134/saa7134.h +++ b/drivers/media/video/saa7134/saa7134.h @@ -296,6 +296,7 @@ struct saa7134_format { #define SAA7134_BOARD_AVERMEDIA_STUDIO_505 170 #define SAA7134_BOARD_BEHOLD_X7 171 #define SAA7134_BOARD_ROVERMEDIA_LINK_PRO_FM 172 +#define SAA7134_BOARD_ZOLID_HYBRID_PCI 173 #define SAA7134_MAXBOARDS 32 #define SAA7134_INPUT_MAX 8 diff --git a/drivers/media/video/saa7164/Kconfig b/drivers/media/video/saa7164/Kconfig new file mode 100644 index 000000000000..353263725172 --- /dev/null +++ b/drivers/media/video/saa7164/Kconfig @@ -0,0 +1,18 @@ +config VIDEO_SAA7164 + tristate "NXP SAA7164 support" + depends on DVB_CORE && PCI && I2C + select I2C_ALGOBIT + select FW_LOADER + select VIDEO_TUNER + select VIDEO_TVEEPROM + select VIDEOBUF_DVB + select DVB_TDA10048 if !DVB_FE_CUSTOMISE + select DVB_S5H1411 if !DVB_FE_CUSTOMISE + select MEDIA_TUNER_TDA18271 if !MEDIA_TUNER_CUSTOMISE + ---help--- + This is a video4linux driver for NXP SAA7164 based + TV cards. + + To compile this driver as a module, choose M here: the + module will be called saa7164 + diff --git a/drivers/media/video/saa7164/Makefile b/drivers/media/video/saa7164/Makefile new file mode 100644 index 000000000000..4b329fd42add --- /dev/null +++ b/drivers/media/video/saa7164/Makefile @@ -0,0 +1,12 @@ +saa7164-objs := saa7164-cards.o saa7164-core.o saa7164-i2c.o saa7164-dvb.o \ + saa7164-fw.o saa7164-bus.o saa7164-cmd.o saa7164-api.o \ + saa7164-buffer.o + +obj-$(CONFIG_VIDEO_SAA7164) += saa7164.o + +EXTRA_CFLAGS += -Idrivers/media/video +EXTRA_CFLAGS += -Idrivers/media/common/tuners +EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core +EXTRA_CFLAGS += -Idrivers/media/dvb/frontends + +EXTRA_CFLAGS += $(extra-cflags-y) $(extra-cflags-m) diff --git a/drivers/media/video/saa7164/saa7164-api.c b/drivers/media/video/saa7164/saa7164-api.c new file mode 100644 index 000000000000..bb6df1b276be --- /dev/null +++ b/drivers/media/video/saa7164/saa7164-api.c @@ -0,0 +1,600 @@ +/* + * Driver for the NXP SAA7164 PCIe bridge + * + * Copyright (c) 2009 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +#include "saa7164.h" + +int saa7164_api_transition_port(struct saa7164_tsport *port, u8 mode) +{ + int ret; + + ret = saa7164_cmd_send(port->dev, port->hwcfg.unitid, SET_CUR, + SAA_STATE_CONTROL, sizeof(mode), &mode); + if (ret != SAA_OK) + printk(KERN_ERR "%s() error, ret = 0x%x\n", __func__, ret); + + return ret; +} + +int saa7164_api_get_fw_version(struct saa7164_dev *dev, u32 *version) +{ + int ret; + + ret = saa7164_cmd_send(dev, 0, GET_CUR, + GET_FW_VERSION_CONTROL, sizeof(u32), version); + if (ret != SAA_OK) + printk(KERN_ERR "%s() error, ret = 0x%x\n", __func__, ret); + + return ret; +} + +int saa7164_api_read_eeprom(struct saa7164_dev *dev, u8 *buf, int buflen) +{ + u8 reg[] = { 0x0f, 0x00 }; + + if (buflen < 128) + return -ENOMEM; + + /* Assumption: Hauppauge eeprom is at 0xa0 on on bus 0 */ + /* TODO: Pull the details from the boards struct */ + return saa7164_api_i2c_read(&dev->i2c_bus[0], 0xa0 >> 1, sizeof(reg), + ®[0], 128, buf); +} + + +int saa7164_api_configure_port_mpeg2ts(struct saa7164_dev *dev, + struct saa7164_tsport *port, + tmComResTSFormatDescrHeader_t *tsfmt) +{ + dprintk(DBGLVL_API, " bFormatIndex = 0x%x\n", tsfmt->bFormatIndex); + dprintk(DBGLVL_API, " bDataOffset = 0x%x\n", tsfmt->bDataOffset); + dprintk(DBGLVL_API, " bPacketLength= 0x%x\n", tsfmt->bPacketLength); + dprintk(DBGLVL_API, " bStrideLength= 0x%x\n", tsfmt->bStrideLength); + dprintk(DBGLVL_API, " bguid = (....)\n"); + + /* Cache the hardware configuration in the port */ + + port->bufcounter = port->hwcfg.BARLocation; + port->pitch = port->hwcfg.BARLocation + (2 * sizeof(u32)); + port->bufsize = port->hwcfg.BARLocation + (3 * sizeof(u32)); + port->bufoffset = port->hwcfg.BARLocation + (4 * sizeof(u32)); + port->bufptr32l = port->hwcfg.BARLocation + + (4 * sizeof(u32)) + + (sizeof(u32) * port->hwcfg.buffercount) + sizeof(u32); + port->bufptr32h = port->hwcfg.BARLocation + + (4 * sizeof(u32)) + + (sizeof(u32) * port->hwcfg.buffercount); + port->bufptr64 = port->hwcfg.BARLocation + + (4 * sizeof(u32)) + + (sizeof(u32) * port->hwcfg.buffercount); + dprintk(DBGLVL_API, " = port->hwcfg.BARLocation = 0x%x\n", + port->hwcfg.BARLocation); + + dprintk(DBGLVL_API, " = VS_FORMAT_MPEGTS (becomes dev->ts[%d])\n", + port->nr); + + return 0; +} + +int saa7164_api_dump_subdevs(struct saa7164_dev *dev, u8 *buf, int len) +{ + struct saa7164_tsport *port = 0; + u32 idx, next_offset; + int i; + tmComResDescrHeader_t *hdr, *t; + tmComResExtDevDescrHeader_t *exthdr; + tmComResPathDescrHeader_t *pathhdr; + tmComResAntTermDescrHeader_t *anttermhdr; + tmComResTunerDescrHeader_t *tunerunithdr; + tmComResDMATermDescrHeader_t *vcoutputtermhdr; + tmComResTSFormatDescrHeader_t *tsfmt; + u32 currpath = 0; + + dprintk(DBGLVL_API, + "%s(?,?,%d) sizeof(tmComResDescrHeader_t) = %d bytes\n", + __func__, len, (u32)sizeof(tmComResDescrHeader_t)); + + for (idx = 0; idx < (len - sizeof(tmComResDescrHeader_t)); ) { + + hdr = (tmComResDescrHeader_t *)(buf + idx); + + if (hdr->type != CS_INTERFACE) + return SAA_ERR_NOT_SUPPORTED; + + dprintk(DBGLVL_API, "@ 0x%x = \n", idx); + switch (hdr->subtype) { + case GENERAL_REQUEST: + dprintk(DBGLVL_API, " GENERAL_REQUEST\n"); + break; + case VC_TUNER_PATH: + dprintk(DBGLVL_API, " VC_TUNER_PATH\n"); + pathhdr = (tmComResPathDescrHeader_t *)(buf + idx); + dprintk(DBGLVL_API, " pathid = 0x%x\n", + pathhdr->pathid); + currpath = pathhdr->pathid; + break; + case VC_INPUT_TERMINAL: + dprintk(DBGLVL_API, " VC_INPUT_TERMINAL\n"); + anttermhdr = + (tmComResAntTermDescrHeader_t *)(buf + idx); + dprintk(DBGLVL_API, " terminalid = 0x%x\n", + anttermhdr->terminalid); + dprintk(DBGLVL_API, " terminaltype = 0x%x\n", + anttermhdr->terminaltype); + switch (anttermhdr->terminaltype) { + case ITT_ANTENNA: + dprintk(DBGLVL_API, " = ITT_ANTENNA\n"); + break; + case LINE_CONNECTOR: + dprintk(DBGLVL_API, " = LINE_CONNECTOR\n"); + break; + case SPDIF_CONNECTOR: + dprintk(DBGLVL_API, " = SPDIF_CONNECTOR\n"); + break; + case COMPOSITE_CONNECTOR: + dprintk(DBGLVL_API, + " = COMPOSITE_CONNECTOR\n"); + break; + case SVIDEO_CONNECTOR: + dprintk(DBGLVL_API, " = SVIDEO_CONNECTOR\n"); + break; + case COMPONENT_CONNECTOR: + dprintk(DBGLVL_API, + " = COMPONENT_CONNECTOR\n"); + break; + case STANDARD_DMA: + dprintk(DBGLVL_API, " = STANDARD_DMA\n"); + break; + default: + dprintk(DBGLVL_API, " = undefined (0x%x)\n", + anttermhdr->terminaltype); + } + dprintk(DBGLVL_API, " assocterminal= 0x%x\n", + anttermhdr->assocterminal); + dprintk(DBGLVL_API, " iterminal = 0x%x\n", + anttermhdr->iterminal); + dprintk(DBGLVL_API, " controlsize = 0x%x\n", + anttermhdr->controlsize); + break; + case VC_OUTPUT_TERMINAL: + dprintk(DBGLVL_API, " VC_OUTPUT_TERMINAL\n"); + vcoutputtermhdr = + (tmComResDMATermDescrHeader_t *)(buf + idx); + dprintk(DBGLVL_API, " unitid = 0x%x\n", + vcoutputtermhdr->unitid); + dprintk(DBGLVL_API, " terminaltype = 0x%x\n", + vcoutputtermhdr->terminaltype); + switch (vcoutputtermhdr->terminaltype) { + case ITT_ANTENNA: + dprintk(DBGLVL_API, " = ITT_ANTENNA\n"); + break; + case LINE_CONNECTOR: + dprintk(DBGLVL_API, " = LINE_CONNECTOR\n"); + break; + case SPDIF_CONNECTOR: + dprintk(DBGLVL_API, " = SPDIF_CONNECTOR\n"); + break; + case COMPOSITE_CONNECTOR: + dprintk(DBGLVL_API, + " = COMPOSITE_CONNECTOR\n"); + break; + case SVIDEO_CONNECTOR: + dprintk(DBGLVL_API, " = SVIDEO_CONNECTOR\n"); + break; + case COMPONENT_CONNECTOR: + dprintk(DBGLVL_API, + " = COMPONENT_CONNECTOR\n"); + break; + case STANDARD_DMA: + dprintk(DBGLVL_API, " = STANDARD_DMA\n"); + break; + default: + dprintk(DBGLVL_API, " = undefined (0x%x)\n", + vcoutputtermhdr->terminaltype); + } + dprintk(DBGLVL_API, " assocterminal= 0x%x\n", + vcoutputtermhdr->assocterminal); + dprintk(DBGLVL_API, " sourceid = 0x%x\n", + vcoutputtermhdr->sourceid); + dprintk(DBGLVL_API, " iterminal = 0x%x\n", + vcoutputtermhdr->iterminal); + dprintk(DBGLVL_API, " BARLocation = 0x%x\n", + vcoutputtermhdr->BARLocation); + dprintk(DBGLVL_API, " flags = 0x%x\n", + vcoutputtermhdr->flags); + dprintk(DBGLVL_API, " interruptid = 0x%x\n", + vcoutputtermhdr->interruptid); + dprintk(DBGLVL_API, " buffercount = 0x%x\n", + vcoutputtermhdr->buffercount); + dprintk(DBGLVL_API, " metadatasize = 0x%x\n", + vcoutputtermhdr->metadatasize); + dprintk(DBGLVL_API, " controlsize = 0x%x\n", + vcoutputtermhdr->controlsize); + dprintk(DBGLVL_API, " numformats = 0x%x\n", + vcoutputtermhdr->numformats); + + t = (tmComResDescrHeader_t *) + ((tmComResDMATermDescrHeader_t *)(buf + idx)); + next_offset = idx + (vcoutputtermhdr->len); + for (i = 0; i < vcoutputtermhdr->numformats; i++) { + t = (tmComResDescrHeader_t *) + (buf + next_offset); + switch (t->subtype) { + case VS_FORMAT_MPEG2TS: + tsfmt = + (tmComResTSFormatDescrHeader_t *)t; + if (currpath == 1) + port = &dev->ts1; + else + port = &dev->ts2; + memcpy(&port->hwcfg, vcoutputtermhdr, + sizeof(*vcoutputtermhdr)); + saa7164_api_configure_port_mpeg2ts(dev, + port, tsfmt); + break; + case VS_FORMAT_MPEG2PS: + dprintk(DBGLVL_API, + " = VS_FORMAT_MPEG2PS\n"); + break; + case VS_FORMAT_VBI: + dprintk(DBGLVL_API, + " = VS_FORMAT_VBI\n"); + break; + case VS_FORMAT_RDS: + dprintk(DBGLVL_API, + " = VS_FORMAT_RDS\n"); + break; + case VS_FORMAT_UNCOMPRESSED: + dprintk(DBGLVL_API, + " = VS_FORMAT_UNCOMPRESSED\n"); + break; + case VS_FORMAT_TYPE: + dprintk(DBGLVL_API, + " = VS_FORMAT_TYPE\n"); + break; + default: + dprintk(DBGLVL_API, + " = undefined (0x%x)\n", + t->subtype); + } + next_offset += t->len; + } + + break; + case TUNER_UNIT: + dprintk(DBGLVL_API, " TUNER_UNIT\n"); + tunerunithdr = + (tmComResTunerDescrHeader_t *)(buf + idx); + dprintk(DBGLVL_API, " unitid = 0x%x\n", + tunerunithdr->unitid); + dprintk(DBGLVL_API, " sourceid = 0x%x\n", + tunerunithdr->sourceid); + dprintk(DBGLVL_API, " iunit = 0x%x\n", + tunerunithdr->iunit); + dprintk(DBGLVL_API, " tuningstandards = 0x%x\n", + tunerunithdr->tuningstandards); + dprintk(DBGLVL_API, " controlsize = 0x%x\n", + tunerunithdr->controlsize); + dprintk(DBGLVL_API, " controls = 0x%x\n", + tunerunithdr->controls); + break; + case VC_SELECTOR_UNIT: + dprintk(DBGLVL_API, " VC_SELECTOR_UNIT\n"); + break; + case VC_PROCESSING_UNIT: + dprintk(DBGLVL_API, " VC_PROCESSING_UNIT\n"); + break; + case FEATURE_UNIT: + dprintk(DBGLVL_API, " FEATURE_UNIT\n"); + break; + case ENCODER_UNIT: + dprintk(DBGLVL_API, " ENCODER_UNIT\n"); + break; + case EXTENSION_UNIT: + dprintk(DBGLVL_API, " EXTENSION_UNIT\n"); + exthdr = (tmComResExtDevDescrHeader_t *)(buf + idx); + dprintk(DBGLVL_API, " unitid = 0x%x\n", + exthdr->unitid); + dprintk(DBGLVL_API, " deviceid = 0x%x\n", + exthdr->deviceid); + dprintk(DBGLVL_API, " devicetype = 0x%x\n", + exthdr->devicetype); + if (exthdr->devicetype & 0x1) + dprintk(DBGLVL_API, " = Decoder Device\n"); + if (exthdr->devicetype & 0x2) + dprintk(DBGLVL_API, " = GPIO Source\n"); + if (exthdr->devicetype & 0x4) + dprintk(DBGLVL_API, " = Video Decoder\n"); + if (exthdr->devicetype & 0x8) + dprintk(DBGLVL_API, " = Audio Decoder\n"); + if (exthdr->devicetype & 0x20) + dprintk(DBGLVL_API, " = Crossbar\n"); + if (exthdr->devicetype & 0x40) + dprintk(DBGLVL_API, " = Tuner\n"); + if (exthdr->devicetype & 0x80) + dprintk(DBGLVL_API, " = IF PLL\n"); + if (exthdr->devicetype & 0x100) + dprintk(DBGLVL_API, " = Demodulator\n"); + if (exthdr->devicetype & 0x200) + dprintk(DBGLVL_API, " = RDS Decoder\n"); + if (exthdr->devicetype & 0x400) + dprintk(DBGLVL_API, " = Encoder\n"); + if (exthdr->devicetype & 0x800) + dprintk(DBGLVL_API, " = IR Decoder\n"); + if (exthdr->devicetype & 0x1000) + dprintk(DBGLVL_API, " = EEPROM\n"); + if (exthdr->devicetype & 0x2000) + dprintk(DBGLVL_API, + " = VBI Decoder\n"); + if (exthdr->devicetype & 0x10000) + dprintk(DBGLVL_API, + " = Streaming Device\n"); + if (exthdr->devicetype & 0x20000) + dprintk(DBGLVL_API, + " = DRM Device\n"); + if (exthdr->devicetype & 0x40000000) + dprintk(DBGLVL_API, + " = Generic Device\n"); + if (exthdr->devicetype & 0x80000000) + dprintk(DBGLVL_API, + " = Config Space Device\n"); + dprintk(DBGLVL_API, " numgpiopins = 0x%x\n", + exthdr->numgpiopins); + dprintk(DBGLVL_API, " numgpiogroups = 0x%x\n", + exthdr->numgpiogroups); + dprintk(DBGLVL_API, " controlsize = 0x%x\n", + exthdr->controlsize); + break; + case PVC_INFRARED_UNIT: + dprintk(DBGLVL_API, " PVC_INFRARED_UNIT\n"); + break; + case DRM_UNIT: + dprintk(DBGLVL_API, " DRM_UNIT\n"); + break; + default: + dprintk(DBGLVL_API, "default %d\n", hdr->subtype); + } + + dprintk(DBGLVL_API, " 1.%x\n", hdr->len); + dprintk(DBGLVL_API, " 2.%x\n", hdr->type); + dprintk(DBGLVL_API, " 3.%x\n", hdr->subtype); + dprintk(DBGLVL_API, " 4.%x\n", hdr->unitid); + + idx += hdr->len; + } + + return 0; +} + +int saa7164_api_enum_subdevs(struct saa7164_dev *dev) +{ + int ret; + u32 buflen = 0; + u8 *buf; + + dprintk(DBGLVL_API, "%s()\n", __func__); + + /* Get the total descriptor length */ + ret = saa7164_cmd_send(dev, 0, GET_LEN, + GET_DESCRIPTORS_CONTROL, sizeof(buflen), &buflen); + if (ret != SAA_OK) + printk(KERN_ERR "%s() error, ret = 0x%x\n", __func__, ret); + + dprintk(DBGLVL_API, "%s() total descriptor size = %d bytes.\n", + __func__, buflen); + + /* Allocate enough storage for all of the descs */ + buf = kzalloc(buflen, GFP_KERNEL); + if (buf == NULL) + return SAA_ERR_NO_RESOURCES; + + /* Retrieve them */ + ret = saa7164_cmd_send(dev, 0, GET_CUR, + GET_DESCRIPTORS_CONTROL, buflen, buf); + if (ret != SAA_OK) { + printk(KERN_ERR "%s() error, ret = 0x%x\n", __func__, ret); + goto out; + } + + if (debug & DBGLVL_API) + saa7164_dumphex16(dev, buf, (buflen/16)*16); + + saa7164_api_dump_subdevs(dev, buf, buflen); + +out: + kfree(buf); + return ret; +} + +int saa7164_api_i2c_read(struct saa7164_i2c *bus, u8 addr, u32 reglen, u8 *reg, + u32 datalen, u8 *data) +{ + struct saa7164_dev *dev = bus->dev; + u16 len = 0; + int unitid; + u32 regval; + u8 buf[256]; + int ret; + + dprintk(DBGLVL_API, "%s()\n", __func__); + + if (reglen > 4) + return -EIO; + + if (reglen == 1) + regval = *(reg); + else + if (reglen == 2) + regval = ((*(reg) << 8) || *(reg+1)); + else + if (reglen == 3) + regval = ((*(reg) << 16) | (*(reg+1) << 8) | *(reg+2)); + else + if (reglen == 4) + regval = ((*(reg) << 24) | (*(reg+1) << 16) | + (*(reg+2) << 8) | *(reg+3)); + + /* Prepare the send buffer */ + /* Bytes 00-03 source register length + * 04-07 source bytes to read + * 08... register address + */ + memset(buf, 0, sizeof(buf)); + memcpy((buf + 2 * sizeof(u32) + 0), reg, reglen); + *((u32 *)(buf + 0 * sizeof(u32))) = reglen; + *((u32 *)(buf + 1 * sizeof(u32))) = datalen; + + unitid = saa7164_i2caddr_to_unitid(bus, addr); + if (unitid < 0) { + printk(KERN_ERR + "%s() error, cannot translate regaddr 0x%x to unitid\n", + __func__, addr); + return -EIO; + } + + ret = saa7164_cmd_send(bus->dev, unitid, GET_LEN, + EXU_REGISTER_ACCESS_CONTROL, sizeof(len), &len); + if (ret != SAA_OK) { + printk(KERN_ERR "%s() error, ret(1) = 0x%x\n", __func__, ret); + return -EIO; + } + + dprintk(DBGLVL_API, "%s() len = %d bytes\n", __func__, len); + + if (debug & DBGLVL_I2C) + saa7164_dumphex16(dev, buf, 2 * 16); + + ret = saa7164_cmd_send(bus->dev, unitid, GET_CUR, + EXU_REGISTER_ACCESS_CONTROL, len, &buf); + if (ret != SAA_OK) + printk(KERN_ERR "%s() error, ret(2) = 0x%x\n", __func__, ret); + else { + if (debug & DBGLVL_I2C) + saa7164_dumphex16(dev, buf, sizeof(buf)); + memcpy(data, (buf + 2 * sizeof(u32) + reglen), datalen); + } + + return ret == SAA_OK ? 0 : -EIO; +} + +/* For a given 8 bit i2c address device, write the buffer */ +int saa7164_api_i2c_write(struct saa7164_i2c *bus, u8 addr, u32 datalen, + u8 *data) +{ + struct saa7164_dev *dev = bus->dev; + u16 len = 0; + int unitid; + int reglen; + u8 buf[256]; + int ret; + + dprintk(DBGLVL_API, "%s()\n", __func__); + + if ((datalen == 0) || (datalen > 232)) + return -EIO; + + memset(buf, 0, sizeof(buf)); + + unitid = saa7164_i2caddr_to_unitid(bus, addr); + if (unitid < 0) { + printk(KERN_ERR + "%s() error, cannot translate regaddr 0x%x to unitid\n", + __func__, addr); + return -EIO; + } + + reglen = saa7164_i2caddr_to_reglen(bus, addr); + if (unitid < 0) { + printk(KERN_ERR + "%s() error, cannot translate regaddr to reglen\n", + __func__); + return -EIO; + } + + ret = saa7164_cmd_send(bus->dev, unitid, GET_LEN, + EXU_REGISTER_ACCESS_CONTROL, sizeof(len), &len); + if (ret != SAA_OK) { + printk(KERN_ERR "%s() error, ret(1) = 0x%x\n", __func__, ret); + return -EIO; + } + + dprintk(DBGLVL_API, "%s() len = %d bytes\n", __func__, len); + + /* Prepare the send buffer */ + /* Bytes 00-03 dest register length + * 04-07 dest bytes to write + * 08... register address + */ + *((u32 *)(buf + 0 * sizeof(u32))) = reglen; + *((u32 *)(buf + 1 * sizeof(u32))) = datalen - reglen; + memcpy((buf + 2 * sizeof(u32)), data, datalen); + + if (debug & DBGLVL_I2C) + saa7164_dumphex16(dev, buf, sizeof(buf)); + + ret = saa7164_cmd_send(bus->dev, unitid, SET_CUR, + EXU_REGISTER_ACCESS_CONTROL, len, &buf); + if (ret != SAA_OK) + printk(KERN_ERR "%s() error, ret(2) = 0x%x\n", __func__, ret); + + return ret == SAA_OK ? 0 : -EIO; +} + + +int saa7164_api_modify_gpio(struct saa7164_dev *dev, u8 unitid, + u8 pin, u8 state) +{ + int ret; + tmComResGPIO_t t; + + dprintk(DBGLVL_API, "%s(0x%x, %d, %d)\n", + __func__, unitid, pin, state); + + if ((pin > 7) || (state > 2)) + return SAA_ERR_BAD_PARAMETER; + + t.pin = pin; + t.state = state; + + ret = saa7164_cmd_send(dev, unitid, SET_CUR, + EXU_GPIO_CONTROL, sizeof(t), &t); + if (ret != SAA_OK) + printk(KERN_ERR "%s() error, ret = 0x%x\n", + __func__, ret); + + return ret; +} + +int saa7164_api_set_gpiobit(struct saa7164_dev *dev, u8 unitid, + u8 pin) +{ + return saa7164_api_modify_gpio(dev, unitid, pin, 1); +} + +int saa7164_api_clear_gpiobit(struct saa7164_dev *dev, u8 unitid, + u8 pin) +{ + return saa7164_api_modify_gpio(dev, unitid, pin, 0); +} + + + diff --git a/drivers/media/video/saa7164/saa7164-buffer.c b/drivers/media/video/saa7164/saa7164-buffer.c new file mode 100644 index 000000000000..9ca5c83d165b --- /dev/null +++ b/drivers/media/video/saa7164/saa7164-buffer.c @@ -0,0 +1,155 @@ +/* + * Driver for the NXP SAA7164 PCIe bridge + * + * Copyright (c) 2009 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "saa7164.h" + +/* The PCI address space for buffer handling looks like this: + + +-u32 wide-------------+ + | + + +-u64 wide------------------------------------+ + + + + +----------------------+ + | CurrentBufferPtr + Pointer to current PCI buffer >-+ + +----------------------+ | + | Unused + | + +----------------------+ | + | Pitch + = 188 (bytes) | + +----------------------+ | + | PCI buffer size + = pitch * number of lines (312) | + +----------------------+ | + |0| Buf0 Write Offset + | + +----------------------+ v + |1| Buf1 Write Offset + | + +----------------------+ | + |2| Buf2 Write Offset + | + +----------------------+ | + |3| Buf3 Write Offset + | + +----------------------+ | + ... More write offsets | + +---------------------------------------------+ | + +0| set of ptrs to PCI pagetables + | + +---------------------------------------------+ | + +1| set of ptrs to PCI pagetables + <--------+ + +---------------------------------------------+ + +2| set of ptrs to PCI pagetables + + +---------------------------------------------+ + +3| set of ptrs to PCI pagetables + >--+ + +---------------------------------------------+ | + ... More buffer pointers | +----------------+ + +->| pt[0] TS data | + | +----------------+ + | + | +----------------+ + +->| pt[1] TS data | + | +----------------+ + | etc + */ + +/* Allocate a new buffer structure and associated PCI space in bytes. + * len must be a multiple of sizeof(u64) + */ +struct saa7164_buffer *saa7164_buffer_alloc(struct saa7164_tsport *port, + u32 len) +{ + struct saa7164_buffer *buf = 0; + struct saa7164_dev *dev = port->dev; + int i; + + if ((len == 0) || (len >= 65536) || (len % sizeof(u64))) { + log_warn("%s() SAA_ERR_BAD_PARAMETER\n", __func__); + goto ret; + } + + buf = kzalloc(sizeof(struct saa7164_buffer), GFP_KERNEL); + if (buf == NULL) { + log_warn("%s() SAA_ERR_NO_RESOURCES\n", __func__); + goto ret; + } + + buf->port = port; + buf->flags = SAA7164_BUFFER_FREE; + /* TODO: arg len is being ignored */ + buf->pci_size = SAA7164_PT_ENTRIES * 0x1000; + buf->pt_size = (SAA7164_PT_ENTRIES * sizeof(u64)) + 0x1000; + + /* Allocate contiguous memory */ + buf->cpu = pci_alloc_consistent(port->dev->pci, buf->pci_size, + &buf->dma); + if (!buf->cpu) + goto fail1; + + buf->pt_cpu = pci_alloc_consistent(port->dev->pci, buf->pt_size, + &buf->pt_dma); + if (!buf->pt_cpu) + goto fail2; + + /* init the buffers to a known pattern, easier during debugging */ + memset(buf->cpu, 0xff, buf->pci_size); + memset(buf->pt_cpu, 0xff, buf->pt_size); + + dprintk(DBGLVL_BUF, "%s() allocated buffer @ 0x%p\n", __func__, buf); + dprintk(DBGLVL_BUF, " pci_cpu @ 0x%p dma @ 0x%08lx len = 0x%x\n", + buf->cpu, (long)buf->dma, buf->pci_size); + dprintk(DBGLVL_BUF, " pt_cpu @ 0x%p pt_dma @ 0x%08lx len = 0x%x\n", + buf->pt_cpu, (long)buf->pt_dma, buf->pt_size); + + /* Format the Page Table Entries to point into the data buffer */ + for (i = 0 ; i < SAA7164_PT_ENTRIES; i++) { + + *(buf->pt_cpu + i) = buf->dma + (i * 0x1000); /* TODO */ + + } + + goto ret; + +fail2: + pci_free_consistent(port->dev->pci, buf->pci_size, buf->cpu, buf->dma); +fail1: + kfree(buf); + + buf = 0; +ret: + return buf; +} + +int saa7164_buffer_dealloc(struct saa7164_tsport *port, + struct saa7164_buffer *buf) +{ + struct saa7164_dev *dev = port->dev; + + if ((buf == 0) || (port == 0)) + return SAA_ERR_BAD_PARAMETER; + + dprintk(DBGLVL_BUF, "%s() deallocating buffer @ 0x%p\n", __func__, buf); + + if (buf->flags != SAA7164_BUFFER_FREE) + log_warn(" freeing a non-free buffer\n"); + + pci_free_consistent(port->dev->pci, buf->pci_size, buf->cpu, buf->dma); + pci_free_consistent(port->dev->pci, buf->pt_size, buf->pt_cpu, + buf->pt_dma); + + kfree(buf); + + return SAA_OK; +} + diff --git a/drivers/media/video/saa7164/saa7164-bus.c b/drivers/media/video/saa7164/saa7164-bus.c new file mode 100644 index 000000000000..83a04640a25a --- /dev/null +++ b/drivers/media/video/saa7164/saa7164-bus.c @@ -0,0 +1,448 @@ +/* + * Driver for the NXP SAA7164 PCIe bridge + * + * Copyright (c) 2009 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "saa7164.h" + +/* The message bus to/from the firmware is a ring buffer in PCI address + * space. Establish the defaults. + */ +int saa7164_bus_setup(struct saa7164_dev *dev) +{ + tmComResBusInfo_t *b = &dev->bus; + + mutex_init(&b->lock); + + b->Type = TYPE_BUS_PCIe; + b->m_wMaxReqSize = SAA_DEVICE_MAXREQUESTSIZE; + + b->m_pdwSetRing = (u8 *)(dev->bmmio + + ((u32)dev->busdesc.CommandRing)); + + b->m_dwSizeSetRing = SAA_DEVICE_BUFFERBLOCKSIZE; + + b->m_pdwGetRing = (u8 *)(dev->bmmio + + ((u32)dev->busdesc.ResponseRing)); + + b->m_dwSizeGetRing = SAA_DEVICE_BUFFERBLOCKSIZE; + + b->m_pdwSetWritePos = (u32 *)((u8 *)(dev->bmmio + + ((u32)dev->intfdesc.BARLocation) + (2 * sizeof(u64)))); + + b->m_pdwSetReadPos = (u32 *)((u8 *)b->m_pdwSetWritePos + + 1 * sizeof(u32)); + + b->m_pdwGetWritePos = (u32 *)((u8 *)b->m_pdwSetWritePos + + 2 * sizeof(u32)); + + b->m_pdwGetReadPos = (u32 *)((u8 *)b->m_pdwSetWritePos + + 3 * sizeof(u32)); + + return 0; +} + +void saa7164_bus_dump(struct saa7164_dev *dev) +{ + tmComResBusInfo_t *b = &dev->bus; + + dprintk(DBGLVL_BUS, "Dumping the bus structure:\n"); + dprintk(DBGLVL_BUS, " .type = %d\n", b->Type); + dprintk(DBGLVL_BUS, " .dev->bmmio = 0x%p\n", dev->bmmio); + dprintk(DBGLVL_BUS, " .m_wMaxReqSize = 0x%x\n", b->m_wMaxReqSize); + dprintk(DBGLVL_BUS, " .m_pdwSetRing = 0x%p\n", b->m_pdwSetRing); + dprintk(DBGLVL_BUS, " .m_dwSizeSetRing = 0x%x\n", b->m_dwSizeSetRing); + dprintk(DBGLVL_BUS, " .m_pdwGetRing = 0x%p\n", b->m_pdwGetRing); + dprintk(DBGLVL_BUS, " .m_dwSizeGetRing = 0x%x\n", b->m_dwSizeGetRing); + + dprintk(DBGLVL_BUS, " .m_pdwSetWritePos = 0x%p (0x%08x)\n", + b->m_pdwSetWritePos, *b->m_pdwSetWritePos); + + dprintk(DBGLVL_BUS, " .m_pdwSetReadPos = 0x%p (0x%08x)\n", + b->m_pdwSetReadPos, *b->m_pdwSetReadPos); + + dprintk(DBGLVL_BUS, " .m_pdwGetWritePos = 0x%p (0x%08x)\n", + b->m_pdwGetWritePos, *b->m_pdwGetWritePos); + + dprintk(DBGLVL_BUS, " .m_pdwGetReadPos = 0x%p (0x%08x)\n", + b->m_pdwGetReadPos, *b->m_pdwGetReadPos); +} + +void saa7164_bus_dumpmsg(struct saa7164_dev *dev, tmComResInfo_t* m, void *buf) +{ + dprintk(DBGLVL_BUS, "Dumping msg structure:\n"); + dprintk(DBGLVL_BUS, " .id = %d\n", m->id); + dprintk(DBGLVL_BUS, " .flags = 0x%x\n", m->flags); + dprintk(DBGLVL_BUS, " .size = 0x%x\n", m->size); + dprintk(DBGLVL_BUS, " .command = 0x%x\n", m->command); + dprintk(DBGLVL_BUS, " .controlselector = 0x%x\n", m->controlselector); + dprintk(DBGLVL_BUS, " .seqno = %d\n", m->seqno); + if (buf) + dprintk(DBGLVL_BUS, " .buffer (ignored)\n"); +} + +/* + * Places a command or a response on the bus. The implementation does not + * know if it is a command or a response it just places the data on the + * bus depending on the bus information given in the tmComResBusInfo_t + * structure. If the command or response does not fit into the bus ring + * buffer it will be refused. + * + * Return Value: + * SAA_OK The function executed successfully. + * < 0 One or more members are not initialized. + */ +int saa7164_bus_set(struct saa7164_dev *dev, tmComResInfo_t* msg, void *buf) +{ + tmComResBusInfo_t *bus = &dev->bus; + u32 bytes_to_write, read_distance, timeout, curr_srp, curr_swp; + u32 new_swp, space_rem; + int ret = SAA_ERR_BAD_PARAMETER; + + if (!msg) { + printk(KERN_ERR "%s() !msg\n", __func__); + return SAA_ERR_BAD_PARAMETER; + } + + dprintk(DBGLVL_BUS, "%s()\n", __func__); + + msg->size = cpu_to_le16(msg->size); + msg->command = cpu_to_le16(msg->command); + msg->controlselector = cpu_to_le16(msg->controlselector); + + if (msg->size > dev->bus.m_wMaxReqSize) { + printk(KERN_ERR "%s() Exceeded dev->bus.m_wMaxReqSize\n", + __func__); + return SAA_ERR_BAD_PARAMETER; + } + + if ((msg->size > 0) && (buf == 0)) { + printk(KERN_ERR "%s() Missing message buffer\n", __func__); + return SAA_ERR_BAD_PARAMETER; + } + + /* Lock the bus from any other access */ + mutex_lock(&bus->lock); + + bytes_to_write = sizeof(*msg) + msg->size; + read_distance = 0; + timeout = SAA_BUS_TIMEOUT; + curr_srp = le32_to_cpu(*bus->m_pdwSetReadPos); + curr_swp = le32_to_cpu(*bus->m_pdwSetWritePos); + + /* Deal with ring wrapping issues */ + if (curr_srp > curr_swp) + /* The ring has not wrapped yet */ + read_distance = curr_srp - curr_swp; + else + /* Deal with the wrapped ring */ + read_distance = (curr_srp + bus->m_dwSizeSetRing) - curr_swp; + + dprintk(DBGLVL_BUS, "%s() bytes_to_write = %d\n", __func__, + bytes_to_write); + + dprintk(DBGLVL_BUS, "%s() read_distance = %d\n", __func__, + read_distance); + + dprintk(DBGLVL_BUS, "%s() curr_srp = %x\n", __func__, curr_srp); + dprintk(DBGLVL_BUS, "%s() curr_swp = %x\n", __func__, curr_swp); + + /* Process the msg and write the content onto the bus */ + while (bytes_to_write >= read_distance) { + + if (timeout-- == 0) { + printk(KERN_ERR "%s() bus timeout\n", __func__); + ret = SAA_ERR_NO_RESOURCES; + goto out; + } + + /* TODO: Review this delay, efficient? */ + /* Wait, allowing the hardware fetch time */ + mdelay(1); + + /* Check the space usage again */ + curr_srp = le32_to_cpu(*bus->m_pdwSetReadPos); + + /* Deal with ring wrapping issues */ + if (curr_srp > curr_swp) + /* Read didn't wrap around the buffer */ + read_distance = curr_srp - curr_swp; + else + /* Deal with the wrapped ring */ + read_distance = (curr_srp + bus->m_dwSizeSetRing) - + curr_swp; + + } + + /* Calculate the new write position */ + new_swp = curr_swp + bytes_to_write; + + dprintk(DBGLVL_BUS, "%s() new_swp = %x\n", __func__, new_swp); + dprintk(DBGLVL_BUS, "%s() bus->m_dwSizeSetRing = %x\n", __func__, + bus->m_dwSizeSetRing); + + /* Mental Note: line 462 tmmhComResBusPCIe.cpp */ + + /* Check if we're going to wrap again */ + if (new_swp > bus->m_dwSizeSetRing) { + + /* Ring wraps */ + new_swp -= bus->m_dwSizeSetRing; + + space_rem = bus->m_dwSizeSetRing - curr_swp; + + dprintk(DBGLVL_BUS, "%s() space_rem = %x\n", __func__, + space_rem); + + dprintk(DBGLVL_BUS, "%s() sizeof(*msg) = %d\n", __func__, + (u32)sizeof(*msg)); + + if (space_rem < sizeof(*msg)) { + dprintk(DBGLVL_BUS, "%s() tr4\n", __func__); + + /* Split the msg into pieces as the ring wraps */ + memcpy(bus->m_pdwSetRing + curr_swp, msg, space_rem); + memcpy(bus->m_pdwSetRing, (u8 *)msg + space_rem, + sizeof(*msg) - space_rem); + + memcpy(bus->m_pdwSetRing + sizeof(*msg) - space_rem, + buf, msg->size); + + } else if (space_rem == sizeof(*msg)) { + dprintk(DBGLVL_BUS, "%s() tr5\n", __func__); + + /* Additional data at the beginning of the ring */ + memcpy(bus->m_pdwSetRing + curr_swp, msg, sizeof(*msg)); + memcpy(bus->m_pdwSetRing, buf, msg->size); + + } else { + /* Additional data wraps around the ring */ + memcpy(bus->m_pdwSetRing + curr_swp, msg, sizeof(*msg)); + if (msg->size > 0) { + memcpy(bus->m_pdwSetRing + curr_swp + + sizeof(*msg), buf, space_rem - + sizeof(*msg)); + memcpy(bus->m_pdwSetRing, (u8 *)buf + + space_rem - sizeof(*msg), + bytes_to_write - space_rem); + } + + } + + } /* (new_swp > bus->m_dwSizeSetRing) */ + else { + dprintk(DBGLVL_BUS, "%s() tr6\n", __func__); + + /* The ring buffer doesn't wrap, two simple copies */ + memcpy(bus->m_pdwSetRing + curr_swp, msg, sizeof(*msg)); + memcpy(bus->m_pdwSetRing + curr_swp + sizeof(*msg), buf, + msg->size); + } + + dprintk(DBGLVL_BUS, "%s() new_swp = %x\n", __func__, new_swp); + + /* TODO: Convert all of the direct PCI writes into + * saa7164_writel/b calls for consistency. + */ + + /* Update the bus write position */ + *bus->m_pdwSetWritePos = cpu_to_le32(new_swp); + ret = SAA_OK; + +out: + mutex_unlock(&bus->lock); + return ret; +} + +/* + * Receive a command or a response from the bus. The implementation does not + * know if it is a command or a response it simply dequeues the data, + * depending on the bus information given in the tmComResBusInfo_t structure. + * + * Return Value: + * 0 The function executed successfully. + * < 0 One or more members are not initialized. + */ +int saa7164_bus_get(struct saa7164_dev *dev, tmComResInfo_t* msg, void *buf, + int peekonly) +{ + tmComResBusInfo_t *bus = &dev->bus; + u32 bytes_to_read, write_distance, curr_grp, curr_gwp, + new_grp, buf_size, space_rem; + tmComResInfo_t msg_tmp; + int ret = SAA_ERR_BAD_PARAMETER; + + if (msg == 0) + return ret; + + if (msg->size > dev->bus.m_wMaxReqSize) { + printk(KERN_ERR "%s() Exceeded dev->bus.m_wMaxReqSize\n", + __func__); + return ret; + } + + if ((peekonly == 0) && (msg->size > 0) && (buf == 0)) { + printk(KERN_ERR + "%s() Missing msg buf, size should be %d bytes\n", + __func__, msg->size); + return ret; + } + + mutex_lock(&bus->lock); + + /* Peek the bus to see if a msg exists, if it's not what we're expecting + * then return cleanly else read the message from the bus. + */ + curr_gwp = le32_to_cpu(*bus->m_pdwGetWritePos); + curr_grp = le32_to_cpu(*bus->m_pdwGetReadPos); + + if (curr_gwp == curr_grp) { + dprintk(DBGLVL_BUS, "%s() No message on the bus\n", __func__); + ret = SAA_ERR_EMPTY; + goto out; + } + + bytes_to_read = sizeof(*msg); + + /* Calculate write distance to current read position */ + write_distance = 0; + if (curr_gwp >= curr_grp) + /* Write doesn't wrap around the ring */ + write_distance = curr_gwp - curr_grp; + else + /* Write wraps around the ring */ + write_distance = curr_gwp + bus->m_dwSizeGetRing - curr_grp; + + if (bytes_to_read > write_distance) { + printk(KERN_ERR "%s() No message/response found\n", __func__); + ret = SAA_ERR_INVALID_COMMAND; + goto out; + } + + /* Calculate the new read position */ + new_grp = curr_grp + bytes_to_read; + if (new_grp > bus->m_dwSizeGetRing) { + + /* Ring wraps */ + new_grp -= bus->m_dwSizeGetRing; + space_rem = bus->m_dwSizeGetRing - curr_grp; + + memcpy(&msg_tmp, bus->m_pdwGetRing + curr_grp, space_rem); + memcpy((u8 *)&msg_tmp + space_rem, bus->m_pdwGetRing, + bytes_to_read - space_rem); + + } else { + /* No wrapping */ + memcpy(&msg_tmp, bus->m_pdwGetRing + curr_grp, bytes_to_read); + } + + /* No need to update the read positions, because this was a peek */ + /* If the caller specifically want to peek, return */ + if (peekonly) { + memcpy(msg, &msg_tmp, sizeof(*msg)); + goto peekout; + } + + /* Check if the command/response matches what is expected */ + if ((msg_tmp.id != msg->id) || (msg_tmp.command != msg->command) || + (msg_tmp.controlselector != msg->controlselector) || + (msg_tmp.seqno != msg->seqno) || (msg_tmp.size != msg->size)) { + + printk(KERN_ERR "%s() Unexpected msg miss-match\n", __func__); + saa7164_bus_dumpmsg(dev, msg, buf); + saa7164_bus_dumpmsg(dev, &msg_tmp, 0); + ret = SAA_ERR_INVALID_COMMAND; + goto out; + } + + /* Get the actual command and response from the bus */ + buf_size = msg->size; + + bytes_to_read = sizeof(*msg) + msg->size; + /* Calculate write distance to current read position */ + write_distance = 0; + if (curr_gwp >= curr_grp) + /* Write doesn't wrap around the ring */ + write_distance = curr_gwp - curr_grp; + else + /* Write wraps around the ring */ + write_distance = curr_gwp + bus->m_dwSizeGetRing - curr_grp; + + if (bytes_to_read > write_distance) { + printk(KERN_ERR "%s() Invalid bus state, missing msg " + "or mangled ring, faulty H/W / bad code?\n", __func__); + ret = SAA_ERR_INVALID_COMMAND; + goto out; + } + + /* Calculate the new read position */ + new_grp = curr_grp + bytes_to_read; + if (new_grp > bus->m_dwSizeGetRing) { + + /* Ring wraps */ + new_grp -= bus->m_dwSizeGetRing; + space_rem = bus->m_dwSizeGetRing - curr_grp; + + if (space_rem < sizeof(*msg)) { + /* msg wraps around the ring */ + memcpy(msg, bus->m_pdwGetRing + curr_grp, space_rem); + memcpy((u8 *)msg + space_rem, bus->m_pdwGetRing, + sizeof(*msg) - space_rem); + if (buf) + memcpy(buf, bus->m_pdwGetRing + sizeof(*msg) - + space_rem, buf_size); + + } else if (space_rem == sizeof(*msg)) { + memcpy(msg, bus->m_pdwGetRing + curr_grp, sizeof(*msg)); + if (buf) + memcpy(buf, bus->m_pdwGetRing, buf_size); + } else { + /* Additional data wraps around the ring */ + memcpy(msg, bus->m_pdwGetRing + curr_grp, sizeof(*msg)); + if (buf) { + memcpy(buf, bus->m_pdwGetRing + curr_grp + + sizeof(*msg), space_rem - sizeof(*msg)); + memcpy(buf + space_rem - sizeof(*msg), + bus->m_pdwGetRing, bytes_to_read - + space_rem); + } + + } + + } else { + /* No wrapping */ + memcpy(msg, bus->m_pdwGetRing + curr_grp, sizeof(*msg)); + if (buf) + memcpy(buf, bus->m_pdwGetRing + curr_grp + sizeof(*msg), + buf_size); + } + + /* Update the read positions, adjusting the ring */ + *bus->m_pdwGetReadPos = cpu_to_le32(new_grp); + +peekout: + msg->size = le16_to_cpu(msg->size); + msg->command = le16_to_cpu(msg->command); + msg->controlselector = le16_to_cpu(msg->controlselector); + ret = SAA_OK; +out: + mutex_unlock(&bus->lock); + return ret; +} + diff --git a/drivers/media/video/saa7164/saa7164-cards.c b/drivers/media/video/saa7164/saa7164-cards.c new file mode 100644 index 000000000000..a3c299405f46 --- /dev/null +++ b/drivers/media/video/saa7164/saa7164-cards.c @@ -0,0 +1,624 @@ +/* + * Driver for the NXP SAA7164 PCIe bridge + * + * Copyright (c) 2009 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +#include "saa7164.h" + +/* The Bridge API needs to understand register widths (in bytes) for the + * attached I2C devices, so we can simplify the virtual i2c mechansms + * and keep the -i2c.c implementation clean. + */ +#define REGLEN_8bit 1 +#define REGLEN_16bit 2 + +struct saa7164_board saa7164_boards[] = { + [SAA7164_BOARD_UNKNOWN] = { + /* Bridge will not load any firmware, without knowing + * the rev this would be fatal. */ + .name = "Unknown", + }, + [SAA7164_BOARD_UNKNOWN_REV2] = { + /* Bridge will load the v2 f/w and dump descriptors */ + /* Required during new board bringup */ + .name = "Generic Rev2", + .chiprev = SAA7164_CHIP_REV2, + }, + [SAA7164_BOARD_UNKNOWN_REV3] = { + /* Bridge will load the v2 f/w and dump descriptors */ + /* Required during new board bringup */ + .name = "Generic Rev3", + .chiprev = SAA7164_CHIP_REV3, + }, + [SAA7164_BOARD_HAUPPAUGE_HVR2200] = { + .name = "Hauppauge WinTV-HVR2200", + .porta = SAA7164_MPEG_DVB, + .portb = SAA7164_MPEG_DVB, + .chiprev = SAA7164_CHIP_REV3, + .unit = {{ + .id = 0x1d, + .type = SAA7164_UNIT_EEPROM, + .name = "4K EEPROM", + .i2c_bus_nr = SAA7164_I2C_BUS_0, + .i2c_bus_addr = 0xa0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x04, + .type = SAA7164_UNIT_TUNER, + .name = "TDA18271-1", + .i2c_bus_nr = SAA7164_I2C_BUS_1, + .i2c_bus_addr = 0xc0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x1b, + .type = SAA7164_UNIT_TUNER, + .name = "TDA18271-2", + .i2c_bus_nr = SAA7164_I2C_BUS_2, + .i2c_bus_addr = 0xc0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x1e, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "TDA10048-1", + .i2c_bus_nr = SAA7164_I2C_BUS_1, + .i2c_bus_addr = 0x10 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x1f, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "TDA10048-2", + .i2c_bus_nr = SAA7164_I2C_BUS_2, + .i2c_bus_addr = 0x12 >> 1, + .i2c_reg_len = REGLEN_8bit, + } }, + }, + [SAA7164_BOARD_HAUPPAUGE_HVR2200_2] = { + .name = "Hauppauge WinTV-HVR2200", + .porta = SAA7164_MPEG_DVB, + .portb = SAA7164_MPEG_DVB, + .chiprev = SAA7164_CHIP_REV2, + .unit = {{ + .id = 0x06, + .type = SAA7164_UNIT_EEPROM, + .name = "4K EEPROM", + .i2c_bus_nr = SAA7164_I2C_BUS_0, + .i2c_bus_addr = 0xa0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x04, + .type = SAA7164_UNIT_TUNER, + .name = "TDA18271-1", + .i2c_bus_nr = SAA7164_I2C_BUS_1, + .i2c_bus_addr = 0xc0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x05, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "TDA10048-1", + .i2c_bus_nr = SAA7164_I2C_BUS_1, + .i2c_bus_addr = 0x10 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x1e, + .type = SAA7164_UNIT_TUNER, + .name = "TDA18271-2", + .i2c_bus_nr = SAA7164_I2C_BUS_2, + .i2c_bus_addr = 0xc0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x1f, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "TDA10048-2", + .i2c_bus_nr = SAA7164_I2C_BUS_2, + .i2c_bus_addr = 0x12 >> 1, + .i2c_reg_len = REGLEN_8bit, + } }, + }, + [SAA7164_BOARD_HAUPPAUGE_HVR2200_3] = { + .name = "Hauppauge WinTV-HVR2200", + .porta = SAA7164_MPEG_DVB, + .portb = SAA7164_MPEG_DVB, + .chiprev = SAA7164_CHIP_REV2, + .unit = {{ + .id = 0x1d, + .type = SAA7164_UNIT_EEPROM, + .name = "4K EEPROM", + .i2c_bus_nr = SAA7164_I2C_BUS_0, + .i2c_bus_addr = 0xa0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x04, + .type = SAA7164_UNIT_TUNER, + .name = "TDA18271-1", + .i2c_bus_nr = SAA7164_I2C_BUS_1, + .i2c_bus_addr = 0xc0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x05, + .type = SAA7164_UNIT_ANALOG_DEMODULATOR, + .name = "TDA8290-1", + .i2c_bus_nr = SAA7164_I2C_BUS_1, + .i2c_bus_addr = 0x84 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x1b, + .type = SAA7164_UNIT_TUNER, + .name = "TDA18271-2", + .i2c_bus_nr = SAA7164_I2C_BUS_2, + .i2c_bus_addr = 0xc0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x1c, + .type = SAA7164_UNIT_ANALOG_DEMODULATOR, + .name = "TDA8290-2", + .i2c_bus_nr = SAA7164_I2C_BUS_2, + .i2c_bus_addr = 0x84 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x1e, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "TDA10048-1", + .i2c_bus_nr = SAA7164_I2C_BUS_1, + .i2c_bus_addr = 0x10 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x1f, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "TDA10048-2", + .i2c_bus_nr = SAA7164_I2C_BUS_2, + .i2c_bus_addr = 0x12 >> 1, + .i2c_reg_len = REGLEN_8bit, + } }, + }, + [SAA7164_BOARD_HAUPPAUGE_HVR2250] = { + .name = "Hauppauge WinTV-HVR2250", + .porta = SAA7164_MPEG_DVB, + .portb = SAA7164_MPEG_DVB, + .chiprev = SAA7164_CHIP_REV3, + .unit = {{ + .id = 0x22, + .type = SAA7164_UNIT_EEPROM, + .name = "4K EEPROM", + .i2c_bus_nr = SAA7164_I2C_BUS_0, + .i2c_bus_addr = 0xa0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x04, + .type = SAA7164_UNIT_TUNER, + .name = "TDA18271-1", + .i2c_bus_nr = SAA7164_I2C_BUS_1, + .i2c_bus_addr = 0xc0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x07, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "CX24228/S5H1411-1 (TOP)", + .i2c_bus_nr = SAA7164_I2C_BUS_1, + .i2c_bus_addr = 0x32 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x08, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "CX24228/S5H1411-1 (QAM)", + .i2c_bus_nr = SAA7164_I2C_BUS_1, + .i2c_bus_addr = 0x34 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x1e, + .type = SAA7164_UNIT_TUNER, + .name = "TDA18271-2", + .i2c_bus_nr = SAA7164_I2C_BUS_2, + .i2c_bus_addr = 0xc0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x20, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "CX24228/S5H1411-2 (TOP)", + .i2c_bus_nr = SAA7164_I2C_BUS_2, + .i2c_bus_addr = 0x32 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x23, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "CX24228/S5H1411-2 (QAM)", + .i2c_bus_nr = SAA7164_I2C_BUS_2, + .i2c_bus_addr = 0x34 >> 1, + .i2c_reg_len = REGLEN_8bit, + } }, + }, + [SAA7164_BOARD_HAUPPAUGE_HVR2250_2] = { + .name = "Hauppauge WinTV-HVR2250", + .porta = SAA7164_MPEG_DVB, + .portb = SAA7164_MPEG_DVB, + .chiprev = SAA7164_CHIP_REV3, + .unit = {{ + .id = 0x28, + .type = SAA7164_UNIT_EEPROM, + .name = "4K EEPROM", + .i2c_bus_nr = SAA7164_I2C_BUS_0, + .i2c_bus_addr = 0xa0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x04, + .type = SAA7164_UNIT_TUNER, + .name = "TDA18271-1", + .i2c_bus_nr = SAA7164_I2C_BUS_1, + .i2c_bus_addr = 0xc0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x07, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "CX24228/S5H1411-1 (TOP)", + .i2c_bus_nr = SAA7164_I2C_BUS_1, + .i2c_bus_addr = 0x32 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x08, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "CX24228/S5H1411-1 (QAM)", + .i2c_bus_nr = SAA7164_I2C_BUS_1, + .i2c_bus_addr = 0x34 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x24, + .type = SAA7164_UNIT_TUNER, + .name = "TDA18271-2", + .i2c_bus_nr = SAA7164_I2C_BUS_2, + .i2c_bus_addr = 0xc0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x26, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "CX24228/S5H1411-2 (TOP)", + .i2c_bus_nr = SAA7164_I2C_BUS_2, + .i2c_bus_addr = 0x32 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x29, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "CX24228/S5H1411-2 (QAM)", + .i2c_bus_nr = SAA7164_I2C_BUS_2, + .i2c_bus_addr = 0x34 >> 1, + .i2c_reg_len = REGLEN_8bit, + } }, + }, + [SAA7164_BOARD_HAUPPAUGE_HVR2250_3] = { + .name = "Hauppauge WinTV-HVR2250", + .porta = SAA7164_MPEG_DVB, + .portb = SAA7164_MPEG_DVB, + .chiprev = SAA7164_CHIP_REV3, + .unit = {{ + .id = 0x26, + .type = SAA7164_UNIT_EEPROM, + .name = "4K EEPROM", + .i2c_bus_nr = SAA7164_I2C_BUS_0, + .i2c_bus_addr = 0xa0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x04, + .type = SAA7164_UNIT_TUNER, + .name = "TDA18271-1", + .i2c_bus_nr = SAA7164_I2C_BUS_1, + .i2c_bus_addr = 0xc0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x07, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "CX24228/S5H1411-1 (TOP)", + .i2c_bus_nr = SAA7164_I2C_BUS_1, + .i2c_bus_addr = 0x32 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x08, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "CX24228/S5H1411-1 (QAM)", + .i2c_bus_nr = SAA7164_I2C_BUS_1, + .i2c_bus_addr = 0x34 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x22, + .type = SAA7164_UNIT_TUNER, + .name = "TDA18271-2", + .i2c_bus_nr = SAA7164_I2C_BUS_2, + .i2c_bus_addr = 0xc0 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x24, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "CX24228/S5H1411-2 (TOP)", + .i2c_bus_nr = SAA7164_I2C_BUS_2, + .i2c_bus_addr = 0x32 >> 1, + .i2c_reg_len = REGLEN_8bit, + }, { + .id = 0x27, + .type = SAA7164_UNIT_DIGITAL_DEMODULATOR, + .name = "CX24228/S5H1411-2 (QAM)", + .i2c_bus_nr = SAA7164_I2C_BUS_2, + .i2c_bus_addr = 0x34 >> 1, + .i2c_reg_len = REGLEN_8bit, + } }, + }, +}; +const unsigned int saa7164_bcount = ARRAY_SIZE(saa7164_boards); + +/* ------------------------------------------------------------------ */ +/* PCI subsystem IDs */ + +struct saa7164_subid saa7164_subids[] = { + { + .subvendor = 0x0070, + .subdevice = 0x8880, + .card = SAA7164_BOARD_HAUPPAUGE_HVR2250, + }, { + .subvendor = 0x0070, + .subdevice = 0x8810, + .card = SAA7164_BOARD_HAUPPAUGE_HVR2250, + }, { + .subvendor = 0x0070, + .subdevice = 0x8980, + .card = SAA7164_BOARD_HAUPPAUGE_HVR2200, + }, { + .subvendor = 0x0070, + .subdevice = 0x8900, + .card = SAA7164_BOARD_HAUPPAUGE_HVR2200_2, + }, { + .subvendor = 0x0070, + .subdevice = 0x8901, + .card = SAA7164_BOARD_HAUPPAUGE_HVR2200_3, + }, { + .subvendor = 0x0070, + .subdevice = 0x88A1, + .card = SAA7164_BOARD_HAUPPAUGE_HVR2250_3, + }, { + .subvendor = 0x0070, + .subdevice = 0x8891, + .card = SAA7164_BOARD_HAUPPAUGE_HVR2250_2, + }, { + .subvendor = 0x0070, + .subdevice = 0x8851, + .card = SAA7164_BOARD_HAUPPAUGE_HVR2250_2, + }, +}; +const unsigned int saa7164_idcount = ARRAY_SIZE(saa7164_subids); + +void saa7164_card_list(struct saa7164_dev *dev) +{ + int i; + + if (0 == dev->pci->subsystem_vendor && + 0 == dev->pci->subsystem_device) { + printk(KERN_ERR + "%s: Board has no valid PCIe Subsystem ID and can't\n" + "%s: be autodetected. Pass card= insmod option to\n" + "%s: workaround that. Send complaints to the vendor\n" + "%s: of the TV card. Best regards,\n" + "%s: -- tux\n", + dev->name, dev->name, dev->name, dev->name, dev->name); + } else { + printk(KERN_ERR + "%s: Your board isn't known (yet) to the driver.\n" + "%s: Try to pick one of the existing card configs via\n" + "%s: card= insmod option. Updating to the latest\n" + "%s: version might help as well.\n", + dev->name, dev->name, dev->name, dev->name); + } + + printk(KERN_ERR "%s: Here are valid choices for the card= insmod " + "option:\n", dev->name); + + for (i = 0; i < saa7164_bcount; i++) + printk(KERN_ERR "%s: card=%d -> %s\n", + dev->name, i, saa7164_boards[i].name); +} + +/* TODO: clean this define up into the -cards.c structs */ +#define PCIEBRIDGE_UNITID 2 + +void saa7164_gpio_setup(struct saa7164_dev *dev) +{ + + + switch (dev->board) { + case SAA7164_BOARD_HAUPPAUGE_HVR2200: + case SAA7164_BOARD_HAUPPAUGE_HVR2200_2: + case SAA7164_BOARD_HAUPPAUGE_HVR2200_3: + case SAA7164_BOARD_HAUPPAUGE_HVR2250: + case SAA7164_BOARD_HAUPPAUGE_HVR2250_2: + case SAA7164_BOARD_HAUPPAUGE_HVR2250_3: + /* + GPIO 2: s5h1411 / tda10048-1 demod reset + GPIO 3: s5h1411 / tda10048-2 demod reset + GPIO 7: IRBlaster Zilog reset + */ + + /* Reset parts by going in and out of reset */ + saa7164_api_clear_gpiobit(dev, PCIEBRIDGE_UNITID, 2); + saa7164_api_clear_gpiobit(dev, PCIEBRIDGE_UNITID, 3); + + msleep(10); + + saa7164_api_set_gpiobit(dev, PCIEBRIDGE_UNITID, 2); + saa7164_api_set_gpiobit(dev, PCIEBRIDGE_UNITID, 3); + break; + } + +} + +static void hauppauge_eeprom(struct saa7164_dev *dev, u8 *eeprom_data) +{ + struct tveeprom tv; + + /* TODO: Assumption: eeprom on bus 0 */ + tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv, + eeprom_data); + + /* Make sure we support the board model */ + switch (tv.model) { + case 88001: + /* Development board - Limit circulation */ + /* WinTV-HVR2250 (PCIe, Retail, full-height bracket) + * ATSC/QAM (TDA18271/S5H1411) and basic analog, no IR, FM */ + case 88021: + /* WinTV-HVR2250 (PCIe, Retail, full-height bracket) + * ATSC/QAM (TDA18271/S5H1411) and basic analog, MCE CIR, FM */ + break; + case 88041: + /* WinTV-HVR2250 (PCIe, Retail, full-height bracket) + * ATSC/QAM (TDA18271/S5H1411) and basic analog, no IR, FM */ + break; + case 88061: + /* WinTV-HVR2250 (PCIe, Retail, full-height bracket) + * ATSC/QAM (TDA18271/S5H1411) and basic analog, FM */ + break; + case 89519: + case 89609: + /* WinTV-HVR2200 (PCIe, Retail, full-height) + * DVB-T (TDA18271/TDA10048) and basic analog, no IR */ + break; + case 89619: + /* WinTV-HVR2200 (PCIe, Retail, half-height) + * DVB-T (TDA18271/TDA10048) and basic analog, no IR */ + break; + default: + printk(KERN_ERR "%s: Warning: Unknown Hauppauge model #%d\n", + dev->name, tv.model); + break; + } + + printk(KERN_INFO "%s: Hauppauge eeprom: model=%d\n", dev->name, + tv.model); +} + +void saa7164_card_setup(struct saa7164_dev *dev) +{ + static u8 eeprom[256]; + + if (dev->i2c_bus[0].i2c_rc == 0) { + if (saa7164_api_read_eeprom(dev, &eeprom[0], + sizeof(eeprom)) < 0) + return; + } + + switch (dev->board) { + case SAA7164_BOARD_HAUPPAUGE_HVR2200: + case SAA7164_BOARD_HAUPPAUGE_HVR2200_2: + case SAA7164_BOARD_HAUPPAUGE_HVR2200_3: + case SAA7164_BOARD_HAUPPAUGE_HVR2250: + case SAA7164_BOARD_HAUPPAUGE_HVR2250_2: + case SAA7164_BOARD_HAUPPAUGE_HVR2250_3: + hauppauge_eeprom(dev, &eeprom[0]); + break; + } +} + +/* With most other drivers, the kernel expects to communicate with subdrivers + * through i2c. This bridge does not allow that, it does not expose any direct + * access to I2C. Instead we have to communicate through the device f/w for + * register access to 'processing units'. Each unit has a unique + * id, regardless of how the physical implementation occurs across + * the three physical i2c busses. The being said if we want leverge of + * the existing kernel drivers for tuners and demods we have to 'speak i2c', + * to this bridge implements 3 virtual i2c buses. This is a helper function + * for those. + * + * Description: Translate the kernels notion of an i2c address and bus into + * the appropriate unitid. + */ +int saa7164_i2caddr_to_unitid(struct saa7164_i2c *bus, int addr) +{ + /* For a given bus and i2c device address, return the saa7164 unique + * unitid. < 0 on error */ + + struct saa7164_dev *dev = bus->dev; + struct saa7164_unit *unit; + int i; + + for (i = 0; i < SAA7164_MAX_UNITS; i++) { + unit = &saa7164_boards[dev->board].unit[i]; + + if (unit->type == SAA7164_UNIT_UNDEFINED) + continue; + if ((bus->nr == unit->i2c_bus_nr) && + (addr == unit->i2c_bus_addr)) + return unit->id; + } + + return -1; +} + +/* The 7164 API needs to know the i2c register length in advance. + * this is a helper function. Based on a specific chip addr and bus return the + * reg length. + */ +int saa7164_i2caddr_to_reglen(struct saa7164_i2c *bus, int addr) +{ + /* For a given bus and i2c device address, return the + * saa7164 registry address width. < 0 on error + */ + + struct saa7164_dev *dev = bus->dev; + struct saa7164_unit *unit; + int i; + + for (i = 0; i < SAA7164_MAX_UNITS; i++) { + unit = &saa7164_boards[dev->board].unit[i]; + + if (unit->type == SAA7164_UNIT_UNDEFINED) + continue; + + if ((bus->nr == unit->i2c_bus_nr) && + (addr == unit->i2c_bus_addr)) + return unit->i2c_reg_len; + } + + return -1; +} +/* TODO: implement a 'findeeprom' functio like the above and fix any other + * eeprom related todo's in -api.c. + */ + +/* Translate a unitid into a x readable device name, for display purposes. */ +char *saa7164_unitid_name(struct saa7164_dev *dev, u8 unitid) +{ + char *undefed = "UNDEFINED"; + char *bridge = "BRIDGE"; + struct saa7164_unit *unit; + int i; + + if (unitid == 0) + return bridge; + + for (i = 0; i < SAA7164_MAX_UNITS; i++) { + unit = &saa7164_boards[dev->board].unit[i]; + + if (unit->type == SAA7164_UNIT_UNDEFINED) + continue; + + if (unitid == unit->id) + return unit->name; + } + + return undefed; +} + diff --git a/drivers/media/video/saa7164/saa7164-cmd.c b/drivers/media/video/saa7164/saa7164-cmd.c new file mode 100644 index 000000000000..e097f1a0969a --- /dev/null +++ b/drivers/media/video/saa7164/saa7164-cmd.c @@ -0,0 +1,572 @@ +/* + * Driver for the NXP SAA7164 PCIe bridge + * + * Copyright (c) 2009 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +#include "saa7164.h" + +int saa7164_cmd_alloc_seqno(struct saa7164_dev *dev) +{ + int i, ret = -1; + + mutex_lock(&dev->lock); + for (i = 0; i < SAA_CMD_MAX_MSG_UNITS; i++) { + if (dev->cmds[i].inuse == 0) { + dev->cmds[i].inuse = 1; + dev->cmds[i].signalled = 0; + dev->cmds[i].timeout = 0; + ret = dev->cmds[i].seqno; + break; + } + } + mutex_unlock(&dev->lock); + + return ret; +} + +void saa7164_cmd_free_seqno(struct saa7164_dev *dev, u8 seqno) +{ + mutex_lock(&dev->lock); + if ((dev->cmds[seqno].inuse == 1) && + (dev->cmds[seqno].seqno == seqno)) { + dev->cmds[seqno].inuse = 0; + dev->cmds[seqno].signalled = 0; + dev->cmds[seqno].timeout = 0; + } + mutex_unlock(&dev->lock); +} + +void saa7164_cmd_timeout_seqno(struct saa7164_dev *dev, u8 seqno) +{ + mutex_lock(&dev->lock); + if ((dev->cmds[seqno].inuse == 1) && + (dev->cmds[seqno].seqno == seqno)) { + dev->cmds[seqno].timeout = 1; + } + mutex_unlock(&dev->lock); +} + +u32 saa7164_cmd_timeout_get(struct saa7164_dev *dev, u8 seqno) +{ + int ret = 0; + + mutex_lock(&dev->lock); + if ((dev->cmds[seqno].inuse == 1) && + (dev->cmds[seqno].seqno == seqno)) { + ret = dev->cmds[seqno].timeout; + } + mutex_unlock(&dev->lock); + + return ret; +} + +/* Commands to the f/w get marshelled to/from this code then onto the PCI + * -bus/c running buffer. */ +int saa7164_irq_dequeue(struct saa7164_dev *dev) +{ + int ret = SAA_OK; + u32 timeout; + wait_queue_head_t *q = 0; + dprintk(DBGLVL_CMD, "%s()\n", __func__); + + /* While any outstand message on the bus exists... */ + do { + + /* Peek the msg bus */ + tmComResInfo_t tRsp = { 0, 0, 0, 0, 0, 0 }; + ret = saa7164_bus_get(dev, &tRsp, NULL, 1); + if (ret != SAA_OK) + break; + + q = &dev->cmds[tRsp.seqno].wait; + timeout = saa7164_cmd_timeout_get(dev, tRsp.seqno); + dprintk(DBGLVL_CMD, "%s() timeout = %d\n", __func__, timeout); + if (!timeout) { + dprintk(DBGLVL_CMD, + "%s() signalled seqno(%d) (for dequeue)\n", + __func__, tRsp.seqno); + dev->cmds[tRsp.seqno].signalled = 1; + wake_up(q); + } else { + printk(KERN_ERR + "%s() found timed out command on the bus\n", + __func__); + } + } while (0); + + return ret; +} + +/* Commands to the f/w get marshelled to/from this code then onto the PCI + * -bus/c running buffer. */ +int saa7164_cmd_dequeue(struct saa7164_dev *dev) +{ + int loop = 1; + int ret; + u32 timeout; + wait_queue_head_t *q = 0; + u8 tmp[512]; + dprintk(DBGLVL_CMD, "%s()\n", __func__); + + while (loop) { + + tmComResInfo_t tRsp = { 0, 0, 0, 0, 0, 0 }; + ret = saa7164_bus_get(dev, &tRsp, NULL, 1); + if (ret == SAA_ERR_EMPTY) + return SAA_OK; + + if (ret != SAA_OK) + return ret; + + q = &dev->cmds[tRsp.seqno].wait; + timeout = saa7164_cmd_timeout_get(dev, tRsp.seqno); + dprintk(DBGLVL_CMD, "%s() timeout = %d\n", __func__, timeout); + if (timeout) { + printk(KERN_ERR "found timed out command on the bus\n"); + + /* Clean the bus */ + ret = saa7164_bus_get(dev, &tRsp, &tmp, 0); + printk(KERN_ERR "ret = %x\n", ret); + if (ret == SAA_ERR_EMPTY) + /* Someone else already fetched the response */ + return SAA_OK; + + if (ret != SAA_OK) + return ret; + + if (tRsp.flags & PVC_CMDFLAG_CONTINUE) + printk(KERN_ERR "split response\n"); + else + saa7164_cmd_free_seqno(dev, tRsp.seqno); + + printk(KERN_ERR " timeout continue\n"); + continue; + } + + dprintk(DBGLVL_CMD, "%s() signalled seqno(%d) (for dequeue)\n", + __func__, tRsp.seqno); + dev->cmds[tRsp.seqno].signalled = 1; + wake_up(q); + return SAA_OK; + } + + return SAA_OK; +} + +int saa7164_cmd_set(struct saa7164_dev *dev, tmComResInfo_t* msg, void *buf) +{ + tmComResBusInfo_t *bus = &dev->bus; + u8 cmd_sent; + u16 size, idx; + u32 cmds; + void *tmp; + int ret = -1; + + if (!msg) { + printk(KERN_ERR "%s() !msg\n", __func__); + return SAA_ERR_BAD_PARAMETER; + } + + mutex_lock(&dev->cmds[msg->id].lock); + + size = msg->size; + idx = 0; + cmds = size / bus->m_wMaxReqSize; + if (size % bus->m_wMaxReqSize == 0) + cmds -= 1; + + cmd_sent = 0; + + /* Split the request into smaller chunks */ + for (idx = 0; idx < cmds; idx++) { + + msg->flags |= SAA_CMDFLAG_CONTINUE; + msg->size = bus->m_wMaxReqSize; + tmp = buf + idx * bus->m_wMaxReqSize; + + ret = saa7164_bus_set(dev, msg, tmp); + if (ret != SAA_OK) { + printk(KERN_ERR "%s() set failed %d\n", __func__, ret); + + if (cmd_sent) { + ret = SAA_ERR_BUSY; + goto out; + } + ret = SAA_ERR_OVERFLOW; + goto out; + } + cmd_sent = 1; + } + + /* If not the last command... */ + if (idx != 0) + msg->flags &= ~SAA_CMDFLAG_CONTINUE; + + msg->size = size - idx * bus->m_wMaxReqSize; + + ret = saa7164_bus_set(dev, msg, buf + idx * bus->m_wMaxReqSize); + if (ret != SAA_OK) { + printk(KERN_ERR "%s() set last failed %d\n", __func__, ret); + + if (cmd_sent) { + ret = SAA_ERR_BUSY; + goto out; + } + ret = SAA_ERR_OVERFLOW; + goto out; + } + ret = SAA_OK; + +out: + mutex_unlock(&dev->cmds[msg->id].lock); + return ret; +} + +/* Wait for a signal event, without holding a mutex. Either return TIMEOUT if + * the event never occured, or SAA_OK if it was signaled during the wait. + */ +int saa7164_cmd_wait(struct saa7164_dev *dev, u8 seqno) +{ + wait_queue_head_t *q = 0; + int ret = SAA_BUS_TIMEOUT; + unsigned long stamp; + int r; + + if (debug >= 4) + saa7164_bus_dump(dev); + + dprintk(DBGLVL_CMD, "%s(seqno=%d)\n", __func__, seqno); + + mutex_lock(&dev->lock); + if ((dev->cmds[seqno].inuse == 1) && + (dev->cmds[seqno].seqno == seqno)) { + q = &dev->cmds[seqno].wait; + } + mutex_unlock(&dev->lock); + + if (q) { + /* If we haven't been signalled we need to wait */ + if (dev->cmds[seqno].signalled == 0) { + stamp = jiffies; + dprintk(DBGLVL_CMD, + "%s(seqno=%d) Waiting (signalled=%d)\n", + __func__, seqno, dev->cmds[seqno].signalled); + + /* Wait for signalled to be flagged or timeout */ + /* In a highly stressed system this can easily extend + * into multiple seconds before the deferred worker + * is scheduled, and we're woken up via signal. + * We typically are signalled in < 50ms but it can + * take MUCH longer. + */ + wait_event_timeout(*q, dev->cmds[seqno].signalled, (HZ * waitsecs)); + r = time_before(jiffies, stamp + (HZ * waitsecs)); + if (r) + ret = SAA_OK; + else + saa7164_cmd_timeout_seqno(dev, seqno); + + dprintk(DBGLVL_CMD, "%s(seqno=%d) Waiting res = %d " + "(signalled=%d)\n", __func__, seqno, r, + dev->cmds[seqno].signalled); + } else + ret = SAA_OK; + } else + printk(KERN_ERR "%s(seqno=%d) seqno is invalid\n", + __func__, seqno); + + return ret; +} + +void saa7164_cmd_signal(struct saa7164_dev *dev, u8 seqno) +{ + int i; + dprintk(DBGLVL_CMD, "%s()\n", __func__); + + mutex_lock(&dev->lock); + for (i = 0; i < SAA_CMD_MAX_MSG_UNITS; i++) { + if (dev->cmds[i].inuse == 1) { + dprintk(DBGLVL_CMD, + "seqno %d inuse, sig = %d, t/out = %d\n", + dev->cmds[i].seqno, + dev->cmds[i].signalled, + dev->cmds[i].timeout); + } + } + + for (i = 0; i < SAA_CMD_MAX_MSG_UNITS; i++) { + if ((dev->cmds[i].inuse == 1) && ((i == 0) || + (dev->cmds[i].signalled) || (dev->cmds[i].timeout))) { + dprintk(DBGLVL_CMD, "%s(seqno=%d) calling wake_up\n", + __func__, i); + dev->cmds[i].signalled = 1; + wake_up(&dev->cmds[i].wait); + } + } + mutex_unlock(&dev->lock); +} + +int saa7164_cmd_send(struct saa7164_dev *dev, u8 id, tmComResCmd_t command, + u16 controlselector, u16 size, void *buf) +{ + tmComResInfo_t command_t, *pcommand_t; + tmComResInfo_t response_t, *presponse_t; + u8 errdata[256]; + u16 resp_dsize; + u16 data_recd; + u32 loop; + int ret; + int safety = 0; + + dprintk(DBGLVL_CMD, "%s(unitid = %s (%d) , command = 0x%x, " + "sel = 0x%x)\n", __func__, saa7164_unitid_name(dev, id), id, + command, controlselector); + + if ((size == 0) || (buf == 0)) { + printk(KERN_ERR "%s() Invalid param\n", __func__); + return SAA_ERR_BAD_PARAMETER; + } + + /* Prepare some basic command/response structures */ + memset(&command_t, 0, sizeof(command_t)); + memset(&response_t, 0, sizeof(&response_t)); + pcommand_t = &command_t; + presponse_t = &response_t; + command_t.id = id; + command_t.command = command; + command_t.controlselector = controlselector; + command_t.size = size; + + /* Allocate a unique sequence number */ + ret = saa7164_cmd_alloc_seqno(dev); + if (ret < 0) { + printk(KERN_ERR "%s() No free sequences\n", __func__); + ret = SAA_ERR_NO_RESOURCES; + goto out; + } + + command_t.seqno = (u8)ret; + + /* Send Command */ + resp_dsize = size; + pcommand_t->size = size; + + dprintk(DBGLVL_CMD, "%s() pcommand_t.seqno = %d\n", + __func__, pcommand_t->seqno); + + dprintk(DBGLVL_CMD, "%s() pcommand_t.size = %d\n", + __func__, pcommand_t->size); + + ret = saa7164_cmd_set(dev, pcommand_t, buf); + if (ret != SAA_OK) { + printk(KERN_ERR "%s() set command failed %d\n", __func__, ret); + + if (ret != SAA_ERR_BUSY) + saa7164_cmd_free_seqno(dev, pcommand_t->seqno); + else + /* Flag a timeout, because at least one + * command was sent */ + saa7164_cmd_timeout_seqno(dev, pcommand_t->seqno); + + goto out; + } + + /* With split responses we have to collect the msgs piece by piece */ + data_recd = 0; + loop = 1; + while (loop) { + dprintk(DBGLVL_CMD, "%s() loop\n", __func__); + + ret = saa7164_cmd_wait(dev, pcommand_t->seqno); + dprintk(DBGLVL_CMD, "%s() loop ret = %d\n", __func__, ret); + + /* if power is down and this is not a power command ... */ + + if (ret == SAA_BUS_TIMEOUT) { + printk(KERN_ERR "Event timed out\n"); + saa7164_cmd_timeout_seqno(dev, pcommand_t->seqno); + return ret; + } + + if (ret != SAA_OK) { + printk(KERN_ERR "spurious error\n"); + return ret; + } + + /* Peek response */ + ret = saa7164_bus_get(dev, presponse_t, NULL, 1); + if (ret == SAA_ERR_EMPTY) { + dprintk(4, "%s() SAA_ERR_EMPTY\n", __func__); + continue; + } + if (ret != SAA_OK) { + printk(KERN_ERR "peek failed\n"); + return ret; + } + + dprintk(DBGLVL_CMD, "%s() presponse_t->seqno = %d\n", + __func__, presponse_t->seqno); + + dprintk(DBGLVL_CMD, "%s() presponse_t->flags = 0x%x\n", + __func__, presponse_t->flags); + + dprintk(DBGLVL_CMD, "%s() presponse_t->size = %d\n", + __func__, presponse_t->size); + + /* Check if the response was for our command */ + if (presponse_t->seqno != pcommand_t->seqno) { + + dprintk(DBGLVL_CMD, + "wrong event: seqno = %d, " + "expected seqno = %d, " + "will dequeue regardless\n", + presponse_t->seqno, pcommand_t->seqno); + + ret = saa7164_cmd_dequeue(dev); + if (ret != SAA_OK) { + printk(KERN_ERR "dequeue failed, ret = %d\n", + ret); + if (safety++ > 16) { + printk(KERN_ERR + "dequeue exceeded, safety exit\n"); + return SAA_ERR_BUSY; + } + } + + continue; + } + + if ((presponse_t->flags & PVC_RESPONSEFLAG_ERROR) != 0) { + + memset(&errdata[0], 0, sizeof(errdata)); + + ret = saa7164_bus_get(dev, presponse_t, &errdata[0], 0); + if (ret != SAA_OK) { + printk(KERN_ERR "get error(2)\n"); + return ret; + } + + saa7164_cmd_free_seqno(dev, pcommand_t->seqno); + + dprintk(DBGLVL_CMD, "%s() errdata %02x%02x%02x%02x\n", + __func__, errdata[0], errdata[1], errdata[2], + errdata[3]); + + /* Map error codes */ + dprintk(DBGLVL_CMD, "%s() cmd, error code = 0x%x\n", + __func__, errdata[0]); + + switch (errdata[0]) { + case PVC_ERRORCODE_INVALID_COMMAND: + dprintk(DBGLVL_CMD, "%s() INVALID_COMMAND\n", + __func__); + ret = SAA_ERR_INVALID_COMMAND; + break; + case PVC_ERRORCODE_INVALID_DATA: + dprintk(DBGLVL_CMD, "%s() INVALID_DATA\n", + __func__); + ret = SAA_ERR_BAD_PARAMETER; + break; + case PVC_ERRORCODE_TIMEOUT: + dprintk(DBGLVL_CMD, "%s() TIMEOUT\n", __func__); + ret = SAA_ERR_TIMEOUT; + break; + case PVC_ERRORCODE_NAK: + dprintk(DBGLVL_CMD, "%s() NAK\n", __func__); + ret = SAA_ERR_NULL_PACKET; + break; + case PVC_ERRORCODE_UNKNOWN: + case PVC_ERRORCODE_INVALID_CONTROL: + dprintk(DBGLVL_CMD, + "%s() UNKNOWN OR INVALID CONTROL\n", + __func__); + default: + dprintk(DBGLVL_CMD, "%s() UNKNOWN\n", __func__); + ret = SAA_ERR_NOT_SUPPORTED; + } + + /* See of other commands are on the bus */ + if (saa7164_cmd_dequeue(dev) != SAA_OK) + printk(KERN_ERR "dequeue(2) failed\n"); + + return ret; + } + + /* If response is invalid */ + if ((presponse_t->id != pcommand_t->id) || + (presponse_t->command != pcommand_t->command) || + (presponse_t->controlselector != + pcommand_t->controlselector) || + (((resp_dsize - data_recd) != presponse_t->size) && + !(presponse_t->flags & PVC_CMDFLAG_CONTINUE)) || + ((resp_dsize - data_recd) < presponse_t->size)) { + + /* Invalid */ + dprintk(DBGLVL_CMD, "%s() Invalid\n", __func__); + ret = saa7164_bus_get(dev, presponse_t, 0, 0); + if (ret != SAA_OK) { + printk(KERN_ERR "get failed\n"); + return ret; + } + + /* See of other commands are on the bus */ + if (saa7164_cmd_dequeue(dev) != SAA_OK) + printk(KERN_ERR "dequeue(3) failed\n"); + continue; + } + + /* OK, now we're actually getting out correct response */ + ret = saa7164_bus_get(dev, presponse_t, buf + data_recd, 0); + if (ret != SAA_OK) { + printk(KERN_ERR "get failed\n"); + return ret; + } + + data_recd = presponse_t->size + data_recd; + if (resp_dsize == data_recd) { + dprintk(DBGLVL_CMD, "%s() Resp recd\n", __func__); + break; + } + + /* See of other commands are on the bus */ + if (saa7164_cmd_dequeue(dev) != SAA_OK) + printk(KERN_ERR "dequeue(3) failed\n"); + + continue; + + } /* (loop) */ + + /* Release the sequence number allocation */ + saa7164_cmd_free_seqno(dev, pcommand_t->seqno); + + /* if powerdown signal all pending commands */ + + dprintk(DBGLVL_CMD, "%s() Calling dequeue then exit\n", __func__); + + /* See of other commands are on the bus */ + if (saa7164_cmd_dequeue(dev) != SAA_OK) + printk(KERN_ERR "dequeue(4) failed\n"); + + ret = SAA_OK; +out: + return ret; +} + diff --git a/drivers/media/video/saa7164/saa7164-core.c b/drivers/media/video/saa7164/saa7164-core.c new file mode 100644 index 000000000000..f0dbead188c8 --- /dev/null +++ b/drivers/media/video/saa7164/saa7164-core.c @@ -0,0 +1,740 @@ +/* + * Driver for the NXP SAA7164 PCIe bridge + * + * Copyright (c) 2009 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "saa7164.h" + +MODULE_DESCRIPTION("Driver for NXP SAA7164 based TV cards"); +MODULE_AUTHOR("Steven Toth "); +MODULE_LICENSE("GPL"); + +/* + 1 Basic + 2 + 4 i2c + 8 api + 16 cmd + 32 bus + */ + +unsigned int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "enable debug messages"); + +unsigned int waitsecs = 10; +module_param(waitsecs, int, 0644); +MODULE_PARM_DESC(debug, "timeout on firmware messages"); + +static unsigned int card[] = {[0 ... (SAA7164_MAXBOARDS - 1)] = UNSET }; +module_param_array(card, int, NULL, 0444); +MODULE_PARM_DESC(card, "card type"); + +static unsigned int saa7164_devcount; + +static DEFINE_MUTEX(devlist); +LIST_HEAD(saa7164_devlist); + +#define INT_SIZE 16 + +static void saa7164_work_cmdhandler(struct work_struct *w) +{ + struct saa7164_dev *dev = container_of(w, struct saa7164_dev, workcmd); + + /* Wake up any complete commands */ + saa7164_irq_dequeue(dev); +} + +static void saa7164_buffer_deliver(struct saa7164_buffer *buf) +{ + struct saa7164_tsport *port = buf->port; + + /* Feed the transport payload into the kernel demux */ + dvb_dmx_swfilter_packets(&port->dvb.demux, (u8 *)buf->cpu, + SAA7164_TS_NUMBER_OF_LINES); + +} + +static irqreturn_t saa7164_irq_ts(struct saa7164_tsport *port) +{ + struct saa7164_dev *dev = port->dev; + struct saa7164_buffer *buf; + struct list_head *c, *n; + int wp, i = 0, rp; + + /* Find the current write point from the hardware */ + wp = saa7164_readl(port->bufcounter); + if (wp > (port->hwcfg.buffercount - 1)) + BUG(); + + /* Find the previous buffer to the current write point */ + if (wp == 0) + rp = 7; + else + rp = wp - 1; + + /* Lookup the WP in the buffer list */ + /* TODO: turn this into a worker thread */ + list_for_each_safe(c, n, &port->dmaqueue.list) { + buf = list_entry(c, struct saa7164_buffer, list); + if (i++ > port->hwcfg.buffercount) + BUG(); + + if (buf->nr == rp) { + /* Found the buffer, deal with it */ + dprintk(DBGLVL_IRQ, "%s() wp: %d processing: %d\n", + __func__, wp, rp); + saa7164_buffer_deliver(buf); + break; + } + + } + return 0; +} + +/* Primary IRQ handler and dispatch mechanism */ +static irqreturn_t saa7164_irq(int irq, void *dev_id) +{ + struct saa7164_dev *dev = dev_id; + u32 intid, intstat[INT_SIZE/4]; + int i, handled = 0, bit; + + if (dev == 0) { + printk(KERN_ERR "%s() No device specified\n", __func__); + handled = 0; + goto out; + } + + /* Check that the hardware is accessable. If the status bytes are + * 0xFF then the device is not accessable, the the IRQ belongs + * to another driver. + * 4 x u32 interrupt registers. + */ + for (i = 0; i < INT_SIZE/4; i++) { + + /* TODO: Convert into saa7164_readl() */ + /* Read the 4 hardware interrupt registers */ + intstat[i] = saa7164_readl(dev->int_status + (i * 4)); + + if (intstat[i]) + handled = 1; + } + if (handled == 0) + goto out; + + /* For each of the HW interrupt registers */ + for (i = 0; i < INT_SIZE/4; i++) { + + if (intstat[i]) { + /* Each function of the board has it's own interruptid. + * Find the function that triggered then call + * it's handler. + */ + for (bit = 0; bit < 32; bit++) { + + if (((intstat[i] >> bit) & 0x00000001) == 0) + continue; + + /* Calculate the interrupt id (0x00 to 0x7f) */ + + intid = (i * 32) + bit; + if (intid == dev->intfdesc.bInterruptId) { + /* A response to an cmd/api call */ + schedule_work(&dev->workcmd); + } else if (intid == + dev->ts1.hwcfg.interruptid) { + + /* Transport path 1 */ + saa7164_irq_ts(&dev->ts1); + + } else if (intid == + dev->ts2.hwcfg.interruptid) { + + /* Transport path 2 */ + saa7164_irq_ts(&dev->ts2); + + } else { + /* Find the function */ + dprintk(DBGLVL_IRQ, + "%s() unhandled interrupt " + "reg 0x%x bit 0x%x " + "intid = 0x%x\n", + __func__, i, bit, intid); + } + } + + /* Ack it */ + saa7164_writel(dev->int_ack + (i * 4), intstat[i]); + + } + } +out: + return IRQ_RETVAL(handled); +} + +void saa7164_getfirmwarestatus(struct saa7164_dev *dev) +{ + struct saa7164_fw_status *s = &dev->fw_status; + + dev->fw_status.status = saa7164_readl(SAA_DEVICE_SYSINIT_STATUS); + dev->fw_status.mode = saa7164_readl(SAA_DEVICE_SYSINIT_MODE); + dev->fw_status.spec = saa7164_readl(SAA_DEVICE_SYSINIT_SPEC); + dev->fw_status.inst = saa7164_readl(SAA_DEVICE_SYSINIT_INST); + dev->fw_status.cpuload = saa7164_readl(SAA_DEVICE_SYSINIT_CPULOAD); + dev->fw_status.remainheap = + saa7164_readl(SAA_DEVICE_SYSINIT_REMAINHEAP); + + dprintk(1, "Firmware status:\n"); + dprintk(1, " .status = 0x%08x\n", s->status); + dprintk(1, " .mode = 0x%08x\n", s->mode); + dprintk(1, " .spec = 0x%08x\n", s->spec); + dprintk(1, " .inst = 0x%08x\n", s->inst); + dprintk(1, " .cpuload = 0x%08x\n", s->cpuload); + dprintk(1, " .remainheap = 0x%08x\n", s->remainheap); +} + +u32 saa7164_getcurrentfirmwareversion(struct saa7164_dev *dev) +{ + u32 reg; + + reg = saa7164_readl(SAA_DEVICE_VERSION); + dprintk(1, "Device running firmware version %d.%d.%d.%d (0x%x)\n", + (reg & 0x0000fc00) >> 10, + (reg & 0x000003e0) >> 5, + (reg & 0x0000001f), + (reg & 0xffff0000) >> 16, + reg); + + return reg; +} + +/* TODO: Debugging func, remove */ +void saa7164_dumphex16(struct saa7164_dev *dev, u8 *buf, int len) +{ + int i; + + printk(KERN_INFO "--------------------> " + "00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f\n"); + + for (i = 0; i < len; i += 16) + printk(KERN_INFO " [0x%08x] " + "%02x %02x %02x %02x %02x %02x %02x %02x " + "%02x %02x %02x %02x %02x %02x %02x %02x\n", i, + *(buf+i+0), *(buf+i+1), *(buf+i+2), *(buf+i+3), + *(buf+i+4), *(buf+i+5), *(buf+i+6), *(buf+i+7), + *(buf+i+8), *(buf+i+9), *(buf+i+10), *(buf+i+11), + *(buf+i+12), *(buf+i+13), *(buf+i+14), *(buf+i+15)); +} + +/* TODO: Debugging func, remove */ +void saa7164_dumpregs(struct saa7164_dev *dev, u32 addr) +{ + int i; + + dprintk(1, "--------------------> " + "00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f\n"); + + for (i = 0; i < 0x100; i += 16) + dprintk(1, "region0[0x%08x] = " + "%02x %02x %02x %02x %02x %02x %02x %02x" + " %02x %02x %02x %02x %02x %02x %02x %02x\n", i, + (u8)saa7164_readb(addr + i + 0), + (u8)saa7164_readb(addr + i + 1), + (u8)saa7164_readb(addr + i + 2), + (u8)saa7164_readb(addr + i + 3), + (u8)saa7164_readb(addr + i + 4), + (u8)saa7164_readb(addr + i + 5), + (u8)saa7164_readb(addr + i + 6), + (u8)saa7164_readb(addr + i + 7), + (u8)saa7164_readb(addr + i + 8), + (u8)saa7164_readb(addr + i + 9), + (u8)saa7164_readb(addr + i + 10), + (u8)saa7164_readb(addr + i + 11), + (u8)saa7164_readb(addr + i + 12), + (u8)saa7164_readb(addr + i + 13), + (u8)saa7164_readb(addr + i + 14), + (u8)saa7164_readb(addr + i + 15) + ); +} + +static void saa7164_dump_hwdesc(struct saa7164_dev *dev) +{ + dprintk(1, "@0x%p hwdesc sizeof(tmComResHWDescr_t) = %d bytes\n", + &dev->hwdesc, (u32)sizeof(tmComResHWDescr_t)); + + dprintk(1, " .bLength = 0x%x\n", dev->hwdesc.bLength); + dprintk(1, " .bDescriptorType = 0x%x\n", dev->hwdesc.bDescriptorType); + dprintk(1, " .bDescriptorSubtype = 0x%x\n", + dev->hwdesc.bDescriptorSubtype); + + dprintk(1, " .bcdSpecVersion = 0x%x\n", dev->hwdesc.bcdSpecVersion); + dprintk(1, " .dwClockFrequency = 0x%x\n", dev->hwdesc.dwClockFrequency); + dprintk(1, " .dwClockUpdateRes = 0x%x\n", dev->hwdesc.dwClockUpdateRes); + dprintk(1, " .bCapabilities = 0x%x\n", dev->hwdesc.bCapabilities); + dprintk(1, " .dwDeviceRegistersLocation = 0x%x\n", + dev->hwdesc.dwDeviceRegistersLocation); + + dprintk(1, " .dwHostMemoryRegion = 0x%x\n", + dev->hwdesc.dwHostMemoryRegion); + + dprintk(1, " .dwHostMemoryRegionSize = 0x%x\n", + dev->hwdesc.dwHostMemoryRegionSize); + + dprintk(1, " .dwHostHibernatMemRegion = 0x%x\n", + dev->hwdesc.dwHostHibernatMemRegion); + + dprintk(1, " .dwHostHibernatMemRegionSize = 0x%x\n", + dev->hwdesc.dwHostHibernatMemRegionSize); +} + +static void saa7164_dump_intfdesc(struct saa7164_dev *dev) +{ + dprintk(1, "@0x%p intfdesc " + "sizeof(tmComResInterfaceDescr_t) = %d bytes\n", + &dev->intfdesc, (u32)sizeof(tmComResInterfaceDescr_t)); + + dprintk(1, " .bLength = 0x%x\n", dev->intfdesc.bLength); + dprintk(1, " .bDescriptorType = 0x%x\n", dev->intfdesc.bDescriptorType); + dprintk(1, " .bDescriptorSubtype = 0x%x\n", + dev->intfdesc.bDescriptorSubtype); + + dprintk(1, " .bFlags = 0x%x\n", dev->intfdesc.bFlags); + dprintk(1, " .bInterfaceType = 0x%x\n", dev->intfdesc.bInterfaceType); + dprintk(1, " .bInterfaceId = 0x%x\n", dev->intfdesc.bInterfaceId); + dprintk(1, " .bBaseInterface = 0x%x\n", dev->intfdesc.bBaseInterface); + dprintk(1, " .bInterruptId = 0x%x\n", dev->intfdesc.bInterruptId); + dprintk(1, " .bDebugInterruptId = 0x%x\n", + dev->intfdesc.bDebugInterruptId); + + dprintk(1, " .BARLocation = 0x%x\n", dev->intfdesc.BARLocation); +} + +static void saa7164_dump_busdesc(struct saa7164_dev *dev) +{ + dprintk(1, "@0x%p busdesc sizeof(tmComResBusDescr_t) = %d bytes\n", + &dev->busdesc, (u32)sizeof(tmComResBusDescr_t)); + + dprintk(1, " .CommandRing = 0x%016Lx\n", dev->busdesc.CommandRing); + dprintk(1, " .ResponseRing = 0x%016Lx\n", dev->busdesc.ResponseRing); + dprintk(1, " .CommandWrite = 0x%x\n", dev->busdesc.CommandWrite); + dprintk(1, " .CommandRead = 0x%x\n", dev->busdesc.CommandRead); + dprintk(1, " .ResponseWrite = 0x%x\n", dev->busdesc.ResponseWrite); + dprintk(1, " .ResponseRead = 0x%x\n", dev->busdesc.ResponseRead); +} + +/* Much of the hardware configuration and PCI registers are configured + * dynamically depending on firmware. We have to cache some initial + * structures then use these to locate other important structures + * from PCI space. + */ +static void saa7164_get_descriptors(struct saa7164_dev *dev) +{ + memcpy(&dev->hwdesc, dev->bmmio, sizeof(tmComResHWDescr_t)); + memcpy(&dev->intfdesc, dev->bmmio + sizeof(tmComResHWDescr_t), + sizeof(tmComResInterfaceDescr_t)); + memcpy(&dev->busdesc, dev->bmmio + dev->intfdesc.BARLocation, + sizeof(tmComResBusDescr_t)); + + if (dev->hwdesc.bLength != sizeof(tmComResHWDescr_t)) { + printk(KERN_ERR "Structure tmComResHWDescr_t is mangled\n"); + printk(KERN_ERR "Need %x got %d\n", dev->hwdesc.bLength, + (u32)sizeof(tmComResHWDescr_t)); + } else + saa7164_dump_hwdesc(dev); + + if (dev->intfdesc.bLength != sizeof(tmComResInterfaceDescr_t)) { + printk(KERN_ERR "struct tmComResInterfaceDescr_t is mangled\n"); + printk(KERN_ERR "Need %x got %d\n", dev->intfdesc.bLength, + (u32)sizeof(tmComResInterfaceDescr_t)); + } else + saa7164_dump_intfdesc(dev); + + saa7164_dump_busdesc(dev); +} + +static int saa7164_pci_quirks(struct saa7164_dev *dev) +{ + return 0; +} + +static int get_resources(struct saa7164_dev *dev) +{ + if (request_mem_region(pci_resource_start(dev->pci, 0), + pci_resource_len(dev->pci, 0), dev->name)) { + + if (request_mem_region(pci_resource_start(dev->pci, 2), + pci_resource_len(dev->pci, 2), dev->name)) + return 0; + } + + printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx or 0x%llx\n", + dev->name, + (u64)pci_resource_start(dev->pci, 0), + (u64)pci_resource_start(dev->pci, 2)); + + return -EBUSY; +} + +static int saa7164_dev_setup(struct saa7164_dev *dev) +{ + int i; + + mutex_init(&dev->lock); + atomic_inc(&dev->refcount); + dev->nr = saa7164_devcount++; + + sprintf(dev->name, "saa7164[%d]", dev->nr); + + mutex_lock(&devlist); + list_add_tail(&dev->devlist, &saa7164_devlist); + mutex_unlock(&devlist); + + /* board config */ + dev->board = UNSET; + if (card[dev->nr] < saa7164_bcount) + dev->board = card[dev->nr]; + + for (i = 0; UNSET == dev->board && i < saa7164_idcount; i++) + if (dev->pci->subsystem_vendor == saa7164_subids[i].subvendor && + dev->pci->subsystem_device == + saa7164_subids[i].subdevice) + dev->board = saa7164_subids[i].card; + + if (UNSET == dev->board) { + dev->board = SAA7164_BOARD_UNKNOWN; + saa7164_card_list(dev); + } + + dev->pci_bus = dev->pci->bus->number; + dev->pci_slot = PCI_SLOT(dev->pci->devfn); + + /* I2C Defaults / setup */ + dev->i2c_bus[0].dev = dev; + dev->i2c_bus[0].nr = 0; + dev->i2c_bus[1].dev = dev; + dev->i2c_bus[1].nr = 1; + dev->i2c_bus[2].dev = dev; + dev->i2c_bus[2].nr = 2; + + /* Transport port A Defaults / setup */ + dev->ts1.dev = dev; + dev->ts1.nr = 0; + mutex_init(&dev->ts1.dvb.lock); + INIT_LIST_HEAD(&dev->ts1.dmaqueue.list); + INIT_LIST_HEAD(&dev->ts1.dummy_dmaqueue.list); + mutex_init(&dev->ts1.dmaqueue_lock); + mutex_init(&dev->ts1.dummy_dmaqueue_lock); + + /* Transport port B Defaults / setup */ + dev->ts2.dev = dev; + dev->ts2.nr = 1; + mutex_init(&dev->ts2.dvb.lock); + INIT_LIST_HEAD(&dev->ts2.dmaqueue.list); + INIT_LIST_HEAD(&dev->ts2.dummy_dmaqueue.list); + mutex_init(&dev->ts2.dmaqueue_lock); + mutex_init(&dev->ts2.dummy_dmaqueue_lock); + + if (get_resources(dev) < 0) { + printk(KERN_ERR "CORE %s No more PCIe resources for " + "subsystem: %04x:%04x\n", + dev->name, dev->pci->subsystem_vendor, + dev->pci->subsystem_device); + + saa7164_devcount--; + return -ENODEV; + } + + /* PCI/e allocations */ + dev->lmmio = ioremap(pci_resource_start(dev->pci, 0), + pci_resource_len(dev->pci, 0)); + + dev->lmmio2 = ioremap(pci_resource_start(dev->pci, 2), + pci_resource_len(dev->pci, 2)); + + dev->bmmio = (u8 __iomem *)dev->lmmio; + dev->bmmio2 = (u8 __iomem *)dev->lmmio2; + + /* Inerrupt and ack register locations offset of bmmio */ + dev->int_status = 0x183000 + 0xf80; + dev->int_ack = 0x183000 + 0xf90; + + printk(KERN_INFO + "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n", + dev->name, dev->pci->subsystem_vendor, + dev->pci->subsystem_device, saa7164_boards[dev->board].name, + dev->board, card[dev->nr] == dev->board ? + "insmod option" : "autodetected"); + + saa7164_pci_quirks(dev); + + return 0; +} + +static void saa7164_dev_unregister(struct saa7164_dev *dev) +{ + dprintk(1, "%s()\n", __func__); + + release_mem_region(pci_resource_start(dev->pci, 0), + pci_resource_len(dev->pci, 0)); + + release_mem_region(pci_resource_start(dev->pci, 2), + pci_resource_len(dev->pci, 2)); + + if (!atomic_dec_and_test(&dev->refcount)) + return; + + iounmap(dev->lmmio); + iounmap(dev->lmmio2); + + return; +} + +static int __devinit saa7164_initdev(struct pci_dev *pci_dev, + const struct pci_device_id *pci_id) +{ + struct saa7164_dev *dev; + int err, i; + u32 version; + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (NULL == dev) + return -ENOMEM; + + /* pci init */ + dev->pci = pci_dev; + if (pci_enable_device(pci_dev)) { + err = -EIO; + goto fail_free; + } + + if (saa7164_dev_setup(dev) < 0) { + err = -EINVAL; + goto fail_free; + } + + /* print pci info */ + pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev); + pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); + printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, " + "latency: %d, mmio: 0x%llx\n", dev->name, + pci_name(pci_dev), dev->pci_rev, pci_dev->irq, + dev->pci_lat, + (unsigned long long)pci_resource_start(pci_dev, 0)); + + pci_set_master(pci_dev); + /* TODO */ + if (!pci_dma_supported(pci_dev, 0xffffffff)) { + printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name); + err = -EIO; + goto fail_irq; + } + + err = request_irq(pci_dev->irq, saa7164_irq, + IRQF_SHARED | IRQF_DISABLED, dev->name, dev); + if (err < 0) { + printk(KERN_ERR "%s: can't get IRQ %d\n", dev->name, + pci_dev->irq); + err = -EIO; + goto fail_irq; + } + + pci_set_drvdata(pci_dev, dev); + + /* Init the internal command list */ + for (i = 0; i < SAA_CMD_MAX_MSG_UNITS; i++) { + dev->cmds[i].seqno = i; + dev->cmds[i].inuse = 0; + mutex_init(&dev->cmds[i].lock); + init_waitqueue_head(&dev->cmds[i].wait); + } + + /* We need a deferred interrupt handler for cmd handling */ + INIT_WORK(&dev->workcmd, saa7164_work_cmdhandler); + + /* Only load the firmware if we know the board */ + if (dev->board != SAA7164_BOARD_UNKNOWN) { + + err = saa7164_downloadfirmware(dev); + if (err < 0) { + printk(KERN_ERR + "Failed to boot firmware, no features " + "registered\n"); + goto fail_fw; + } + + saa7164_get_descriptors(dev); + saa7164_dumpregs(dev, 0); + saa7164_getcurrentfirmwareversion(dev); + saa7164_getfirmwarestatus(dev); + err = saa7164_bus_setup(dev); + if (err < 0) + printk(KERN_ERR + "Failed to setup the bus, will continue\n"); + saa7164_bus_dump(dev); + + /* Ping the running firmware via the command bus and get the + * firmware version, this checks the bus is running OK. + */ + version = 0; + if (saa7164_api_get_fw_version(dev, &version) == SAA_OK) + dprintk(1, "Bus is operating correctly using " + "version %d.%d.%d.%d (0x%x)\n", + (version & 0x0000fc00) >> 10, + (version & 0x000003e0) >> 5, + (version & 0x0000001f), + (version & 0xffff0000) >> 16, + version); + else + printk(KERN_ERR + "Failed to communicate with the firmware\n"); + + /* Bring up the I2C buses */ + saa7164_i2c_register(&dev->i2c_bus[0]); + saa7164_i2c_register(&dev->i2c_bus[1]); + saa7164_i2c_register(&dev->i2c_bus[2]); + saa7164_gpio_setup(dev); + saa7164_card_setup(dev); + + + /* Parse the dynamic device configuration, find various + * media endpoints (MPEG, WMV, PS, TS) and cache their + * configuration details into the driver, so we can + * reference them later during simething_register() func, + * interrupt handlers, deferred work handlers etc. + */ + saa7164_api_enum_subdevs(dev); + + /* Begin to create the video sub-systems and register funcs */ + if (saa7164_boards[dev->board].porta == SAA7164_MPEG_DVB) { + if (saa7164_dvb_register(&dev->ts1) < 0) { + printk(KERN_ERR "%s() Failed to register " + "dvb adapters on porta\n", + __func__); + } + } + + if (saa7164_boards[dev->board].portb == SAA7164_MPEG_DVB) { + if (saa7164_dvb_register(&dev->ts2) < 0) { + printk(KERN_ERR"%s() Failed to register " + "dvb adapters on portb\n", + __func__); + } + } + + } /* != BOARD_UNKNOWN */ + else + printk(KERN_ERR "%s() Unsupported board detected, " + "registering without firmware\n", __func__); + + dprintk(1, "%s() parameter debug = %d\n", __func__, debug); + dprintk(1, "%s() parameter waitsecs = %d\n", __func__, waitsecs); + +fail_fw: + return 0; + +fail_irq: + saa7164_dev_unregister(dev); +fail_free: + kfree(dev); + return err; +} + +static void saa7164_shutdown(struct saa7164_dev *dev) +{ + dprintk(1, "%s()\n", __func__); +} + +static void __devexit saa7164_finidev(struct pci_dev *pci_dev) +{ + struct saa7164_dev *dev = pci_get_drvdata(pci_dev); + + saa7164_shutdown(dev); + + if (saa7164_boards[dev->board].porta == SAA7164_MPEG_DVB) + saa7164_dvb_unregister(&dev->ts1); + + if (saa7164_boards[dev->board].portb == SAA7164_MPEG_DVB) + saa7164_dvb_unregister(&dev->ts2); + + saa7164_i2c_unregister(&dev->i2c_bus[0]); + saa7164_i2c_unregister(&dev->i2c_bus[1]); + saa7164_i2c_unregister(&dev->i2c_bus[2]); + + pci_disable_device(pci_dev); + + /* unregister stuff */ + free_irq(pci_dev->irq, dev); + pci_set_drvdata(pci_dev, NULL); + + mutex_lock(&devlist); + list_del(&dev->devlist); + mutex_unlock(&devlist); + + saa7164_dev_unregister(dev); + kfree(dev); +} + +static struct pci_device_id saa7164_pci_tbl[] = { + { + /* SAA7164 */ + .vendor = 0x1131, + .device = 0x7164, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, { + /* --- end of list --- */ + } +}; +MODULE_DEVICE_TABLE(pci, saa7164_pci_tbl); + +static struct pci_driver saa7164_pci_driver = { + .name = "saa7164", + .id_table = saa7164_pci_tbl, + .probe = saa7164_initdev, + .remove = __devexit_p(saa7164_finidev), + /* TODO */ + .suspend = NULL, + .resume = NULL, +}; + +static int saa7164_init(void) +{ + printk(KERN_INFO "saa7164 driver loaded\n"); + return pci_register_driver(&saa7164_pci_driver); +} + +static void saa7164_fini(void) +{ + pci_unregister_driver(&saa7164_pci_driver); +} + +module_init(saa7164_init); +module_exit(saa7164_fini); + diff --git a/drivers/media/video/saa7164/saa7164-dvb.c b/drivers/media/video/saa7164/saa7164-dvb.c new file mode 100644 index 000000000000..6a2d847d6a88 --- /dev/null +++ b/drivers/media/video/saa7164/saa7164-dvb.c @@ -0,0 +1,602 @@ +/* + * Driver for the NXP SAA7164 PCIe bridge + * + * Copyright (c) 2009 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "saa7164.h" + +#include "tda10048.h" +#include "tda18271.h" +#include "s5h1411.h" + +#define DRIVER_NAME "saa7164" + +DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); + +/* addr is in the card struct, get it from there */ +static struct tda10048_config hauppauge_hvr2200_1_config = { + .demod_address = 0x10 >> 1, + .output_mode = TDA10048_SERIAL_OUTPUT, + .fwbulkwritelen = TDA10048_BULKWRITE_200, + .inversion = TDA10048_INVERSION_ON, + .dtv6_if_freq_khz = TDA10048_IF_3300, + .dtv7_if_freq_khz = TDA10048_IF_3500, + .dtv8_if_freq_khz = TDA10048_IF_4000, + .clk_freq_khz = TDA10048_CLK_16000, +}; +static struct tda10048_config hauppauge_hvr2200_2_config = { + .demod_address = 0x12 >> 1, + .output_mode = TDA10048_SERIAL_OUTPUT, + .fwbulkwritelen = TDA10048_BULKWRITE_200, + .inversion = TDA10048_INVERSION_ON, + .dtv6_if_freq_khz = TDA10048_IF_3300, + .dtv7_if_freq_khz = TDA10048_IF_3500, + .dtv8_if_freq_khz = TDA10048_IF_4000, + .clk_freq_khz = TDA10048_CLK_16000, +}; + +static struct tda18271_std_map hauppauge_tda18271_std_map = { + .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 3, + .if_lvl = 6, .rfagc_top = 0x37 }, + .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0, + .if_lvl = 6, .rfagc_top = 0x37 }, +}; + +static struct tda18271_config hauppauge_hvr22x0_tuner_config = { + .std_map = &hauppauge_tda18271_std_map, + .gate = TDA18271_GATE_ANALOG, + .role = TDA18271_MASTER, +}; + +static struct tda18271_config hauppauge_hvr22x0s_tuner_config = { + .std_map = &hauppauge_tda18271_std_map, + .gate = TDA18271_GATE_ANALOG, + .role = TDA18271_SLAVE, + .rf_cal_on_startup = 1 +}; + +static struct s5h1411_config hauppauge_s5h1411_config = { + .output_mode = S5H1411_SERIAL_OUTPUT, + .gpio = S5H1411_GPIO_ON, + .qam_if = S5H1411_IF_4000, + .vsb_if = S5H1411_IF_3250, + .inversion = S5H1411_INVERSION_ON, + .status_mode = S5H1411_DEMODLOCKING, + .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, +}; + +static int saa7164_dvb_stop_tsport(struct saa7164_tsport *port) +{ + struct saa7164_dev *dev = port->dev; + int ret; + + ret = saa7164_api_transition_port(port, SAA_DMASTATE_STOP); + if ((ret != SAA_OK) && (ret != SAA_ERR_ALREADY_STOPPED)) { + printk(KERN_ERR "%s() stop transition failed, ret = 0x%x\n", + __func__, ret); + ret = -EIO; + } else { + dprintk(DBGLVL_DVB, "%s() Stopped\n", __func__); + ret = 0; + } + + return ret; +} + +static int saa7164_dvb_acquire_tsport(struct saa7164_tsport *port) +{ + struct saa7164_dev *dev = port->dev; + int ret; + + ret = saa7164_api_transition_port(port, SAA_DMASTATE_ACQUIRE); + if ((ret != SAA_OK) && (ret != SAA_ERR_ALREADY_STOPPED)) { + printk(KERN_ERR "%s() acquire transition failed, ret = 0x%x\n", + __func__, ret); + ret = -EIO; + } else { + dprintk(DBGLVL_DVB, "%s() Acquired\n", __func__); + ret = 0; + } + + return ret; +} + +static int saa7164_dvb_pause_tsport(struct saa7164_tsport *port) +{ + struct saa7164_dev *dev = port->dev; + int ret; + + ret = saa7164_api_transition_port(port, SAA_DMASTATE_PAUSE); + if ((ret != SAA_OK) && (ret != SAA_ERR_ALREADY_STOPPED)) { + printk(KERN_ERR "%s() pause transition failed, ret = 0x%x\n", + __func__, ret); + ret = -EIO; + } else { + dprintk(DBGLVL_DVB, "%s() Paused\n", __func__); + ret = 0; + } + + return ret; +} + +/* Firmware is very windows centric, meaning you have to transition + * the part through AVStream / KS Windows stages, forwards or backwards. + * States are: stopped, acquired (h/w), paused, started. + */ +static int saa7164_dvb_stop_streaming(struct saa7164_tsport *port) +{ + struct saa7164_dev *dev = port->dev; + int ret; + + dprintk(DBGLVL_DVB, "%s(port=%d)\n", __func__, port->nr); + + ret = saa7164_dvb_pause_tsport(port); + ret = saa7164_dvb_acquire_tsport(port); + ret = saa7164_dvb_stop_tsport(port); + + return ret; +} + +static int saa7164_dvb_cfg_tsport(struct saa7164_tsport *port) +{ + tmHWStreamParameters_t *params = &port->hw_streamingparams; + struct saa7164_dev *dev = port->dev; + struct saa7164_buffer *buf; + struct list_head *c, *n; + int i = 0; + + dprintk(DBGLVL_DVB, "%s(port=%d)\n", __func__, port->nr); + + saa7164_writel(port->pitch, params->pitch); + saa7164_writel(port->bufsize, params->pitch * params->numberoflines); + + dprintk(DBGLVL_DVB, " configured:\n"); + dprintk(DBGLVL_DVB, " lmmio 0x%p\n", dev->lmmio); + dprintk(DBGLVL_DVB, " bufcounter 0x%x = 0x%x\n", port->bufcounter, + saa7164_readl(port->bufcounter)); + + dprintk(DBGLVL_DVB, " pitch 0x%x = %d\n", port->pitch, + saa7164_readl(port->pitch)); + + dprintk(DBGLVL_DVB, " bufsize 0x%x = %d\n", port->bufsize, + saa7164_readl(port->bufsize)); + + dprintk(DBGLVL_DVB, " buffercount = %d\n", port->hwcfg.buffercount); + dprintk(DBGLVL_DVB, " bufoffset = 0x%x\n", port->bufoffset); + dprintk(DBGLVL_DVB, " bufptr32h = 0x%x\n", port->bufptr32h); + dprintk(DBGLVL_DVB, " bufptr32l = 0x%x\n", port->bufptr32l); + + /* Poke the buffers and offsets into PCI space */ + mutex_lock(&port->dmaqueue_lock); + list_for_each_safe(c, n, &port->dmaqueue.list) { + buf = list_entry(c, struct saa7164_buffer, list); + + /* TODO: Review this in light of 32v64 assignments */ + saa7164_writel(port->bufoffset + (sizeof(u32) * i), 0); + saa7164_writel(port->bufptr32h + ((sizeof(u32) * 2) * i), + buf->pt_dma); + saa7164_writel(port->bufptr32l + ((sizeof(u32) * 2) * i), 0); + + dprintk(DBGLVL_DVB, + " buf[%d] offset 0x%llx (0x%x) " + "buf 0x%llx/%llx (0x%x/%x)\n", + i, + (u64)port->bufoffset + (i * sizeof(u32)), + saa7164_readl(port->bufoffset + (sizeof(u32) * i)), + (u64)port->bufptr32h + ((sizeof(u32) * 2) * i), + (u64)port->bufptr32l + ((sizeof(u32) * 2) * i), + saa7164_readl(port->bufptr32h + ((sizeof(u32) * i) + * 2)), + saa7164_readl(port->bufptr32l + ((sizeof(u32) * i) + * 2))); + + if (i++ > port->hwcfg.buffercount) + BUG(); + + } + mutex_unlock(&port->dmaqueue_lock); + + return 0; +} + +static int saa7164_dvb_start_tsport(struct saa7164_tsport *port) +{ + struct saa7164_dev *dev = port->dev; + int ret = 0, result; + + dprintk(DBGLVL_DVB, "%s(port=%d)\n", __func__, port->nr); + + saa7164_dvb_cfg_tsport(port); + + /* Acquire the hardware */ + result = saa7164_api_transition_port(port, SAA_DMASTATE_ACQUIRE); + if ((result != SAA_OK) && (result != SAA_ERR_ALREADY_STOPPED)) { + printk(KERN_ERR "%s() acquire transition failed, res = 0x%x\n", + __func__, result); + + /* Stop the hardware, regardless */ + result = saa7164_api_transition_port(port, SAA_DMASTATE_STOP); + if ((result != SAA_OK) && (result != SAA_ERR_ALREADY_STOPPED)) { + printk(KERN_ERR "%s() acquire/forced stop transition " + "failed, res = 0x%x\n", __func__, result); + } + ret = -EIO; + goto out; + } else + dprintk(DBGLVL_DVB, "%s() Acquired\n", __func__); + + /* Pause the hardware */ + result = saa7164_api_transition_port(port, SAA_DMASTATE_PAUSE); + if ((result != SAA_OK) && (result != SAA_ERR_ALREADY_STOPPED)) { + printk(KERN_ERR "%s() pause transition failed, res = 0x%x\n", + __func__, result); + + /* Stop the hardware, regardless */ + result = saa7164_api_transition_port(port, SAA_DMASTATE_STOP); + if ((result != SAA_OK) && (result != SAA_ERR_ALREADY_STOPPED)) { + printk(KERN_ERR "%s() pause/forced stop transition " + "failed, res = 0x%x\n", __func__, result); + } + + ret = -EIO; + goto out; + } else + dprintk(DBGLVL_DVB, "%s() Paused\n", __func__); + + /* Start the hardware */ + result = saa7164_api_transition_port(port, SAA_DMASTATE_RUN); + if ((result != SAA_OK) && (result != SAA_ERR_ALREADY_STOPPED)) { + printk(KERN_ERR "%s() run transition failed, result = 0x%x\n", + __func__, result); + + /* Stop the hardware, regardless */ + result = saa7164_api_transition_port(port, SAA_DMASTATE_STOP); + if ((result != SAA_OK) && (result != SAA_ERR_ALREADY_STOPPED)) { + printk(KERN_ERR "%s() run/forced stop transition " + "failed, res = 0x%x\n", __func__, result); + } + + ret = -EIO; + } else + dprintk(DBGLVL_DVB, "%s() Running\n", __func__); + +out: + return ret; +} + +static int saa7164_dvb_start_feed(struct dvb_demux_feed *feed) +{ + struct dvb_demux *demux = feed->demux; + struct saa7164_tsport *port = (struct saa7164_tsport *) demux->priv; + struct saa7164_dvb *dvb = &port->dvb; + struct saa7164_dev *dev = port->dev; + int ret = 0; + + dprintk(DBGLVL_DVB, "%s(port=%d)\n", __func__, port->nr); + + if (!demux->dmx.frontend) + return -EINVAL; + + if (dvb) { + mutex_lock(&dvb->lock); + if (dvb->feeding++ == 0) { + /* Start transport */ + ret = saa7164_dvb_start_tsport(port); + } + mutex_unlock(&dvb->lock); + dprintk(DBGLVL_DVB, "%s(port=%d) now feeding = %d\n", + __func__, port->nr, dvb->feeding); + } + + return ret; +} + +static int saa7164_dvb_stop_feed(struct dvb_demux_feed *feed) +{ + struct dvb_demux *demux = feed->demux; + struct saa7164_tsport *port = (struct saa7164_tsport *) demux->priv; + struct saa7164_dvb *dvb = &port->dvb; + struct saa7164_dev *dev = port->dev; + int ret = 0; + + dprintk(DBGLVL_DVB, "%s(port=%d)\n", __func__, port->nr); + + if (dvb) { + mutex_lock(&dvb->lock); + if (--dvb->feeding == 0) { + /* Stop transport */ + ret = saa7164_dvb_stop_streaming(port); + } + mutex_unlock(&dvb->lock); + dprintk(DBGLVL_DVB, "%s(port=%d) now feeding = %d\n", + __func__, port->nr, dvb->feeding); + } + + return ret; +} + +static int dvb_register(struct saa7164_tsport *port) +{ + struct saa7164_dvb *dvb = &port->dvb; + struct saa7164_dev *dev = port->dev; + struct saa7164_buffer *buf; + int result, i; + + dprintk(DBGLVL_DVB, "%s(port=%d)\n", __func__, port->nr); + + /* Sanity check that the PCI configuration space is active */ + if (port->hwcfg.BARLocation == 0) { + result = -ENOMEM; + printk(KERN_ERR "%s: dvb_register_adapter failed " + "(errno = %d), NO PCI configuration\n", + DRIVER_NAME, result); + goto fail_adapter; + } + + /* Init and establish defaults */ + port->hw_streamingparams.bitspersample = 8; + port->hw_streamingparams.samplesperline = 188; + port->hw_streamingparams.numberoflines = + (SAA7164_TS_NUMBER_OF_LINES * 188) / 188; + + port->hw_streamingparams.pitch = 188; + port->hw_streamingparams.linethreshold = 0; + port->hw_streamingparams.pagetablelistvirt = 0; + port->hw_streamingparams.pagetablelistphys = 0; + port->hw_streamingparams.numpagetables = 2 + + ((SAA7164_TS_NUMBER_OF_LINES * 188) / PAGE_SIZE); + + port->hw_streamingparams.numpagetableentries = port->hwcfg.buffercount; + + /* Allocate the PCI resources */ + for (i = 0; i < port->hwcfg.buffercount; i++) { + buf = saa7164_buffer_alloc(port, + port->hw_streamingparams.numberoflines * + port->hw_streamingparams.pitch); + + if (!buf) { + result = -ENOMEM; + printk(KERN_ERR "%s: dvb_register_adapter failed " + "(errno = %d), unable to allocate buffers\n", + DRIVER_NAME, result); + goto fail_adapter; + } + buf->nr = i; + + mutex_lock(&port->dmaqueue_lock); + list_add_tail(&buf->list, &port->dmaqueue.list); + mutex_unlock(&port->dmaqueue_lock); + } + + /* register adapter */ + result = dvb_register_adapter(&dvb->adapter, DRIVER_NAME, THIS_MODULE, + &dev->pci->dev, adapter_nr); + if (result < 0) { + printk(KERN_ERR "%s: dvb_register_adapter failed " + "(errno = %d)\n", DRIVER_NAME, result); + goto fail_adapter; + } + dvb->adapter.priv = port; + + /* register frontend */ + result = dvb_register_frontend(&dvb->adapter, dvb->frontend); + if (result < 0) { + printk(KERN_ERR "%s: dvb_register_frontend failed " + "(errno = %d)\n", DRIVER_NAME, result); + goto fail_frontend; + } + + /* register demux stuff */ + dvb->demux.dmx.capabilities = + DMX_TS_FILTERING | DMX_SECTION_FILTERING | + DMX_MEMORY_BASED_FILTERING; + dvb->demux.priv = port; + dvb->demux.filternum = 256; + dvb->demux.feednum = 256; + dvb->demux.start_feed = saa7164_dvb_start_feed; + dvb->demux.stop_feed = saa7164_dvb_stop_feed; + result = dvb_dmx_init(&dvb->demux); + if (result < 0) { + printk(KERN_ERR "%s: dvb_dmx_init failed (errno = %d)\n", + DRIVER_NAME, result); + goto fail_dmx; + } + + dvb->dmxdev.filternum = 256; + dvb->dmxdev.demux = &dvb->demux.dmx; + dvb->dmxdev.capabilities = 0; + result = dvb_dmxdev_init(&dvb->dmxdev, &dvb->adapter); + if (result < 0) { + printk(KERN_ERR "%s: dvb_dmxdev_init failed (errno = %d)\n", + DRIVER_NAME, result); + goto fail_dmxdev; + } + + dvb->fe_hw.source = DMX_FRONTEND_0; + result = dvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->fe_hw); + if (result < 0) { + printk(KERN_ERR "%s: add_frontend failed " + "(DMX_FRONTEND_0, errno = %d)\n", DRIVER_NAME, result); + goto fail_fe_hw; + } + + dvb->fe_mem.source = DMX_MEMORY_FE; + result = dvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->fe_mem); + if (result < 0) { + printk(KERN_ERR "%s: add_frontend failed " + "(DMX_MEMORY_FE, errno = %d)\n", DRIVER_NAME, result); + goto fail_fe_mem; + } + + result = dvb->demux.dmx.connect_frontend(&dvb->demux.dmx, &dvb->fe_hw); + if (result < 0) { + printk(KERN_ERR "%s: connect_frontend failed (errno = %d)\n", + DRIVER_NAME, result); + goto fail_fe_conn; + } + + /* register network adapter */ + dvb_net_init(&dvb->adapter, &dvb->net, &dvb->demux.dmx); + return 0; + +fail_fe_conn: + dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_mem); +fail_fe_mem: + dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_hw); +fail_fe_hw: + dvb_dmxdev_release(&dvb->dmxdev); +fail_dmxdev: + dvb_dmx_release(&dvb->demux); +fail_dmx: + dvb_unregister_frontend(dvb->frontend); +fail_frontend: + dvb_frontend_detach(dvb->frontend); + dvb_unregister_adapter(&dvb->adapter); +fail_adapter: + return result; +} + +int saa7164_dvb_unregister(struct saa7164_tsport *port) +{ + struct saa7164_dvb *dvb = &port->dvb; + struct saa7164_dev *dev = port->dev; + struct saa7164_buffer *b; + struct list_head *c, *n; + + dprintk(DBGLVL_DVB, "%s()\n", __func__); + + /* Remove any allocated buffers */ + mutex_lock(&port->dmaqueue_lock); + list_for_each_safe(c, n, &port->dmaqueue.list) { + b = list_entry(c, struct saa7164_buffer, list); + list_del(c); + saa7164_buffer_dealloc(port, b); + } + mutex_unlock(&port->dmaqueue_lock); + + if (dvb->frontend == NULL) + return 0; + + dvb_net_release(&dvb->net); + dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_mem); + dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_hw); + dvb_dmxdev_release(&dvb->dmxdev); + dvb_dmx_release(&dvb->demux); + dvb_unregister_frontend(dvb->frontend); + dvb_frontend_detach(dvb->frontend); + dvb_unregister_adapter(&dvb->adapter); + return 0; +} + +/* All the DVB attach calls go here, this function get's modified + * for each new card. + */ +int saa7164_dvb_register(struct saa7164_tsport *port) +{ + struct saa7164_dev *dev = port->dev; + struct saa7164_dvb *dvb = &port->dvb; + struct saa7164_i2c *i2c_bus = NULL; + int ret; + + dprintk(DBGLVL_DVB, "%s()\n", __func__); + + /* init frontend */ + switch (dev->board) { + case SAA7164_BOARD_HAUPPAUGE_HVR2200: + case SAA7164_BOARD_HAUPPAUGE_HVR2200_2: + case SAA7164_BOARD_HAUPPAUGE_HVR2200_3: + i2c_bus = &dev->i2c_bus[port->nr + 1]; + switch (port->nr) { + case 0: + port->dvb.frontend = dvb_attach(tda10048_attach, + &hauppauge_hvr2200_1_config, + &i2c_bus->i2c_adap); + + if (port->dvb.frontend != NULL) { + /* TODO: addr is in the card struct */ + dvb_attach(tda18271_attach, port->dvb.frontend, + 0xc0 >> 1, &i2c_bus->i2c_adap, + &hauppauge_hvr22x0_tuner_config); + } + + break; + case 1: + port->dvb.frontend = dvb_attach(tda10048_attach, + &hauppauge_hvr2200_2_config, + &i2c_bus->i2c_adap); + + if (port->dvb.frontend != NULL) { + /* TODO: addr is in the card struct */ + dvb_attach(tda18271_attach, port->dvb.frontend, + 0xc0 >> 1, &i2c_bus->i2c_adap, + &hauppauge_hvr22x0s_tuner_config); + } + + break; + } + break; + case SAA7164_BOARD_HAUPPAUGE_HVR2250: + case SAA7164_BOARD_HAUPPAUGE_HVR2250_2: + case SAA7164_BOARD_HAUPPAUGE_HVR2250_3: + i2c_bus = &dev->i2c_bus[port->nr + 1]; + + port->dvb.frontend = dvb_attach(s5h1411_attach, + &hauppauge_s5h1411_config, + &i2c_bus->i2c_adap); + + if (port->dvb.frontend != NULL) { + if (port->nr == 0) { + /* Master TDA18271 */ + /* TODO: addr is in the card struct */ + dvb_attach(tda18271_attach, port->dvb.frontend, + 0xc0 >> 1, &i2c_bus->i2c_adap, + &hauppauge_hvr22x0_tuner_config); + } else { + /* Slave TDA18271 */ + dvb_attach(tda18271_attach, port->dvb.frontend, + 0xc0 >> 1, &i2c_bus->i2c_adap, + &hauppauge_hvr22x0s_tuner_config); + } + } + + break; + default: + printk(KERN_ERR "%s: The frontend isn't supported\n", + dev->name); + break; + } + if (NULL == dvb->frontend) { + printk(KERN_ERR "%s() Frontend initialization failed\n", + __func__); + return -1; + } + + /* Put the analog decoder in standby to keep it quiet */ + + /* register everything */ + ret = dvb_register(port); + if (ret < 0) { + if (dvb->frontend->ops.release) + dvb->frontend->ops.release(dvb->frontend); + return ret; + } + + return 0; +} + diff --git a/drivers/media/video/saa7164/saa7164-fw.c b/drivers/media/video/saa7164/saa7164-fw.c new file mode 100644 index 000000000000..ee0af3534ede --- /dev/null +++ b/drivers/media/video/saa7164/saa7164-fw.c @@ -0,0 +1,613 @@ +/* + * Driver for the NXP SAA7164 PCIe bridge + * + * Copyright (c) 2009 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +#include "saa7164.h" + +#define SAA7164_REV2_FIRMWARE "v4l-saa7164-1.0.2.fw" +#define SAA7164_REV2_FIRMWARE_SIZE 3978608 + +#define SAA7164_REV3_FIRMWARE "v4l-saa7164-1.0.3.fw" +#define SAA7164_REV3_FIRMWARE_SIZE 3978608 + +struct fw_header { + u32 firmwaresize; + u32 bslsize; + u32 reserved; + u32 version; +}; + +int saa7164_dl_wait_ack(struct saa7164_dev *dev, u32 reg) +{ + u32 timeout = SAA_DEVICE_TIMEOUT; + while ((saa7164_readl(reg) & 0x01) == 0) { + timeout -= 10; + if (timeout == 0) { + printk(KERN_ERR "%s() timeout (no d/l ack)\n", + __func__); + return -EBUSY; + } + msleep(100); + } + + return 0; +} + +int saa7164_dl_wait_clr(struct saa7164_dev *dev, u32 reg) +{ + u32 timeout = SAA_DEVICE_TIMEOUT; + while (saa7164_readl(reg) & 0x01) { + timeout -= 10; + if (timeout == 0) { + printk(KERN_ERR "%s() timeout (no d/l clr)\n", + __func__); + return -EBUSY; + } + msleep(100); + } + + return 0; +} + +/* TODO: move dlflags into dev-> and change to write/readl/b */ +/* TODO: Excessive levels of debug */ +int saa7164_downloadimage(struct saa7164_dev *dev, u8 *src, u32 srcsize, + u32 dlflags, u8 *dst, u32 dstsize) +{ + u32 reg, timeout, offset; + u8 *srcbuf = NULL; + int ret; + + u32 dlflag = dlflags; + u32 dlflag_ack = dlflag + 4; + u32 drflag = dlflag_ack + 4; + u32 drflag_ack = drflag + 4; + u32 bleflag = drflag_ack + 4; + + dprintk(DBGLVL_FW, + "%s(image=%p, size=%d, flags=0x%x, dst=%p, dstsize=0x%x)\n", + __func__, src, srcsize, dlflags, dst, dstsize); + + if ((src == 0) || (dst == 0)) { + ret = -EIO; + goto out; + } + + srcbuf = kzalloc(4 * 1048576, GFP_KERNEL); + if (NULL == srcbuf) { + ret = -ENOMEM; + goto out; + } + + if (srcsize > (4*1048576)) { + ret = -ENOMEM; + goto out; + } + + memcpy(srcbuf, src, srcsize); + + dprintk(DBGLVL_FW, "%s() dlflag = 0x%x\n", __func__, dlflag); + dprintk(DBGLVL_FW, "%s() dlflag_ack = 0x%x\n", __func__, dlflag_ack); + dprintk(DBGLVL_FW, "%s() drflag = 0x%x\n", __func__, drflag); + dprintk(DBGLVL_FW, "%s() drflag_ack = 0x%x\n", __func__, drflag_ack); + dprintk(DBGLVL_FW, "%s() bleflag = 0x%x\n", __func__, bleflag); + + reg = saa7164_readl(dlflag); + dprintk(DBGLVL_FW, "%s() dlflag (0x%x)= 0x%x\n", __func__, dlflag, reg); + if (reg == 1) + dprintk(DBGLVL_FW, + "%s() Download flag already set, please reboot\n", + __func__); + + /* Indicate download start */ + saa7164_writel(dlflag, 1); + ret = saa7164_dl_wait_ack(dev, dlflag_ack); + if (ret < 0) + goto out; + + /* Ack download start, then wait for wait */ + saa7164_writel(dlflag, 0); + ret = saa7164_dl_wait_clr(dev, dlflag_ack); + if (ret < 0) + goto out; + + /* Deal with the raw firmware, in the appropriate chunk size */ + for (offset = 0; srcsize > dstsize; + srcsize -= dstsize, offset += dstsize) { + + dprintk(DBGLVL_FW, "%s() memcpy %d\n", __func__, dstsize); + memcpy(dst, srcbuf + offset, dstsize); + + /* Flag the data as ready */ + saa7164_writel(drflag, 1); + ret = saa7164_dl_wait_ack(dev, drflag_ack); + if (ret < 0) + goto out; + + /* Wait for indication data was received */ + saa7164_writel(drflag, 0); + ret = saa7164_dl_wait_clr(dev, drflag_ack); + if (ret < 0) + goto out; + + } + + dprintk(DBGLVL_FW, "%s() memcpy(l) %d\n", __func__, dstsize); + /* Write last block to the device */ + memcpy(dst, srcbuf+offset, srcsize); + + /* Flag the data as ready */ + saa7164_writel(drflag, 1); + ret = saa7164_dl_wait_ack(dev, drflag_ack); + if (ret < 0) + goto out; + + saa7164_writel(drflag, 0); + timeout = 0; + while (saa7164_readl(bleflag) != SAA_DEVICE_IMAGE_BOOTING) { + if (saa7164_readl(bleflag) & SAA_DEVICE_IMAGE_CORRUPT) { + printk(KERN_ERR "%s() image corrupt\n", __func__); + ret = -EBUSY; + goto out; + } + + if (saa7164_readl(bleflag) & SAA_DEVICE_MEMORY_CORRUPT) { + printk(KERN_ERR "%s() device memory corrupt\n", + __func__); + ret = -EBUSY; + goto out; + } + + msleep(10); + if (timeout++ > 60) + break; + } + + printk(KERN_INFO "%s() Image downloaded, booting...\n", __func__); + + ret = saa7164_dl_wait_clr(dev, drflag_ack); + if (ret < 0) + goto out; + + printk(KERN_INFO "%s() Image booted successfully.\n", __func__); + ret = 0; + +out: + kfree(srcbuf); + return ret; +} + +/* TODO: Excessive debug */ +/* Load the firmware. Optionally it can be in ROM or newer versions + * can be on disk, saving the expense of the ROM hardware. */ +int saa7164_downloadfirmware(struct saa7164_dev *dev) +{ + /* u32 second_timeout = 60 * SAA_DEVICE_TIMEOUT; */ + u32 tmp, filesize, version, err_flags, first_timeout, fwlength; + u32 second_timeout, updatebootloader = 1, bootloadersize = 0; + const struct firmware *fw = NULL; + struct fw_header *hdr, *boothdr = NULL, *fwhdr; + u32 bootloaderversion = 0, fwloadersize; + u8 *bootloaderoffset = NULL, *fwloaderoffset; + char *fwname; + int ret; + + dprintk(DBGLVL_FW, "%s()\n", __func__); + + if (saa7164_boards[dev->board].chiprev == SAA7164_CHIP_REV2) { + fwname = SAA7164_REV2_FIRMWARE; + fwlength = SAA7164_REV2_FIRMWARE_SIZE; + } else { + fwname = SAA7164_REV3_FIRMWARE; + fwlength = SAA7164_REV3_FIRMWARE_SIZE; + } + + version = saa7164_getcurrentfirmwareversion(dev); + + if (version == 0x00) { + + second_timeout = 100; + first_timeout = 100; + err_flags = saa7164_readl(SAA_BOOTLOADERERROR_FLAGS); + dprintk(DBGLVL_FW, "%s() err_flags = %x\n", + __func__, err_flags); + + while (err_flags != SAA_DEVICE_IMAGE_BOOTING) { + dprintk(DBGLVL_FW, "%s() err_flags = %x\n", + __func__, err_flags); + msleep(10); + + if (err_flags & SAA_DEVICE_IMAGE_CORRUPT) { + printk(KERN_ERR "%s() firmware corrupt\n", + __func__); + break; + } + if (err_flags & SAA_DEVICE_MEMORY_CORRUPT) { + printk(KERN_ERR "%s() device memory corrupt\n", + __func__); + break; + } + if (err_flags & SAA_DEVICE_NO_IMAGE) { + printk(KERN_ERR "%s() no first image\n", + __func__); + break; + } + if (err_flags & SAA_DEVICE_IMAGE_SEARCHING) { + first_timeout -= 10; + if (first_timeout == 0) { + printk(KERN_ERR + "%s() no first image\n", + __func__); + break; + } + } else if (err_flags & SAA_DEVICE_IMAGE_LOADING) { + second_timeout -= 10; + if (second_timeout == 0) { + printk(KERN_ERR + "%s() FW load time exceeded\n", + __func__); + break; + } + } else { + second_timeout -= 10; + if (second_timeout == 0) { + printk(KERN_ERR + "%s() Unknown bootloader flags 0x%x\n", + __func__, err_flags); + break; + } + } + + err_flags = saa7164_readl(SAA_BOOTLOADERERROR_FLAGS); + } /* While != Booting */ + + if (err_flags == SAA_DEVICE_IMAGE_BOOTING) { + dprintk(DBGLVL_FW, "%s() Loader 1 has loaded.\n", + __func__); + first_timeout = SAA_DEVICE_TIMEOUT; + second_timeout = 60 * SAA_DEVICE_TIMEOUT; + second_timeout = 100; + + err_flags = saa7164_readl(SAA_SECONDSTAGEERROR_FLAGS); + dprintk(DBGLVL_FW, "%s() err_flags2 = %x\n", + __func__, err_flags); + while (err_flags != SAA_DEVICE_IMAGE_BOOTING) { + dprintk(DBGLVL_FW, "%s() err_flags2 = %x\n", + __func__, err_flags); + msleep(10); + + if (err_flags & SAA_DEVICE_IMAGE_CORRUPT) { + printk(KERN_ERR + "%s() firmware corrupt\n", + __func__); + break; + } + if (err_flags & SAA_DEVICE_MEMORY_CORRUPT) { + printk(KERN_ERR + "%s() device memory corrupt\n", + __func__); + break; + } + if (err_flags & SAA_DEVICE_NO_IMAGE) { + printk(KERN_ERR "%s() no first image\n", + __func__); + break; + } + if (err_flags & SAA_DEVICE_IMAGE_SEARCHING) { + first_timeout -= 10; + if (first_timeout == 0) { + printk(KERN_ERR + "%s() no second image\n", + __func__); + break; + } + } else if (err_flags & + SAA_DEVICE_IMAGE_LOADING) { + second_timeout -= 10; + if (second_timeout == 0) { + printk(KERN_ERR + "%s() FW load time exceeded\n", + __func__); + break; + } + } else { + second_timeout -= 10; + if (second_timeout == 0) { + printk(KERN_ERR + "%s() Unknown bootloader flags 0x%x\n", + __func__, err_flags); + break; + } + } + + err_flags = + saa7164_readl(SAA_SECONDSTAGEERROR_FLAGS); + } /* err_flags != SAA_DEVICE_IMAGE_BOOTING */ + + dprintk(DBGLVL_FW, "%s() Loader flags 1:0x%x 2:0x%x.\n", + __func__, + saa7164_readl(SAA_BOOTLOADERERROR_FLAGS), + saa7164_readl(SAA_SECONDSTAGEERROR_FLAGS)); + + } /* err_flags == SAA_DEVICE_IMAGE_BOOTING */ + + /* It's possible for both firmwares to have booted, + * but that doesn't mean they've finished booting yet. + */ + if ((saa7164_readl(SAA_BOOTLOADERERROR_FLAGS) == + SAA_DEVICE_IMAGE_BOOTING) && + (saa7164_readl(SAA_SECONDSTAGEERROR_FLAGS) == + SAA_DEVICE_IMAGE_BOOTING)) { + + + dprintk(DBGLVL_FW, "%s() Loader 2 has loaded.\n", + __func__); + + first_timeout = SAA_DEVICE_TIMEOUT; + while (first_timeout) { + msleep(10); + + version = + saa7164_getcurrentfirmwareversion(dev); + if (version) { + dprintk(DBGLVL_FW, + "%s() All f/w loaded successfully\n", + __func__); + break; + } else { + first_timeout -= 10; + if (first_timeout == 0) { + printk(KERN_ERR + "%s() FW did not boot\n", + __func__); + break; + } + } + } + } + version = saa7164_getcurrentfirmwareversion(dev); + } /* version == 0 */ + + /* Has the firmware really booted? */ + if ((saa7164_readl(SAA_BOOTLOADERERROR_FLAGS) == + SAA_DEVICE_IMAGE_BOOTING) && + (saa7164_readl(SAA_SECONDSTAGEERROR_FLAGS) == + SAA_DEVICE_IMAGE_BOOTING) && (version == 0)) { + + printk(KERN_ERR + "%s() The firmware hung, probably bad firmware\n", + __func__); + + /* Tell the second stage loader we have a deadlock */ + saa7164_writel(SAA_DEVICE_DEADLOCK_DETECTED_OFFSET, + SAA_DEVICE_DEADLOCK_DETECTED); + + saa7164_getfirmwarestatus(dev); + + return -ENOMEM; + } + + dprintk(DBGLVL_FW, "Device has Firmware Version %d.%d.%d.%d\n", + (version & 0x0000fc00) >> 10, + (version & 0x000003e0) >> 5, + (version & 0x0000001f), + (version & 0xffff0000) >> 16); + + /* Load the firmwware from the disk if required */ + if (version == 0) { + + printk(KERN_INFO "%s() Waiting for firmware upload (%s)\n", + __func__, fwname); + + ret = request_firmware(&fw, fwname, &dev->pci->dev); + if (ret) { + printk(KERN_ERR "%s() Upload failed. " + "(file not found?)\n", __func__); + return -ENOMEM; + } + + printk(KERN_INFO "%s() firmware read %Zu bytes.\n", + __func__, fw->size); + + if (fw->size != fwlength) { + printk(KERN_ERR "xc5000: firmware incorrect size\n"); + ret = -ENOMEM; + goto out; + } + + printk(KERN_INFO "%s() firmware loaded.\n", __func__); + + hdr = (struct fw_header *)fw->data; + printk(KERN_INFO "Firmware file header part 1:\n"); + printk(KERN_INFO " .FirmwareSize = 0x%x\n", hdr->firmwaresize); + printk(KERN_INFO " .BSLSize = 0x%x\n", hdr->bslsize); + printk(KERN_INFO " .Reserved = 0x%x\n", hdr->reserved); + printk(KERN_INFO " .Version = 0x%x\n", hdr->version); + + /* Retreive bootloader if reqd */ + if ((hdr->firmwaresize == 0) && (hdr->bslsize == 0)) + /* Second bootloader in the firmware file */ + filesize = hdr->reserved * 16; + else + filesize = (hdr->firmwaresize + hdr->bslsize) * + 16 + sizeof(struct fw_header); + + printk(KERN_INFO "%s() SecBootLoader.FileSize = %d\n", + __func__, filesize); + + /* Get bootloader (if reqd) and firmware header */ + if ((hdr->firmwaresize == 0) && (hdr->bslsize == 0)) { + /* Second boot loader is required */ + + /* Get the loader header */ + boothdr = (struct fw_header *)(fw->data + + sizeof(struct fw_header)); + + bootloaderversion = + saa7164_readl(SAA_DEVICE_2ND_VERSION); + dprintk(DBGLVL_FW, "Onboard BootLoader:\n"); + dprintk(DBGLVL_FW, "->Flag 0x%x\n", + saa7164_readl(SAA_BOOTLOADERERROR_FLAGS)); + dprintk(DBGLVL_FW, "->Ack 0x%x\n", + saa7164_readl(SAA_DATAREADY_FLAG_ACK)); + dprintk(DBGLVL_FW, "->FW Version 0x%x\n", version); + dprintk(DBGLVL_FW, "->Loader Version 0x%x\n", + bootloaderversion); + + if ((saa7164_readl(SAA_BOOTLOADERERROR_FLAGS) == + 0x03) && (saa7164_readl(SAA_DATAREADY_FLAG_ACK) + == 0x00) && (version == 0x00)) { + + dprintk(DBGLVL_FW, "BootLoader version in " + "rom %d.%d.%d.%d\n", + (bootloaderversion & 0x0000fc00) >> 10, + (bootloaderversion & 0x000003e0) >> 5, + (bootloaderversion & 0x0000001f), + (bootloaderversion & 0xffff0000) >> 16 + ); + dprintk(DBGLVL_FW, "BootLoader version " + "in file %d.%d.%d.%d\n", + (boothdr->version & 0x0000fc00) >> 10, + (boothdr->version & 0x000003e0) >> 5, + (boothdr->version & 0x0000001f), + (boothdr->version & 0xffff0000) >> 16 + ); + + if (bootloaderversion == boothdr->version) + updatebootloader = 0; + } + + /* Calculate offset to firmware header */ + tmp = (boothdr->firmwaresize + boothdr->bslsize) * 16 + + (sizeof(struct fw_header) + + sizeof(struct fw_header)); + + fwhdr = (struct fw_header *)(fw->data+tmp); + } else { + /* No second boot loader */ + fwhdr = hdr; + } + + dprintk(DBGLVL_FW, "Firmware version in file %d.%d.%d.%d\n", + (fwhdr->version & 0x0000fc00) >> 10, + (fwhdr->version & 0x000003e0) >> 5, + (fwhdr->version & 0x0000001f), + (fwhdr->version & 0xffff0000) >> 16 + ); + + if (version == fwhdr->version) { + /* No download, firmware already on board */ + ret = 0; + goto out; + } + + if ((hdr->firmwaresize == 0) && (hdr->bslsize == 0)) { + if (updatebootloader) { + /* Get ready to upload the bootloader */ + bootloadersize = (boothdr->firmwaresize + + boothdr->bslsize) * 16 + + sizeof(struct fw_header); + + bootloaderoffset = (u8 *)(fw->data + + sizeof(struct fw_header)); + + dprintk(DBGLVL_FW, "bootloader d/l starts.\n"); + printk(KERN_INFO "%s() FirmwareSize = 0x%x\n", + __func__, boothdr->firmwaresize); + printk(KERN_INFO "%s() BSLSize = 0x%x\n", + __func__, boothdr->bslsize); + printk(KERN_INFO "%s() Reserved = 0x%x\n", + __func__, boothdr->reserved); + printk(KERN_INFO "%s() Version = 0x%x\n", + __func__, boothdr->version); + ret = saa7164_downloadimage( + dev, + bootloaderoffset, + bootloadersize, + SAA_DOWNLOAD_FLAGS, + dev->bmmio + SAA_DEVICE_DOWNLOAD_OFFSET, + SAA_DEVICE_BUFFERBLOCKSIZE); + if (ret < 0) { + printk(KERN_ERR + "bootloader d/l has failed\n"); + goto out; + } + dprintk(DBGLVL_FW, + "bootloader download complete.\n"); + + } + + printk(KERN_ERR "starting firmware download(2)\n"); + bootloadersize = (boothdr->firmwaresize + + boothdr->bslsize) * 16 + + sizeof(struct fw_header); + + bootloaderoffset = + (u8 *)(fw->data + sizeof(struct fw_header)); + + fwloaderoffset = bootloaderoffset + bootloadersize; + + /* TODO: fix this bounds overrun here with old f/ws */ + fwloadersize = (fwhdr->firmwaresize + fwhdr->bslsize) * + 16 + sizeof(struct fw_header); + + ret = saa7164_downloadimage( + dev, + fwloaderoffset, + fwloadersize, + SAA_DEVICE_2ND_DOWNLOADFLAG_OFFSET, + dev->bmmio + SAA_DEVICE_2ND_DOWNLOAD_OFFSET, + SAA_DEVICE_2ND_BUFFERBLOCKSIZE); + if (ret < 0) { + printk(KERN_ERR "firmware download failed\n"); + goto out; + } + printk(KERN_ERR "firmware download complete.\n"); + + } else { + + /* No bootloader update reqd, download firmware only */ + printk(KERN_ERR "starting firmware download(3)\n"); + + ret = saa7164_downloadimage( + dev, + (u8 *)fw->data, + fw->size, + SAA_DOWNLOAD_FLAGS, + dev->bmmio + SAA_DEVICE_DOWNLOAD_OFFSET, + SAA_DEVICE_BUFFERBLOCKSIZE); + if (ret < 0) { + printk(KERN_ERR "firmware download failed\n"); + goto out; + } + printk(KERN_ERR "firmware download complete.\n"); + } + } + + ret = 0; + +out: + if (fw) + release_firmware(fw); + + return ret; +} diff --git a/drivers/media/video/saa7164/saa7164-i2c.c b/drivers/media/video/saa7164/saa7164-i2c.c new file mode 100644 index 000000000000..e1ae9b01bf0f --- /dev/null +++ b/drivers/media/video/saa7164/saa7164-i2c.c @@ -0,0 +1,141 @@ +/* + * Driver for the NXP SAA7164 PCIe bridge + * + * Copyright (c) 2009 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include + +#include "saa7164.h" + +static int i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) +{ + struct saa7164_i2c *bus = i2c_adap->algo_data; + struct saa7164_dev *dev = bus->dev; + int i, retval = 0; + + dprintk(DBGLVL_I2C, "%s(num = %d)\n", __func__, num); + + for (i = 0 ; i < num; i++) { + dprintk(DBGLVL_I2C, "%s(num = %d) addr = 0x%02x len = 0x%x\n", + __func__, num, msgs[i].addr, msgs[i].len); + if (msgs[i].flags & I2C_M_RD) { + /* Unsupported - Yet*/ + printk(KERN_ERR "%s() Unsupported - Yet\n", __func__); + continue; + } else if (i + 1 < num && (msgs[i + 1].flags & I2C_M_RD) && + msgs[i].addr == msgs[i + 1].addr) { + /* write then read from same address */ + + retval = saa7164_api_i2c_read(bus, msgs[i].addr, + msgs[i].len, msgs[i].buf, + msgs[i+1].len, msgs[i+1].buf + ); + + i++; + + if (retval < 0) + goto err; + } else { + /* write */ + retval = saa7164_api_i2c_write(bus, msgs[i].addr, + msgs[i].len, msgs[i].buf); + } + if (retval < 0) + goto err; + } + return num; + + err: + return retval; +} + +void saa7164_call_i2c_clients(struct saa7164_i2c *bus, unsigned int cmd, + void *arg) +{ + if (bus->i2c_rc != 0) + return; + + i2c_clients_command(&bus->i2c_adap, cmd, arg); +} + +static u32 saa7164_functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C; +} + +static struct i2c_algorithm saa7164_i2c_algo_template = { + .master_xfer = i2c_xfer, + .functionality = saa7164_functionality, +}; + +/* ----------------------------------------------------------------------- */ + +static struct i2c_adapter saa7164_i2c_adap_template = { + .name = "saa7164", + .owner = THIS_MODULE, + .algo = &saa7164_i2c_algo_template, +}; + +static struct i2c_client saa7164_i2c_client_template = { + .name = "saa7164 internal", +}; + +int saa7164_i2c_register(struct saa7164_i2c *bus) +{ + struct saa7164_dev *dev = bus->dev; + + dprintk(DBGLVL_I2C, "%s(bus = %d)\n", __func__, bus->nr); + + memcpy(&bus->i2c_adap, &saa7164_i2c_adap_template, + sizeof(bus->i2c_adap)); + + memcpy(&bus->i2c_algo, &saa7164_i2c_algo_template, + sizeof(bus->i2c_algo)); + + memcpy(&bus->i2c_client, &saa7164_i2c_client_template, + sizeof(bus->i2c_client)); + + bus->i2c_adap.dev.parent = &dev->pci->dev; + + strlcpy(bus->i2c_adap.name, bus->dev->name, + sizeof(bus->i2c_adap.name)); + + bus->i2c_algo.data = bus; + bus->i2c_adap.algo_data = bus; + i2c_set_adapdata(&bus->i2c_adap, bus); + i2c_add_adapter(&bus->i2c_adap); + + bus->i2c_client.adapter = &bus->i2c_adap; + + if (0 != bus->i2c_rc) + printk(KERN_ERR "%s: i2c bus %d register FAILED\n", + dev->name, bus->nr); + + return bus->i2c_rc; +} + +int saa7164_i2c_unregister(struct saa7164_i2c *bus) +{ + i2c_del_adapter(&bus->i2c_adap); + return 0; +} diff --git a/drivers/media/video/saa7164/saa7164-reg.h b/drivers/media/video/saa7164/saa7164-reg.h new file mode 100644 index 000000000000..06be4c13d5b1 --- /dev/null +++ b/drivers/media/video/saa7164/saa7164-reg.h @@ -0,0 +1,166 @@ +/* + * Driver for the NXP SAA7164 PCIe bridge + * + * Copyright (c) 2009 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* TODO: Retest the driver with errors expressed as negatives */ + +/* Result codes */ +#define SAA_OK 0 +#define SAA_ERR_BAD_PARAMETER 0x09 +#define SAA_ERR_NO_RESOURCES 0x0c +#define SAA_ERR_NOT_SUPPORTED 0x13 +#define SAA_ERR_BUSY 0x15 +#define SAA_ERR_READ 0x17 +#define SAA_ERR_TIMEOUT 0x1f +#define SAA_ERR_OVERFLOW 0x20 +#define SAA_ERR_EMPTY 0x22 +#define SAA_ERR_NOT_STARTED 0x23 +#define SAA_ERR_ALREADY_STARTED 0x24 +#define SAA_ERR_NOT_STOPPED 0x25 +#define SAA_ERR_ALREADY_STOPPED 0x26 +#define SAA_ERR_INVALID_COMMAND 0x3e +#define SAA_ERR_NULL_PACKET 0x59 + +/* Errors and flags from the silicon */ +#define PVC_ERRORCODE_UNKNOWN 0x00 +#define PVC_ERRORCODE_INVALID_COMMAND 0x01 +#define PVC_ERRORCODE_INVALID_CONTROL 0x02 +#define PVC_ERRORCODE_INVALID_DATA 0x03 +#define PVC_ERRORCODE_TIMEOUT 0x04 +#define PVC_ERRORCODE_NAK 0x05 +#define PVC_RESPONSEFLAG_ERROR 0x01 +#define PVC_RESPONSEFLAG_OVERFLOW 0x02 +#define PVC_RESPONSEFLAG_RESET 0x04 +#define PVC_RESPONSEFLAG_INTERFACE 0x08 +#define PVC_RESPONSEFLAG_CONTINUED 0x10 +#define PVC_CMDFLAG_INTERRUPT 0x02 +#define PVC_CMDFLAG_INTERFACE 0x04 +#define PVC_CMDFLAG_SERIALIZE 0x08 +#define PVC_CMDFLAG_CONTINUE 0x10 + +/* Silicon Commands */ +#define GET_DESCRIPTORS_CONTROL 0x01 +#define GET_STRING_CONTROL 0x03 +#define GET_LANGUAGE_CONTROL 0x05 +#define SET_POWER_CONTROL 0x07 +#define GET_FW_VERSION_CONTROL 0x09 +#define SET_DEBUG_LEVEL_CONTROL 0x0B +#define GET_DEBUG_DATA_CONTROL 0x0C +#define GET_PRODUCTION_INFO_CONTROL 0x0D + +/* cmd defines */ +#define SAA_CMDFLAG_CONTINUE 0x10 +#define SAA_CMD_MAX_MSG_UNITS 256 + +/* Some defines */ +#define SAA_BUS_TIMEOUT 50 +#define SAA_DEVICE_TIMEOUT 5000 +#define SAA_DEVICE_MAXREQUESTSIZE 256 + +/* Register addresses */ +#define SAA_DEVICE_VERSION 0x30 +#define SAA_DOWNLOAD_FLAGS 0x34 +#define SAA_DOWNLOAD_FLAG 0x34 +#define SAA_DOWNLOAD_FLAG_ACK 0x38 +#define SAA_DATAREADY_FLAG 0x3C +#define SAA_DATAREADY_FLAG_ACK 0x40 + +/* Boot loader register and bit definitions */ +#define SAA_BOOTLOADERERROR_FLAGS 0x44 +#define SAA_DEVICE_IMAGE_SEARCHING 0x01 +#define SAA_DEVICE_IMAGE_LOADING 0x02 +#define SAA_DEVICE_IMAGE_BOOTING 0x03 +#define SAA_DEVICE_IMAGE_CORRUPT 0x04 +#define SAA_DEVICE_MEMORY_CORRUPT 0x08 +#define SAA_DEVICE_NO_IMAGE 0x10 + +/* Register addresses */ +#define SAA_DEVICE_2ND_VERSION 0x50 +#define SAA_DEVICE_2ND_DOWNLOADFLAG_OFFSET 0x54 + +/* Register addresses */ +#define SAA_SECONDSTAGEERROR_FLAGS 0x64 + +/* Bootloader regs and flags */ +#define SAA_DEVICE_DEADLOCK_DETECTED_OFFSET 0x6C +#define SAA_DEVICE_DEADLOCK_DETECTED 0xDEADDEAD + +/* Basic firmware status registers */ +#define SAA_DEVICE_SYSINIT_STATUS_OFFSET 0x70 +#define SAA_DEVICE_SYSINIT_STATUS 0x70 +#define SAA_DEVICE_SYSINIT_MODE 0x74 +#define SAA_DEVICE_SYSINIT_SPEC 0x78 +#define SAA_DEVICE_SYSINIT_INST 0x7C +#define SAA_DEVICE_SYSINIT_CPULOAD 0x80 +#define SAA_DEVICE_SYSINIT_REMAINHEAP 0x84 + +#define SAA_DEVICE_DOWNLOAD_OFFSET 0x1000 +#define SAA_DEVICE_BUFFERBLOCKSIZE 0x1000 + +#define SAA_DEVICE_2ND_BUFFERBLOCKSIZE 0x100000 +#define SAA_DEVICE_2ND_DOWNLOAD_OFFSET 0x200000 + +/* Descriptors */ +#define CS_INTERFACE 0x24 + +/* Descriptor subtypes */ +#define VC_INPUT_TERMINAL 0x02 +#define VC_OUTPUT_TERMINAL 0x03 +#define VC_SELECTOR_UNIT 0x04 +#define VC_PROCESSING_UNIT 0x05 +#define FEATURE_UNIT 0x06 +#define TUNER_UNIT 0x09 +#define ENCODER_UNIT 0x0A +#define EXTENSION_UNIT 0x0B +#define VC_TUNER_PATH 0xF0 +#define PVC_HARDWARE_DESCRIPTOR 0xF1 +#define PVC_INTERFACE_DESCRIPTOR 0xF2 +#define PVC_INFRARED_UNIT 0xF3 +#define DRM_UNIT 0xF4 +#define GENERAL_REQUEST 0xF5 + +/* Format Types */ +#define VS_FORMAT_TYPE 0x02 +#define VS_FORMAT_TYPE_I 0x01 +#define VS_FORMAT_UNCOMPRESSED 0x04 +#define VS_FRAME_UNCOMPRESSED 0x05 +#define VS_FORMAT_MPEG2PS 0x09 +#define VS_FORMAT_MPEG2TS 0x0A +#define VS_FORMAT_MPEG4SL 0x0B +#define VS_FORMAT_WM9 0x0C +#define VS_FORMAT_DIVX 0x0D +#define VS_FORMAT_VBI 0x0E +#define VS_FORMAT_RDS 0x0F + +/* Device extension commands */ +#define EXU_REGISTER_ACCESS_CONTROL 0x00 +#define EXU_GPIO_CONTROL 0x01 +#define EXU_GPIO_GROUP_CONTROL 0x02 +#define EXU_INTERRUPT_CONTROL 0x03 + +/* State Transition and args */ +#define SAA_STATE_CONTROL 0x03 +#define SAA_DMASTATE_STOP 0x00 +#define SAA_DMASTATE_ACQUIRE 0x01 +#define SAA_DMASTATE_PAUSE 0x02 +#define SAA_DMASTATE_RUN 0x03 + +/* Hardware registers */ + diff --git a/drivers/media/video/saa7164/saa7164-types.h b/drivers/media/video/saa7164/saa7164-types.h new file mode 100644 index 000000000000..99093f23aae5 --- /dev/null +++ b/drivers/media/video/saa7164/saa7164-types.h @@ -0,0 +1,287 @@ +/* + * Driver for the NXP SAA7164 PCIe bridge + * + * Copyright (c) 2009 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* TODO: Cleanup and shorten the namespace */ + +/* Some structues are passed directly to/from the firmware and + * have strict alignment requirements. This is one of them. + */ +typedef struct { + u8 bLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; + u16 bcdSpecVersion; + u32 dwClockFrequency; + u32 dwClockUpdateRes; + u8 bCapabilities; + u32 dwDeviceRegistersLocation; + u32 dwHostMemoryRegion; + u32 dwHostMemoryRegionSize; + u32 dwHostHibernatMemRegion; + u32 dwHostHibernatMemRegionSize; +} __attribute__((packed)) tmComResHWDescr_t; + +/* This is DWORD aligned on windows but I can't find the right + * gcc syntax to match the binary data from the device. + * I've manually padded with Reserved[3] bytes to match the hardware, + * but this could break if GCC decies to pack in a different way. + */ +typedef struct { + u8 bLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; + u8 bFlags; + u8 bInterfaceType; + u8 bInterfaceId; + u8 bBaseInterface; + u8 bInterruptId; + u8 bDebugInterruptId; + u8 BARLocation; + u8 Reserved[3]; +} tmComResInterfaceDescr_t; + +typedef struct { + u64 CommandRing; + u64 ResponseRing; + u32 CommandWrite; + u32 CommandRead; + u32 ResponseWrite; + u32 ResponseRead; +} tmComResBusDescr_t; + +typedef enum { + NONE = 0, + TYPE_BUS_PCI = 1, + TYPE_BUS_PCIe = 2, + TYPE_BUS_USB = 3, + TYPE_BUS_I2C = 4 +} tmBusType_t; + +typedef struct { + tmBusType_t Type; + u16 m_wMaxReqSize; + u8 *m_pdwSetRing; + u32 m_dwSizeSetRing; + u8 *m_pdwGetRing; + u32 m_dwSizeGetRing; + u32 *m_pdwSetWritePos; + u32 *m_pdwSetReadPos; + u32 *m_pdwGetWritePos; + u32 *m_pdwGetReadPos; + + /* All access is protected */ + struct mutex lock; + +} tmComResBusInfo_t; + +typedef struct { + u8 id; + u8 flags; + u16 size; + u32 command; + u16 controlselector; + u8 seqno; +} __attribute__((packed)) tmComResInfo_t; + +typedef enum { + SET_CUR = 0x01, + GET_CUR = 0x81, + GET_MIN = 0x82, + GET_MAX = 0x83, + GET_RES = 0x84, + GET_LEN = 0x85, + GET_INFO = 0x86, + GET_DEF = 0x87 +} tmComResCmd_t; + +struct cmd { + u8 seqno; + u32 inuse; + u32 timeout; + u32 signalled; + struct mutex lock; + wait_queue_head_t wait; +}; + +typedef struct { + u32 pathid; + u32 size; + void *descriptor; +} tmDescriptor_t; + +typedef struct { + u8 len; + u8 type; + u8 subtype; + u8 unitid; +} __attribute__((packed)) tmComResDescrHeader_t; + +typedef struct { + u8 len; + u8 type; + u8 subtype; + u8 unitid; + u32 devicetype; + u16 deviceid; + u32 numgpiopins; + u8 numgpiogroups; + u8 controlsize; +} __attribute__((packed)) tmComResExtDevDescrHeader_t; + +typedef struct { + u32 pin; + u8 state; +} __attribute__((packed)) tmComResGPIO_t; + +typedef struct { + u8 len; + u8 type; + u8 subtype; + u8 pathid; +} __attribute__((packed)) tmComResPathDescrHeader_t; + +/* terminaltype */ +typedef enum { + ITT_ANTENNA = 0x0203, + LINE_CONNECTOR = 0x0603, + SPDIF_CONNECTOR = 0x0605, + COMPOSITE_CONNECTOR = 0x0401, + SVIDEO_CONNECTOR = 0x0402, + COMPONENT_CONNECTOR = 0x0403, + STANDARD_DMA = 0xF101 +} tmComResTermType_t; + +typedef struct { + u8 len; + u8 type; + u8 subtype; + u8 terminalid; + u16 terminaltype; + u8 assocterminal; + u8 iterminal; + u8 controlsize; +} __attribute__((packed)) tmComResAntTermDescrHeader_t; + +typedef struct { + u8 len; + u8 type; + u8 subtype; + u8 unitid; + u8 sourceid; + u8 iunit; + u32 tuningstandards; + u8 controlsize; + u32 controls; +} __attribute__((packed)) tmComResTunerDescrHeader_t; + +typedef enum { + /* the buffer does not contain any valid data */ + TM_BUFFER_FLAG_EMPTY, + + /* the buffer is filled with valid data */ + TM_BUFFER_FLAG_DONE, + + /* the buffer is the dummy buffer - TODO??? */ + TM_BUFFER_FLAG_DUMMY_BUFFER +} tmBufferFlag_t; + +typedef struct { + u64 *pagetablevirt; + u64 pagetablephys; + u16 offset; + u8 *context; + u64 timestamp; + tmBufferFlag_t BufferFlag_t; + u32 lostbuffers; + u32 validbuffers; + u64 *dummypagevirt; + u64 dummypagephys; + u64 *addressvirt; +} tmBuffer_t; + +typedef struct { + u32 bitspersample; + u32 samplesperline; + u32 numberoflines; + u32 pitch; + u32 linethreshold; + u64 **pagetablelistvirt; + u64 *pagetablelistphys; + u32 numpagetables; + u32 numpagetableentries; +} tmHWStreamParameters_t; + +typedef struct { + tmHWStreamParameters_t HWStreamParameters_t; + u64 qwDummyPageTablePhys; + u64 *pDummyPageTableVirt; +} tmStreamParameters_t; + +typedef struct { + u8 len; + u8 type; + u8 subtyle; + u8 unitid; + u16 terminaltype; + u8 assocterminal; + u8 sourceid; + u8 iterminal; + u32 BARLocation; + u8 flags; + u8 interruptid; + u8 buffercount; + u8 metadatasize; + u8 numformats; + u8 controlsize; +} __attribute__((packed)) tmComResDMATermDescrHeader_t; + +/* + * + * Description: + * This is the transport stream format header. + * + * Settings: + * bLength - The size of this descriptor in bytes. + * bDescriptorType - CS_INTERFACE. + * bDescriptorSubtype - VS_FORMAT_MPEG2TS descriptor subtype. + * bFormatIndex - A non-zero constant that uniquely identifies the + * format. + * bDataOffset - Offset to TSP packet within MPEG-2 TS transport + * stride, in bytes. + * bPacketLength - Length of TSP packet, in bytes (typically 188). + * bStrideLength - Length of MPEG-2 TS transport stride. + * guidStrideFormat - A Globally Unique Identifier indicating the + * format of the stride data (if any). Set to zeros + * if there is no Stride Data, or if the Stride + * Data is to be ignored by the application. + * + */ +typedef struct { + u8 len; + u8 type; + u8 subtype; + u8 bFormatIndex; + u8 bDataOffset; + u8 bPacketLength; + u8 bStrideLength; + u8 guidStrideFormat[16]; +} __attribute__((packed)) tmComResTSFormatDescrHeader_t; + diff --git a/drivers/media/video/saa7164/saa7164.h b/drivers/media/video/saa7164/saa7164.h new file mode 100644 index 000000000000..6753008a9c9b --- /dev/null +++ b/drivers/media/video/saa7164/saa7164.h @@ -0,0 +1,400 @@ +/* + * Driver for the NXP SAA7164 PCIe bridge + * + * Copyright (c) 2009 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + Driver architecture + ******************* + + saa7164_core.c/buffer.c/cards.c/i2c.c/dvb.c + | : Standard Linux driver framework for creating + | : exposing and managing interfaces to the rest + | : of the kernel or userland. Also uses _fw.c to load + | : firmware direct into the PCIe bus, bypassing layers. + V + saa7164_api..() : Translate kernel specific functions/features + | : into command buffers. + V + saa7164_cmd..() : Manages the flow of command packets on/off, + | : the bus. Deal with bus errors, timeouts etc. + V + saa7164_bus..() : Manage a read/write memory ring buffer in the + | : PCIe Address space. + | + | saa7164_fw...() : Load any frimware + | | : direct into the device + V V + <- ----------------- PCIe address space -------------------- -> +*/ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "saa7164-reg.h" +#include "saa7164-types.h" + +#include +#include + +#define SAA7164_MAXBOARDS 8 + +#define UNSET (-1U) +#define SAA7164_BOARD_NOAUTO UNSET +#define SAA7164_BOARD_UNKNOWN 0 +#define SAA7164_BOARD_UNKNOWN_REV2 1 +#define SAA7164_BOARD_UNKNOWN_REV3 2 +#define SAA7164_BOARD_HAUPPAUGE_HVR2250 3 +#define SAA7164_BOARD_HAUPPAUGE_HVR2200 4 +#define SAA7164_BOARD_HAUPPAUGE_HVR2200_2 5 +#define SAA7164_BOARD_HAUPPAUGE_HVR2200_3 6 +#define SAA7164_BOARD_HAUPPAUGE_HVR2250_2 7 +#define SAA7164_BOARD_HAUPPAUGE_HVR2250_3 8 + +#define SAA7164_MAX_UNITS 8 +#define SAA7164_TS_NUMBER_OF_LINES 312 +#define SAA7164_PT_ENTRIES 16 /* (312 * 188) / 4096 */ + +#define DBGLVL_FW 4 +#define DBGLVL_DVB 8 +#define DBGLVL_I2C 16 +#define DBGLVL_API 32 +#define DBGLVL_CMD 64 +#define DBGLVL_BUS 128 +#define DBGLVL_IRQ 256 +#define DBGLVL_BUF 512 + +enum port_t { + SAA7164_MPEG_UNDEFINED = 0, + SAA7164_MPEG_DVB, +}; + +enum saa7164_i2c_bus_nr { + SAA7164_I2C_BUS_0 = 0, + SAA7164_I2C_BUS_1, + SAA7164_I2C_BUS_2, +}; + +enum saa7164_buffer_flags { + SAA7164_BUFFER_UNDEFINED = 0, + SAA7164_BUFFER_FREE, + SAA7164_BUFFER_BUSY, + SAA7164_BUFFER_FULL +}; + +enum saa7164_unit_type { + SAA7164_UNIT_UNDEFINED = 0, + SAA7164_UNIT_DIGITAL_DEMODULATOR, + SAA7164_UNIT_ANALOG_DEMODULATOR, + SAA7164_UNIT_TUNER, + SAA7164_UNIT_EEPROM, + SAA7164_UNIT_ZILOG_IRBLASTER, + SAA7164_UNIT_ENCODER, +}; + +/* The PCIe bridge doesn't grant direct access to i2c. + * Instead, you address i2c devices using a uniqely + * allocated 'unitid' value via a messaging API. This + * is a problem. The kernel and existing demod/tuner + * drivers expect to talk 'i2c', so we have to maintain + * a translation layer, and a series of functions to + * convert i2c bus + device address into a unit id. + */ +struct saa7164_unit { + enum saa7164_unit_type type; + u8 id; + char *name; + enum saa7164_i2c_bus_nr i2c_bus_nr; + u8 i2c_bus_addr; + u8 i2c_reg_len; +}; + +struct saa7164_board { + char *name; + enum port_t porta, portb; + enum { + SAA7164_CHIP_UNDEFINED = 0, + SAA7164_CHIP_REV2, + SAA7164_CHIP_REV3, + } chiprev; + struct saa7164_unit unit[SAA7164_MAX_UNITS]; +}; + +struct saa7164_subid { + u16 subvendor; + u16 subdevice; + u32 card; +}; + +struct saa7164_fw_status { + + /* RISC Core details */ + u32 status; + u32 mode; + u32 spec; + u32 inst; + u32 cpuload; + u32 remainheap; + + /* Firmware version */ + u32 version; + u32 major; + u32 sub; + u32 rel; + u32 buildnr; +}; + +struct saa7164_dvb { + struct mutex lock; + struct dvb_adapter adapter; + struct dvb_frontend *frontend; + struct dvb_demux demux; + struct dmxdev dmxdev; + struct dmx_frontend fe_hw; + struct dmx_frontend fe_mem; + struct dvb_net net; + int feeding; +}; + +struct saa7164_i2c { + struct saa7164_dev *dev; + + enum saa7164_i2c_bus_nr nr; + + /* I2C I/O */ + struct i2c_adapter i2c_adap; + struct i2c_algo_bit_data i2c_algo; + struct i2c_client i2c_client; + u32 i2c_rc; +}; + +struct saa7164_tsport; + +struct saa7164_buffer { + struct list_head list; + + u32 nr; + + struct saa7164_tsport *port; + + /* Hardware Specific */ + /* PCI Memory allocations */ + enum saa7164_buffer_flags flags; /* Free, Busy, Full */ + + /* A block of page align PCI memory */ + u32 pci_size; /* PCI allocation size in bytes */ + u64 *cpu; /* Virtual address */ + dma_addr_t dma; /* Physical address */ + + /* A page table that splits the block into a number of entries */ + u32 pt_size; /* PCI allocation size in bytes */ + u64 *pt_cpu; /* Virtual address */ + dma_addr_t pt_dma; /* Physical address */ +}; + +struct saa7164_tsport { + + struct saa7164_dev *dev; + int nr; + enum port_t type; + + struct saa7164_dvb dvb; + + /* HW related stream parameters */ + tmHWStreamParameters_t hw_streamingparams; + + /* DMA configuration values, is seeded during initialization */ + tmComResDMATermDescrHeader_t hwcfg; + + /* hardware specific registers */ + u32 bufcounter; + u32 pitch; + u32 bufsize; + u32 bufoffset; + u32 bufptr32l; + u32 bufptr32h; + u64 bufptr64; + + u32 numpte; /* Number of entries in array, only valid in head */ + struct mutex dmaqueue_lock; + struct mutex dummy_dmaqueue_lock; + struct saa7164_buffer dmaqueue; + struct saa7164_buffer dummy_dmaqueue; + +}; + +struct saa7164_dev { + struct list_head devlist; + atomic_t refcount; + + /* pci stuff */ + struct pci_dev *pci; + unsigned char pci_rev, pci_lat; + int pci_bus, pci_slot; + u32 __iomem *lmmio; + u8 __iomem *bmmio; + u32 __iomem *lmmio2; + u8 __iomem *bmmio2; + int pci_irqmask; + + /* board details */ + int nr; + int hwrevision; + u32 board; + char name[32]; + + /* firmware status */ + struct saa7164_fw_status fw_status; + + tmComResHWDescr_t hwdesc; + tmComResInterfaceDescr_t intfdesc; + tmComResBusDescr_t busdesc; + + tmComResBusInfo_t bus; + + /* Interrupt status and ack registers */ + u32 int_status; + u32 int_ack; + + struct cmd cmds[SAA_CMD_MAX_MSG_UNITS]; + struct mutex lock; + + /* I2c related */ + struct saa7164_i2c i2c_bus[3]; + + /* Transport related */ + struct saa7164_tsport ts1, ts2; + + /* Deferred command/api interrupts handling */ + struct work_struct workcmd; + +}; + +extern struct list_head saa7164_devlist; +extern unsigned int waitsecs; + +/* ----------------------------------------------------------- */ +/* saa7164-core.c */ +void saa7164_dumpregs(struct saa7164_dev *dev, u32 addr); +void saa7164_dumphex16(struct saa7164_dev *dev, u8 *buf, int len); +void saa7164_getfirmwarestatus(struct saa7164_dev *dev); +u32 saa7164_getcurrentfirmwareversion(struct saa7164_dev *dev); + +/* ----------------------------------------------------------- */ +/* saa7164-fw.c */ +int saa7164_downloadfirmware(struct saa7164_dev *dev); + +/* ----------------------------------------------------------- */ +/* saa7164-i2c.c */ +extern int saa7164_i2c_register(struct saa7164_i2c *bus); +extern int saa7164_i2c_unregister(struct saa7164_i2c *bus); +extern void saa7164_call_i2c_clients(struct saa7164_i2c *bus, + unsigned int cmd, void *arg); + +/* ----------------------------------------------------------- */ +/* saa7164-bus.c */ +int saa7164_bus_setup(struct saa7164_dev *dev); +void saa7164_bus_dump(struct saa7164_dev *dev); +int saa7164_bus_set(struct saa7164_dev *dev, tmComResInfo_t* msg, void *buf); +int saa7164_bus_get(struct saa7164_dev *dev, tmComResInfo_t* msg, + void *buf, int peekonly); + +/* ----------------------------------------------------------- */ +/* saa7164-cmd.c */ +int saa7164_cmd_send(struct saa7164_dev *dev, + u8 id, tmComResCmd_t command, u16 controlselector, + u16 size, void *buf); +void saa7164_cmd_signal(struct saa7164_dev *dev, u8 seqno); +int saa7164_irq_dequeue(struct saa7164_dev *dev); + +/* ----------------------------------------------------------- */ +/* saa7164-api.c */ +int saa7164_api_get_fw_version(struct saa7164_dev *dev, u32 *version); +int saa7164_api_enum_subdevs(struct saa7164_dev *dev); +int saa7164_api_i2c_read(struct saa7164_i2c *bus, u8 addr, u32 reglen, u8 *reg, + u32 datalen, u8 *data); +int saa7164_api_i2c_write(struct saa7164_i2c *bus, u8 addr, + u32 datalen, u8 *data); +int saa7164_api_dif_write(struct saa7164_i2c *bus, u8 addr, + u32 datalen, u8 *data); +int saa7164_api_read_eeprom(struct saa7164_dev *dev, u8 *buf, int buflen); +int saa7164_api_set_gpiobit(struct saa7164_dev *dev, u8 unitid, u8 pin); +int saa7164_api_clear_gpiobit(struct saa7164_dev *dev, u8 unitid, u8 pin); +int saa7164_api_transition_port(struct saa7164_tsport *port, u8 mode); + +/* ----------------------------------------------------------- */ +/* saa7164-cards.c */ +extern struct saa7164_board saa7164_boards[]; +extern const unsigned int saa7164_bcount; + +extern struct saa7164_subid saa7164_subids[]; +extern const unsigned int saa7164_idcount; + +extern void saa7164_card_list(struct saa7164_dev *dev); +extern void saa7164_gpio_setup(struct saa7164_dev *dev); +extern void saa7164_card_setup(struct saa7164_dev *dev); + +extern int saa7164_i2caddr_to_reglen(struct saa7164_i2c *bus, int addr); +extern int saa7164_i2caddr_to_unitid(struct saa7164_i2c *bus, int addr); +extern char *saa7164_unitid_name(struct saa7164_dev *dev, u8 unitid); + +/* ----------------------------------------------------------- */ +/* saa7164-dvb.c */ +extern int saa7164_dvb_register(struct saa7164_tsport *port); +extern int saa7164_dvb_unregister(struct saa7164_tsport *port); + +/* ----------------------------------------------------------- */ +/* saa7164-buffer.c */ +extern struct saa7164_buffer *saa7164_buffer_alloc(struct saa7164_tsport *port, + u32 len); +extern int saa7164_buffer_dealloc(struct saa7164_tsport *port, + struct saa7164_buffer *buf); + +/* ----------------------------------------------------------- */ + +extern unsigned int debug; +#define dprintk(level, fmt, arg...)\ + do { if (debug & level)\ + printk(KERN_DEBUG "%s: " fmt, dev->name, ## arg);\ + } while (0) + +#define log_warn(fmt, arg...)\ + do { \ + printk(KERN_WARNING "%s: " fmt, dev->name, ## arg);\ + } while (0) + +#define log_err(fmt, arg...)\ + do { \ + printk(KERN_ERROR "%s: " fmt, dev->name, ## arg);\ + } while (0) + +#define saa7164_readl(reg) readl(dev->lmmio + ((reg) >> 2)) +#define saa7164_writel(reg, value) writel((value), dev->lmmio + ((reg) >> 2)) + + +#define saa7164_readb(reg) readl(dev->bmmio + (reg)) +#define saa7164_writeb(reg, value) writel((value), dev->bmmio + (reg)) + diff --git a/drivers/media/video/sh_mobile_ceu_camera.c b/drivers/media/video/sh_mobile_ceu_camera.c index 61c47b824083..5ab7c5aefd62 100644 --- a/drivers/media/video/sh_mobile_ceu_camera.c +++ b/drivers/media/video/sh_mobile_ceu_camera.c @@ -74,6 +74,13 @@ #define CDBYR2 0x98 /* Capture data bottom-field address Y register 2 */ #define CDBCR2 0x9c /* Capture data bottom-field address C register 2 */ +#undef DEBUG_GEOMETRY +#ifdef DEBUG_GEOMETRY +#define dev_geo dev_info +#else +#define dev_geo dev_dbg +#endif + /* per video frame buffer */ struct sh_mobile_ceu_buffer { struct videobuf_buffer vb; /* v4l buffer must be first */ @@ -92,10 +99,21 @@ struct sh_mobile_ceu_dev { spinlock_t lock; struct list_head capture; struct videobuf_buffer *active; - int is_interlaced; struct sh_mobile_ceu_info *pdata; + u32 cflcr; + + unsigned int is_interlaced:1; + unsigned int image_mode:1; + unsigned int is_16bit:1; +}; + +struct sh_mobile_ceu_cam { + struct v4l2_rect ceu_rect; + unsigned int cam_width; + unsigned int cam_height; + const struct soc_camera_data_format *extra_fmt; const struct soc_camera_data_format *camera_fmt; }; @@ -146,7 +164,8 @@ static int sh_mobile_ceu_videobuf_setup(struct videobuf_queue *vq, struct sh_mobile_ceu_dev *pcdev = ici->priv; int bytes_per_pixel = (icd->current_fmt->depth + 7) >> 3; - *size = PAGE_ALIGN(icd->width * icd->height * bytes_per_pixel); + *size = PAGE_ALIGN(icd->user_width * icd->user_height * + bytes_per_pixel); if (0 == *count) *count = 2; @@ -156,7 +175,7 @@ static int sh_mobile_ceu_videobuf_setup(struct videobuf_queue *vq, (*count)--; } - dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); + dev_dbg(icd->dev.parent, "count=%d, size=%d\n", *count, *size); return 0; } @@ -165,8 +184,9 @@ static void free_buffer(struct videobuf_queue *vq, struct sh_mobile_ceu_buffer *buf) { struct soc_camera_device *icd = vq->priv_data; + struct device *dev = icd->dev.parent; - dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %zd\n", __func__, + dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %zd\n", __func__, &buf->vb, buf->vb.baddr, buf->vb.bsize); if (in_interrupt()) @@ -174,7 +194,7 @@ static void free_buffer(struct videobuf_queue *vq, videobuf_waiton(&buf->vb, 0, 0); videobuf_dma_contig_free(vq, &buf->vb); - dev_dbg(&icd->dev, "%s freed\n", __func__); + dev_dbg(dev, "%s freed\n", __func__); buf->vb.state = VIDEOBUF_NEEDS_INIT; } @@ -205,7 +225,7 @@ static void sh_mobile_ceu_capture(struct sh_mobile_ceu_dev *pcdev) phys_addr_top = videobuf_to_dma_contig(pcdev->active); ceu_write(pcdev, CDAYR, phys_addr_top); if (pcdev->is_interlaced) { - phys_addr_bottom = phys_addr_top + icd->width; + phys_addr_bottom = phys_addr_top + icd->user_width; ceu_write(pcdev, CDBYR, phys_addr_bottom); } @@ -214,10 +234,12 @@ static void sh_mobile_ceu_capture(struct sh_mobile_ceu_dev *pcdev) case V4L2_PIX_FMT_NV21: case V4L2_PIX_FMT_NV16: case V4L2_PIX_FMT_NV61: - phys_addr_top += icd->width * icd->height; + phys_addr_top += icd->user_width * + icd->user_height; ceu_write(pcdev, CDACR, phys_addr_top); if (pcdev->is_interlaced) { - phys_addr_bottom = phys_addr_top + icd->width; + phys_addr_bottom = phys_addr_top + + icd->user_width; ceu_write(pcdev, CDBCR, phys_addr_bottom); } } @@ -236,7 +258,7 @@ static int sh_mobile_ceu_videobuf_prepare(struct videobuf_queue *vq, buf = container_of(vb, struct sh_mobile_ceu_buffer, vb); - dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %zd\n", __func__, + dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %zd\n", __func__, vb, vb->baddr, vb->bsize); /* Added list head initialization on alloc */ @@ -251,12 +273,12 @@ static int sh_mobile_ceu_videobuf_prepare(struct videobuf_queue *vq, BUG_ON(NULL == icd->current_fmt); if (buf->fmt != icd->current_fmt || - vb->width != icd->width || - vb->height != icd->height || + vb->width != icd->user_width || + vb->height != icd->user_height || vb->field != field) { buf->fmt = icd->current_fmt; - vb->width = icd->width; - vb->height = icd->height; + vb->width = icd->user_width; + vb->height = icd->user_height; vb->field = field; vb->state = VIDEOBUF_NEEDS_INIT; } @@ -289,7 +311,7 @@ static void sh_mobile_ceu_videobuf_queue(struct videobuf_queue *vq, struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); struct sh_mobile_ceu_dev *pcdev = ici->priv; - dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %zd\n", __func__, + dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %zd\n", __func__, vb, vb->baddr, vb->bsize); vb->state = VIDEOBUF_QUEUED; @@ -304,6 +326,27 @@ static void sh_mobile_ceu_videobuf_queue(struct videobuf_queue *vq, static void sh_mobile_ceu_videobuf_release(struct videobuf_queue *vq, struct videobuf_buffer *vb) { + struct soc_camera_device *icd = vq->priv_data; + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct sh_mobile_ceu_dev *pcdev = ici->priv; + unsigned long flags; + + spin_lock_irqsave(&pcdev->lock, flags); + + if (pcdev->active == vb) { + /* disable capture (release DMA buffer), reset */ + ceu_write(pcdev, CAPSR, 1 << 16); + pcdev->active = NULL; + } + + if ((vb->state == VIDEOBUF_ACTIVE || vb->state == VIDEOBUF_QUEUED) && + !list_empty(&vb->queue)) { + vb->state = VIDEOBUF_ERROR; + list_del_init(&vb->queue); + } + + spin_unlock_irqrestore(&pcdev->lock, flags); + free_buffer(vq, container_of(vb, struct sh_mobile_ceu_buffer, vb)); } @@ -323,6 +366,10 @@ static irqreturn_t sh_mobile_ceu_irq(int irq, void *data) spin_lock_irqsave(&pcdev->lock, flags); vb = pcdev->active; + if (!vb) + /* Stale interrupt from a released buffer */ + goto out; + list_del_init(&vb->queue); if (!list_empty(&pcdev->capture)) @@ -337,6 +384,8 @@ static irqreturn_t sh_mobile_ceu_irq(int irq, void *data) do_gettimeofday(&vb->ts); vb->field_count++; wake_up(&vb->done); + +out: spin_unlock_irqrestore(&pcdev->lock, flags); return IRQ_HANDLED; @@ -347,28 +396,23 @@ static int sh_mobile_ceu_add_device(struct soc_camera_device *icd) { struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); struct sh_mobile_ceu_dev *pcdev = ici->priv; - int ret = -EBUSY; if (pcdev->icd) - goto err; + return -EBUSY; - dev_info(&icd->dev, + dev_info(icd->dev.parent, "SuperH Mobile CEU driver attached to camera %d\n", icd->devnum); - ret = icd->ops->init(icd); - if (ret) - goto err; - - pm_runtime_get_sync(ici->dev); + clk_enable(pcdev->clk); ceu_write(pcdev, CAPSR, 1 << 16); /* reset */ while (ceu_read(pcdev, CSTSR) & 1) msleep(1); pcdev->icd = icd; -err: - return ret; + + return 0; } /* Called with .video_lock held */ @@ -394,25 +438,151 @@ static void sh_mobile_ceu_remove_device(struct soc_camera_device *icd) } spin_unlock_irqrestore(&pcdev->lock, flags); - pm_runtime_put_sync(ici->dev); + clk_disable(pcdev->clk); - icd->ops->release(icd); - - dev_info(&icd->dev, + dev_info(icd->dev.parent, "SuperH Mobile CEU driver detached from camera %d\n", icd->devnum); pcdev->icd = NULL; } +/* + * See chapter 29.4.12 "Capture Filter Control Register (CFLCR)" + * in SH7722 Hardware Manual + */ +static unsigned int size_dst(unsigned int src, unsigned int scale) +{ + unsigned int mant_pre = scale >> 12; + if (!src || !scale) + return src; + return ((mant_pre + 2 * (src - 1)) / (2 * mant_pre) - 1) * + mant_pre * 4096 / scale + 1; +} + +static u16 calc_scale(unsigned int src, unsigned int *dst) +{ + u16 scale; + + if (src == *dst) + return 0; + + scale = (src * 4096 / *dst) & ~7; + + while (scale > 4096 && size_dst(src, scale) < *dst) + scale -= 8; + + *dst = size_dst(src, scale); + + return scale; +} + +/* rect is guaranteed to not exceed the scaled camera rectangle */ +static void sh_mobile_ceu_set_rect(struct soc_camera_device *icd, + unsigned int out_width, + unsigned int out_height) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct sh_mobile_ceu_cam *cam = icd->host_priv; + struct v4l2_rect *rect = &cam->ceu_rect; + struct sh_mobile_ceu_dev *pcdev = ici->priv; + unsigned int height, width, cdwdr_width, in_width, in_height; + unsigned int left_offset, top_offset; + u32 camor; + + dev_dbg(icd->dev.parent, "Crop %ux%u@%u:%u\n", + rect->width, rect->height, rect->left, rect->top); + + left_offset = rect->left; + top_offset = rect->top; + + if (pcdev->image_mode) { + in_width = rect->width; + if (!pcdev->is_16bit) { + in_width *= 2; + left_offset *= 2; + } + width = cdwdr_width = out_width; + } else { + unsigned int w_factor = (icd->current_fmt->depth + 7) >> 3; + + width = out_width * w_factor / 2; + + if (!pcdev->is_16bit) + w_factor *= 2; + + in_width = rect->width * w_factor / 2; + left_offset = left_offset * w_factor / 2; + + cdwdr_width = width * 2; + } + + height = out_height; + in_height = rect->height; + if (pcdev->is_interlaced) { + height /= 2; + in_height /= 2; + top_offset /= 2; + cdwdr_width *= 2; + } + + /* Set CAMOR, CAPWR, CFSZR, take care of CDWDR */ + camor = left_offset | (top_offset << 16); + + dev_geo(icd->dev.parent, + "CAMOR 0x%x, CAPWR 0x%x, CFSZR 0x%x, CDWDR 0x%x\n", camor, + (in_height << 16) | in_width, (height << 16) | width, + cdwdr_width); + + ceu_write(pcdev, CAMOR, camor); + ceu_write(pcdev, CAPWR, (in_height << 16) | in_width); + ceu_write(pcdev, CFSZR, (height << 16) | width); + ceu_write(pcdev, CDWDR, cdwdr_width); +} + +static u32 capture_save_reset(struct sh_mobile_ceu_dev *pcdev) +{ + u32 capsr = ceu_read(pcdev, CAPSR); + ceu_write(pcdev, CAPSR, 1 << 16); /* reset, stop capture */ + return capsr; +} + +static void capture_restore(struct sh_mobile_ceu_dev *pcdev, u32 capsr) +{ + unsigned long timeout = jiffies + 10 * HZ; + + /* + * Wait until the end of the current frame. It can take a long time, + * but if it has been aborted by a CAPSR reset, it shoule exit sooner. + */ + while ((ceu_read(pcdev, CSTSR) & 1) && time_before(jiffies, timeout)) + msleep(1); + + if (time_after(jiffies, timeout)) { + dev_err(pcdev->ici.v4l2_dev.dev, + "Timeout waiting for frame end! Interface problem?\n"); + return; + } + + /* Wait until reset clears, this shall not hang... */ + while (ceu_read(pcdev, CAPSR) & (1 << 16)) + udelay(10); + + /* Anything to restore? */ + if (capsr & ~(1 << 16)) + ceu_write(pcdev, CAPSR, capsr); +} + static int sh_mobile_ceu_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) { struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); struct sh_mobile_ceu_dev *pcdev = ici->priv; - int ret, buswidth, width, height, cfszr_width, cdwdr_width; + int ret; unsigned long camera_flags, common_flags, value; - int yuv_mode, yuv_lineskip; + int yuv_lineskip; + struct sh_mobile_ceu_cam *cam = icd->host_priv; + u32 capsr = capture_save_reset(pcdev); camera_flags = icd->ops->query_bus_param(icd); common_flags = soc_camera_bus_param_compatible(camera_flags, @@ -426,10 +596,10 @@ static int sh_mobile_ceu_set_bus_param(struct soc_camera_device *icd, switch (common_flags & SOCAM_DATAWIDTH_MASK) { case SOCAM_DATAWIDTH_8: - buswidth = 8; + pcdev->is_16bit = 0; break; case SOCAM_DATAWIDTH_16: - buswidth = 16; + pcdev->is_16bit = 1; break; default: return -EINVAL; @@ -439,7 +609,7 @@ static int sh_mobile_ceu_set_bus_param(struct soc_camera_device *icd, ceu_write(pcdev, CRCMPR, 0); value = 0x00000010; /* data fetch by default */ - yuv_mode = yuv_lineskip = 0; + yuv_lineskip = 0; switch (icd->current_fmt->fourcc) { case V4L2_PIX_FMT_NV12: @@ -448,8 +618,7 @@ static int sh_mobile_ceu_set_bus_param(struct soc_camera_device *icd, /* fall-through */ case V4L2_PIX_FMT_NV16: case V4L2_PIX_FMT_NV61: - yuv_mode = 1; - switch (pcdev->camera_fmt->fourcc) { + switch (cam->camera_fmt->fourcc) { case V4L2_PIX_FMT_UYVY: value = 0x00000000; /* Cb0, Y0, Cr0, Y1 */ break; @@ -473,36 +642,16 @@ static int sh_mobile_ceu_set_bus_param(struct soc_camera_device *icd, value |= common_flags & SOCAM_VSYNC_ACTIVE_LOW ? 1 << 1 : 0; value |= common_flags & SOCAM_HSYNC_ACTIVE_LOW ? 1 << 0 : 0; - value |= buswidth == 16 ? 1 << 12 : 0; + value |= pcdev->is_16bit ? 1 << 12 : 0; ceu_write(pcdev, CAMCR, value); ceu_write(pcdev, CAPCR, 0x00300000); ceu_write(pcdev, CAIFR, pcdev->is_interlaced ? 0x101 : 0); + sh_mobile_ceu_set_rect(icd, icd->user_width, icd->user_height); mdelay(1); - if (yuv_mode) { - width = icd->width * 2; - width = buswidth == 16 ? width / 2 : width; - cfszr_width = cdwdr_width = icd->width; - } else { - width = icd->width * ((icd->current_fmt->depth + 7) >> 3); - width = buswidth == 16 ? width / 2 : width; - cfszr_width = buswidth == 8 ? width / 2 : width; - cdwdr_width = buswidth == 16 ? width * 2 : width; - } - - height = icd->height; - if (pcdev->is_interlaced) { - height /= 2; - cdwdr_width *= 2; - } - - ceu_write(pcdev, CAMOR, 0); - ceu_write(pcdev, CAPWR, (height << 16) | width); - ceu_write(pcdev, CFLCR, 0); /* no scaling */ - ceu_write(pcdev, CFSZR, (height << 16) | cfszr_width); - ceu_write(pcdev, CLFCR, 0); /* no lowpass filter */ + ceu_write(pcdev, CFLCR, pcdev->cflcr); /* A few words about byte order (observed in Big Endian mode) * @@ -521,10 +670,15 @@ static int sh_mobile_ceu_set_bus_param(struct soc_camera_device *icd, value &= ~0x00000010; /* convert 4:2:2 -> 4:2:0 */ ceu_write(pcdev, CDOCR, value); - - ceu_write(pcdev, CDWDR, cdwdr_width); ceu_write(pcdev, CFWCR, 0); /* keep "datafetch firewall" disabled */ + dev_dbg(icd->dev.parent, "S_FMT successful for %c%c%c%c %ux%u\n", + pixfmt & 0xff, (pixfmt >> 8) & 0xff, + (pixfmt >> 16) & 0xff, (pixfmt >> 24) & 0xff, + icd->user_width, icd->user_height); + + capture_restore(pcdev, capsr); + /* not in bundle mode: skip CBDSR, CDAYR2, CDACR2, CDBYR2, CDBCR2 */ return 0; } @@ -574,24 +728,35 @@ static const struct soc_camera_data_format sh_mobile_ceu_formats[] = { static int sh_mobile_ceu_get_formats(struct soc_camera_device *icd, int idx, struct soc_camera_format_xlate *xlate) { - struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct device *dev = icd->dev.parent; int ret, k, n; int formats = 0; + struct sh_mobile_ceu_cam *cam; ret = sh_mobile_ceu_try_bus_param(icd); if (ret < 0) return 0; + if (!icd->host_priv) { + cam = kzalloc(sizeof(*cam), GFP_KERNEL); + if (!cam) + return -ENOMEM; + + icd->host_priv = cam; + } else { + cam = icd->host_priv; + } + /* Beginning of a pass */ if (!idx) - icd->host_priv = NULL; + cam->extra_fmt = NULL; switch (icd->formats[idx].fourcc) { case V4L2_PIX_FMT_UYVY: case V4L2_PIX_FMT_VYUY: case V4L2_PIX_FMT_YUYV: case V4L2_PIX_FMT_YVYU: - if (icd->host_priv) + if (cam->extra_fmt) goto add_single_format; /* @@ -603,7 +768,7 @@ static int sh_mobile_ceu_get_formats(struct soc_camera_device *icd, int idx, * the host_priv pointer and check whether the format you're * going to add now is already there. */ - icd->host_priv = (void *)sh_mobile_ceu_formats; + cam->extra_fmt = (void *)sh_mobile_ceu_formats; n = ARRAY_SIZE(sh_mobile_ceu_formats); formats += n; @@ -612,7 +777,7 @@ static int sh_mobile_ceu_get_formats(struct soc_camera_device *icd, int idx, xlate->cam_fmt = icd->formats + idx; xlate->buswidth = icd->formats[idx].depth; xlate++; - dev_dbg(ici->dev, "Providing format %s using %s\n", + dev_dbg(dev, "Providing format %s using %s\n", sh_mobile_ceu_formats[k].name, icd->formats[idx].name); } @@ -625,7 +790,7 @@ add_single_format: xlate->cam_fmt = icd->formats + idx; xlate->buswidth = icd->formats[idx].depth; xlate++; - dev_dbg(ici->dev, + dev_dbg(dev, "Providing format %s in pass-through mode\n", icd->formats[idx].name); } @@ -634,82 +799,714 @@ add_single_format: return formats; } +static void sh_mobile_ceu_put_formats(struct soc_camera_device *icd) +{ + kfree(icd->host_priv); + icd->host_priv = NULL; +} + +/* Check if any dimension of r1 is smaller than respective one of r2 */ +static bool is_smaller(struct v4l2_rect *r1, struct v4l2_rect *r2) +{ + return r1->width < r2->width || r1->height < r2->height; +} + +/* Check if r1 fails to cover r2 */ +static bool is_inside(struct v4l2_rect *r1, struct v4l2_rect *r2) +{ + return r1->left > r2->left || r1->top > r2->top || + r1->left + r1->width < r2->left + r2->width || + r1->top + r1->height < r2->top + r2->height; +} + +static unsigned int scale_down(unsigned int size, unsigned int scale) +{ + return (size * 4096 + scale / 2) / scale; +} + +static unsigned int scale_up(unsigned int size, unsigned int scale) +{ + return (size * scale + 2048) / 4096; +} + +static unsigned int calc_generic_scale(unsigned int input, unsigned int output) +{ + return (input * 4096 + output / 2) / output; +} + +static int client_g_rect(struct v4l2_subdev *sd, struct v4l2_rect *rect) +{ + struct v4l2_crop crop; + struct v4l2_cropcap cap; + int ret; + + crop.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + ret = v4l2_subdev_call(sd, video, g_crop, &crop); + if (!ret) { + *rect = crop.c; + return ret; + } + + /* Camera driver doesn't support .g_crop(), assume default rectangle */ + cap.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + ret = v4l2_subdev_call(sd, video, cropcap, &cap); + if (ret < 0) + return ret; + + *rect = cap.defrect; + + return ret; +} + +/* + * The common for both scaling and cropping iterative approach is: + * 1. try if the client can produce exactly what requested by the user + * 2. if (1) failed, try to double the client image until we get one big enough + * 3. if (2) failed, try to request the maximum image + */ +static int client_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *crop, + struct v4l2_crop *cam_crop) +{ + struct v4l2_rect *rect = &crop->c, *cam_rect = &cam_crop->c; + struct device *dev = sd->v4l2_dev->dev; + struct v4l2_cropcap cap; + int ret; + unsigned int width, height; + + v4l2_subdev_call(sd, video, s_crop, crop); + ret = client_g_rect(sd, cam_rect); + if (ret < 0) + return ret; + + /* + * Now cam_crop contains the current camera input rectangle, and it must + * be within camera cropcap bounds + */ + if (!memcmp(rect, cam_rect, sizeof(*rect))) { + /* Even if camera S_CROP failed, but camera rectangle matches */ + dev_dbg(dev, "Camera S_CROP successful for %ux%u@%u:%u\n", + rect->width, rect->height, rect->left, rect->top); + return 0; + } + + /* Try to fix cropping, that camera hasn't managed to set */ + dev_geo(dev, "Fix camera S_CROP for %ux%u@%u:%u to %ux%u@%u:%u\n", + cam_rect->width, cam_rect->height, + cam_rect->left, cam_rect->top, + rect->width, rect->height, rect->left, rect->top); + + /* We need sensor maximum rectangle */ + ret = v4l2_subdev_call(sd, video, cropcap, &cap); + if (ret < 0) + return ret; + + soc_camera_limit_side(&rect->left, &rect->width, cap.bounds.left, 2, + cap.bounds.width); + soc_camera_limit_side(&rect->top, &rect->height, cap.bounds.top, 4, + cap.bounds.height); + + /* + * Popular special case - some cameras can only handle fixed sizes like + * QVGA, VGA,... Take care to avoid infinite loop. + */ + width = max(cam_rect->width, 2); + height = max(cam_rect->height, 2); + + while (!ret && (is_smaller(cam_rect, rect) || + is_inside(cam_rect, rect)) && + (cap.bounds.width > width || cap.bounds.height > height)) { + + width *= 2; + height *= 2; + + cam_rect->width = width; + cam_rect->height = height; + + /* + * We do not know what capabilities the camera has to set up + * left and top borders. We could try to be smarter in iterating + * them, e.g., if camera current left is to the right of the + * target left, set it to the middle point between the current + * left and minimum left. But that would add too much + * complexity: we would have to iterate each border separately. + */ + if (cam_rect->left > rect->left) + cam_rect->left = cap.bounds.left; + + if (cam_rect->left + cam_rect->width < rect->left + rect->width) + cam_rect->width = rect->left + rect->width - + cam_rect->left; + + if (cam_rect->top > rect->top) + cam_rect->top = cap.bounds.top; + + if (cam_rect->top + cam_rect->height < rect->top + rect->height) + cam_rect->height = rect->top + rect->height - + cam_rect->top; + + v4l2_subdev_call(sd, video, s_crop, cam_crop); + ret = client_g_rect(sd, cam_rect); + dev_geo(dev, "Camera S_CROP %d for %ux%u@%u:%u\n", ret, + cam_rect->width, cam_rect->height, + cam_rect->left, cam_rect->top); + } + + /* S_CROP must not modify the rectangle */ + if (is_smaller(cam_rect, rect) || is_inside(cam_rect, rect)) { + /* + * The camera failed to configure a suitable cropping, + * we cannot use the current rectangle, set to max + */ + *cam_rect = cap.bounds; + v4l2_subdev_call(sd, video, s_crop, cam_crop); + ret = client_g_rect(sd, cam_rect); + dev_geo(dev, "Camera S_CROP %d for max %ux%u@%u:%u\n", ret, + cam_rect->width, cam_rect->height, + cam_rect->left, cam_rect->top); + } + + return ret; +} + +static int get_camera_scales(struct v4l2_subdev *sd, struct v4l2_rect *rect, + unsigned int *scale_h, unsigned int *scale_v) +{ + struct v4l2_format f; + int ret; + + f.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + ret = v4l2_subdev_call(sd, video, g_fmt, &f); + if (ret < 0) + return ret; + + *scale_h = calc_generic_scale(rect->width, f.fmt.pix.width); + *scale_v = calc_generic_scale(rect->height, f.fmt.pix.height); + + return 0; +} + +static int get_camera_subwin(struct soc_camera_device *icd, + struct v4l2_rect *cam_subrect, + unsigned int cam_hscale, unsigned int cam_vscale) +{ + struct sh_mobile_ceu_cam *cam = icd->host_priv; + struct v4l2_rect *ceu_rect = &cam->ceu_rect; + + if (!ceu_rect->width) { + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + struct device *dev = icd->dev.parent; + struct v4l2_format f; + struct v4l2_pix_format *pix = &f.fmt.pix; + int ret; + /* First time */ + + f.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + ret = v4l2_subdev_call(sd, video, g_fmt, &f); + if (ret < 0) + return ret; + + dev_geo(dev, "camera fmt %ux%u\n", pix->width, pix->height); + + if (pix->width > 2560) { + ceu_rect->width = 2560; + ceu_rect->left = (pix->width - 2560) / 2; + } else { + ceu_rect->width = pix->width; + ceu_rect->left = 0; + } + + if (pix->height > 1920) { + ceu_rect->height = 1920; + ceu_rect->top = (pix->height - 1920) / 2; + } else { + ceu_rect->height = pix->height; + ceu_rect->top = 0; + } + + dev_geo(dev, "initialised CEU rect %ux%u@%u:%u\n", + ceu_rect->width, ceu_rect->height, + ceu_rect->left, ceu_rect->top); + } + + cam_subrect->width = scale_up(ceu_rect->width, cam_hscale); + cam_subrect->left = scale_up(ceu_rect->left, cam_hscale); + cam_subrect->height = scale_up(ceu_rect->height, cam_vscale); + cam_subrect->top = scale_up(ceu_rect->top, cam_vscale); + + return 0; +} + +static int client_s_fmt(struct soc_camera_device *icd, struct v4l2_format *f, + bool ceu_can_scale) +{ + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + struct device *dev = icd->dev.parent; + struct v4l2_pix_format *pix = &f->fmt.pix; + unsigned int width = pix->width, height = pix->height, tmp_w, tmp_h; + unsigned int max_width, max_height; + struct v4l2_cropcap cap; + int ret; + + cap.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + ret = v4l2_subdev_call(sd, video, cropcap, &cap); + if (ret < 0) + return ret; + + max_width = min(cap.bounds.width, 2560); + max_height = min(cap.bounds.height, 1920); + + ret = v4l2_subdev_call(sd, video, s_fmt, f); + if (ret < 0) + return ret; + + dev_geo(dev, "camera scaled to %ux%u\n", pix->width, pix->height); + + if ((width == pix->width && height == pix->height) || !ceu_can_scale) + return 0; + + /* Camera set a format, but geometry is not precise, try to improve */ + tmp_w = pix->width; + tmp_h = pix->height; + + /* width <= max_width && height <= max_height - guaranteed by try_fmt */ + while ((width > tmp_w || height > tmp_h) && + tmp_w < max_width && tmp_h < max_height) { + tmp_w = min(2 * tmp_w, max_width); + tmp_h = min(2 * tmp_h, max_height); + pix->width = tmp_w; + pix->height = tmp_h; + ret = v4l2_subdev_call(sd, video, s_fmt, f); + dev_geo(dev, "Camera scaled to %ux%u\n", + pix->width, pix->height); + if (ret < 0) { + /* This shouldn't happen */ + dev_err(dev, "Client failed to set format: %d\n", ret); + return ret; + } + } + + return 0; +} + +/** + * @rect - camera cropped rectangle + * @sub_rect - CEU cropped rectangle, mapped back to camera input area + * @ceu_rect - on output calculated CEU crop rectangle + */ +static int client_scale(struct soc_camera_device *icd, struct v4l2_rect *rect, + struct v4l2_rect *sub_rect, struct v4l2_rect *ceu_rect, + struct v4l2_format *f, bool ceu_can_scale) +{ + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + struct sh_mobile_ceu_cam *cam = icd->host_priv; + struct device *dev = icd->dev.parent; + struct v4l2_format f_tmp = *f; + struct v4l2_pix_format *pix_tmp = &f_tmp.fmt.pix; + unsigned int scale_h, scale_v; + int ret; + + /* 5. Apply iterative camera S_FMT for camera user window. */ + ret = client_s_fmt(icd, &f_tmp, ceu_can_scale); + if (ret < 0) + return ret; + + dev_geo(dev, "5: camera scaled to %ux%u\n", + pix_tmp->width, pix_tmp->height); + + /* 6. Retrieve camera output window (g_fmt) */ + + /* unneeded - it is already in "f_tmp" */ + + /* 7. Calculate new camera scales. */ + ret = get_camera_scales(sd, rect, &scale_h, &scale_v); + if (ret < 0) + return ret; + + dev_geo(dev, "7: camera scales %u:%u\n", scale_h, scale_v); + + cam->cam_width = pix_tmp->width; + cam->cam_height = pix_tmp->height; + f->fmt.pix.width = pix_tmp->width; + f->fmt.pix.height = pix_tmp->height; + + /* + * 8. Calculate new CEU crop - apply camera scales to previously + * calculated "effective" crop. + */ + ceu_rect->left = scale_down(sub_rect->left, scale_h); + ceu_rect->width = scale_down(sub_rect->width, scale_h); + ceu_rect->top = scale_down(sub_rect->top, scale_v); + ceu_rect->height = scale_down(sub_rect->height, scale_v); + + dev_geo(dev, "8: new CEU rect %ux%u@%u:%u\n", + ceu_rect->width, ceu_rect->height, + ceu_rect->left, ceu_rect->top); + + return 0; +} + +/* Get combined scales */ +static int get_scales(struct soc_camera_device *icd, + unsigned int *scale_h, unsigned int *scale_v) +{ + struct sh_mobile_ceu_cam *cam = icd->host_priv; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + struct v4l2_crop cam_crop; + unsigned int width_in, height_in; + int ret; + + cam_crop.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + ret = client_g_rect(sd, &cam_crop.c); + if (ret < 0) + return ret; + + ret = get_camera_scales(sd, &cam_crop.c, scale_h, scale_v); + if (ret < 0) + return ret; + + width_in = scale_up(cam->ceu_rect.width, *scale_h); + height_in = scale_up(cam->ceu_rect.height, *scale_v); + + *scale_h = calc_generic_scale(cam->ceu_rect.width, icd->user_width); + *scale_v = calc_generic_scale(cam->ceu_rect.height, icd->user_height); + + return 0; +} + +/* + * CEU can scale and crop, but we don't want to waste bandwidth and kill the + * framerate by always requesting the maximum image from the client. See + * Documentation/video4linux/sh_mobile_camera_ceu.txt for a description of + * scaling and cropping algorithms and for the meaning of referenced here steps. + */ static int sh_mobile_ceu_set_crop(struct soc_camera_device *icd, - struct v4l2_rect *rect) + struct v4l2_crop *a) { - return icd->ops->set_crop(icd, rect); + struct v4l2_rect *rect = &a->c; + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct sh_mobile_ceu_dev *pcdev = ici->priv; + struct v4l2_crop cam_crop; + struct sh_mobile_ceu_cam *cam = icd->host_priv; + struct v4l2_rect *cam_rect = &cam_crop.c, *ceu_rect = &cam->ceu_rect; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + struct device *dev = icd->dev.parent; + struct v4l2_format f; + struct v4l2_pix_format *pix = &f.fmt.pix; + unsigned int scale_comb_h, scale_comb_v, scale_ceu_h, scale_ceu_v, + out_width, out_height; + u32 capsr, cflcr; + int ret; + + /* 1. Calculate current combined scales. */ + ret = get_scales(icd, &scale_comb_h, &scale_comb_v); + if (ret < 0) + return ret; + + dev_geo(dev, "1: combined scales %u:%u\n", scale_comb_h, scale_comb_v); + + /* 2. Apply iterative camera S_CROP for new input window. */ + ret = client_s_crop(sd, a, &cam_crop); + if (ret < 0) + return ret; + + dev_geo(dev, "2: camera cropped to %ux%u@%u:%u\n", + cam_rect->width, cam_rect->height, + cam_rect->left, cam_rect->top); + + /* On success cam_crop contains current camera crop */ + + /* + * 3. If old combined scales applied to new crop produce an impossible + * user window, adjust scales to produce nearest possible window. + */ + out_width = scale_down(rect->width, scale_comb_h); + out_height = scale_down(rect->height, scale_comb_v); + + if (out_width > 2560) + out_width = 2560; + else if (out_width < 2) + out_width = 2; + + if (out_height > 1920) + out_height = 1920; + else if (out_height < 4) + out_height = 4; + + dev_geo(dev, "3: Adjusted output %ux%u\n", out_width, out_height); + + /* 4. Use G_CROP to retrieve actual input window: already in cam_crop */ + + /* + * 5. Using actual input window and calculated combined scales calculate + * camera target output window. + */ + pix->width = scale_down(cam_rect->width, scale_comb_h); + pix->height = scale_down(cam_rect->height, scale_comb_v); + + dev_geo(dev, "5: camera target %ux%u\n", pix->width, pix->height); + + /* 6. - 9. */ + pix->pixelformat = cam->camera_fmt->fourcc; + pix->colorspace = cam->camera_fmt->colorspace; + + capsr = capture_save_reset(pcdev); + dev_dbg(dev, "CAPSR 0x%x, CFLCR 0x%x\n", capsr, pcdev->cflcr); + + /* Make relative to camera rectangle */ + rect->left -= cam_rect->left; + rect->top -= cam_rect->top; + + f.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + ret = client_scale(icd, cam_rect, rect, ceu_rect, &f, + pcdev->image_mode && !pcdev->is_interlaced); + + dev_geo(dev, "6-9: %d\n", ret); + + /* 10. Use CEU cropping to crop to the new window. */ + sh_mobile_ceu_set_rect(icd, out_width, out_height); + + dev_geo(dev, "10: CEU cropped to %ux%u@%u:%u\n", + ceu_rect->width, ceu_rect->height, + ceu_rect->left, ceu_rect->top); + + /* + * 11. Calculate CEU scales from camera scales from results of (10) and + * user window from (3) + */ + scale_ceu_h = calc_scale(ceu_rect->width, &out_width); + scale_ceu_v = calc_scale(ceu_rect->height, &out_height); + + dev_geo(dev, "11: CEU scales %u:%u\n", scale_ceu_h, scale_ceu_v); + + /* 12. Apply CEU scales. */ + cflcr = scale_ceu_h | (scale_ceu_v << 16); + if (cflcr != pcdev->cflcr) { + pcdev->cflcr = cflcr; + ceu_write(pcdev, CFLCR, cflcr); + } + + /* Restore capture */ + if (pcdev->active) + capsr |= 1; + capture_restore(pcdev, capsr); + + icd->user_width = out_width; + icd->user_height = out_height; + + /* Even if only camera cropping succeeded */ + return ret; } +/* Similar to set_crop multistage iterative algorithm */ static int sh_mobile_ceu_set_fmt(struct soc_camera_device *icd, struct v4l2_format *f) { struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); struct sh_mobile_ceu_dev *pcdev = ici->priv; - __u32 pixfmt = f->fmt.pix.pixelformat; - const struct soc_camera_format_xlate *xlate; + struct sh_mobile_ceu_cam *cam = icd->host_priv; + struct v4l2_pix_format *pix = &f->fmt.pix; struct v4l2_format cam_f = *f; + struct v4l2_pix_format *cam_pix = &cam_f.fmt.pix; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + struct device *dev = icd->dev.parent; + __u32 pixfmt = pix->pixelformat; + const struct soc_camera_format_xlate *xlate; + struct v4l2_crop cam_crop; + struct v4l2_rect *cam_rect = &cam_crop.c, cam_subrect, ceu_rect; + unsigned int scale_cam_h, scale_cam_v; + u16 scale_v, scale_h; int ret; + bool is_interlaced, image_mode; + + switch (pix->field) { + case V4L2_FIELD_INTERLACED: + is_interlaced = true; + break; + case V4L2_FIELD_ANY: + default: + pix->field = V4L2_FIELD_NONE; + /* fall-through */ + case V4L2_FIELD_NONE: + is_interlaced = false; + break; + } xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); if (!xlate) { - dev_warn(ici->dev, "Format %x not found\n", pixfmt); + dev_warn(dev, "Format %x not found\n", pixfmt); return -EINVAL; } - cam_f.fmt.pix.pixelformat = xlate->cam_fmt->fourcc; - ret = icd->ops->set_fmt(icd, &cam_f); + /* 1. Calculate current camera scales. */ + cam_crop.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - if (!ret) { - icd->buswidth = xlate->buswidth; - icd->current_fmt = xlate->host_fmt; - pcdev->camera_fmt = xlate->cam_fmt; + ret = client_g_rect(sd, cam_rect); + if (ret < 0) + return ret; + + ret = get_camera_scales(sd, cam_rect, &scale_cam_h, &scale_cam_v); + if (ret < 0) + return ret; + + dev_geo(dev, "1: camera scales %u:%u\n", scale_cam_h, scale_cam_v); + + /* + * 2. Calculate "effective" input crop (sensor subwindow) - CEU crop + * scaled back at current camera scales onto input window. + */ + ret = get_camera_subwin(icd, &cam_subrect, scale_cam_h, scale_cam_v); + if (ret < 0) + return ret; + + dev_geo(dev, "2: subwin %ux%u@%u:%u\n", + cam_subrect.width, cam_subrect.height, + cam_subrect.left, cam_subrect.top); + + /* + * 3. Calculate new combined scales from "effective" input window to + * requested user window. + */ + scale_h = calc_generic_scale(cam_subrect.width, pix->width); + scale_v = calc_generic_scale(cam_subrect.height, pix->height); + + dev_geo(dev, "3: scales %u:%u\n", scale_h, scale_v); + + /* + * 4. Calculate camera output window by applying combined scales to real + * input window. + */ + cam_pix->width = scale_down(cam_rect->width, scale_h); + cam_pix->height = scale_down(cam_rect->height, scale_v); + cam_pix->pixelformat = xlate->cam_fmt->fourcc; + + switch (pixfmt) { + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_NV21: + case V4L2_PIX_FMT_NV16: + case V4L2_PIX_FMT_NV61: + image_mode = true; + break; + default: + image_mode = false; } - return ret; + dev_geo(dev, "4: camera output %ux%u\n", + cam_pix->width, cam_pix->height); + + /* 5. - 9. */ + ret = client_scale(icd, cam_rect, &cam_subrect, &ceu_rect, &cam_f, + image_mode && !is_interlaced); + + dev_geo(dev, "5-9: client scale %d\n", ret); + + /* Done with the camera. Now see if we can improve the result */ + + dev_dbg(dev, "Camera %d fmt %ux%u, requested %ux%u\n", + ret, cam_pix->width, cam_pix->height, pix->width, pix->height); + if (ret < 0) + return ret; + + /* 10. Use CEU scaling to scale to the requested user window. */ + + /* We cannot scale up */ + if (pix->width > cam_pix->width) + pix->width = cam_pix->width; + if (pix->width > ceu_rect.width) + pix->width = ceu_rect.width; + + if (pix->height > cam_pix->height) + pix->height = cam_pix->height; + if (pix->height > ceu_rect.height) + pix->height = ceu_rect.height; + + /* Let's rock: scale pix->{width x height} down to width x height */ + scale_h = calc_scale(ceu_rect.width, &pix->width); + scale_v = calc_scale(ceu_rect.height, &pix->height); + + dev_geo(dev, "10: W: %u : 0x%x = %u, H: %u : 0x%x = %u\n", + ceu_rect.width, scale_h, pix->width, + ceu_rect.height, scale_v, pix->height); + + pcdev->cflcr = scale_h | (scale_v << 16); + + icd->buswidth = xlate->buswidth; + icd->current_fmt = xlate->host_fmt; + cam->camera_fmt = xlate->cam_fmt; + cam->ceu_rect = ceu_rect; + + pcdev->is_interlaced = is_interlaced; + pcdev->image_mode = image_mode; + + return 0; } static int sh_mobile_ceu_try_fmt(struct soc_camera_device *icd, struct v4l2_format *f) { - struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); - struct sh_mobile_ceu_dev *pcdev = ici->priv; const struct soc_camera_format_xlate *xlate; - __u32 pixfmt = f->fmt.pix.pixelformat; + struct v4l2_pix_format *pix = &f->fmt.pix; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + __u32 pixfmt = pix->pixelformat; + int width, height; int ret; xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); if (!xlate) { - dev_warn(ici->dev, "Format %x not found\n", pixfmt); + dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt); return -EINVAL; } /* FIXME: calculate using depth and bus width */ - v4l_bound_align_image(&f->fmt.pix.width, 2, 2560, 1, - &f->fmt.pix.height, 4, 1920, 2, 0); + v4l_bound_align_image(&pix->width, 2, 2560, 1, + &pix->height, 4, 1920, 2, 0); + + width = pix->width; + height = pix->height; - f->fmt.pix.bytesperline = f->fmt.pix.width * + pix->bytesperline = pix->width * DIV_ROUND_UP(xlate->host_fmt->depth, 8); - f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; + pix->sizeimage = pix->height * pix->bytesperline; + + pix->pixelformat = xlate->cam_fmt->fourcc; /* limit to sensor capabilities */ - ret = icd->ops->try_fmt(icd, f); + ret = v4l2_subdev_call(sd, video, try_fmt, f); + pix->pixelformat = pixfmt; if (ret < 0) return ret; - switch (f->fmt.pix.field) { - case V4L2_FIELD_INTERLACED: - pcdev->is_interlaced = 1; - break; - case V4L2_FIELD_ANY: - f->fmt.pix.field = V4L2_FIELD_NONE; - /* fall-through */ - case V4L2_FIELD_NONE: - pcdev->is_interlaced = 0; - break; - default: - ret = -EINVAL; - break; + switch (pixfmt) { + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_NV21: + case V4L2_PIX_FMT_NV16: + case V4L2_PIX_FMT_NV61: + /* FIXME: check against rect_max after converting soc-camera */ + /* We can scale precisely, need a bigger image from camera */ + if (pix->width < width || pix->height < height) { + int tmp_w = pix->width, tmp_h = pix->height; + pix->width = 2560; + pix->height = 1920; + ret = v4l2_subdev_call(sd, video, try_fmt, f); + if (ret < 0) { + /* Shouldn't actually happen... */ + dev_err(icd->dev.parent, + "FIXME: try_fmt() returned %d\n", ret); + pix->width = tmp_w; + pix->height = tmp_h; + } + } + if (pix->width > width) + pix->width = width; + if (pix->height > height) + pix->height = height; } return ret; @@ -769,7 +1566,7 @@ static void sh_mobile_ceu_init_videobuf(struct videobuf_queue *q, videobuf_queue_dma_contig_init(q, &sh_mobile_ceu_videobuf_ops, - ici->dev, &pcdev->lock, + icd->dev.parent, &pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE, pcdev->is_interlaced ? V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE, @@ -777,22 +1574,76 @@ static void sh_mobile_ceu_init_videobuf(struct videobuf_queue *q, icd); } +static int sh_mobile_ceu_get_ctrl(struct soc_camera_device *icd, + struct v4l2_control *ctrl) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct sh_mobile_ceu_dev *pcdev = ici->priv; + u32 val; + + switch (ctrl->id) { + case V4L2_CID_SHARPNESS: + val = ceu_read(pcdev, CLFCR); + ctrl->value = val ^ 1; + return 0; + } + return -ENOIOCTLCMD; +} + +static int sh_mobile_ceu_set_ctrl(struct soc_camera_device *icd, + struct v4l2_control *ctrl) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct sh_mobile_ceu_dev *pcdev = ici->priv; + + switch (ctrl->id) { + case V4L2_CID_SHARPNESS: + switch (icd->current_fmt->fourcc) { + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_NV21: + case V4L2_PIX_FMT_NV16: + case V4L2_PIX_FMT_NV61: + ceu_write(pcdev, CLFCR, !ctrl->value); + return 0; + } + return -EINVAL; + } + return -ENOIOCTLCMD; +} + +static const struct v4l2_queryctrl sh_mobile_ceu_controls[] = { + { + .id = V4L2_CID_SHARPNESS, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Low-pass filter", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, +}; + static struct soc_camera_host_ops sh_mobile_ceu_host_ops = { .owner = THIS_MODULE, .add = sh_mobile_ceu_add_device, .remove = sh_mobile_ceu_remove_device, .get_formats = sh_mobile_ceu_get_formats, + .put_formats = sh_mobile_ceu_put_formats, .set_crop = sh_mobile_ceu_set_crop, .set_fmt = sh_mobile_ceu_set_fmt, .try_fmt = sh_mobile_ceu_try_fmt, + .set_ctrl = sh_mobile_ceu_set_ctrl, + .get_ctrl = sh_mobile_ceu_get_ctrl, .reqbufs = sh_mobile_ceu_reqbufs, .poll = sh_mobile_ceu_poll, .querycap = sh_mobile_ceu_querycap, .set_bus_param = sh_mobile_ceu_set_bus_param, .init_videobuf = sh_mobile_ceu_init_videobuf, + .controls = sh_mobile_ceu_controls, + .num_controls = ARRAY_SIZE(sh_mobile_ceu_controls), }; -static int sh_mobile_ceu_probe(struct platform_device *pdev) +static int __devinit sh_mobile_ceu_probe(struct platform_device *pdev) { struct sh_mobile_ceu_dev *pcdev; struct resource *res; @@ -865,7 +1716,7 @@ static int sh_mobile_ceu_probe(struct platform_device *pdev) pm_runtime_resume(&pdev->dev); pcdev->ici.priv = pcdev; - pcdev->ici.dev = &pdev->dev; + pcdev->ici.v4l2_dev.dev = &pdev->dev; pcdev->ici.nr = pdev->id; pcdev->ici.drv_name = dev_name(&pdev->dev); pcdev->ici.ops = &sh_mobile_ceu_host_ops; @@ -889,7 +1740,7 @@ exit: return err; } -static int sh_mobile_ceu_remove(struct platform_device *pdev) +static int __devexit sh_mobile_ceu_remove(struct platform_device *pdev) { struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); struct sh_mobile_ceu_dev *pcdev = container_of(soc_host, @@ -927,7 +1778,7 @@ static struct platform_driver sh_mobile_ceu_driver = { .pm = &sh_mobile_ceu_dev_pm_ops, }, .probe = sh_mobile_ceu_probe, - .remove = sh_mobile_ceu_remove, + .remove = __exit_p(sh_mobile_ceu_remove), }; static int __init sh_mobile_ceu_init(void) @@ -946,3 +1797,4 @@ module_exit(sh_mobile_ceu_exit); MODULE_DESCRIPTION("SuperH Mobile CEU driver"); MODULE_AUTHOR("Magnus Damm"); MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:sh_mobile_ceu"); diff --git a/drivers/media/video/sn9c102/sn9c102_core.c b/drivers/media/video/sn9c102/sn9c102_core.c index 23edfdc4d4bc..9d84c94e8a40 100644 --- a/drivers/media/video/sn9c102/sn9c102_core.c +++ b/drivers/media/video/sn9c102/sn9c102_core.c @@ -1954,8 +1954,10 @@ sn9c102_read(struct file* filp, char __user * buf, size_t count, loff_t* f_pos) (!list_empty(&cam->outqueue)) || (cam->state & DEV_DISCONNECTED) || (cam->state & DEV_MISCONFIGURED), - cam->module_param.frame_timeout * - 1000 * msecs_to_jiffies(1) ); + msecs_to_jiffies( + cam->module_param.frame_timeout * 1000 + ) + ); if (timeout < 0) { mutex_unlock(&cam->fileop_mutex); return timeout; diff --git a/drivers/media/video/soc_camera.c b/drivers/media/video/soc_camera.c index 9f5ae8167855..59aa7a3694c2 100644 --- a/drivers/media/video/soc_camera.c +++ b/drivers/media/video/soc_camera.c @@ -21,15 +21,15 @@ #include #include #include -#include #include +#include #include #include #include #include -#include #include +#include #include /* Default to VGA resolution */ @@ -38,7 +38,7 @@ static LIST_HEAD(hosts); static LIST_HEAD(devices); -static DEFINE_MUTEX(list_lock); +static DEFINE_MUTEX(list_lock); /* Protects the list of hosts */ const struct soc_camera_data_format *soc_camera_format_by_fourcc( struct soc_camera_device *icd, unsigned int fourcc) @@ -152,12 +152,9 @@ static int soc_camera_s_std(struct file *file, void *priv, v4l2_std_id *a) { struct soc_camera_file *icf = file->private_data; struct soc_camera_device *icd = icf->icd; - int ret = 0; - - if (icd->ops->set_std) - ret = icd->ops->set_std(icd, a); + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); - return ret; + return v4l2_subdev_call(sd, core, s_std, *a); } static int soc_camera_reqbufs(struct file *file, void *priv, @@ -170,8 +167,6 @@ static int soc_camera_reqbufs(struct file *file, void *priv, WARN_ON(priv != file->private_data); - dev_dbg(&icd->dev, "%s: %d\n", __func__, p->memory); - ret = videobuf_reqbufs(&icf->vb_vidq, p); if (ret < 0) return ret; @@ -209,10 +204,11 @@ static int soc_camera_dqbuf(struct file *file, void *priv, return videobuf_dqbuf(&icf->vb_vidq, p, file->f_flags & O_NONBLOCK); } +/* Always entered with .video_lock held */ static int soc_camera_init_user_formats(struct soc_camera_device *icd) { struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); - int i, fmts = 0; + int i, fmts = 0, ret; if (!ici->ops->get_formats) /* @@ -225,8 +221,12 @@ static int soc_camera_init_user_formats(struct soc_camera_device *icd) * First pass - only count formats this host-sensor * configuration can provide */ - for (i = 0; i < icd->num_formats; i++) - fmts += ici->ops->get_formats(icd, i, NULL); + for (i = 0; i < icd->num_formats; i++) { + ret = ici->ops->get_formats(icd, i, NULL); + if (ret < 0) + return ret; + fmts += ret; + } if (!fmts) return -ENXIO; @@ -248,20 +248,39 @@ static int soc_camera_init_user_formats(struct soc_camera_device *icd) icd->user_formats[i].cam_fmt = icd->formats + i; icd->user_formats[i].buswidth = icd->formats[i].depth; } else { - fmts += ici->ops->get_formats(icd, i, - &icd->user_formats[fmts]); + ret = ici->ops->get_formats(icd, i, + &icd->user_formats[fmts]); + if (ret < 0) + goto egfmt; + fmts += ret; } icd->current_fmt = icd->user_formats[0].host_fmt; return 0; + +egfmt: + icd->num_user_formats = 0; + vfree(icd->user_formats); + return ret; } +/* Always entered with .video_lock held */ static void soc_camera_free_user_formats(struct soc_camera_device *icd) { + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + + if (ici->ops->put_formats) + ici->ops->put_formats(icd); + icd->current_fmt = NULL; + icd->num_user_formats = 0; vfree(icd->user_formats); + icd->user_formats = NULL; } +#define pixfmtstr(x) (x) & 0xff, ((x) >> 8) & 0xff, ((x) >> 16) & 0xff, \ + ((x) >> 24) & 0xff + /* Called with .vb_lock held */ static int soc_camera_set_fmt(struct soc_camera_file *icf, struct v4l2_format *f) @@ -271,6 +290,9 @@ static int soc_camera_set_fmt(struct soc_camera_file *icf, struct v4l2_pix_format *pix = &f->fmt.pix; int ret; + dev_dbg(&icd->dev, "S_FMT(%c%c%c%c, %ux%u)\n", + pixfmtstr(pix->pixelformat), pix->width, pix->height); + /* We always call try_fmt() before set_fmt() or set_crop() */ ret = ici->ops->try_fmt(icd, f); if (ret < 0) @@ -281,13 +303,13 @@ static int soc_camera_set_fmt(struct soc_camera_file *icf, return ret; } else if (!icd->current_fmt || icd->current_fmt->fourcc != pix->pixelformat) { - dev_err(ici->dev, + dev_err(&icd->dev, "Host driver hasn't set up current format correctly!\n"); return -EINVAL; } - icd->width = pix->width; - icd->height = pix->height; + icd->user_width = pix->width; + icd->user_height = pix->height; icf->vb_vidq.field = icd->field = pix->field; @@ -296,7 +318,7 @@ static int soc_camera_set_fmt(struct soc_camera_file *icf, f->type); dev_dbg(&icd->dev, "set width: %d height: %d\n", - icd->width, icd->height); + icd->user_width, icd->user_height); /* set physical bus parameters */ return ici->ops->set_bus_param(icd, pix->pixelformat); @@ -304,30 +326,24 @@ static int soc_camera_set_fmt(struct soc_camera_file *icf, static int soc_camera_open(struct file *file) { - struct video_device *vdev; - struct soc_camera_device *icd; + struct video_device *vdev = video_devdata(file); + struct soc_camera_device *icd = container_of(vdev->parent, + struct soc_camera_device, + dev); + struct soc_camera_link *icl = to_soc_camera_link(icd); struct soc_camera_host *ici; struct soc_camera_file *icf; int ret; - icf = vmalloc(sizeof(*icf)); - if (!icf) - return -ENOMEM; - - /* - * It is safe to dereference these pointers now as long as a user has - * the video device open - we are protected by the held cdev reference. - */ + if (!icd->ops) + /* No device driver attached */ + return -ENODEV; - vdev = video_devdata(file); - icd = container_of(vdev->parent, struct soc_camera_device, dev); ici = to_soc_camera_host(icd->dev.parent); - if (!try_module_get(icd->ops->owner)) { - dev_err(&icd->dev, "Couldn't lock sensor driver.\n"); - ret = -EINVAL; - goto emgd; - } + icf = vmalloc(sizeof(*icf)); + if (!icf) + return -ENOMEM; if (!try_module_get(ici->ops->owner)) { dev_err(&icd->dev, "Couldn't lock capture bus driver.\n"); @@ -335,7 +351,10 @@ static int soc_camera_open(struct file *file) goto emgi; } - /* Protect against icd->remove() until we module_get() both drivers. */ + /* + * Protect against icd->ops->remove() until we module_get() both + * drivers. + */ mutex_lock(&icd->video_lock); icf->icd = icd; @@ -347,14 +366,24 @@ static int soc_camera_open(struct file *file) struct v4l2_format f = { .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, .fmt.pix = { - .width = icd->width, - .height = icd->height, + .width = icd->user_width, + .height = icd->user_height, .field = icd->field, .pixelformat = icd->current_fmt->fourcc, .colorspace = icd->current_fmt->colorspace, }, }; + if (icl->power) { + ret = icl->power(icd->pdev, 1); + if (ret < 0) + goto epower; + } + + /* The camera could have been already on, try to reset */ + if (icl->reset) + icl->reset(icd->pdev); + ret = ici->ops->add(icd); if (ret < 0) { dev_err(&icd->dev, "Couldn't activate the camera: %d\n", ret); @@ -367,28 +396,29 @@ static int soc_camera_open(struct file *file) goto esfmt; } - mutex_unlock(&icd->video_lock); - file->private_data = icf; dev_dbg(&icd->dev, "camera device open\n"); ici->ops->init_videobuf(&icf->vb_vidq, icd); + mutex_unlock(&icd->video_lock); + return 0; /* - * First three errors are entered with the .video_lock held + * First five errors are entered with the .video_lock held * and use_count == 1 */ esfmt: ici->ops->remove(icd); eiciadd: + if (icl->power) + icl->power(icd->pdev, 0); +epower: icd->use_count--; mutex_unlock(&icd->video_lock); module_put(ici->ops->owner); emgi: - module_put(icd->ops->owner); -emgd: vfree(icf); return ret; } @@ -398,21 +428,24 @@ static int soc_camera_close(struct file *file) struct soc_camera_file *icf = file->private_data; struct soc_camera_device *icd = icf->icd; struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); - struct video_device *vdev = icd->vdev; mutex_lock(&icd->video_lock); icd->use_count--; - if (!icd->use_count) + if (!icd->use_count) { + struct soc_camera_link *icl = to_soc_camera_link(icd); + ici->ops->remove(icd); + if (icl->power) + icl->power(icd->pdev, 0); + } mutex_unlock(&icd->video_lock); - module_put(icd->ops->owner); module_put(ici->ops->owner); vfree(icf); - dev_dbg(vdev->parent, "camera device close\n"); + dev_dbg(&icd->dev, "camera device close\n"); return 0; } @@ -422,10 +455,9 @@ static ssize_t soc_camera_read(struct file *file, char __user *buf, { struct soc_camera_file *icf = file->private_data; struct soc_camera_device *icd = icf->icd; - struct video_device *vdev = icd->vdev; int err = -EINVAL; - dev_err(vdev->parent, "camera device read not implemented\n"); + dev_err(&icd->dev, "camera device read not implemented\n"); return err; } @@ -483,8 +515,8 @@ static int soc_camera_s_fmt_vid_cap(struct file *file, void *priv, mutex_lock(&icf->vb_vidq.vb_lock); - if (videobuf_queue_is_busy(&icf->vb_vidq)) { - dev_err(&icd->dev, "S_FMT denied: queue busy\n"); + if (icf->vb_vidq.bufs[0]) { + dev_err(&icd->dev, "S_FMT denied: queue initialised\n"); ret = -EBUSY; goto unlock; } @@ -525,8 +557,8 @@ static int soc_camera_g_fmt_vid_cap(struct file *file, void *priv, WARN_ON(priv != file->private_data); - pix->width = icd->width; - pix->height = icd->height; + pix->width = icd->user_width; + pix->height = icd->user_height; pix->field = icf->vb_vidq.field; pix->pixelformat = icd->current_fmt->fourcc; pix->bytesperline = pix->width * @@ -555,18 +587,17 @@ static int soc_camera_streamon(struct file *file, void *priv, { struct soc_camera_file *icf = file->private_data; struct soc_camera_device *icd = icf->icd; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); int ret; WARN_ON(priv != file->private_data); - dev_dbg(&icd->dev, "%s\n", __func__); - if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; mutex_lock(&icd->video_lock); - icd->ops->start_capture(icd); + v4l2_subdev_call(sd, video, s_stream, 1); /* This calls buf_queue from host driver's videobuf_queue_ops */ ret = videobuf_streamon(&icf->vb_vidq); @@ -581,11 +612,10 @@ static int soc_camera_streamoff(struct file *file, void *priv, { struct soc_camera_file *icf = file->private_data; struct soc_camera_device *icd = icf->icd; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); WARN_ON(priv != file->private_data); - dev_dbg(&icd->dev, "%s\n", __func__); - if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; @@ -595,7 +625,7 @@ static int soc_camera_streamoff(struct file *file, void *priv, * remaining buffers. When the last buffer is freed, stop capture */ videobuf_streamoff(&icf->vb_vidq); - icd->ops->stop_capture(icd); + v4l2_subdev_call(sd, video, s_stream, 0); mutex_unlock(&icd->video_lock); @@ -607,6 +637,7 @@ static int soc_camera_queryctrl(struct file *file, void *priv, { struct soc_camera_file *icf = file->private_data; struct soc_camera_device *icd = icf->icd; + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); int i; WARN_ON(priv != file->private_data); @@ -614,6 +645,15 @@ static int soc_camera_queryctrl(struct file *file, void *priv, if (!qc->id) return -EINVAL; + /* First check host controls */ + for (i = 0; i < ici->ops->num_controls; i++) + if (qc->id == ici->ops->controls[i].id) { + memcpy(qc, &(ici->ops->controls[i]), + sizeof(*qc)); + return 0; + } + + /* Then device controls */ for (i = 0; i < icd->ops->num_controls; i++) if (qc->id == icd->ops->controls[i].id) { memcpy(qc, &(icd->ops->controls[i]), @@ -629,25 +669,19 @@ static int soc_camera_g_ctrl(struct file *file, void *priv, { struct soc_camera_file *icf = file->private_data; struct soc_camera_device *icd = icf->icd; + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + int ret; WARN_ON(priv != file->private_data); - switch (ctrl->id) { - case V4L2_CID_GAIN: - if (icd->gain == (unsigned short)~0) - return -EINVAL; - ctrl->value = icd->gain; - return 0; - case V4L2_CID_EXPOSURE: - if (icd->exposure == (unsigned short)~0) - return -EINVAL; - ctrl->value = icd->exposure; - return 0; + if (ici->ops->get_ctrl) { + ret = ici->ops->get_ctrl(icd, ctrl); + if (ret != -ENOIOCTLCMD) + return ret; } - if (icd->ops->get_control) - return icd->ops->get_control(icd, ctrl); - return -EINVAL; + return v4l2_subdev_call(sd, core, g_ctrl, ctrl); } static int soc_camera_s_ctrl(struct file *file, void *priv, @@ -655,12 +689,19 @@ static int soc_camera_s_ctrl(struct file *file, void *priv, { struct soc_camera_file *icf = file->private_data; struct soc_camera_device *icd = icf->icd; + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + int ret; WARN_ON(priv != file->private_data); - if (icd->ops->set_control) - return icd->ops->set_control(icd, ctrl); - return -EINVAL; + if (ici->ops->set_ctrl) { + ret = ici->ops->set_ctrl(icd, ctrl); + if (ret != -ENOIOCTLCMD) + return ret; + } + + return v4l2_subdev_call(sd, core, s_ctrl, ctrl); } static int soc_camera_cropcap(struct file *file, void *fh, @@ -668,20 +709,9 @@ static int soc_camera_cropcap(struct file *file, void *fh, { struct soc_camera_file *icf = file->private_data; struct soc_camera_device *icd = icf->icd; + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); - a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - a->bounds.left = icd->x_min; - a->bounds.top = icd->y_min; - a->bounds.width = icd->width_max; - a->bounds.height = icd->height_max; - a->defrect.left = icd->x_min; - a->defrect.top = icd->y_min; - a->defrect.width = DEFAULT_WIDTH; - a->defrect.height = DEFAULT_HEIGHT; - a->pixelaspect.numerator = 1; - a->pixelaspect.denominator = 1; - - return 0; + return ici->ops->cropcap(icd, a); } static int soc_camera_g_crop(struct file *file, void *fh, @@ -689,36 +719,53 @@ static int soc_camera_g_crop(struct file *file, void *fh, { struct soc_camera_file *icf = file->private_data; struct soc_camera_device *icd = icf->icd; + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + int ret; - a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - a->c.left = icd->x_current; - a->c.top = icd->y_current; - a->c.width = icd->width; - a->c.height = icd->height; + mutex_lock(&icf->vb_vidq.vb_lock); + ret = ici->ops->get_crop(icd, a); + mutex_unlock(&icf->vb_vidq.vb_lock); - return 0; + return ret; } +/* + * According to the V4L2 API, drivers shall not update the struct v4l2_crop + * argument with the actual geometry, instead, the user shall use G_CROP to + * retrieve it. However, we expect camera host and client drivers to update + * the argument, which we then use internally, but do not return to the user. + */ static int soc_camera_s_crop(struct file *file, void *fh, struct v4l2_crop *a) { struct soc_camera_file *icf = file->private_data; struct soc_camera_device *icd = icf->icd; struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct v4l2_rect *rect = &a->c; + struct v4l2_crop current_crop; int ret; if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; + dev_dbg(&icd->dev, "S_CROP(%ux%u@%u:%u)\n", + rect->width, rect->height, rect->left, rect->top); + /* Cropping is allowed during a running capture, guard consistency */ mutex_lock(&icf->vb_vidq.vb_lock); - ret = ici->ops->set_crop(icd, &a->c); - if (!ret) { - icd->width = a->c.width; - icd->height = a->c.height; - icd->x_current = a->c.left; - icd->y_current = a->c.top; + /* If get_crop fails, we'll let host and / or client drivers decide */ + ret = ici->ops->get_crop(icd, ¤t_crop); + + /* Prohibit window size change with initialised buffers */ + if (icf->vb_vidq.bufs[0] && !ret && + (a->c.width != current_crop.c.width || + a->c.height != current_crop.c.height)) { + dev_err(&icd->dev, + "S_CROP denied: queue initialised and sizes differ\n"); + ret = -EBUSY; + } else { + ret = ici->ops->set_crop(icd, a); } mutex_unlock(&icf->vb_vidq.vb_lock); @@ -731,11 +778,9 @@ static int soc_camera_g_chip_ident(struct file *file, void *fh, { struct soc_camera_file *icf = file->private_data; struct soc_camera_device *icd = icf->icd; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); - if (!icd->ops->get_chip_id) - return -EINVAL; - - return icd->ops->get_chip_id(icd, id); + return v4l2_subdev_call(sd, core, g_chip_ident, id); } #ifdef CONFIG_VIDEO_ADV_DEBUG @@ -744,11 +789,9 @@ static int soc_camera_g_register(struct file *file, void *fh, { struct soc_camera_file *icf = file->private_data; struct soc_camera_device *icd = icf->icd; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); - if (!icd->ops->get_register) - return -EINVAL; - - return icd->ops->get_register(icd, reg); + return v4l2_subdev_call(sd, core, g_register, reg); } static int soc_camera_s_register(struct file *file, void *fh, @@ -756,37 +799,12 @@ static int soc_camera_s_register(struct file *file, void *fh, { struct soc_camera_file *icf = file->private_data; struct soc_camera_device *icd = icf->icd; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); - if (!icd->ops->set_register) - return -EINVAL; - - return icd->ops->set_register(icd, reg); + return v4l2_subdev_call(sd, core, s_register, reg); } #endif -static int device_register_link(struct soc_camera_device *icd) -{ - int ret = dev_set_name(&icd->dev, "%u-%u", icd->iface, icd->devnum); - - if (!ret) - ret = device_register(&icd->dev); - - if (ret < 0) { - /* Prevent calling device_unregister() */ - icd->dev.parent = NULL; - dev_err(&icd->dev, "Cannot register device: %d\n", ret); - /* Even if probe() was unsuccessful for all registered drivers, - * device_register() returns 0, and we add the link, just to - * document this camera's control device */ - } else if (icd->control) - /* Have to sysfs_remove_link() before device_unregister()? */ - if (sysfs_create_link(&icd->dev.kobj, &icd->control->kobj, - "control")) - dev_warn(&icd->dev, - "Failed creating the control symlink\n"); - return ret; -} - /* So far this function cannot fail */ static void scan_add_host(struct soc_camera_host *ici) { @@ -796,106 +814,193 @@ static void scan_add_host(struct soc_camera_host *ici) list_for_each_entry(icd, &devices, list) { if (icd->iface == ici->nr) { - icd->dev.parent = ici->dev; - device_register_link(icd); + int ret; + icd->dev.parent = ici->v4l2_dev.dev; + dev_set_name(&icd->dev, "%u-%u", icd->iface, + icd->devnum); + ret = device_register(&icd->dev); + if (ret < 0) { + icd->dev.parent = NULL; + dev_err(&icd->dev, + "Cannot register device: %d\n", ret); + } } } mutex_unlock(&list_lock); } -/* return: 0 if no match found or a match found and - * device_register() successful, error code otherwise */ -static int scan_add_device(struct soc_camera_device *icd) +#ifdef CONFIG_I2C_BOARDINFO +static int soc_camera_init_i2c(struct soc_camera_device *icd, + struct soc_camera_link *icl) { - struct soc_camera_host *ici; - int ret = 0; + struct i2c_client *client; + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct i2c_adapter *adap = i2c_get_adapter(icl->i2c_adapter_id); + struct v4l2_subdev *subdev; + int ret; - mutex_lock(&list_lock); + if (!adap) { + ret = -ENODEV; + dev_err(&icd->dev, "Cannot get I2C adapter #%d. No driver?\n", + icl->i2c_adapter_id); + goto ei2cga; + } - list_add_tail(&icd->list, &devices); + icl->board_info->platform_data = icd; - /* Watch out for class_for_each_device / class_find_device API by - * Dave Young */ - list_for_each_entry(ici, &hosts, list) { - if (icd->iface == ici->nr) { - ret = 1; - icd->dev.parent = ici->dev; - break; - } + subdev = v4l2_i2c_new_subdev_board(&ici->v4l2_dev, adap, + icl->module_name, icl->board_info, NULL); + if (!subdev) { + ret = -ENOMEM; + goto ei2cnd; } - mutex_unlock(&list_lock); + client = subdev->priv; - if (ret) - ret = device_register_link(icd); + /* Use to_i2c_client(dev) to recover the i2c client */ + dev_set_drvdata(&icd->dev, &client->dev); + return 0; +ei2cnd: + i2c_put_adapter(adap); +ei2cga: return ret; } +static void soc_camera_free_i2c(struct soc_camera_device *icd) +{ + struct i2c_client *client = + to_i2c_client(to_soc_camera_control(icd)); + dev_set_drvdata(&icd->dev, NULL); + v4l2_device_unregister_subdev(i2c_get_clientdata(client)); + i2c_unregister_device(client); + i2c_put_adapter(client->adapter); +} +#else +#define soc_camera_init_i2c(icd, icl) (-ENODEV) +#define soc_camera_free_i2c(icd) do {} while (0) +#endif + +static int soc_camera_video_start(struct soc_camera_device *icd); +static int video_dev_create(struct soc_camera_device *icd); +/* Called during host-driver probe */ static int soc_camera_probe(struct device *dev) { struct soc_camera_device *icd = to_soc_camera_dev(dev); - struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct soc_camera_host *ici = to_soc_camera_host(dev->parent); + struct soc_camera_link *icl = to_soc_camera_link(icd); + struct device *control = NULL; + struct v4l2_subdev *sd; + struct v4l2_format f = {.type = V4L2_BUF_TYPE_VIDEO_CAPTURE}; int ret; - /* - * Possible race scenario: - * modprobe triggers __func__ - * at this moment respective gets rmmod'ed - * to protect take module references. - */ + dev_info(dev, "Probing %s\n", dev_name(dev)); - if (!try_module_get(icd->ops->owner)) { - dev_err(&icd->dev, "Couldn't lock sensor driver.\n"); - ret = -EINVAL; - goto emgd; + if (icl->power) { + ret = icl->power(icd->pdev, 1); + if (ret < 0) { + dev_err(dev, + "Platform failed to power-on the camera.\n"); + goto epower; + } } - if (!try_module_get(ici->ops->owner)) { - dev_err(&icd->dev, "Couldn't lock capture bus driver.\n"); + /* The camera could have been already on, try to reset */ + if (icl->reset) + icl->reset(icd->pdev); + + ret = ici->ops->add(icd); + if (ret < 0) + goto eadd; + + /* Must have icd->vdev before registering the device */ + ret = video_dev_create(icd); + if (ret < 0) + goto evdc; + + /* Non-i2c cameras, e.g., soc_camera_platform, have no board_info */ + if (icl->board_info) { + ret = soc_camera_init_i2c(icd, icl); + if (ret < 0) + goto eadddev; + } else if (!icl->add_device || !icl->del_device) { ret = -EINVAL; - goto emgi; + goto eadddev; + } else { + if (icl->module_name) + ret = request_module(icl->module_name); + + ret = icl->add_device(icl, &icd->dev); + if (ret < 0) + goto eadddev; + + /* + * FIXME: this is racy, have to use driver-binding notification, + * when it is available + */ + control = to_soc_camera_control(icd); + if (!control || !control->driver || !dev_get_drvdata(control) || + !try_module_get(control->driver->owner)) { + icl->del_device(icl); + goto enodrv; + } } + /* At this point client .probe() should have run already */ + ret = soc_camera_init_user_formats(icd); + if (ret < 0) + goto eiufmt; + + icd->field = V4L2_FIELD_ANY; + + /* ..._video_start() will create a device node, so we have to protect */ mutex_lock(&icd->video_lock); - /* We only call ->add() here to activate and probe the camera. - * We shall ->remove() and deactivate it immediately afterwards. */ - ret = ici->ops->add(icd); + ret = soc_camera_video_start(icd); if (ret < 0) - goto eiadd; + goto evidstart; + + /* Try to improve our guess of a reasonable window format */ + sd = soc_camera_to_subdev(icd); + if (!v4l2_subdev_call(sd, video, g_fmt, &f)) { + icd->user_width = f.fmt.pix.width; + icd->user_height = f.fmt.pix.height; + } - ret = icd->ops->probe(icd); - if (ret >= 0) { - const struct v4l2_queryctrl *qctrl; + /* Do we have to sysfs_remove_link() before device_unregister()? */ + if (sysfs_create_link(&icd->dev.kobj, &to_soc_camera_control(icd)->kobj, + "control")) + dev_warn(&icd->dev, "Failed creating the control symlink\n"); - qctrl = soc_camera_find_qctrl(icd->ops, V4L2_CID_GAIN); - icd->gain = qctrl ? qctrl->default_value : (unsigned short)~0; - qctrl = soc_camera_find_qctrl(icd->ops, V4L2_CID_EXPOSURE); - icd->exposure = qctrl ? qctrl->default_value : - (unsigned short)~0; + ici->ops->remove(icd); - ret = soc_camera_init_user_formats(icd); - if (ret < 0) { - if (icd->ops->remove) - icd->ops->remove(icd); - goto eiufmt; - } + if (icl->power) + icl->power(icd->pdev, 0); - icd->height = DEFAULT_HEIGHT; - icd->width = DEFAULT_WIDTH; - icd->field = V4L2_FIELD_ANY; - } + mutex_unlock(&icd->video_lock); + return 0; + +evidstart: + mutex_unlock(&icd->video_lock); + soc_camera_free_user_formats(icd); eiufmt: + if (icl->board_info) { + soc_camera_free_i2c(icd); + } else { + icl->del_device(icl); + module_put(control->driver->owner); + } +enodrv: +eadddev: + video_device_release(icd->vdev); +evdc: ici->ops->remove(icd); -eiadd: - mutex_unlock(&icd->video_lock); - module_put(ici->ops->owner); -emgi: - module_put(icd->ops->owner); -emgd: +eadd: + if (icl->power) + icl->power(icd->pdev, 0); +epower: return ret; } @@ -904,12 +1009,28 @@ emgd: static int soc_camera_remove(struct device *dev) { struct soc_camera_device *icd = to_soc_camera_dev(dev); + struct soc_camera_link *icl = to_soc_camera_link(icd); + struct video_device *vdev = icd->vdev; - mutex_lock(&icd->video_lock); - if (icd->ops->remove) - icd->ops->remove(icd); - mutex_unlock(&icd->video_lock); + BUG_ON(!dev->parent); + if (vdev) { + mutex_lock(&icd->video_lock); + video_unregister_device(vdev); + icd->vdev = NULL; + mutex_unlock(&icd->video_lock); + } + + if (icl->board_info) { + soc_camera_free_i2c(icd); + } else { + struct device_driver *drv = to_soc_camera_control(icd) ? + to_soc_camera_control(icd)->driver : NULL; + if (drv) { + icl->del_device(icl); + module_put(drv->owner); + } + } soc_camera_free_user_formats(icd); return 0; @@ -957,14 +1078,33 @@ static void dummy_release(struct device *dev) { } +static int default_cropcap(struct soc_camera_device *icd, + struct v4l2_cropcap *a) +{ + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + return v4l2_subdev_call(sd, video, cropcap, a); +} + +static int default_g_crop(struct soc_camera_device *icd, struct v4l2_crop *a) +{ + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + return v4l2_subdev_call(sd, video, g_crop, a); +} + +static int default_s_crop(struct soc_camera_device *icd, struct v4l2_crop *a) +{ + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + return v4l2_subdev_call(sd, video, s_crop, a); +} + int soc_camera_host_register(struct soc_camera_host *ici) { struct soc_camera_host *ix; + int ret; if (!ici || !ici->ops || !ici->ops->try_fmt || !ici->ops->set_fmt || - !ici->ops->set_crop || !ici->ops->set_bus_param || !ici->ops->querycap || !ici->ops->init_videobuf || @@ -972,18 +1112,27 @@ int soc_camera_host_register(struct soc_camera_host *ici) !ici->ops->add || !ici->ops->remove || !ici->ops->poll || - !ici->dev) + !ici->v4l2_dev.dev) return -EINVAL; + if (!ici->ops->set_crop) + ici->ops->set_crop = default_s_crop; + if (!ici->ops->get_crop) + ici->ops->get_crop = default_g_crop; + if (!ici->ops->cropcap) + ici->ops->cropcap = default_cropcap; + mutex_lock(&list_lock); list_for_each_entry(ix, &hosts, list) { if (ix->nr == ici->nr) { - mutex_unlock(&list_lock); - return -EBUSY; + ret = -EBUSY; + goto edevreg; } } - dev_set_drvdata(ici->dev, ici); + ret = v4l2_device_register(ici->v4l2_dev.dev, &ici->v4l2_dev); + if (ret < 0) + goto edevreg; list_add_tail(&ici->list, &hosts); mutex_unlock(&list_lock); @@ -991,6 +1140,10 @@ int soc_camera_host_register(struct soc_camera_host *ici) scan_add_host(ici); return 0; + +edevreg: + mutex_unlock(&list_lock); + return ret; } EXPORT_SYMBOL(soc_camera_host_register); @@ -1004,42 +1157,34 @@ void soc_camera_host_unregister(struct soc_camera_host *ici) list_del(&ici->list); list_for_each_entry(icd, &devices, list) { - if (icd->dev.parent == ici->dev) { + if (icd->iface == ici->nr) { + /* The bus->remove will be called */ device_unregister(&icd->dev); /* Not before device_unregister(), .remove * needs parent to call ici->ops->remove() */ icd->dev.parent = NULL; + + /* If the host module is loaded again, device_register() + * would complain "already initialised" */ memset(&icd->dev.kobj, 0, sizeof(icd->dev.kobj)); } } mutex_unlock(&list_lock); - dev_set_drvdata(ici->dev, NULL); + v4l2_device_unregister(&ici->v4l2_dev); } EXPORT_SYMBOL(soc_camera_host_unregister); /* Image capture device */ -int soc_camera_device_register(struct soc_camera_device *icd) +static int soc_camera_device_register(struct soc_camera_device *icd) { struct soc_camera_device *ix; int num = -1, i; - if (!icd || !icd->ops || - !icd->ops->probe || - !icd->ops->init || - !icd->ops->release || - !icd->ops->start_capture || - !icd->ops->stop_capture || - !icd->ops->set_crop || - !icd->ops->set_fmt || - !icd->ops->try_fmt || - !icd->ops->query_bus_param || - !icd->ops->set_bus_param) - return -EINVAL; - for (i = 0; i < 256 && num < 0; i++) { num = i; + /* Check if this index is available on this interface */ list_for_each_entry(ix, &devices, list) { if (ix->iface == icd->iface && ix->devnum == i) { num = -1; @@ -1061,21 +1206,15 @@ int soc_camera_device_register(struct soc_camera_device *icd) icd->host_priv = NULL; mutex_init(&icd->video_lock); - return scan_add_device(icd); + list_add_tail(&icd->list, &devices); + + return 0; } -EXPORT_SYMBOL(soc_camera_device_register); -void soc_camera_device_unregister(struct soc_camera_device *icd) +static void soc_camera_device_unregister(struct soc_camera_device *icd) { - mutex_lock(&list_lock); list_del(&icd->list); - - /* The bus->remove will be eventually called */ - if (icd->dev.parent) - device_unregister(&icd->dev); - mutex_unlock(&list_lock); } -EXPORT_SYMBOL(soc_camera_device_unregister); static const struct v4l2_ioctl_ops soc_camera_ioctl_ops = { .vidioc_querycap = soc_camera_querycap, @@ -1106,23 +1245,13 @@ static const struct v4l2_ioctl_ops soc_camera_ioctl_ops = { #endif }; -/* - * Usually called from the struct soc_camera_ops .probe() method, i.e., from - * soc_camera_probe() above with .video_lock held - */ -int soc_camera_video_start(struct soc_camera_device *icd) +static int video_dev_create(struct soc_camera_device *icd) { struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); - int err = -ENOMEM; - struct video_device *vdev; + struct video_device *vdev = video_device_alloc(); - if (!icd->dev.parent) - return -ENODEV; - - vdev = video_device_alloc(); if (!vdev) - goto evidallocd; - dev_dbg(ici->dev, "Allocated video_device %p\n", vdev); + return -ENOMEM; strlcpy(vdev->name, ici->drv_name, sizeof(vdev->name)); @@ -1132,87 +1261,93 @@ int soc_camera_video_start(struct soc_camera_device *icd) vdev->ioctl_ops = &soc_camera_ioctl_ops; vdev->release = video_device_release; vdev->minor = -1; - vdev->tvnorms = V4L2_STD_UNKNOWN, + vdev->tvnorms = V4L2_STD_UNKNOWN; - err = video_register_device(vdev, VFL_TYPE_GRABBER, vdev->minor); - if (err < 0) { - dev_err(vdev->parent, "video_register_device failed\n"); - goto evidregd; - } icd->vdev = vdev; return 0; - -evidregd: - video_device_release(vdev); -evidallocd: - return err; } -EXPORT_SYMBOL(soc_camera_video_start); -/* Called from client .remove() methods with .video_lock held */ -void soc_camera_video_stop(struct soc_camera_device *icd) +/* + * Called from soc_camera_probe() above (with .video_lock held???) + */ +static int soc_camera_video_start(struct soc_camera_device *icd) { - struct video_device *vdev = icd->vdev; + int ret; - dev_dbg(&icd->dev, "%s\n", __func__); + if (!icd->dev.parent) + return -ENODEV; - if (!icd->dev.parent || !vdev) - return; + if (!icd->ops || + !icd->ops->query_bus_param || + !icd->ops->set_bus_param) + return -EINVAL; + + ret = video_register_device(icd->vdev, VFL_TYPE_GRABBER, + icd->vdev->minor); + if (ret < 0) { + dev_err(&icd->dev, "video_register_device failed: %d\n", ret); + return ret; + } - video_unregister_device(vdev); - icd->vdev = NULL; + return 0; } -EXPORT_SYMBOL(soc_camera_video_stop); static int __devinit soc_camera_pdrv_probe(struct platform_device *pdev) { struct soc_camera_link *icl = pdev->dev.platform_data; - struct i2c_adapter *adap; - struct i2c_client *client; + struct soc_camera_device *icd; + int ret; if (!icl) return -EINVAL; - adap = i2c_get_adapter(icl->i2c_adapter_id); - if (!adap) { - dev_warn(&pdev->dev, "Cannot get adapter #%d. No driver?\n", - icl->i2c_adapter_id); - /* -ENODEV and -ENXIO do not produce an error on probe()... */ - return -ENOENT; - } - - icl->board_info->platform_data = icl; - client = i2c_new_device(adap, icl->board_info); - if (!client) { - i2c_put_adapter(adap); + icd = kzalloc(sizeof(*icd), GFP_KERNEL); + if (!icd) return -ENOMEM; - } - platform_set_drvdata(pdev, client); + icd->iface = icl->bus_id; + icd->pdev = &pdev->dev; + platform_set_drvdata(pdev, icd); + icd->dev.platform_data = icl; + + ret = soc_camera_device_register(icd); + if (ret < 0) + goto escdevreg; + + icd->user_width = DEFAULT_WIDTH; + icd->user_height = DEFAULT_HEIGHT; return 0; + +escdevreg: + kfree(icd); + + return ret; } +/* Only called on rmmod for each platform device, since they are not + * hot-pluggable. Now we know, that all our users - hosts and devices have + * been unloaded already */ static int __devexit soc_camera_pdrv_remove(struct platform_device *pdev) { - struct i2c_client *client = platform_get_drvdata(pdev); + struct soc_camera_device *icd = platform_get_drvdata(pdev); - if (!client) - return -ENODEV; + if (!icd) + return -EINVAL; - i2c_unregister_device(client); - i2c_put_adapter(client->adapter); + soc_camera_device_unregister(icd); + + kfree(icd); return 0; } static struct platform_driver __refdata soc_camera_pdrv = { - .probe = soc_camera_pdrv_probe, - .remove = __devexit_p(soc_camera_pdrv_remove), - .driver = { - .name = "soc-camera-pdrv", - .owner = THIS_MODULE, + .remove = __devexit_p(soc_camera_pdrv_remove), + .driver = { + .name = "soc-camera-pdrv", + .owner = THIS_MODULE, }, }; @@ -1225,7 +1360,7 @@ static int __init soc_camera_init(void) if (ret) goto edrvr; - ret = platform_driver_register(&soc_camera_pdrv); + ret = platform_driver_probe(&soc_camera_pdrv, soc_camera_pdrv_probe); if (ret) goto epdr; diff --git a/drivers/media/video/soc_camera_platform.c b/drivers/media/video/soc_camera_platform.c index c48676356ab7..b6a575ce5da2 100644 --- a/drivers/media/video/soc_camera_platform.c +++ b/drivers/media/video/soc_camera_platform.c @@ -16,54 +16,32 @@ #include #include #include -#include +#include #include #include struct soc_camera_platform_priv { - struct soc_camera_platform_info *info; - struct soc_camera_device icd; + struct v4l2_subdev subdev; struct soc_camera_data_format format; }; -static struct soc_camera_platform_info * -soc_camera_platform_get_info(struct soc_camera_device *icd) +static struct soc_camera_platform_priv *get_priv(struct platform_device *pdev) { - struct soc_camera_platform_priv *priv; - priv = container_of(icd, struct soc_camera_platform_priv, icd); - return priv->info; -} - -static int soc_camera_platform_init(struct soc_camera_device *icd) -{ - struct soc_camera_platform_info *p = soc_camera_platform_get_info(icd); - - if (p->power) - p->power(1); - - return 0; -} - -static int soc_camera_platform_release(struct soc_camera_device *icd) -{ - struct soc_camera_platform_info *p = soc_camera_platform_get_info(icd); - - if (p->power) - p->power(0); - - return 0; + struct v4l2_subdev *subdev = platform_get_drvdata(pdev); + return container_of(subdev, struct soc_camera_platform_priv, subdev); } -static int soc_camera_platform_start_capture(struct soc_camera_device *icd) +static struct soc_camera_platform_info *get_info(struct soc_camera_device *icd) { - struct soc_camera_platform_info *p = soc_camera_platform_get_info(icd); - return p->set_capture(p, 1); + struct platform_device *pdev = + to_platform_device(to_soc_camera_control(icd)); + return pdev->dev.platform_data; } -static int soc_camera_platform_stop_capture(struct soc_camera_device *icd) +static int soc_camera_platform_s_stream(struct v4l2_subdev *sd, int enable) { - struct soc_camera_platform_info *p = soc_camera_platform_get_info(icd); - return p->set_capture(p, 0); + struct soc_camera_platform_info *p = v4l2_get_subdevdata(sd); + return p->set_capture(p, enable); } static int soc_camera_platform_set_bus_param(struct soc_camera_device *icd, @@ -75,26 +53,14 @@ static int soc_camera_platform_set_bus_param(struct soc_camera_device *icd, static unsigned long soc_camera_platform_query_bus_param(struct soc_camera_device *icd) { - struct soc_camera_platform_info *p = soc_camera_platform_get_info(icd); + struct soc_camera_platform_info *p = get_info(icd); return p->bus_param; } -static int soc_camera_platform_set_crop(struct soc_camera_device *icd, - struct v4l2_rect *rect) -{ - return 0; -} - -static int soc_camera_platform_set_fmt(struct soc_camera_device *icd, +static int soc_camera_platform_try_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) { - return 0; -} - -static int soc_camera_platform_try_fmt(struct soc_camera_device *icd, - struct v4l2_format *f) -{ - struct soc_camera_platform_info *p = soc_camera_platform_get_info(icd); + struct soc_camera_platform_info *p = v4l2_get_subdevdata(sd); struct v4l2_pix_format *pix = &f->fmt.pix; pix->width = p->format.width; @@ -102,82 +68,99 @@ static int soc_camera_platform_try_fmt(struct soc_camera_device *icd, return 0; } -static int soc_camera_platform_video_probe(struct soc_camera_device *icd) +static void soc_camera_platform_video_probe(struct soc_camera_device *icd, + struct platform_device *pdev) { - struct soc_camera_platform_priv *priv; - priv = container_of(icd, struct soc_camera_platform_priv, icd); + struct soc_camera_platform_priv *priv = get_priv(pdev); + struct soc_camera_platform_info *p = pdev->dev.platform_data; - priv->format.name = priv->info->format_name; - priv->format.depth = priv->info->format_depth; - priv->format.fourcc = priv->info->format.pixelformat; - priv->format.colorspace = priv->info->format.colorspace; + priv->format.name = p->format_name; + priv->format.depth = p->format_depth; + priv->format.fourcc = p->format.pixelformat; + priv->format.colorspace = p->format.colorspace; icd->formats = &priv->format; icd->num_formats = 1; - - return soc_camera_video_start(icd); } -static void soc_camera_platform_video_remove(struct soc_camera_device *icd) -{ - soc_camera_video_stop(icd); -} +static struct v4l2_subdev_core_ops platform_subdev_core_ops; + +static struct v4l2_subdev_video_ops platform_subdev_video_ops = { + .s_stream = soc_camera_platform_s_stream, + .try_fmt = soc_camera_platform_try_fmt, +}; + +static struct v4l2_subdev_ops platform_subdev_ops = { + .core = &platform_subdev_core_ops, + .video = &platform_subdev_video_ops, +}; static struct soc_camera_ops soc_camera_platform_ops = { - .owner = THIS_MODULE, - .probe = soc_camera_platform_video_probe, - .remove = soc_camera_platform_video_remove, - .init = soc_camera_platform_init, - .release = soc_camera_platform_release, - .start_capture = soc_camera_platform_start_capture, - .stop_capture = soc_camera_platform_stop_capture, - .set_crop = soc_camera_platform_set_crop, - .set_fmt = soc_camera_platform_set_fmt, - .try_fmt = soc_camera_platform_try_fmt, .set_bus_param = soc_camera_platform_set_bus_param, .query_bus_param = soc_camera_platform_query_bus_param, }; static int soc_camera_platform_probe(struct platform_device *pdev) { + struct soc_camera_host *ici; struct soc_camera_platform_priv *priv; - struct soc_camera_platform_info *p; + struct soc_camera_platform_info *p = pdev->dev.platform_data; struct soc_camera_device *icd; int ret; - p = pdev->dev.platform_data; if (!p) return -EINVAL; + if (!p->dev) { + dev_err(&pdev->dev, + "Platform has not set soc_camera_device pointer!\n"); + return -EINVAL; + } + priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; - priv->info = p; - platform_set_drvdata(pdev, priv); + icd = to_soc_camera_dev(p->dev); + + /* soc-camera convention: control's drvdata points to the subdev */ + platform_set_drvdata(pdev, &priv->subdev); + /* Set the control device reference */ + dev_set_drvdata(&icd->dev, &pdev->dev); + + icd->y_skip_top = 0; + icd->ops = &soc_camera_platform_ops; + + ici = to_soc_camera_host(icd->dev.parent); - icd = &priv->icd; - icd->ops = &soc_camera_platform_ops; - icd->control = &pdev->dev; - icd->width_min = 0; - icd->width_max = priv->info->format.width; - icd->height_min = 0; - icd->height_max = priv->info->format.height; - icd->y_skip_top = 0; - icd->iface = priv->info->iface; + soc_camera_platform_video_probe(icd, pdev); - ret = soc_camera_device_register(icd); + v4l2_subdev_init(&priv->subdev, &platform_subdev_ops); + v4l2_set_subdevdata(&priv->subdev, p); + strncpy(priv->subdev.name, dev_name(&pdev->dev), V4L2_SUBDEV_NAME_SIZE); + + ret = v4l2_device_register_subdev(&ici->v4l2_dev, &priv->subdev); if (ret) - kfree(priv); + goto evdrs; + + return ret; +evdrs: + icd->ops = NULL; + platform_set_drvdata(pdev, NULL); + kfree(priv); return ret; } static int soc_camera_platform_remove(struct platform_device *pdev) { - struct soc_camera_platform_priv *priv = platform_get_drvdata(pdev); + struct soc_camera_platform_priv *priv = get_priv(pdev); + struct soc_camera_platform_info *p = pdev->dev.platform_data; + struct soc_camera_device *icd = to_soc_camera_dev(p->dev); - soc_camera_device_unregister(&priv->icd); + v4l2_device_unregister_subdev(&priv->subdev); + icd->ops = NULL; + platform_set_drvdata(pdev, NULL); kfree(priv); return 0; } @@ -185,6 +168,7 @@ static int soc_camera_platform_remove(struct platform_device *pdev) static struct platform_driver soc_camera_platform_driver = { .driver = { .name = "soc_camera_platform", + .owner = THIS_MODULE, }, .probe = soc_camera_platform_probe, .remove = soc_camera_platform_remove, @@ -206,3 +190,4 @@ module_exit(soc_camera_platform_module_exit); MODULE_DESCRIPTION("SoC Camera Platform driver"); MODULE_AUTHOR("Magnus Damm"); MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:soc_camera_platform"); diff --git a/drivers/media/video/tuner-core.c b/drivers/media/video/tuner-core.c index 2816f1839230..aba92e2313d8 100644 --- a/drivers/media/video/tuner-core.c +++ b/drivers/media/video/tuner-core.c @@ -29,6 +29,7 @@ #include "tuner-simple.h" #include "tda9887.h" #include "xc5000.h" +#include "tda18271.h" #define UNSET (-1U) @@ -420,6 +421,17 @@ static void set_type(struct i2c_client *c, unsigned int type, goto attach_failed; break; } + case TUNER_NXP_TDA18271: + { + struct tda18271_config cfg = { + .config = t->config, + }; + + if (!dvb_attach(tda18271_attach, &t->fe, t->i2c->addr, + t->i2c->adapter, &cfg)) + goto attach_failed; + break; + } default: if (!dvb_attach(simple_tuner_attach, &t->fe, t->i2c->adapter, t->i2c->addr, t->type)) diff --git a/drivers/media/video/tvp514x.c b/drivers/media/video/tvp514x.c index 3750f7fadb12..244372627df2 100644 --- a/drivers/media/video/tvp514x.c +++ b/drivers/media/video/tvp514x.c @@ -31,7 +31,10 @@ #include #include #include -#include + +#include +#include +#include #include #include "tvp514x_regs.h" @@ -49,29 +52,17 @@ static int debug; module_param(debug, bool, 0644); MODULE_PARM_DESC(debug, "Debug level (0-1)"); -#define dump_reg(client, reg, val) \ - do { \ - val = tvp514x_read_reg(client, reg); \ - v4l_info(client, "Reg(0x%.2X): 0x%.2X\n", reg, val); \ - } while (0) +MODULE_AUTHOR("Texas Instruments"); +MODULE_DESCRIPTION("TVP514X linux decoder driver"); +MODULE_LICENSE("GPL"); -/** - * enum tvp514x_std - enum for supported standards - */ +/* enum tvp514x_std - enum for supported standards */ enum tvp514x_std { STD_NTSC_MJ = 0, STD_PAL_BDGHIN, STD_INVALID }; -/** - * enum tvp514x_state - enum for different decoder states - */ -enum tvp514x_state { - STATE_NOT_DETECTED, - STATE_DETECTED -}; - /** * struct tvp514x_std_info - Structure to store standard informations * @width: Line width in pixels @@ -89,33 +80,27 @@ struct tvp514x_std_info { static struct tvp514x_reg tvp514x_reg_list_default[0x40]; /** * struct tvp514x_decoder - TVP5146/47 decoder object - * @v4l2_int_device: Slave handle - * @tvp514x_slave: Slave pointer which is used by @v4l2_int_device + * @sd: Subdevice Slave handle * @tvp514x_regs: copy of hw's regs with preset values. * @pdata: Board specific - * @client: I2C client data - * @id: Entry from I2C table * @ver: Chip version - * @state: TVP5146/47 decoder state - detected or not-detected + * @streaming: TVP5146/47 decoder streaming - enabled or disabled. * @pix: Current pixel format * @num_fmts: Number of formats * @fmt_list: Format list * @current_std: Current standard * @num_stds: Number of standards * @std_list: Standards list - * @route: input and output routing at chip level + * @input: Input routing at chip level + * @output: Output routing at chip level */ struct tvp514x_decoder { - struct v4l2_int_device v4l2_int_device; - struct v4l2_int_slave tvp514x_slave; + struct v4l2_subdev sd; struct tvp514x_reg tvp514x_regs[ARRAY_SIZE(tvp514x_reg_list_default)]; const struct tvp514x_platform_data *pdata; - struct i2c_client *client; - - struct i2c_device_id *id; int ver; - enum tvp514x_state state; + int streaming; struct v4l2_pix_format pix; int num_fmts; @@ -124,15 +109,18 @@ struct tvp514x_decoder { enum tvp514x_std current_std; int num_stds; struct tvp514x_std_info *std_list; - - struct v4l2_routing route; + /* Input and Output Routing parameters */ + u32 input; + u32 output; }; /* TVP514x default register values */ static struct tvp514x_reg tvp514x_reg_list_default[] = { - {TOK_WRITE, REG_INPUT_SEL, 0x05}, /* Composite selected */ + /* Composite selected */ + {TOK_WRITE, REG_INPUT_SEL, 0x05}, {TOK_WRITE, REG_AFE_GAIN_CTRL, 0x0F}, - {TOK_WRITE, REG_VIDEO_STD, 0x00}, /* Auto mode */ + /* Auto mode */ + {TOK_WRITE, REG_VIDEO_STD, 0x00}, {TOK_WRITE, REG_OPERATION_MODE, 0x00}, {TOK_SKIP, REG_AUTOSWITCH_MASK, 0x3F}, {TOK_WRITE, REG_COLOR_KILLER, 0x10}, @@ -145,53 +133,74 @@ static struct tvp514x_reg tvp514x_reg_list_default[] = { {TOK_WRITE, REG_HUE, 0x00}, {TOK_WRITE, REG_CHROMA_CONTROL1, 0x00}, {TOK_WRITE, REG_CHROMA_CONTROL2, 0x0E}, - {TOK_SKIP, 0x0F, 0x00}, /* Reserved */ + /* Reserved */ + {TOK_SKIP, 0x0F, 0x00}, {TOK_WRITE, REG_COMP_PR_SATURATION, 0x80}, {TOK_WRITE, REG_COMP_Y_CONTRAST, 0x80}, {TOK_WRITE, REG_COMP_PB_SATURATION, 0x80}, - {TOK_SKIP, 0x13, 0x00}, /* Reserved */ + /* Reserved */ + {TOK_SKIP, 0x13, 0x00}, {TOK_WRITE, REG_COMP_Y_BRIGHTNESS, 0x80}, - {TOK_SKIP, 0x15, 0x00}, /* Reserved */ - {TOK_SKIP, REG_AVID_START_PIXEL_LSB, 0x55}, /* NTSC timing */ + /* Reserved */ + {TOK_SKIP, 0x15, 0x00}, + /* NTSC timing */ + {TOK_SKIP, REG_AVID_START_PIXEL_LSB, 0x55}, {TOK_SKIP, REG_AVID_START_PIXEL_MSB, 0x00}, {TOK_SKIP, REG_AVID_STOP_PIXEL_LSB, 0x25}, {TOK_SKIP, REG_AVID_STOP_PIXEL_MSB, 0x03}, - {TOK_SKIP, REG_HSYNC_START_PIXEL_LSB, 0x00}, /* NTSC timing */ + /* NTSC timing */ + {TOK_SKIP, REG_HSYNC_START_PIXEL_LSB, 0x00}, {TOK_SKIP, REG_HSYNC_START_PIXEL_MSB, 0x00}, {TOK_SKIP, REG_HSYNC_STOP_PIXEL_LSB, 0x40}, {TOK_SKIP, REG_HSYNC_STOP_PIXEL_MSB, 0x00}, - {TOK_SKIP, REG_VSYNC_START_LINE_LSB, 0x04}, /* NTSC timing */ + /* NTSC timing */ + {TOK_SKIP, REG_VSYNC_START_LINE_LSB, 0x04}, {TOK_SKIP, REG_VSYNC_START_LINE_MSB, 0x00}, {TOK_SKIP, REG_VSYNC_STOP_LINE_LSB, 0x07}, {TOK_SKIP, REG_VSYNC_STOP_LINE_MSB, 0x00}, - {TOK_SKIP, REG_VBLK_START_LINE_LSB, 0x01}, /* NTSC timing */ + /* NTSC timing */ + {TOK_SKIP, REG_VBLK_START_LINE_LSB, 0x01}, {TOK_SKIP, REG_VBLK_START_LINE_MSB, 0x00}, {TOK_SKIP, REG_VBLK_STOP_LINE_LSB, 0x15}, {TOK_SKIP, REG_VBLK_STOP_LINE_MSB, 0x00}, - {TOK_SKIP, 0x26, 0x00}, /* Reserved */ - {TOK_SKIP, 0x27, 0x00}, /* Reserved */ + /* Reserved */ + {TOK_SKIP, 0x26, 0x00}, + /* Reserved */ + {TOK_SKIP, 0x27, 0x00}, {TOK_SKIP, REG_FAST_SWTICH_CONTROL, 0xCC}, - {TOK_SKIP, 0x29, 0x00}, /* Reserved */ + /* Reserved */ + {TOK_SKIP, 0x29, 0x00}, {TOK_SKIP, REG_FAST_SWTICH_SCART_DELAY, 0x00}, - {TOK_SKIP, 0x2B, 0x00}, /* Reserved */ + /* Reserved */ + {TOK_SKIP, 0x2B, 0x00}, {TOK_SKIP, REG_SCART_DELAY, 0x00}, {TOK_SKIP, REG_CTI_DELAY, 0x00}, {TOK_SKIP, REG_CTI_CONTROL, 0x00}, - {TOK_SKIP, 0x2F, 0x00}, /* Reserved */ - {TOK_SKIP, 0x30, 0x00}, /* Reserved */ - {TOK_SKIP, 0x31, 0x00}, /* Reserved */ - {TOK_WRITE, REG_SYNC_CONTROL, 0x00}, /* HS, VS active high */ - {TOK_WRITE, REG_OUTPUT_FORMATTER1, 0x00}, /* 10-bit BT.656 */ - {TOK_WRITE, REG_OUTPUT_FORMATTER2, 0x11}, /* Enable clk & data */ - {TOK_WRITE, REG_OUTPUT_FORMATTER3, 0xEE}, /* Enable AVID & FLD */ - {TOK_WRITE, REG_OUTPUT_FORMATTER4, 0xAF}, /* Enable VS & HS */ + /* Reserved */ + {TOK_SKIP, 0x2F, 0x00}, + /* Reserved */ + {TOK_SKIP, 0x30, 0x00}, + /* Reserved */ + {TOK_SKIP, 0x31, 0x00}, + /* HS, VS active high */ + {TOK_WRITE, REG_SYNC_CONTROL, 0x00}, + /* 10-bit BT.656 */ + {TOK_WRITE, REG_OUTPUT_FORMATTER1, 0x00}, + /* Enable clk & data */ + {TOK_WRITE, REG_OUTPUT_FORMATTER2, 0x11}, + /* Enable AVID & FLD */ + {TOK_WRITE, REG_OUTPUT_FORMATTER3, 0xEE}, + /* Enable VS & HS */ + {TOK_WRITE, REG_OUTPUT_FORMATTER4, 0xAF}, {TOK_WRITE, REG_OUTPUT_FORMATTER5, 0xFF}, {TOK_WRITE, REG_OUTPUT_FORMATTER6, 0xFF}, - {TOK_WRITE, REG_CLEAR_LOST_LOCK, 0x01}, /* Clear status */ + /* Clear status */ + {TOK_WRITE, REG_CLEAR_LOST_LOCK, 0x01}, {TOK_TERM, 0, 0}, }; -/* List of image formats supported by TVP5146/47 decoder +/** + * List of image formats supported by TVP5146/47 decoder * Currently we are using 8 bit mode only, but can be * extended to 10/20 bit mode. */ @@ -205,7 +214,7 @@ static const struct v4l2_fmtdesc tvp514x_fmt_list[] = { }, }; -/* +/** * Supported standards - * * Currently supports two standards only, need to add support for rest of the @@ -240,35 +249,32 @@ static struct tvp514x_std_info tvp514x_std_list[] = { }, /* Standard: need to add for additional standard */ }; -/* - * Control structure for Auto Gain - * This is temporary data, will get replaced once - * v4l2_ctrl_query_fill supports it. - */ -static const struct v4l2_queryctrl tvp514x_autogain_ctrl = { - .id = V4L2_CID_AUTOGAIN, - .name = "Gain, Automatic", - .type = V4L2_CTRL_TYPE_BOOLEAN, - .minimum = 0, - .maximum = 1, - .step = 1, - .default_value = 1, -}; -/* - * Read a value from a register in an TVP5146/47 decoder device. + +static inline struct tvp514x_decoder *to_decoder(struct v4l2_subdev *sd) +{ + return container_of(sd, struct tvp514x_decoder, sd); +} + + +/** + * tvp514x_read_reg() - Read a value from a register in an TVP5146/47. + * @sd: ptr to v4l2_subdev struct + * @reg: TVP5146/47 register address + * * Returns value read if successful, or non-zero (-1) otherwise. */ -static int tvp514x_read_reg(struct i2c_client *client, u8 reg) +static int tvp514x_read_reg(struct v4l2_subdev *sd, u8 reg) { - int err; - int retry = 0; + int err, retry = 0; + struct i2c_client *client = v4l2_get_subdevdata(sd); + read_again: err = i2c_smbus_read_byte_data(client, reg); if (err == -1) { if (retry <= I2C_RETRY_COUNT) { - v4l_warn(client, "Read: retry ... %d\n", retry); + v4l2_warn(sd, "Read: retry ... %d\n", retry); retry++; msleep_interruptible(10); goto read_again; @@ -278,20 +284,39 @@ read_again: return err; } -/* +/** + * dump_reg() - dump the register content of TVP5146/47. + * @sd: ptr to v4l2_subdev struct + * @reg: TVP5146/47 register address + */ +static void dump_reg(struct v4l2_subdev *sd, u8 reg) +{ + u32 val; + + val = tvp514x_read_reg(sd, reg); + v4l2_info(sd, "Reg(0x%.2X): 0x%.2X\n", reg, val); +} + +/** + * tvp514x_write_reg() - Write a value to a register in TVP5146/47 + * @sd: ptr to v4l2_subdev struct + * @reg: TVP5146/47 register address + * @val: value to be written to the register + * * Write a value to a register in an TVP5146/47 decoder device. * Returns zero if successful, or non-zero otherwise. */ -static int tvp514x_write_reg(struct i2c_client *client, u8 reg, u8 val) +static int tvp514x_write_reg(struct v4l2_subdev *sd, u8 reg, u8 val) { - int err; - int retry = 0; + int err, retry = 0; + struct i2c_client *client = v4l2_get_subdevdata(sd); + write_again: err = i2c_smbus_write_byte_data(client, reg, val); if (err) { if (retry <= I2C_RETRY_COUNT) { - v4l_warn(client, "Write: retry ... %d\n", retry); + v4l2_warn(sd, "Write: retry ... %d\n", retry); retry++; msleep_interruptible(10); goto write_again; @@ -301,17 +326,19 @@ write_again: return err; } -/* - * tvp514x_write_regs : Initializes a list of TVP5146/47 registers +/** + * tvp514x_write_regs() : Initializes a list of TVP5146/47 registers + * @sd: ptr to v4l2_subdev struct + * @reglist: list of TVP5146/47 registers and values + * + * Initializes a list of TVP5146/47 registers:- * if token is TOK_TERM, then entire write operation terminates * if token is TOK_DELAY, then a delay of 'val' msec is introduced * if token is TOK_SKIP, then the register write is skipped * if token is TOK_WRITE, then the register write is performed - * - * reglist - list of registers to be written * Returns zero if successful, or non-zero otherwise. */ -static int tvp514x_write_regs(struct i2c_client *client, +static int tvp514x_write_regs(struct v4l2_subdev *sd, const struct tvp514x_reg reglist[]) { int err; @@ -326,31 +353,33 @@ static int tvp514x_write_regs(struct i2c_client *client, if (next->token == TOK_SKIP) continue; - err = tvp514x_write_reg(client, next->reg, (u8) next->val); + err = tvp514x_write_reg(sd, next->reg, (u8) next->val); if (err) { - v4l_err(client, "Write failed. Err[%d]\n", err); + v4l2_err(sd, "Write failed. Err[%d]\n", err); return err; } } return 0; } -/* - * tvp514x_get_current_std: - * Returns the current standard detected by TVP5146/47 +/** + * tvp514x_get_current_std() : Get the current standard detected by TVP5146/47 + * @sd: ptr to v4l2_subdev struct + * + * Get current standard detected by TVP5146/47, STD_INVALID if there is no + * standard detected. */ -static enum tvp514x_std tvp514x_get_current_std(struct tvp514x_decoder - *decoder) +static enum tvp514x_std tvp514x_get_current_std(struct v4l2_subdev *sd) { u8 std, std_status; - std = tvp514x_read_reg(decoder->client, REG_VIDEO_STD); - if ((std & VIDEO_STD_MASK) == VIDEO_STD_AUTO_SWITCH_BIT) { + std = tvp514x_read_reg(sd, REG_VIDEO_STD); + if ((std & VIDEO_STD_MASK) == VIDEO_STD_AUTO_SWITCH_BIT) /* use the standard status register */ - std_status = tvp514x_read_reg(decoder->client, - REG_VIDEO_STD_STATUS); - } else - std_status = std; /* use the standard register itself */ + std_status = tvp514x_read_reg(sd, REG_VIDEO_STD_STATUS); + else + /* use the standard register itself */ + std_status = std; switch (std_status & VIDEO_STD_MASK) { case VIDEO_STD_NTSC_MJ_BIT: @@ -366,94 +395,99 @@ static enum tvp514x_std tvp514x_get_current_std(struct tvp514x_decoder return STD_INVALID; } -/* - * TVP5146/47 register dump function - */ -static void tvp514x_reg_dump(struct tvp514x_decoder *decoder) +/* TVP5146/47 register dump function */ +static void tvp514x_reg_dump(struct v4l2_subdev *sd) { - u8 value; - - dump_reg(decoder->client, REG_INPUT_SEL, value); - dump_reg(decoder->client, REG_AFE_GAIN_CTRL, value); - dump_reg(decoder->client, REG_VIDEO_STD, value); - dump_reg(decoder->client, REG_OPERATION_MODE, value); - dump_reg(decoder->client, REG_COLOR_KILLER, value); - dump_reg(decoder->client, REG_LUMA_CONTROL1, value); - dump_reg(decoder->client, REG_LUMA_CONTROL2, value); - dump_reg(decoder->client, REG_LUMA_CONTROL3, value); - dump_reg(decoder->client, REG_BRIGHTNESS, value); - dump_reg(decoder->client, REG_CONTRAST, value); - dump_reg(decoder->client, REG_SATURATION, value); - dump_reg(decoder->client, REG_HUE, value); - dump_reg(decoder->client, REG_CHROMA_CONTROL1, value); - dump_reg(decoder->client, REG_CHROMA_CONTROL2, value); - dump_reg(decoder->client, REG_COMP_PR_SATURATION, value); - dump_reg(decoder->client, REG_COMP_Y_CONTRAST, value); - dump_reg(decoder->client, REG_COMP_PB_SATURATION, value); - dump_reg(decoder->client, REG_COMP_Y_BRIGHTNESS, value); - dump_reg(decoder->client, REG_AVID_START_PIXEL_LSB, value); - dump_reg(decoder->client, REG_AVID_START_PIXEL_MSB, value); - dump_reg(decoder->client, REG_AVID_STOP_PIXEL_LSB, value); - dump_reg(decoder->client, REG_AVID_STOP_PIXEL_MSB, value); - dump_reg(decoder->client, REG_HSYNC_START_PIXEL_LSB, value); - dump_reg(decoder->client, REG_HSYNC_START_PIXEL_MSB, value); - dump_reg(decoder->client, REG_HSYNC_STOP_PIXEL_LSB, value); - dump_reg(decoder->client, REG_HSYNC_STOP_PIXEL_MSB, value); - dump_reg(decoder->client, REG_VSYNC_START_LINE_LSB, value); - dump_reg(decoder->client, REG_VSYNC_START_LINE_MSB, value); - dump_reg(decoder->client, REG_VSYNC_STOP_LINE_LSB, value); - dump_reg(decoder->client, REG_VSYNC_STOP_LINE_MSB, value); - dump_reg(decoder->client, REG_VBLK_START_LINE_LSB, value); - dump_reg(decoder->client, REG_VBLK_START_LINE_MSB, value); - dump_reg(decoder->client, REG_VBLK_STOP_LINE_LSB, value); - dump_reg(decoder->client, REG_VBLK_STOP_LINE_MSB, value); - dump_reg(decoder->client, REG_SYNC_CONTROL, value); - dump_reg(decoder->client, REG_OUTPUT_FORMATTER1, value); - dump_reg(decoder->client, REG_OUTPUT_FORMATTER2, value); - dump_reg(decoder->client, REG_OUTPUT_FORMATTER3, value); - dump_reg(decoder->client, REG_OUTPUT_FORMATTER4, value); - dump_reg(decoder->client, REG_OUTPUT_FORMATTER5, value); - dump_reg(decoder->client, REG_OUTPUT_FORMATTER6, value); - dump_reg(decoder->client, REG_CLEAR_LOST_LOCK, value); + dump_reg(sd, REG_INPUT_SEL); + dump_reg(sd, REG_AFE_GAIN_CTRL); + dump_reg(sd, REG_VIDEO_STD); + dump_reg(sd, REG_OPERATION_MODE); + dump_reg(sd, REG_COLOR_KILLER); + dump_reg(sd, REG_LUMA_CONTROL1); + dump_reg(sd, REG_LUMA_CONTROL2); + dump_reg(sd, REG_LUMA_CONTROL3); + dump_reg(sd, REG_BRIGHTNESS); + dump_reg(sd, REG_CONTRAST); + dump_reg(sd, REG_SATURATION); + dump_reg(sd, REG_HUE); + dump_reg(sd, REG_CHROMA_CONTROL1); + dump_reg(sd, REG_CHROMA_CONTROL2); + dump_reg(sd, REG_COMP_PR_SATURATION); + dump_reg(sd, REG_COMP_Y_CONTRAST); + dump_reg(sd, REG_COMP_PB_SATURATION); + dump_reg(sd, REG_COMP_Y_BRIGHTNESS); + dump_reg(sd, REG_AVID_START_PIXEL_LSB); + dump_reg(sd, REG_AVID_START_PIXEL_MSB); + dump_reg(sd, REG_AVID_STOP_PIXEL_LSB); + dump_reg(sd, REG_AVID_STOP_PIXEL_MSB); + dump_reg(sd, REG_HSYNC_START_PIXEL_LSB); + dump_reg(sd, REG_HSYNC_START_PIXEL_MSB); + dump_reg(sd, REG_HSYNC_STOP_PIXEL_LSB); + dump_reg(sd, REG_HSYNC_STOP_PIXEL_MSB); + dump_reg(sd, REG_VSYNC_START_LINE_LSB); + dump_reg(sd, REG_VSYNC_START_LINE_MSB); + dump_reg(sd, REG_VSYNC_STOP_LINE_LSB); + dump_reg(sd, REG_VSYNC_STOP_LINE_MSB); + dump_reg(sd, REG_VBLK_START_LINE_LSB); + dump_reg(sd, REG_VBLK_START_LINE_MSB); + dump_reg(sd, REG_VBLK_STOP_LINE_LSB); + dump_reg(sd, REG_VBLK_STOP_LINE_MSB); + dump_reg(sd, REG_SYNC_CONTROL); + dump_reg(sd, REG_OUTPUT_FORMATTER1); + dump_reg(sd, REG_OUTPUT_FORMATTER2); + dump_reg(sd, REG_OUTPUT_FORMATTER3); + dump_reg(sd, REG_OUTPUT_FORMATTER4); + dump_reg(sd, REG_OUTPUT_FORMATTER5); + dump_reg(sd, REG_OUTPUT_FORMATTER6); + dump_reg(sd, REG_CLEAR_LOST_LOCK); } -/* - * Configure the TVP5146/47 with the current register settings +/** + * tvp514x_configure() - Configure the TVP5146/47 registers + * @sd: ptr to v4l2_subdev struct + * @decoder: ptr to tvp514x_decoder structure + * * Returns zero if successful, or non-zero otherwise. */ -static int tvp514x_configure(struct tvp514x_decoder *decoder) +static int tvp514x_configure(struct v4l2_subdev *sd, + struct tvp514x_decoder *decoder) { int err; /* common register initialization */ err = - tvp514x_write_regs(decoder->client, decoder->tvp514x_regs); + tvp514x_write_regs(sd, decoder->tvp514x_regs); if (err) return err; if (debug) - tvp514x_reg_dump(decoder); + tvp514x_reg_dump(sd); return 0; } -/* - * Detect if an tvp514x is present, and if so which revision. +/** + * tvp514x_detect() - Detect if an tvp514x is present, and if so which revision. + * @sd: pointer to standard V4L2 sub-device structure + * @decoder: pointer to tvp514x_decoder structure + * * A device is considered to be detected if the chip ID (LSB and MSB) * registers match the expected values. * Any value of the rom version register is accepted. * Returns ENODEV error number if no device is detected, or zero * if a device is detected. */ -static int tvp514x_detect(struct tvp514x_decoder *decoder) +static int tvp514x_detect(struct v4l2_subdev *sd, + struct tvp514x_decoder *decoder) { u8 chip_id_msb, chip_id_lsb, rom_ver; + struct i2c_client *client = v4l2_get_subdevdata(sd); - chip_id_msb = tvp514x_read_reg(decoder->client, REG_CHIP_ID_MSB); - chip_id_lsb = tvp514x_read_reg(decoder->client, REG_CHIP_ID_LSB); - rom_ver = tvp514x_read_reg(decoder->client, REG_ROM_VERSION); + chip_id_msb = tvp514x_read_reg(sd, REG_CHIP_ID_MSB); + chip_id_lsb = tvp514x_read_reg(sd, REG_CHIP_ID_LSB); + rom_ver = tvp514x_read_reg(sd, REG_ROM_VERSION); - v4l_dbg(1, debug, decoder->client, + v4l2_dbg(1, debug, sd, "chip id detected msb:0x%x lsb:0x%x rom version:0x%x\n", chip_id_msb, chip_id_lsb, rom_ver); if ((chip_id_msb != TVP514X_CHIP_ID_MSB) @@ -462,38 +496,30 @@ static int tvp514x_detect(struct tvp514x_decoder *decoder) /* We didn't read the values we expected, so this must not be * an TVP5146/47. */ - v4l_err(decoder->client, - "chip id mismatch msb:0x%x lsb:0x%x\n", - chip_id_msb, chip_id_lsb); + v4l2_err(sd, "chip id mismatch msb:0x%x lsb:0x%x\n", + chip_id_msb, chip_id_lsb); return -ENODEV; } decoder->ver = rom_ver; - decoder->state = STATE_DETECTED; - v4l_info(decoder->client, - "%s found at 0x%x (%s)\n", decoder->client->name, - decoder->client->addr << 1, - decoder->client->adapter->name); + v4l2_info(sd, "%s (Version - 0x%.2x) found at 0x%x (%s)\n", + client->name, decoder->ver, + client->addr << 1, client->adapter->name); return 0; } -/* - * Following are decoder interface functions implemented by - * TVP5146/47 decoder driver. - */ - /** - * ioctl_querystd - V4L2 decoder interface handler for VIDIOC_QUERYSTD ioctl - * @s: pointer to standard V4L2 device structure + * tvp514x_querystd() - V4L2 decoder interface handler for querystd + * @sd: pointer to standard V4L2 sub-device structure * @std_id: standard V4L2 std_id ioctl enum * * Returns the current standard detected by TVP5146/47. If no active input is * detected, returns -EINVAL */ -static int ioctl_querystd(struct v4l2_int_device *s, v4l2_std_id *std_id) +static int tvp514x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std_id) { - struct tvp514x_decoder *decoder = s->priv; + struct tvp514x_decoder *decoder = to_decoder(sd); enum tvp514x_std current_std; enum tvp514x_input input_sel; u8 sync_lock_status, lock_mask; @@ -502,11 +528,11 @@ static int ioctl_querystd(struct v4l2_int_device *s, v4l2_std_id *std_id) return -EINVAL; /* get the current standard */ - current_std = tvp514x_get_current_std(decoder); + current_std = tvp514x_get_current_std(sd); if (current_std == STD_INVALID) return -EINVAL; - input_sel = decoder->route.input; + input_sel = decoder->input; switch (input_sel) { case INPUT_CVBS_VI1A: @@ -544,42 +570,39 @@ static int ioctl_querystd(struct v4l2_int_device *s, v4l2_std_id *std_id) return -EINVAL; } /* check whether signal is locked */ - sync_lock_status = tvp514x_read_reg(decoder->client, REG_STATUS1); + sync_lock_status = tvp514x_read_reg(sd, REG_STATUS1); if (lock_mask != (sync_lock_status & lock_mask)) return -EINVAL; /* No input detected */ decoder->current_std = current_std; *std_id = decoder->std_list[current_std].standard.id; - v4l_dbg(1, debug, decoder->client, "Current STD: %s", + v4l2_dbg(1, debug, sd, "Current STD: %s", decoder->std_list[current_std].standard.name); return 0; } /** - * ioctl_s_std - V4L2 decoder interface handler for VIDIOC_S_STD ioctl - * @s: pointer to standard V4L2 device structure + * tvp514x_s_std() - V4L2 decoder interface handler for s_std + * @sd: pointer to standard V4L2 sub-device structure * @std_id: standard V4L2 v4l2_std_id ioctl enum * * If std_id is supported, sets the requested standard. Otherwise, returns * -EINVAL */ -static int ioctl_s_std(struct v4l2_int_device *s, v4l2_std_id *std_id) +static int tvp514x_s_std(struct v4l2_subdev *sd, v4l2_std_id std_id) { - struct tvp514x_decoder *decoder = s->priv; + struct tvp514x_decoder *decoder = to_decoder(sd); int err, i; - if (std_id == NULL) - return -EINVAL; - for (i = 0; i < decoder->num_stds; i++) - if (*std_id & decoder->std_list[i].standard.id) + if (std_id & decoder->std_list[i].standard.id) break; if ((i == decoder->num_stds) || (i == STD_INVALID)) return -EINVAL; - err = tvp514x_write_reg(decoder->client, REG_VIDEO_STD, + err = tvp514x_write_reg(sd, REG_VIDEO_STD, decoder->std_list[i].video_std); if (err) return err; @@ -588,24 +611,26 @@ static int ioctl_s_std(struct v4l2_int_device *s, v4l2_std_id *std_id) decoder->tvp514x_regs[REG_VIDEO_STD].val = decoder->std_list[i].video_std; - v4l_dbg(1, debug, decoder->client, "Standard set to: %s", + v4l2_dbg(1, debug, sd, "Standard set to: %s", decoder->std_list[i].standard.name); return 0; } /** - * ioctl_s_routing - V4L2 decoder interface handler for VIDIOC_S_INPUT ioctl - * @s: pointer to standard V4L2 device structure - * @index: number of the input + * tvp514x_s_routing() - V4L2 decoder interface handler for s_routing + * @sd: pointer to standard V4L2 sub-device structure + * @input: input selector for routing the signal + * @output: output selector for routing the signal + * @config: config value. Not used * * If index is valid, selects the requested input. Otherwise, returns -EINVAL if * the input is not supported or there is no active signal present in the * selected input. */ -static int ioctl_s_routing(struct v4l2_int_device *s, - struct v4l2_routing *route) +static int tvp514x_s_routing(struct v4l2_subdev *sd, + u32 input, u32 output, u32 config) { - struct tvp514x_decoder *decoder = s->priv; + struct tvp514x_decoder *decoder = to_decoder(sd); int err; enum tvp514x_input input_sel; enum tvp514x_output output_sel; @@ -613,20 +638,21 @@ static int ioctl_s_routing(struct v4l2_int_device *s, u8 sync_lock_status, lock_mask; int try_count = LOCK_RETRY_COUNT; - if ((!route) || (route->input >= INPUT_INVALID) || - (route->output >= OUTPUT_INVALID)) - return -EINVAL; /* Index out of bound */ + if ((input >= INPUT_INVALID) || + (output >= OUTPUT_INVALID)) + /* Index out of bound */ + return -EINVAL; - input_sel = route->input; - output_sel = route->output; + input_sel = input; + output_sel = output; - err = tvp514x_write_reg(decoder->client, REG_INPUT_SEL, input_sel); + err = tvp514x_write_reg(sd, REG_INPUT_SEL, input_sel); if (err) return err; - output_sel |= tvp514x_read_reg(decoder->client, + output_sel |= tvp514x_read_reg(sd, REG_OUTPUT_FORMATTER1) & 0x7; - err = tvp514x_write_reg(decoder->client, REG_OUTPUT_FORMATTER1, + err = tvp514x_write_reg(sd, REG_OUTPUT_FORMATTER1, output_sel); if (err) return err; @@ -637,7 +663,7 @@ static int ioctl_s_routing(struct v4l2_int_device *s, /* Clear status */ msleep(LOCK_RETRY_DELAY); err = - tvp514x_write_reg(decoder->client, REG_CLEAR_LOST_LOCK, 0x01); + tvp514x_write_reg(sd, REG_CLEAR_LOST_LOCK, 0x01); if (err) return err; @@ -672,7 +698,7 @@ static int ioctl_s_routing(struct v4l2_int_device *s, lock_mask = STATUS_HORZ_SYNC_LOCK_BIT | STATUS_VIRT_SYNC_LOCK_BIT; break; - /*Need to add other interfaces*/ + /* Need to add other interfaces*/ default: return -EINVAL; } @@ -682,42 +708,41 @@ static int ioctl_s_routing(struct v4l2_int_device *s, msleep(LOCK_RETRY_DELAY); /* get the current standard for future reference */ - current_std = tvp514x_get_current_std(decoder); + current_std = tvp514x_get_current_std(sd); if (current_std == STD_INVALID) continue; - sync_lock_status = tvp514x_read_reg(decoder->client, + sync_lock_status = tvp514x_read_reg(sd, REG_STATUS1); if (lock_mask == (sync_lock_status & lock_mask)) - break; /* Input detected */ + /* Input detected */ + break; } if ((current_std == STD_INVALID) || (try_count < 0)) return -EINVAL; decoder->current_std = current_std; - decoder->route.input = route->input; - decoder->route.output = route->output; + decoder->input = input; + decoder->output = output; - v4l_dbg(1, debug, decoder->client, - "Input set to: %d, std : %d", + v4l2_dbg(1, debug, sd, "Input set to: %d, std : %d", input_sel, current_std); return 0; } /** - * ioctl_queryctrl - V4L2 decoder interface handler for VIDIOC_QUERYCTRL ioctl - * @s: pointer to standard V4L2 device structure + * tvp514x_queryctrl() - V4L2 decoder interface handler for queryctrl + * @sd: pointer to standard V4L2 sub-device structure * @qctrl: standard V4L2 v4l2_queryctrl structure * * If the requested control is supported, returns the control information. * Otherwise, returns -EINVAL if the control is not supported. */ static int -ioctl_queryctrl(struct v4l2_int_device *s, struct v4l2_queryctrl *qctrl) +tvp514x_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qctrl) { - struct tvp514x_decoder *decoder = s->priv; int err = -EINVAL; if (qctrl == NULL) @@ -725,13 +750,13 @@ ioctl_queryctrl(struct v4l2_int_device *s, struct v4l2_queryctrl *qctrl) switch (qctrl->id) { case V4L2_CID_BRIGHTNESS: - /* Brightness supported is (0-255), - */ + /* Brightness supported is (0-255), */ err = v4l2_ctrl_query_fill(qctrl, 0, 255, 1, 128); break; case V4L2_CID_CONTRAST: case V4L2_CID_SATURATION: - /* Saturation and Contrast supported is - + /** + * Saturation and Contrast supported is - * Contrast: 0 - 255 (Default - 128) * Saturation: 0 - 255 (Default - 128) */ @@ -744,30 +769,27 @@ ioctl_queryctrl(struct v4l2_int_device *s, struct v4l2_queryctrl *qctrl) err = v4l2_ctrl_query_fill(qctrl, -180, 180, 180, 0); break; case V4L2_CID_AUTOGAIN: - /* Autogain is either 0 or 1*/ - memcpy(qctrl, &tvp514x_autogain_ctrl, - sizeof(struct v4l2_queryctrl)); - err = 0; + /** + * Auto Gain supported is - + * 0 - 1 (Default - 1) + */ + err = v4l2_ctrl_query_fill(qctrl, 0, 1, 1, 1); break; default: - v4l_err(decoder->client, - "invalid control id %d\n", qctrl->id); + v4l2_err(sd, "invalid control id %d\n", qctrl->id); return err; } - v4l_dbg(1, debug, decoder->client, - "Query Control: %s : Min - %d, Max - %d, Def - %d", - qctrl->name, - qctrl->minimum, - qctrl->maximum, + v4l2_dbg(1, debug, sd, "Query Control:%s: Min - %d, Max - %d, Def - %d", + qctrl->name, qctrl->minimum, qctrl->maximum, qctrl->default_value); return err; } /** - * ioctl_g_ctrl - V4L2 decoder interface handler for VIDIOC_G_CTRL ioctl - * @s: pointer to standard V4L2 device structure + * tvp514x_g_ctrl() - V4L2 decoder interface handler for g_ctrl + * @sd: pointer to standard V4L2 sub-device structure * @ctrl: pointer to v4l2_control structure * * If the requested control is supported, returns the control's current @@ -775,9 +797,9 @@ ioctl_queryctrl(struct v4l2_int_device *s, struct v4l2_queryctrl *qctrl) * supported. */ static int -ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *ctrl) +tvp514x_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) { - struct tvp514x_decoder *decoder = s->priv; + struct tvp514x_decoder *decoder = to_decoder(sd); if (ctrl == NULL) return -EINVAL; @@ -811,74 +833,70 @@ ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *ctrl) break; default: - v4l_err(decoder->client, - "invalid control id %d\n", ctrl->id); + v4l2_err(sd, "invalid control id %d\n", ctrl->id); return -EINVAL; } - v4l_dbg(1, debug, decoder->client, - "Get Control: ID - %d - %d", + v4l2_dbg(1, debug, sd, "Get Control: ID - %d - %d", ctrl->id, ctrl->value); return 0; } /** - * ioctl_s_ctrl - V4L2 decoder interface handler for VIDIOC_S_CTRL ioctl - * @s: pointer to standard V4L2 device structure + * tvp514x_s_ctrl() - V4L2 decoder interface handler for s_ctrl + * @sd: pointer to standard V4L2 sub-device structure * @ctrl: pointer to v4l2_control structure * * If the requested control is supported, sets the control's current * value in HW. Otherwise, returns -EINVAL if the control is not supported. */ static int -ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *ctrl) +tvp514x_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) { - struct tvp514x_decoder *decoder = s->priv; + struct tvp514x_decoder *decoder = to_decoder(sd); int err = -EINVAL, value; if (ctrl == NULL) return err; - value = (__s32) ctrl->value; + value = ctrl->value; switch (ctrl->id) { case V4L2_CID_BRIGHTNESS: if (ctrl->value < 0 || ctrl->value > 255) { - v4l_err(decoder->client, - "invalid brightness setting %d\n", + v4l2_err(sd, "invalid brightness setting %d\n", ctrl->value); return -ERANGE; } - err = tvp514x_write_reg(decoder->client, REG_BRIGHTNESS, + err = tvp514x_write_reg(sd, REG_BRIGHTNESS, value); if (err) return err; + decoder->tvp514x_regs[REG_BRIGHTNESS].val = value; break; case V4L2_CID_CONTRAST: if (ctrl->value < 0 || ctrl->value > 255) { - v4l_err(decoder->client, - "invalid contrast setting %d\n", + v4l2_err(sd, "invalid contrast setting %d\n", ctrl->value); return -ERANGE; } - err = tvp514x_write_reg(decoder->client, REG_CONTRAST, - value); + err = tvp514x_write_reg(sd, REG_CONTRAST, value); if (err) return err; + decoder->tvp514x_regs[REG_CONTRAST].val = value; break; case V4L2_CID_SATURATION: if (ctrl->value < 0 || ctrl->value > 255) { - v4l_err(decoder->client, - "invalid saturation setting %d\n", + v4l2_err(sd, "invalid saturation setting %d\n", ctrl->value); return -ERANGE; } - err = tvp514x_write_reg(decoder->client, REG_SATURATION, - value); + err = tvp514x_write_reg(sd, REG_SATURATION, value); if (err) return err; + decoder->tvp514x_regs[REG_SATURATION].val = value; break; case V4L2_CID_HUE: @@ -889,15 +907,13 @@ ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *ctrl) else if (value == 0) value = 0; else { - v4l_err(decoder->client, - "invalid hue setting %d\n", - ctrl->value); + v4l2_err(sd, "invalid hue setting %d\n", ctrl->value); return -ERANGE; } - err = tvp514x_write_reg(decoder->client, REG_HUE, - value); + err = tvp514x_write_reg(sd, REG_HUE, value); if (err) return err; + decoder->tvp514x_regs[REG_HUE].val = value; break; case V4L2_CID_AUTOGAIN: @@ -906,41 +922,38 @@ ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *ctrl) else if (value == 0) value = 0x0C; else { - v4l_err(decoder->client, - "invalid auto gain setting %d\n", + v4l2_err(sd, "invalid auto gain setting %d\n", ctrl->value); return -ERANGE; } - err = tvp514x_write_reg(decoder->client, REG_AFE_GAIN_CTRL, - value); + err = tvp514x_write_reg(sd, REG_AFE_GAIN_CTRL, value); if (err) return err; + decoder->tvp514x_regs[REG_AFE_GAIN_CTRL].val = value; break; default: - v4l_err(decoder->client, - "invalid control id %d\n", ctrl->id); + v4l2_err(sd, "invalid control id %d\n", ctrl->id); return err; } - v4l_dbg(1, debug, decoder->client, - "Set Control: ID - %d - %d", + v4l2_dbg(1, debug, sd, "Set Control: ID - %d - %d", ctrl->id, ctrl->value); return err; } /** - * ioctl_enum_fmt_cap - Implement the CAPTURE buffer VIDIOC_ENUM_FMT ioctl - * @s: pointer to standard V4L2 device structure + * tvp514x_enum_fmt_cap() - V4L2 decoder interface handler for enum_fmt + * @sd: pointer to standard V4L2 sub-device structure * @fmt: standard V4L2 VIDIOC_ENUM_FMT ioctl structure * * Implement the VIDIOC_ENUM_FMT ioctl to enumerate supported formats */ static int -ioctl_enum_fmt_cap(struct v4l2_int_device *s, struct v4l2_fmtdesc *fmt) +tvp514x_enum_fmt_cap(struct v4l2_subdev *sd, struct v4l2_fmtdesc *fmt) { - struct tvp514x_decoder *decoder = s->priv; + struct tvp514x_decoder *decoder = to_decoder(sd); int index; if (fmt == NULL) @@ -948,24 +961,25 @@ ioctl_enum_fmt_cap(struct v4l2_int_device *s, struct v4l2_fmtdesc *fmt) index = fmt->index; if ((index >= decoder->num_fmts) || (index < 0)) - return -EINVAL; /* Index out of bound */ + /* Index out of bound */ + return -EINVAL; if (fmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) - return -EINVAL; /* only capture is supported */ + /* only capture is supported */ + return -EINVAL; memcpy(fmt, &decoder->fmt_list[index], sizeof(struct v4l2_fmtdesc)); - v4l_dbg(1, debug, decoder->client, - "Current FMT: index - %d (%s)", + v4l2_dbg(1, debug, sd, "Current FMT: index - %d (%s)", decoder->fmt_list[index].index, decoder->fmt_list[index].description); return 0; } /** - * ioctl_try_fmt_cap - Implement the CAPTURE buffer VIDIOC_TRY_FMT ioctl - * @s: pointer to standard V4L2 device structure + * tvp514x_try_fmt_cap() - V4L2 decoder interface handler for try_fmt + * @sd: pointer to standard V4L2 sub-device structure * @f: pointer to standard V4L2 VIDIOC_TRY_FMT ioctl structure * * Implement the VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type. This @@ -973,9 +987,9 @@ ioctl_enum_fmt_cap(struct v4l2_int_device *s, struct v4l2_fmtdesc *fmt) * without actually making it take effect. */ static int -ioctl_try_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +tvp514x_try_fmt_cap(struct v4l2_subdev *sd, struct v4l2_format *f) { - struct tvp514x_decoder *decoder = s->priv; + struct tvp514x_decoder *decoder = to_decoder(sd); int ifmt; struct v4l2_pix_format *pix; enum tvp514x_std current_std; @@ -984,12 +998,13 @@ ioctl_try_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) return -EINVAL; if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + /* only capture is supported */ f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; pix = &f->fmt.pix; /* Calculate height and width based on current standard */ - current_std = tvp514x_get_current_std(decoder); + current_std = tvp514x_get_current_std(sd); if (current_std == STD_INVALID) return -EINVAL; @@ -1003,7 +1018,8 @@ ioctl_try_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) break; } if (ifmt == decoder->num_fmts) - ifmt = 0; /* None of the format matched, select default */ + /* None of the format matched, select default */ + ifmt = 0; pix->pixelformat = decoder->fmt_list[ifmt].pixelformat; pix->field = V4L2_FIELD_INTERLACED; @@ -1012,8 +1028,7 @@ ioctl_try_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) pix->colorspace = V4L2_COLORSPACE_SMPTE170M; pix->priv = 0; - v4l_dbg(1, debug, decoder->client, - "Try FMT: pixelformat - %s, bytesperline - %d" + v4l2_dbg(1, debug, sd, "Try FMT: pixelformat - %s, bytesperline - %d" "Width - %d, Height - %d", decoder->fmt_list[ifmt].description, pix->bytesperline, pix->width, pix->height); @@ -1021,8 +1036,8 @@ ioctl_try_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) } /** - * ioctl_s_fmt_cap - V4L2 decoder interface handler for VIDIOC_S_FMT ioctl - * @s: pointer to standard V4L2 device structure + * tvp514x_s_fmt_cap() - V4L2 decoder interface handler for s_fmt + * @sd: pointer to standard V4L2 sub-device structure * @f: pointer to standard V4L2 VIDIOC_S_FMT ioctl structure * * If the requested format is supported, configures the HW to use that @@ -1030,9 +1045,9 @@ ioctl_try_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) * correctly configured. */ static int -ioctl_s_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +tvp514x_s_fmt_cap(struct v4l2_subdev *sd, struct v4l2_format *f) { - struct tvp514x_decoder *decoder = s->priv; + struct tvp514x_decoder *decoder = to_decoder(sd); struct v4l2_pix_format *pix; int rval; @@ -1040,10 +1055,11 @@ ioctl_s_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) return -EINVAL; if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) - return -EINVAL; /* only capture is supported */ + /* only capture is supported */ + return -EINVAL; pix = &f->fmt.pix; - rval = ioctl_try_fmt_cap(s, f); + rval = tvp514x_try_fmt_cap(sd, f); if (rval) return rval; @@ -1053,28 +1069,28 @@ ioctl_s_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) } /** - * ioctl_g_fmt_cap - V4L2 decoder interface handler for ioctl_g_fmt_cap - * @s: pointer to standard V4L2 device structure + * tvp514x_g_fmt_cap() - V4L2 decoder interface handler for tvp514x_g_fmt_cap + * @sd: pointer to standard V4L2 sub-device structure * @f: pointer to standard V4L2 v4l2_format structure * * Returns the decoder's current pixel format in the v4l2_format * parameter. */ static int -ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +tvp514x_g_fmt_cap(struct v4l2_subdev *sd, struct v4l2_format *f) { - struct tvp514x_decoder *decoder = s->priv; + struct tvp514x_decoder *decoder = to_decoder(sd); if (f == NULL) return -EINVAL; if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) - return -EINVAL; /* only capture is supported */ + /* only capture is supported */ + return -EINVAL; f->fmt.pix = decoder->pix; - v4l_dbg(1, debug, decoder->client, - "Current FMT: bytesperline - %d" + v4l2_dbg(1, debug, sd, "Current FMT: bytesperline - %d" "Width - %d, Height - %d", decoder->pix.bytesperline, decoder->pix.width, decoder->pix.height); @@ -1082,16 +1098,16 @@ ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) } /** - * ioctl_g_parm - V4L2 decoder interface handler for VIDIOC_G_PARM ioctl - * @s: pointer to standard V4L2 device structure + * tvp514x_g_parm() - V4L2 decoder interface handler for g_parm + * @sd: pointer to standard V4L2 sub-device structure * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure * * Returns the decoder's video CAPTURE parameters. */ static int -ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +tvp514x_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a) { - struct tvp514x_decoder *decoder = s->priv; + struct tvp514x_decoder *decoder = to_decoder(sd); struct v4l2_captureparm *cparm; enum tvp514x_std current_std; @@ -1099,13 +1115,14 @@ ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) return -EINVAL; if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) - return -EINVAL; /* only capture is supported */ + /* only capture is supported */ + return -EINVAL; memset(a, 0, sizeof(*a)); a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; /* get the current standard */ - current_std = tvp514x_get_current_std(decoder); + current_std = tvp514x_get_current_std(sd); if (current_std == STD_INVALID) return -EINVAL; @@ -1120,17 +1137,17 @@ ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) } /** - * ioctl_s_parm - V4L2 decoder interface handler for VIDIOC_S_PARM ioctl - * @s: pointer to standard V4L2 device structure + * tvp514x_s_parm() - V4L2 decoder interface handler for s_parm + * @sd: pointer to standard V4L2 sub-device structure * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure * * Configures the decoder to use the input parameters, if possible. If * not possible, returns the appropriate error code. */ static int -ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +tvp514x_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a) { - struct tvp514x_decoder *decoder = s->priv; + struct tvp514x_decoder *decoder = to_decoder(sd); struct v4l2_fract *timeperframe; enum tvp514x_std current_std; @@ -1138,12 +1155,13 @@ ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) return -EINVAL; if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) - return -EINVAL; /* only capture is supported */ + /* only capture is supported */ + return -EINVAL; timeperframe = &a->parm.capture.timeperframe; /* get the current standard */ - current_std = tvp514x_get_current_std(decoder); + current_std = tvp514x_get_current_std(sd); if (current_std == STD_INVALID) return -EINVAL; @@ -1156,111 +1174,58 @@ ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) } /** - * ioctl_g_ifparm - V4L2 decoder interface handler for vidioc_int_g_ifparm_num - * @s: pointer to standard V4L2 device structure - * @p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure - * - * Gets slave interface parameters. - * Calculates the required xclk value to support the requested - * clock parameters in p. This value is returned in the p - * parameter. - */ -static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) -{ - struct tvp514x_decoder *decoder = s->priv; - int rval; - - if (p == NULL) - return -EINVAL; - - if (NULL == decoder->pdata->ifparm) - return -EINVAL; - - rval = decoder->pdata->ifparm(p); - if (rval) { - v4l_err(decoder->client, "g_ifparm.Err[%d]\n", rval); - return rval; - } - - p->u.bt656.clock_curr = TVP514X_XCLK_BT656; - - return 0; -} - -/** - * ioctl_g_priv - V4L2 decoder interface handler for vidioc_int_g_priv_num - * @s: pointer to standard V4L2 device structure - * @p: void pointer to hold decoder's private data address - * - * Returns device's (decoder's) private data area address in p parameter - */ -static int ioctl_g_priv(struct v4l2_int_device *s, void *p) -{ - struct tvp514x_decoder *decoder = s->priv; - - if (NULL == decoder->pdata->priv_data_set) - return -EINVAL; - - return decoder->pdata->priv_data_set(p); -} - -/** - * ioctl_s_power - V4L2 decoder interface handler for vidioc_int_s_power_num - * @s: pointer to standard V4L2 device structure - * @on: power state to which device is to be set + * tvp514x_s_stream() - V4L2 decoder i/f handler for s_stream + * @sd: pointer to standard V4L2 sub-device structure + * @enable: streaming enable or disable * - * Sets devices power state to requrested state, if possible. + * Sets streaming to enable or disable, if possible. */ -static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) +static int tvp514x_s_stream(struct v4l2_subdev *sd, int enable) { - struct tvp514x_decoder *decoder = s->priv; int err = 0; + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct tvp514x_decoder *decoder = to_decoder(sd); - switch (on) { - case V4L2_POWER_OFF: - /* Power Down Sequence */ - err = - tvp514x_write_reg(decoder->client, REG_OPERATION_MODE, - 0x01); - /* Disable mux for TVP5146/47 decoder data path */ - if (decoder->pdata->power_set) - err |= decoder->pdata->power_set(on); - decoder->state = STATE_NOT_DETECTED; - break; + if (decoder->streaming == enable) + return 0; - case V4L2_POWER_STANDBY: - if (decoder->pdata->power_set) - err = decoder->pdata->power_set(on); + switch (enable) { + case 0: + { + /* Power Down Sequence */ + err = tvp514x_write_reg(sd, REG_OPERATION_MODE, 0x01); + if (err) { + v4l2_err(sd, "Unable to turn off decoder\n"); + return err; + } + decoder->streaming = enable; break; + } + case 1: + { + struct tvp514x_reg *int_seq = (struct tvp514x_reg *) + client->driver->id_table->driver_data; - case V4L2_POWER_ON: - /* Enable mux for TVP5146/47 decoder data path */ - if ((decoder->pdata->power_set) && - (decoder->state == STATE_NOT_DETECTED)) { - int i; - struct tvp514x_init_seq *int_seq = - (struct tvp514x_init_seq *) - decoder->id->driver_data; - - err = decoder->pdata->power_set(on); - - /* Power Up Sequence */ - for (i = 0; i < int_seq->no_regs; i++) { - err |= tvp514x_write_reg(decoder->client, - int_seq->init_reg_seq[i].reg, - int_seq->init_reg_seq[i].val); - } - /* Detect the sensor is not already detected */ - err |= tvp514x_detect(decoder); - if (err) { - v4l_err(decoder->client, - "Unable to detect decoder\n"); - return err; - } + /* Power Up Sequence */ + err = tvp514x_write_regs(sd, int_seq); + if (err) { + v4l2_err(sd, "Unable to turn on decoder\n"); + return err; } - err |= tvp514x_configure(decoder); + /* Detect if not already detected */ + err = tvp514x_detect(sd, decoder); + if (err) { + v4l2_err(sd, "Unable to detect decoder\n"); + return err; + } + err = tvp514x_configure(sd, decoder); + if (err) { + v4l2_err(sd, "Unable to configure decoder\n"); + return err; + } + decoder->streaming = enable; break; - + } default: err = -ENODEV; break; @@ -1269,93 +1234,38 @@ static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) return err; } -/** - * ioctl_init - V4L2 decoder interface handler for VIDIOC_INT_INIT - * @s: pointer to standard V4L2 device structure - * - * Initialize the decoder device (calls tvp514x_configure()) - */ -static int ioctl_init(struct v4l2_int_device *s) -{ - struct tvp514x_decoder *decoder = s->priv; - - /* Set default standard to auto */ - decoder->tvp514x_regs[REG_VIDEO_STD].val = - VIDEO_STD_AUTO_SWITCH_BIT; - - return tvp514x_configure(decoder); -} - -/** - * ioctl_dev_exit - V4L2 decoder interface handler for vidioc_int_dev_exit_num - * @s: pointer to standard V4L2 device structure - * - * Delinitialise the dev. at slave detach. The complement of ioctl_dev_init. - */ -static int ioctl_dev_exit(struct v4l2_int_device *s) -{ - return 0; -} - -/** - * ioctl_dev_init - V4L2 decoder interface handler for vidioc_int_dev_init_num - * @s: pointer to standard V4L2 device structure - * - * Initialise the device when slave attaches to the master. Returns 0 if - * TVP5146/47 device could be found, otherwise returns appropriate error. - */ -static int ioctl_dev_init(struct v4l2_int_device *s) -{ - struct tvp514x_decoder *decoder = s->priv; - int err; - - err = tvp514x_detect(decoder); - if (err < 0) { - v4l_err(decoder->client, - "Unable to detect decoder\n"); - return err; - } - - v4l_info(decoder->client, - "chip version 0x%.2x detected\n", decoder->ver); +static const struct v4l2_subdev_core_ops tvp514x_core_ops = { + .queryctrl = tvp514x_queryctrl, + .g_ctrl = tvp514x_g_ctrl, + .s_ctrl = tvp514x_s_ctrl, + .s_std = tvp514x_s_std, +}; - return 0; -} +static const struct v4l2_subdev_video_ops tvp514x_video_ops = { + .s_routing = tvp514x_s_routing, + .querystd = tvp514x_querystd, + .enum_fmt = tvp514x_enum_fmt_cap, + .g_fmt = tvp514x_g_fmt_cap, + .try_fmt = tvp514x_try_fmt_cap, + .s_fmt = tvp514x_s_fmt_cap, + .g_parm = tvp514x_g_parm, + .s_parm = tvp514x_s_parm, + .s_stream = tvp514x_s_stream, +}; -static struct v4l2_int_ioctl_desc tvp514x_ioctl_desc[] = { - {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*) ioctl_dev_init}, - {vidioc_int_dev_exit_num, (v4l2_int_ioctl_func*) ioctl_dev_exit}, - {vidioc_int_s_power_num, (v4l2_int_ioctl_func*) ioctl_s_power}, - {vidioc_int_g_priv_num, (v4l2_int_ioctl_func*) ioctl_g_priv}, - {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*) ioctl_g_ifparm}, - {vidioc_int_init_num, (v4l2_int_ioctl_func*) ioctl_init}, - {vidioc_int_enum_fmt_cap_num, - (v4l2_int_ioctl_func *) ioctl_enum_fmt_cap}, - {vidioc_int_try_fmt_cap_num, - (v4l2_int_ioctl_func *) ioctl_try_fmt_cap}, - {vidioc_int_g_fmt_cap_num, - (v4l2_int_ioctl_func *) ioctl_g_fmt_cap}, - {vidioc_int_s_fmt_cap_num, - (v4l2_int_ioctl_func *) ioctl_s_fmt_cap}, - {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *) ioctl_g_parm}, - {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *) ioctl_s_parm}, - {vidioc_int_queryctrl_num, - (v4l2_int_ioctl_func *) ioctl_queryctrl}, - {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *) ioctl_g_ctrl}, - {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *) ioctl_s_ctrl}, - {vidioc_int_querystd_num, (v4l2_int_ioctl_func *) ioctl_querystd}, - {vidioc_int_s_std_num, (v4l2_int_ioctl_func *) ioctl_s_std}, - {vidioc_int_s_video_routing_num, - (v4l2_int_ioctl_func *) ioctl_s_routing}, +static const struct v4l2_subdev_ops tvp514x_ops = { + .core = &tvp514x_core_ops, + .video = &tvp514x_video_ops, }; static struct tvp514x_decoder tvp514x_dev = { - .state = STATE_NOT_DETECTED, + .streaming = 0, .fmt_list = tvp514x_fmt_list, .num_fmts = ARRAY_SIZE(tvp514x_fmt_list), - .pix = { /* Default to NTSC 8-bit YUV 422 */ + .pix = { + /* Default to NTSC 8-bit YUV 422 */ .width = NTSC_NUM_ACTIVE_PIXELS, .height = NTSC_NUM_ACTIVE_LINES, .pixelformat = V4L2_PIX_FMT_UYVY, @@ -1369,20 +1279,13 @@ static struct tvp514x_decoder tvp514x_dev = { .current_std = STD_NTSC_MJ, .std_list = tvp514x_std_list, .num_stds = ARRAY_SIZE(tvp514x_std_list), - .v4l2_int_device = { - .module = THIS_MODULE, - .name = TVP514X_MODULE_NAME, - .type = v4l2_int_type_slave, - }, - .tvp514x_slave = { - .ioctls = tvp514x_ioctl_desc, - .num_ioctls = ARRAY_SIZE(tvp514x_ioctl_desc), - }, + }; /** - * tvp514x_probe - decoder driver i2c probe handler + * tvp514x_probe() - decoder driver i2c probe handler * @client: i2c driver client device structure + * @id: i2c driver id table * * Register decoder as an i2c client device and V4L2 * device. @@ -1391,88 +1294,71 @@ static int tvp514x_probe(struct i2c_client *client, const struct i2c_device_id *id) { struct tvp514x_decoder *decoder; - int err; + struct v4l2_subdev *sd; /* Check if the adapter supports the needed features */ if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) return -EIO; + if (!client->dev.platform_data) { + v4l2_err(client, "No platform data!!\n"); + return -ENODEV; + } + decoder = kzalloc(sizeof(*decoder), GFP_KERNEL); if (!decoder) return -ENOMEM; - if (!client->dev.platform_data) { - v4l_err(client, "No platform data!!\n"); - err = -ENODEV; - goto out_free; - } - + /* Initialize the tvp514x_decoder with default configuration */ *decoder = tvp514x_dev; - decoder->v4l2_int_device.priv = decoder; - decoder->pdata = client->dev.platform_data; - decoder->v4l2_int_device.u.slave = &decoder->tvp514x_slave; + /* Copy default register configuration */ memcpy(decoder->tvp514x_regs, tvp514x_reg_list_default, sizeof(tvp514x_reg_list_default)); - /* + + /* Copy board specific information here */ + decoder->pdata = client->dev.platform_data; + + /** * Fetch platform specific data, and configure the * tvp514x_reg_list[] accordingly. Since this is one * time configuration, no need to preserve. */ decoder->tvp514x_regs[REG_OUTPUT_FORMATTER2].val |= - (decoder->pdata->clk_polarity << 1); + (decoder->pdata->clk_polarity << 1); decoder->tvp514x_regs[REG_SYNC_CONTROL].val |= - ((decoder->pdata->hs_polarity << 2) | - (decoder->pdata->vs_polarity << 3)); - /* - * Save the id data, required for power up sequence - */ - decoder->id = (struct i2c_device_id *)id; - /* Attach to Master */ - strcpy(decoder->v4l2_int_device.u.slave->attach_to, - decoder->pdata->master); - decoder->client = client; - i2c_set_clientdata(client, decoder); + ((decoder->pdata->hs_polarity << 2) | + (decoder->pdata->vs_polarity << 3)); + /* Set default standard to auto */ + decoder->tvp514x_regs[REG_VIDEO_STD].val = + VIDEO_STD_AUTO_SWITCH_BIT; /* Register with V4L2 layer as slave device */ - err = v4l2_int_device_register(&decoder->v4l2_int_device); - if (err) { - i2c_set_clientdata(client, NULL); - v4l_err(client, - "Unable to register to v4l2. Err[%d]\n", err); - goto out_free; - - } else - v4l_info(client, "Registered to v4l2 master %s!!\n", - decoder->pdata->master); + sd = &decoder->sd; + v4l2_i2c_subdev_init(sd, client, &tvp514x_ops); + + v4l2_info(sd, "%s decoder driver registered !!\n", sd->name); + return 0; -out_free: - kfree(decoder); - return err; } /** - * tvp514x_remove - decoder driver i2c remove handler + * tvp514x_remove() - decoder driver i2c remove handler * @client: i2c driver client device structure * * Unregister decoder as an i2c client device and V4L2 * device. Complement of tvp514x_probe(). */ -static int __exit tvp514x_remove(struct i2c_client *client) +static int tvp514x_remove(struct i2c_client *client) { - struct tvp514x_decoder *decoder = i2c_get_clientdata(client); - - if (!client->adapter) - return -ENODEV; /* our client isn't attached */ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct tvp514x_decoder *decoder = to_decoder(sd); - v4l2_int_device_unregister(&decoder->v4l2_int_device); - i2c_set_clientdata(client, NULL); + v4l2_device_unregister_subdev(sd); kfree(decoder); return 0; } -/* - * TVP5146 Init/Power on Sequence - */ +/* TVP5146 Init/Power on Sequence */ static const struct tvp514x_reg tvp5146_init_reg_seq[] = { {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x02}, {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00}, @@ -1485,14 +1371,10 @@ static const struct tvp514x_reg tvp5146_init_reg_seq[] = { {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x00}, {TOK_WRITE, REG_OPERATION_MODE, 0x01}, {TOK_WRITE, REG_OPERATION_MODE, 0x00}, + {TOK_TERM, 0, 0}, }; -static const struct tvp514x_init_seq tvp5146_init = { - .no_regs = ARRAY_SIZE(tvp5146_init_reg_seq), - .init_reg_seq = tvp5146_init_reg_seq, -}; -/* - * TVP5147 Init/Power on Sequence - */ + +/* TVP5147 Init/Power on Sequence */ static const struct tvp514x_reg tvp5147_init_reg_seq[] = { {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x02}, {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00}, @@ -1512,71 +1394,51 @@ static const struct tvp514x_reg tvp5147_init_reg_seq[] = { {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x00}, {TOK_WRITE, REG_OPERATION_MODE, 0x01}, {TOK_WRITE, REG_OPERATION_MODE, 0x00}, + {TOK_TERM, 0, 0}, }; -static const struct tvp514x_init_seq tvp5147_init = { - .no_regs = ARRAY_SIZE(tvp5147_init_reg_seq), - .init_reg_seq = tvp5147_init_reg_seq, -}; -/* - * TVP5146M2/TVP5147M1 Init/Power on Sequence - */ + +/* TVP5146M2/TVP5147M1 Init/Power on Sequence */ static const struct tvp514x_reg tvp514xm_init_reg_seq[] = { {TOK_WRITE, REG_OPERATION_MODE, 0x01}, {TOK_WRITE, REG_OPERATION_MODE, 0x00}, + {TOK_TERM, 0, 0}, }; -static const struct tvp514x_init_seq tvp514xm_init = { - .no_regs = ARRAY_SIZE(tvp514xm_init_reg_seq), - .init_reg_seq = tvp514xm_init_reg_seq, -}; -/* + +/** * I2C Device Table - * * name - Name of the actual device/chip. * driver_data - Driver data */ static const struct i2c_device_id tvp514x_id[] = { - {"tvp5146", (unsigned long)&tvp5146_init}, - {"tvp5146m2", (unsigned long)&tvp514xm_init}, - {"tvp5147", (unsigned long)&tvp5147_init}, - {"tvp5147m1", (unsigned long)&tvp514xm_init}, + {"tvp5146", (unsigned long)tvp5146_init_reg_seq}, + {"tvp5146m2", (unsigned long)tvp514xm_init_reg_seq}, + {"tvp5147", (unsigned long)tvp5147_init_reg_seq}, + {"tvp5147m1", (unsigned long)tvp514xm_init_reg_seq}, {}, }; MODULE_DEVICE_TABLE(i2c, tvp514x_id); -static struct i2c_driver tvp514x_i2c_driver = { +static struct i2c_driver tvp514x_driver = { .driver = { - .name = TVP514X_MODULE_NAME, - .owner = THIS_MODULE, - }, + .owner = THIS_MODULE, + .name = TVP514X_MODULE_NAME, + }, .probe = tvp514x_probe, - .remove = __exit_p(tvp514x_remove), + .remove = tvp514x_remove, .id_table = tvp514x_id, }; -/** - * tvp514x_init - * - * Module init function - */ static int __init tvp514x_init(void) { - return i2c_add_driver(&tvp514x_i2c_driver); + return i2c_add_driver(&tvp514x_driver); } -/** - * tvp514x_cleanup - * - * Module exit function - */ -static void __exit tvp514x_cleanup(void) +static void __exit tvp514x_exit(void) { - i2c_del_driver(&tvp514x_i2c_driver); + i2c_del_driver(&tvp514x_driver); } module_init(tvp514x_init); -module_exit(tvp514x_cleanup); - -MODULE_AUTHOR("Texas Instruments"); -MODULE_DESCRIPTION("TVP514X linux decoder driver"); -MODULE_LICENSE("GPL"); +module_exit(tvp514x_exit); diff --git a/drivers/media/video/tvp514x_regs.h b/drivers/media/video/tvp514x_regs.h index 351620aeecc2..18f29ad0dfe2 100644 --- a/drivers/media/video/tvp514x_regs.h +++ b/drivers/media/video/tvp514x_regs.h @@ -284,14 +284,4 @@ struct tvp514x_reg { u32 val; }; -/** - * struct tvp514x_init_seq - Structure for TVP5146/47/46M2/47M1 power up - * Sequence. - * @ no_regs - Number of registers to write for power up sequence. - * @ init_reg_seq - Array of registers and respective value to write. - */ -struct tvp514x_init_seq { - unsigned int no_regs; - const struct tvp514x_reg *init_reg_seq; -}; #endif /* ifndef _TVP514X_REGS_H */ diff --git a/drivers/media/video/tw9910.c b/drivers/media/video/tw9910.c index aa5065ea09ed..269ab044072a 100644 --- a/drivers/media/video/tw9910.c +++ b/drivers/media/video/tw9910.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include @@ -223,9 +223,8 @@ struct tw9910_hsync_ctrl { }; struct tw9910_priv { + struct v4l2_subdev subdev; struct tw9910_video_info *info; - struct i2c_client *client; - struct soc_camera_device icd; const struct tw9910_scale_ctrl *scale; }; @@ -356,6 +355,12 @@ static const struct tw9910_hsync_ctrl tw9910_hsync_ctrl = { /* * general function */ +static struct tw9910_priv *to_tw9910(const struct i2c_client *client) +{ + return container_of(i2c_get_clientdata(client), struct tw9910_priv, + subdev); +} + static int tw9910_set_scale(struct i2c_client *client, const struct tw9910_scale_ctrl *scale) { @@ -509,44 +514,20 @@ tw9910_select_norm(struct soc_camera_device *icd, u32 width, u32 height) /* * soc_camera_ops function */ -static int tw9910_init(struct soc_camera_device *icd) -{ - struct tw9910_priv *priv = container_of(icd, struct tw9910_priv, icd); - int ret = 0; - - if (priv->info->link.power) { - ret = priv->info->link.power(&priv->client->dev, 1); - if (ret < 0) - return ret; - } - - if (priv->info->link.reset) - ret = priv->info->link.reset(&priv->client->dev); - - return ret; -} - -static int tw9910_release(struct soc_camera_device *icd) +static int tw9910_s_stream(struct v4l2_subdev *sd, int enable) { - struct tw9910_priv *priv = container_of(icd, struct tw9910_priv, icd); - int ret = 0; - - if (priv->info->link.power) - ret = priv->info->link.power(&priv->client->dev, 0); - - return ret; -} + struct i2c_client *client = sd->priv; + struct tw9910_priv *priv = to_tw9910(client); -static int tw9910_start_capture(struct soc_camera_device *icd) -{ - struct tw9910_priv *priv = container_of(icd, struct tw9910_priv, icd); + if (!enable) + return 0; if (!priv->scale) { - dev_err(&icd->dev, "norm select error\n"); + dev_err(&client->dev, "norm select error\n"); return -EPERM; } - dev_dbg(&icd->dev, "%s %dx%d\n", + dev_dbg(&client->dev, "%s %dx%d\n", priv->scale->name, priv->scale->width, priv->scale->height); @@ -554,11 +535,6 @@ static int tw9910_start_capture(struct soc_camera_device *icd) return 0; } -static int tw9910_stop_capture(struct soc_camera_device *icd) -{ - return 0; -} - static int tw9910_set_bus_param(struct soc_camera_device *icd, unsigned long flags) { @@ -567,8 +543,9 @@ static int tw9910_set_bus_param(struct soc_camera_device *icd, static unsigned long tw9910_query_bus_param(struct soc_camera_device *icd) { - struct tw9910_priv *priv = container_of(icd, struct tw9910_priv, icd); - struct soc_camera_link *icl = priv->client->dev.platform_data; + struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd)); + struct tw9910_priv *priv = to_tw9910(client); + struct soc_camera_link *icl = to_soc_camera_link(icd); unsigned long flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_MASTER | SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_DATA_ACTIVE_HIGH | priv->info->buswidth; @@ -576,21 +553,11 @@ static unsigned long tw9910_query_bus_param(struct soc_camera_device *icd) return soc_camera_apply_sensor_flags(icl, flags); } -static int tw9910_get_chip_id(struct soc_camera_device *icd, - struct v4l2_dbg_chip_ident *id) -{ - id->ident = V4L2_IDENT_TW9910; - id->revision = 0; - - return 0; -} - -static int tw9910_set_std(struct soc_camera_device *icd, - v4l2_std_id *a) +static int tw9910_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) { int ret = -EINVAL; - if (*a & (V4L2_STD_NTSC | V4L2_STD_PAL)) + if (norm & (V4L2_STD_NTSC | V4L2_STD_PAL)) ret = 0; return ret; @@ -606,17 +573,26 @@ static int tw9910_enum_input(struct soc_camera_device *icd, return 0; } +static int tw9910_g_chip_ident(struct v4l2_subdev *sd, + struct v4l2_dbg_chip_ident *id) +{ + id->ident = V4L2_IDENT_TW9910; + id->revision = 0; + + return 0; +} + #ifdef CONFIG_VIDEO_ADV_DEBUG -static int tw9910_get_register(struct soc_camera_device *icd, - struct v4l2_dbg_register *reg) +static int tw9910_g_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) { - struct tw9910_priv *priv = container_of(icd, struct tw9910_priv, icd); + struct i2c_client *client = sd->priv; int ret; if (reg->reg > 0xff) return -EINVAL; - ret = i2c_smbus_read_byte_data(priv->client, reg->reg); + ret = i2c_smbus_read_byte_data(client, reg->reg); if (ret < 0) return ret; @@ -628,23 +604,25 @@ static int tw9910_get_register(struct soc_camera_device *icd, return 0; } -static int tw9910_set_register(struct soc_camera_device *icd, - struct v4l2_dbg_register *reg) +static int tw9910_s_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) { - struct tw9910_priv *priv = container_of(icd, struct tw9910_priv, icd); + struct i2c_client *client = sd->priv; if (reg->reg > 0xff || reg->val > 0xff) return -EINVAL; - return i2c_smbus_write_byte_data(priv->client, reg->reg, reg->val); + return i2c_smbus_write_byte_data(client, reg->reg, reg->val); } #endif -static int tw9910_set_crop(struct soc_camera_device *icd, - struct v4l2_rect *rect) +static int tw9910_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) { - struct tw9910_priv *priv = container_of(icd, struct tw9910_priv, icd); + struct v4l2_rect *rect = &a->c; + struct i2c_client *client = sd->priv; + struct tw9910_priv *priv = to_tw9910(client); + struct soc_camera_device *icd = client->dev.platform_data; int ret = -EINVAL; u8 val; @@ -658,8 +636,8 @@ static int tw9910_set_crop(struct soc_camera_device *icd, /* * reset hardware */ - tw9910_reset(priv->client); - ret = tw9910_write_array(priv->client, tw9910_default_regs); + tw9910_reset(client); + ret = tw9910_write_array(client, tw9910_default_regs); if (ret < 0) goto tw9910_set_fmt_error; @@ -670,7 +648,7 @@ static int tw9910_set_crop(struct soc_camera_device *icd, if (SOCAM_DATAWIDTH_16 == priv->info->buswidth) val = LEN; - ret = tw9910_mask_set(priv->client, OPFORM, LEN, val); + ret = tw9910_mask_set(client, OPFORM, LEN, val); if (ret < 0) goto tw9910_set_fmt_error; @@ -698,52 +676,139 @@ static int tw9910_set_crop(struct soc_camera_device *icd, val = 0; } - ret = tw9910_mask_set(priv->client, VBICNTL, RTSEL_MASK, val); + ret = tw9910_mask_set(client, VBICNTL, RTSEL_MASK, val); if (ret < 0) goto tw9910_set_fmt_error; /* * set scale */ - ret = tw9910_set_scale(priv->client, priv->scale); + ret = tw9910_set_scale(client, priv->scale); if (ret < 0) goto tw9910_set_fmt_error; /* * set cropping */ - ret = tw9910_set_cropping(priv->client, &tw9910_cropping_ctrl); + ret = tw9910_set_cropping(client, &tw9910_cropping_ctrl); if (ret < 0) goto tw9910_set_fmt_error; /* * set hsync */ - ret = tw9910_set_hsync(priv->client, &tw9910_hsync_ctrl); + ret = tw9910_set_hsync(client, &tw9910_hsync_ctrl); if (ret < 0) goto tw9910_set_fmt_error; + rect->width = priv->scale->width; + rect->height = priv->scale->height; + rect->left = 0; + rect->top = 0; + return ret; tw9910_set_fmt_error: - tw9910_reset(priv->client); + tw9910_reset(client); priv->scale = NULL; return ret; } -static int tw9910_set_fmt(struct soc_camera_device *icd, - struct v4l2_format *f) +static int tw9910_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) +{ + struct i2c_client *client = sd->priv; + struct tw9910_priv *priv = to_tw9910(client); + + if (!priv->scale) { + int ret; + struct v4l2_crop crop = { + .c = { + .left = 0, + .top = 0, + .width = 640, + .height = 480, + }, + }; + ret = tw9910_s_crop(sd, &crop); + if (ret < 0) + return ret; + } + + a->c.left = 0; + a->c.top = 0; + a->c.width = priv->scale->width; + a->c.height = priv->scale->height; + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + return 0; +} + +static int tw9910_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) { + a->bounds.left = 0; + a->bounds.top = 0; + a->bounds.width = 768; + a->bounds.height = 576; + a->defrect.left = 0; + a->defrect.top = 0; + a->defrect.width = 640; + a->defrect.height = 480; + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + a->pixelaspect.numerator = 1; + a->pixelaspect.denominator = 1; + + return 0; +} + +static int tw9910_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) +{ + struct i2c_client *client = sd->priv; + struct tw9910_priv *priv = to_tw9910(client); + struct v4l2_pix_format *pix = &f->fmt.pix; + + if (!priv->scale) { + int ret; + struct v4l2_crop crop = { + .c = { + .left = 0, + .top = 0, + .width = 640, + .height = 480, + }, + }; + ret = tw9910_s_crop(sd, &crop); + if (ret < 0) + return ret; + } + + f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + pix->width = priv->scale->width; + pix->height = priv->scale->height; + pix->pixelformat = V4L2_PIX_FMT_VYUY; + pix->colorspace = V4L2_COLORSPACE_SMPTE170M; + pix->field = V4L2_FIELD_INTERLACED; + + return 0; +} + +static int tw9910_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) +{ + struct i2c_client *client = sd->priv; + struct tw9910_priv *priv = to_tw9910(client); struct v4l2_pix_format *pix = &f->fmt.pix; - struct v4l2_rect rect = { - .left = icd->x_current, - .top = icd->y_current, - .width = pix->width, - .height = pix->height, + /* See tw9910_s_crop() - no proper cropping support */ + struct v4l2_crop a = { + .c = { + .left = 0, + .top = 0, + .width = pix->width, + .height = pix->height, + }, }; - int i; + int i, ret; /* * check color format @@ -755,19 +820,25 @@ static int tw9910_set_fmt(struct soc_camera_device *icd, if (i == ARRAY_SIZE(tw9910_color_fmt)) return -EINVAL; - return tw9910_set_crop(icd, &rect); + ret = tw9910_s_crop(sd, &a); + if (!ret) { + pix->width = priv->scale->width; + pix->height = priv->scale->height; + } + return ret; } -static int tw9910_try_fmt(struct soc_camera_device *icd, - struct v4l2_format *f) +static int tw9910_try_fmt(struct v4l2_subdev *sd, struct v4l2_format *f) { + struct i2c_client *client = sd->priv; + struct soc_camera_device *icd = client->dev.platform_data; struct v4l2_pix_format *pix = &f->fmt.pix; const struct tw9910_scale_ctrl *scale; if (V4L2_FIELD_ANY == pix->field) { pix->field = V4L2_FIELD_INTERLACED; } else if (V4L2_FIELD_INTERLACED != pix->field) { - dev_err(&icd->dev, "Field type invalid.\n"); + dev_err(&client->dev, "Field type invalid.\n"); return -EINVAL; } @@ -784,11 +855,11 @@ static int tw9910_try_fmt(struct soc_camera_device *icd, return 0; } -static int tw9910_video_probe(struct soc_camera_device *icd) +static int tw9910_video_probe(struct soc_camera_device *icd, + struct i2c_client *client) { - struct tw9910_priv *priv = container_of(icd, struct tw9910_priv, icd); + struct tw9910_priv *priv = to_tw9910(client); s32 val; - int ret; /* * We must have a parent by now. And it cannot be a wrong one. @@ -803,7 +874,7 @@ static int tw9910_video_probe(struct soc_camera_device *icd) */ if (SOCAM_DATAWIDTH_16 != priv->info->buswidth && SOCAM_DATAWIDTH_8 != priv->info->buswidth) { - dev_err(&icd->dev, "bus width error\n"); + dev_err(&client->dev, "bus width error\n"); return -ENODEV; } @@ -813,54 +884,54 @@ static int tw9910_video_probe(struct soc_camera_device *icd) /* * check and show Product ID */ - val = i2c_smbus_read_byte_data(priv->client, ID); + val = i2c_smbus_read_byte_data(client, ID); + if (0x0B != GET_ID(val) || 0x00 != GET_ReV(val)) { - dev_err(&icd->dev, + dev_err(&client->dev, "Product ID error %x:%x\n", GET_ID(val), GET_ReV(val)); return -ENODEV; } - dev_info(&icd->dev, + dev_info(&client->dev, "tw9910 Product ID %0x:%0x\n", GET_ID(val), GET_ReV(val)); - ret = soc_camera_video_start(icd); - if (ret < 0) - return ret; - icd->vdev->tvnorms = V4L2_STD_NTSC | V4L2_STD_PAL; icd->vdev->current_norm = V4L2_STD_NTSC; - return ret; -} - -static void tw9910_video_remove(struct soc_camera_device *icd) -{ - soc_camera_video_stop(icd); + return 0; } static struct soc_camera_ops tw9910_ops = { - .owner = THIS_MODULE, - .probe = tw9910_video_probe, - .remove = tw9910_video_remove, - .init = tw9910_init, - .release = tw9910_release, - .start_capture = tw9910_start_capture, - .stop_capture = tw9910_stop_capture, - .set_crop = tw9910_set_crop, - .set_fmt = tw9910_set_fmt, - .try_fmt = tw9910_try_fmt, .set_bus_param = tw9910_set_bus_param, .query_bus_param = tw9910_query_bus_param, - .get_chip_id = tw9910_get_chip_id, - .set_std = tw9910_set_std, .enum_input = tw9910_enum_input, +}; + +static struct v4l2_subdev_core_ops tw9910_subdev_core_ops = { + .g_chip_ident = tw9910_g_chip_ident, + .s_std = tw9910_s_std, #ifdef CONFIG_VIDEO_ADV_DEBUG - .get_register = tw9910_get_register, - .set_register = tw9910_set_register, + .g_register = tw9910_g_register, + .s_register = tw9910_s_register, #endif }; +static struct v4l2_subdev_video_ops tw9910_subdev_video_ops = { + .s_stream = tw9910_s_stream, + .g_fmt = tw9910_g_fmt, + .s_fmt = tw9910_s_fmt, + .try_fmt = tw9910_try_fmt, + .cropcap = tw9910_cropcap, + .g_crop = tw9910_g_crop, + .s_crop = tw9910_s_crop, +}; + +static struct v4l2_subdev_ops tw9910_subdev_ops = { + .core = &tw9910_subdev_core_ops, + .video = &tw9910_subdev_video_ops, +}; + /* * i2c_driver function */ @@ -871,18 +942,24 @@ static int tw9910_probe(struct i2c_client *client, { struct tw9910_priv *priv; struct tw9910_video_info *info; - struct soc_camera_device *icd; - const struct tw9910_scale_ctrl *scale; - int i, ret; + struct soc_camera_device *icd = client->dev.platform_data; + struct i2c_adapter *adapter = + to_i2c_adapter(client->dev.parent); + struct soc_camera_link *icl; + int ret; + + if (!icd) { + dev_err(&client->dev, "TW9910: missing soc-camera data!\n"); + return -EINVAL; + } - if (!client->dev.platform_data) + icl = to_soc_camera_link(icd); + if (!icl) return -EINVAL; - info = container_of(client->dev.platform_data, - struct tw9910_video_info, link); + info = container_of(icl, struct tw9910_video_info, link); - if (!i2c_check_functionality(to_i2c_adapter(client->dev.parent), - I2C_FUNC_SMBUS_BYTE_DATA)) { + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { dev_err(&client->dev, "I2C-Adapter doesn't support " "I2C_FUNC_SMBUS_BYTE_DATA\n"); @@ -894,40 +971,15 @@ static int tw9910_probe(struct i2c_client *client, return -ENOMEM; priv->info = info; - priv->client = client; - i2c_set_clientdata(client, priv); - icd = &priv->icd; + v4l2_i2c_subdev_init(&priv->subdev, client, &tw9910_subdev_ops); + icd->ops = &tw9910_ops; - icd->control = &client->dev; icd->iface = info->link.bus_id; - /* - * set width and height - */ - icd->width_max = tw9910_ntsc_scales[0].width; /* set default */ - icd->width_min = tw9910_ntsc_scales[0].width; - icd->height_max = tw9910_ntsc_scales[0].height; - icd->height_min = tw9910_ntsc_scales[0].height; - - scale = tw9910_ntsc_scales; - for (i = 0; i < ARRAY_SIZE(tw9910_ntsc_scales); i++) { - icd->width_max = max(scale[i].width, icd->width_max); - icd->width_min = min(scale[i].width, icd->width_min); - icd->height_max = max(scale[i].height, icd->height_max); - icd->height_min = min(scale[i].height, icd->height_min); - } - scale = tw9910_pal_scales; - for (i = 0; i < ARRAY_SIZE(tw9910_pal_scales); i++) { - icd->width_max = max(scale[i].width, icd->width_max); - icd->width_min = min(scale[i].width, icd->width_min); - icd->height_max = max(scale[i].height, icd->height_max); - icd->height_min = min(scale[i].height, icd->height_min); - } - - ret = soc_camera_device_register(icd); - + ret = tw9910_video_probe(icd, client); if (ret) { + icd->ops = NULL; i2c_set_clientdata(client, NULL); kfree(priv); } @@ -937,9 +989,10 @@ static int tw9910_probe(struct i2c_client *client, static int tw9910_remove(struct i2c_client *client) { - struct tw9910_priv *priv = i2c_get_clientdata(client); + struct tw9910_priv *priv = to_tw9910(client); + struct soc_camera_device *icd = client->dev.platform_data; - soc_camera_device_unregister(&priv->icd); + icd->ops = NULL; i2c_set_clientdata(client, NULL); kfree(priv); return 0; diff --git a/drivers/media/video/usbvision/usbvision-i2c.c b/drivers/media/video/usbvision/usbvision-i2c.c index 1fe5befbbf85..f97fd06d5948 100644 --- a/drivers/media/video/usbvision/usbvision-i2c.c +++ b/drivers/media/video/usbvision/usbvision-i2c.c @@ -246,9 +246,9 @@ int usbvision_i2c_register(struct usb_usbvision *usbvision) switch (usbvision_device_data[usbvision->DevModel].Codec) { case CODEC_SAA7113: case CODEC_SAA7111: - v4l2_i2c_new_probed_subdev(&usbvision->v4l2_dev, + v4l2_i2c_new_subdev(&usbvision->v4l2_dev, &usbvision->i2c_adap, "saa7115", - "saa7115_auto", saa711x_addrs); + "saa7115_auto", 0, saa711x_addrs); break; } if (usbvision_device_data[usbvision->DevModel].Tuner == 1) { @@ -256,16 +256,16 @@ int usbvision_i2c_register(struct usb_usbvision *usbvision) enum v4l2_i2c_tuner_type type; struct tuner_setup tun_setup; - sd = v4l2_i2c_new_probed_subdev(&usbvision->v4l2_dev, + sd = v4l2_i2c_new_subdev(&usbvision->v4l2_dev, &usbvision->i2c_adap, "tuner", - "tuner", v4l2_i2c_tuner_addrs(ADDRS_DEMOD)); + "tuner", 0, v4l2_i2c_tuner_addrs(ADDRS_DEMOD)); /* depending on whether we found a demod or not, select the tuner type. */ type = sd ? ADDRS_TV_WITH_DEMOD : ADDRS_TV; - sd = v4l2_i2c_new_probed_subdev(&usbvision->v4l2_dev, + sd = v4l2_i2c_new_subdev(&usbvision->v4l2_dev, &usbvision->i2c_adap, "tuner", - "tuner", v4l2_i2c_tuner_addrs(type)); + "tuner", 0, v4l2_i2c_tuner_addrs(type)); if (usbvision->tuner_type != -1) { tun_setup.mode_mask = T_ANALOG_TV | T_RADIO; diff --git a/drivers/media/video/uvc/uvc_video.c b/drivers/media/video/uvc/uvc_video.c index 5b757f32d997..f960e8ea4f17 100644 --- a/drivers/media/video/uvc/uvc_video.c +++ b/drivers/media/video/uvc/uvc_video.c @@ -124,13 +124,14 @@ static int uvc_get_video_ctrl(struct uvc_streaming *stream, int ret; size = stream->dev->uvc_version >= 0x0110 ? 34 : 26; + if ((stream->dev->quirks & UVC_QUIRK_PROBE_DEF) && + query == UVC_GET_DEF) + return -EIO; + data = kmalloc(size, GFP_KERNEL); if (data == NULL) return -ENOMEM; - if ((stream->dev->quirks & UVC_QUIRK_PROBE_DEF) && query == UVC_GET_DEF) - return -EIO; - ret = __uvc_query_ctrl(stream->dev, query, 0, stream->intfnum, probe ? UVC_VS_PROBE_CONTROL : UVC_VS_COMMIT_CONTROL, data, size, UVC_CTRL_STREAMING_TIMEOUT); diff --git a/drivers/media/video/v4l1-compat.c b/drivers/media/video/v4l1-compat.c index 761fbd64db58..0c2105ca611e 100644 --- a/drivers/media/video/v4l1-compat.c +++ b/drivers/media/video/v4l1-compat.c @@ -564,10 +564,9 @@ static noinline long v4l1_compat_get_input_info( break; } chan->norm = 0; - err = drv(file, VIDIOC_G_STD, &sid); - if (err < 0) - dprintk("VIDIOCGCHAN / VIDIOC_G_STD: %ld\n", err); - if (err == 0) { + /* Note: G_STD might not be present for radio receivers, + * so we should ignore any errors. */ + if (drv(file, VIDIOC_G_STD, &sid) == 0) { if (sid & V4L2_STD_PAL) chan->norm = VIDEO_MODE_PAL; if (sid & V4L2_STD_NTSC) @@ -776,10 +775,9 @@ static noinline long v4l1_compat_get_tuner( tun->flags |= VIDEO_TUNER_SECAM; } - err = drv(file, VIDIOC_G_STD, &sid); - if (err < 0) - dprintk("VIDIOCGTUNER / VIDIOC_G_STD: %ld\n", err); - if (err == 0) { + /* Note: G_STD might not be present for radio receivers, + * so we should ignore any errors. */ + if (drv(file, VIDIOC_G_STD, &sid) == 0) { if (sid & V4L2_STD_PAL) tun->mode = VIDEO_MODE_PAL; if (sid & V4L2_STD_NTSC) diff --git a/drivers/media/video/v4l2-common.c b/drivers/media/video/v4l2-common.c index 3a0c64935b0e..f5a93ae3cdf9 100644 --- a/drivers/media/video/v4l2-common.c +++ b/drivers/media/video/v4l2-common.c @@ -813,139 +813,6 @@ EXPORT_SYMBOL_GPL(v4l2_i2c_subdev_init); -/* Load an i2c sub-device. */ -struct v4l2_subdev *v4l2_i2c_new_subdev(struct v4l2_device *v4l2_dev, - struct i2c_adapter *adapter, - const char *module_name, const char *client_type, u8 addr) -{ - struct v4l2_subdev *sd = NULL; - struct i2c_client *client; - struct i2c_board_info info; - - BUG_ON(!v4l2_dev); - - if (module_name) - request_module(module_name); - - /* Setup the i2c board info with the device type and - the device address. */ - memset(&info, 0, sizeof(info)); - strlcpy(info.type, client_type, sizeof(info.type)); - info.addr = addr; - - /* Create the i2c client */ - client = i2c_new_device(adapter, &info); - /* Note: it is possible in the future that - c->driver is NULL if the driver is still being loaded. - We need better support from the kernel so that we - can easily wait for the load to finish. */ - if (client == NULL || client->driver == NULL) - goto error; - - /* Lock the module so we can safely get the v4l2_subdev pointer */ - if (!try_module_get(client->driver->driver.owner)) - goto error; - sd = i2c_get_clientdata(client); - - /* Register with the v4l2_device which increases the module's - use count as well. */ - if (v4l2_device_register_subdev(v4l2_dev, sd)) - sd = NULL; - /* Decrease the module use count to match the first try_module_get. */ - module_put(client->driver->driver.owner); - - if (sd) { - /* We return errors from v4l2_subdev_call only if we have the - callback as the .s_config is not mandatory */ - int err = v4l2_subdev_call(sd, core, s_config, 0, NULL); - - if (err && err != -ENOIOCTLCMD) { - v4l2_device_unregister_subdev(sd); - sd = NULL; - } - } - -error: - /* If we have a client but no subdev, then something went wrong and - we must unregister the client. */ - if (client && sd == NULL) - i2c_unregister_device(client); - return sd; -} -EXPORT_SYMBOL_GPL(v4l2_i2c_new_subdev); - -/* Probe and load an i2c sub-device. */ -struct v4l2_subdev *v4l2_i2c_new_probed_subdev(struct v4l2_device *v4l2_dev, - struct i2c_adapter *adapter, - const char *module_name, const char *client_type, - const unsigned short *addrs) -{ - struct v4l2_subdev *sd = NULL; - struct i2c_client *client = NULL; - struct i2c_board_info info; - - BUG_ON(!v4l2_dev); - - if (module_name) - request_module(module_name); - - /* Setup the i2c board info with the device type and - the device address. */ - memset(&info, 0, sizeof(info)); - strlcpy(info.type, client_type, sizeof(info.type)); - - /* Probe and create the i2c client */ - client = i2c_new_probed_device(adapter, &info, addrs); - /* Note: it is possible in the future that - c->driver is NULL if the driver is still being loaded. - We need better support from the kernel so that we - can easily wait for the load to finish. */ - if (client == NULL || client->driver == NULL) - goto error; - - /* Lock the module so we can safely get the v4l2_subdev pointer */ - if (!try_module_get(client->driver->driver.owner)) - goto error; - sd = i2c_get_clientdata(client); - - /* Register with the v4l2_device which increases the module's - use count as well. */ - if (v4l2_device_register_subdev(v4l2_dev, sd)) - sd = NULL; - /* Decrease the module use count to match the first try_module_get. */ - module_put(client->driver->driver.owner); - - if (sd) { - /* We return errors from v4l2_subdev_call only if we have the - callback as the .s_config is not mandatory */ - int err = v4l2_subdev_call(sd, core, s_config, 0, NULL); - - if (err && err != -ENOIOCTLCMD) { - v4l2_device_unregister_subdev(sd); - sd = NULL; - } - } - -error: - /* If we have a client but no subdev, then something went wrong and - we must unregister the client. */ - if (client && sd == NULL) - i2c_unregister_device(client); - return sd; -} -EXPORT_SYMBOL_GPL(v4l2_i2c_new_probed_subdev); - -struct v4l2_subdev *v4l2_i2c_new_probed_subdev_addr(struct v4l2_device *v4l2_dev, - struct i2c_adapter *adapter, - const char *module_name, const char *client_type, u8 addr) -{ - unsigned short addrs[2] = { addr, I2C_CLIENT_END }; - - return v4l2_i2c_new_probed_subdev(v4l2_dev, adapter, - module_name, client_type, addrs); -} -EXPORT_SYMBOL_GPL(v4l2_i2c_new_probed_subdev_addr); - /* Load an i2c sub-device. */ struct v4l2_subdev *v4l2_i2c_new_subdev_board(struct v4l2_device *v4l2_dev, struct i2c_adapter *adapter, const char *module_name, diff --git a/drivers/media/video/v4l2-dev.c b/drivers/media/video/v4l2-dev.c index a7f1b69a7dab..500cbe9891ac 100644 --- a/drivers/media/video/v4l2-dev.c +++ b/drivers/media/video/v4l2-dev.c @@ -66,7 +66,49 @@ static struct device_attribute video_device_attrs[] = { */ static struct video_device *video_device[VIDEO_NUM_DEVICES]; static DEFINE_MUTEX(videodev_lock); -static DECLARE_BITMAP(video_nums[VFL_TYPE_MAX], VIDEO_NUM_DEVICES); +static DECLARE_BITMAP(devnode_nums[VFL_TYPE_MAX], VIDEO_NUM_DEVICES); + +/* Device node utility functions */ + +/* Note: these utility functions all assume that vfl_type is in the range + [0, VFL_TYPE_MAX-1]. */ + +#ifdef CONFIG_VIDEO_FIXED_MINOR_RANGES +/* Return the bitmap corresponding to vfl_type. */ +static inline unsigned long *devnode_bits(int vfl_type) +{ + /* Any types not assigned to fixed minor ranges must be mapped to + one single bitmap for the purposes of finding a free node number + since all those unassigned types use the same minor range. */ + int idx = (vfl_type > VFL_TYPE_VTX) ? VFL_TYPE_MAX - 1 : vfl_type; + + return devnode_nums[idx]; +} +#else +/* Return the bitmap corresponding to vfl_type. */ +static inline unsigned long *devnode_bits(int vfl_type) +{ + return devnode_nums[vfl_type]; +} +#endif + +/* Mark device node number vdev->num as used */ +static inline void devnode_set(struct video_device *vdev) +{ + set_bit(vdev->num, devnode_bits(vdev->vfl_type)); +} + +/* Mark device node number vdev->num as unused */ +static inline void devnode_clear(struct video_device *vdev) +{ + clear_bit(vdev->num, devnode_bits(vdev->vfl_type)); +} + +/* Try to find a free device node number in the range [from, to> */ +static inline int devnode_find(struct video_device *vdev, int from, int to) +{ + return find_next_zero_bit(devnode_bits(vdev->vfl_type), to, from); +} struct video_device *video_device_alloc(void) { @@ -119,8 +161,8 @@ static void v4l2_device_release(struct device *cd) the release() callback. */ vdev->cdev = NULL; - /* Mark minor as free */ - clear_bit(vdev->num, video_nums[vdev->vfl_type]); + /* Mark device node number as free */ + devnode_clear(vdev); mutex_unlock(&videodev_lock); @@ -299,32 +341,28 @@ static const struct file_operations v4l2_fops = { }; /** - * get_index - assign stream number based on parent device + * get_index - assign stream index number based on parent device * @vdev: video_device to assign index number to, vdev->parent should be assigned - * @num: -1 if auto assign, requested number otherwise * * Note that when this is called the new device has not yet been registered - * in the video_device array. + * in the video_device array, but it was able to obtain a minor number. + * + * This means that we can always obtain a free stream index number since + * the worst case scenario is that there are VIDEO_NUM_DEVICES - 1 slots in + * use of the video_device array. * - * Returns -ENFILE if num is already in use, a free index number if - * successful. + * Returns a free index number. */ -static int get_index(struct video_device *vdev, int num) +static int get_index(struct video_device *vdev) { /* This can be static since this function is called with the global videodev_lock held. */ static DECLARE_BITMAP(used, VIDEO_NUM_DEVICES); int i; - if (num >= VIDEO_NUM_DEVICES) { - printk(KERN_ERR "videodev: %s num is too large\n", __func__); - return -EINVAL; - } - - /* Some drivers do not set the parent. In that case always return - num or 0. */ + /* Some drivers do not set the parent. In that case always return 0. */ if (vdev->parent == NULL) - return num >= 0 ? num : 0; + return 0; bitmap_zero(used, VIDEO_NUM_DEVICES); @@ -335,35 +373,23 @@ static int get_index(struct video_device *vdev, int num) } } - if (num >= 0) { - if (test_bit(num, used)) - return -ENFILE; - return num; - } - - i = find_first_zero_bit(used, VIDEO_NUM_DEVICES); - return i == VIDEO_NUM_DEVICES ? -ENFILE : i; + return find_first_zero_bit(used, VIDEO_NUM_DEVICES); } -int video_register_device(struct video_device *vdev, int type, int nr) -{ - return video_register_device_index(vdev, type, nr, -1); -} -EXPORT_SYMBOL(video_register_device); - /** - * video_register_device_index - register video4linux devices + * video_register_device - register video4linux devices * @vdev: video device structure we want to register * @type: type of device to register - * @nr: which device number (0 == /dev/video0, 1 == /dev/video1, ... + * @nr: which device node number (0 == /dev/video0, 1 == /dev/video1, ... * -1 == first free) - * @index: stream number based on parent device; - * -1 if auto assign, requested number otherwise + * @warn_if_nr_in_use: warn if the desired device node number + * was already in use and another number was chosen instead. * - * The registration code assigns minor numbers based on the type - * requested. -ENFILE is returned in all the device slots for this - * category are full. If not then the minor field is set and the - * driver initialize function is called (if non %NULL). + * The registration code assigns minor numbers and device node numbers + * based on the requested type and registers the new device node with + * the kernel. + * An error is returned if no free minor or device node number could be + * found, or if the registration of the device node failed. * * Zero is returned on success. * @@ -377,8 +403,8 @@ EXPORT_SYMBOL(video_register_device); * * %VFL_TYPE_RADIO - A radio card */ -int video_register_device_index(struct video_device *vdev, int type, int nr, - int index) +static int __video_register_device(struct video_device *vdev, int type, int nr, + int warn_if_nr_in_use) { int i = 0; int ret; @@ -421,7 +447,7 @@ int video_register_device_index(struct video_device *vdev, int type, int nr, if (vdev->v4l2_dev && vdev->v4l2_dev->dev) vdev->parent = vdev->v4l2_dev->dev; - /* Part 2: find a free minor, kernel number and device index. */ + /* Part 2: find a free minor, device node number and device index. */ #ifdef CONFIG_VIDEO_FIXED_MINOR_RANGES /* Keep the ranges for the first four types for historical * reasons. @@ -452,21 +478,22 @@ int video_register_device_index(struct video_device *vdev, int type, int nr, } #endif - /* Pick a minor number */ + /* Pick a device node number */ mutex_lock(&videodev_lock); - nr = find_next_zero_bit(video_nums[type], minor_cnt, nr == -1 ? 0 : nr); + nr = devnode_find(vdev, nr == -1 ? 0 : nr, minor_cnt); if (nr == minor_cnt) - nr = find_first_zero_bit(video_nums[type], minor_cnt); + nr = devnode_find(vdev, 0, minor_cnt); if (nr == minor_cnt) { - printk(KERN_ERR "could not get a free kernel number\n"); + printk(KERN_ERR "could not get a free device node number\n"); mutex_unlock(&videodev_lock); return -ENFILE; } #ifdef CONFIG_VIDEO_FIXED_MINOR_RANGES - /* 1-on-1 mapping of kernel number to minor number */ + /* 1-on-1 mapping of device node number to minor number */ i = nr; #else - /* The kernel number and minor numbers are independent */ + /* The device node number and minor numbers are independent, so + we just find the first free minor number. */ for (i = 0; i < VIDEO_NUM_DEVICES; i++) if (video_device[i] == NULL) break; @@ -478,17 +505,13 @@ int video_register_device_index(struct video_device *vdev, int type, int nr, #endif vdev->minor = i + minor_offset; vdev->num = nr; - set_bit(nr, video_nums[type]); + devnode_set(vdev); + /* Should not happen since we thought this minor was free */ WARN_ON(video_device[vdev->minor] != NULL); - ret = vdev->index = get_index(vdev, index); + vdev->index = get_index(vdev); mutex_unlock(&videodev_lock); - if (ret < 0) { - printk(KERN_ERR "%s: get_index failed\n", __func__); - goto cleanup; - } - /* Part 3: Initialize the character device */ vdev->cdev = cdev_alloc(); if (vdev->cdev == NULL) { @@ -517,7 +540,7 @@ int video_register_device_index(struct video_device *vdev, int type, int nr, vdev->dev.devt = MKDEV(VIDEO_MAJOR, vdev->minor); if (vdev->parent) vdev->dev.parent = vdev->parent; - dev_set_name(&vdev->dev, "%s%d", name_base, nr); + dev_set_name(&vdev->dev, "%s%d", name_base, vdev->num); ret = device_register(&vdev->dev); if (ret < 0) { printk(KERN_ERR "%s: device_register failed\n", __func__); @@ -527,6 +550,10 @@ int video_register_device_index(struct video_device *vdev, int type, int nr, reference to the device goes away. */ vdev->dev.release = v4l2_device_release; + if (nr != -1 && nr != vdev->num && warn_if_nr_in_use) + printk(KERN_WARNING "%s: requested %s%d, got %s%d\n", + __func__, name_base, nr, name_base, vdev->num); + /* Part 5: Activate this minor. The char device can now be used. */ mutex_lock(&videodev_lock); video_device[vdev->minor] = vdev; @@ -537,13 +564,24 @@ cleanup: mutex_lock(&videodev_lock); if (vdev->cdev) cdev_del(vdev->cdev); - clear_bit(vdev->num, video_nums[type]); + devnode_clear(vdev); mutex_unlock(&videodev_lock); /* Mark this video device as never having been registered. */ vdev->minor = -1; return ret; } -EXPORT_SYMBOL(video_register_device_index); + +int video_register_device(struct video_device *vdev, int type, int nr) +{ + return __video_register_device(vdev, type, nr, 1); +} +EXPORT_SYMBOL(video_register_device); + +int video_register_device_no_warn(struct video_device *vdev, int type, int nr) +{ + return __video_register_device(vdev, type, nr, 0); +} +EXPORT_SYMBOL(video_register_device_no_warn); /** * video_unregister_device - unregister a video4linux device diff --git a/drivers/media/video/vino.c b/drivers/media/video/vino.c index f3b6e15d91f2..cd6a3446ab7e 100644 --- a/drivers/media/video/vino.c +++ b/drivers/media/video/vino.c @@ -4333,11 +4333,11 @@ static int __init vino_module_init(void) vino_init_stage++; vino_drvdata->decoder = - v4l2_i2c_new_probed_subdev_addr(&vino_drvdata->v4l2_dev, - &vino_i2c_adapter, "saa7191", "saa7191", 0x45); + v4l2_i2c_new_subdev(&vino_drvdata->v4l2_dev, &vino_i2c_adapter, + "saa7191", "saa7191", 0, I2C_ADDRS(0x45)); vino_drvdata->camera = - v4l2_i2c_new_probed_subdev_addr(&vino_drvdata->v4l2_dev, - &vino_i2c_adapter, "indycam", "indycam", 0x2b); + v4l2_i2c_new_subdev(&vino_drvdata->v4l2_dev, &vino_i2c_adapter, + "indycam", "indycam", 0, I2C_ADDRS(0x2b)); dprintk("init complete!\n"); diff --git a/drivers/media/video/w9968cf.c b/drivers/media/video/w9968cf.c index 602484dd3da9..37fcdc447db5 100644 --- a/drivers/media/video/w9968cf.c +++ b/drivers/media/video/w9968cf.c @@ -3515,9 +3515,9 @@ w9968cf_usb_probe(struct usb_interface* intf, const struct usb_device_id* id) w9968cf_turn_on_led(cam); w9968cf_i2c_init(cam); - cam->sensor_sd = v4l2_i2c_new_probed_subdev(&cam->v4l2_dev, + cam->sensor_sd = v4l2_i2c_new_subdev(&cam->v4l2_dev, &cam->i2c_adapter, - "ovcamchip", "ovcamchip", addrs); + "ovcamchip", "ovcamchip", 0, addrs); usb_set_intfdata(intf, cam); mutex_unlock(&cam->dev_mutex); diff --git a/drivers/media/video/zc0301/zc0301_core.c b/drivers/media/video/zc0301/zc0301_core.c index 96971044fc78..b3c6436b33ba 100644 --- a/drivers/media/video/zc0301/zc0301_core.c +++ b/drivers/media/video/zc0301/zc0301_core.c @@ -819,8 +819,10 @@ zc0301_read(struct file* filp, char __user * buf, size_t count, loff_t* f_pos) (!list_empty(&cam->outqueue)) || (cam->state & DEV_DISCONNECTED) || (cam->state & DEV_MISCONFIGURED), - cam->module_param.frame_timeout * - 1000 * msecs_to_jiffies(1) ); + msecs_to_jiffies( + cam->module_param.frame_timeout * 1000 + ) + ); if (timeout < 0) { mutex_unlock(&cam->fileop_mutex); return timeout; diff --git a/drivers/media/video/zoran/zoran_card.c b/drivers/media/video/zoran/zoran_card.c index 0c4d9b1f8e6f..be70574870de 100644 --- a/drivers/media/video/zoran/zoran_card.c +++ b/drivers/media/video/zoran/zoran_card.c @@ -1357,15 +1357,15 @@ static int __devinit zoran_probe(struct pci_dev *pdev, goto zr_free_irq; } - zr->decoder = v4l2_i2c_new_probed_subdev(&zr->v4l2_dev, + zr->decoder = v4l2_i2c_new_subdev(&zr->v4l2_dev, &zr->i2c_adapter, zr->card.mod_decoder, zr->card.i2c_decoder, - zr->card.addrs_decoder); + 0, zr->card.addrs_decoder); if (zr->card.mod_encoder) - zr->encoder = v4l2_i2c_new_probed_subdev(&zr->v4l2_dev, + zr->encoder = v4l2_i2c_new_subdev(&zr->v4l2_dev, &zr->i2c_adapter, zr->card.mod_encoder, zr->card.i2c_encoder, - zr->card.addrs_encoder); + 0, zr->card.addrs_encoder); dprintk(2, KERN_INFO "%s: Initializing videocodec bus...\n", diff --git a/drivers/mtd/ubi/debug.c b/drivers/mtd/ubi/debug.c index 54b0186915fb..4876977e52cb 100644 --- a/drivers/mtd/ubi/debug.c +++ b/drivers/mtd/ubi/debug.c @@ -196,4 +196,36 @@ void ubi_dbg_dump_mkvol_req(const struct ubi_mkvol_req *req) printk(KERN_DEBUG "\t1st 16 characters of name: %s\n", nm); } +/** + * ubi_dbg_dump_flash - dump a region of flash. + * @ubi: UBI device description object + * @pnum: the physical eraseblock number to dump + * @offset: the starting offset within the physical eraseblock to dump + * @len: the length of the region to dump + */ +void ubi_dbg_dump_flash(struct ubi_device *ubi, int pnum, int offset, int len) +{ + int err; + size_t read; + void *buf; + loff_t addr = (loff_t)pnum * ubi->peb_size + offset; + + buf = vmalloc(len); + if (!buf) + return; + err = ubi->mtd->read(ubi->mtd, addr, len, &read, buf); + if (err && err != -EUCLEAN) { + ubi_err("error %d while reading %d bytes from PEB %d:%d, " + "read %zd bytes", err, len, pnum, offset, read); + goto out; + } + + dbg_msg("dumping %d bytes of data from PEB %d, offset %d", + len, pnum, offset); + print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, buf, len, 1); +out: + vfree(buf); + return; +} + #endif /* CONFIG_MTD_UBI_DEBUG */ diff --git a/drivers/mtd/ubi/debug.h b/drivers/mtd/ubi/debug.h index a4da7a09b949..f30bcb372c05 100644 --- a/drivers/mtd/ubi/debug.h +++ b/drivers/mtd/ubi/debug.h @@ -55,6 +55,7 @@ void ubi_dbg_dump_vtbl_record(const struct ubi_vtbl_record *r, int idx); void ubi_dbg_dump_sv(const struct ubi_scan_volume *sv); void ubi_dbg_dump_seb(const struct ubi_scan_leb *seb, int type); void ubi_dbg_dump_mkvol_req(const struct ubi_mkvol_req *req); +void ubi_dbg_dump_flash(struct ubi_device *ubi, int pnum, int offset, int len); #ifdef CONFIG_MTD_UBI_DEBUG_MSG /* General debugging messages */ @@ -167,6 +168,7 @@ static inline int ubi_dbg_is_erase_failure(void) #define ubi_dbg_dump_sv(sv) ({}) #define ubi_dbg_dump_seb(seb, type) ({}) #define ubi_dbg_dump_mkvol_req(req) ({}) +#define ubi_dbg_dump_flash(ubi, pnum, offset, len) ({}) #define UBI_IO_DEBUG 0 #define DBG_DISABLE_BGT 0 diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c index 4cb69925d8d9..8aa51e7a6a7d 100644 --- a/drivers/mtd/ubi/io.c +++ b/drivers/mtd/ubi/io.c @@ -269,6 +269,7 @@ int ubi_io_write(struct ubi_device *ubi, const void *buf, int pnum, int offset, ubi_err("error %d while writing %d bytes to PEB %d:%d, written " "%zd bytes", err, len, pnum, offset, written); ubi_dbg_dump_stack(); + ubi_dbg_dump_flash(ubi, pnum, offset, len); } else ubi_assert(written == len); @@ -475,30 +476,46 @@ out: */ static int nor_erase_prepare(struct ubi_device *ubi, int pnum) { - int err; + int err, err1; size_t written; loff_t addr; uint32_t data = 0; + struct ubi_vid_hdr vid_hdr; - addr = (loff_t)pnum * ubi->peb_size; + addr = (loff_t)pnum * ubi->peb_size + ubi->vid_hdr_aloffset; err = ubi->mtd->write(ubi->mtd, addr, 4, &written, (void *)&data); - if (err) { - ubi_err("error %d while writing 4 bytes to PEB %d:%d, written " - "%zd bytes", err, pnum, 0, written); - ubi_dbg_dump_stack(); - return err; + if (!err) { + addr -= ubi->vid_hdr_aloffset; + err = ubi->mtd->write(ubi->mtd, addr, 4, &written, + (void *)&data); + if (!err) + return 0; } - addr += ubi->vid_hdr_aloffset; - err = ubi->mtd->write(ubi->mtd, addr, 4, &written, (void *)&data); - if (err) { - ubi_err("error %d while writing 4 bytes to PEB %d:%d, written " - "%zd bytes", err, pnum, ubi->vid_hdr_aloffset, written); - ubi_dbg_dump_stack(); - return err; - } + /* + * We failed to write to the media. This was observed with Spansion + * S29GL512N NOR flash. Most probably the eraseblock erasure was + * interrupted at a very inappropriate moment, so it became unwritable. + * In this case we probably anyway have garbage in this PEB. + */ + err1 = ubi_io_read_vid_hdr(ubi, pnum, &vid_hdr, 0); + if (err1 == UBI_IO_BAD_VID_HDR) + /* + * The VID header is corrupted, so we can safely erase this + * PEB and not afraid that it will be treated as a valid PEB in + * case of an unclean reboot. + */ + return 0; - return 0; + /* + * The PEB contains a valid VID header, but we cannot invalidate it. + * Supposedly the flash media or the driver is screwed up, so return an + * error. + */ + ubi_err("cannot invalidate PEB %d, write returned %d read returned %d", + pnum, err, err1); + ubi_dbg_dump_flash(ubi, pnum, 0, ubi->peb_size); + return -EIO; } /** diff --git a/drivers/mtd/ubi/scan.c b/drivers/mtd/ubi/scan.c index b847745394b4..e7161adc419d 100644 --- a/drivers/mtd/ubi/scan.c +++ b/drivers/mtd/ubi/scan.c @@ -75,9 +75,10 @@ static int add_to_list(struct ubi_scan_info *si, int pnum, int ec, dbg_bld("add to free: PEB %d, EC %d", pnum, ec); else if (list == &si->erase) dbg_bld("add to erase: PEB %d, EC %d", pnum, ec); - else if (list == &si->corr) + else if (list == &si->corr) { dbg_bld("add to corrupted: PEB %d, EC %d", pnum, ec); - else if (list == &si->alien) + si->corr_count += 1; + } else if (list == &si->alien) dbg_bld("add to alien: PEB %d, EC %d", pnum, ec); else BUG(); @@ -864,7 +865,9 @@ static int process_eb(struct ubi_device *ubi, struct ubi_scan_info *si, } } - /* Both UBI headers seem to be fine */ + if (ec_corr) + ubi_warn("valid VID header but corrupted EC header at PEB %d", + pnum); err = ubi_scan_add_used(ubi, si, pnum, ec, vidh, bitflips); if (err) return err; @@ -935,6 +938,19 @@ struct ubi_scan_info *ubi_scan(struct ubi_device *ubi) if (si->is_empty) ubi_msg("empty MTD device detected"); + /* + * Few corrupted PEBs are not a problem and may be just a result of + * unclean reboots. However, many of them may indicate some problems + * with the flash HW or driver. Print a warning in this case. + */ + if (si->corr_count >= 8 || si->corr_count >= ubi->peb_count / 4) { + ubi_warn("%d PEBs are corrupted", si->corr_count); + printk(KERN_WARNING "corrupted PEBs are:"); + list_for_each_entry(seb, &si->corr, u.list) + printk(KERN_CONT " %d", seb->pnum); + printk(KERN_CONT "\n"); + } + /* * In case of unknown erase counter we use the mean erase counter * value. diff --git a/drivers/mtd/ubi/scan.h b/drivers/mtd/ubi/scan.h index 1017cf12def5..bab31695dace 100644 --- a/drivers/mtd/ubi/scan.h +++ b/drivers/mtd/ubi/scan.h @@ -102,6 +102,7 @@ struct ubi_scan_volume { * @mean_ec: mean erase counter value * @ec_sum: a temporary variable used when calculating @mean_ec * @ec_count: a temporary variable used when calculating @mean_ec + * @corr_count: count of corrupted PEBs * @image_seq_set: indicates @ubi->image_seq is known * * This data structure contains the result of scanning and may be used by other @@ -125,6 +126,7 @@ struct ubi_scan_info { int mean_ec; uint64_t ec_sum; int ec_count; + int corr_count; int image_seq_set; }; diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h index 6a5fe9633783..c290f51dd178 100644 --- a/drivers/mtd/ubi/ubi.h +++ b/drivers/mtd/ubi/ubi.h @@ -579,7 +579,8 @@ void ubi_do_get_volume_info(struct ubi_device *ubi, struct ubi_volume *vol, for (rb = rb_first(root), \ pos = (rb ? container_of(rb, typeof(*pos), member) : NULL); \ rb; \ - rb = rb_next(rb), pos = container_of(rb, typeof(*pos), member)) + rb = rb_next(rb), \ + pos = (rb ? container_of(rb, typeof(*pos), member) : NULL)) /** * ubi_zalloc_vid_hdr - allocate a volume identifier header object. diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index 10d3fcffe91c..82b34893e5b5 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -47,6 +47,8 @@ source "drivers/staging/slicoss/Kconfig" source "drivers/staging/go7007/Kconfig" +source "drivers/staging/cx25821/Kconfig" + source "drivers/staging/usbip/Kconfig" source "drivers/staging/winbond/Kconfig" diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index c30093bae621..b1cad0d9ba72 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_STAGING) += staging.o obj-$(CONFIG_ET131X) += et131x/ obj-$(CONFIG_SLICOSS) += slicoss/ obj-$(CONFIG_VIDEO_GO7007) += go7007/ +obj-$(CONFIG_VIDEO_CX25821) += cx25821/ obj-$(CONFIG_USB_IP_COMMON) += usbip/ obj-$(CONFIG_W35UND) += winbond/ obj-$(CONFIG_PRISM2_USB) += wlan-ng/ diff --git a/drivers/staging/cx25821/Kconfig b/drivers/staging/cx25821/Kconfig new file mode 100644 index 000000000000..df7756a95fad --- /dev/null +++ b/drivers/staging/cx25821/Kconfig @@ -0,0 +1,34 @@ +config VIDEO_CX25821 + tristate "Conexant cx25821 support" + depends on DVB_CORE && VIDEO_DEV && PCI && I2C && INPUT + select I2C_ALGOBIT + select VIDEO_BTCX + select VIDEO_TVEEPROM + select VIDEO_IR + select VIDEOBUF_DVB + select VIDEOBUF_DMA_SG + select VIDEO_CX25840 + select VIDEO_CX2341X + ---help--- + This is a video4linux driver for Conexant 25821 based + TV cards. + + To compile this driver as a module, choose M here: the + module will be called cx25821 + +config VIDEO_CX25821_ALSA + tristate "Conexant 25821 DMA audio support" + depends on VIDEO_CX25821 && SND && EXPERIMENTAL + select SND_PCM + ---help--- + This is a video4linux driver for direct (DMA) audio on + Conexant 25821 based capture cards using ALSA. + + It only works with boards with function 01 enabled. + To check if your board supports, use lspci -n. + If supported, you should see 14f1:8801 or 14f1:8811 + PCI device. + + To compile this driver as a module, choose M here: the + module will be called cx25821-alsa. + diff --git a/drivers/staging/cx25821/Makefile b/drivers/staging/cx25821/Makefile new file mode 100644 index 000000000000..10f87f05d8e8 --- /dev/null +++ b/drivers/staging/cx25821/Makefile @@ -0,0 +1,14 @@ +cx25821-objs := cx25821-core.o cx25821-cards.o cx25821-i2c.o cx25821-gpio.o \ + cx25821-medusa-video.o cx25821-video.o cx25821-video0.o cx25821-video1.o \ + cx25821-video2.o cx25821-video3.o cx25821-video4.o cx25821-video5.o \ + cx25821-video6.o cx25821-video7.o cx25821-vidups9.o cx25821-vidups10.o \ + cx25821-audups11.o cx25821-video-upstream.o cx25821-video-upstream-ch2.o \ + cx25821-audio-upstream.o cx25821-videoioctl.o + +obj-$(CONFIG_VIDEO_CX25821) += cx25821.o +obj-$(CONFIG_VIDEO_CX25821_ALSA) += cx25821-alsa.o + +EXTRA_CFLAGS += -Idrivers/media/video +EXTRA_CFLAGS += -Idrivers/media/common/tuners +EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core +EXTRA_CFLAGS += -Idrivers/media/dvb/frontends diff --git a/drivers/staging/cx25821/README b/drivers/staging/cx25821/README new file mode 100644 index 000000000000..a9ba50b9888b --- /dev/null +++ b/drivers/staging/cx25821/README @@ -0,0 +1,6 @@ +Todo: + - checkpatch.pl cleanups + - sparse cleanups + +Please send patches to linux-media@vger.kernel.org + diff --git a/drivers/staging/cx25821/cx25821-alsa.c b/drivers/staging/cx25821/cx25821-alsa.c new file mode 100644 index 000000000000..e0eef12759e4 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-alsa.c @@ -0,0 +1,789 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on SAA713x ALSA driver and CX88 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "cx25821.h" +#include "cx25821-reg.h" + +#define AUDIO_SRAM_CHANNEL SRAM_CH08 + +#define dprintk(level,fmt, arg...) if (debug >= level) \ + printk(KERN_INFO "%s/1: " fmt, chip->dev->name , ## arg) + +#define dprintk_core(level,fmt, arg...) if (debug >= level) \ + printk(KERN_DEBUG "%s/1: " fmt, chip->dev->name , ## arg) + +/**************************************************************************** + Data type declarations - Can be moded to a header file later + ****************************************************************************/ + +static struct snd_card *snd_cx25821_cards[SNDRV_CARDS]; +static int devno; + +struct cx25821_audio_dev { + struct cx25821_dev *dev; + struct cx25821_dmaqueue q; + + /* pci i/o */ + struct pci_dev *pci; + + /* audio controls */ + int irq; + + struct snd_card *card; + + unsigned long iobase; + spinlock_t reg_lock; + atomic_t count; + + unsigned int dma_size; + unsigned int period_size; + unsigned int num_periods; + + struct videobuf_dmabuf *dma_risc; + + struct cx25821_buffer *buf; + + struct snd_pcm_substream *substream; +}; +typedef struct cx25821_audio_dev snd_cx25821_card_t; + + +/**************************************************************************** + Module global static vars + ****************************************************************************/ + +static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ +static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ +static int enable[SNDRV_CARDS] = { 1,[1 ... (SNDRV_CARDS - 1)] = 1 }; + +module_param_array(enable, bool, NULL, 0444); +MODULE_PARM_DESC(enable, "Enable cx25821 soundcard. default enabled."); + +module_param_array(index, int, NULL, 0444); +MODULE_PARM_DESC(index, "Index value for cx25821 capture interface(s)."); + +/**************************************************************************** + Module macros + ****************************************************************************/ + +MODULE_DESCRIPTION("ALSA driver module for cx25821 based capture cards"); +MODULE_AUTHOR("Hiep Huynh"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("{{Conexant,25821}"); //"{{Conexant,23881}," + +static unsigned int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "enable debug messages"); + +/**************************************************************************** + Module specific funtions + ****************************************************************************/ +/* Constants taken from cx88-reg.h */ +#define AUD_INT_DN_RISCI1 (1 << 0) +#define AUD_INT_UP_RISCI1 (1 << 1) +#define AUD_INT_RDS_DN_RISCI1 (1 << 2) +#define AUD_INT_DN_RISCI2 (1 << 4) /* yes, 3 is skipped */ +#define AUD_INT_UP_RISCI2 (1 << 5) +#define AUD_INT_RDS_DN_RISCI2 (1 << 6) +#define AUD_INT_DN_SYNC (1 << 12) +#define AUD_INT_UP_SYNC (1 << 13) +#define AUD_INT_RDS_DN_SYNC (1 << 14) +#define AUD_INT_OPC_ERR (1 << 16) +#define AUD_INT_BER_IRQ (1 << 20) +#define AUD_INT_MCHG_IRQ (1 << 21) +#define GP_COUNT_CONTROL_RESET 0x3 + +#define PCI_MSK_AUD_EXT (1 << 4) +#define PCI_MSK_AUD_INT (1 << 3) +/* + * BOARD Specific: Sets audio DMA + */ + +static int _cx25821_start_audio_dma(snd_cx25821_card_t * chip) +{ + struct cx25821_buffer *buf = chip->buf; + struct cx25821_dev *dev = chip->dev; + struct sram_channel *audio_ch = + &cx25821_sram_channels[AUDIO_SRAM_CHANNEL]; + u32 tmp = 0; + + // enable output on the GPIO 0 for the MCLK ADC (Audio) + cx25821_set_gpiopin_direction(chip->dev, 0, 0); + + /* Make sure RISC/FIFO are off before changing FIFO/RISC settings */ + cx_clear(AUD_INT_DMA_CTL, + FLD_AUD_DST_A_RISC_EN | FLD_AUD_DST_A_FIFO_EN); + + /* setup fifo + format - out channel */ + cx25821_sram_channel_setup_audio(chip->dev, audio_ch, buf->bpl, + buf->risc.dma); + + /* sets bpl size */ + cx_write(AUD_A_LNGTH, buf->bpl); + + /* reset counter */ + cx_write(AUD_A_GPCNT_CTL, GP_COUNT_CONTROL_RESET); //GP_COUNT_CONTROL_RESET = 0x3 + atomic_set(&chip->count, 0); + + //Set the input mode to 16-bit + tmp = cx_read(AUD_A_CFG); + cx_write(AUD_A_CFG, + tmp | FLD_AUD_DST_PK_MODE | FLD_AUD_DST_ENABLE | + FLD_AUD_CLK_ENABLE); + + //printk(KERN_INFO "DEBUG: Start audio DMA, %d B/line, cmds_start(0x%x)= %d lines/FIFO, %d periods, %d " + // "byte buffer\n", buf->bpl, audio_ch->cmds_start, cx_read(audio_ch->cmds_start + 12)>>1, + // chip->num_periods, buf->bpl * chip->num_periods); + + /* Enables corresponding bits at AUD_INT_STAT */ + cx_write(AUD_A_INT_MSK, + FLD_AUD_DST_RISCI1 | FLD_AUD_DST_OF | FLD_AUD_DST_SYNC | + FLD_AUD_DST_OPC_ERR); + + /* Clean any pending interrupt bits already set */ + cx_write(AUD_A_INT_STAT, ~0); + + /* enable audio irqs */ + cx_set(PCI_INT_MSK, chip->dev->pci_irqmask | PCI_MSK_AUD_INT); + + // Turn on audio downstream fifo and risc enable 0x101 + tmp = cx_read(AUD_INT_DMA_CTL); + cx_set(AUD_INT_DMA_CTL, + tmp | (FLD_AUD_DST_A_RISC_EN | FLD_AUD_DST_A_FIFO_EN)); + + mdelay(100); + return 0; +} + +/* + * BOARD Specific: Resets audio DMA + */ +static int _cx25821_stop_audio_dma(snd_cx25821_card_t * chip) +{ + struct cx25821_dev *dev = chip->dev; + + /* stop dma */ + cx_clear(AUD_INT_DMA_CTL, + FLD_AUD_DST_A_RISC_EN | FLD_AUD_DST_A_FIFO_EN); + + /* disable irqs */ + cx_clear(PCI_INT_MSK, PCI_MSK_AUD_INT); + cx_clear(AUD_A_INT_MSK, + AUD_INT_OPC_ERR | AUD_INT_DN_SYNC | AUD_INT_DN_RISCI2 | + AUD_INT_DN_RISCI1); + + return 0; +} + +#define MAX_IRQ_LOOP 50 + +/* + * BOARD Specific: IRQ dma bits + */ +static char *cx25821_aud_irqs[32] = { + "dn_risci1", "up_risci1", "rds_dn_risc1", /* 0-2 */ + NULL, /* reserved */ + "dn_risci2", "up_risci2", "rds_dn_risc2", /* 4-6 */ + NULL, /* reserved */ + "dnf_of", "upf_uf", "rds_dnf_uf", /* 8-10 */ + NULL, /* reserved */ + "dn_sync", "up_sync", "rds_dn_sync", /* 12-14 */ + NULL, /* reserved */ + "opc_err", "par_err", "rip_err", /* 16-18 */ + "pci_abort", "ber_irq", "mchg_irq" /* 19-21 */ +}; + +/* + * BOARD Specific: Threats IRQ audio specific calls + */ +static void cx25821_aud_irq(snd_cx25821_card_t * chip, u32 status, u32 mask) +{ + struct cx25821_dev *dev = chip->dev; + + if (0 == (status & mask)) { + return; + } + + cx_write(AUD_A_INT_STAT, status); + if (debug > 1 || (status & mask & ~0xff)) + cx25821_print_irqbits(dev->name, "irq aud", + cx25821_aud_irqs, + ARRAY_SIZE(cx25821_aud_irqs), status, + mask); + + /* risc op code error */ + if (status & AUD_INT_OPC_ERR) { + printk(KERN_WARNING "WARNING %s/1: Audio risc op code error\n", + dev->name); + + cx_clear(AUD_INT_DMA_CTL, + FLD_AUD_DST_A_RISC_EN | FLD_AUD_DST_A_FIFO_EN); + cx25821_sram_channel_dump_audio(dev, + &cx25821_sram_channels + [AUDIO_SRAM_CHANNEL]); + } + if (status & AUD_INT_DN_SYNC) { + printk(KERN_WARNING "WARNING %s: Downstream sync error!\n", + dev->name); + cx_write(AUD_A_GPCNT_CTL, GP_COUNT_CONTROL_RESET); + return; + } + + /* risc1 downstream */ + if (status & AUD_INT_DN_RISCI1) { + atomic_set(&chip->count, cx_read(AUD_A_GPCNT)); + snd_pcm_period_elapsed(chip->substream); + } +} + +/* + * BOARD Specific: Handles IRQ calls + */ +static irqreturn_t cx25821_irq(int irq, void *dev_id) +{ + snd_cx25821_card_t *chip = dev_id; + struct cx25821_dev *dev = chip->dev; + u32 status, pci_status; + u32 audint_status, audint_mask; + int loop, handled = 0; + int audint_count = 0; + + audint_status = cx_read(AUD_A_INT_STAT); + audint_mask = cx_read(AUD_A_INT_MSK); + audint_count = cx_read(AUD_A_GPCNT); + status = cx_read(PCI_INT_STAT); + + for (loop = 0; loop < 1; loop++) { + status = cx_read(PCI_INT_STAT); + if (0 == status) { + status = cx_read(PCI_INT_STAT); + audint_status = cx_read(AUD_A_INT_STAT); + audint_mask = cx_read(AUD_A_INT_MSK); + + if (status) { + handled = 1; + cx_write(PCI_INT_STAT, status); + + cx25821_aud_irq(chip, audint_status, + audint_mask); + break; + } else + goto out; + } + + handled = 1; + cx_write(PCI_INT_STAT, status); + + cx25821_aud_irq(chip, audint_status, audint_mask); + } + + pci_status = cx_read(PCI_INT_STAT); + + if (handled) + cx_write(PCI_INT_STAT, pci_status); + + out: + return IRQ_RETVAL(handled); +} + +static int dsp_buffer_free(snd_cx25821_card_t * chip) +{ + BUG_ON(!chip->dma_size); + + dprintk(2, "Freeing buffer\n"); + videobuf_sg_dma_unmap(&chip->pci->dev, chip->dma_risc); + videobuf_dma_free(chip->dma_risc); + btcx_riscmem_free(chip->pci, &chip->buf->risc); + kfree(chip->buf); + + chip->dma_risc = NULL; + chip->dma_size = 0; + + return 0; +} + +/**************************************************************************** + ALSA PCM Interface + ****************************************************************************/ + +/* + * Digital hardware definition + */ +#define DEFAULT_FIFO_SIZE 384 +static struct snd_pcm_hardware snd_cx25821_digital_hw = { + .info = SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP_VALID, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + + .rates = SNDRV_PCM_RATE_48000, + .rate_min = 48000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + /* Analog audio output will be full of clicks and pops if there + are not exactly four lines in the SRAM FIFO buffer. */ + .period_bytes_min = DEFAULT_FIFO_SIZE / 3, + .period_bytes_max = DEFAULT_FIFO_SIZE / 3, + .periods_min = 1, + .periods_max = AUDIO_LINE_SIZE, + .buffer_bytes_max = (AUDIO_LINE_SIZE * AUDIO_LINE_SIZE), //128*128 = 16384 = 1024 * 16 +}; + +/* + * audio pcm capture open callback + */ +static int snd_cx25821_pcm_open(struct snd_pcm_substream *substream) +{ + snd_cx25821_card_t *chip = snd_pcm_substream_chip(substream); + struct snd_pcm_runtime *runtime = substream->runtime; + int err; + unsigned int bpl = 0; + + if (!chip) { + printk(KERN_ERR "DEBUG: cx25821 can't find device struct." + " Can't proceed with open\n"); + return -ENODEV; + } + + err = + snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIODS); + if (err < 0) + goto _error; + + chip->substream = substream; + + runtime->hw = snd_cx25821_digital_hw; + + if (cx25821_sram_channels[AUDIO_SRAM_CHANNEL].fifo_size != + DEFAULT_FIFO_SIZE) { + bpl = cx25821_sram_channels[AUDIO_SRAM_CHANNEL].fifo_size / 3; //since there are 3 audio Clusters + bpl &= ~7; /* must be multiple of 8 */ + + if (bpl > AUDIO_LINE_SIZE) { + bpl = AUDIO_LINE_SIZE; + } + runtime->hw.period_bytes_min = bpl; + runtime->hw.period_bytes_max = bpl; + } + + return 0; + _error: + dprintk(1, "Error opening PCM!\n"); + return err; +} + +/* + * audio close callback + */ +static int snd_cx25821_close(struct snd_pcm_substream *substream) +{ + return 0; +} + +/* + * hw_params callback + */ +static int snd_cx25821_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *hw_params) +{ + snd_cx25821_card_t *chip = snd_pcm_substream_chip(substream); + struct videobuf_dmabuf *dma; + + struct cx25821_buffer *buf; + int ret; + + if (substream->runtime->dma_area) { + dsp_buffer_free(chip); + substream->runtime->dma_area = NULL; + } + + chip->period_size = params_period_bytes(hw_params); + chip->num_periods = params_periods(hw_params); + chip->dma_size = chip->period_size * params_periods(hw_params); + + BUG_ON(!chip->dma_size); + BUG_ON(chip->num_periods & (chip->num_periods - 1)); + + buf = videobuf_sg_alloc(sizeof(*buf)); + if (NULL == buf) + return -ENOMEM; + + if (chip->period_size > AUDIO_LINE_SIZE) { + chip->period_size = AUDIO_LINE_SIZE; + } + + buf->vb.memory = V4L2_MEMORY_MMAP; + buf->vb.field = V4L2_FIELD_NONE; + buf->vb.width = chip->period_size; + buf->bpl = chip->period_size; + buf->vb.height = chip->num_periods; + buf->vb.size = chip->dma_size; + + dma = videobuf_to_dma(&buf->vb); + videobuf_dma_init(dma); + + ret = videobuf_dma_init_kernel(dma, PCI_DMA_FROMDEVICE, + (PAGE_ALIGN(buf->vb.size) >> + PAGE_SHIFT)); + if (ret < 0) + goto error; + + ret = videobuf_sg_dma_map(&chip->pci->dev, dma); + if (ret < 0) + goto error; + + ret = + cx25821_risc_databuffer_audio(chip->pci, &buf->risc, dma->sglist, + buf->vb.width, buf->vb.height, 1); + if (ret < 0) { + printk(KERN_INFO + "DEBUG: ERROR after cx25821_risc_databuffer_audio() \n"); + goto error; + } + + /* Loop back to start of program */ + buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); + buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma); + buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ + + buf->vb.state = VIDEOBUF_PREPARED; + + chip->buf = buf; + chip->dma_risc = dma; + + substream->runtime->dma_area = chip->dma_risc->vmalloc; + substream->runtime->dma_bytes = chip->dma_size; + substream->runtime->dma_addr = 0; + + return 0; + + error: + kfree(buf); + return ret; +} + +/* + * hw free callback + */ +static int snd_cx25821_hw_free(struct snd_pcm_substream *substream) +{ + snd_cx25821_card_t *chip = snd_pcm_substream_chip(substream); + + if (substream->runtime->dma_area) { + dsp_buffer_free(chip); + substream->runtime->dma_area = NULL; + } + + return 0; +} + +/* + * prepare callback + */ +static int snd_cx25821_prepare(struct snd_pcm_substream *substream) +{ + return 0; +} + +/* + * trigger callback + */ +static int snd_cx25821_card_trigger(struct snd_pcm_substream *substream, + int cmd) +{ + snd_cx25821_card_t *chip = snd_pcm_substream_chip(substream); + int err = 0; + + /* Local interrupts are already disabled by ALSA */ + spin_lock(&chip->reg_lock); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + err = _cx25821_start_audio_dma(chip); + break; + case SNDRV_PCM_TRIGGER_STOP: + err = _cx25821_stop_audio_dma(chip); + break; + default: + err = -EINVAL; + break; + } + + spin_unlock(&chip->reg_lock); + + return err; +} + +/* + * pointer callback + */ +static snd_pcm_uframes_t snd_cx25821_pointer(struct snd_pcm_substream + *substream) +{ + snd_cx25821_card_t *chip = snd_pcm_substream_chip(substream); + struct snd_pcm_runtime *runtime = substream->runtime; + u16 count; + + count = atomic_read(&chip->count); + + return runtime->period_size * (count & (runtime->periods - 1)); +} + +/* + * page callback (needed for mmap) + */ +static struct page *snd_cx25821_page(struct snd_pcm_substream *substream, + unsigned long offset) +{ + void *pageptr = substream->runtime->dma_area + offset; + + return vmalloc_to_page(pageptr); +} + +/* + * operators + */ +static struct snd_pcm_ops snd_cx25821_pcm_ops = { + .open = snd_cx25821_pcm_open, + .close = snd_cx25821_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = snd_cx25821_hw_params, + .hw_free = snd_cx25821_hw_free, + .prepare = snd_cx25821_prepare, + .trigger = snd_cx25821_card_trigger, + .pointer = snd_cx25821_pointer, + .page = snd_cx25821_page, +}; + +/* + * ALSA create a PCM device: Called when initializing the board. Sets up the name and hooks up + * the callbacks + */ +static int snd_cx25821_pcm(snd_cx25821_card_t * chip, int device, char *name) +{ + struct snd_pcm *pcm; + int err; + + err = snd_pcm_new(chip->card, name, device, 0, 1, &pcm); + if (err < 0) { + printk(KERN_INFO "ERROR: FAILED snd_pcm_new() in %s\n", + __func__); + return err; + } + pcm->private_data = chip; + pcm->info_flags = 0; + strcpy(pcm->name, name); + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cx25821_pcm_ops); + + return 0; +} + +/**************************************************************************** + Basic Flow for Sound Devices + ****************************************************************************/ + +/* + * PCI ID Table - 14f1:8801 and 14f1:8811 means function 1: Audio + * Only boards with eeprom and byte 1 at eeprom=1 have it + */ + +static struct pci_device_id cx25821_audio_pci_tbl[] __devinitdata = { + {0x14f1, 0x0920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, + {0,} +}; + +MODULE_DEVICE_TABLE(pci, cx25821_audio_pci_tbl); + +/* + * Not used in the function snd_cx25821_dev_free so removing + * from the file. + */ +/* +static int snd_cx25821_free(snd_cx25821_card_t *chip) +{ + if (chip->irq >= 0) + free_irq(chip->irq, chip); + + cx25821_dev_unregister(chip->dev); + pci_disable_device(chip->pci); + + return 0; +} +*/ + +/* + * Component Destructor + */ +static void snd_cx25821_dev_free(struct snd_card *card) +{ + snd_cx25821_card_t *chip = card->private_data; + + //snd_cx25821_free(chip); + snd_card_free(chip->card); +} + +/* + * Alsa Constructor - Component probe + */ +static int cx25821_audio_initdev(struct cx25821_dev *dev) +{ + struct snd_card *card; + snd_cx25821_card_t *chip; + int err; + + if (devno >= SNDRV_CARDS) { + printk(KERN_INFO "DEBUG ERROR: devno >= SNDRV_CARDS %s\n", + __func__); + return (-ENODEV); + } + + if (!enable[devno]) { + ++devno; + printk(KERN_INFO "DEBUG ERROR: !enable[devno] %s\n", __func__); + return (-ENOENT); + } + + err = snd_card_create(index[devno], id[devno], THIS_MODULE, + sizeof(snd_cx25821_card_t), &card); + if (err < 0) { + printk(KERN_INFO + "DEBUG ERROR: cannot create snd_card_new in %s\n", + __func__); + return err; + } + + strcpy(card->driver, "cx25821"); + + /* Card "creation" */ + card->private_free = snd_cx25821_dev_free; + chip = (snd_cx25821_card_t *) card->private_data; + spin_lock_init(&chip->reg_lock); + + chip->dev = dev; + chip->card = card; + chip->pci = dev->pci; + chip->iobase = pci_resource_start(dev->pci, 0); + + chip->irq = dev->pci->irq; + + err = request_irq(dev->pci->irq, cx25821_irq, + IRQF_SHARED | IRQF_DISABLED, chip->dev->name, chip); + + if (err < 0) { + printk(KERN_ERR "ERROR %s: can't get IRQ %d for ALSA\n", + chip->dev->name, dev->pci->irq); + goto error; + } + + if ((err = snd_cx25821_pcm(chip, 0, "cx25821 Digital")) < 0) { + printk(KERN_INFO + "DEBUG ERROR: cannot create snd_cx25821_pcm %s\n", + __func__); + goto error; + } + + snd_card_set_dev(card, &chip->pci->dev); + + strcpy(card->shortname, "cx25821"); + sprintf(card->longname, "%s at 0x%lx irq %d", chip->dev->name, + chip->iobase, chip->irq); + strcpy(card->mixername, "CX25821"); + + printk(KERN_INFO "%s/%i: ALSA support for cx25821 boards\n", + card->driver, devno); + + err = snd_card_register(card); + if (err < 0) { + printk(KERN_INFO "DEBUG ERROR: cannot register sound card %s\n", + __func__); + goto error; + } + + snd_cx25821_cards[devno] = card; + + devno++; + return 0; + + error: + snd_card_free(card); + return err; +} + +/**************************************************************************** + LINUX MODULE INIT + ****************************************************************************/ +static void cx25821_audio_fini(void) +{ + snd_card_free(snd_cx25821_cards[0]); +} + +/* + * Module initializer + * + * Loops through present saa7134 cards, and assigns an ALSA device + * to each one + * + */ +static int cx25821_alsa_init(void) +{ + struct cx25821_dev *dev = NULL; + struct list_head *list; + + list_for_each(list, &cx25821_devlist) { + dev = list_entry(list, struct cx25821_dev, devlist); + cx25821_audio_initdev(dev); + } + + if (dev == NULL) + printk(KERN_INFO + "cx25821 ERROR ALSA: no cx25821 cards found\n"); + + return 0; + +} + +late_initcall(cx25821_alsa_init); +module_exit(cx25821_audio_fini); + +/* ----------------------------------------------------------- */ +/* + * Local variables: + * c-basic-offset: 8 + * End: + */ diff --git a/drivers/staging/cx25821/cx25821-audio-upstream.c b/drivers/staging/cx25821/cx25821-audio-upstream.c new file mode 100644 index 000000000000..ddddf651266b --- /dev/null +++ b/drivers/staging/cx25821/cx25821-audio-upstream.c @@ -0,0 +1,804 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821-video.h" +#include "cx25821-audio-upstream.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards"); +MODULE_AUTHOR("Hiep Huynh "); +MODULE_LICENSE("GPL"); + +static int _intr_msk = + FLD_AUD_SRC_RISCI1 | FLD_AUD_SRC_OF | FLD_AUD_SRC_SYNC | + FLD_AUD_SRC_OPC_ERR; + +int cx25821_sram_channel_setup_upstream_audio(struct cx25821_dev *dev, + struct sram_channel *ch, + unsigned int bpl, u32 risc) +{ + unsigned int i, lines; + u32 cdt; + + if (ch->cmds_start == 0) { + cx_write(ch->ptr1_reg, 0); + cx_write(ch->ptr2_reg, 0); + cx_write(ch->cnt2_reg, 0); + cx_write(ch->cnt1_reg, 0); + return 0; + } + + bpl = (bpl + 7) & ~7; /* alignment */ + cdt = ch->cdt; + lines = ch->fifo_size / bpl; + + if (lines > 3) { + lines = 3; + } + + BUG_ON(lines < 2); + + /* write CDT */ + for (i = 0; i < lines; i++) { + cx_write(cdt + 16 * i, ch->fifo_start + bpl * i); + cx_write(cdt + 16 * i + 4, 0); + cx_write(cdt + 16 * i + 8, 0); + cx_write(cdt + 16 * i + 12, 0); + } + + /* write CMDS */ + cx_write(ch->cmds_start + 0, risc); + + cx_write(ch->cmds_start + 4, 0); + cx_write(ch->cmds_start + 8, cdt); + cx_write(ch->cmds_start + 12, AUDIO_CDT_SIZE_QW); + cx_write(ch->cmds_start + 16, ch->ctrl_start); + + //IQ size + cx_write(ch->cmds_start + 20, AUDIO_IQ_SIZE_DW); + + for (i = 24; i < 80; i += 4) + cx_write(ch->cmds_start + i, 0); + + /* fill registers */ + cx_write(ch->ptr1_reg, ch->fifo_start); + cx_write(ch->ptr2_reg, cdt); + cx_write(ch->cnt2_reg, AUDIO_CDT_SIZE_QW); + cx_write(ch->cnt1_reg, AUDIO_CLUSTER_SIZE_QW - 1); + + return 0; +} + +static __le32 *cx25821_risc_field_upstream_audio(struct cx25821_dev *dev, + __le32 * rp, + dma_addr_t databuf_phys_addr, + unsigned int bpl, + int fifo_enable) +{ + unsigned int line; + struct sram_channel *sram_ch = + &dev->sram_channels[dev->_audio_upstream_channel_select]; + int offset = 0; + + /* scan lines */ + for (line = 0; line < LINES_PER_AUDIO_BUFFER; line++) { + *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl); + *(rp++) = cpu_to_le32(databuf_phys_addr + offset); + *(rp++) = cpu_to_le32(0); /* bits 63-32 */ + + // Check if we need to enable the FIFO after the first 3 lines + // For the upstream audio channel, the risc engine will enable the FIFO. + if (fifo_enable && line == 2) { + *(rp++) = RISC_WRITECR; + *(rp++) = sram_ch->dma_ctl; + *(rp++) = sram_ch->fld_aud_fifo_en; + *(rp++) = 0x00000020; + } + + offset += AUDIO_LINE_SIZE; + } + + return rp; +} + +int cx25821_risc_buffer_upstream_audio(struct cx25821_dev *dev, + struct pci_dev *pci, + unsigned int bpl, unsigned int lines) +{ + __le32 *rp; + int fifo_enable = 0; + int frame = 0, i = 0; + int frame_size = AUDIO_DATA_BUF_SZ; + int databuf_offset = 0; + int risc_flag = RISC_CNT_INC; + dma_addr_t risc_phys_jump_addr; + + /* Virtual address of Risc buffer program */ + rp = dev->_risc_virt_addr; + + /* sync instruction */ + *(rp++) = cpu_to_le32(RISC_RESYNC | AUDIO_SYNC_LINE); + + for (frame = 0; frame < NUM_AUDIO_FRAMES; frame++) { + databuf_offset = frame_size * frame; + + if (frame == 0) { + fifo_enable = 1; + risc_flag = RISC_CNT_RESET; + } else { + fifo_enable = 0; + risc_flag = RISC_CNT_INC; + } + + //Calculate physical jump address + if ((frame + 1) == NUM_AUDIO_FRAMES) { + risc_phys_jump_addr = + dev->_risc_phys_start_addr + + RISC_SYNC_INSTRUCTION_SIZE; + } else { + risc_phys_jump_addr = + dev->_risc_phys_start_addr + + RISC_SYNC_INSTRUCTION_SIZE + + AUDIO_RISC_DMA_BUF_SIZE * (frame + 1); + } + + rp = cx25821_risc_field_upstream_audio(dev, rp, + dev-> + _audiodata_buf_phys_addr + + databuf_offset, bpl, + fifo_enable); + + if (USE_RISC_NOOP_AUDIO) { + for (i = 0; i < NUM_NO_OPS; i++) { + *(rp++) = cpu_to_le32(RISC_NOOP); + } + } + + // Loop to (Nth)FrameRISC or to Start of Risc program & generate IRQ + *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag); + *(rp++) = cpu_to_le32(risc_phys_jump_addr); + *(rp++) = cpu_to_le32(0); + + //Recalculate virtual address based on frame index + rp = dev->_risc_virt_addr + RISC_SYNC_INSTRUCTION_SIZE / 4 + + (AUDIO_RISC_DMA_BUF_SIZE * (frame + 1) / 4); + } + + return 0; +} + +void cx25821_free_memory_audio(struct cx25821_dev *dev) +{ + if (dev->_risc_virt_addr) { + pci_free_consistent(dev->pci, dev->_audiorisc_size, + dev->_risc_virt_addr, dev->_risc_phys_addr); + dev->_risc_virt_addr = NULL; + } + + if (dev->_audiodata_buf_virt_addr) { + pci_free_consistent(dev->pci, dev->_audiodata_buf_size, + dev->_audiodata_buf_virt_addr, + dev->_audiodata_buf_phys_addr); + dev->_audiodata_buf_virt_addr = NULL; + } +} + +void cx25821_stop_upstream_audio(struct cx25821_dev *dev) +{ + struct sram_channel *sram_ch = + &dev->sram_channels[AUDIO_UPSTREAM_SRAM_CHANNEL_B]; + u32 tmp = 0; + + if (!dev->_audio_is_running) { + printk + ("cx25821: No audio file is currently running so return!\n"); + return; + } + //Disable RISC interrupts + cx_write(sram_ch->int_msk, 0); + + //Turn OFF risc and fifo enable in AUD_DMA_CNTRL + tmp = cx_read(sram_ch->dma_ctl); + cx_write(sram_ch->dma_ctl, + tmp & ~(sram_ch->fld_aud_fifo_en | sram_ch->fld_aud_risc_en)); + + //Clear data buffer memory + if (dev->_audiodata_buf_virt_addr) + memset(dev->_audiodata_buf_virt_addr, 0, + dev->_audiodata_buf_size); + + dev->_audio_is_running = 0; + dev->_is_first_audio_frame = 0; + dev->_audioframe_count = 0; + dev->_audiofile_status = END_OF_FILE; + + if (dev->_irq_audio_queues) { + kfree(dev->_irq_audio_queues); + dev->_irq_audio_queues = NULL; + } + + if (dev->_audiofilename != NULL) + kfree(dev->_audiofilename); +} + +void cx25821_free_mem_upstream_audio(struct cx25821_dev *dev) +{ + if (dev->_audio_is_running) { + cx25821_stop_upstream_audio(dev); + } + + cx25821_free_memory_audio(dev); +} + +int cx25821_get_audio_data(struct cx25821_dev *dev, + struct sram_channel *sram_ch) +{ + struct file *myfile; + int frame_index_temp = dev->_audioframe_index; + int i = 0; + int line_size = AUDIO_LINE_SIZE; + int frame_size = AUDIO_DATA_BUF_SZ; + int frame_offset = frame_size * frame_index_temp; + ssize_t vfs_read_retval = 0; + char mybuf[line_size]; + loff_t file_offset = dev->_audioframe_count * frame_size; + loff_t pos; + mm_segment_t old_fs; + + if (dev->_audiofile_status == END_OF_FILE) + return 0; + + myfile = filp_open(dev->_audiofilename, O_RDONLY | O_LARGEFILE, 0); + + if (IS_ERR(myfile)) { + const int open_errno = -PTR_ERR(myfile); + printk("%s(): ERROR opening file(%s) with errno = %d! \n", + __func__, dev->_audiofilename, open_errno); + return PTR_ERR(myfile); + } else { + if (!(myfile->f_op)) { + printk("%s: File has no file operations registered!\n", + __func__); + filp_close(myfile, NULL); + return -EIO; + } + + if (!myfile->f_op->read) { + printk("%s: File has no READ operations registered! \n", + __func__); + filp_close(myfile, NULL); + return -EIO; + } + + pos = myfile->f_pos; + old_fs = get_fs(); + set_fs(KERNEL_DS); + + for (i = 0; i < dev->_audio_lines_count; i++) { + pos = file_offset; + + vfs_read_retval = + vfs_read(myfile, mybuf, line_size, &pos); + + if (vfs_read_retval > 0 && vfs_read_retval == line_size + && dev->_audiodata_buf_virt_addr != NULL) { + memcpy((void *)(dev->_audiodata_buf_virt_addr + + frame_offset / 4), mybuf, + vfs_read_retval); + } + + file_offset += vfs_read_retval; + frame_offset += vfs_read_retval; + + if (vfs_read_retval < line_size) { + printk(KERN_INFO + "Done: exit %s() since no more bytes to read from Audio file.\n", + __func__); + break; + } + } + + if (i > 0) + dev->_audioframe_count++; + + dev->_audiofile_status = + (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE; + + set_fs(old_fs); + filp_close(myfile, NULL); + } + + return 0; +} + +static void cx25821_audioups_handler(struct work_struct *work) +{ + struct cx25821_dev *dev = + container_of(work, struct cx25821_dev, _audio_work_entry); + + if (!dev) { + printk("ERROR %s(): since container_of(work_struct) FAILED! \n", + __func__); + return; + } + + cx25821_get_audio_data(dev, + &dev->sram_channels[dev-> + _audio_upstream_channel_select]); +} + +int cx25821_openfile_audio(struct cx25821_dev *dev, + struct sram_channel *sram_ch) +{ + struct file *myfile; + int i = 0, j = 0; + int line_size = AUDIO_LINE_SIZE; + ssize_t vfs_read_retval = 0; + char mybuf[line_size]; + loff_t pos; + loff_t offset = (unsigned long)0; + mm_segment_t old_fs; + + myfile = filp_open(dev->_audiofilename, O_RDONLY | O_LARGEFILE, 0); + + if (IS_ERR(myfile)) { + const int open_errno = -PTR_ERR(myfile); + printk("%s(): ERROR opening file(%s) with errno = %d! \n", + __func__, dev->_audiofilename, open_errno); + return PTR_ERR(myfile); + } else { + if (!(myfile->f_op)) { + printk("%s: File has no file operations registered! \n", + __func__); + filp_close(myfile, NULL); + return -EIO; + } + + if (!myfile->f_op->read) { + printk("%s: File has no READ operations registered! \n", + __func__); + filp_close(myfile, NULL); + return -EIO; + } + + pos = myfile->f_pos; + old_fs = get_fs(); + set_fs(KERNEL_DS); + + for (j = 0; j < NUM_AUDIO_FRAMES; j++) { + for (i = 0; i < dev->_audio_lines_count; i++) { + pos = offset; + + vfs_read_retval = + vfs_read(myfile, mybuf, line_size, &pos); + + if (vfs_read_retval > 0 + && vfs_read_retval == line_size + && dev->_audiodata_buf_virt_addr != NULL) { + memcpy((void *)(dev-> + _audiodata_buf_virt_addr + + offset / 4), mybuf, + vfs_read_retval); + } + + offset += vfs_read_retval; + + if (vfs_read_retval < line_size) { + printk(KERN_INFO + "Done: exit %s() since no more bytes to read from Audio file.\n", + __func__); + break; + } + } + + if (i > 0) { + dev->_audioframe_count++; + } + + if (vfs_read_retval < line_size) { + break; + } + } + + dev->_audiofile_status = + (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE; + + set_fs(old_fs); + myfile->f_pos = 0; + filp_close(myfile, NULL); + } + + return 0; +} + +static int cx25821_audio_upstream_buffer_prepare(struct cx25821_dev *dev, + struct sram_channel *sram_ch, + int bpl) +{ + int ret = 0; + dma_addr_t dma_addr; + dma_addr_t data_dma_addr; + + cx25821_free_memory_audio(dev); + + dev->_risc_virt_addr = + pci_alloc_consistent(dev->pci, dev->audio_upstream_riscbuf_size, + &dma_addr); + dev->_risc_virt_start_addr = dev->_risc_virt_addr; + dev->_risc_phys_start_addr = dma_addr; + dev->_risc_phys_addr = dma_addr; + dev->_audiorisc_size = dev->audio_upstream_riscbuf_size; + + if (!dev->_risc_virt_addr) { + printk + ("cx25821 ERROR: pci_alloc_consistent() FAILED to allocate memory for RISC program! Returning.\n"); + return -ENOMEM; + } + //Clear out memory at address + memset(dev->_risc_virt_addr, 0, dev->_audiorisc_size); + + //For Audio Data buffer allocation + dev->_audiodata_buf_virt_addr = + pci_alloc_consistent(dev->pci, dev->audio_upstream_databuf_size, + &data_dma_addr); + dev->_audiodata_buf_phys_addr = data_dma_addr; + dev->_audiodata_buf_size = dev->audio_upstream_databuf_size; + + if (!dev->_audiodata_buf_virt_addr) { + printk + ("cx25821 ERROR: pci_alloc_consistent() FAILED to allocate memory for data buffer! Returning. \n"); + return -ENOMEM; + } + //Clear out memory at address + memset(dev->_audiodata_buf_virt_addr, 0, dev->_audiodata_buf_size); + + ret = cx25821_openfile_audio(dev, sram_ch); + if (ret < 0) + return ret; + + //Creating RISC programs + ret = + cx25821_risc_buffer_upstream_audio(dev, dev->pci, bpl, + dev->_audio_lines_count); + if (ret < 0) { + printk(KERN_DEBUG + "cx25821 ERROR creating audio upstream RISC programs! \n"); + goto error; + } + + return 0; + + error: + return ret; +} + +int cx25821_audio_upstream_irq(struct cx25821_dev *dev, int chan_num, + u32 status) +{ + int i = 0; + u32 int_msk_tmp; + struct sram_channel *channel = &dev->sram_channels[chan_num]; + dma_addr_t risc_phys_jump_addr; + __le32 *rp; + + if (status & FLD_AUD_SRC_RISCI1) { + //Get interrupt_index of the program that interrupted + u32 prog_cnt = cx_read(channel->gpcnt); + + //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers + cx_write(channel->int_msk, 0); + cx_write(channel->int_stat, cx_read(channel->int_stat)); + + spin_lock(&dev->slock); + + while (prog_cnt != dev->_last_index_irq) { + //Update _last_index_irq + if (dev->_last_index_irq < (NUMBER_OF_PROGRAMS - 1)) { + dev->_last_index_irq++; + } else { + dev->_last_index_irq = 0; + } + + dev->_audioframe_index = dev->_last_index_irq; + + queue_work(dev->_irq_audio_queues, + &dev->_audio_work_entry); + } + + if (dev->_is_first_audio_frame) { + dev->_is_first_audio_frame = 0; + + if (dev->_risc_virt_start_addr != NULL) { + risc_phys_jump_addr = + dev->_risc_phys_start_addr + + RISC_SYNC_INSTRUCTION_SIZE + + AUDIO_RISC_DMA_BUF_SIZE; + + rp = cx25821_risc_field_upstream_audio(dev, + dev-> + _risc_virt_start_addr + + 1, + dev-> + _audiodata_buf_phys_addr, + AUDIO_LINE_SIZE, + FIFO_DISABLE); + + if (USE_RISC_NOOP_AUDIO) { + for (i = 0; i < NUM_NO_OPS; i++) { + *(rp++) = + cpu_to_le32(RISC_NOOP); + } + } + // Jump to 2nd Audio Frame + *(rp++) = + cpu_to_le32(RISC_JUMP | RISC_IRQ1 | + RISC_CNT_RESET); + *(rp++) = cpu_to_le32(risc_phys_jump_addr); + *(rp++) = cpu_to_le32(0); + } + } + + spin_unlock(&dev->slock); + } else { + if (status & FLD_AUD_SRC_OF) + printk("%s: Audio Received Overflow Error Interrupt!\n", + __func__); + + if (status & FLD_AUD_SRC_SYNC) + printk("%s: Audio Received Sync Error Interrupt!\n", + __func__); + + if (status & FLD_AUD_SRC_OPC_ERR) + printk("%s: Audio Received OpCode Error Interrupt!\n", + __func__); + + // Read and write back the interrupt status register to clear our bits + cx_write(channel->int_stat, cx_read(channel->int_stat)); + } + + if (dev->_audiofile_status == END_OF_FILE) { + printk("cx25821: EOF Channel Audio Framecount = %d\n", + dev->_audioframe_count); + return -1; + } + //ElSE, set the interrupt mask register, re-enable irq. + int_msk_tmp = cx_read(channel->int_msk); + cx_write(channel->int_msk, int_msk_tmp |= _intr_msk); + + return 0; +} + +static irqreturn_t cx25821_upstream_irq_audio(int irq, void *dev_id) +{ + struct cx25821_dev *dev = dev_id; + u32 msk_stat, audio_status; + int handled = 0; + struct sram_channel *sram_ch; + + if (!dev) + return -1; + + sram_ch = &dev->sram_channels[dev->_audio_upstream_channel_select]; + + msk_stat = cx_read(sram_ch->int_mstat); + audio_status = cx_read(sram_ch->int_stat); + + // Only deal with our interrupt + if (audio_status) { + handled = + cx25821_audio_upstream_irq(dev, + dev-> + _audio_upstream_channel_select, + audio_status); + } + + if (handled < 0) { + cx25821_stop_upstream_audio(dev); + } else { + handled += handled; + } + + return IRQ_RETVAL(handled); +} + +static void cx25821_wait_fifo_enable(struct cx25821_dev *dev, + struct sram_channel *sram_ch) +{ + int count = 0; + u32 tmp; + + do { + //Wait 10 microsecond before checking to see if the FIFO is turned ON. + udelay(10); + + tmp = cx_read(sram_ch->dma_ctl); + + if (count++ > 1000) //10 millisecond timeout + { + printk + ("cx25821 ERROR: %s() fifo is NOT turned on. Timeout!\n", + __func__); + return; + } + + } while (!(tmp & sram_ch->fld_aud_fifo_en)); + +} + +int cx25821_start_audio_dma_upstream(struct cx25821_dev *dev, + struct sram_channel *sram_ch) +{ + u32 tmp = 0; + int err = 0; + + // Set the physical start address of the RISC program in the initial program counter(IPC) member of the CMDS. + cx_write(sram_ch->cmds_start + 0, dev->_risc_phys_addr); + cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */ + + /* reset counter */ + cx_write(sram_ch->gpcnt_ctl, 3); + + //Set the line length (It looks like we do not need to set the line length) + cx_write(sram_ch->aud_length, AUDIO_LINE_SIZE & FLD_AUD_DST_LN_LNGTH); + + //Set the input mode to 16-bit + tmp = cx_read(sram_ch->aud_cfg); + tmp |= + FLD_AUD_SRC_ENABLE | FLD_AUD_DST_PK_MODE | FLD_AUD_CLK_ENABLE | + FLD_AUD_MASTER_MODE | FLD_AUD_CLK_SELECT_PLL_D | FLD_AUD_SONY_MODE; + cx_write(sram_ch->aud_cfg, tmp); + + // Read and write back the interrupt status register to clear it + tmp = cx_read(sram_ch->int_stat); + cx_write(sram_ch->int_stat, tmp); + + // Clear our bits from the interrupt status register. + cx_write(sram_ch->int_stat, _intr_msk); + + //Set the interrupt mask register, enable irq. + cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit)); + tmp = cx_read(sram_ch->int_msk); + cx_write(sram_ch->int_msk, tmp |= _intr_msk); + + err = + request_irq(dev->pci->irq, cx25821_upstream_irq_audio, + IRQF_SHARED | IRQF_DISABLED, dev->name, dev); + if (err < 0) { + printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name, + dev->pci->irq); + goto fail_irq; + } + + // Start the DMA engine + tmp = cx_read(sram_ch->dma_ctl); + cx_set(sram_ch->dma_ctl, tmp | sram_ch->fld_aud_risc_en); + + dev->_audio_is_running = 1; + dev->_is_first_audio_frame = 1; + + // The fifo_en bit turns on by the first Risc program + cx25821_wait_fifo_enable(dev, sram_ch); + + return 0; + + fail_irq: + cx25821_dev_unregister(dev); + return err; +} + +int cx25821_audio_upstream_init(struct cx25821_dev *dev, int channel_select) +{ + struct sram_channel *sram_ch; + int retval = 0; + int err = 0; + int str_length = 0; + + if (dev->_audio_is_running) { + printk("Audio Channel is still running so return!\n"); + return 0; + } + + dev->_audio_upstream_channel_select = channel_select; + sram_ch = &dev->sram_channels[channel_select]; + + //Work queue + INIT_WORK(&dev->_audio_work_entry, cx25821_audioups_handler); + dev->_irq_audio_queues = + create_singlethread_workqueue("cx25821_audioworkqueue"); + + if (!dev->_irq_audio_queues) { + printk + ("cx25821 ERROR: create_singlethread_workqueue() for Audio FAILED!\n"); + return -ENOMEM; + } + + dev->_last_index_irq = 0; + dev->_audio_is_running = 0; + dev->_audioframe_count = 0; + dev->_audiofile_status = RESET_STATUS; + dev->_audio_lines_count = LINES_PER_AUDIO_BUFFER; + _line_size = AUDIO_LINE_SIZE; + + if (dev->input_audiofilename) { + str_length = strlen(dev->input_audiofilename); + dev->_audiofilename = + (char *)kmalloc(str_length + 1, GFP_KERNEL); + + if (!dev->_audiofilename) + goto error; + + memcpy(dev->_audiofilename, dev->input_audiofilename, + str_length + 1); + + //Default if filename is empty string + if (strcmp(dev->input_audiofilename, "") == 0) { + dev->_audiofilename = "/root/audioGOOD.wav"; + } + } else { + str_length = strlen(_defaultAudioName); + dev->_audiofilename = + (char *)kmalloc(str_length + 1, GFP_KERNEL); + + if (!dev->_audiofilename) + goto error; + + memcpy(dev->_audiofilename, _defaultAudioName, str_length + 1); + } + + retval = + cx25821_sram_channel_setup_upstream_audio(dev, sram_ch, _line_size, + 0); + + dev->audio_upstream_riscbuf_size = + AUDIO_RISC_DMA_BUF_SIZE * NUM_AUDIO_PROGS + + RISC_SYNC_INSTRUCTION_SIZE; + dev->audio_upstream_databuf_size = AUDIO_DATA_BUF_SZ * NUM_AUDIO_PROGS; + + //Allocating buffers and prepare RISC program + retval = + cx25821_audio_upstream_buffer_prepare(dev, sram_ch, _line_size); + if (retval < 0) { + printk(KERN_ERR + "%s: Failed to set up Audio upstream buffers!\n", + dev->name); + goto error; + } + //Start RISC engine + cx25821_start_audio_dma_upstream(dev, sram_ch); + + return 0; + + error: + cx25821_dev_unregister(dev); + + return err; +} diff --git a/drivers/staging/cx25821/cx25821-audio-upstream.h b/drivers/staging/cx25821/cx25821-audio-upstream.h new file mode 100644 index 000000000000..ca987addf815 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-audio-upstream.h @@ -0,0 +1,57 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#define NUM_AUDIO_PROGS 8 +#define NUM_AUDIO_FRAMES 8 +#define END_OF_FILE 0 +#define IN_PROGRESS 1 +#define RESET_STATUS -1 +#define FIFO_DISABLE 0 +#define FIFO_ENABLE 1 +#define NUM_NO_OPS 4 + +#define RISC_READ_INSTRUCTION_SIZE 12 +#define RISC_JUMP_INSTRUCTION_SIZE 12 +#define RISC_WRITECR_INSTRUCTION_SIZE 16 +#define RISC_SYNC_INSTRUCTION_SIZE 4 +#define DWORD_SIZE 4 +#define AUDIO_SYNC_LINE 4 + +#define LINES_PER_AUDIO_BUFFER 15 +#define AUDIO_LINE_SIZE 128 +#define AUDIO_DATA_BUF_SZ (AUDIO_LINE_SIZE * LINES_PER_AUDIO_BUFFER) + +#define USE_RISC_NOOP_AUDIO 1 + +#ifdef USE_RISC_NOOP_AUDIO +#define AUDIO_RISC_DMA_BUF_SIZE ( LINES_PER_AUDIO_BUFFER*RISC_READ_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE + RISC_JUMP_INSTRUCTION_SIZE) +#endif + +#ifndef USE_RISC_NOOP_AUDIO +#define AUDIO_RISC_DMA_BUF_SIZE ( LINES_PER_AUDIO_BUFFER*RISC_READ_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + RISC_JUMP_INSTRUCTION_SIZE) +#endif + +static int _line_size; +char *_defaultAudioName = "/root/audioGOOD.wav"; diff --git a/drivers/staging/cx25821/cx25821-audio.h b/drivers/staging/cx25821/cx25821-audio.h new file mode 100644 index 000000000000..503f42f036a8 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-audio.h @@ -0,0 +1,57 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CX25821_AUDIO_H__ +#define __CX25821_AUDIO_H__ + +#define USE_RISC_NOOP 1 +#define LINES_PER_BUFFER 15 +#define AUDIO_LINE_SIZE 128 + +//Number of buffer programs to use at once. +#define NUMBER_OF_PROGRAMS 8 + +//Max size of the RISC program for a buffer. - worst case is 2 writes per line +// Space is also added for the 4 no-op instructions added on the end. + +#ifndef USE_RISC_NOOP +#define MAX_BUFFER_PROGRAM_SIZE \ + (2*LINES_PER_BUFFER*RISC_WRITE_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE*4) +#endif + +// MAE 12 July 2005 Try to use NOOP RISC instruction instead +#ifdef USE_RISC_NOOP +#define MAX_BUFFER_PROGRAM_SIZE \ + (2*LINES_PER_BUFFER*RISC_WRITE_INSTRUCTION_SIZE + RISC_NOOP_INSTRUCTION_SIZE*4) +#endif + +//Sizes of various instructions in bytes. Used when adding instructions. +#define RISC_WRITE_INSTRUCTION_SIZE 12 +#define RISC_JUMP_INSTRUCTION_SIZE 12 +#define RISC_SKIP_INSTRUCTION_SIZE 4 +#define RISC_SYNC_INSTRUCTION_SIZE 4 +#define RISC_WRITECR_INSTRUCTION_SIZE 16 +#define RISC_NOOP_INSTRUCTION_SIZE 4 + +#define MAX_AUDIO_DMA_BUFFER_SIZE (MAX_BUFFER_PROGRAM_SIZE * NUMBER_OF_PROGRAMS + RISC_SYNC_INSTRUCTION_SIZE) + +#endif diff --git a/drivers/staging/cx25821/cx25821-audups11.c b/drivers/staging/cx25821/cx25821-audups11.c new file mode 100644 index 000000000000..f78b8912d905 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-audups11.c @@ -0,0 +1,434 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821-video.h" + +static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct cx25821_buffer *buf = + container_of(vb, struct cx25821_buffer, vb); + struct cx25821_buffer *prev; + struct cx25821_fh *fh = vq->priv_data; + struct cx25821_dev *dev = fh->dev; + struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH11]; + + /* add jump to stopper */ + buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); + buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); + buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ + + dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); + + if (!list_empty(&q->queued)) { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, + buf->vb.i); + + } else if (list_empty(&q->active)) { + list_add_tail(&buf->vb.queue, &q->active); + cx25821_start_video_dma(dev, q, buf, + &dev->sram_channels[SRAM_CH11]); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT); + dprintk(2, + "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", + buf, buf->vb.i, buf->count, q->count); + } else { + prev = + list_entry(q->active.prev, struct cx25821_buffer, vb.queue); + if (prev->vb.width == buf->vb.width + && prev->vb.height == buf->vb.height + && prev->fmt == buf->fmt) { + list_add_tail(&buf->vb.queue, &q->active); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); + + /* 64 bit bits 63-32 */ + prev->risc.jmp[2] = cpu_to_le32(0); + dprintk(2, + "[%p/%d] buffer_queue - append to active, buf->count=%d\n", + buf, buf->vb.i, buf->count); + + } else { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, + buf->vb.i); + } + } + + if (list_empty(&q->active)) { + dprintk(2, "active queue empty!\n"); + } +} + +static struct videobuf_queue_ops cx25821_video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +static int video_open(struct file *file) +{ + int minor = video_devdata(file)->minor; + struct cx25821_dev *h, *dev = NULL; + struct cx25821_fh *fh; + struct list_head *list; + enum v4l2_buf_type type = 0; + + lock_kernel(); + list_for_each(list, &cx25821_devlist) { + h = list_entry(list, struct cx25821_dev, devlist); + + if (h->video_dev[SRAM_CH11] + && h->video_dev[SRAM_CH11]->minor == minor) { + dev = h; + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + } + } + + if (NULL == dev) { + unlock_kernel(); + return -ENODEV; + } + + printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); + + /* allocate + initialize per filehandle data */ + fh = kzalloc(sizeof(*fh), GFP_KERNEL); + if (NULL == fh) { + unlock_kernel(); + return -ENOMEM; + } + + file->private_data = fh; + fh->dev = dev; + fh->type = type; + fh->width = 720; + + if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) + fh->height = 576; + else + fh->height = 480; + + dev->channel_opened = 10; + fh->fmt = format_by_fourcc(V4L2_PIX_FMT_YUYV); + + v4l2_prio_open(&dev->prio, &fh->prio); + + videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, + &dev->pci->dev, &dev->slock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_INTERLACED, + sizeof(struct cx25821_buffer), fh); + + dprintk(1, "post videobuf_queue_init()\n"); + unlock_kernel(); + + return 0; +} + +static ssize_t video_read(struct file *file, char __user * data, size_t count, + loff_t * ppos) +{ + struct cx25821_fh *fh = file->private_data; + + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + if (res_locked(fh->dev, RESOURCE_VIDEO11)) + return -EBUSY; + + return videobuf_read_one(&fh->vidq, data, count, ppos, + file->f_flags & O_NONBLOCK); + + default: + BUG(); + return 0; + } +} + +static unsigned int video_poll(struct file *file, + struct poll_table_struct *wait) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_buffer *buf; + + if (res_check(fh, RESOURCE_VIDEO11)) { + /* streaming capture */ + if (list_empty(&fh->vidq.stream)) + return POLLERR; + buf = list_entry(fh->vidq.stream.next, + struct cx25821_buffer, vb.stream); + } else { + /* read() capture */ + buf = (struct cx25821_buffer *)fh->vidq.read_buf; + if (NULL == buf) + return POLLERR; + } + + poll_wait(file, &buf->vb.done, wait); + if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) + return POLLIN | POLLRDNORM; + return 0; +} + +static int video_release(struct file *file) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_dev *dev = fh->dev; + + //stop the risc engine and fifo + //cx_write(channel11->dma_ctl, 0); + + /* stop video capture */ + if (res_check(fh, RESOURCE_VIDEO11)) { + videobuf_queue_cancel(&fh->vidq); + res_free(dev, fh, RESOURCE_VIDEO11); + } + + if (fh->vidq.read_buf) { + buffer_release(&fh->vidq, fh->vidq.read_buf); + kfree(fh->vidq.read_buf); + } + + videobuf_mmap_free(&fh->vidq); + + v4l2_prio_close(&dev->prio, &fh->prio); + + file->private_data = NULL; + kfree(fh); + + return 0; +} + +static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + + if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) { + return -EINVAL; + } + + if (unlikely(i != fh->type)) { + return -EINVAL; + } + + if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO11)))) { + return -EBUSY; + } + + return videobuf_streamon(get_queue(fh)); +} + +static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + int err, res; + + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + if (i != fh->type) + return -EINVAL; + + res = get_resource(fh, RESOURCE_VIDEO11); + err = videobuf_streamoff(get_queue(fh)); + if (err < 0) + return err; + res_free(dev, fh, res); + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + dprintk(2, "%s()\n", __func__); + err = vidioc_try_fmt_vid_cap(file, priv, f); + + if (0 != err) + return err; + fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); + fh->width = f->fmt.pix.width; + fh->height = f->fmt.pix.height; + fh->vidq.field = f->fmt.pix.field; + dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, + fh->height, fh->vidq.field); + cx25821_call_all(dev, video, s_fmt, f); + return 0; +} + +static long video_ioctl_upstream11(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_dev *dev = fh->dev; + int command = 0; + struct upstream_user_struct *data_from_user; + + data_from_user = (struct upstream_user_struct *)arg; + + if (!data_from_user) { + printk + ("cx25821 in %s(): Upstream data is INVALID. Returning.\n", + __func__); + return 0; + } + + command = data_from_user->command; + + if (command != UPSTREAM_START_AUDIO && command != UPSTREAM_STOP_AUDIO) { + return 0; + } + + dev->input_filename = data_from_user->input_filename; + dev->input_audiofilename = data_from_user->input_filename; + dev->vid_stdname = data_from_user->vid_stdname; + dev->pixel_format = data_from_user->pixel_format; + dev->channel_select = data_from_user->channel_select; + dev->command = data_from_user->command; + + switch (command) { + case UPSTREAM_START_AUDIO: + cx25821_start_upstream_audio(dev, data_from_user); + break; + + case UPSTREAM_STOP_AUDIO: + cx25821_stop_upstream_audio(dev); + break; + } + + return 0; +} + +static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct cx25821_fh *fh = priv; + return videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); +} + +static int vidioc_log_status(struct file *file, void *priv) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + char name[32 + 2]; + + snprintf(name, sizeof(name), "%s/2", dev->name); + printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", + dev->name); + cx25821_call_all(dev, core, log_status); + printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", + dev->name); + return 0; +} + +static int vidioc_s_ctrl(struct file *file, void *priv, + struct v4l2_control *ctl) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + return 0; +} + +// exported stuff +static const struct v4l2_file_operations video_fops = { + .owner = THIS_MODULE, + .open = video_open, + .release = video_release, + .read = video_read, + .poll = video_poll, + .mmap = video_mmap, + .ioctl = video_ioctl_upstream11, +}; + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, +#ifdef TUNER_FLAG + .vidioc_s_std = vidioc_s_std, + .vidioc_querystd = vidioc_querystd, +#endif + .vidioc_cropcap = vidioc_cropcap, + .vidioc_s_crop = vidioc_s_crop, + .vidioc_g_crop = vidioc_g_crop, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_g_ctrl = vidioc_g_ctrl, + .vidioc_s_ctrl = vidioc_s_ctrl, + .vidioc_queryctrl = vidioc_queryctrl, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_log_status = vidioc_log_status, + .vidioc_g_priority = vidioc_g_priority, + .vidioc_s_priority = vidioc_s_priority, +#ifdef CONFIG_VIDEO_V4L1_COMPAT + .vidiocgmbuf = vidiocgmbuf, +#endif +#ifdef TUNER_FLAG + .vidioc_g_tuner = vidioc_g_tuner, + .vidioc_s_tuner = vidioc_s_tuner, + .vidioc_g_frequency = vidioc_g_frequency, + .vidioc_s_frequency = vidioc_s_frequency, +#endif +#ifdef CONFIG_VIDEO_ADV_DEBUG + .vidioc_g_register = vidioc_g_register, + .vidioc_s_register = vidioc_s_register, +#endif +}; + +struct video_device cx25821_video_template11 = { + .name = "cx25821-audioupstream", + .fops = &video_fops, + .minor = -1, + .ioctl_ops = &video_ioctl_ops, + .tvnorms = CX25821_NORMS, + .current_norm = V4L2_STD_NTSC_M, +}; diff --git a/drivers/staging/cx25821/cx25821-biffuncs.h b/drivers/staging/cx25821/cx25821-biffuncs.h new file mode 100644 index 000000000000..9326a7c729ec --- /dev/null +++ b/drivers/staging/cx25821/cx25821-biffuncs.h @@ -0,0 +1,45 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _BITFUNCS_H +#define _BITFUNCS_H + +#define SetBit(Bit) (1 << Bit) + +inline u8 getBit(u32 sample, u8 index) +{ + return (u8) ((sample >> index) & 1); +} + +inline u32 clearBitAtPos(u32 value, u8 bit) +{ + return value & ~(1 << bit); +} + +inline u32 setBitAtPos(u32 sample, u8 bit) +{ + sample |= (1 << bit); + return sample; + +} + +#endif diff --git a/drivers/staging/cx25821/cx25821-cards.c b/drivers/staging/cx25821/cx25821-cards.c new file mode 100644 index 000000000000..4d0b9eac3e49 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-cards.c @@ -0,0 +1,70 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include + +#include "cx25821.h" +#include "tuner-xc2028.h" + +// board config info + +struct cx25821_board cx25821_boards[] = { + [UNKNOWN_BOARD] = { + .name = "UNKNOWN/GENERIC", + // Ensure safe default for unknown boards + .clk_freq = 0, + }, + + [CX25821_BOARD] = { + .name = "CX25821", + .portb = CX25821_RAW, + .portc = CX25821_264, + .input[0].type = CX25821_VMUX_COMPOSITE, + }, + +}; + +const unsigned int cx25821_bcount = ARRAY_SIZE(cx25821_boards); + +struct cx25821_subid cx25821_subids[] = { + { + .subvendor = 0x14f1, + .subdevice = 0x0920, + .card = CX25821_BOARD, + }, +}; + +void cx25821_card_setup(struct cx25821_dev *dev) +{ + static u8 eeprom[256]; + + if (dev->i2c_bus[0].i2c_rc == 0) { + dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; + tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, + sizeof(eeprom)); + } +} diff --git a/drivers/staging/cx25821/cx25821-core.c b/drivers/staging/cx25821/cx25821-core.c new file mode 100644 index 000000000000..8aceae5a072e --- /dev/null +++ b/drivers/staging/cx25821/cx25821-core.c @@ -0,0 +1,1551 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include "cx25821.h" +#include "cx25821-sram.h" +#include "cx25821-video.h" + +MODULE_DESCRIPTION("Driver for Athena cards"); +MODULE_AUTHOR("Shu Lin - Hiep Huynh"); +MODULE_LICENSE("GPL"); + +struct list_head cx25821_devlist; + +static unsigned int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "enable debug messages"); + +static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET }; +module_param_array(card, int, NULL, 0444); +MODULE_PARM_DESC(card, "card type"); + +static unsigned int cx25821_devcount = 0; + +static DEFINE_MUTEX(devlist); +LIST_HEAD(cx25821_devlist); + +struct sram_channel cx25821_sram_channels[] = { + [SRAM_CH00] = { + .i = SRAM_CH00, + .name = "VID A", + .cmds_start = VID_A_DOWN_CMDS, + .ctrl_start = VID_A_IQ, + .cdt = VID_A_CDT, + .fifo_start = VID_A_DOWN_CLUSTER_1, + .fifo_size = (VID_CLUSTER_SIZE << 2), + .ptr1_reg = DMA1_PTR1, + .ptr2_reg = DMA1_PTR2, + .cnt1_reg = DMA1_CNT1, + .cnt2_reg = DMA1_CNT2, + .int_msk = VID_A_INT_MSK, + .int_stat = VID_A_INT_STAT, + .int_mstat = VID_A_INT_MSTAT, + .dma_ctl = VID_DST_A_DMA_CTL, + .gpcnt_ctl = VID_DST_A_GPCNT_CTL, + .gpcnt = VID_DST_A_GPCNT, + .vip_ctl = VID_DST_A_VIP_CTL, + .pix_frmt = VID_DST_A_PIX_FRMT, + }, + + [SRAM_CH01] = { + .i = SRAM_CH01, + .name = "VID B", + .cmds_start = VID_B_DOWN_CMDS, + .ctrl_start = VID_B_IQ, + .cdt = VID_B_CDT, + .fifo_start = VID_B_DOWN_CLUSTER_1, + .fifo_size = (VID_CLUSTER_SIZE << 2), + .ptr1_reg = DMA2_PTR1, + .ptr2_reg = DMA2_PTR2, + .cnt1_reg = DMA2_CNT1, + .cnt2_reg = DMA2_CNT2, + .int_msk = VID_B_INT_MSK, + .int_stat = VID_B_INT_STAT, + .int_mstat = VID_B_INT_MSTAT, + .dma_ctl = VID_DST_B_DMA_CTL, + .gpcnt_ctl = VID_DST_B_GPCNT_CTL, + .gpcnt = VID_DST_B_GPCNT, + .vip_ctl = VID_DST_B_VIP_CTL, + .pix_frmt = VID_DST_B_PIX_FRMT, + }, + + [SRAM_CH02] = { + .i = SRAM_CH02, + .name = "VID C", + .cmds_start = VID_C_DOWN_CMDS, + .ctrl_start = VID_C_IQ, + .cdt = VID_C_CDT, + .fifo_start = VID_C_DOWN_CLUSTER_1, + .fifo_size = (VID_CLUSTER_SIZE << 2), + .ptr1_reg = DMA3_PTR1, + .ptr2_reg = DMA3_PTR2, + .cnt1_reg = DMA3_CNT1, + .cnt2_reg = DMA3_CNT2, + .int_msk = VID_C_INT_MSK, + .int_stat = VID_C_INT_STAT, + .int_mstat = VID_C_INT_MSTAT, + .dma_ctl = VID_DST_C_DMA_CTL, + .gpcnt_ctl = VID_DST_C_GPCNT_CTL, + .gpcnt = VID_DST_C_GPCNT, + .vip_ctl = VID_DST_C_VIP_CTL, + .pix_frmt = VID_DST_C_PIX_FRMT, + }, + + [SRAM_CH03] = { + .i = SRAM_CH03, + .name = "VID D", + .cmds_start = VID_D_DOWN_CMDS, + .ctrl_start = VID_D_IQ, + .cdt = VID_D_CDT, + .fifo_start = VID_D_DOWN_CLUSTER_1, + .fifo_size = (VID_CLUSTER_SIZE << 2), + .ptr1_reg = DMA4_PTR1, + .ptr2_reg = DMA4_PTR2, + .cnt1_reg = DMA4_CNT1, + .cnt2_reg = DMA4_CNT2, + .int_msk = VID_D_INT_MSK, + .int_stat = VID_D_INT_STAT, + .int_mstat = VID_D_INT_MSTAT, + .dma_ctl = VID_DST_D_DMA_CTL, + .gpcnt_ctl = VID_DST_D_GPCNT_CTL, + .gpcnt = VID_DST_D_GPCNT, + .vip_ctl = VID_DST_D_VIP_CTL, + .pix_frmt = VID_DST_D_PIX_FRMT, + }, + + [SRAM_CH04] = { + .i = SRAM_CH04, + .name = "VID E", + .cmds_start = VID_E_DOWN_CMDS, + .ctrl_start = VID_E_IQ, + .cdt = VID_E_CDT, + .fifo_start = VID_E_DOWN_CLUSTER_1, + .fifo_size = (VID_CLUSTER_SIZE << 2), + .ptr1_reg = DMA5_PTR1, + .ptr2_reg = DMA5_PTR2, + .cnt1_reg = DMA5_CNT1, + .cnt2_reg = DMA5_CNT2, + .int_msk = VID_E_INT_MSK, + .int_stat = VID_E_INT_STAT, + .int_mstat = VID_E_INT_MSTAT, + .dma_ctl = VID_DST_E_DMA_CTL, + .gpcnt_ctl = VID_DST_E_GPCNT_CTL, + .gpcnt = VID_DST_E_GPCNT, + .vip_ctl = VID_DST_E_VIP_CTL, + .pix_frmt = VID_DST_E_PIX_FRMT, + }, + + [SRAM_CH05] = { + .i = SRAM_CH05, + .name = "VID F", + .cmds_start = VID_F_DOWN_CMDS, + .ctrl_start = VID_F_IQ, + .cdt = VID_F_CDT, + .fifo_start = VID_F_DOWN_CLUSTER_1, + .fifo_size = (VID_CLUSTER_SIZE << 2), + .ptr1_reg = DMA6_PTR1, + .ptr2_reg = DMA6_PTR2, + .cnt1_reg = DMA6_CNT1, + .cnt2_reg = DMA6_CNT2, + .int_msk = VID_F_INT_MSK, + .int_stat = VID_F_INT_STAT, + .int_mstat = VID_F_INT_MSTAT, + .dma_ctl = VID_DST_F_DMA_CTL, + .gpcnt_ctl = VID_DST_F_GPCNT_CTL, + .gpcnt = VID_DST_F_GPCNT, + .vip_ctl = VID_DST_F_VIP_CTL, + .pix_frmt = VID_DST_F_PIX_FRMT, + }, + + [SRAM_CH06] = { + .i = SRAM_CH06, + .name = "VID G", + .cmds_start = VID_G_DOWN_CMDS, + .ctrl_start = VID_G_IQ, + .cdt = VID_G_CDT, + .fifo_start = VID_G_DOWN_CLUSTER_1, + .fifo_size = (VID_CLUSTER_SIZE << 2), + .ptr1_reg = DMA7_PTR1, + .ptr2_reg = DMA7_PTR2, + .cnt1_reg = DMA7_CNT1, + .cnt2_reg = DMA7_CNT2, + .int_msk = VID_G_INT_MSK, + .int_stat = VID_G_INT_STAT, + .int_mstat = VID_G_INT_MSTAT, + .dma_ctl = VID_DST_G_DMA_CTL, + .gpcnt_ctl = VID_DST_G_GPCNT_CTL, + .gpcnt = VID_DST_G_GPCNT, + .vip_ctl = VID_DST_G_VIP_CTL, + .pix_frmt = VID_DST_G_PIX_FRMT, + }, + + [SRAM_CH07] = { + .i = SRAM_CH07, + .name = "VID H", + .cmds_start = VID_H_DOWN_CMDS, + .ctrl_start = VID_H_IQ, + .cdt = VID_H_CDT, + .fifo_start = VID_H_DOWN_CLUSTER_1, + .fifo_size = (VID_CLUSTER_SIZE << 2), + .ptr1_reg = DMA8_PTR1, + .ptr2_reg = DMA8_PTR2, + .cnt1_reg = DMA8_CNT1, + .cnt2_reg = DMA8_CNT2, + .int_msk = VID_H_INT_MSK, + .int_stat = VID_H_INT_STAT, + .int_mstat = VID_H_INT_MSTAT, + .dma_ctl = VID_DST_H_DMA_CTL, + .gpcnt_ctl = VID_DST_H_GPCNT_CTL, + .gpcnt = VID_DST_H_GPCNT, + .vip_ctl = VID_DST_H_VIP_CTL, + .pix_frmt = VID_DST_H_PIX_FRMT, + }, + + [SRAM_CH08] = { + .name = "audio from", + .cmds_start = AUD_A_DOWN_CMDS, + .ctrl_start = AUD_A_IQ, + .cdt = AUD_A_CDT, + .fifo_start = AUD_A_DOWN_CLUSTER_1, + .fifo_size = AUDIO_CLUSTER_SIZE * 3, + .ptr1_reg = DMA17_PTR1, + .ptr2_reg = DMA17_PTR2, + .cnt1_reg = DMA17_CNT1, + .cnt2_reg = DMA17_CNT2, + }, + + [SRAM_CH09] = { + .i = SRAM_CH09, + .name = "VID Upstream I", + .cmds_start = VID_I_UP_CMDS, + .ctrl_start = VID_I_IQ, + .cdt = VID_I_CDT, + .fifo_start = VID_I_UP_CLUSTER_1, + .fifo_size = (VID_CLUSTER_SIZE << 2), + .ptr1_reg = DMA15_PTR1, + .ptr2_reg = DMA15_PTR2, + .cnt1_reg = DMA15_CNT1, + .cnt2_reg = DMA15_CNT2, + .int_msk = VID_I_INT_MSK, + .int_stat = VID_I_INT_STAT, + .int_mstat = VID_I_INT_MSTAT, + .dma_ctl = VID_SRC_I_DMA_CTL, + .gpcnt_ctl = VID_SRC_I_GPCNT_CTL, + .gpcnt = VID_SRC_I_GPCNT, + + .vid_fmt_ctl = VID_SRC_I_FMT_CTL, + .vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1, + .vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2, + .vid_cdt_size = VID_SRC_I_CDT_SZ, + .irq_bit = 8, + }, + + [SRAM_CH10] = { + .i = SRAM_CH10, + .name = "VID Upstream J", + .cmds_start = VID_J_UP_CMDS, + .ctrl_start = VID_J_IQ, + .cdt = VID_J_CDT, + .fifo_start = VID_J_UP_CLUSTER_1, + .fifo_size = (VID_CLUSTER_SIZE << 2), + .ptr1_reg = DMA16_PTR1, + .ptr2_reg = DMA16_PTR2, + .cnt1_reg = DMA16_CNT1, + .cnt2_reg = DMA16_CNT2, + .int_msk = VID_J_INT_MSK, + .int_stat = VID_J_INT_STAT, + .int_mstat = VID_J_INT_MSTAT, + .dma_ctl = VID_SRC_J_DMA_CTL, + .gpcnt_ctl = VID_SRC_J_GPCNT_CTL, + .gpcnt = VID_SRC_J_GPCNT, + + .vid_fmt_ctl = VID_SRC_J_FMT_CTL, + .vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1, + .vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2, + .vid_cdt_size = VID_SRC_J_CDT_SZ, + .irq_bit = 9, + }, + + [SRAM_CH11] = { + .i = SRAM_CH11, + .name = "Audio Upstream Channel B", + .cmds_start = AUD_B_UP_CMDS, + .ctrl_start = AUD_B_IQ, + .cdt = AUD_B_CDT, + .fifo_start = AUD_B_UP_CLUSTER_1, + .fifo_size = (AUDIO_CLUSTER_SIZE * 3), + .ptr1_reg = DMA22_PTR1, + .ptr2_reg = DMA22_PTR2, + .cnt1_reg = DMA22_CNT1, + .cnt2_reg = DMA22_CNT2, + .int_msk = AUD_B_INT_MSK, + .int_stat = AUD_B_INT_STAT, + .int_mstat = AUD_B_INT_MSTAT, + .dma_ctl = AUD_INT_DMA_CTL, + .gpcnt_ctl = AUD_B_GPCNT_CTL, + .gpcnt = AUD_B_GPCNT, + .aud_length = AUD_B_LNGTH, + .aud_cfg = AUD_B_CFG, + .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN, + .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN, + .irq_bit = 11, + }, +}; + +struct sram_channel *channel0 = &cx25821_sram_channels[SRAM_CH00]; +struct sram_channel *channel1 = &cx25821_sram_channels[SRAM_CH01]; +struct sram_channel *channel2 = &cx25821_sram_channels[SRAM_CH02]; +struct sram_channel *channel3 = &cx25821_sram_channels[SRAM_CH03]; +struct sram_channel *channel4 = &cx25821_sram_channels[SRAM_CH04]; +struct sram_channel *channel5 = &cx25821_sram_channels[SRAM_CH05]; +struct sram_channel *channel6 = &cx25821_sram_channels[SRAM_CH06]; +struct sram_channel *channel7 = &cx25821_sram_channels[SRAM_CH07]; +struct sram_channel *channel9 = &cx25821_sram_channels[SRAM_CH09]; +struct sram_channel *channel10 = &cx25821_sram_channels[SRAM_CH10]; +struct sram_channel *channel11 = &cx25821_sram_channels[SRAM_CH11]; + +struct cx25821_dmaqueue mpegq; + +static int cx25821_risc_decode(u32 risc) +{ + static char *instr[16] = { + [RISC_SYNC >> 28] = "sync", + [RISC_WRITE >> 28] = "write", + [RISC_WRITEC >> 28] = "writec", + [RISC_READ >> 28] = "read", + [RISC_READC >> 28] = "readc", + [RISC_JUMP >> 28] = "jump", + [RISC_SKIP >> 28] = "skip", + [RISC_WRITERM >> 28] = "writerm", + [RISC_WRITECM >> 28] = "writecm", + [RISC_WRITECR >> 28] = "writecr", + }; + static int incr[16] = { + [RISC_WRITE >> 28] = 3, + [RISC_JUMP >> 28] = 3, + [RISC_SKIP >> 28] = 1, + [RISC_SYNC >> 28] = 1, + [RISC_WRITERM >> 28] = 3, + [RISC_WRITECM >> 28] = 3, + [RISC_WRITECR >> 28] = 4, + }; + static char *bits[] = { + "12", "13", "14", "resync", + "cnt0", "cnt1", "18", "19", + "20", "21", "22", "23", + "irq1", "irq2", "eol", "sol", + }; + int i; + + printk("0x%08x [ %s", risc, + instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); + for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) { + if (risc & (1 << (i + 12))) + printk(" %s", bits[i]); + } + printk(" count=%d ]\n", risc & 0xfff); + return incr[risc >> 28] ? incr[risc >> 28] : 1; +} + +static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap) +{ + struct cx25821_i2c *bus = i2c_adap->algo_data; + struct cx25821_dev *dev = bus->dev; + return cx_read(bus->reg_stat) & 0x01; +} + +void cx_i2c_read_print(struct cx25821_dev *dev, u32 reg, const char *reg_string) +{ + int tmp = 0; + u32 value = 0; + + value = cx25821_i2c_read(&dev->i2c_bus[0], reg, &tmp); +} + +static void cx25821_registers_init(struct cx25821_dev *dev) +{ + u32 tmp; + + // enable RUN_RISC in Pecos + cx_write(DEV_CNTRL2, 0x20); + + // Set the master PCI interrupt masks to enable video, audio, MBIF, and GPIO interrupts + // I2C interrupt masking is handled by the I2C objects themselves. + cx_write(PCI_INT_MSK, 0x2001FFFF); + + tmp = cx_read(RDR_TLCTL0); + tmp &= ~FLD_CFG_RCB_CK_EN; // Clear the RCB_CK_EN bit + cx_write(RDR_TLCTL0, tmp); + + // PLL-A setting for the Audio Master Clock + cx_write(PLL_A_INT_FRAC, 0x9807A58B); + + // PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 + cx_write(PLL_A_POST_STAT_BIST, 0x8000019C); + + // clear reset bit [31] + tmp = cx_read(PLL_A_INT_FRAC); + cx_write(PLL_A_INT_FRAC, tmp & 0x7FFFFFFF); + + // PLL-B setting for Mobilygen Host Bus Interface + cx_write(PLL_B_INT_FRAC, 0x9883A86F); + + // PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0 + cx_write(PLL_B_POST_STAT_BIST, 0x8000018D); + + // clear reset bit [31] + tmp = cx_read(PLL_B_INT_FRAC); + cx_write(PLL_B_INT_FRAC, tmp & 0x7FFFFFFF); + + // PLL-C setting for video upstream channel + cx_write(PLL_C_INT_FRAC, 0x96A0EA3F); + + // PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0 + cx_write(PLL_C_POST_STAT_BIST, 0x80000103); + + // clear reset bit [31] + tmp = cx_read(PLL_C_INT_FRAC); + cx_write(PLL_C_INT_FRAC, tmp & 0x7FFFFFFF); + + // PLL-D setting for audio upstream channel + cx_write(PLL_D_INT_FRAC, 0x98757F5B); + + // PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0 + cx_write(PLL_D_POST_STAT_BIST, 0x80000113); + + // clear reset bit [31] + tmp = cx_read(PLL_D_INT_FRAC); + cx_write(PLL_D_INT_FRAC, tmp & 0x7FFFFFFF); + + // This selects the PLL C clock source for the video upstream channel I and J + tmp = cx_read(VID_CH_CLK_SEL); + cx_write(VID_CH_CLK_SEL, (tmp & 0x00FFFFFF) | 0x24000000); + + // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C + //select 656/VIP DST for downstream Channel A - C + tmp = cx_read(VID_CH_MODE_SEL); + //cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); + cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00); + + // enables 656 port I and J as output + tmp = cx_read(CLK_RST); + tmp |= FLD_USE_ALT_PLL_REF; // use external ALT_PLL_REF pin as its reference clock instead + cx_write(CLK_RST, tmp & ~(FLD_VID_I_CLK_NOE | FLD_VID_J_CLK_NOE)); + + mdelay(100); +} + +int cx25821_sram_channel_setup(struct cx25821_dev *dev, + struct sram_channel *ch, + unsigned int bpl, u32 risc) +{ + unsigned int i, lines; + u32 cdt; + + if (ch->cmds_start == 0) { + cx_write(ch->ptr1_reg, 0); + cx_write(ch->ptr2_reg, 0); + cx_write(ch->cnt2_reg, 0); + cx_write(ch->cnt1_reg, 0); + return 0; + } + + bpl = (bpl + 7) & ~7; /* alignment */ + cdt = ch->cdt; + lines = ch->fifo_size / bpl; + + if (lines > 4) { + lines = 4; + } + + BUG_ON(lines < 2); + + cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); + cx_write(8 + 4, 8); + cx_write(8 + 8, 0); + + /* write CDT */ + for (i = 0; i < lines; i++) { + cx_write(cdt + 16 * i, ch->fifo_start + bpl * i); + cx_write(cdt + 16 * i + 4, 0); + cx_write(cdt + 16 * i + 8, 0); + cx_write(cdt + 16 * i + 12, 0); + } + + //init the first cdt buffer + for (i = 0; i < 128; i++) + cx_write(ch->fifo_start + 4 * i, i); + + /* write CMDS */ + if (ch->jumponly) { + cx_write(ch->cmds_start + 0, 8); + } else { + cx_write(ch->cmds_start + 0, risc); + } + + cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */ + cx_write(ch->cmds_start + 8, cdt); + cx_write(ch->cmds_start + 12, (lines * 16) >> 3); + cx_write(ch->cmds_start + 16, ch->ctrl_start); + + if (ch->jumponly) + cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2)); + else + cx_write(ch->cmds_start + 20, 64 >> 2); + + for (i = 24; i < 80; i += 4) + cx_write(ch->cmds_start + i, 0); + + /* fill registers */ + cx_write(ch->ptr1_reg, ch->fifo_start); + cx_write(ch->ptr2_reg, cdt); + cx_write(ch->cnt2_reg, (lines * 16) >> 3); + cx_write(ch->cnt1_reg, (bpl >> 3) - 1); + + return 0; +} + +int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev, + struct sram_channel *ch, + unsigned int bpl, u32 risc) +{ + unsigned int i, lines; + u32 cdt; + + if (ch->cmds_start == 0) { + cx_write(ch->ptr1_reg, 0); + cx_write(ch->ptr2_reg, 0); + cx_write(ch->cnt2_reg, 0); + cx_write(ch->cnt1_reg, 0); + return 0; + } + + bpl = (bpl + 7) & ~7; /* alignment */ + cdt = ch->cdt; + lines = ch->fifo_size / bpl; + + if (lines > 3) { + lines = 3; //for AUDIO + } + + BUG_ON(lines < 2); + + cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); + cx_write(8 + 4, 8); + cx_write(8 + 8, 0); + + /* write CDT */ + for (i = 0; i < lines; i++) { + cx_write(cdt + 16 * i, ch->fifo_start + bpl * i); + cx_write(cdt + 16 * i + 4, 0); + cx_write(cdt + 16 * i + 8, 0); + cx_write(cdt + 16 * i + 12, 0); + } + + /* write CMDS */ + if (ch->jumponly) { + cx_write(ch->cmds_start + 0, 8); + } else { + cx_write(ch->cmds_start + 0, risc); + } + + cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */ + cx_write(ch->cmds_start + 8, cdt); + cx_write(ch->cmds_start + 12, (lines * 16) >> 3); + cx_write(ch->cmds_start + 16, ch->ctrl_start); + + //IQ size + if (ch->jumponly) { + cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2)); + } else { + cx_write(ch->cmds_start + 20, 64 >> 2); + } + + //zero out + for (i = 24; i < 80; i += 4) + cx_write(ch->cmds_start + i, 0); + + /* fill registers */ + cx_write(ch->ptr1_reg, ch->fifo_start); + cx_write(ch->ptr2_reg, cdt); + cx_write(ch->cnt2_reg, (lines * 16) >> 3); + cx_write(ch->cnt1_reg, (bpl >> 3) - 1); + + return 0; +} + +void cx25821_sram_channel_dump(struct cx25821_dev *dev, struct sram_channel *ch) +{ + static char *name[] = { + "init risc lo", + "init risc hi", + "cdt base", + "cdt size", + "iq base", + "iq size", + "risc pc lo", + "risc pc hi", + "iq wr ptr", + "iq rd ptr", + "cdt current", + "pci target lo", + "pci target hi", + "line / byte", + }; + u32 risc; + unsigned int i, j, n; + + printk(KERN_WARNING "%s: %s - dma channel status dump\n", dev->name, + ch->name); + for (i = 0; i < ARRAY_SIZE(name); i++) + printk(KERN_WARNING "cmds + 0x%2x: %-15s: 0x%08x\n", i * 4, + name[i], cx_read(ch->cmds_start + 4 * i)); + + j = i * 4; + for (i = 0; i < 4;) { + risc = cx_read(ch->cmds_start + 4 * (i + 14)); + printk(KERN_WARNING "cmds + 0x%2x: risc%d: ", j + i * 4, i); + i += cx25821_risc_decode(risc); + } + + for (i = 0; i < (64 >> 2); i += n) { + risc = cx_read(ch->ctrl_start + 4 * i); + /* No consideration for bits 63-32 */ + + printk(KERN_WARNING "ctrl + 0x%2x (0x%08x): iq %x: ", i * 4, + ch->ctrl_start + 4 * i, i); + n = cx25821_risc_decode(risc); + for (j = 1; j < n; j++) { + risc = cx_read(ch->ctrl_start + 4 * (i + j)); + printk(KERN_WARNING + "ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n", + 4 * (i + j), i + j, risc, j); + } + } + + printk(KERN_WARNING " : fifo: 0x%08x -> 0x%x\n", + ch->fifo_start, ch->fifo_start + ch->fifo_size); + printk(KERN_WARNING " : ctrl: 0x%08x -> 0x%x\n", + ch->ctrl_start, ch->ctrl_start + 6 * 16); + printk(KERN_WARNING " : ptr1_reg: 0x%08x\n", + cx_read(ch->ptr1_reg)); + printk(KERN_WARNING " : ptr2_reg: 0x%08x\n", + cx_read(ch->ptr2_reg)); + printk(KERN_WARNING " : cnt1_reg: 0x%08x\n", + cx_read(ch->cnt1_reg)); + printk(KERN_WARNING " : cnt2_reg: 0x%08x\n", + cx_read(ch->cnt2_reg)); +} + +void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev, + struct sram_channel *ch) +{ + static char *name[] = { + "init risc lo", + "init risc hi", + "cdt base", + "cdt size", + "iq base", + "iq size", + "risc pc lo", + "risc pc hi", + "iq wr ptr", + "iq rd ptr", + "cdt current", + "pci target lo", + "pci target hi", + "line / byte", + }; + + u32 risc, value, tmp; + unsigned int i, j, n; + + printk(KERN_INFO "\n%s: %s - dma Audio channel status dump\n", + dev->name, ch->name); + + for (i = 0; i < ARRAY_SIZE(name); i++) + printk(KERN_INFO "%s: cmds + 0x%2x: %-15s: 0x%08x\n", + dev->name, i * 4, name[i], + cx_read(ch->cmds_start + 4 * i)); + + j = i * 4; + for (i = 0; i < 4;) { + risc = cx_read(ch->cmds_start + 4 * (i + 14)); + printk(KERN_WARNING "cmds + 0x%2x: risc%d: ", j + i * 4, i); + i += cx25821_risc_decode(risc); + } + + for (i = 0; i < (64 >> 2); i += n) { + risc = cx_read(ch->ctrl_start + 4 * i); + /* No consideration for bits 63-32 */ + + printk(KERN_WARNING "ctrl + 0x%2x (0x%08x): iq %x: ", i * 4, + ch->ctrl_start + 4 * i, i); + n = cx25821_risc_decode(risc); + + for (j = 1; j < n; j++) { + risc = cx_read(ch->ctrl_start + 4 * (i + j)); + printk(KERN_WARNING + "ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n", + 4 * (i + j), i + j, risc, j); + } + } + + printk(KERN_WARNING " : fifo: 0x%08x -> 0x%x\n", + ch->fifo_start, ch->fifo_start + ch->fifo_size); + printk(KERN_WARNING " : ctrl: 0x%08x -> 0x%x\n", + ch->ctrl_start, ch->ctrl_start + 6 * 16); + printk(KERN_WARNING " : ptr1_reg: 0x%08x\n", + cx_read(ch->ptr1_reg)); + printk(KERN_WARNING " : ptr2_reg: 0x%08x\n", + cx_read(ch->ptr2_reg)); + printk(KERN_WARNING " : cnt1_reg: 0x%08x\n", + cx_read(ch->cnt1_reg)); + printk(KERN_WARNING " : cnt2_reg: 0x%08x\n", + cx_read(ch->cnt2_reg)); + + for (i = 0; i < 4; i++) { + risc = cx_read(ch->cmds_start + 56 + (i * 4)); + printk(KERN_WARNING "instruction %d = 0x%x\n", i, risc); + } + + //read data from the first cdt buffer + risc = cx_read(AUD_A_CDT); + printk(KERN_WARNING "\nread cdt loc=0x%x\n", risc); + for (i = 0; i < 8; i++) { + n = cx_read(risc + i * 4); + printk(KERN_WARNING "0x%x ", n); + } + printk(KERN_WARNING "\n\n"); + + value = cx_read(CLK_RST); + CX25821_INFO(" CLK_RST = 0x%x \n\n", value); + + value = cx_read(PLL_A_POST_STAT_BIST); + CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x \n\n", value); + value = cx_read(PLL_A_INT_FRAC); + CX25821_INFO(" PLL_A_INT_FRAC = 0x%x \n\n", value); + + value = cx_read(PLL_B_POST_STAT_BIST); + CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x \n\n", value); + value = cx_read(PLL_B_INT_FRAC); + CX25821_INFO(" PLL_B_INT_FRAC = 0x%x \n\n", value); + + value = cx_read(PLL_C_POST_STAT_BIST); + CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x \n\n", value); + value = cx_read(PLL_C_INT_FRAC); + CX25821_INFO(" PLL_C_INT_FRAC = 0x%x \n\n", value); + + value = cx_read(PLL_D_POST_STAT_BIST); + CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x \n\n", value); + value = cx_read(PLL_D_INT_FRAC); + CX25821_INFO(" PLL_D_INT_FRAC = 0x%x \n\n", value); + + value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp); + CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x \n\n", value); +} + +static void cx25821_shutdown(struct cx25821_dev *dev) +{ + int i; + + /* disable RISC controller */ + cx_write(DEV_CNTRL2, 0); + + /* Disable Video A/B activity */ + for (i = 0; i < VID_CHANNEL_NUM; i++) { + cx_write(dev->sram_channels[i].dma_ctl, 0); + cx_write(dev->sram_channels[i].int_msk, 0); + } + + for (i = VID_UPSTREAM_SRAM_CHANNEL_I; i <= VID_UPSTREAM_SRAM_CHANNEL_J; + i++) { + cx_write(dev->sram_channels[i].dma_ctl, 0); + cx_write(dev->sram_channels[i].int_msk, 0); + } + + /* Disable Audio activity */ + cx_write(AUD_INT_DMA_CTL, 0); + + /* Disable Serial port */ + cx_write(UART_CTL, 0); + + /* Disable Interrupts */ + cx_write(PCI_INT_MSK, 0); + cx_write(AUD_A_INT_MSK, 0); +} + +void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel_select, + u32 format) +{ + struct sram_channel *ch; + + if (channel_select <= 7 && channel_select >= 0) { + ch = &cx25821_sram_channels[channel_select]; + cx_write(ch->pix_frmt, format); + dev->pixel_formats[channel_select] = format; + } +} + +static void cx25821_set_vip_mode(struct cx25821_dev *dev, + struct sram_channel *ch) +{ + cx_write(ch->pix_frmt, PIXEL_FRMT_422); + cx_write(ch->vip_ctl, PIXEL_ENGINE_VIP1); +} + +static void cx25821_initialize(struct cx25821_dev *dev) +{ + int i; + + dprintk(1, "%s()\n", __func__); + + cx25821_shutdown(dev); + cx_write(PCI_INT_STAT, 0xffffffff); + + for (i = 0; i < VID_CHANNEL_NUM; i++) + cx_write(dev->sram_channels[i].int_stat, 0xffffffff); + + cx_write(AUD_A_INT_STAT, 0xffffffff); + cx_write(AUD_B_INT_STAT, 0xffffffff); + cx_write(AUD_C_INT_STAT, 0xffffffff); + cx_write(AUD_D_INT_STAT, 0xffffffff); + cx_write(AUD_E_INT_STAT, 0xffffffff); + + cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000); + cx_write(PAD_CTRL, 0x12); //for I2C + cx25821_registers_init(dev); //init Pecos registers + mdelay(100); + + for (i = 0; i < VID_CHANNEL_NUM; i++) { + cx25821_set_vip_mode(dev, &dev->sram_channels[i]); + cx25821_sram_channel_setup(dev, &dev->sram_channels[i], 1440, + 0); + dev->pixel_formats[i] = PIXEL_FRMT_422; + dev->use_cif_resolution[i] = FALSE; + } + + //Probably only affect Downstream + for (i = VID_UPSTREAM_SRAM_CHANNEL_I; i <= VID_UPSTREAM_SRAM_CHANNEL_J; + i++) { + cx25821_set_vip_mode(dev, &dev->sram_channels[i]); + } + + cx25821_sram_channel_setup_audio(dev, &dev->sram_channels[SRAM_CH08], + 128, 0); + + cx25821_gpio_init(dev); +} + +static int get_resources(struct cx25821_dev *dev) +{ + if (request_mem_region + (pci_resource_start(dev->pci, 0), pci_resource_len(dev->pci, 0), + dev->name)) + return 0; + + printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n", + dev->name, (unsigned long long)pci_resource_start(dev->pci, 0)); + + return -EBUSY; +} + +static void cx25821_dev_checkrevision(struct cx25821_dev *dev) +{ + dev->hwrevision = cx_read(RDR_CFG2) & 0xff; + + printk(KERN_INFO "%s() Hardware revision = 0x%02x\n", __func__, + dev->hwrevision); +} + +static void cx25821_iounmap(struct cx25821_dev *dev) +{ + if (dev == NULL) + return; + + /* Releasing IO memory */ + if (dev->lmmio != NULL) { + CX25821_INFO("Releasing lmmio.\n"); + iounmap(dev->lmmio); + dev->lmmio = NULL; + } +} + +static int cx25821_dev_setup(struct cx25821_dev *dev) +{ + int io_size = 0, i; + + struct video_device *video_template[] = { + &cx25821_video_template0, + &cx25821_video_template1, + &cx25821_video_template2, + &cx25821_video_template3, + &cx25821_video_template4, + &cx25821_video_template5, + &cx25821_video_template6, + &cx25821_video_template7, + &cx25821_video_template9, + &cx25821_video_template10, + &cx25821_video_template11, + &cx25821_videoioctl_template, + }; + + printk(KERN_INFO "\n***********************************\n"); + printk(KERN_INFO "cx25821 set up\n"); + printk(KERN_INFO "***********************************\n\n"); + + mutex_init(&dev->lock); + + atomic_inc(&dev->refcount); + + dev->nr = ++cx25821_devcount; + sprintf(dev->name, "cx25821[%d]", dev->nr); + + mutex_lock(&devlist); + list_add_tail(&dev->devlist, &cx25821_devlist); + mutex_unlock(&devlist); + + strcpy(cx25821_boards[UNKNOWN_BOARD].name, "unknown"); + strcpy(cx25821_boards[CX25821_BOARD].name, "cx25821"); + + if (dev->pci->device != 0x8210) { + printk(KERN_INFO + "%s() Exiting. Incorrect Hardware device = 0x%02x\n", + __func__, dev->pci->device); + return -1; + } else { + printk(KERN_INFO "Athena Hardware device = 0x%02x\n", + dev->pci->device); + } + + /* Apply a sensible clock frequency for the PCIe bridge */ + dev->clk_freq = 28000000; + dev->sram_channels = cx25821_sram_channels; + + if (dev->nr > 1) { + CX25821_INFO("dev->nr > 1!"); + } + + /* board config */ + dev->board = 1; //card[dev->nr]; + dev->_max_num_decoders = MAX_DECODERS; + + dev->pci_bus = dev->pci->bus->number; + dev->pci_slot = PCI_SLOT(dev->pci->devfn); + dev->pci_irqmask = 0x001f00; + + /* External Master 1 Bus */ + dev->i2c_bus[0].nr = 0; + dev->i2c_bus[0].dev = dev; + dev->i2c_bus[0].reg_stat = I2C1_STAT; + dev->i2c_bus[0].reg_ctrl = I2C1_CTRL; + dev->i2c_bus[0].reg_addr = I2C1_ADDR; + dev->i2c_bus[0].reg_rdata = I2C1_RDATA; + dev->i2c_bus[0].reg_wdata = I2C1_WDATA; + dev->i2c_bus[0].i2c_period = (0x07 << 24); /* 1.95MHz */ + + + if (get_resources(dev) < 0) { + printk(KERN_ERR "%s No more PCIe resources for " + "subsystem: %04x:%04x\n", + dev->name, dev->pci->subsystem_vendor, + dev->pci->subsystem_device); + + cx25821_devcount--; + return -ENODEV; + } + + /* PCIe stuff */ + dev->base_io_addr = pci_resource_start(dev->pci, 0); + io_size = pci_resource_len(dev->pci, 0); + + if (!dev->base_io_addr) { + CX25821_ERR("No PCI Memory resources, exiting!\n"); + return -ENODEV; + } + + dev->lmmio = ioremap(dev->base_io_addr, pci_resource_len(dev->pci, 0)); + + if (!dev->lmmio) { + CX25821_ERR + ("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n"); + cx25821_iounmap(dev); + return -ENOMEM; + } + + dev->bmmio = (u8 __iomem *) dev->lmmio; + + printk(KERN_INFO "%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n", + dev->name, dev->pci->subsystem_vendor, + dev->pci->subsystem_device, cx25821_boards[dev->board].name, + dev->board, card[dev->nr] == dev->board ? + "insmod option" : "autodetected"); + + /* init hardware */ + cx25821_initialize(dev); + + cx25821_i2c_register(&dev->i2c_bus[0]); +// cx25821_i2c_register(&dev->i2c_bus[1]); +// cx25821_i2c_register(&dev->i2c_bus[2]); + + CX25821_INFO("i2c register! bus->i2c_rc = %d\n", + dev->i2c_bus[0].i2c_rc); + + cx25821_card_setup(dev); + medusa_video_init(dev); + + for (i = 0; i < VID_CHANNEL_NUM; i++) { + if (cx25821_video_register(dev, i, video_template[i]) < 0) { + printk(KERN_ERR + "%s() Failed to register analog video adapters on VID channel %d\n", + __func__, i); + } + } + + for (i = VID_UPSTREAM_SRAM_CHANNEL_I; + i <= AUDIO_UPSTREAM_SRAM_CHANNEL_B; i++) { + //Since we don't have template8 for Audio Downstream + if (cx25821_video_register(dev, i, video_template[i - 1]) < 0) { + printk(KERN_ERR + "%s() Failed to register analog video adapters for Upstream channel %d.\n", + __func__, i); + } + } + + // register IOCTL device + dev->ioctl_dev = + cx25821_vdev_init(dev, dev->pci, video_template[VIDEO_IOCTL_CH], + "video"); + + if (video_register_device + (dev->ioctl_dev, VFL_TYPE_GRABBER, VIDEO_IOCTL_CH) < 0) { + cx25821_videoioctl_unregister(dev); + printk(KERN_ERR + "%s() Failed to register video adapter for IOCTL so releasing.\n", + __func__); + } + + cx25821_dev_checkrevision(dev); + CX25821_INFO("cx25821 setup done!\n"); + + return 0; +} + +void cx25821_start_upstream_video_ch1(struct cx25821_dev *dev, + struct upstream_user_struct *up_data) +{ + dev->_isNTSC = !strcmp(dev->vid_stdname, "NTSC") ? 1 : 0; + + dev->tvnorm = !dev->_isNTSC ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M; + medusa_set_videostandard(dev); + + cx25821_vidupstream_init_ch1(dev, dev->channel_select, + dev->pixel_format); +} + +void cx25821_start_upstream_video_ch2(struct cx25821_dev *dev, + struct upstream_user_struct *up_data) +{ + dev->_isNTSC_ch2 = !strcmp(dev->vid_stdname_ch2, "NTSC") ? 1 : 0; + + dev->tvnorm = !dev->_isNTSC_ch2 ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M; + medusa_set_videostandard(dev); + + cx25821_vidupstream_init_ch2(dev, dev->channel_select_ch2, + dev->pixel_format_ch2); +} + +void cx25821_start_upstream_audio(struct cx25821_dev *dev, + struct upstream_user_struct *up_data) +{ + cx25821_audio_upstream_init(dev, AUDIO_UPSTREAM_SRAM_CHANNEL_B); +} + +void cx25821_dev_unregister(struct cx25821_dev *dev) +{ + int i; + + if (!dev->base_io_addr) + return; + + cx25821_free_mem_upstream_ch1(dev); + cx25821_free_mem_upstream_ch2(dev); + cx25821_free_mem_upstream_audio(dev); + + release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0)); + + if (!atomic_dec_and_test(&dev->refcount)) + return; + + for (i = 0; i < VID_CHANNEL_NUM; i++) + cx25821_video_unregister(dev, i); + + for (i = VID_UPSTREAM_SRAM_CHANNEL_I; + i <= AUDIO_UPSTREAM_SRAM_CHANNEL_B; i++) { + cx25821_video_unregister(dev, i); + } + + cx25821_videoioctl_unregister(dev); + + cx25821_i2c_unregister(&dev->i2c_bus[0]); + cx25821_iounmap(dev); +} + +static __le32 *cx25821_risc_field(__le32 * rp, struct scatterlist *sglist, + unsigned int offset, u32 sync_line, + unsigned int bpl, unsigned int padding, + unsigned int lines) +{ + struct scatterlist *sg; + unsigned int line, todo; + + /* sync instruction */ + if (sync_line != NO_SYNC_LINE) { + *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); + } + + /* scan lines */ + sg = sglist; + for (line = 0; line < lines; line++) { + while (offset && offset >= sg_dma_len(sg)) { + offset -= sg_dma_len(sg); + sg++; + } + if (bpl <= sg_dma_len(sg) - offset) { + /* fits into current chunk */ + *(rp++) = + cpu_to_le32(RISC_WRITE | RISC_SOL | RISC_EOL | bpl); + *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); + *(rp++) = cpu_to_le32(0); /* bits 63-32 */ + offset += bpl; + } else { + /* scanline needs to be split */ + todo = bpl; + *(rp++) = + cpu_to_le32(RISC_WRITE | RISC_SOL | + (sg_dma_len(sg) - offset)); + *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); + *(rp++) = cpu_to_le32(0); /* bits 63-32 */ + todo -= (sg_dma_len(sg) - offset); + offset = 0; + sg++; + while (todo > sg_dma_len(sg)) { + *(rp++) = + cpu_to_le32(RISC_WRITE | sg_dma_len(sg)); + *(rp++) = cpu_to_le32(sg_dma_address(sg)); + *(rp++) = cpu_to_le32(0); /* bits 63-32 */ + todo -= sg_dma_len(sg); + sg++; + } + *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo); + *(rp++) = cpu_to_le32(sg_dma_address(sg)); + *(rp++) = cpu_to_le32(0); /* bits 63-32 */ + offset += todo; + } + + offset += padding; + } + + return rp; +} + +int cx25821_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc, + struct scatterlist *sglist, unsigned int top_offset, + unsigned int bottom_offset, unsigned int bpl, + unsigned int padding, unsigned int lines) +{ + u32 instructions; + u32 fields; + __le32 *rp; + int rc; + + fields = 0; + if (UNSET != top_offset) + fields++; + if (UNSET != bottom_offset) + fields++; + + /* estimate risc mem: worst case is one write per page border + + one write per scan line + syncs + jump (all 2 dwords). Padding + can cause next bpl to start close to a page border. First DMA + region may be smaller than PAGE_SIZE */ + /* write and jump need and extra dword */ + instructions = + fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines); + instructions += 2; + rc = btcx_riscmem_alloc(pci, risc, instructions * 12); + + if (rc < 0) + return rc; + + /* write risc instructions */ + rp = risc->cpu; + + if (UNSET != top_offset) { + rp = cx25821_risc_field(rp, sglist, top_offset, 0, bpl, padding, + lines); + } + + if (UNSET != bottom_offset) { + rp = cx25821_risc_field(rp, sglist, bottom_offset, 0x200, bpl, + padding, lines); + } + + /* save pointer to jmp instruction address */ + risc->jmp = rp; + BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); + + return 0; +} + +static __le32 *cx25821_risc_field_audio(__le32 * rp, struct scatterlist *sglist, + unsigned int offset, u32 sync_line, + unsigned int bpl, unsigned int padding, + unsigned int lines, unsigned int lpi) +{ + struct scatterlist *sg; + unsigned int line, todo, sol; + + /* sync instruction */ + if (sync_line != NO_SYNC_LINE) + *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); + + /* scan lines */ + sg = sglist; + for (line = 0; line < lines; line++) { + while (offset && offset >= sg_dma_len(sg)) { + offset -= sg_dma_len(sg); + sg++; + } + + if (lpi && line > 0 && !(line % lpi)) + sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC; + else + sol = RISC_SOL; + + if (bpl <= sg_dma_len(sg) - offset) { + /* fits into current chunk */ + *(rp++) = + cpu_to_le32(RISC_WRITE | sol | RISC_EOL | bpl); + *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); + *(rp++) = cpu_to_le32(0); /* bits 63-32 */ + offset += bpl; + } else { + /* scanline needs to be split */ + todo = bpl; + *(rp++) = cpu_to_le32(RISC_WRITE | sol | + (sg_dma_len(sg) - offset)); + *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); + *(rp++) = cpu_to_le32(0); /* bits 63-32 */ + todo -= (sg_dma_len(sg) - offset); + offset = 0; + sg++; + while (todo > sg_dma_len(sg)) { + *(rp++) = cpu_to_le32(RISC_WRITE | + sg_dma_len(sg)); + *(rp++) = cpu_to_le32(sg_dma_address(sg)); + *(rp++) = cpu_to_le32(0); /* bits 63-32 */ + todo -= sg_dma_len(sg); + sg++; + } + *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo); + *(rp++) = cpu_to_le32(sg_dma_address(sg)); + *(rp++) = cpu_to_le32(0); /* bits 63-32 */ + offset += todo; + } + offset += padding; + } + + return rp; +} + +int cx25821_risc_databuffer_audio(struct pci_dev *pci, + struct btcx_riscmem *risc, + struct scatterlist *sglist, + unsigned int bpl, + unsigned int lines, unsigned int lpi) +{ + u32 instructions; + __le32 *rp; + int rc; + + /* estimate risc mem: worst case is one write per page border + + one write per scan line + syncs + jump (all 2 dwords). Here + there is no padding and no sync. First DMA region may be smaller + than PAGE_SIZE */ + /* Jump and write need an extra dword */ + instructions = 1 + (bpl * lines) / PAGE_SIZE + lines; + instructions += 1; + + if ((rc = btcx_riscmem_alloc(pci, risc, instructions * 12)) < 0) + return rc; + + /* write risc instructions */ + rp = risc->cpu; + rp = cx25821_risc_field_audio(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, + lines, lpi); + + /* save pointer to jmp instruction address */ + risc->jmp = rp; + BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); + return 0; +} + +int cx25821_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc, + u32 reg, u32 mask, u32 value) +{ + __le32 *rp; + int rc; + + rc = btcx_riscmem_alloc(pci, risc, 4 * 16); + + if (rc < 0) + return rc; + + /* write risc instructions */ + rp = risc->cpu; + + *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ1); + *(rp++) = cpu_to_le32(reg); + *(rp++) = cpu_to_le32(value); + *(rp++) = cpu_to_le32(mask); + *(rp++) = cpu_to_le32(RISC_JUMP); + *(rp++) = cpu_to_le32(risc->dma); + *(rp++) = cpu_to_le32(0); /* bits 63-32 */ + return 0; +} + +void cx25821_free_buffer(struct videobuf_queue *q, struct cx25821_buffer *buf) +{ + struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); + + BUG_ON(in_interrupt()); + videobuf_waiton(&buf->vb, 0, 0); + videobuf_dma_unmap(q, dma); + videobuf_dma_free(dma); + btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc); + buf->vb.state = VIDEOBUF_NEEDS_INIT; +} + +static irqreturn_t cx25821_irq(int irq, void *dev_id) +{ + struct cx25821_dev *dev = dev_id; + u32 pci_status, pci_mask; + u32 vid_status; + int i, handled = 0; + u32 mask[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; + + pci_status = cx_read(PCI_INT_STAT); + pci_mask = cx_read(PCI_INT_MSK); + + if (pci_status == 0) + goto out; + + for (i = 0; i < VID_CHANNEL_NUM; i++) { + if (pci_status & mask[i]) { + vid_status = cx_read(dev->sram_channels[i].int_stat); + + if (vid_status) + handled += + cx25821_video_irq(dev, i, vid_status); + + cx_write(PCI_INT_STAT, mask[i]); + } + } + + out: + return IRQ_RETVAL(handled); +} + +void cx25821_print_irqbits(char *name, char *tag, char **strings, + int len, u32 bits, u32 mask) +{ + unsigned int i; + + printk(KERN_DEBUG "%s: %s [0x%x]", name, tag, bits); + + for (i = 0; i < len; i++) { + if (!(bits & (1 << i))) + continue; + if (strings[i]) + printk(" %s", strings[i]); + else + printk(" %d", i); + if (!(mask & (1 << i))) + continue; + printk("*"); + } + printk("\n"); +} + +struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci) +{ + struct cx25821_dev *dev = pci_get_drvdata(pci); + return dev; +} + +static int __devinit cx25821_initdev(struct pci_dev *pci_dev, + const struct pci_device_id *pci_id) +{ + struct cx25821_dev *dev; + int err = 0; + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (NULL == dev) + return -ENOMEM; + + err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev); + if (err < 0) + goto fail_free; + + /* pci init */ + dev->pci = pci_dev; + if (pci_enable_device(pci_dev)) { + err = -EIO; + + printk(KERN_INFO "pci enable failed! "); + + goto fail_unregister_device; + } + + printk(KERN_INFO "cx25821 Athena pci enable ! \n"); + + if (cx25821_dev_setup(dev) < 0) { + err = -EINVAL; + goto fail_unregister_device; + } + + /* print pci info */ + pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev); + pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); + printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, " + "latency: %d, mmio: 0x%llx\n", dev->name, + pci_name(pci_dev), dev->pci_rev, pci_dev->irq, + dev->pci_lat, (unsigned long long)dev->base_io_addr); + + pci_set_master(pci_dev); + if (!pci_dma_supported(pci_dev, 0xffffffff)) { + printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name); + err = -EIO; + goto fail_irq; + } + + err = + request_irq(pci_dev->irq, cx25821_irq, IRQF_SHARED | IRQF_DISABLED, + dev->name, dev); + + if (err < 0) { + printk(KERN_ERR "%s: can't get IRQ %d\n", dev->name, + pci_dev->irq); + goto fail_irq; + } + + return 0; + + fail_irq: + printk(KERN_INFO "cx25821 cx25821_initdev() can't get IRQ ! \n"); + cx25821_dev_unregister(dev); + + fail_unregister_device: + v4l2_device_unregister(&dev->v4l2_dev); + + fail_free: + kfree(dev); + return err; +} + +static void __devexit cx25821_finidev(struct pci_dev *pci_dev) +{ + struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev); + struct cx25821_dev *dev = get_cx25821(v4l2_dev); + + cx25821_shutdown(dev); + pci_disable_device(pci_dev); + + /* unregister stuff */ + if (pci_dev->irq) + free_irq(pci_dev->irq, dev); + + mutex_lock(&devlist); + list_del(&dev->devlist); + mutex_unlock(&devlist); + + cx25821_dev_unregister(dev); + v4l2_device_unregister(v4l2_dev); + kfree(dev); +} + +static struct pci_device_id cx25821_pci_tbl[] = { + { + /* CX25821 Athena */ + .vendor = 0x14f1, + .device = 0x8210, + .subvendor = 0x14f1, + .subdevice = 0x0920, + }, + { + /* --- end of list --- */ + } +}; + +MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl); + +static struct pci_driver cx25821_pci_driver = { + .name = "cx25821", + .id_table = cx25821_pci_tbl, + .probe = cx25821_initdev, + .remove = __devexit_p(cx25821_finidev), + /* TODO */ + .suspend = NULL, + .resume = NULL, +}; + +static int cx25821_init(void) +{ + INIT_LIST_HEAD(&cx25821_devlist); + printk(KERN_INFO "cx25821 driver version %d.%d.%d loaded\n", + (CX25821_VERSION_CODE >> 16) & 0xff, + (CX25821_VERSION_CODE >> 8) & 0xff, CX25821_VERSION_CODE & 0xff); + return pci_register_driver(&cx25821_pci_driver); +} + +static void cx25821_fini(void) +{ + pci_unregister_driver(&cx25821_pci_driver); +} + +EXPORT_SYMBOL(cx25821_devlist); +EXPORT_SYMBOL(cx25821_sram_channels); +EXPORT_SYMBOL(cx25821_print_irqbits); +EXPORT_SYMBOL(cx25821_dev_get); +EXPORT_SYMBOL(cx25821_dev_unregister); +EXPORT_SYMBOL(cx25821_sram_channel_setup); +EXPORT_SYMBOL(cx25821_sram_channel_dump); +EXPORT_SYMBOL(cx25821_sram_channel_setup_audio); +EXPORT_SYMBOL(cx25821_sram_channel_dump_audio); +EXPORT_SYMBOL(cx25821_risc_databuffer_audio); +EXPORT_SYMBOL(cx25821_set_gpiopin_direction); + +module_init(cx25821_init); +module_exit(cx25821_fini); diff --git a/drivers/staging/cx25821/cx25821-gpio.c b/drivers/staging/cx25821/cx25821-gpio.c new file mode 100644 index 000000000000..e8a37b47e437 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-gpio.c @@ -0,0 +1,98 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821.h" + +/********************* GPIO stuffs *********************/ +void cx25821_set_gpiopin_direction(struct cx25821_dev *dev, + int pin_number, int pin_logic_value) +{ + int bit = pin_number; + u32 gpio_oe_reg = GPIO_LO_OE; + u32 gpio_register = 0; + u32 value = 0; + + // Check for valid pinNumber + if (pin_number >= 47) + return; + + if (pin_number > 31) { + bit = pin_number - 31; + gpio_oe_reg = GPIO_HI_OE; + } + // Here we will make sure that the GPIOs 0 and 1 are output. keep the rest as is + gpio_register = cx_read(gpio_oe_reg); + + if (pin_logic_value == 1) { + value = gpio_register | Set_GPIO_Bit(bit); + } else { + value = gpio_register & Clear_GPIO_Bit(bit); + } + + cx_write(gpio_oe_reg, value); +} + +static void cx25821_set_gpiopin_logicvalue(struct cx25821_dev *dev, + int pin_number, int pin_logic_value) +{ + int bit = pin_number; + u32 gpio_reg = GPIO_LO; + u32 value = 0; + + // Check for valid pinNumber + if (pin_number >= 47) + return; + + cx25821_set_gpiopin_direction(dev, pin_number, 0); // change to output direction + + if (pin_number > 31) { + bit = pin_number - 31; + gpio_reg = GPIO_HI; + } + + value = cx_read(gpio_reg); + + if (pin_logic_value == 0) { + value &= Clear_GPIO_Bit(bit); + } else { + value |= Set_GPIO_Bit(bit); + } + + cx_write(gpio_reg, value); +} + +void cx25821_gpio_init(struct cx25821_dev *dev) +{ + if (dev == NULL) { + return; + } + + switch (dev->board) { + case CX25821_BOARD_CONEXANT_ATHENA10: + default: + //set GPIO 5 to select the path for Medusa/Athena + cx25821_set_gpiopin_logicvalue(dev, 5, 1); + mdelay(20); + break; + } + +} diff --git a/drivers/staging/cx25821/cx25821-gpio.h b/drivers/staging/cx25821/cx25821-gpio.h new file mode 100644 index 000000000000..ca07644154af --- /dev/null +++ b/drivers/staging/cx25821/cx25821-gpio.h @@ -0,0 +1,2 @@ + +void cx25821_gpio_init(struct athena_dev *dev); diff --git a/drivers/staging/cx25821/cx25821-i2c.c b/drivers/staging/cx25821/cx25821-i2c.c new file mode 100644 index 000000000000..f4f2681d8f1c --- /dev/null +++ b/drivers/staging/cx25821/cx25821-i2c.c @@ -0,0 +1,419 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821.h" +#include + +static unsigned int i2c_debug; +module_param(i2c_debug, int, 0644); +MODULE_PARM_DESC(i2c_debug, "enable debug messages [i2c]"); + +static unsigned int i2c_scan = 0; +module_param(i2c_scan, int, 0444); +MODULE_PARM_DESC(i2c_scan, "scan i2c bus at insmod time"); + +#define dprintk(level, fmt, arg...)\ + do { if (i2c_debug >= level)\ + printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\ + } while (0) + +#define I2C_WAIT_DELAY 32 +#define I2C_WAIT_RETRY 64 + +#define I2C_EXTEND (1 << 3) +#define I2C_NOSTOP (1 << 4) + +static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap) +{ + struct cx25821_i2c *bus = i2c_adap->algo_data; + struct cx25821_dev *dev = bus->dev; + return cx_read(bus->reg_stat) & 0x01; +} + +static inline int i2c_is_busy(struct i2c_adapter *i2c_adap) +{ + struct cx25821_i2c *bus = i2c_adap->algo_data; + struct cx25821_dev *dev = bus->dev; + return cx_read(bus->reg_stat) & 0x02 ? 1 : 0; +} + +static int i2c_wait_done(struct i2c_adapter *i2c_adap) +{ + int count; + + for (count = 0; count < I2C_WAIT_RETRY; count++) { + if (!i2c_is_busy(i2c_adap)) + break; + udelay(I2C_WAIT_DELAY); + } + + if (I2C_WAIT_RETRY == count) + return 0; + + return 1; +} + +static int i2c_sendbytes(struct i2c_adapter *i2c_adap, + const struct i2c_msg *msg, int joined_rlen) +{ + struct cx25821_i2c *bus = i2c_adap->algo_data; + struct cx25821_dev *dev = bus->dev; + u32 wdata, addr, ctrl; + int retval, cnt; + + if (joined_rlen) + dprintk(1, "%s(msg->wlen=%d, nextmsg->rlen=%d)\n", __func__, + msg->len, joined_rlen); + else + dprintk(1, "%s(msg->len=%d)\n", __func__, msg->len); + + /* Deal with i2c probe functions with zero payload */ + if (msg->len == 0) { + cx_write(bus->reg_addr, msg->addr << 25); + cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2)); + + if (!i2c_wait_done(i2c_adap)) + return -EIO; + + if (!i2c_slave_did_ack(i2c_adap)) + return -EIO; + + dprintk(1, "%s() returns 0\n", __func__); + return 0; + } + + /* dev, reg + first byte */ + addr = (msg->addr << 25) | msg->buf[0]; + wdata = msg->buf[0]; + + ctrl = bus->i2c_period | (1 << 12) | (1 << 2); + + if (msg->len > 1) + ctrl |= I2C_NOSTOP | I2C_EXTEND; + else if (joined_rlen) + ctrl |= I2C_NOSTOP; + + cx_write(bus->reg_addr, addr); + cx_write(bus->reg_wdata, wdata); + cx_write(bus->reg_ctrl, ctrl); + + retval = i2c_wait_done(i2c_adap); + if (retval < 0) + goto err; + + if (retval == 0) + goto eio; + + if (i2c_debug) { + if (!(ctrl & I2C_NOSTOP)) + printk(" >\n"); + } + + for (cnt = 1; cnt < msg->len; cnt++) { + /* following bytes */ + wdata = msg->buf[cnt]; + ctrl = bus->i2c_period | (1 << 12) | (1 << 2); + + if (cnt < msg->len - 1) + ctrl |= I2C_NOSTOP | I2C_EXTEND; + else if (joined_rlen) + ctrl |= I2C_NOSTOP; + + cx_write(bus->reg_addr, addr); + cx_write(bus->reg_wdata, wdata); + cx_write(bus->reg_ctrl, ctrl); + + retval = i2c_wait_done(i2c_adap); + if (retval < 0) + goto err; + + if (retval == 0) + goto eio; + + if (i2c_debug) { + dprintk(1, " %02x", msg->buf[cnt]); + if (!(ctrl & I2C_NOSTOP)) + dprintk(1, " >\n"); + } + } + + return msg->len; + + eio: + retval = -EIO; + err: + if (i2c_debug) + printk(KERN_ERR " ERR: %d\n", retval); + return retval; +} + +static int i2c_readbytes(struct i2c_adapter *i2c_adap, + const struct i2c_msg *msg, int joined) +{ + struct cx25821_i2c *bus = i2c_adap->algo_data; + struct cx25821_dev *dev = bus->dev; + u32 ctrl, cnt; + int retval; + + if (i2c_debug && !joined) + dprintk(1, "6-%s(msg->len=%d)\n", __func__, msg->len); + + /* Deal with i2c probe functions with zero payload */ + if (msg->len == 0) { + cx_write(bus->reg_addr, msg->addr << 25); + cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2) | 1); + if (!i2c_wait_done(i2c_adap)) + return -EIO; + if (!i2c_slave_did_ack(i2c_adap)) + return -EIO; + + dprintk(1, "%s() returns 0\n", __func__); + return 0; + } + + if (i2c_debug) { + if (joined) + dprintk(1, " R"); + else + dprintk(1, " addr << 1) + 1); + } + + for (cnt = 0; cnt < msg->len; cnt++) { + + ctrl = bus->i2c_period | (1 << 12) | (1 << 2) | 1; + + if (cnt < msg->len - 1) + ctrl |= I2C_NOSTOP | I2C_EXTEND; + + cx_write(bus->reg_addr, msg->addr << 25); + cx_write(bus->reg_ctrl, ctrl); + + retval = i2c_wait_done(i2c_adap); + if (retval < 0) + goto err; + if (retval == 0) + goto eio; + msg->buf[cnt] = cx_read(bus->reg_rdata) & 0xff; + + if (i2c_debug) { + dprintk(1, " %02x", msg->buf[cnt]); + if (!(ctrl & I2C_NOSTOP)) + dprintk(1, " >\n"); + } + } + + return msg->len; + eio: + retval = -EIO; + err: + if (i2c_debug) + printk(KERN_ERR " ERR: %d\n", retval); + return retval; +} + +static int i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) +{ + struct cx25821_i2c *bus = i2c_adap->algo_data; + struct cx25821_dev *dev = bus->dev; + int i, retval = 0; + + dprintk(1, "%s(num = %d)\n", __func__, num); + + for (i = 0; i < num; i++) { + dprintk(1, "%s(num = %d) addr = 0x%02x len = 0x%x\n", + __func__, num, msgs[i].addr, msgs[i].len); + + if (msgs[i].flags & I2C_M_RD) { + /* read */ + retval = i2c_readbytes(i2c_adap, &msgs[i], 0); + } else if (i + 1 < num && (msgs[i + 1].flags & I2C_M_RD) && + msgs[i].addr == msgs[i + 1].addr) { + /* write then read from same address */ + retval = + i2c_sendbytes(i2c_adap, &msgs[i], msgs[i + 1].len); + + if (retval < 0) + goto err; + i++; + retval = i2c_readbytes(i2c_adap, &msgs[i], 1); + } else { + /* write */ + retval = i2c_sendbytes(i2c_adap, &msgs[i], 0); + } + + if (retval < 0) + goto err; + } + return num; + + err: + return retval; +} + + +static u32 cx25821_functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_SMBUS_EMUL | + I2C_FUNC_I2C | + I2C_FUNC_SMBUS_WORD_DATA | + I2C_FUNC_SMBUS_READ_WORD_DATA | I2C_FUNC_SMBUS_WRITE_WORD_DATA; +} + +static struct i2c_algorithm cx25821_i2c_algo_template = { + .master_xfer = i2c_xfer, + .functionality = cx25821_functionality, +}; + +static struct i2c_adapter cx25821_i2c_adap_template = { + .name = "cx25821", + .owner = THIS_MODULE, + .algo = &cx25821_i2c_algo_template, +}; + +static struct i2c_client cx25821_i2c_client_template = { + .name = "cx25821 internal", +}; + +/* init + register i2c algo-bit adapter */ +int cx25821_i2c_register(struct cx25821_i2c *bus) +{ + struct cx25821_dev *dev = bus->dev; + + dprintk(1, "%s(bus = %d)\n", __func__, bus->nr); + + memcpy(&bus->i2c_adap, &cx25821_i2c_adap_template, + sizeof(bus->i2c_adap)); + memcpy(&bus->i2c_algo, &cx25821_i2c_algo_template, + sizeof(bus->i2c_algo)); + memcpy(&bus->i2c_client, &cx25821_i2c_client_template, + sizeof(bus->i2c_client)); + + bus->i2c_adap.dev.parent = &dev->pci->dev; + + strlcpy(bus->i2c_adap.name, bus->dev->name, sizeof(bus->i2c_adap.name)); + + bus->i2c_algo.data = bus; + bus->i2c_adap.algo_data = bus; + i2c_set_adapdata(&bus->i2c_adap, &dev->v4l2_dev); + i2c_add_adapter(&bus->i2c_adap); + + bus->i2c_client.adapter = &bus->i2c_adap; + + //set up the I2c + bus->i2c_client.addr = (0x88 >> 1); + + return bus->i2c_rc; +} + +int cx25821_i2c_unregister(struct cx25821_i2c *bus) +{ + i2c_del_adapter(&bus->i2c_adap); + return 0; +} + +void cx25821_av_clk(struct cx25821_dev *dev, int enable) +{ + /* write 0 to bus 2 addr 0x144 via i2x_xfer() */ + char buffer[3]; + struct i2c_msg msg; + dprintk(1, "%s(enabled = %d)\n", __func__, enable); + + /* Register 0x144 */ + buffer[0] = 0x01; + buffer[1] = 0x44; + if (enable == 1) + buffer[2] = 0x05; + else + buffer[2] = 0x00; + + msg.addr = 0x44; + msg.flags = I2C_M_TEN; + msg.len = 3; + msg.buf = buffer; + + i2c_xfer(&dev->i2c_bus[0].i2c_adap, &msg, 1); +} + +int cx25821_i2c_read(struct cx25821_i2c *bus, u16 reg_addr, int *value) +{ + struct i2c_client *client = &bus->i2c_client; + int retval = 0; + int v = 0; + u8 addr[2] = { 0, 0 }; + u8 buf[4] = { 0, 0, 0, 0 }; + + struct i2c_msg msgs[2] = { + { + .addr = client->addr, + .flags = 0, + .len = 2, + .buf = addr, + }, { + .addr = client->addr, + .flags = I2C_M_RD, + .len = 4, + .buf = buf, + } + }; + + addr[0] = (reg_addr >> 8); + addr[1] = (reg_addr & 0xff); + msgs[0].addr = 0x44; + msgs[1].addr = 0x44; + + retval = i2c_xfer(client->adapter, msgs, 2); + + v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; + *value = v; + + return v; +} + +int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value) +{ + struct i2c_client *client = &bus->i2c_client; + int retval = 0; + u8 buf[6] = { 0, 0, 0, 0, 0, 0 }; + + struct i2c_msg msgs[1] = { + { + .addr = client->addr, + .flags = 0, + .len = 6, + .buf = buf, + } + }; + + buf[0] = reg_addr >> 8; + buf[1] = reg_addr & 0xff; + buf[5] = (value >> 24) & 0xff; + buf[4] = (value >> 16) & 0xff; + buf[3] = (value >> 8) & 0xff; + buf[2] = value & 0xff; + client->flags = 0; + msgs[0].addr = 0x44; + + retval = i2c_xfer(client->adapter, msgs, 1); + + return retval; +} diff --git a/drivers/staging/cx25821/cx25821-medusa-defines.h b/drivers/staging/cx25821/cx25821-medusa-defines.h new file mode 100644 index 000000000000..b0d216ba7f81 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-medusa-defines.h @@ -0,0 +1,51 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _MEDUSA_DEF_H_ +#define _MEDUSA_DEF_H_ + +// Video deocder that we supported +#define VDEC_A 0 +#define VDEC_B 1 +#define VDEC_C 2 +#define VDEC_D 3 +#define VDEC_E 4 +#define VDEC_F 5 +#define VDEC_G 6 +#define VDEC_H 7 + +//#define AUTO_SWITCH_BIT[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; + +// The following bit position enables automatic source switching for decoder A-H. +// Display index per camera. +//#define VDEC_INDEX[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}; + +// Select input bit to video decoder A-H. +//#define CH_SRC_SEL_BIT[] = {24, 25, 26, 27, 28, 29, 30, 31}; + +// end of display sequence +#define END_OF_SEQ 0xF; + +// registry string size +#define MAX_REGISTRY_SZ 40; + +#endif diff --git a/drivers/staging/cx25821/cx25821-medusa-reg.h b/drivers/staging/cx25821/cx25821-medusa-reg.h new file mode 100644 index 000000000000..12c90f831b22 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-medusa-reg.h @@ -0,0 +1,455 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __MEDUSA_REGISTERS__ +#define __MEDUSA_REGISTERS__ + +// Serial Slave Registers +#define HOST_REGISTER1 0x0000 +#define HOST_REGISTER2 0x0001 + +// Chip Configuration Registers +#define CHIP_CTRL 0x0100 +#define AFE_AB_CTRL 0x0104 +#define AFE_CD_CTRL 0x0108 +#define AFE_EF_CTRL 0x010C +#define AFE_GH_CTRL 0x0110 +#define DENC_AB_CTRL 0x0114 +#define BYP_AB_CTRL 0x0118 +#define MON_A_CTRL 0x011C +#define DISP_SEQ_A 0x0120 +#define DISP_SEQ_B 0x0124 +#define DISP_AB_CNT 0x0128 +#define DISP_CD_CNT 0x012C +#define DISP_EF_CNT 0x0130 +#define DISP_GH_CNT 0x0134 +#define DISP_IJ_CNT 0x0138 +#define PIN_OE_CTRL 0x013C +#define PIN_SPD_CTRL 0x0140 +#define PIN_SPD_CTRL2 0x0144 +#define IRQ_STAT_CTRL 0x0148 +#define POWER_CTRL_AB 0x014C +#define POWER_CTRL_CD 0x0150 +#define POWER_CTRL_EF 0x0154 +#define POWER_CTRL_GH 0x0158 +#define TUNE_CTRL 0x015C +#define BIAS_CTRL 0x0160 +#define AFE_AB_DIAG_CTRL 0x0164 +#define AFE_CD_DIAG_CTRL 0x0168 +#define AFE_EF_DIAG_CTRL 0x016C +#define AFE_GH_DIAG_CTRL 0x0170 +#define PLL_AB_DIAG_CTRL 0x0174 +#define PLL_CD_DIAG_CTRL 0x0178 +#define PLL_EF_DIAG_CTRL 0x017C +#define PLL_GH_DIAG_CTRL 0x0180 +#define TEST_CTRL 0x0184 +#define BIST_STAT 0x0188 +#define BIST_STAT2 0x018C +#define BIST_VID_PLL_AB_STAT 0x0190 +#define BIST_VID_PLL_CD_STAT 0x0194 +#define BIST_VID_PLL_EF_STAT 0x0198 +#define BIST_VID_PLL_GH_STAT 0x019C +#define DLL_DIAG_CTRL 0x01A0 +#define DEV_CH_ID_CTRL 0x01A4 +#define ABIST_CTRL_STATUS 0x01A8 +#define ABIST_FREQ 0x01AC +#define ABIST_GOERT_SHIFT 0x01B0 +#define ABIST_COEF12 0x01B4 +#define ABIST_COEF34 0x01B8 +#define ABIST_COEF56 0x01BC +#define ABIST_COEF7_SNR 0x01C0 +#define ABIST_ADC_CAL 0x01C4 +#define ABIST_BIN1_VGA0 0x01C8 +#define ABIST_BIN2_VGA1 0x01CC +#define ABIST_BIN3_VGA2 0x01D0 +#define ABIST_BIN4_VGA3 0x01D4 +#define ABIST_BIN5_VGA4 0x01D8 +#define ABIST_BIN6_VGA5 0x01DC +#define ABIST_BIN7_VGA6 0x0x1E0 +#define ABIST_CLAMP_A 0x0x1E4 +#define ABIST_CLAMP_B 0x0x1E8 +#define ABIST_CLAMP_C 0x01EC +#define ABIST_CLAMP_D 0x01F0 +#define ABIST_CLAMP_E 0x01F4 +#define ABIST_CLAMP_F 0x01F8 + +// Digital Video Encoder A Registers +#define DENC_A_REG_1 0x0200 +#define DENC_A_REG_2 0x0204 +#define DENC_A_REG_3 0x0208 +#define DENC_A_REG_4 0x020C +#define DENC_A_REG_5 0x0210 +#define DENC_A_REG_6 0x0214 +#define DENC_A_REG_7 0x0218 +#define DENC_A_REG_8 0x021C + +// Digital Video Encoder B Registers +#define DENC_B_REG_1 0x0300 +#define DENC_B_REG_2 0x0304 +#define DENC_B_REG_3 0x0308 +#define DENC_B_REG_4 0x030C +#define DENC_B_REG_5 0x0310 +#define DENC_B_REG_6 0x0314 +#define DENC_B_REG_7 0x0318 +#define DENC_B_REG_8 0x031C + +// Video Decoder A Registers +#define MODE_CTRL 0x1000 +#define OUT_CTRL1 0x1004 +#define OUT_CTRL_NS 0x1008 +#define GEN_STAT 0x100C +#define INT_STAT_MASK 0x1010 +#define LUMA_CTRL 0x1014 +#define CHROMA_CTRL 0x1018 +#define CRUSH_CTRL 0x101C +#define HORIZ_TIM_CTRL 0x1020 +#define VERT_TIM_CTRL 0x1024 +#define MISC_TIM_CTRL 0x1028 +#define FIELD_COUNT 0x102C +#define HSCALE_CTRL 0x1030 +#define VSCALE_CTRL 0x1034 +#define MAN_VGA_CTRL 0x1038 +#define MAN_AGC_CTRL 0x103C +#define DFE_CTRL1 0x1040 +#define DFE_CTRL2 0x1044 +#define DFE_CTRL3 0x1048 +#define PLL_CTRL 0x104C +#define PLL_CTRL_FAST 0x1050 +#define HTL_CTRL 0x1054 +#define SRC_CFG 0x1058 +#define SC_STEP_SIZE 0x105C +#define SC_CONVERGE_CTRL 0x1060 +#define SC_LOOP_CTRL 0x1064 +#define COMB_2D_HFS_CFG 0x1068 +#define COMB_2D_HFD_CFG 0x106C +#define COMB_2D_LF_CFG 0x1070 +#define COMB_2D_BLEND 0x1074 +#define COMB_MISC_CTRL 0x1078 +#define COMB_FLAT_THRESH_CTRL 0x107C +#define COMB_TEST 0x1080 +#define BP_MISC_CTRL 0x1084 +#define VCR_DET_CTRL 0x1088 +#define NOISE_DET_CTRL 0x108C +#define COMB_FLAT_NOISE_CTRL 0x1090 +#define VERSION 0x11F8 +#define SOFT_RST_CTRL 0x11FC + +// Video Decoder B Registers +#define VDEC_B_MODE_CTRL 0x1200 +#define VDEC_B_OUT_CTRL1 0x1204 +#define VDEC_B_OUT_CTRL_NS 0x1208 +#define VDEC_B_GEN_STAT 0x120C +#define VDEC_B_INT_STAT_MASK 0x1210 +#define VDEC_B_LUMA_CTRL 0x1214 +#define VDEC_B_CHROMA_CTRL 0x1218 +#define VDEC_B_CRUSH_CTRL 0x121C +#define VDEC_B_HORIZ_TIM_CTRL 0x1220 +#define VDEC_B_VERT_TIM_CTRL 0x1224 +#define VDEC_B_MISC_TIM_CTRL 0x1228 +#define VDEC_B_FIELD_COUNT 0x122C +#define VDEC_B_HSCALE_CTRL 0x1230 +#define VDEC_B_VSCALE_CTRL 0x1234 +#define VDEC_B_MAN_VGA_CTRL 0x1238 +#define VDEC_B_MAN_AGC_CTRL 0x123C +#define VDEC_B_DFE_CTRL1 0x1240 +#define VDEC_B_DFE_CTRL2 0x1244 +#define VDEC_B_DFE_CTRL3 0x1248 +#define VDEC_B_PLL_CTRL 0x124C +#define VDEC_B_PLL_CTRL_FAST 0x1250 +#define VDEC_B_HTL_CTRL 0x1254 +#define VDEC_B_SRC_CFG 0x1258 +#define VDEC_B_SC_STEP_SIZE 0x125C +#define VDEC_B_SC_CONVERGE_CTRL 0x1260 +#define VDEC_B_SC_LOOP_CTRL 0x1264 +#define VDEC_B_COMB_2D_HFS_CFG 0x1268 +#define VDEC_B_COMB_2D_HFD_CFG 0x126C +#define VDEC_B_COMB_2D_LF_CFG 0x1270 +#define VDEC_B_COMB_2D_BLEND 0x1274 +#define VDEC_B_COMB_MISC_CTRL 0x1278 +#define VDEC_B_COMB_FLAT_THRESH_CTRL 0x127C +#define VDEC_B_COMB_TEST 0x1280 +#define VDEC_B_BP_MISC_CTRL 0x1284 +#define VDEC_B_VCR_DET_CTRL 0x1288 +#define VDEC_B_NOISE_DET_CTRL 0x128C +#define VDEC_B_COMB_FLAT_NOISE_CTRL 0x1290 +#define VDEC_B_VERSION 0x13F8 +#define VDEC_B_SOFT_RST_CTRL 0x13FC + +// Video Decoder C Registers +#define VDEC_C_MODE_CTRL 0x1400 +#define VDEC_C_OUT_CTRL1 0x1404 +#define VDEC_C_OUT_CTRL_NS 0x1408 +#define VDEC_C_GEN_STAT 0x140C +#define VDEC_C_INT_STAT_MASK 0x1410 +#define VDEC_C_LUMA_CTRL 0x1414 +#define VDEC_C_CHROMA_CTRL 0x1418 +#define VDEC_C_CRUSH_CTRL 0x141C +#define VDEC_C_HORIZ_TIM_CTRL 0x1420 +#define VDEC_C_VERT_TIM_CTRL 0x1424 +#define VDEC_C_MISC_TIM_CTRL 0x1428 +#define VDEC_C_FIELD_COUNT 0x142C +#define VDEC_C_HSCALE_CTRL 0x1430 +#define VDEC_C_VSCALE_CTRL 0x1434 +#define VDEC_C_MAN_VGA_CTRL 0x1438 +#define VDEC_C_MAN_AGC_CTRL 0x143C +#define VDEC_C_DFE_CTRL1 0x1440 +#define VDEC_C_DFE_CTRL2 0x1444 +#define VDEC_C_DFE_CTRL3 0x1448 +#define VDEC_C_PLL_CTRL 0x144C +#define VDEC_C_PLL_CTRL_FAST 0x1450 +#define VDEC_C_HTL_CTRL 0x1454 +#define VDEC_C_SRC_CFG 0x1458 +#define VDEC_C_SC_STEP_SIZE 0x145C +#define VDEC_C_SC_CONVERGE_CTRL 0x1460 +#define VDEC_C_SC_LOOP_CTRL 0x1464 +#define VDEC_C_COMB_2D_HFS_CFG 0x1468 +#define VDEC_C_COMB_2D_HFD_CFG 0x146C +#define VDEC_C_COMB_2D_LF_CFG 0x1470 +#define VDEC_C_COMB_2D_BLEND 0x1474 +#define VDEC_C_COMB_MISC_CTRL 0x1478 +#define VDEC_C_COMB_FLAT_THRESH_CTRL 0x147C +#define VDEC_C_COMB_TEST 0x1480 +#define VDEC_C_BP_MISC_CTRL 0x1484 +#define VDEC_C_VCR_DET_CTRL 0x1488 +#define VDEC_C_NOISE_DET_CTRL 0x148C +#define VDEC_C_COMB_FLAT_NOISE_CTRL 0x1490 +#define VDEC_C_VERSION 0x15F8 +#define VDEC_C_SOFT_RST_CTRL 0x15FC + +// Video Decoder D Registers +#define VDEC_D_MODE_CTRL 0x1600 +#define VDEC_D_OUT_CTRL1 0x1604 +#define VDEC_D_OUT_CTRL_NS 0x1608 +#define VDEC_D_GEN_STAT 0x160C +#define VDEC_D_INT_STAT_MASK 0x1610 +#define VDEC_D_LUMA_CTRL 0x1614 +#define VDEC_D_CHROMA_CTRL 0x1618 +#define VDEC_D_CRUSH_CTRL 0x161C +#define VDEC_D_HORIZ_TIM_CTRL 0x1620 +#define VDEC_D_VERT_TIM_CTRL 0x1624 +#define VDEC_D_MISC_TIM_CTRL 0x1628 +#define VDEC_D_FIELD_COUNT 0x162C +#define VDEC_D_HSCALE_CTRL 0x1630 +#define VDEC_D_VSCALE_CTRL 0x1634 +#define VDEC_D_MAN_VGA_CTRL 0x1638 +#define VDEC_D_MAN_AGC_CTRL 0x163C +#define VDEC_D_DFE_CTRL1 0x1640 +#define VDEC_D_DFE_CTRL2 0x1644 +#define VDEC_D_DFE_CTRL3 0x1648 +#define VDEC_D_PLL_CTRL 0x164C +#define VDEC_D_PLL_CTRL_FAST 0x1650 +#define VDEC_D_HTL_CTRL 0x1654 +#define VDEC_D_SRC_CFG 0x1658 +#define VDEC_D_SC_STEP_SIZE 0x165C +#define VDEC_D_SC_CONVERGE_CTRL 0x1660 +#define VDEC_D_SC_LOOP_CTRL 0x1664 +#define VDEC_D_COMB_2D_HFS_CFG 0x1668 +#define VDEC_D_COMB_2D_HFD_CFG 0x166C +#define VDEC_D_COMB_2D_LF_CFG 0x1670 +#define VDEC_D_COMB_2D_BLEND 0x1674 +#define VDEC_D_COMB_MISC_CTRL 0x1678 +#define VDEC_D_COMB_FLAT_THRESH_CTRL 0x167C +#define VDEC_D_COMB_TEST 0x1680 +#define VDEC_D_BP_MISC_CTRL 0x1684 +#define VDEC_D_VCR_DET_CTRL 0x1688 +#define VDEC_D_NOISE_DET_CTRL 0x168C +#define VDEC_D_COMB_FLAT_NOISE_CTRL 0x1690 +#define VDEC_D_VERSION 0x17F8 +#define VDEC_D_SOFT_RST_CTRL 0x17FC + +// Video Decoder E Registers +#define VDEC_E_MODE_CTRL 0x1800 +#define VDEC_E_OUT_CTRL1 0x1804 +#define VDEC_E_OUT_CTRL_NS 0x1808 +#define VDEC_E_GEN_STAT 0x180C +#define VDEC_E_INT_STAT_MASK 0x1810 +#define VDEC_E_LUMA_CTRL 0x1814 +#define VDEC_E_CHROMA_CTRL 0x1818 +#define VDEC_E_CRUSH_CTRL 0x181C +#define VDEC_E_HORIZ_TIM_CTRL 0x1820 +#define VDEC_E_VERT_TIM_CTRL 0x1824 +#define VDEC_E_MISC_TIM_CTRL 0x1828 +#define VDEC_E_FIELD_COUNT 0x182C +#define VDEC_E_HSCALE_CTRL 0x1830 +#define VDEC_E_VSCALE_CTRL 0x1834 +#define VDEC_E_MAN_VGA_CTRL 0x1838 +#define VDEC_E_MAN_AGC_CTRL 0x183C +#define VDEC_E_DFE_CTRL1 0x1840 +#define VDEC_E_DFE_CTRL2 0x1844 +#define VDEC_E_DFE_CTRL3 0x1848 +#define VDEC_E_PLL_CTRL 0x184C +#define VDEC_E_PLL_CTRL_FAST 0x1850 +#define VDEC_E_HTL_CTRL 0x1854 +#define VDEC_E_SRC_CFG 0x1858 +#define VDEC_E_SC_STEP_SIZE 0x185C +#define VDEC_E_SC_CONVERGE_CTRL 0x1860 +#define VDEC_E_SC_LOOP_CTRL 0x1864 +#define VDEC_E_COMB_2D_HFS_CFG 0x1868 +#define VDEC_E_COMB_2D_HFD_CFG 0x186C +#define VDEC_E_COMB_2D_LF_CFG 0x1870 +#define VDEC_E_COMB_2D_BLEND 0x1874 +#define VDEC_E_COMB_MISC_CTRL 0x1878 +#define VDEC_E_COMB_FLAT_THRESH_CTRL 0x187C +#define VDEC_E_COMB_TEST 0x1880 +#define VDEC_E_BP_MISC_CTRL 0x1884 +#define VDEC_E_VCR_DET_CTRL 0x1888 +#define VDEC_E_NOISE_DET_CTRL 0x188C +#define VDEC_E_COMB_FLAT_NOISE_CTRL 0x1890 +#define VDEC_E_VERSION 0x19F8 +#define VDEC_E_SOFT_RST_CTRL 0x19FC + +// Video Decoder F Registers +#define VDEC_F_MODE_CTRL 0x1A00 +#define VDEC_F_OUT_CTRL1 0x1A04 +#define VDEC_F_OUT_CTRL_NS 0x1A08 +#define VDEC_F_GEN_STAT 0x1A0C +#define VDEC_F_INT_STAT_MASK 0x1A10 +#define VDEC_F_LUMA_CTRL 0x1A14 +#define VDEC_F_CHROMA_CTRL 0x1A18 +#define VDEC_F_CRUSH_CTRL 0x1A1C +#define VDEC_F_HORIZ_TIM_CTRL 0x1A20 +#define VDEC_F_VERT_TIM_CTRL 0x1A24 +#define VDEC_F_MISC_TIM_CTRL 0x1A28 +#define VDEC_F_FIELD_COUNT 0x1A2C +#define VDEC_F_HSCALE_CTRL 0x1A30 +#define VDEC_F_VSCALE_CTRL 0x1A34 +#define VDEC_F_MAN_VGA_CTRL 0x1A38 +#define VDEC_F_MAN_AGC_CTRL 0x1A3C +#define VDEC_F_DFE_CTRL1 0x1A40 +#define VDEC_F_DFE_CTRL2 0x1A44 +#define VDEC_F_DFE_CTRL3 0x1A48 +#define VDEC_F_PLL_CTRL 0x1A4C +#define VDEC_F_PLL_CTRL_FAST 0x1A50 +#define VDEC_F_HTL_CTRL 0x1A54 +#define VDEC_F_SRC_CFG 0x1A58 +#define VDEC_F_SC_STEP_SIZE 0x1A5C +#define VDEC_F_SC_CONVERGE_CTRL 0x1A60 +#define VDEC_F_SC_LOOP_CTRL 0x1A64 +#define VDEC_F_COMB_2D_HFS_CFG 0x1A68 +#define VDEC_F_COMB_2D_HFD_CFG 0x1A6C +#define VDEC_F_COMB_2D_LF_CFG 0x1A70 +#define VDEC_F_COMB_2D_BLEND 0x1A74 +#define VDEC_F_COMB_MISC_CTRL 0x1A78 +#define VDEC_F_COMB_FLAT_THRESH_CTRL 0x1A7C +#define VDEC_F_COMB_TEST 0x1A80 +#define VDEC_F_BP_MISC_CTRL 0x1A84 +#define VDEC_F_VCR_DET_CTRL 0x1A88 +#define VDEC_F_NOISE_DET_CTRL 0x1A8C +#define VDEC_F_COMB_FLAT_NOISE_CTRL 0x1A90 +#define VDEC_F_VERSION 0x1BF8 +#define VDEC_F_SOFT_RST_CTRL 0x1BFC + +// Video Decoder G Registers +#define VDEC_G_MODE_CTRL 0x1C00 +#define VDEC_G_OUT_CTRL1 0x1C04 +#define VDEC_G_OUT_CTRL_NS 0x1C08 +#define VDEC_G_GEN_STAT 0x1C0C +#define VDEC_G_INT_STAT_MASK 0x1C10 +#define VDEC_G_LUMA_CTRL 0x1C14 +#define VDEC_G_CHROMA_CTRL 0x1C18 +#define VDEC_G_CRUSH_CTRL 0x1C1C +#define VDEC_G_HORIZ_TIM_CTRL 0x1C20 +#define VDEC_G_VERT_TIM_CTRL 0x1C24 +#define VDEC_G_MISC_TIM_CTRL 0x1C28 +#define VDEC_G_FIELD_COUNT 0x1C2C +#define VDEC_G_HSCALE_CTRL 0x1C30 +#define VDEC_G_VSCALE_CTRL 0x1C34 +#define VDEC_G_MAN_VGA_CTRL 0x1C38 +#define VDEC_G_MAN_AGC_CTRL 0x1C3C +#define VDEC_G_DFE_CTRL1 0x1C40 +#define VDEC_G_DFE_CTRL2 0x1C44 +#define VDEC_G_DFE_CTRL3 0x1C48 +#define VDEC_G_PLL_CTRL 0x1C4C +#define VDEC_G_PLL_CTRL_FAST 0x1C50 +#define VDEC_G_HTL_CTRL 0x1C54 +#define VDEC_G_SRC_CFG 0x1C58 +#define VDEC_G_SC_STEP_SIZE 0x1C5C +#define VDEC_G_SC_CONVERGE_CTRL 0x1C60 +#define VDEC_G_SC_LOOP_CTRL 0x1C64 +#define VDEC_G_COMB_2D_HFS_CFG 0x1C68 +#define VDEC_G_COMB_2D_HFD_CFG 0x1C6C +#define VDEC_G_COMB_2D_LF_CFG 0x1C70 +#define VDEC_G_COMB_2D_BLEND 0x1C74 +#define VDEC_G_COMB_MISC_CTRL 0x1C78 +#define VDEC_G_COMB_FLAT_THRESH_CTRL 0x1C7C +#define VDEC_G_COMB_TEST 0x1C80 +#define VDEC_G_BP_MISC_CTRL 0x1C84 +#define VDEC_G_VCR_DET_CTRL 0x1C88 +#define VDEC_G_NOISE_DET_CTRL 0x1C8C +#define VDEC_G_COMB_FLAT_NOISE_CTRL 0x1C90 +#define VDEC_G_VERSION 0x1DF8 +#define VDEC_G_SOFT_RST_CTRL 0x1DFC + +// Video Decoder H Registers +#define VDEC_H_MODE_CTRL 0x1E00 +#define VDEC_H_OUT_CTRL1 0x1E04 +#define VDEC_H_OUT_CTRL_NS 0x1E08 +#define VDEC_H_GEN_STAT 0x1E0C +#define VDEC_H_INT_STAT_MASK 0x1E1E +#define VDEC_H_LUMA_CTRL 0x1E14 +#define VDEC_H_CHROMA_CTRL 0x1E18 +#define VDEC_H_CRUSH_CTRL 0x1E1C +#define VDEC_H_HORIZ_TIM_CTRL 0x1E20 +#define VDEC_H_VERT_TIM_CTRL 0x1E24 +#define VDEC_H_MISC_TIM_CTRL 0x1E28 +#define VDEC_H_FIELD_COUNT 0x1E2C +#define VDEC_H_HSCALE_CTRL 0x1E30 +#define VDEC_H_VSCALE_CTRL 0x1E34 +#define VDEC_H_MAN_VGA_CTRL 0x1E38 +#define VDEC_H_MAN_AGC_CTRL 0x1E3C +#define VDEC_H_DFE_CTRL1 0x1E40 +#define VDEC_H_DFE_CTRL2 0x1E44 +#define VDEC_H_DFE_CTRL3 0x1E48 +#define VDEC_H_PLL_CTRL 0x1E4C +#define VDEC_H_PLL_CTRL_FAST 0x1E50 +#define VDEC_H_HTL_CTRL 0x1E54 +#define VDEC_H_SRC_CFG 0x1E58 +#define VDEC_H_SC_STEP_SIZE 0x1E5C +#define VDEC_H_SC_CONVERGE_CTRL 0x1E60 +#define VDEC_H_SC_LOOP_CTRL 0x1E64 +#define VDEC_H_COMB_2D_HFS_CFG 0x1E68 +#define VDEC_H_COMB_2D_HFD_CFG 0x1E6C +#define VDEC_H_COMB_2D_LF_CFG 0x1E70 +#define VDEC_H_COMB_2D_BLEND 0x1E74 +#define VDEC_H_COMB_MISC_CTRL 0x1E78 +#define VDEC_H_COMB_FLAT_THRESH_CTRL 0x1E7C +#define VDEC_H_COMB_TEST 0x1E80 +#define VDEC_H_BP_MISC_CTRL 0x1E84 +#define VDEC_H_VCR_DET_CTRL 0x1E88 +#define VDEC_H_NOISE_DET_CTRL 0x1E8C +#define VDEC_H_COMB_FLAT_NOISE_CTRL 0x1E90 +#define VDEC_H_VERSION 0x1FF8 +#define VDEC_H_SOFT_RST_CTRL 0x1FFC + +//***************************************************************************** +// LUMA_CTRL register fields +#define VDEC_A_BRITE_CTRL 0x1014 +#define VDEC_A_CNTRST_CTRL 0x1015 +#define VDEC_A_PEAK_SEL 0x1016 + +//***************************************************************************** +// CHROMA_CTRL register fields +#define VDEC_A_USAT_CTRL 0x1018 +#define VDEC_A_VSAT_CTRL 0x1019 +#define VDEC_A_HUE_CTRL 0x101A + +#endif diff --git a/drivers/staging/cx25821/cx25821-medusa-video.c b/drivers/staging/cx25821/cx25821-medusa-video.c new file mode 100644 index 000000000000..e4df8134f059 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-medusa-video.c @@ -0,0 +1,869 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821.h" +#include "cx25821-medusa-video.h" +#include "cx25821-biffuncs.h" + +///////////////////////////////////////////////////////////////////////////////////////// +//medusa_enable_bluefield_output() +// +// Enable the generation of blue filed output if no video +// +static void medusa_enable_bluefield_output(struct cx25821_dev *dev, int channel, + int enable) +{ + int ret_val = 1; + u32 value = 0; + u32 tmp = 0; + int out_ctrl = OUT_CTRL1; + int out_ctrl_ns = OUT_CTRL_NS; + + switch (channel) { + default: + case VDEC_A: + break; + case VDEC_B: + out_ctrl = VDEC_B_OUT_CTRL1; + out_ctrl_ns = VDEC_B_OUT_CTRL_NS; + break; + case VDEC_C: + out_ctrl = VDEC_C_OUT_CTRL1; + out_ctrl_ns = VDEC_C_OUT_CTRL_NS; + break; + case VDEC_D: + out_ctrl = VDEC_D_OUT_CTRL1; + out_ctrl_ns = VDEC_D_OUT_CTRL_NS; + break; + case VDEC_E: + out_ctrl = VDEC_E_OUT_CTRL1; + out_ctrl_ns = VDEC_E_OUT_CTRL_NS; + return; + case VDEC_F: + out_ctrl = VDEC_F_OUT_CTRL1; + out_ctrl_ns = VDEC_F_OUT_CTRL_NS; + return; + case VDEC_G: + out_ctrl = VDEC_G_OUT_CTRL1; + out_ctrl_ns = VDEC_G_OUT_CTRL_NS; + return; + case VDEC_H: + out_ctrl = VDEC_H_OUT_CTRL1; + out_ctrl_ns = VDEC_H_OUT_CTRL_NS; + return; + } + + value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); + value &= 0xFFFFFF7F; // clear BLUE_FIELD_EN + if (enable) + value |= 0x00000080; // set BLUE_FIELD_EN + ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); + + value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); + value &= 0xFFFFFF7F; + if (enable) + value |= 0x00000080; // set BLUE_FIELD_EN + ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); +} + +static int medusa_initialize_ntsc(struct cx25821_dev *dev) +{ + int ret_val = 0; + int i = 0; + u32 value = 0; + u32 tmp = 0; + + mutex_lock(&dev->lock); + + for (i = 0; i < MAX_DECODERS; i++) { + // set video format NTSC-M + value = + cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i), + &tmp); + value &= 0xFFFFFFF0; + value |= 0x10001; // enable the fast locking mode bit[16] + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i), + value); + + // resolution NTSC 720x480 + value = + cx25821_i2c_read(&dev->i2c_bus[0], + HORIZ_TIM_CTRL + (0x200 * i), &tmp); + value &= 0x00C00C00; + value |= 0x612D0074; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + HORIZ_TIM_CTRL + (0x200 * i), value); + + value = + cx25821_i2c_read(&dev->i2c_bus[0], + VERT_TIM_CTRL + (0x200 * i), &tmp); + value &= 0x00C00C00; + value |= 0x1C1E001A; // vblank_cnt + 2 to get camera ID + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + VERT_TIM_CTRL + (0x200 * i), value); + + // chroma subcarrier step size + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + SC_STEP_SIZE + (0x200 * i), 0x43E00000); + + // enable VIP optional active + value = + cx25821_i2c_read(&dev->i2c_bus[0], + OUT_CTRL_NS + (0x200 * i), &tmp); + value &= 0xFFFBFFFF; + value |= 0x00040000; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + OUT_CTRL_NS + (0x200 * i), value); + + // enable VIP optional active (VIP_OPT_AL) for direct output. + value = + cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i), + &tmp); + value &= 0xFFFBFFFF; + value |= 0x00040000; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i), + value); + + // clear VPRES_VERT_EN bit, fixes the chroma run away problem + // when the input switching rate < 16 fields + // + value = + cx25821_i2c_read(&dev->i2c_bus[0], + MISC_TIM_CTRL + (0x200 * i), &tmp); + value = setBitAtPos(value, 14); // disable special play detection + value = clearBitAtPos(value, 15); + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + MISC_TIM_CTRL + (0x200 * i), value); + + // set vbi_gate_en to 0 + value = + cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i), + &tmp); + value = clearBitAtPos(value, 29); + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i), + value); + + // Enable the generation of blue field output if no video + medusa_enable_bluefield_output(dev, i, 1); + } + + for (i = 0; i < MAX_ENCODERS; i++) { + // NTSC hclock + value = + cx25821_i2c_read(&dev->i2c_bus[0], + DENC_A_REG_1 + (0x100 * i), &tmp); + value &= 0xF000FC00; + value |= 0x06B402D0; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + DENC_A_REG_1 + (0x100 * i), value); + + // burst begin and burst end + value = + cx25821_i2c_read(&dev->i2c_bus[0], + DENC_A_REG_2 + (0x100 * i), &tmp); + value &= 0xFF000000; + value |= 0x007E9054; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + DENC_A_REG_2 + (0x100 * i), value); + + value = + cx25821_i2c_read(&dev->i2c_bus[0], + DENC_A_REG_3 + (0x100 * i), &tmp); + value &= 0xFC00FE00; + value |= 0x00EC00F0; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + DENC_A_REG_3 + (0x100 * i), value); + + // set NTSC vblank, no phase alternation, 7.5 IRE pedestal + value = + cx25821_i2c_read(&dev->i2c_bus[0], + DENC_A_REG_4 + (0x100 * i), &tmp); + value &= 0x00FCFFFF; + value |= 0x13020000; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + DENC_A_REG_4 + (0x100 * i), value); + + value = + cx25821_i2c_read(&dev->i2c_bus[0], + DENC_A_REG_5 + (0x100 * i), &tmp); + value &= 0xFFFF0000; + value |= 0x0000E575; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + DENC_A_REG_5 + (0x100 * i), value); + + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + DENC_A_REG_6 + (0x100 * i), 0x009A89C1); + + // Subcarrier Increment + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + DENC_A_REG_7 + (0x100 * i), 0x21F07C1F); + } + + //set picture resolutions + ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0); //0 - 720 + ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0); //0 - 480 + + // set Bypass input format to NTSC 525 lines + value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); + value |= 0x00080200; + ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value); + + mutex_unlock(&dev->lock); + + return ret_val; +} + +static int medusa_PALCombInit(struct cx25821_dev *dev, int dec) +{ + int ret_val = -1; + u32 value = 0, tmp = 0; + + // Setup for 2D threshold + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_HFS_CFG + (0x200 * dec), + 0x20002861); + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_HFD_CFG + (0x200 * dec), + 0x20002861); + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_LF_CFG + (0x200 * dec), + 0x200A1023); + + // Setup flat chroma and luma thresholds + value = + cx25821_i2c_read(&dev->i2c_bus[0], + COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp); + value &= 0x06230000; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + COMB_FLAT_THRESH_CTRL + (0x200 * dec), value); + + // set comb 2D blend + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_BLEND + (0x200 * dec), + 0x210F0F0F); + + // COMB MISC CONTROL + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], COMB_MISC_CTRL + (0x200 * dec), + 0x41120A7F); + + return ret_val; +} + +static int medusa_initialize_pal(struct cx25821_dev *dev) +{ + int ret_val = 0; + int i = 0; + u32 value = 0; + u32 tmp = 0; + + mutex_lock(&dev->lock); + + for (i = 0; i < MAX_DECODERS; i++) { + // set video format PAL-BDGHI + value = + cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i), + &tmp); + value &= 0xFFFFFFF0; + value |= 0x10004; // enable the fast locking mode bit[16] + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i), + value); + + // resolution PAL 720x576 + value = + cx25821_i2c_read(&dev->i2c_bus[0], + HORIZ_TIM_CTRL + (0x200 * i), &tmp); + value &= 0x00C00C00; + value |= 0x632D007D; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + HORIZ_TIM_CTRL + (0x200 * i), value); + + // vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24 + value = + cx25821_i2c_read(&dev->i2c_bus[0], + VERT_TIM_CTRL + (0x200 * i), &tmp); + value &= 0x00C00C00; + value |= 0x28240026; // vblank_cnt + 2 to get camera ID + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + VERT_TIM_CTRL + (0x200 * i), value); + + // chroma subcarrier step size + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + SC_STEP_SIZE + (0x200 * i), 0x5411E2D0); + + // enable VIP optional active + value = + cx25821_i2c_read(&dev->i2c_bus[0], + OUT_CTRL_NS + (0x200 * i), &tmp); + value &= 0xFFFBFFFF; + value |= 0x00040000; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + OUT_CTRL_NS + (0x200 * i), value); + + // enable VIP optional active (VIP_OPT_AL) for direct output. + value = + cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i), + &tmp); + value &= 0xFFFBFFFF; + value |= 0x00040000; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i), + value); + + // clear VPRES_VERT_EN bit, fixes the chroma run away problem + // when the input switching rate < 16 fields + value = + cx25821_i2c_read(&dev->i2c_bus[0], + MISC_TIM_CTRL + (0x200 * i), &tmp); + value = setBitAtPos(value, 14); // disable special play detection + value = clearBitAtPos(value, 15); + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + MISC_TIM_CTRL + (0x200 * i), value); + + // set vbi_gate_en to 0 + value = + cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i), + &tmp); + value = clearBitAtPos(value, 29); + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i), + value); + + medusa_PALCombInit(dev, i); + + // Enable the generation of blue field output if no video + medusa_enable_bluefield_output(dev, i, 1); + } + + for (i = 0; i < MAX_ENCODERS; i++) { + // PAL hclock + value = + cx25821_i2c_read(&dev->i2c_bus[0], + DENC_A_REG_1 + (0x100 * i), &tmp); + value &= 0xF000FC00; + value |= 0x06C002D0; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + DENC_A_REG_1 + (0x100 * i), value); + + // burst begin and burst end + value = + cx25821_i2c_read(&dev->i2c_bus[0], + DENC_A_REG_2 + (0x100 * i), &tmp); + value &= 0xFF000000; + value |= 0x007E9754; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + DENC_A_REG_2 + (0x100 * i), value); + + // hblank and vactive + value = + cx25821_i2c_read(&dev->i2c_bus[0], + DENC_A_REG_3 + (0x100 * i), &tmp); + value &= 0xFC00FE00; + value |= 0x00FC0120; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + DENC_A_REG_3 + (0x100 * i), value); + + // set PAL vblank, phase alternation, 0 IRE pedestal + value = + cx25821_i2c_read(&dev->i2c_bus[0], + DENC_A_REG_4 + (0x100 * i), &tmp); + value &= 0x00FCFFFF; + value |= 0x14010000; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + DENC_A_REG_4 + (0x100 * i), value); + + value = + cx25821_i2c_read(&dev->i2c_bus[0], + DENC_A_REG_5 + (0x100 * i), &tmp); + value &= 0xFFFF0000; + value |= 0x0000F078; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + DENC_A_REG_5 + (0x100 * i), value); + + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + DENC_A_REG_6 + (0x100 * i), 0x00A493CF); + + // Subcarrier Increment + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + DENC_A_REG_7 + (0x100 * i), 0x2A098ACB); + } + + //set picture resolutions + ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0); //0 - 720 + ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0); //0 - 576 + + // set Bypass input format to PAL 625 lines + value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); + value &= 0xFFF7FDFF; + ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value); + + mutex_unlock(&dev->lock); + + return ret_val; +} + +int medusa_set_videostandard(struct cx25821_dev *dev) +{ + int status = STATUS_SUCCESS; + u32 value = 0, tmp = 0; + + if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) { + status = medusa_initialize_pal(dev); + } else { + status = medusa_initialize_ntsc(dev); + } + + // Enable DENC_A output + value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4, &tmp); + value = setBitAtPos(value, 4); + status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4, value); + + // Enable DENC_B output + value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_B_REG_4, &tmp); + value = setBitAtPos(value, 4); + status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_B_REG_4, value); + + return status; +} + +void medusa_set_resolution(struct cx25821_dev *dev, int width, + int decoder_select) +{ + int decoder = 0; + int decoder_count = 0; + int ret_val = 0; + u32 hscale = 0x0; + u32 vscale = 0x0; + const int MAX_WIDTH = 720; + + mutex_lock(&dev->lock); + + // validate the width - cannot be negative + if (width > MAX_WIDTH) { + printk + ("cx25821 %s() : width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH \n", + __func__, width, MAX_WIDTH); + width = MAX_WIDTH; + } + + if (decoder_select <= 7 && decoder_select >= 0) { + decoder = decoder_select; + decoder_count = decoder_select + 1; + } else { + decoder = 0; + decoder_count = _num_decoders; + } + + switch (width) { + case 320: + hscale = 0x13E34B; + vscale = 0x0; + break; + + case 352: + hscale = 0x10A273; + vscale = 0x0; + break; + + case 176: + hscale = 0x3115B2; + vscale = 0x1E00; + break; + + case 160: + hscale = 0x378D84; + vscale = 0x1E00; + break; + + default: //720 + hscale = 0x0; + vscale = 0x0; + break; + } + + for (; decoder < decoder_count; decoder++) { + // write scaling values for each decoder + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + HSCALE_CTRL + (0x200 * decoder), hscale); + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], + VSCALE_CTRL + (0x200 * decoder), vscale); + } + + mutex_unlock(&dev->lock); +} + +static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder, + int duration) +{ + int ret_val = 0; + u32 fld_cnt = 0; + u32 tmp = 0; + u32 disp_cnt_reg = DISP_AB_CNT; + + mutex_lock(&dev->lock); + + // no support + if (decoder < VDEC_A && decoder > VDEC_H) { + mutex_unlock(&dev->lock); + return; + } + + switch (decoder) { + default: + break; + case VDEC_C: + case VDEC_D: + disp_cnt_reg = DISP_CD_CNT; + break; + case VDEC_E: + case VDEC_F: + disp_cnt_reg = DISP_EF_CNT; + break; + case VDEC_G: + case VDEC_H: + disp_cnt_reg = DISP_GH_CNT; + break; + } + + _display_field_cnt[decoder] = duration; + + // update hardware + fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp); + + if (!(decoder % 2)) // EVEN decoder + { + fld_cnt &= 0xFFFF0000; + fld_cnt |= duration; + } else { + fld_cnt &= 0x0000FFFF; + fld_cnt |= ((u32) duration) << 16; + } + + ret_val = cx25821_i2c_write(&dev->i2c_bus[0], disp_cnt_reg, fld_cnt); + + mutex_unlock(&dev->lock); +} + +///////////////////////////////////////////////////////////////////////////////////////// +// Map to Medusa register setting +static int mapM(int srcMin, + int srcMax, int srcVal, int dstMin, int dstMax, int *dstVal) +{ + int numerator; + int denominator; + int quotient; + + if ((srcMin == srcMax) || (srcVal < srcMin) || (srcVal > srcMax)) { + return -1; + } + // This is the overall expression used: + // *dstVal = (srcVal - srcMin)*(dstMax - dstMin) / (srcMax - srcMin) + dstMin; + // but we need to account for rounding so below we use the modulus + // operator to find the remainder and increment if necessary. + numerator = (srcVal - srcMin) * (dstMax - dstMin); + denominator = srcMax - srcMin; + quotient = numerator / denominator; + + if (2 * (numerator % denominator) >= denominator) { + quotient++; + } + + *dstVal = quotient + dstMin; + + return 0; +} + +static unsigned long convert_to_twos(long numeric, unsigned long bits_len) +{ + unsigned char temp; + + if (numeric >= 0) + return numeric; + else { + temp = ~(abs(numeric) & 0xFF); + temp += 1; + return temp; + } +} + +///////////////////////////////////////////////////////////////////////////////////////// +int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder) +{ + int ret_val = 0; + int value = 0; + u32 val = 0, tmp = 0; + + mutex_lock(&dev->lock); + if ((brightness > VIDEO_PROCAMP_MAX) + || (brightness < VIDEO_PROCAMP_MIN)) { + mutex_unlock(&dev->lock); + return -1; + } + ret_val = + mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, brightness, + SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value); + value = convert_to_twos(value, 8); + val = + cx25821_i2c_read(&dev->i2c_bus[0], + VDEC_A_BRITE_CTRL + (0x200 * decoder), &tmp); + val &= 0xFFFFFF00; + ret_val |= + cx25821_i2c_write(&dev->i2c_bus[0], + VDEC_A_BRITE_CTRL + (0x200 * decoder), + val | value); + mutex_unlock(&dev->lock); + return ret_val; +} + +///////////////////////////////////////////////////////////////////////////////////////// +int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder) +{ + int ret_val = 0; + int value = 0; + u32 val = 0, tmp = 0; + + mutex_lock(&dev->lock); + + if ((contrast > VIDEO_PROCAMP_MAX) || (contrast < VIDEO_PROCAMP_MIN)) { + mutex_unlock(&dev->lock); + return -1; + } + + ret_val = + mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, contrast, + UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value); + val = + cx25821_i2c_read(&dev->i2c_bus[0], + VDEC_A_CNTRST_CTRL + (0x200 * decoder), &tmp); + val &= 0xFFFFFF00; + ret_val |= + cx25821_i2c_write(&dev->i2c_bus[0], + VDEC_A_CNTRST_CTRL + (0x200 * decoder), + val | value); + + mutex_unlock(&dev->lock); + return ret_val; +} + +///////////////////////////////////////////////////////////////////////////////////////// +int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder) +{ + int ret_val = 0; + int value = 0; + u32 val = 0, tmp = 0; + + mutex_lock(&dev->lock); + + if ((hue > VIDEO_PROCAMP_MAX) || (hue < VIDEO_PROCAMP_MIN)) { + mutex_unlock(&dev->lock); + return -1; + } + + ret_val = + mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, hue, SIGNED_BYTE_MIN, + SIGNED_BYTE_MAX, &value); + + value = convert_to_twos(value, 8); + val = + cx25821_i2c_read(&dev->i2c_bus[0], + VDEC_A_HUE_CTRL + (0x200 * decoder), &tmp); + val &= 0xFFFFFF00; + + ret_val |= + cx25821_i2c_write(&dev->i2c_bus[0], + VDEC_A_HUE_CTRL + (0x200 * decoder), val | value); + + mutex_unlock(&dev->lock); + return ret_val; +} + +///////////////////////////////////////////////////////////////////////////////////////// +int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder) +{ + int ret_val = 0; + int value = 0; + u32 val = 0, tmp = 0; + + mutex_lock(&dev->lock); + + if ((saturation > VIDEO_PROCAMP_MAX) + || (saturation < VIDEO_PROCAMP_MIN)) { + mutex_unlock(&dev->lock); + return -1; + } + + ret_val = + mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, saturation, + UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value); + + val = + cx25821_i2c_read(&dev->i2c_bus[0], + VDEC_A_USAT_CTRL + (0x200 * decoder), &tmp); + val &= 0xFFFFFF00; + ret_val |= + cx25821_i2c_write(&dev->i2c_bus[0], + VDEC_A_USAT_CTRL + (0x200 * decoder), + val | value); + + val = + cx25821_i2c_read(&dev->i2c_bus[0], + VDEC_A_VSAT_CTRL + (0x200 * decoder), &tmp); + val &= 0xFFFFFF00; + ret_val |= + cx25821_i2c_write(&dev->i2c_bus[0], + VDEC_A_VSAT_CTRL + (0x200 * decoder), + val | value); + + mutex_unlock(&dev->lock); + return ret_val; +} + +///////////////////////////////////////////////////////////////////////////////////////// +// Program the display sequence and monitor output. +// +int medusa_video_init(struct cx25821_dev *dev) +{ + u32 value = 0, tmp = 0; + int ret_val = 0; + int i = 0; + + mutex_lock(&dev->lock); + + _num_decoders = dev->_max_num_decoders; + + // disable Auto source selection on all video decoders + value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp); + value &= 0xFFFFF0FF; + ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value); + + if (ret_val < 0) { + mutex_unlock(&dev->lock); + return -EINVAL; + } + // Turn off Master source switch enable + value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp); + value &= 0xFFFFFFDF; + ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value); + + if (ret_val < 0) { + mutex_unlock(&dev->lock); + return -EINVAL; + } + + mutex_unlock(&dev->lock); + + for (i = 0; i < _num_decoders; i++) { + medusa_set_decoderduration(dev, i, _display_field_cnt[i]); + } + + mutex_lock(&dev->lock); + + // Select monitor as DENC A input, power up the DAC + value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp); + value &= 0xFF70FF70; + value |= 0x00090008; // set en_active + ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_AB_CTRL, value); + + if (ret_val < 0) { + mutex_unlock(&dev->lock); + return -EINVAL; + } + // enable input is VIP/656 + value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); + value |= 0x00040100; // enable VIP + ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value); + + if (ret_val < 0) { + mutex_unlock(&dev->lock); + return -EINVAL; + } + // select AFE clock to output mode + value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp); + value &= 0x83FFFFFF; + ret_val = + cx25821_i2c_write(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, + value | 0x10000000); + + if (ret_val < 0) { + mutex_unlock(&dev->lock); + return -EINVAL; + } + // Turn on all of the data out and control output pins. + value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp); + value &= 0xFEF0FE00; + if (_num_decoders == MAX_DECODERS) { + // Note: The octal board does not support control pins(bit16-19). + // These bits are ignored in the octal board. + value |= 0x010001F8; // disable VDEC A-C port, default to Mobilygen Interface + } else { + value |= 0x010F0108; // disable VDEC A-C port, default to Mobilygen Interface + } + + value |= 7; + ret_val = cx25821_i2c_write(&dev->i2c_bus[0], PIN_OE_CTRL, value); + if (ret_val < 0) { + mutex_unlock(&dev->lock); + return -EINVAL; + } + + mutex_unlock(&dev->lock); + + ret_val = medusa_set_videostandard(dev); + + if (ret_val < 0) { + mutex_unlock(&dev->lock); + return -EINVAL; + } + + return 1; +} diff --git a/drivers/staging/cx25821/cx25821-medusa-video.h b/drivers/staging/cx25821/cx25821-medusa-video.h new file mode 100644 index 000000000000..2fab4b2f251c --- /dev/null +++ b/drivers/staging/cx25821/cx25821-medusa-video.h @@ -0,0 +1,49 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _MEDUSA_VIDEO_H +#define _MEDUSA_VIDEO_H + +#include "cx25821-medusa-defines.h" + +// Color control constants +#define VIDEO_PROCAMP_MIN 0 +#define VIDEO_PROCAMP_MAX 10000 +#define UNSIGNED_BYTE_MIN 0 +#define UNSIGNED_BYTE_MAX 0xFF +#define SIGNED_BYTE_MIN -128 +#define SIGNED_BYTE_MAX 127 + +// Default video color settings +#define SHARPNESS_DEFAULT 50 +#define SATURATION_DEFAULT 5000 +#define BRIGHTNESS_DEFAULT 6200 +#define CONTRAST_DEFAULT 5000 +#define HUE_DEFAULT 5000 + +unsigned short _num_decoders; +unsigned short _num_cameras; + +unsigned int _video_standard; +int _display_field_cnt[MAX_DECODERS]; + +#endif diff --git a/drivers/staging/cx25821/cx25821-reg.h b/drivers/staging/cx25821/cx25821-reg.h new file mode 100644 index 000000000000..7241e7ee3fd3 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-reg.h @@ -0,0 +1,1592 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CX25821_REGISTERS__ +#define __CX25821_REGISTERS__ + +/* Risc Instructions */ +#define RISC_CNT_INC 0x00010000 +#define RISC_CNT_RESET 0x00030000 +#define RISC_IRQ1 0x01000000 +#define RISC_IRQ2 0x02000000 +#define RISC_EOL 0x04000000 +#define RISC_SOL 0x08000000 +#define RISC_WRITE 0x10000000 +#define RISC_SKIP 0x20000000 +#define RISC_JUMP 0x70000000 +#define RISC_SYNC 0x80000000 +#define RISC_RESYNC 0x80008000 +#define RISC_READ 0x90000000 +#define RISC_WRITERM 0xB0000000 +#define RISC_WRITECM 0xC0000000 +#define RISC_WRITECR 0xD0000000 +#define RISC_WRITEC 0x50000000 +#define RISC_READC 0xA0000000 + +#define RISC_SYNC_ODD 0x00000000 +#define RISC_SYNC_EVEN 0x00000200 +#define RISC_SYNC_ODD_VBI 0x00000006 +#define RISC_SYNC_EVEN_VBI 0x00000207 +#define RISC_NOOP 0xF0000000 + +//***************************************************************************** +// ASB SRAM +//***************************************************************************** +#define TX_SRAM 0x000000 // Transmit SRAM + +//***************************************************************************** +#define RX_RAM 0x010000 // Receive SRAM + +//***************************************************************************** +// Application Layer (AL) +//***************************************************************************** +#define DEV_CNTRL2 0x040000 // Device control +#define FLD_RUN_RISC 0x00000020 + +//***************************************************************************** +#define PCI_INT_MSK 0x040010 // PCI interrupt mask +#define PCI_INT_STAT 0x040014 // PCI interrupt status +#define PCI_INT_MSTAT 0x040018 // PCI interrupt masked status +#define FLD_HAMMERHEAD_INT (1 << 27) +#define FLD_UART_INT (1 << 26) +#define FLD_IRQN_INT (1 << 25) +#define FLD_TM_INT (1 << 28) +#define FLD_I2C_3_RACK (1 << 27) +#define FLD_I2C_3_INT (1 << 26) +#define FLD_I2C_2_RACK (1 << 25) +#define FLD_I2C_2_INT (1 << 24) +#define FLD_I2C_1_RACK (1 << 23) +#define FLD_I2C_1_INT (1 << 22) + +#define FLD_APB_DMA_BERR_INT (1 << 21) +#define FLD_AL_WR_BERR_INT (1 << 20) +#define FLD_AL_RD_BERR_INT (1 << 19) +#define FLD_RISC_WR_BERR_INT (1 << 18) +#define FLD_RISC_RD_BERR_INT (1 << 17) + +#define FLD_VID_I_INT (1 << 8) +#define FLD_VID_H_INT (1 << 7) +#define FLD_VID_G_INT (1 << 6) +#define FLD_VID_F_INT (1 << 5) +#define FLD_VID_E_INT (1 << 4) +#define FLD_VID_D_INT (1 << 3) +#define FLD_VID_C_INT (1 << 2) +#define FLD_VID_B_INT (1 << 1) +#define FLD_VID_A_INT (1 << 0) + +//***************************************************************************** +#define VID_A_INT_MSK 0x040020 // Video A interrupt mask +#define VID_A_INT_STAT 0x040024 // Video A interrupt status +#define VID_A_INT_MSTAT 0x040028 // Video A interrupt masked status +#define VID_A_INT_SSTAT 0x04002C // Video A interrupt set status + +//***************************************************************************** +#define VID_B_INT_MSK 0x040030 // Video B interrupt mask +#define VID_B_INT_STAT 0x040034 // Video B interrupt status +#define VID_B_INT_MSTAT 0x040038 // Video B interrupt masked status +#define VID_B_INT_SSTAT 0x04003C // Video B interrupt set status + +//***************************************************************************** +#define VID_C_INT_MSK 0x040040 // Video C interrupt mask +#define VID_C_INT_STAT 0x040044 // Video C interrupt status +#define VID_C_INT_MSTAT 0x040048 // Video C interrupt masked status +#define VID_C_INT_SSTAT 0x04004C // Video C interrupt set status + +//***************************************************************************** +#define VID_D_INT_MSK 0x040050 // Video D interrupt mask +#define VID_D_INT_STAT 0x040054 // Video D interrupt status +#define VID_D_INT_MSTAT 0x040058 // Video D interrupt masked status +#define VID_D_INT_SSTAT 0x04005C // Video D interrupt set status + +//***************************************************************************** +#define VID_E_INT_MSK 0x040060 // Video E interrupt mask +#define VID_E_INT_STAT 0x040064 // Video E interrupt status +#define VID_E_INT_MSTAT 0x040068 // Video E interrupt masked status +#define VID_E_INT_SSTAT 0x04006C // Video E interrupt set status + +//***************************************************************************** +#define VID_F_INT_MSK 0x040070 // Video F interrupt mask +#define VID_F_INT_STAT 0x040074 // Video F interrupt status +#define VID_F_INT_MSTAT 0x040078 // Video F interrupt masked status +#define VID_F_INT_SSTAT 0x04007C // Video F interrupt set status + +//***************************************************************************** +#define VID_G_INT_MSK 0x040080 // Video G interrupt mask +#define VID_G_INT_STAT 0x040084 // Video G interrupt status +#define VID_G_INT_MSTAT 0x040088 // Video G interrupt masked status +#define VID_G_INT_SSTAT 0x04008C // Video G interrupt set status + +//***************************************************************************** +#define VID_H_INT_MSK 0x040090 // Video H interrupt mask +#define VID_H_INT_STAT 0x040094 // Video H interrupt status +#define VID_H_INT_MSTAT 0x040098 // Video H interrupt masked status +#define VID_H_INT_SSTAT 0x04009C // Video H interrupt set status + +//***************************************************************************** +#define VID_I_INT_MSK 0x0400A0 // Video I interrupt mask +#define VID_I_INT_STAT 0x0400A4 // Video I interrupt status +#define VID_I_INT_MSTAT 0x0400A8 // Video I interrupt masked status +#define VID_I_INT_SSTAT 0x0400AC // Video I interrupt set status + +//***************************************************************************** +#define VID_J_INT_MSK 0x0400B0 // Video J interrupt mask +#define VID_J_INT_STAT 0x0400B4 // Video J interrupt status +#define VID_J_INT_MSTAT 0x0400B8 // Video J interrupt masked status +#define VID_J_INT_SSTAT 0x0400BC // Video J interrupt set status + +#define FLD_VID_SRC_OPC_ERR 0x00020000 +#define FLD_VID_DST_OPC_ERR 0x00010000 +#define FLD_VID_SRC_SYNC 0x00002000 +#define FLD_VID_DST_SYNC 0x00001000 +#define FLD_VID_SRC_UF 0x00000200 +#define FLD_VID_DST_OF 0x00000100 +#define FLD_VID_SRC_RISC2 0x00000020 +#define FLD_VID_DST_RISC2 0x00000010 +#define FLD_VID_SRC_RISC1 0x00000002 +#define FLD_VID_DST_RISC1 0x00000001 +#define FLD_VID_SRC_ERRORS FLD_VID_SRC_OPC_ERR | FLD_VID_SRC_SYNC | FLD_VID_SRC_UF +#define FLD_VID_DST_ERRORS FLD_VID_DST_OPC_ERR | FLD_VID_DST_SYNC | FLD_VID_DST_OF + +//***************************************************************************** +#define AUD_A_INT_MSK 0x0400C0 // Audio Int interrupt mask +#define AUD_A_INT_STAT 0x0400C4 // Audio Int interrupt status +#define AUD_A_INT_MSTAT 0x0400C8 // Audio Int interrupt masked status +#define AUD_A_INT_SSTAT 0x0400CC // Audio Int interrupt set status + +//***************************************************************************** +#define AUD_B_INT_MSK 0x0400D0 // Audio Int interrupt mask +#define AUD_B_INT_STAT 0x0400D4 // Audio Int interrupt status +#define AUD_B_INT_MSTAT 0x0400D8 // Audio Int interrupt masked status +#define AUD_B_INT_SSTAT 0x0400DC // Audio Int interrupt set status + +//***************************************************************************** +#define AUD_C_INT_MSK 0x0400E0 // Audio Int interrupt mask +#define AUD_C_INT_STAT 0x0400E4 // Audio Int interrupt status +#define AUD_C_INT_MSTAT 0x0400E8 // Audio Int interrupt masked status +#define AUD_C_INT_SSTAT 0x0400EC // Audio Int interrupt set status + +//***************************************************************************** +#define AUD_D_INT_MSK 0x0400F0 // Audio Int interrupt mask +#define AUD_D_INT_STAT 0x0400F4 // Audio Int interrupt status +#define AUD_D_INT_MSTAT 0x0400F8 // Audio Int interrupt masked status +#define AUD_D_INT_SSTAT 0x0400FC // Audio Int interrupt set status + +//***************************************************************************** +#define AUD_E_INT_MSK 0x040100 // Audio Int interrupt mask +#define AUD_E_INT_STAT 0x040104 // Audio Int interrupt status +#define AUD_E_INT_MSTAT 0x040108 // Audio Int interrupt masked status +#define AUD_E_INT_SSTAT 0x04010C // Audio Int interrupt set status + +#define FLD_AUD_SRC_OPC_ERR 0x00020000 +#define FLD_AUD_DST_OPC_ERR 0x00010000 +#define FLD_AUD_SRC_SYNC 0x00002000 +#define FLD_AUD_DST_SYNC 0x00001000 +#define FLD_AUD_SRC_OF 0x00000200 +#define FLD_AUD_DST_OF 0x00000100 +#define FLD_AUD_SRC_RISCI2 0x00000020 +#define FLD_AUD_DST_RISCI2 0x00000010 +#define FLD_AUD_SRC_RISCI1 0x00000002 +#define FLD_AUD_DST_RISCI1 0x00000001 + +//***************************************************************************** +#define MBIF_A_INT_MSK 0x040110 // MBIF Int interrupt mask +#define MBIF_A_INT_STAT 0x040114 // MBIF Int interrupt status +#define MBIF_A_INT_MSTAT 0x040118 // MBIF Int interrupt masked status +#define MBIF_A_INT_SSTAT 0x04011C // MBIF Int interrupt set status + +//***************************************************************************** +#define MBIF_B_INT_MSK 0x040120 // MBIF Int interrupt mask +#define MBIF_B_INT_STAT 0x040124 // MBIF Int interrupt status +#define MBIF_B_INT_MSTAT 0x040128 // MBIF Int interrupt masked status +#define MBIF_B_INT_SSTAT 0x04012C // MBIF Int interrupt set status + +#define FLD_MBIF_DST_OPC_ERR 0x00010000 +#define FLD_MBIF_DST_SYNC 0x00001000 +#define FLD_MBIF_DST_OF 0x00000100 +#define FLD_MBIF_DST_RISCI2 0x00000010 +#define FLD_MBIF_DST_RISCI1 0x00000001 + +//***************************************************************************** +#define AUD_EXT_INT_MSK 0x040060 // Audio Ext interrupt mask +#define AUD_EXT_INT_STAT 0x040064 // Audio Ext interrupt status +#define AUD_EXT_INT_MSTAT 0x040068 // Audio Ext interrupt masked status +#define AUD_EXT_INT_SSTAT 0x04006C // Audio Ext interrupt set status +#define FLD_AUD_EXT_OPC_ERR 0x00010000 +#define FLD_AUD_EXT_SYNC 0x00001000 +#define FLD_AUD_EXT_OF 0x00000100 +#define FLD_AUD_EXT_RISCI2 0x00000010 +#define FLD_AUD_EXT_RISCI1 0x00000001 + +//***************************************************************************** +#define GPIO_LO 0x110010 // Lower of GPIO pins [31:0] +#define GPIO_HI 0x110014 // Upper WORD of GPIO pins [47:31] + +#define GPIO_LO_OE 0x110018 // Lower of GPIO output enable [31:0] +#define GPIO_HI_OE 0x11001C // Upper word of GPIO output enable [47:32] + +#define GPIO_LO_INT_MSK 0x11003C // GPIO interrupt mask +#define GPIO_LO_INT_STAT 0x110044 // GPIO interrupt status +#define GPIO_LO_INT_MSTAT 0x11004C // GPIO interrupt masked status +#define GPIO_LO_ISM_SNS 0x110054 // GPIO interrupt sensitivity +#define GPIO_LO_ISM_POL 0x11005C // GPIO interrupt polarity + +#define GPIO_HI_INT_MSK 0x110040 // GPIO interrupt mask +#define GPIO_HI_INT_STAT 0x110048 // GPIO interrupt status +#define GPIO_HI_INT_MSTAT 0x110050 // GPIO interrupt masked status +#define GPIO_HI_ISM_SNS 0x110058 // GPIO interrupt sensitivity +#define GPIO_HI_ISM_POL 0x110060 // GPIO interrupt polarity + +#define FLD_GPIO43_INT (1 << 11) +#define FLD_GPIO42_INT (1 << 10) +#define FLD_GPIO41_INT (1 << 9) +#define FLD_GPIO40_INT (1 << 8) + +#define FLD_GPIO9_INT (1 << 9) +#define FLD_GPIO8_INT (1 << 8) +#define FLD_GPIO7_INT (1 << 7) +#define FLD_GPIO6_INT (1 << 6) +#define FLD_GPIO5_INT (1 << 5) +#define FLD_GPIO4_INT (1 << 4) +#define FLD_GPIO3_INT (1 << 3) +#define FLD_GPIO2_INT (1 << 2) +#define FLD_GPIO1_INT (1 << 1) +#define FLD_GPIO0_INT (1 << 0) + +//***************************************************************************** +#define TC_REQ 0x040090 // Rider PCI Express traFFic class request + +//***************************************************************************** +#define TC_REQ_SET 0x040094 // Rider PCI Express traFFic class request set + +//***************************************************************************** +// Rider +//***************************************************************************** + +// PCI Compatible Header +//***************************************************************************** +#define RDR_CFG0 0x050000 +#define RDR_VENDOR_DEVICE_ID_CFG 0x050000 + +//***************************************************************************** +#define RDR_CFG1 0x050004 + +//***************************************************************************** +#define RDR_CFG2 0x050008 + +//***************************************************************************** +#define RDR_CFG3 0x05000C + +//***************************************************************************** +#define RDR_CFG4 0x050010 + +//***************************************************************************** +#define RDR_CFG5 0x050014 + +//***************************************************************************** +#define RDR_CFG6 0x050018 + +//***************************************************************************** +#define RDR_CFG7 0x05001C + +//***************************************************************************** +#define RDR_CFG8 0x050020 + +//***************************************************************************** +#define RDR_CFG9 0x050024 + +//***************************************************************************** +#define RDR_CFGA 0x050028 + +//***************************************************************************** +#define RDR_CFGB 0x05002C +#define RDR_SUSSYSTEM_ID_CFG 0x05002C + +//***************************************************************************** +#define RDR_CFGC 0x050030 + +//***************************************************************************** +#define RDR_CFGD 0x050034 + +//***************************************************************************** +#define RDR_CFGE 0x050038 + +//***************************************************************************** +#define RDR_CFGF 0x05003C + +//***************************************************************************** +// PCI-Express Capabilities +//***************************************************************************** +#define RDR_PECAP 0x050040 + +//***************************************************************************** +#define RDR_PEDEVCAP 0x050044 + +//***************************************************************************** +#define RDR_PEDEVSC 0x050048 + +//***************************************************************************** +#define RDR_PELINKCAP 0x05004C + +//***************************************************************************** +#define RDR_PELINKSC 0x050050 + +//***************************************************************************** +#define RDR_PMICAP 0x050080 + +//***************************************************************************** +#define RDR_PMCSR 0x050084 + +//***************************************************************************** +#define RDR_VPDCAP 0x050090 + +//***************************************************************************** +#define RDR_VPDDATA 0x050094 + +//***************************************************************************** +#define RDR_MSICAP 0x0500A0 + +//***************************************************************************** +#define RDR_MSIARL 0x0500A4 + +//***************************************************************************** +#define RDR_MSIARU 0x0500A8 + +//***************************************************************************** +#define RDR_MSIDATA 0x0500AC + +//***************************************************************************** +// PCI Express Extended Capabilities +//***************************************************************************** +#define RDR_AERXCAP 0x050100 + +//***************************************************************************** +#define RDR_AERUESTA 0x050104 + +//***************************************************************************** +#define RDR_AERUEMSK 0x050108 + +//***************************************************************************** +#define RDR_AERUESEV 0x05010C + +//***************************************************************************** +#define RDR_AERCESTA 0x050110 + +//***************************************************************************** +#define RDR_AERCEMSK 0x050114 + +//***************************************************************************** +#define RDR_AERCC 0x050118 + +//***************************************************************************** +#define RDR_AERHL0 0x05011C + +//***************************************************************************** +#define RDR_AERHL1 0x050120 + +//***************************************************************************** +#define RDR_AERHL2 0x050124 + +//***************************************************************************** +#define RDR_AERHL3 0x050128 + +//***************************************************************************** +#define RDR_VCXCAP 0x050200 + +//***************************************************************************** +#define RDR_VCCAP1 0x050204 + +//***************************************************************************** +#define RDR_VCCAP2 0x050208 + +//***************************************************************************** +#define RDR_VCSC 0x05020C + +//***************************************************************************** +#define RDR_VCR0_CAP 0x050210 + +//***************************************************************************** +#define RDR_VCR0_CTRL 0x050214 + +//***************************************************************************** +#define RDR_VCR0_STAT 0x050218 + +//***************************************************************************** +#define RDR_VCR1_CAP 0x05021C + +//***************************************************************************** +#define RDR_VCR1_CTRL 0x050220 + +//***************************************************************************** +#define RDR_VCR1_STAT 0x050224 + +//***************************************************************************** +#define RDR_VCR2_CAP 0x050228 + +//***************************************************************************** +#define RDR_VCR2_CTRL 0x05022C + +//***************************************************************************** +#define RDR_VCR2_STAT 0x050230 + +//***************************************************************************** +#define RDR_VCR3_CAP 0x050234 + +//***************************************************************************** +#define RDR_VCR3_CTRL 0x050238 + +//***************************************************************************** +#define RDR_VCR3_STAT 0x05023C + +//***************************************************************************** +#define RDR_VCARB0 0x050240 + +//***************************************************************************** +#define RDR_VCARB1 0x050244 + +//***************************************************************************** +#define RDR_VCARB2 0x050248 + +//***************************************************************************** +#define RDR_VCARB3 0x05024C + +//***************************************************************************** +#define RDR_VCARB4 0x050250 + +//***************************************************************************** +#define RDR_VCARB5 0x050254 + +//***************************************************************************** +#define RDR_VCARB6 0x050258 + +//***************************************************************************** +#define RDR_VCARB7 0x05025C + +//***************************************************************************** +#define RDR_RDRSTAT0 0x050300 + +//***************************************************************************** +#define RDR_RDRSTAT1 0x050304 + +//***************************************************************************** +#define RDR_RDRCTL0 0x050308 + +//***************************************************************************** +#define RDR_RDRCTL1 0x05030C + +//***************************************************************************** +// Transaction Layer Registers +//***************************************************************************** +#define RDR_TLSTAT0 0x050310 + +//***************************************************************************** +#define RDR_TLSTAT1 0x050314 + +//***************************************************************************** +#define RDR_TLCTL0 0x050318 +#define FLD_CFG_UR_CPL_MODE 0x00000040 +#define FLD_CFG_CORR_ERR_QUITE 0x00000020 +#define FLD_CFG_RCB_CK_EN 0x00000010 +#define FLD_CFG_BNDRY_CK_EN 0x00000008 +#define FLD_CFG_BYTE_EN_CK_EN 0x00000004 +#define FLD_CFG_RELAX_ORDER_MSK 0x00000002 +#define FLD_CFG_TAG_ORDER_EN 0x00000001 + +//***************************************************************************** +#define RDR_TLCTL1 0x05031C + +//***************************************************************************** +#define RDR_REQRCAL 0x050320 + +//***************************************************************************** +#define RDR_REQRCAU 0x050324 + +//***************************************************************************** +#define RDR_REQEPA 0x050328 + +//***************************************************************************** +#define RDR_REQCTRL 0x05032C + +//***************************************************************************** +#define RDR_REQSTAT 0x050330 + +//***************************************************************************** +#define RDR_TL_TEST 0x050334 + +//***************************************************************************** +#define RDR_VCR01_CTL 0x050348 + +//***************************************************************************** +#define RDR_VCR23_CTL 0x05034C + +//***************************************************************************** +#define RDR_RX_VCR0_FC 0x050350 + +//***************************************************************************** +#define RDR_RX_VCR1_FC 0x050354 + +//***************************************************************************** +#define RDR_RX_VCR2_FC 0x050358 + +//***************************************************************************** +#define RDR_RX_VCR3_FC 0x05035C + +//***************************************************************************** +// Data Link Layer Registers +//***************************************************************************** +#define RDR_DLLSTAT 0x050360 + +//***************************************************************************** +#define RDR_DLLCTRL 0x050364 + +//***************************************************************************** +#define RDR_REPLAYTO 0x050368 + +//***************************************************************************** +#define RDR_ACKLATTO 0x05036C + +//***************************************************************************** +// MAC Layer Registers +//***************************************************************************** +#define RDR_MACSTAT0 0x050380 + +//***************************************************************************** +#define RDR_MACSTAT1 0x050384 + +//***************************************************************************** +#define RDR_MACCTRL0 0x050388 + +//***************************************************************************** +#define RDR_MACCTRL1 0x05038C + +//***************************************************************************** +#define RDR_MACCTRL2 0x050390 + +//***************************************************************************** +#define RDR_MAC_LB_DATA 0x050394 + +//***************************************************************************** +#define RDR_L0S_EXIT_LAT 0x050398 + +//***************************************************************************** +// DMAC +//***************************************************************************** +#define DMA1_PTR1 0x100000 // DMA Current Ptr : Ch#1 + +//***************************************************************************** +#define DMA2_PTR1 0x100004 // DMA Current Ptr : Ch#2 + +//***************************************************************************** +#define DMA3_PTR1 0x100008 // DMA Current Ptr : Ch#3 + +//***************************************************************************** +#define DMA4_PTR1 0x10000C // DMA Current Ptr : Ch#4 + +//***************************************************************************** +#define DMA5_PTR1 0x100010 // DMA Current Ptr : Ch#5 + +//***************************************************************************** +#define DMA6_PTR1 0x100014 // DMA Current Ptr : Ch#6 + +//***************************************************************************** +#define DMA7_PTR1 0x100018 // DMA Current Ptr : Ch#7 + +//***************************************************************************** +#define DMA8_PTR1 0x10001C // DMA Current Ptr : Ch#8 + +//***************************************************************************** +#define DMA9_PTR1 0x100020 // DMA Current Ptr : Ch#9 + +//***************************************************************************** +#define DMA10_PTR1 0x100024 // DMA Current Ptr : Ch#10 + +//***************************************************************************** +#define DMA11_PTR1 0x100028 // DMA Current Ptr : Ch#11 + +//***************************************************************************** +#define DMA12_PTR1 0x10002C // DMA Current Ptr : Ch#12 + +//***************************************************************************** +#define DMA13_PTR1 0x100030 // DMA Current Ptr : Ch#13 + +//***************************************************************************** +#define DMA14_PTR1 0x100034 // DMA Current Ptr : Ch#14 + +//***************************************************************************** +#define DMA15_PTR1 0x100038 // DMA Current Ptr : Ch#15 + +//***************************************************************************** +#define DMA16_PTR1 0x10003C // DMA Current Ptr : Ch#16 + +//***************************************************************************** +#define DMA17_PTR1 0x100040 // DMA Current Ptr : Ch#17 + +//***************************************************************************** +#define DMA18_PTR1 0x100044 // DMA Current Ptr : Ch#18 + +//***************************************************************************** +#define DMA19_PTR1 0x100048 // DMA Current Ptr : Ch#19 + +//***************************************************************************** +#define DMA20_PTR1 0x10004C // DMA Current Ptr : Ch#20 + +//***************************************************************************** +#define DMA21_PTR1 0x100050 // DMA Current Ptr : Ch#21 + +//***************************************************************************** +#define DMA22_PTR1 0x100054 // DMA Current Ptr : Ch#22 + +//***************************************************************************** +#define DMA23_PTR1 0x100058 // DMA Current Ptr : Ch#23 + +//***************************************************************************** +#define DMA24_PTR1 0x10005C // DMA Current Ptr : Ch#24 + +//***************************************************************************** +#define DMA25_PTR1 0x100060 // DMA Current Ptr : Ch#25 + +//***************************************************************************** +#define DMA26_PTR1 0x100064 // DMA Current Ptr : Ch#26 + +//***************************************************************************** +#define DMA1_PTR2 0x100080 // DMA Tab Ptr : Ch#1 + +//***************************************************************************** +#define DMA2_PTR2 0x100084 // DMA Tab Ptr : Ch#2 + +//***************************************************************************** +#define DMA3_PTR2 0x100088 // DMA Tab Ptr : Ch#3 + +//***************************************************************************** +#define DMA4_PTR2 0x10008C // DMA Tab Ptr : Ch#4 + +//***************************************************************************** +#define DMA5_PTR2 0x100090 // DMA Tab Ptr : Ch#5 + +//***************************************************************************** +#define DMA6_PTR2 0x100094 // DMA Tab Ptr : Ch#6 + +//***************************************************************************** +#define DMA7_PTR2 0x100098 // DMA Tab Ptr : Ch#7 + +//***************************************************************************** +#define DMA8_PTR2 0x10009C // DMA Tab Ptr : Ch#8 + +//***************************************************************************** +#define DMA9_PTR2 0x1000A0 // DMA Tab Ptr : Ch#9 + +//***************************************************************************** +#define DMA10_PTR2 0x1000A4 // DMA Tab Ptr : Ch#10 + +//***************************************************************************** +#define DMA11_PTR2 0x1000A8 // DMA Tab Ptr : Ch#11 + +//***************************************************************************** +#define DMA12_PTR2 0x1000AC // DMA Tab Ptr : Ch#12 + +//***************************************************************************** +#define DMA13_PTR2 0x1000B0 // DMA Tab Ptr : Ch#13 + +//***************************************************************************** +#define DMA14_PTR2 0x1000B4 // DMA Tab Ptr : Ch#14 + +//***************************************************************************** +#define DMA15_PTR2 0x1000B8 // DMA Tab Ptr : Ch#15 + +//***************************************************************************** +#define DMA16_PTR2 0x1000BC // DMA Tab Ptr : Ch#16 + +//***************************************************************************** +#define DMA17_PTR2 0x1000C0 // DMA Tab Ptr : Ch#17 + +//***************************************************************************** +#define DMA18_PTR2 0x1000C4 // DMA Tab Ptr : Ch#18 + +//***************************************************************************** +#define DMA19_PTR2 0x1000C8 // DMA Tab Ptr : Ch#19 + +//***************************************************************************** +#define DMA20_PTR2 0x1000CC // DMA Tab Ptr : Ch#20 + +//***************************************************************************** +#define DMA21_PTR2 0x1000D0 // DMA Tab Ptr : Ch#21 + +//***************************************************************************** +#define DMA22_PTR2 0x1000D4 // DMA Tab Ptr : Ch#22 + +//***************************************************************************** +#define DMA23_PTR2 0x1000D8 // DMA Tab Ptr : Ch#23 + +//***************************************************************************** +#define DMA24_PTR2 0x1000DC // DMA Tab Ptr : Ch#24 + +//***************************************************************************** +#define DMA25_PTR2 0x1000E0 // DMA Tab Ptr : Ch#25 + +//***************************************************************************** +#define DMA26_PTR2 0x1000E4 // DMA Tab Ptr : Ch#26 + +//***************************************************************************** +#define DMA1_CNT1 0x100100 // DMA BuFFer Size : Ch#1 + +//***************************************************************************** +#define DMA2_CNT1 0x100104 // DMA BuFFer Size : Ch#2 + +//***************************************************************************** +#define DMA3_CNT1 0x100108 // DMA BuFFer Size : Ch#3 + +//***************************************************************************** +#define DMA4_CNT1 0x10010C // DMA BuFFer Size : Ch#4 + +//***************************************************************************** +#define DMA5_CNT1 0x100110 // DMA BuFFer Size : Ch#5 + +//***************************************************************************** +#define DMA6_CNT1 0x100114 // DMA BuFFer Size : Ch#6 + +//***************************************************************************** +#define DMA7_CNT1 0x100118 // DMA BuFFer Size : Ch#7 + +//***************************************************************************** +#define DMA8_CNT1 0x10011C // DMA BuFFer Size : Ch#8 + +//***************************************************************************** +#define DMA9_CNT1 0x100120 // DMA BuFFer Size : Ch#9 + +//***************************************************************************** +#define DMA10_CNT1 0x100124 // DMA BuFFer Size : Ch#10 + +//***************************************************************************** +#define DMA11_CNT1 0x100128 // DMA BuFFer Size : Ch#11 + +//***************************************************************************** +#define DMA12_CNT1 0x10012C // DMA BuFFer Size : Ch#12 + +//***************************************************************************** +#define DMA13_CNT1 0x100130 // DMA BuFFer Size : Ch#13 + +//***************************************************************************** +#define DMA14_CNT1 0x100134 // DMA BuFFer Size : Ch#14 + +//***************************************************************************** +#define DMA15_CNT1 0x100138 // DMA BuFFer Size : Ch#15 + +//***************************************************************************** +#define DMA16_CNT1 0x10013C // DMA BuFFer Size : Ch#16 + +//***************************************************************************** +#define DMA17_CNT1 0x100140 // DMA BuFFer Size : Ch#17 + +//***************************************************************************** +#define DMA18_CNT1 0x100144 // DMA BuFFer Size : Ch#18 + +//***************************************************************************** +#define DMA19_CNT1 0x100148 // DMA BuFFer Size : Ch#19 + +//***************************************************************************** +#define DMA20_CNT1 0x10014C // DMA BuFFer Size : Ch#20 + +//***************************************************************************** +#define DMA21_CNT1 0x100150 // DMA BuFFer Size : Ch#21 + +//***************************************************************************** +#define DMA22_CNT1 0x100154 // DMA BuFFer Size : Ch#22 + +//***************************************************************************** +#define DMA23_CNT1 0x100158 // DMA BuFFer Size : Ch#23 + +//***************************************************************************** +#define DMA24_CNT1 0x10015C // DMA BuFFer Size : Ch#24 + +//***************************************************************************** +#define DMA25_CNT1 0x100160 // DMA BuFFer Size : Ch#25 + +//***************************************************************************** +#define DMA26_CNT1 0x100164 // DMA BuFFer Size : Ch#26 + +//***************************************************************************** +#define DMA1_CNT2 0x100180 // DMA Table Size : Ch#1 + +//***************************************************************************** +#define DMA2_CNT2 0x100184 // DMA Table Size : Ch#2 + +//***************************************************************************** +#define DMA3_CNT2 0x100188 // DMA Table Size : Ch#3 + +//***************************************************************************** +#define DMA4_CNT2 0x10018C // DMA Table Size : Ch#4 + +//***************************************************************************** +#define DMA5_CNT2 0x100190 // DMA Table Size : Ch#5 + +//***************************************************************************** +#define DMA6_CNT2 0x100194 // DMA Table Size : Ch#6 + +//***************************************************************************** +#define DMA7_CNT2 0x100198 // DMA Table Size : Ch#7 + +//***************************************************************************** +#define DMA8_CNT2 0x10019C // DMA Table Size : Ch#8 + +//***************************************************************************** +#define DMA9_CNT2 0x1001A0 // DMA Table Size : Ch#9 + +//***************************************************************************** +#define DMA10_CNT2 0x1001A4 // DMA Table Size : Ch#10 + +//***************************************************************************** +#define DMA11_CNT2 0x1001A8 // DMA Table Size : Ch#11 + +//***************************************************************************** +#define DMA12_CNT2 0x1001AC // DMA Table Size : Ch#12 + +//***************************************************************************** +#define DMA13_CNT2 0x1001B0 // DMA Table Size : Ch#13 + +//***************************************************************************** +#define DMA14_CNT2 0x1001B4 // DMA Table Size : Ch#14 + +//***************************************************************************** +#define DMA15_CNT2 0x1001B8 // DMA Table Size : Ch#15 + +//***************************************************************************** +#define DMA16_CNT2 0x1001BC // DMA Table Size : Ch#16 + +//***************************************************************************** +#define DMA17_CNT2 0x1001C0 // DMA Table Size : Ch#17 + +//***************************************************************************** +#define DMA18_CNT2 0x1001C4 // DMA Table Size : Ch#18 + +//***************************************************************************** +#define DMA19_CNT2 0x1001C8 // DMA Table Size : Ch#19 + +//***************************************************************************** +#define DMA20_CNT2 0x1001CC // DMA Table Size : Ch#20 + +//***************************************************************************** +#define DMA21_CNT2 0x1001D0 // DMA Table Size : Ch#21 + +//***************************************************************************** +#define DMA22_CNT2 0x1001D4 // DMA Table Size : Ch#22 + +//***************************************************************************** +#define DMA23_CNT2 0x1001D8 // DMA Table Size : Ch#23 + +//***************************************************************************** +#define DMA24_CNT2 0x1001DC // DMA Table Size : Ch#24 + +//***************************************************************************** +#define DMA25_CNT2 0x1001E0 // DMA Table Size : Ch#25 + +//***************************************************************************** +#define DMA26_CNT2 0x1001E4 // DMA Table Size : Ch#26 + +//***************************************************************************** + // ITG +//***************************************************************************** +#define TM_CNT_LDW 0x110000 // Timer : Counter low + +//***************************************************************************** +#define TM_CNT_UW 0x110004 // Timer : Counter high word + +//***************************************************************************** +#define TM_LMT_LDW 0x110008 // Timer : Limit low + +//***************************************************************************** +#define TM_LMT_UW 0x11000C // Timer : Limit high word + +//***************************************************************************** +#define GP0_IO 0x110010 // GPIO output enables data I/O +#define FLD_GP_OE 0x00FF0000 // GPIO: GP_OE output enable +#define FLD_GP_IN 0x0000FF00 // GPIO: GP_IN status +#define FLD_GP_OUT 0x000000FF // GPIO: GP_OUT control + +//***************************************************************************** +#define GPIO_ISM 0x110014 // GPIO interrupt sensitivity mode +#define FLD_GP_ISM_SNS 0x00000070 +#define FLD_GP_ISM_POL 0x00000007 + +//***************************************************************************** +#define SOFT_RESET 0x11001C // Output system reset reg +#define FLD_PECOS_SOFT_RESET 0x00000001 + +//***************************************************************************** +#define MC416_RWD 0x110020 // MC416 GPIO[18:3] pin +#define MC416_OEN 0x110024 // Output enable of GPIO[18:3] +#define MC416_CTL 0x110028 + +//***************************************************************************** +#define ALT_PIN_OUT_SEL 0x11002C // Alternate GPIO output select + +#define FLD_ALT_GPIO_OUT_SEL 0xF0000000 +// 0 Disabled <-- default +// 1 GPIO[0] +// 2 GPIO[10] +// 3 VIP_656_DATA_VAL +// 4 VIP_656_DATA[0] +// 5 VIP_656_CLK +// 6 VIP_656_DATA_EXT[1] +// 7 VIP_656_DATA_EXT[0] +// 8 ATT_IF + +#define FLD_AUX_PLL_CLK_ALT_SEL 0x0F000000 +// 0 AUX_PLL_CLK<-- default +// 1 GPIO[2] +// 2 GPIO[10] +// 3 VIP_656_DATA_VAL +// 4 VIP_656_DATA[0] +// 5 VIP_656_CLK +// 6 VIP_656_DATA_EXT[1] +// 7 VIP_656_DATA_EXT[0] + +#define FLD_IR_TX_ALT_SEL 0x00F00000 +// 0 IR_TX <-- default +// 1 GPIO[1] +// 2 GPIO[10] +// 3 VIP_656_DATA_VAL +// 4 VIP_656_DATA[0] +// 5 VIP_656_CLK +// 6 VIP_656_DATA_EXT[1] +// 7 VIP_656_DATA_EXT[0] + +#define FLD_IR_RX_ALT_SEL 0x000F0000 +// 0 IR_RX <-- default +// 1 GPIO[0] +// 2 GPIO[10] +// 3 VIP_656_DATA_VAL +// 4 VIP_656_DATA[0] +// 5 VIP_656_CLK +// 6 VIP_656_DATA_EXT[1] +// 7 VIP_656_DATA_EXT[0] + +#define FLD_GPIO10_ALT_SEL 0x0000F000 +// 0 GPIO[10] <-- default +// 1 GPIO[0] +// 2 GPIO[10] +// 3 VIP_656_DATA_VAL +// 4 VIP_656_DATA[0] +// 5 VIP_656_CLK +// 6 VIP_656_DATA_EXT[1] +// 7 VIP_656_DATA_EXT[0] + +#define FLD_GPIO2_ALT_SEL 0x00000F00 +// 0 GPIO[2] <-- default +// 1 GPIO[1] +// 2 GPIO[10] +// 3 VIP_656_DATA_VAL +// 4 VIP_656_DATA[0] +// 5 VIP_656_CLK +// 6 VIP_656_DATA_EXT[1] +// 7 VIP_656_DATA_EXT[0] + +#define FLD_GPIO1_ALT_SEL 0x000000F0 +// 0 GPIO[1] <-- default +// 1 GPIO[0] +// 2 GPIO[10] +// 3 VIP_656_DATA_VAL +// 4 VIP_656_DATA[0] +// 5 VIP_656_CLK +// 6 VIP_656_DATA_EXT[1] +// 7 VIP_656_DATA_EXT[0] + +#define FLD_GPIO0_ALT_SEL 0x0000000F +// 0 GPIO[0] <-- default +// 1 GPIO[1] +// 2 GPIO[10] +// 3 VIP_656_DATA_VAL +// 4 VIP_656_DATA[0] +// 5 VIP_656_CLK +// 6 VIP_656_DATA_EXT[1] +// 7 VIP_656_DATA_EXT[0] + +#define ALT_PIN_IN_SEL 0x110030 // Alternate GPIO input select + +#define FLD_GPIO10_ALT_IN_SEL 0x0000F000 +// 0 GPIO[10] <-- default +// 1 IR_RX +// 2 IR_TX +// 3 AUX_PLL_CLK +// 4 IF_ATT_SEL +// 5 GPIO[0] +// 6 GPIO[1] +// 7 GPIO[2] + +#define FLD_GPIO2_ALT_IN_SEL 0x00000F00 +// 0 GPIO[2] <-- default +// 1 IR_RX +// 2 IR_TX +// 3 AUX_PLL_CLK +// 4 IF_ATT_SEL + +#define FLD_GPIO1_ALT_IN_SEL 0x000000F0 +// 0 GPIO[1] <-- default +// 1 IR_RX +// 2 IR_TX +// 3 AUX_PLL_CLK +// 4 IF_ATT_SEL + +#define FLD_GPIO0_ALT_IN_SEL 0x0000000F +// 0 GPIO[0] <-- default +// 1 IR_RX +// 2 IR_TX +// 3 AUX_PLL_CLK +// 4 IF_ATT_SEL + +//***************************************************************************** +#define TEST_BUS_CTL1 0x110040 // Test bus control register #1 + +//***************************************************************************** +#define TEST_BUS_CTL2 0x110044 // Test bus control register #2 + +//***************************************************************************** +#define CLK_DELAY 0x110048 // Clock delay +#define FLD_MOE_CLK_DIS 0x80000000 // Disable MoE clock + +//***************************************************************************** +#define PAD_CTRL 0x110068 // Pad drive strength control + +//***************************************************************************** +#define MBIST_CTRL 0x110050 // SRAM memory built-in self test control + +//***************************************************************************** +#define MBIST_STAT 0x110054 // SRAM memory built-in self test status + +//***************************************************************************** +// PLL registers +//***************************************************************************** +#define PLL_A_INT_FRAC 0x110088 +#define PLL_A_POST_STAT_BIST 0x11008C +#define PLL_B_INT_FRAC 0x110090 +#define PLL_B_POST_STAT_BIST 0x110094 +#define PLL_C_INT_FRAC 0x110098 +#define PLL_C_POST_STAT_BIST 0x11009C +#define PLL_D_INT_FRAC 0x1100A0 +#define PLL_D_POST_STAT_BIST 0x1100A4 + +#define CLK_RST 0x11002C +#define FLD_VID_I_CLK_NOE 0x00001000 +#define FLD_VID_J_CLK_NOE 0x00002000 +#define FLD_USE_ALT_PLL_REF 0x00004000 + +#define VID_CH_MODE_SEL 0x110078 +#define VID_CH_CLK_SEL 0x11007C + +//***************************************************************************** +#define VBI_A_DMA 0x130008 // VBI A DMA data port + +//***************************************************************************** +#define VID_A_VIP_CTL 0x130080 // Video A VIP format control +#define FLD_VIP_MODE 0x00000001 + +//***************************************************************************** +#define VID_A_PIXEL_FRMT 0x130084 // Video A pixel format +#define FLD_VID_A_GAMMA_DIS 0x00000008 +#define FLD_VID_A_FORMAT 0x00000007 +#define FLD_VID_A_GAMMA_FACTOR 0x00000010 + +//***************************************************************************** +#define VID_A_VBI_CTL 0x130088 // Video A VBI miscellaneous control +#define FLD_VID_A_VIP_EXT 0x00000003 + +//***************************************************************************** +#define VID_B_DMA 0x130100 // Video B DMA data port + +//***************************************************************************** +#define VBI_B_DMA 0x130108 // VBI B DMA data port + +//***************************************************************************** +#define VID_B_SRC_SEL 0x130144 // Video B source select +#define FLD_VID_B_SRC_SEL 0x00000000 + +//***************************************************************************** +#define VID_B_LNGTH 0x130150 // Video B line length +#define FLD_VID_B_LN_LNGTH 0x00000FFF + +//***************************************************************************** +#define VID_B_VIP_CTL 0x130180 // Video B VIP format control + +//***************************************************************************** +#define VID_B_PIXEL_FRMT 0x130184 // Video B pixel format +#define FLD_VID_B_GAMMA_DIS 0x00000008 +#define FLD_VID_B_FORMAT 0x00000007 +#define FLD_VID_B_GAMMA_FACTOR 0x00000010 + +//***************************************************************************** +#define VID_C_DMA 0x130200 // Video C DMA data port + +//***************************************************************************** +#define VID_C_LNGTH 0x130250 // Video C line length +#define FLD_VID_C_LN_LNGTH 0x00000FFF + +//***************************************************************************** +// Video Destination Channels +//***************************************************************************** + +#define VID_DST_A_GPCNT 0x130020 // Video A general purpose counter +#define VID_DST_B_GPCNT 0x130120 // Video B general purpose counter +#define VID_DST_C_GPCNT 0x130220 // Video C general purpose counter +#define VID_DST_D_GPCNT 0x130320 // Video D general purpose counter +#define VID_DST_E_GPCNT 0x130420 // Video E general purpose counter +#define VID_DST_F_GPCNT 0x130520 // Video F general purpose counter +#define VID_DST_G_GPCNT 0x130620 // Video G general purpose counter +#define VID_DST_H_GPCNT 0x130720 // Video H general purpose counter + +//***************************************************************************** + +#define VID_DST_A_GPCNT_CTL 0x130030 // Video A general purpose control +#define VID_DST_B_GPCNT_CTL 0x130130 // Video B general purpose control +#define VID_DST_C_GPCNT_CTL 0x130230 // Video C general purpose control +#define VID_DST_D_GPCNT_CTL 0x130330 // Video D general purpose control +#define VID_DST_E_GPCNT_CTL 0x130430 // Video E general purpose control +#define VID_DST_F_GPCNT_CTL 0x130530 // Video F general purpose control +#define VID_DST_G_GPCNT_CTL 0x130630 // Video G general purpose control +#define VID_DST_H_GPCNT_CTL 0x130730 // Video H general purpose control + +//***************************************************************************** + +#define VID_DST_A_DMA_CTL 0x130040 // Video A DMA control +#define VID_DST_B_DMA_CTL 0x130140 // Video B DMA control +#define VID_DST_C_DMA_CTL 0x130240 // Video C DMA control +#define VID_DST_D_DMA_CTL 0x130340 // Video D DMA control +#define VID_DST_E_DMA_CTL 0x130440 // Video E DMA control +#define VID_DST_F_DMA_CTL 0x130540 // Video F DMA control +#define VID_DST_G_DMA_CTL 0x130640 // Video G DMA control +#define VID_DST_H_DMA_CTL 0x130740 // Video H DMA control + +#define FLD_VID_RISC_EN 0x00000010 +#define FLD_VID_FIFO_EN 0x00000001 + +//***************************************************************************** + +#define VID_DST_A_VIP_CTL 0x130080 // Video A VIP control +#define VID_DST_B_VIP_CTL 0x130180 // Video B VIP control +#define VID_DST_C_VIP_CTL 0x130280 // Video C VIP control +#define VID_DST_D_VIP_CTL 0x130380 // Video D VIP control +#define VID_DST_E_VIP_CTL 0x130480 // Video E VIP control +#define VID_DST_F_VIP_CTL 0x130580 // Video F VIP control +#define VID_DST_G_VIP_CTL 0x130680 // Video G VIP control +#define VID_DST_H_VIP_CTL 0x130780 // Video H VIP control + +//***************************************************************************** + +#define VID_DST_A_PIX_FRMT 0x130084 // Video A Pixel format +#define VID_DST_B_PIX_FRMT 0x130184 // Video B Pixel format +#define VID_DST_C_PIX_FRMT 0x130284 // Video C Pixel format +#define VID_DST_D_PIX_FRMT 0x130384 // Video D Pixel format +#define VID_DST_E_PIX_FRMT 0x130484 // Video E Pixel format +#define VID_DST_F_PIX_FRMT 0x130584 // Video F Pixel format +#define VID_DST_G_PIX_FRMT 0x130684 // Video G Pixel format +#define VID_DST_H_PIX_FRMT 0x130784 // Video H Pixel format + +//***************************************************************************** +// Video Source Channels +//***************************************************************************** + +#define VID_SRC_A_GPCNT_CTL 0x130804 // Video A general purpose control +#define VID_SRC_B_GPCNT_CTL 0x130904 // Video B general purpose control +#define VID_SRC_C_GPCNT_CTL 0x130A04 // Video C general purpose control +#define VID_SRC_D_GPCNT_CTL 0x130B04 // Video D general purpose control +#define VID_SRC_E_GPCNT_CTL 0x130C04 // Video E general purpose control +#define VID_SRC_F_GPCNT_CTL 0x130D04 // Video F general purpose control +#define VID_SRC_I_GPCNT_CTL 0x130E04 // Video I general purpose control +#define VID_SRC_J_GPCNT_CTL 0x130F04 // Video J general purpose control + +//***************************************************************************** + +#define VID_SRC_A_GPCNT 0x130808 // Video A general purpose counter +#define VID_SRC_B_GPCNT 0x130908 // Video B general purpose counter +#define VID_SRC_C_GPCNT 0x130A08 // Video C general purpose counter +#define VID_SRC_D_GPCNT 0x130B08 // Video D general purpose counter +#define VID_SRC_E_GPCNT 0x130C08 // Video E general purpose counter +#define VID_SRC_F_GPCNT 0x130D08 // Video F general purpose counter +#define VID_SRC_I_GPCNT 0x130E08 // Video I general purpose counter +#define VID_SRC_J_GPCNT 0x130F08 // Video J general purpose counter + +//***************************************************************************** + +#define VID_SRC_A_DMA_CTL 0x13080C // Video A DMA control +#define VID_SRC_B_DMA_CTL 0x13090C // Video B DMA control +#define VID_SRC_C_DMA_CTL 0x130A0C // Video C DMA control +#define VID_SRC_D_DMA_CTL 0x130B0C // Video D DMA control +#define VID_SRC_E_DMA_CTL 0x130C0C // Video E DMA control +#define VID_SRC_F_DMA_CTL 0x130D0C // Video F DMA control +#define VID_SRC_I_DMA_CTL 0x130E0C // Video I DMA control +#define VID_SRC_J_DMA_CTL 0x130F0C // Video J DMA control + +#define FLD_APB_RISC_EN 0x00000010 +#define FLD_APB_FIFO_EN 0x00000001 + +//***************************************************************************** + +#define VID_SRC_A_FMT_CTL 0x130810 // Video A format control +#define VID_SRC_B_FMT_CTL 0x130910 // Video B format control +#define VID_SRC_C_FMT_CTL 0x130A10 // Video C format control +#define VID_SRC_D_FMT_CTL 0x130B10 // Video D format control +#define VID_SRC_E_FMT_CTL 0x130C10 // Video E format control +#define VID_SRC_F_FMT_CTL 0x130D10 // Video F format control +#define VID_SRC_I_FMT_CTL 0x130E10 // Video I format control +#define VID_SRC_J_FMT_CTL 0x130F10 // Video J format control + +//***************************************************************************** + +#define VID_SRC_A_ACTIVE_CTL1 0x130814 // Video A active control 1 +#define VID_SRC_B_ACTIVE_CTL1 0x130914 // Video B active control 1 +#define VID_SRC_C_ACTIVE_CTL1 0x130A14 // Video C active control 1 +#define VID_SRC_D_ACTIVE_CTL1 0x130B14 // Video D active control 1 +#define VID_SRC_E_ACTIVE_CTL1 0x130C14 // Video E active control 1 +#define VID_SRC_F_ACTIVE_CTL1 0x130D14 // Video F active control 1 +#define VID_SRC_I_ACTIVE_CTL1 0x130E14 // Video I active control 1 +#define VID_SRC_J_ACTIVE_CTL1 0x130F14 // Video J active control 1 + +//***************************************************************************** + +#define VID_SRC_A_ACTIVE_CTL2 0x130818 // Video A active control 2 +#define VID_SRC_B_ACTIVE_CTL2 0x130918 // Video B active control 2 +#define VID_SRC_C_ACTIVE_CTL2 0x130A18 // Video C active control 2 +#define VID_SRC_D_ACTIVE_CTL2 0x130B18 // Video D active control 2 +#define VID_SRC_E_ACTIVE_CTL2 0x130C18 // Video E active control 2 +#define VID_SRC_F_ACTIVE_CTL2 0x130D18 // Video F active control 2 +#define VID_SRC_I_ACTIVE_CTL2 0x130E18 // Video I active control 2 +#define VID_SRC_J_ACTIVE_CTL2 0x130F18 // Video J active control 2 + +//***************************************************************************** + +#define VID_SRC_A_CDT_SZ 0x13081C // Video A CDT size +#define VID_SRC_B_CDT_SZ 0x13091C // Video B CDT size +#define VID_SRC_C_CDT_SZ 0x130A1C // Video C CDT size +#define VID_SRC_D_CDT_SZ 0x130B1C // Video D CDT size +#define VID_SRC_E_CDT_SZ 0x130C1C // Video E CDT size +#define VID_SRC_F_CDT_SZ 0x130D1C // Video F CDT size +#define VID_SRC_I_CDT_SZ 0x130E1C // Video I CDT size +#define VID_SRC_J_CDT_SZ 0x130F1C // Video J CDT size + +//***************************************************************************** +// Audio I/F +//***************************************************************************** +#define AUD_DST_A_DMA 0x140000 // Audio Int A DMA data port +#define AUD_SRC_A_DMA 0x140008 // Audio Int A DMA data port + +#define AUD_A_GPCNT 0x140010 // Audio Int A gp counter +#define FLD_AUD_A_GP_CNT 0x0000FFFF + +#define AUD_A_GPCNT_CTL 0x140014 // Audio Int A gp control + +#define AUD_A_LNGTH 0x140018 // Audio Int A line length + +#define AUD_A_CFG 0x14001C // Audio Int A configuration + +//***************************************************************************** +#define AUD_DST_B_DMA 0x140100 // Audio Int B DMA data port +#define AUD_SRC_B_DMA 0x140108 // Audio Int B DMA data port + +#define AUD_B_GPCNT 0x140110 // Audio Int B gp counter +#define FLD_AUD_B_GP_CNT 0x0000FFFF + +#define AUD_B_GPCNT_CTL 0x140114 // Audio Int B gp control + +#define AUD_B_LNGTH 0x140118 // Audio Int B line length + +#define AUD_B_CFG 0x14011C // Audio Int B configuration + +//***************************************************************************** +#define AUD_DST_C_DMA 0x140200 // Audio Int C DMA data port +#define AUD_SRC_C_DMA 0x140208 // Audio Int C DMA data port + +#define AUD_C_GPCNT 0x140210 // Audio Int C gp counter +#define FLD_AUD_C_GP_CNT 0x0000FFFF + +#define AUD_C_GPCNT_CTL 0x140214 // Audio Int C gp control + +#define AUD_C_LNGTH 0x140218 // Audio Int C line length + +#define AUD_C_CFG 0x14021C // Audio Int C configuration + +//***************************************************************************** +#define AUD_DST_D_DMA 0x140300 // Audio Int D DMA data port +#define AUD_SRC_D_DMA 0x140308 // Audio Int D DMA data port + +#define AUD_D_GPCNT 0x140310 // Audio Int D gp counter +#define FLD_AUD_D_GP_CNT 0x0000FFFF + +#define AUD_D_GPCNT_CTL 0x140314 // Audio Int D gp control + +#define AUD_D_LNGTH 0x140318 // Audio Int D line length + +#define AUD_D_CFG 0x14031C // Audio Int D configuration + +//***************************************************************************** +#define AUD_SRC_E_DMA 0x140400 // Audio Int E DMA data port + +#define AUD_E_GPCNT 0x140410 // Audio Int E gp counter +#define FLD_AUD_E_GP_CNT 0x0000FFFF + +#define AUD_E_GPCNT_CTL 0x140414 // Audio Int E gp control + +#define AUD_E_CFG 0x14041C // Audio Int E configuration + +//***************************************************************************** + +#define FLD_AUD_DST_LN_LNGTH 0x00000FFF + +#define FLD_AUD_DST_PK_MODE 0x00004000 + +#define FLD_AUD_CLK_ENABLE 0x00000200 + +#define FLD_AUD_MASTER_MODE 0x00000002 + +#define FLD_AUD_SONY_MODE 0x00000001 + +#define FLD_AUD_CLK_SELECT_PLL_D 0x00001800 + +#define FLD_AUD_DST_ENABLE 0x00020000 + +#define FLD_AUD_SRC_ENABLE 0x00010000 + +//***************************************************************************** +#define AUD_INT_DMA_CTL 0x140500 // Audio Int DMA control + +#define FLD_AUD_SRC_E_RISC_EN 0x00008000 +#define FLD_AUD_SRC_C_RISC_EN 0x00004000 +#define FLD_AUD_SRC_B_RISC_EN 0x00002000 +#define FLD_AUD_SRC_A_RISC_EN 0x00001000 + +#define FLD_AUD_DST_D_RISC_EN 0x00000800 +#define FLD_AUD_DST_C_RISC_EN 0x00000400 +#define FLD_AUD_DST_B_RISC_EN 0x00000200 +#define FLD_AUD_DST_A_RISC_EN 0x00000100 + +#define FLD_AUD_SRC_E_FIFO_EN 0x00000080 +#define FLD_AUD_SRC_C_FIFO_EN 0x00000040 +#define FLD_AUD_SRC_B_FIFO_EN 0x00000020 +#define FLD_AUD_SRC_A_FIFO_EN 0x00000010 + +#define FLD_AUD_DST_D_FIFO_EN 0x00000008 +#define FLD_AUD_DST_C_FIFO_EN 0x00000004 +#define FLD_AUD_DST_B_FIFO_EN 0x00000002 +#define FLD_AUD_DST_A_FIFO_EN 0x00000001 + +//***************************************************************************** +// +// Mobilygen Interface Registers +// +//***************************************************************************** +// Mobilygen Interface A +//***************************************************************************** +#define MB_IF_A_DMA 0x150000 // MBIF A DMA data port +#define MB_IF_A_GPCN 0x150008 // MBIF A GP counter +#define MB_IF_A_GPCN_CTRL 0x15000C +#define MB_IF_A_DMA_CTRL 0x150010 +#define MB_IF_A_LENGTH 0x150014 +#define MB_IF_A_HDMA_XFER_SZ 0x150018 +#define MB_IF_A_HCMD 0x15001C +#define MB_IF_A_HCONFIG 0x150020 +#define MB_IF_A_DATA_STRUCT_0 0x150024 +#define MB_IF_A_DATA_STRUCT_1 0x150028 +#define MB_IF_A_DATA_STRUCT_2 0x15002C +#define MB_IF_A_DATA_STRUCT_3 0x150030 +#define MB_IF_A_DATA_STRUCT_4 0x150034 +#define MB_IF_A_DATA_STRUCT_5 0x150038 +#define MB_IF_A_DATA_STRUCT_6 0x15003C +#define MB_IF_A_DATA_STRUCT_7 0x150040 +#define MB_IF_A_DATA_STRUCT_8 0x150044 +#define MB_IF_A_DATA_STRUCT_9 0x150048 +#define MB_IF_A_DATA_STRUCT_A 0x15004C +#define MB_IF_A_DATA_STRUCT_B 0x150050 +#define MB_IF_A_DATA_STRUCT_C 0x150054 +#define MB_IF_A_DATA_STRUCT_D 0x150058 +#define MB_IF_A_DATA_STRUCT_E 0x15005C +#define MB_IF_A_DATA_STRUCT_F 0x150060 +//***************************************************************************** +// Mobilygen Interface B +//***************************************************************************** +#define MB_IF_B_DMA 0x160000 // MBIF A DMA data port +#define MB_IF_B_GPCN 0x160008 // MBIF A GP counter +#define MB_IF_B_GPCN_CTRL 0x16000C +#define MB_IF_B_DMA_CTRL 0x160010 +#define MB_IF_B_LENGTH 0x160014 +#define MB_IF_B_HDMA_XFER_SZ 0x160018 +#define MB_IF_B_HCMD 0x16001C +#define MB_IF_B_HCONFIG 0x160020 +#define MB_IF_B_DATA_STRUCT_0 0x160024 +#define MB_IF_B_DATA_STRUCT_1 0x160028 +#define MB_IF_B_DATA_STRUCT_2 0x16002C +#define MB_IF_B_DATA_STRUCT_3 0x160030 +#define MB_IF_B_DATA_STRUCT_4 0x160034 +#define MB_IF_B_DATA_STRUCT_5 0x160038 +#define MB_IF_B_DATA_STRUCT_6 0x16003C +#define MB_IF_B_DATA_STRUCT_7 0x160040 +#define MB_IF_B_DATA_STRUCT_8 0x160044 +#define MB_IF_B_DATA_STRUCT_9 0x160048 +#define MB_IF_B_DATA_STRUCT_A 0x16004C +#define MB_IF_B_DATA_STRUCT_B 0x160050 +#define MB_IF_B_DATA_STRUCT_C 0x160054 +#define MB_IF_B_DATA_STRUCT_D 0x160058 +#define MB_IF_B_DATA_STRUCT_E 0x16005C +#define MB_IF_B_DATA_STRUCT_F 0x160060 + +// MB_DMA_CTRL +#define FLD_MB_IF_RISC_EN 0x00000010 +#define FLD_MB_IF_FIFO_EN 0x00000001 + +// MB_LENGTH +#define FLD_MB_IF_LN_LNGTH 0x00000FFF + +// MB_HCMD register +#define FLD_MB_HCMD_H_GO 0x80000000 +#define FLD_MB_HCMD_H_BUSY 0x40000000 +#define FLD_MB_HCMD_H_DMA_HOLD 0x10000000 +#define FLD_MB_HCMD_H_DMA_BUSY 0x08000000 +#define FLD_MB_HCMD_H_DMA_TYPE 0x04000000 +#define FLD_MB_HCMD_H_DMA_XACT 0x02000000 +#define FLD_MB_HCMD_H_RW_N 0x01000000 +#define FLD_MB_HCMD_H_ADDR 0x00FF0000 +#define FLD_MB_HCMD_H_DATA 0x0000FFFF + +//***************************************************************************** +// I2C #1 +//***************************************************************************** +#define I2C1_ADDR 0x180000 // I2C #1 address +#define FLD_I2C_DADDR 0xfe000000 // RW [31:25] I2C Device Address + // RO [24] reserved +//***************************************************************************** +#define FLD_I2C_SADDR 0x00FFFFFF // RW [23:0] I2C Sub-address + +//***************************************************************************** +#define I2C1_WDATA 0x180004 // I2C #1 write data +#define FLD_I2C_WDATA 0xFFFFFFFF // RW [31:0] + +//***************************************************************************** +#define I2C1_CTRL 0x180008 // I2C #1 control +#define FLD_I2C_PERIOD 0xFF000000 // RW [31:24] +#define FLD_I2C_SCL_IN 0x00200000 // RW [21] +#define FLD_I2C_SDA_IN 0x00100000 // RW [20] + // RO [19:18] reserved +#define FLD_I2C_SCL_OUT 0x00020000 // RW [17] +#define FLD_I2C_SDA_OUT 0x00010000 // RW [16] + // RO [15] reserved +#define FLD_I2C_DATA_LEN 0x00007000 // RW [14:12] +#define FLD_I2C_SADDR_INC 0x00000800 // RW [11] + // RO [10:9] reserved +#define FLD_I2C_SADDR_LEN 0x00000300 // RW [9:8] + // RO [7:6] reserved +#define FLD_I2C_SOFT 0x00000020 // RW [5] +#define FLD_I2C_NOSTOP 0x00000010 // RW [4] +#define FLD_I2C_EXTEND 0x00000008 // RW [3] +#define FLD_I2C_SYNC 0x00000004 // RW [2] +#define FLD_I2C_READ_SA 0x00000002 // RW [1] +#define FLD_I2C_READ_WRN 0x00000001 // RW [0] + +//***************************************************************************** +#define I2C1_RDATA 0x18000C // I2C #1 read data +#define FLD_I2C_RDATA 0xFFFFFFFF // RO [31:0] + +//***************************************************************************** +#define I2C1_STAT 0x180010 // I2C #1 status +#define FLD_I2C_XFER_IN_PROG 0x00000002 // RO [1] +#define FLD_I2C_RACK 0x00000001 // RO [0] + +//***************************************************************************** +// I2C #2 +//***************************************************************************** +#define I2C2_ADDR 0x190000 // I2C #2 address + +//***************************************************************************** +#define I2C2_WDATA 0x190004 // I2C #2 write data + +//***************************************************************************** +#define I2C2_CTRL 0x190008 // I2C #2 control + +//***************************************************************************** +#define I2C2_RDATA 0x19000C // I2C #2 read data + +//***************************************************************************** +#define I2C2_STAT 0x190010 // I2C #2 status + +//***************************************************************************** +// I2C #3 +//***************************************************************************** +#define I2C3_ADDR 0x1A0000 // I2C #3 address + +//***************************************************************************** +#define I2C3_WDATA 0x1A0004 // I2C #3 write data + +//***************************************************************************** +#define I2C3_CTRL 0x1A0008 // I2C #3 control + +//***************************************************************************** +#define I2C3_RDATA 0x1A000C // I2C #3 read data + +//***************************************************************************** +#define I2C3_STAT 0x1A0010 // I2C #3 status + +//***************************************************************************** +// UART +//***************************************************************************** +#define UART_CTL 0x1B0000 // UART Control Register +#define FLD_LOOP_BACK_EN (1 << 7) // RW field - default 0 +#define FLD_RX_TRG_SZ (3 << 2) // RW field - default 0 +#define FLD_RX_EN (1 << 1) // RW field - default 0 +#define FLD_TX_EN (1 << 0) // RW field - default 0 + +//***************************************************************************** +#define UART_BRD 0x1B0004 // UART Baud Rate Divisor +#define FLD_BRD 0x0000FFFF // RW field - default 0x197 + +//***************************************************************************** +#define UART_DBUF 0x1B0008 // UART Tx/Rx Data BuFFer +#define FLD_DB 0xFFFFFFFF // RW field - default 0 + +//***************************************************************************** +#define UART_ISR 0x1B000C // UART Interrupt Status +#define FLD_RXD_TIMEOUT_EN (1 << 7) // RW field - default 0 +#define FLD_FRM_ERR_EN (1 << 6) // RW field - default 0 +#define FLD_RXD_RDY_EN (1 << 5) // RW field - default 0 +#define FLD_TXD_EMPTY_EN (1 << 4) // RW field - default 0 +#define FLD_RXD_OVERFLOW (1 << 3) // RW field - default 0 +#define FLD_FRM_ERR (1 << 2) // RW field - default 0 +#define FLD_RXD_RDY (1 << 1) // RW field - default 0 +#define FLD_TXD_EMPTY (1 << 0) // RW field - default 0 + +//***************************************************************************** +#define UART_CNT 0x1B0010 // UART Tx/Rx FIFO Byte Count +#define FLD_TXD_CNT (0x1F << 8) // RW field - default 0 +#define FLD_RXD_CNT (0x1F << 0) // RW field - default 0 + +//***************************************************************************** +// Motion Detection +#define MD_CH0_GRID_BLOCK_YCNT 0x170014 +#define MD_CH1_GRID_BLOCK_YCNT 0x170094 +#define MD_CH2_GRID_BLOCK_YCNT 0x170114 +#define MD_CH3_GRID_BLOCK_YCNT 0x170194 +#define MD_CH4_GRID_BLOCK_YCNT 0x170214 +#define MD_CH5_GRID_BLOCK_YCNT 0x170294 +#define MD_CH6_GRID_BLOCK_YCNT 0x170314 +#define MD_CH7_GRID_BLOCK_YCNT 0x170394 + +#define PIXEL_FRMT_422 4 +#define PIXEL_FRMT_411 5 +#define PIXEL_FRMT_Y8 6 + +#define PIXEL_ENGINE_VIP1 0 +#define PIXEL_ENGINE_VIP2 1 + +#endif //Athena_REGISTERS diff --git a/drivers/staging/cx25821/cx25821-sram.h b/drivers/staging/cx25821/cx25821-sram.h new file mode 100644 index 000000000000..bd677ee22996 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-sram.h @@ -0,0 +1,261 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ATHENA_SRAM_H__ +#define __ATHENA_SRAM_H__ + +//#define RX_SRAM_START_SIZE = 0; // Start of reserved SRAM +#define VID_CMDS_SIZE 80 // Video CMDS size in bytes +#define AUDIO_CMDS_SIZE 80 // AUDIO CMDS size in bytes +#define MBIF_CMDS_SIZE 80 // MBIF CMDS size in bytes + +//#define RX_SRAM_POOL_START_SIZE = 0; // Start of useable RX SRAM for buffers +#define VID_IQ_SIZE 64 // VID instruction queue size in bytes +#define MBIF_IQ_SIZE 64 +#define AUDIO_IQ_SIZE 64 // AUD instruction queue size in bytes + +#define VID_CDT_SIZE 64 // VID cluster descriptor table size in bytes +#define MBIF_CDT_SIZE 64 // MBIF/HBI cluster descriptor table size in bytes +#define AUDIO_CDT_SIZE 48 // AUD cluster descriptor table size in bytes + +//#define RX_SRAM_POOL_FREE_SIZE = 16; // Start of available RX SRAM +//#define RX_SRAM_END_SIZE = 0; // End of RX SRAM + +//#define TX_SRAM_POOL_START_SIZE = 0; // Start of transmit pool SRAM +//#define MSI_DATA_SIZE = 64; // Reserved (MSI Data, RISC working stora + +#define VID_CLUSTER_SIZE 1440 // VID cluster data line +#define AUDIO_CLUSTER_SIZE 128 // AUDIO cluster data line +#define MBIF_CLUSTER_SIZE 1440 // MBIF/HBI cluster data line + +//#define TX_SRAM_POOL_FREE_SIZE = 704; // Start of available TX SRAM +//#define TX_SRAM_END_SIZE = 0; // End of TX SRAM + +// Receive SRAM +#define RX_SRAM_START 0x10000 +#define VID_A_DOWN_CMDS 0x10000 +#define VID_B_DOWN_CMDS 0x10050 +#define VID_C_DOWN_CMDS 0x100A0 +#define VID_D_DOWN_CMDS 0x100F0 +#define VID_E_DOWN_CMDS 0x10140 +#define VID_F_DOWN_CMDS 0x10190 +#define VID_G_DOWN_CMDS 0x101E0 +#define VID_H_DOWN_CMDS 0x10230 +#define VID_A_UP_CMDS 0x10280 +#define VID_B_UP_CMDS 0x102D0 +#define VID_C_UP_CMDS 0x10320 +#define VID_D_UP_CMDS 0x10370 +#define VID_E_UP_CMDS 0x103C0 +#define VID_F_UP_CMDS 0x10410 +#define VID_I_UP_CMDS 0x10460 +#define VID_J_UP_CMDS 0x104B0 +#define AUD_A_DOWN_CMDS 0x10500 +#define AUD_B_DOWN_CMDS 0x10550 +#define AUD_C_DOWN_CMDS 0x105A0 +#define AUD_D_DOWN_CMDS 0x105F0 +#define AUD_A_UP_CMDS 0x10640 +#define AUD_B_UP_CMDS 0x10690 +#define AUD_C_UP_CMDS 0x106E0 +#define AUD_E_UP_CMDS 0x10730 +#define MBIF_A_DOWN_CMDS 0x10780 +#define MBIF_B_DOWN_CMDS 0x107D0 +#define DMA_SCRATCH_PAD 0x10820 // Scratch pad area from 0x10820 to 0x10B40 + +//#define RX_SRAM_POOL_START = 0x105B0; + +#define VID_A_IQ 0x11000 +#define VID_B_IQ 0x11040 +#define VID_C_IQ 0x11080 +#define VID_D_IQ 0x110C0 +#define VID_E_IQ 0x11100 +#define VID_F_IQ 0x11140 +#define VID_G_IQ 0x11180 +#define VID_H_IQ 0x111C0 +#define VID_I_IQ 0x11200 +#define VID_J_IQ 0x11240 +#define AUD_A_IQ 0x11280 +#define AUD_B_IQ 0x112C0 +#define AUD_C_IQ 0x11300 +#define AUD_D_IQ 0x11340 +#define AUD_E_IQ 0x11380 +#define MBIF_A_IQ 0x11000 +#define MBIF_B_IQ 0x110C0 + +#define VID_A_CDT 0x10C00 +#define VID_B_CDT 0x10C40 +#define VID_C_CDT 0x10C80 +#define VID_D_CDT 0x10CC0 +#define VID_E_CDT 0x10D00 +#define VID_F_CDT 0x10D40 +#define VID_G_CDT 0x10D80 +#define VID_H_CDT 0x10DC0 +#define VID_I_CDT 0x10E00 +#define VID_J_CDT 0x10E40 +#define AUD_A_CDT 0x10E80 +#define AUD_B_CDT 0x10EB0 +#define AUD_C_CDT 0x10EE0 +#define AUD_D_CDT 0x10F10 +#define AUD_E_CDT 0x10F40 +#define MBIF_A_CDT 0x10C00 +#define MBIF_B_CDT 0x10CC0 + +// Cluster Buffer for RX +#define VID_A_UP_CLUSTER_1 0x11400 +#define VID_A_UP_CLUSTER_2 0x119A0 +#define VID_A_UP_CLUSTER_3 0x11F40 +#define VID_A_UP_CLUSTER_4 0x124E0 + +#define VID_B_UP_CLUSTER_1 0x12A80 +#define VID_B_UP_CLUSTER_2 0x13020 +#define VID_B_UP_CLUSTER_3 0x135C0 +#define VID_B_UP_CLUSTER_4 0x13B60 + +#define VID_C_UP_CLUSTER_1 0x14100 +#define VID_C_UP_CLUSTER_2 0x146A0 +#define VID_C_UP_CLUSTER_3 0x14C40 +#define VID_C_UP_CLUSTER_4 0x151E0 + +#define VID_D_UP_CLUSTER_1 0x15780 +#define VID_D_UP_CLUSTER_2 0x15D20 +#define VID_D_UP_CLUSTER_3 0x162C0 +#define VID_D_UP_CLUSTER_4 0x16860 + +#define VID_E_UP_CLUSTER_1 0x16E00 +#define VID_E_UP_CLUSTER_2 0x173A0 +#define VID_E_UP_CLUSTER_3 0x17940 +#define VID_E_UP_CLUSTER_4 0x17EE0 + +#define VID_F_UP_CLUSTER_1 0x18480 +#define VID_F_UP_CLUSTER_2 0x18A20 +#define VID_F_UP_CLUSTER_3 0x18FC0 +#define VID_F_UP_CLUSTER_4 0x19560 + +#define VID_I_UP_CLUSTER_1 0x19B00 +#define VID_I_UP_CLUSTER_2 0x1A0A0 +#define VID_I_UP_CLUSTER_3 0x1A640 +#define VID_I_UP_CLUSTER_4 0x1ABE0 + +#define VID_J_UP_CLUSTER_1 0x1B180 +#define VID_J_UP_CLUSTER_2 0x1B720 +#define VID_J_UP_CLUSTER_3 0x1BCC0 +#define VID_J_UP_CLUSTER_4 0x1C260 + +#define AUD_A_UP_CLUSTER_1 0x1C800 +#define AUD_A_UP_CLUSTER_2 0x1C880 +#define AUD_A_UP_CLUSTER_3 0x1C900 + +#define AUD_B_UP_CLUSTER_1 0x1C980 +#define AUD_B_UP_CLUSTER_2 0x1CA00 +#define AUD_B_UP_CLUSTER_3 0x1CA80 + +#define AUD_C_UP_CLUSTER_1 0x1CB00 +#define AUD_C_UP_CLUSTER_2 0x1CB80 +#define AUD_C_UP_CLUSTER_3 0x1CC00 + +#define AUD_E_UP_CLUSTER_1 0x1CC80 +#define AUD_E_UP_CLUSTER_2 0x1CD00 +#define AUD_E_UP_CLUSTER_3 0x1CD80 + +#define RX_SRAM_POOL_FREE 0x1CE00 +#define RX_SRAM_END 0x1D000 + +// Free Receive SRAM 144 Bytes + +// Transmit SRAM +#define TX_SRAM_POOL_START 0x00000 + +#define VID_A_DOWN_CLUSTER_1 0x00040 +#define VID_A_DOWN_CLUSTER_2 0x005E0 +#define VID_A_DOWN_CLUSTER_3 0x00B80 +#define VID_A_DOWN_CLUSTER_4 0x01120 + +#define VID_B_DOWN_CLUSTER_1 0x016C0 +#define VID_B_DOWN_CLUSTER_2 0x01C60 +#define VID_B_DOWN_CLUSTER_3 0x02200 +#define VID_B_DOWN_CLUSTER_4 0x027A0 + +#define VID_C_DOWN_CLUSTER_1 0x02D40 +#define VID_C_DOWN_CLUSTER_2 0x032E0 +#define VID_C_DOWN_CLUSTER_3 0x03880 +#define VID_C_DOWN_CLUSTER_4 0x03E20 + +#define VID_D_DOWN_CLUSTER_1 0x043C0 +#define VID_D_DOWN_CLUSTER_2 0x04960 +#define VID_D_DOWN_CLUSTER_3 0x04F00 +#define VID_D_DOWN_CLUSTER_4 0x054A0 + +#define VID_E_DOWN_CLUSTER_1 0x05a40 +#define VID_E_DOWN_CLUSTER_2 0x05FE0 +#define VID_E_DOWN_CLUSTER_3 0x06580 +#define VID_E_DOWN_CLUSTER_4 0x06B20 + +#define VID_F_DOWN_CLUSTER_1 0x070C0 +#define VID_F_DOWN_CLUSTER_2 0x07660 +#define VID_F_DOWN_CLUSTER_3 0x07C00 +#define VID_F_DOWN_CLUSTER_4 0x081A0 + +#define VID_G_DOWN_CLUSTER_1 0x08740 +#define VID_G_DOWN_CLUSTER_2 0x08CE0 +#define VID_G_DOWN_CLUSTER_3 0x09280 +#define VID_G_DOWN_CLUSTER_4 0x09820 + +#define VID_H_DOWN_CLUSTER_1 0x09DC0 +#define VID_H_DOWN_CLUSTER_2 0x0A360 +#define VID_H_DOWN_CLUSTER_3 0x0A900 +#define VID_H_DOWN_CLUSTER_4 0x0AEA0 + +#define AUD_A_DOWN_CLUSTER_1 0x0B500 +#define AUD_A_DOWN_CLUSTER_2 0x0B580 +#define AUD_A_DOWN_CLUSTER_3 0x0B600 + +#define AUD_B_DOWN_CLUSTER_1 0x0B680 +#define AUD_B_DOWN_CLUSTER_2 0x0B700 +#define AUD_B_DOWN_CLUSTER_3 0x0B780 + +#define AUD_C_DOWN_CLUSTER_1 0x0B800 +#define AUD_C_DOWN_CLUSTER_2 0x0B880 +#define AUD_C_DOWN_CLUSTER_3 0x0B900 + +#define AUD_D_DOWN_CLUSTER_1 0x0B980 +#define AUD_D_DOWN_CLUSTER_2 0x0BA00 +#define AUD_D_DOWN_CLUSTER_3 0x0BA80 + +#define TX_SRAM_POOL_FREE 0x0BB00 +#define TX_SRAM_END 0x0C000 + +#define BYTES_TO_DWORDS(bcount) ((bcount) >> 2) +#define BYTES_TO_QWORDS(bcount) ((bcount) >> 3) +#define BYTES_TO_OWORDS(bcount) ((bcount) >> 4) + +#define VID_IQ_SIZE_DW BYTES_TO_DWORDS(VID_IQ_SIZE) +#define VID_CDT_SIZE_QW BYTES_TO_QWORDS(VID_CDT_SIZE) +#define VID_CLUSTER_SIZE_OW BYTES_TO_OWORDS(VID_CLUSTER_SIZE) + +#define AUDIO_IQ_SIZE_DW BYTES_TO_DWORDS(AUDIO_IQ_SIZE) +#define AUDIO_CDT_SIZE_QW BYTES_TO_QWORDS(AUDIO_CDT_SIZE) +#define AUDIO_CLUSTER_SIZE_QW BYTES_TO_QWORDS(AUDIO_CLUSTER_SIZE) + +#define MBIF_IQ_SIZE_DW BYTES_TO_DWORDS(MBIF_IQ_SIZE) +#define MBIF_CDT_SIZE_QW BYTES_TO_QWORDS(MBIF_CDT_SIZE) +#define MBIF_CLUSTER_SIZE_OW BYTES_TO_OWORDS(MBIF_CLUSTER_SIZE) + +#endif diff --git a/drivers/staging/cx25821/cx25821-video-upstream-ch2.c b/drivers/staging/cx25821/cx25821-video-upstream-ch2.c new file mode 100644 index 000000000000..c8905e0ac509 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-video-upstream-ch2.c @@ -0,0 +1,835 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821-video.h" +#include "cx25821-video-upstream-ch2.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards"); +MODULE_AUTHOR("Hiep Huynh "); +MODULE_LICENSE("GPL"); + +static int _intr_msk = + FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR; + +static __le32 *cx25821_update_riscprogram_ch2(struct cx25821_dev *dev, + __le32 * rp, unsigned int offset, + unsigned int bpl, u32 sync_line, + unsigned int lines, + int fifo_enable, int field_type) +{ + unsigned int line, i; + int dist_betwn_starts = bpl * 2; + + *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); + + if (USE_RISC_NOOP_VIDEO) { + for (i = 0; i < NUM_NO_OPS; i++) { + *(rp++) = cpu_to_le32(RISC_NOOP); + } + } + + /* scan lines */ + for (line = 0; line < lines; line++) { + *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl); + *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr_ch2 + offset); + *(rp++) = cpu_to_le32(0); /* bits 63-32 */ + + if ((lines <= NTSC_FIELD_HEIGHT) + || (line < (NTSC_FIELD_HEIGHT - 1)) + || !(dev->_isNTSC_ch2)) { + offset += dist_betwn_starts; + } + } + + return rp; +} + +static __le32 *cx25821_risc_field_upstream_ch2(struct cx25821_dev *dev, + __le32 * rp, + dma_addr_t databuf_phys_addr, + unsigned int offset, + u32 sync_line, unsigned int bpl, + unsigned int lines, + int fifo_enable, int field_type) +{ + unsigned int line, i; + struct sram_channel *sram_ch = + &dev->sram_channels[dev->_channel2_upstream_select]; + int dist_betwn_starts = bpl * 2; + + /* sync instruction */ + if (sync_line != NO_SYNC_LINE) { + *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); + } + + if (USE_RISC_NOOP_VIDEO) { + for (i = 0; i < NUM_NO_OPS; i++) { + *(rp++) = cpu_to_le32(RISC_NOOP); + } + } + + /* scan lines */ + for (line = 0; line < lines; line++) { + *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl); + *(rp++) = cpu_to_le32(databuf_phys_addr + offset); + *(rp++) = cpu_to_le32(0); /* bits 63-32 */ + + if ((lines <= NTSC_FIELD_HEIGHT) + || (line < (NTSC_FIELD_HEIGHT - 1)) + || !(dev->_isNTSC_ch2)) { + offset += dist_betwn_starts; + } + + // check if we need to enable the FIFO after the first 4 lines + // For the upstream video channel, the risc engine will enable the FIFO. + if (fifo_enable && line == 3) { + *(rp++) = RISC_WRITECR; + *(rp++) = sram_ch->dma_ctl; + *(rp++) = FLD_VID_FIFO_EN; + *(rp++) = 0x00000001; + } + } + + return rp; +} + +int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev, + struct pci_dev *pci, + unsigned int top_offset, unsigned int bpl, + unsigned int lines) +{ + __le32 *rp; + int fifo_enable = 0; + int singlefield_lines = lines >> 1; //get line count for single field + int odd_num_lines = singlefield_lines; + int frame = 0; + int frame_size = 0; + int databuf_offset = 0; + int risc_program_size = 0; + int risc_flag = RISC_CNT_RESET; + unsigned int bottom_offset = bpl; + dma_addr_t risc_phys_jump_addr; + + if (dev->_isNTSC_ch2) { + odd_num_lines = singlefield_lines + 1; + risc_program_size = FRAME1_VID_PROG_SIZE; + frame_size = + (bpl == + Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 : + FRAME_SIZE_NTSC_Y422; + } else { + risc_program_size = PAL_VID_PROG_SIZE; + frame_size = + (bpl == + Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422; + } + + /* Virtual address of Risc buffer program */ + rp = dev->_dma_virt_addr_ch2; + + for (frame = 0; frame < NUM_FRAMES; frame++) { + databuf_offset = frame_size * frame; + + if (UNSET != top_offset) { + fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE; + rp = cx25821_risc_field_upstream_ch2(dev, rp, + dev-> + _data_buf_phys_addr_ch2 + + databuf_offset, + top_offset, 0, bpl, + odd_num_lines, + fifo_enable, + ODD_FIELD); + } + + fifo_enable = FIFO_DISABLE; + + //Even field + rp = cx25821_risc_field_upstream_ch2(dev, rp, + dev-> + _data_buf_phys_addr_ch2 + + databuf_offset, + bottom_offset, 0x200, bpl, + singlefield_lines, + fifo_enable, EVEN_FIELD); + + if (frame == 0) { + risc_flag = RISC_CNT_RESET; + risc_phys_jump_addr = + dev->_dma_phys_start_addr_ch2 + risc_program_size; + } else { + risc_flag = RISC_CNT_INC; + risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2; + } + + // Loop to 2ndFrameRISC or to Start of Risc program & generate IRQ + *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag); + *(rp++) = cpu_to_le32(risc_phys_jump_addr); + *(rp++) = cpu_to_le32(0); + } + + return 0; +} + +void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev) +{ + struct sram_channel *sram_ch = + &dev->sram_channels[VID_UPSTREAM_SRAM_CHANNEL_J]; + u32 tmp = 0; + + if (!dev->_is_running_ch2) { + printk + ("cx25821: No video file is currently running so return!\n"); + return; + } + //Disable RISC interrupts + tmp = cx_read(sram_ch->int_msk); + cx_write(sram_ch->int_msk, tmp & ~_intr_msk); + + //Turn OFF risc and fifo + tmp = cx_read(sram_ch->dma_ctl); + cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN)); + + //Clear data buffer memory + if (dev->_data_buf_virt_addr_ch2) + memset(dev->_data_buf_virt_addr_ch2, 0, + dev->_data_buf_size_ch2); + + dev->_is_running_ch2 = 0; + dev->_is_first_frame_ch2 = 0; + dev->_frame_count_ch2 = 0; + dev->_file_status_ch2 = END_OF_FILE; + + if (dev->_irq_queues_ch2) { + kfree(dev->_irq_queues_ch2); + dev->_irq_queues_ch2 = NULL; + } + + if (dev->_filename_ch2 != NULL) + kfree(dev->_filename_ch2); + + tmp = cx_read(VID_CH_MODE_SEL); + cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00); +} + +void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev) +{ + if (dev->_is_running_ch2) { + cx25821_stop_upstream_video_ch2(dev); + } + + if (dev->_dma_virt_addr_ch2) { + pci_free_consistent(dev->pci, dev->_risc_size_ch2, + dev->_dma_virt_addr_ch2, + dev->_dma_phys_addr_ch2); + dev->_dma_virt_addr_ch2 = NULL; + } + + if (dev->_data_buf_virt_addr_ch2) { + pci_free_consistent(dev->pci, dev->_data_buf_size_ch2, + dev->_data_buf_virt_addr_ch2, + dev->_data_buf_phys_addr_ch2); + dev->_data_buf_virt_addr_ch2 = NULL; + } +} + +int cx25821_get_frame_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch) +{ + struct file *myfile; + int frame_index_temp = dev->_frame_index_ch2; + int i = 0; + int line_size = + (dev->_pixel_format_ch2 == + PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ; + int frame_size = 0; + int frame_offset = 0; + ssize_t vfs_read_retval = 0; + char mybuf[line_size]; + loff_t file_offset; + loff_t pos; + mm_segment_t old_fs; + + if (dev->_file_status_ch2 == END_OF_FILE) + return 0; + + if (dev->_isNTSC_ch2) { + frame_size = + (line_size == + Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 : + FRAME_SIZE_NTSC_Y422; + } else { + frame_size = + (line_size == + Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422; + } + + frame_offset = (frame_index_temp > 0) ? frame_size : 0; + file_offset = dev->_frame_count_ch2 * frame_size; + + myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0); + + if (IS_ERR(myfile)) { + const int open_errno = -PTR_ERR(myfile); + printk("%s(): ERROR opening file(%s) with errno = %d! \n", + __func__, dev->_filename_ch2, open_errno); + return PTR_ERR(myfile); + } else { + if (!(myfile->f_op)) { + printk("%s: File has no file operations registered!", + __func__); + filp_close(myfile, NULL); + return -EIO; + } + + if (!myfile->f_op->read) { + printk("%s: File has no READ operations registered!", + __func__); + filp_close(myfile, NULL); + return -EIO; + } + + pos = myfile->f_pos; + old_fs = get_fs(); + set_fs(KERNEL_DS); + + for (i = 0; i < dev->_lines_count_ch2; i++) { + pos = file_offset; + + vfs_read_retval = + vfs_read(myfile, mybuf, line_size, &pos); + + if (vfs_read_retval > 0 && vfs_read_retval == line_size + && dev->_data_buf_virt_addr_ch2 != NULL) { + memcpy((void *)(dev->_data_buf_virt_addr_ch2 + + frame_offset / 4), mybuf, + vfs_read_retval); + } + + file_offset += vfs_read_retval; + frame_offset += vfs_read_retval; + + if (vfs_read_retval < line_size) { + printk(KERN_INFO + "Done: exit %s() since no more bytes to read from Video file.\n", + __func__); + break; + } + } + + if (i > 0) + dev->_frame_count_ch2++; + + dev->_file_status_ch2 = + (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE; + + set_fs(old_fs); + filp_close(myfile, NULL); + } + + return 0; +} + +static void cx25821_vidups_handler_ch2(struct work_struct *work) +{ + struct cx25821_dev *dev = + container_of(work, struct cx25821_dev, _irq_work_entry_ch2); + + if (!dev) { + printk("ERROR %s(): since container_of(work_struct) FAILED! \n", + __func__); + return; + } + + cx25821_get_frame_ch2(dev, + &dev->sram_channels[dev-> + _channel2_upstream_select]); +} + +int cx25821_openfile_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch) +{ + struct file *myfile; + int i = 0, j = 0; + int line_size = + (dev->_pixel_format_ch2 == + PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ; + ssize_t vfs_read_retval = 0; + char mybuf[line_size]; + loff_t pos; + loff_t offset = (unsigned long)0; + mm_segment_t old_fs; + + myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0); + + if (IS_ERR(myfile)) { + const int open_errno = -PTR_ERR(myfile); + printk("%s(): ERROR opening file(%s) with errno = %d! \n", + __func__, dev->_filename_ch2, open_errno); + return PTR_ERR(myfile); + } else { + if (!(myfile->f_op)) { + printk("%s: File has no file operations registered!", + __func__); + filp_close(myfile, NULL); + return -EIO; + } + + if (!myfile->f_op->read) { + printk + ("%s: File has no READ operations registered! Returning.", + __func__); + filp_close(myfile, NULL); + return -EIO; + } + + pos = myfile->f_pos; + old_fs = get_fs(); + set_fs(KERNEL_DS); + + for (j = 0; j < NUM_FRAMES; j++) { + for (i = 0; i < dev->_lines_count_ch2; i++) { + pos = offset; + + vfs_read_retval = + vfs_read(myfile, mybuf, line_size, &pos); + + if (vfs_read_retval > 0 + && vfs_read_retval == line_size + && dev->_data_buf_virt_addr_ch2 != NULL) { + memcpy((void *)(dev-> + _data_buf_virt_addr_ch2 + + offset / 4), mybuf, + vfs_read_retval); + } + + offset += vfs_read_retval; + + if (vfs_read_retval < line_size) { + printk(KERN_INFO + "Done: exit %s() since no more bytes to read from Video file.\n", + __func__); + break; + } + } + + if (i > 0) + dev->_frame_count_ch2++; + + if (vfs_read_retval < line_size) { + break; + } + } + + dev->_file_status_ch2 = + (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE; + + set_fs(old_fs); + myfile->f_pos = 0; + filp_close(myfile, NULL); + } + + return 0; +} + +static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev, + struct sram_channel *sram_ch, + int bpl) +{ + int ret = 0; + dma_addr_t dma_addr; + dma_addr_t data_dma_addr; + + if (dev->_dma_virt_addr_ch2 != NULL) { + pci_free_consistent(dev->pci, dev->upstream_riscbuf_size_ch2, + dev->_dma_virt_addr_ch2, + dev->_dma_phys_addr_ch2); + } + + dev->_dma_virt_addr_ch2 = + pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size_ch2, + &dma_addr); + dev->_dma_virt_start_addr_ch2 = dev->_dma_virt_addr_ch2; + dev->_dma_phys_start_addr_ch2 = dma_addr; + dev->_dma_phys_addr_ch2 = dma_addr; + dev->_risc_size_ch2 = dev->upstream_riscbuf_size_ch2; + + if (!dev->_dma_virt_addr_ch2) { + printk + ("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n"); + return -ENOMEM; + } + + //Iniitize at this address until n bytes to 0 + memset(dev->_dma_virt_addr_ch2, 0, dev->_risc_size_ch2); + + if (dev->_data_buf_virt_addr_ch2 != NULL) { + pci_free_consistent(dev->pci, dev->upstream_databuf_size_ch2, + dev->_data_buf_virt_addr_ch2, + dev->_data_buf_phys_addr_ch2); + } + //For Video Data buffer allocation + dev->_data_buf_virt_addr_ch2 = + pci_alloc_consistent(dev->pci, dev->upstream_databuf_size_ch2, + &data_dma_addr); + dev->_data_buf_phys_addr_ch2 = data_dma_addr; + dev->_data_buf_size_ch2 = dev->upstream_databuf_size_ch2; + + if (!dev->_data_buf_virt_addr_ch2) { + printk + ("cx25821: FAILED to allocate memory for data buffer! Returning.\n"); + return -ENOMEM; + } + + //Initialize at this address until n bytes to 0 + memset(dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2); + + ret = cx25821_openfile_ch2(dev, sram_ch); + if (ret < 0) + return ret; + + //Creating RISC programs + ret = + cx25821_risc_buffer_upstream_ch2(dev, dev->pci, 0, bpl, + dev->_lines_count_ch2); + if (ret < 0) { + printk(KERN_INFO + "cx25821: Failed creating Video Upstream Risc programs! \n"); + goto error; + } + + return 0; + + error: + return ret; +} + +int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num, + u32 status) +{ + u32 int_msk_tmp; + struct sram_channel *channel = &dev->sram_channels[chan_num]; + int singlefield_lines = NTSC_FIELD_HEIGHT; + int line_size_in_bytes = Y422_LINE_SZ; + int odd_risc_prog_size = 0; + dma_addr_t risc_phys_jump_addr; + __le32 *rp; + + if (status & FLD_VID_SRC_RISC1) { + // We should only process one program per call + u32 prog_cnt = cx_read(channel->gpcnt); + + //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers + int_msk_tmp = cx_read(channel->int_msk); + cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk); + cx_write(channel->int_stat, _intr_msk); + + spin_lock(&dev->slock); + + dev->_frame_index_ch2 = prog_cnt; + + queue_work(dev->_irq_queues_ch2, &dev->_irq_work_entry_ch2); + + if (dev->_is_first_frame_ch2) { + dev->_is_first_frame_ch2 = 0; + + if (dev->_isNTSC_ch2) { + singlefield_lines += 1; + odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE; + } else { + singlefield_lines = PAL_FIELD_HEIGHT; + odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE; + } + + if (dev->_dma_virt_start_addr_ch2 != NULL) { + line_size_in_bytes = + (dev->_pixel_format_ch2 == + PIXEL_FRMT_411) ? Y411_LINE_SZ : + Y422_LINE_SZ; + risc_phys_jump_addr = + dev->_dma_phys_start_addr_ch2 + + odd_risc_prog_size; + + rp = cx25821_update_riscprogram_ch2(dev, + dev-> + _dma_virt_start_addr_ch2, + TOP_OFFSET, + line_size_in_bytes, + 0x0, + singlefield_lines, + FIFO_DISABLE, + ODD_FIELD); + + // Jump to Even Risc program of 1st Frame + *(rp++) = cpu_to_le32(RISC_JUMP); + *(rp++) = cpu_to_le32(risc_phys_jump_addr); + *(rp++) = cpu_to_le32(0); + } + } + + spin_unlock(&dev->slock); + } + + if (dev->_file_status_ch2 == END_OF_FILE) { + printk("cx25821: EOF Channel 2 Framecount = %d\n", + dev->_frame_count_ch2); + return -1; + } + //ElSE, set the interrupt mask register, re-enable irq. + int_msk_tmp = cx_read(channel->int_msk); + cx_write(channel->int_msk, int_msk_tmp |= _intr_msk); + + return 0; +} + +static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id) +{ + struct cx25821_dev *dev = dev_id; + u32 msk_stat, vid_status; + int handled = 0; + int channel_num = 0; + struct sram_channel *sram_ch; + + if (!dev) + return -1; + + channel_num = VID_UPSTREAM_SRAM_CHANNEL_J; + + sram_ch = &dev->sram_channels[channel_num]; + + msk_stat = cx_read(sram_ch->int_mstat); + vid_status = cx_read(sram_ch->int_stat); + + // Only deal with our interrupt + if (vid_status) { + handled = + cx25821_video_upstream_irq_ch2(dev, channel_num, + vid_status); + } + + if (handled < 0) { + cx25821_stop_upstream_video_ch2(dev); + } else { + handled += handled; + } + + return IRQ_RETVAL(handled); +} + +static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev, + struct sram_channel *ch, int pix_format) +{ + int width = WIDTH_D1; + int height = dev->_lines_count_ch2; + int num_lines, odd_num_lines; + u32 value; + int vip_mode = PIXEL_ENGINE_VIP1; + + value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7); + value &= 0xFFFFFFEF; + value |= dev->_isNTSC_ch2 ? 0 : 0x10; + cx_write(ch->vid_fmt_ctl, value); + + // set number of active pixels in each line. Default is 720 pixels in both NTSC and PAL format + cx_write(ch->vid_active_ctl1, width); + + num_lines = (height / 2) & 0x3FF; + odd_num_lines = num_lines; + + if (dev->_isNTSC_ch2) { + odd_num_lines += 1; + } + + value = (num_lines << 16) | odd_num_lines; + + // set number of active lines in field 0 (top) and field 1 (bottom) + cx_write(ch->vid_active_ctl2, value); + + cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3); +} + +int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev, + struct sram_channel *sram_ch) +{ + u32 tmp = 0; + int err = 0; + + // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C + tmp = cx_read(VID_CH_MODE_SEL); + cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF); + + // Set the physical start address of the RISC program in the initial program counter(IPC) member of the cmds. + cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2); + cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */ + + /* reset counter */ + cx_write(sram_ch->gpcnt_ctl, 3); + + // Clear our bits from the interrupt status register. + cx_write(sram_ch->int_stat, _intr_msk); + + //Set the interrupt mask register, enable irq. + cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit)); + tmp = cx_read(sram_ch->int_msk); + cx_write(sram_ch->int_msk, tmp |= _intr_msk); + + err = + request_irq(dev->pci->irq, cx25821_upstream_irq_ch2, + IRQF_SHARED | IRQF_DISABLED, dev->name, dev); + if (err < 0) { + printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name, + dev->pci->irq); + goto fail_irq; + } + // Start the DMA engine + tmp = cx_read(sram_ch->dma_ctl); + cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN); + + dev->_is_running_ch2 = 1; + dev->_is_first_frame_ch2 = 1; + + return 0; + + fail_irq: + cx25821_dev_unregister(dev); + return err; +} + +int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select, + int pixel_format) +{ + struct sram_channel *sram_ch; + u32 tmp; + int retval = 0; + int err = 0; + int data_frame_size = 0; + int risc_buffer_size = 0; + int str_length = 0; + + if (dev->_is_running_ch2) { + printk("Video Channel is still running so return!\n"); + return 0; + } + + dev->_channel2_upstream_select = channel_select; + sram_ch = &dev->sram_channels[channel_select]; + + INIT_WORK(&dev->_irq_work_entry_ch2, cx25821_vidups_handler_ch2); + dev->_irq_queues_ch2 = + create_singlethread_workqueue("cx25821_workqueue2"); + + if (!dev->_irq_queues_ch2) { + printk + ("cx25821: create_singlethread_workqueue() for Video FAILED!\n"); + return -ENOMEM; + } + // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C + tmp = cx_read(VID_CH_MODE_SEL); + cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF); + + dev->_is_running_ch2 = 0; + dev->_frame_count_ch2 = 0; + dev->_file_status_ch2 = RESET_STATUS; + dev->_lines_count_ch2 = dev->_isNTSC_ch2 ? 480 : 576; + dev->_pixel_format_ch2 = pixel_format; + dev->_line_size_ch2 = + (dev->_pixel_format_ch2 == + PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2; + data_frame_size = dev->_isNTSC_ch2 ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ; + risc_buffer_size = + dev->_isNTSC_ch2 ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE; + + if (dev->input_filename_ch2) { + str_length = strlen(dev->input_filename_ch2); + dev->_filename_ch2 = + (char *)kmalloc(str_length + 1, GFP_KERNEL); + + if (!dev->_filename_ch2) + goto error; + + memcpy(dev->_filename_ch2, dev->input_filename_ch2, + str_length + 1); + } else { + str_length = strlen(dev->_defaultname_ch2); + dev->_filename_ch2 = + (char *)kmalloc(str_length + 1, GFP_KERNEL); + + if (!dev->_filename_ch2) + goto error; + + memcpy(dev->_filename_ch2, dev->_defaultname_ch2, + str_length + 1); + } + + //Default if filename is empty string + if (strcmp(dev->input_filename_ch2, "") == 0) { + if (dev->_isNTSC_ch2) { + dev->_filename_ch2 = + (dev->_pixel_format_ch2 == + PIXEL_FRMT_411) ? "/root/vid411.yuv" : + "/root/vidtest.yuv"; + } else { + dev->_filename_ch2 = + (dev->_pixel_format_ch2 == + PIXEL_FRMT_411) ? "/root/pal411.yuv" : + "/root/pal422.yuv"; + } + } + + retval = + cx25821_sram_channel_setup_upstream(dev, sram_ch, + dev->_line_size_ch2, 0); + + /* setup fifo + format */ + cx25821_set_pixelengine_ch2(dev, sram_ch, dev->_pixel_format_ch2); + + dev->upstream_riscbuf_size_ch2 = risc_buffer_size * 2; + dev->upstream_databuf_size_ch2 = data_frame_size * 2; + + //Allocating buffers and prepare RISC program + retval = + cx25821_upstream_buffer_prepare_ch2(dev, sram_ch, + dev->_line_size_ch2); + if (retval < 0) { + printk(KERN_ERR + "%s: Failed to set up Video upstream buffers!\n", + dev->name); + goto error; + } + + cx25821_start_video_dma_upstream_ch2(dev, sram_ch); + + return 0; + + error: + cx25821_dev_unregister(dev); + + return err; +} diff --git a/drivers/staging/cx25821/cx25821-video-upstream-ch2.h b/drivers/staging/cx25821/cx25821-video-upstream-ch2.h new file mode 100644 index 000000000000..73feea114c1c --- /dev/null +++ b/drivers/staging/cx25821/cx25821-video-upstream-ch2.h @@ -0,0 +1,101 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#define OPEN_FILE_1 0 +#define NUM_PROGS 8 +#define NUM_FRAMES 2 +#define ODD_FIELD 0 +#define EVEN_FIELD 1 +#define TOP_OFFSET 0 +#define FIFO_DISABLE 0 +#define FIFO_ENABLE 1 +#define TEST_FRAMES 5 +#define END_OF_FILE 0 +#define IN_PROGRESS 1 +#define RESET_STATUS -1 +#define NUM_NO_OPS 5 + +// PAL and NTSC line sizes and number of lines. +#define WIDTH_D1 720 +#define NTSC_LINES_PER_FRAME 480 +#define PAL_LINES_PER_FRAME 576 +#define PAL_LINE_SZ 1440 +#define Y422_LINE_SZ 1440 +#define Y411_LINE_SZ 1080 +#define NTSC_FIELD_HEIGHT 240 +#define NTSC_ODD_FLD_LINES 241 +#define PAL_FIELD_HEIGHT 288 + +#define FRAME_SIZE_NTSC_Y422 (NTSC_LINES_PER_FRAME * Y422_LINE_SZ) +#define FRAME_SIZE_NTSC_Y411 (NTSC_LINES_PER_FRAME * Y411_LINE_SZ) +#define FRAME_SIZE_PAL_Y422 (PAL_LINES_PER_FRAME * Y422_LINE_SZ) +#define FRAME_SIZE_PAL_Y411 (PAL_LINES_PER_FRAME * Y411_LINE_SZ) + +#define NTSC_DATA_BUF_SZ (Y422_LINE_SZ * NTSC_LINES_PER_FRAME) +#define PAL_DATA_BUF_SZ (Y422_LINE_SZ * PAL_LINES_PER_FRAME) + +#define RISC_WRITECR_INSTRUCTION_SIZE 16 +#define RISC_SYNC_INSTRUCTION_SIZE 4 +#define JUMP_INSTRUCTION_SIZE 12 +#define MAXSIZE_NO_OPS 36 +#define DWORD_SIZE 4 + +#define USE_RISC_NOOP_VIDEO 1 + +#ifdef USE_RISC_NOOP_VIDEO +#define PAL_US_VID_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \ + RISC_SYNC_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE) + +#define PAL_RISC_BUF_SIZE (2 * PAL_US_VID_PROG_SIZE) + +#define PAL_VID_PROG_SIZE ((PAL_FIELD_HEIGHT*2) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \ + RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE + 2*NUM_NO_OPS*DWORD_SIZE) + +#define ODD_FLD_PAL_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + \ + RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE) + +#define NTSC_US_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \ + JUMP_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE) + +#define NTSC_RISC_BUF_SIZE (2 * (RISC_SYNC_INSTRUCTION_SIZE + NTSC_US_VID_PROG_SIZE)) + +#define FRAME1_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + NTSC_FIELD_HEIGHT) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \ + RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE + 2*NUM_NO_OPS*DWORD_SIZE) +#define ODD_FLD_NTSC_PROG_SIZE ((NTSC_ODD_FLD_LINES) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + \ + RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE) +#endif + +#ifndef USE_RISC_NOOP_VIDEO +#define PAL_US_VID_PROG_SIZE ((PAL_FIELD_HEIGHT + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE ) +#define PAL_RISC_BUF_SIZE ( 2 * (RISC_SYNC_INSTRUCTION_SIZE + PAL_US_VID_PROG_SIZE) ) +#define PAL_VID_PROG_SIZE ((PAL_FIELD_HEIGHT*2) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \ + RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE ) +#define ODD_FLD_PAL_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE ) +#define ODD_FLD_NTSC_PROG_SIZE ((NTSC_ODD_FLD_LINES) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE ) +#define NTSC_US_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE) +#define NTSC_RISC_BUF_SIZE (2 * (RISC_SYNC_INSTRUCTION_SIZE + NTSC_US_VID_PROG_SIZE) ) +#define FRAME1_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + NTSC_FIELD_HEIGHT) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \ + RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE ) +#endif diff --git a/drivers/staging/cx25821/cx25821-video-upstream.c b/drivers/staging/cx25821/cx25821-video-upstream.c new file mode 100644 index 000000000000..3d7dd3f66541 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-video-upstream.c @@ -0,0 +1,894 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821-video.h" +#include "cx25821-video-upstream.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards"); +MODULE_AUTHOR("Hiep Huynh "); +MODULE_LICENSE("GPL"); + +static int _intr_msk = + FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR; + +int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev, + struct sram_channel *ch, + unsigned int bpl, u32 risc) +{ + unsigned int i, lines; + u32 cdt; + + if (ch->cmds_start == 0) { + cx_write(ch->ptr1_reg, 0); + cx_write(ch->ptr2_reg, 0); + cx_write(ch->cnt2_reg, 0); + cx_write(ch->cnt1_reg, 0); + return 0; + } + + bpl = (bpl + 7) & ~7; /* alignment */ + cdt = ch->cdt; + lines = ch->fifo_size / bpl; + + if (lines > 4) { + lines = 4; + } + + BUG_ON(lines < 2); + + /* write CDT */ + for (i = 0; i < lines; i++) { + cx_write(cdt + 16 * i, ch->fifo_start + bpl * i); + cx_write(cdt + 16 * i + 4, 0); + cx_write(cdt + 16 * i + 8, 0); + cx_write(cdt + 16 * i + 12, 0); + } + + /* write CMDS */ + cx_write(ch->cmds_start + 0, risc); + + cx_write(ch->cmds_start + 4, 0); + cx_write(ch->cmds_start + 8, cdt); + cx_write(ch->cmds_start + 12, (lines * 16) >> 3); + cx_write(ch->cmds_start + 16, ch->ctrl_start); + + cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW); + + for (i = 24; i < 80; i += 4) + cx_write(ch->cmds_start + i, 0); + + /* fill registers */ + cx_write(ch->ptr1_reg, ch->fifo_start); + cx_write(ch->ptr2_reg, cdt); + cx_write(ch->cnt2_reg, (lines * 16) >> 3); + cx_write(ch->cnt1_reg, (bpl >> 3) - 1); + + return 0; +} + +static __le32 *cx25821_update_riscprogram(struct cx25821_dev *dev, + __le32 * rp, unsigned int offset, + unsigned int bpl, u32 sync_line, + unsigned int lines, int fifo_enable, + int field_type) +{ + unsigned int line, i; + int dist_betwn_starts = bpl * 2; + + *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); + + if (USE_RISC_NOOP_VIDEO) { + for (i = 0; i < NUM_NO_OPS; i++) { + *(rp++) = cpu_to_le32(RISC_NOOP); + } + } + + /* scan lines */ + for (line = 0; line < lines; line++) { + *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl); + *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr + offset); + *(rp++) = cpu_to_le32(0); /* bits 63-32 */ + + if ((lines <= NTSC_FIELD_HEIGHT) + || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) { + offset += dist_betwn_starts; + } + } + + return rp; +} + +static __le32 *cx25821_risc_field_upstream(struct cx25821_dev *dev, __le32 * rp, + dma_addr_t databuf_phys_addr, + unsigned int offset, u32 sync_line, + unsigned int bpl, unsigned int lines, + int fifo_enable, int field_type) +{ + unsigned int line, i; + struct sram_channel *sram_ch = + &dev->sram_channels[dev->_channel_upstream_select]; + int dist_betwn_starts = bpl * 2; + + /* sync instruction */ + if (sync_line != NO_SYNC_LINE) { + *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); + } + + if (USE_RISC_NOOP_VIDEO) { + for (i = 0; i < NUM_NO_OPS; i++) { + *(rp++) = cpu_to_le32(RISC_NOOP); + } + } + + /* scan lines */ + for (line = 0; line < lines; line++) { + *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl); + *(rp++) = cpu_to_le32(databuf_phys_addr + offset); + *(rp++) = cpu_to_le32(0); /* bits 63-32 */ + + if ((lines <= NTSC_FIELD_HEIGHT) + || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) { + offset += dist_betwn_starts; //to skip the other field line + } + + // check if we need to enable the FIFO after the first 4 lines + // For the upstream video channel, the risc engine will enable the FIFO. + if (fifo_enable && line == 3) { + *(rp++) = RISC_WRITECR; + *(rp++) = sram_ch->dma_ctl; + *(rp++) = FLD_VID_FIFO_EN; + *(rp++) = 0x00000001; + } + } + + return rp; +} + +int cx25821_risc_buffer_upstream(struct cx25821_dev *dev, + struct pci_dev *pci, + unsigned int top_offset, + unsigned int bpl, unsigned int lines) +{ + __le32 *rp; + int fifo_enable = 0; + int singlefield_lines = lines >> 1; //get line count for single field + int odd_num_lines = singlefield_lines; + int frame = 0; + int frame_size = 0; + int databuf_offset = 0; + int risc_program_size = 0; + int risc_flag = RISC_CNT_RESET; + unsigned int bottom_offset = bpl; + dma_addr_t risc_phys_jump_addr; + + if (dev->_isNTSC) { + odd_num_lines = singlefield_lines + 1; + risc_program_size = FRAME1_VID_PROG_SIZE; + frame_size = + (bpl == + Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 : + FRAME_SIZE_NTSC_Y422; + } else { + risc_program_size = PAL_VID_PROG_SIZE; + frame_size = + (bpl == + Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422; + } + + /* Virtual address of Risc buffer program */ + rp = dev->_dma_virt_addr; + + for (frame = 0; frame < NUM_FRAMES; frame++) { + databuf_offset = frame_size * frame; + + if (UNSET != top_offset) { + fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE; + rp = cx25821_risc_field_upstream(dev, rp, + dev-> + _data_buf_phys_addr + + databuf_offset, + top_offset, 0, bpl, + odd_num_lines, + fifo_enable, + ODD_FIELD); + } + + fifo_enable = FIFO_DISABLE; + + //Even Field + rp = cx25821_risc_field_upstream(dev, rp, + dev->_data_buf_phys_addr + + databuf_offset, bottom_offset, + 0x200, bpl, singlefield_lines, + fifo_enable, EVEN_FIELD); + + if (frame == 0) { + risc_flag = RISC_CNT_RESET; + risc_phys_jump_addr = + dev->_dma_phys_start_addr + risc_program_size; + } else { + risc_phys_jump_addr = dev->_dma_phys_start_addr; + risc_flag = RISC_CNT_INC; + } + + // Loop to 2ndFrameRISC or to Start of Risc program & generate IRQ + *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag); + *(rp++) = cpu_to_le32(risc_phys_jump_addr); + *(rp++) = cpu_to_le32(0); + } + + return 0; +} + +void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev) +{ + struct sram_channel *sram_ch = + &dev->sram_channels[VID_UPSTREAM_SRAM_CHANNEL_I]; + u32 tmp = 0; + + if (!dev->_is_running) { + printk + ("cx25821: No video file is currently running so return!\n"); + return; + } + //Disable RISC interrupts + tmp = cx_read(sram_ch->int_msk); + cx_write(sram_ch->int_msk, tmp & ~_intr_msk); + + //Turn OFF risc and fifo enable + tmp = cx_read(sram_ch->dma_ctl); + cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN)); + + //Clear data buffer memory + if (dev->_data_buf_virt_addr) + memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size); + + dev->_is_running = 0; + dev->_is_first_frame = 0; + dev->_frame_count = 0; + dev->_file_status = END_OF_FILE; + + if (dev->_irq_queues) { + kfree(dev->_irq_queues); + dev->_irq_queues = NULL; + } + + if (dev->_filename != NULL) + kfree(dev->_filename); + + tmp = cx_read(VID_CH_MODE_SEL); + cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00); +} + +void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev) +{ + if (dev->_is_running) { + cx25821_stop_upstream_video_ch1(dev); + } + + if (dev->_dma_virt_addr) { + pci_free_consistent(dev->pci, dev->_risc_size, + dev->_dma_virt_addr, dev->_dma_phys_addr); + dev->_dma_virt_addr = NULL; + } + + if (dev->_data_buf_virt_addr) { + pci_free_consistent(dev->pci, dev->_data_buf_size, + dev->_data_buf_virt_addr, + dev->_data_buf_phys_addr); + dev->_data_buf_virt_addr = NULL; + } +} + +int cx25821_get_frame(struct cx25821_dev *dev, struct sram_channel *sram_ch) +{ + struct file *myfile; + int frame_index_temp = dev->_frame_index; + int i = 0; + int line_size = + (dev->_pixel_format == + PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ; + int frame_size = 0; + int frame_offset = 0; + ssize_t vfs_read_retval = 0; + char mybuf[line_size]; + loff_t file_offset; + loff_t pos; + mm_segment_t old_fs; + + if (dev->_file_status == END_OF_FILE) + return 0; + + if (dev->_isNTSC) { + frame_size = + (line_size == + Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 : + FRAME_SIZE_NTSC_Y422; + } else { + frame_size = + (line_size == + Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422; + } + + frame_offset = (frame_index_temp > 0) ? frame_size : 0; + file_offset = dev->_frame_count * frame_size; + + myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0); + + if (IS_ERR(myfile)) { + const int open_errno = -PTR_ERR(myfile); + printk("%s(): ERROR opening file(%s) with errno = %d! \n", + __func__, dev->_filename, open_errno); + return PTR_ERR(myfile); + } else { + if (!(myfile->f_op)) { + printk("%s: File has no file operations registered!", + __func__); + filp_close(myfile, NULL); + return -EIO; + } + + if (!myfile->f_op->read) { + printk("%s: File has no READ operations registered!", + __func__); + filp_close(myfile, NULL); + return -EIO; + } + + pos = myfile->f_pos; + old_fs = get_fs(); + set_fs(KERNEL_DS); + + for (i = 0; i < dev->_lines_count; i++) { + pos = file_offset; + + vfs_read_retval = + vfs_read(myfile, mybuf, line_size, &pos); + + if (vfs_read_retval > 0 && vfs_read_retval == line_size + && dev->_data_buf_virt_addr != NULL) { + memcpy((void *)(dev->_data_buf_virt_addr + + frame_offset / 4), mybuf, + vfs_read_retval); + } + + file_offset += vfs_read_retval; + frame_offset += vfs_read_retval; + + if (vfs_read_retval < line_size) { + printk(KERN_INFO + "Done: exit %s() since no more bytes to read from Video file.\n", + __func__); + break; + } + } + + if (i > 0) + dev->_frame_count++; + + dev->_file_status = + (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE; + + set_fs(old_fs); + filp_close(myfile, NULL); + } + + return 0; +} + +static void cx25821_vidups_handler(struct work_struct *work) +{ + struct cx25821_dev *dev = + container_of(work, struct cx25821_dev, _irq_work_entry); + + if (!dev) { + printk("ERROR %s(): since container_of(work_struct) FAILED! \n", + __func__); + return; + } + + cx25821_get_frame(dev, + &dev->sram_channels[dev->_channel_upstream_select]); +} + +int cx25821_openfile(struct cx25821_dev *dev, struct sram_channel *sram_ch) +{ + struct file *myfile; + int i = 0, j = 0; + int line_size = + (dev->_pixel_format == + PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ; + ssize_t vfs_read_retval = 0; + char mybuf[line_size]; + loff_t pos; + loff_t offset = (unsigned long)0; + mm_segment_t old_fs; + + myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0); + + if (IS_ERR(myfile)) { + const int open_errno = -PTR_ERR(myfile); + printk("%s(): ERROR opening file(%s) with errno = %d! \n", + __func__, dev->_filename, open_errno); + return PTR_ERR(myfile); + } else { + if (!(myfile->f_op)) { + printk("%s: File has no file operations registered!", + __func__); + filp_close(myfile, NULL); + return -EIO; + } + + if (!myfile->f_op->read) { + printk + ("%s: File has no READ operations registered! Returning.", + __func__); + filp_close(myfile, NULL); + return -EIO; + } + + pos = myfile->f_pos; + old_fs = get_fs(); + set_fs(KERNEL_DS); + + for (j = 0; j < NUM_FRAMES; j++) { + for (i = 0; i < dev->_lines_count; i++) { + pos = offset; + + vfs_read_retval = + vfs_read(myfile, mybuf, line_size, &pos); + + if (vfs_read_retval > 0 + && vfs_read_retval == line_size + && dev->_data_buf_virt_addr != NULL) { + memcpy((void *)(dev-> + _data_buf_virt_addr + + offset / 4), mybuf, + vfs_read_retval); + } + + offset += vfs_read_retval; + + if (vfs_read_retval < line_size) { + printk(KERN_INFO + "Done: exit %s() since no more bytes to read from Video file.\n", + __func__); + break; + } + } + + if (i > 0) + dev->_frame_count++; + + if (vfs_read_retval < line_size) { + break; + } + } + + dev->_file_status = + (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE; + + set_fs(old_fs); + myfile->f_pos = 0; + filp_close(myfile, NULL); + } + + return 0; +} + +int cx25821_upstream_buffer_prepare(struct cx25821_dev *dev, + struct sram_channel *sram_ch, int bpl) +{ + int ret = 0; + dma_addr_t dma_addr; + dma_addr_t data_dma_addr; + + if (dev->_dma_virt_addr != NULL) { + pci_free_consistent(dev->pci, dev->upstream_riscbuf_size, + dev->_dma_virt_addr, dev->_dma_phys_addr); + } + + dev->_dma_virt_addr = + pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size, + &dma_addr); + dev->_dma_virt_start_addr = dev->_dma_virt_addr; + dev->_dma_phys_start_addr = dma_addr; + dev->_dma_phys_addr = dma_addr; + dev->_risc_size = dev->upstream_riscbuf_size; + + if (!dev->_dma_virt_addr) { + printk + ("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n"); + return -ENOMEM; + } + + //Clear memory at address + memset(dev->_dma_virt_addr, 0, dev->_risc_size); + + if (dev->_data_buf_virt_addr != NULL) { + pci_free_consistent(dev->pci, dev->upstream_databuf_size, + dev->_data_buf_virt_addr, + dev->_data_buf_phys_addr); + } + //For Video Data buffer allocation + dev->_data_buf_virt_addr = + pci_alloc_consistent(dev->pci, dev->upstream_databuf_size, + &data_dma_addr); + dev->_data_buf_phys_addr = data_dma_addr; + dev->_data_buf_size = dev->upstream_databuf_size; + + if (!dev->_data_buf_virt_addr) { + printk + ("cx25821: FAILED to allocate memory for data buffer! Returning.\n"); + return -ENOMEM; + } + + //Clear memory at address + memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size); + + ret = cx25821_openfile(dev, sram_ch); + if (ret < 0) + return ret; + + //Create RISC programs + ret = + cx25821_risc_buffer_upstream(dev, dev->pci, 0, bpl, + dev->_lines_count); + if (ret < 0) { + printk(KERN_INFO + "cx25821: Failed creating Video Upstream Risc programs! \n"); + goto error; + } + + return 0; + + error: + return ret; +} + +int cx25821_video_upstream_irq(struct cx25821_dev *dev, int chan_num, + u32 status) +{ + u32 int_msk_tmp; + struct sram_channel *channel = &dev->sram_channels[chan_num]; + int singlefield_lines = NTSC_FIELD_HEIGHT; + int line_size_in_bytes = Y422_LINE_SZ; + int odd_risc_prog_size = 0; + dma_addr_t risc_phys_jump_addr; + __le32 *rp; + + if (status & FLD_VID_SRC_RISC1) { + // We should only process one program per call + u32 prog_cnt = cx_read(channel->gpcnt); + + //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers + int_msk_tmp = cx_read(channel->int_msk); + cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk); + cx_write(channel->int_stat, _intr_msk); + + spin_lock(&dev->slock); + + dev->_frame_index = prog_cnt; + + queue_work(dev->_irq_queues, &dev->_irq_work_entry); + + if (dev->_is_first_frame) { + dev->_is_first_frame = 0; + + if (dev->_isNTSC) { + singlefield_lines += 1; + odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE; + } else { + singlefield_lines = PAL_FIELD_HEIGHT; + odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE; + } + + if (dev->_dma_virt_start_addr != NULL) { + line_size_in_bytes = + (dev->_pixel_format == + PIXEL_FRMT_411) ? Y411_LINE_SZ : + Y422_LINE_SZ; + risc_phys_jump_addr = + dev->_dma_phys_start_addr + + odd_risc_prog_size; + + rp = cx25821_update_riscprogram(dev, + dev-> + _dma_virt_start_addr, + TOP_OFFSET, + line_size_in_bytes, + 0x0, + singlefield_lines, + FIFO_DISABLE, + ODD_FIELD); + + // Jump to Even Risc program of 1st Frame + *(rp++) = cpu_to_le32(RISC_JUMP); + *(rp++) = cpu_to_le32(risc_phys_jump_addr); + *(rp++) = cpu_to_le32(0); + } + } + + spin_unlock(&dev->slock); + } else { + if (status & FLD_VID_SRC_UF) + printk + ("%s: Video Received Underflow Error Interrupt!\n", + __func__); + + if (status & FLD_VID_SRC_SYNC) + printk("%s: Video Received Sync Error Interrupt!\n", + __func__); + + if (status & FLD_VID_SRC_OPC_ERR) + printk("%s: Video Received OpCode Error Interrupt!\n", + __func__); + } + + if (dev->_file_status == END_OF_FILE) { + printk("cx25821: EOF Channel 1 Framecount = %d\n", + dev->_frame_count); + return -1; + } + //ElSE, set the interrupt mask register, re-enable irq. + int_msk_tmp = cx_read(channel->int_msk); + cx_write(channel->int_msk, int_msk_tmp |= _intr_msk); + + return 0; +} + +static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id) +{ + struct cx25821_dev *dev = dev_id; + u32 msk_stat, vid_status; + int handled = 0; + int channel_num = 0; + struct sram_channel *sram_ch; + + if (!dev) + return -1; + + channel_num = VID_UPSTREAM_SRAM_CHANNEL_I; + + sram_ch = &dev->sram_channels[channel_num]; + + msk_stat = cx_read(sram_ch->int_mstat); + vid_status = cx_read(sram_ch->int_stat); + + // Only deal with our interrupt + if (vid_status) { + handled = + cx25821_video_upstream_irq(dev, channel_num, vid_status); + } + + if (handled < 0) { + cx25821_stop_upstream_video_ch1(dev); + } else { + handled += handled; + } + + return IRQ_RETVAL(handled); +} + +void cx25821_set_pixelengine(struct cx25821_dev *dev, struct sram_channel *ch, + int pix_format) +{ + int width = WIDTH_D1; + int height = dev->_lines_count; + int num_lines, odd_num_lines; + u32 value; + int vip_mode = OUTPUT_FRMT_656; + + value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7); + value &= 0xFFFFFFEF; + value |= dev->_isNTSC ? 0 : 0x10; + cx_write(ch->vid_fmt_ctl, value); + + // set number of active pixels in each line. Default is 720 pixels in both NTSC and PAL format + cx_write(ch->vid_active_ctl1, width); + + num_lines = (height / 2) & 0x3FF; + odd_num_lines = num_lines; + + if (dev->_isNTSC) { + odd_num_lines += 1; + } + + value = (num_lines << 16) | odd_num_lines; + + // set number of active lines in field 0 (top) and field 1 (bottom) + cx_write(ch->vid_active_ctl2, value); + + cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3); +} + +int cx25821_start_video_dma_upstream(struct cx25821_dev *dev, + struct sram_channel *sram_ch) +{ + u32 tmp = 0; + int err = 0; + + // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C + tmp = cx_read(VID_CH_MODE_SEL); + cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF); + + // Set the physical start address of the RISC program in the initial program counter(IPC) member of the cmds. + cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr); + cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */ + + /* reset counter */ + cx_write(sram_ch->gpcnt_ctl, 3); + + // Clear our bits from the interrupt status register. + cx_write(sram_ch->int_stat, _intr_msk); + + //Set the interrupt mask register, enable irq. + cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit)); + tmp = cx_read(sram_ch->int_msk); + cx_write(sram_ch->int_msk, tmp |= _intr_msk); + + err = + request_irq(dev->pci->irq, cx25821_upstream_irq, + IRQF_SHARED | IRQF_DISABLED, dev->name, dev); + if (err < 0) { + printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name, + dev->pci->irq); + goto fail_irq; + } + + // Start the DMA engine + tmp = cx_read(sram_ch->dma_ctl); + cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN); + + dev->_is_running = 1; + dev->_is_first_frame = 1; + + return 0; + + fail_irq: + cx25821_dev_unregister(dev); + return err; +} + +int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, int channel_select, + int pixel_format) +{ + struct sram_channel *sram_ch; + u32 tmp; + int retval = 0; + int err = 0; + int data_frame_size = 0; + int risc_buffer_size = 0; + int str_length = 0; + + if (dev->_is_running) { + printk("Video Channel is still running so return!\n"); + return 0; + } + + dev->_channel_upstream_select = channel_select; + sram_ch = &dev->sram_channels[channel_select]; + + INIT_WORK(&dev->_irq_work_entry, cx25821_vidups_handler); + dev->_irq_queues = create_singlethread_workqueue("cx25821_workqueue"); + + if (!dev->_irq_queues) { + printk + ("cx25821: create_singlethread_workqueue() for Video FAILED!\n"); + return -ENOMEM; + } + // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C + tmp = cx_read(VID_CH_MODE_SEL); + cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF); + + dev->_is_running = 0; + dev->_frame_count = 0; + dev->_file_status = RESET_STATUS; + dev->_lines_count = dev->_isNTSC ? 480 : 576; + dev->_pixel_format = pixel_format; + dev->_line_size = + (dev->_pixel_format == + PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2; + data_frame_size = dev->_isNTSC ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ; + risc_buffer_size = + dev->_isNTSC ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE; + + if (dev->input_filename) { + str_length = strlen(dev->input_filename); + dev->_filename = (char *)kmalloc(str_length + 1, GFP_KERNEL); + + if (!dev->_filename) + goto error; + + memcpy(dev->_filename, dev->input_filename, str_length + 1); + } else { + str_length = strlen(dev->_defaultname); + dev->_filename = (char *)kmalloc(str_length + 1, GFP_KERNEL); + + if (!dev->_filename) + goto error; + + memcpy(dev->_filename, dev->_defaultname, str_length + 1); + } + + //Default if filename is empty string + if (strcmp(dev->input_filename, "") == 0) { + if (dev->_isNTSC) { + dev->_filename = + (dev->_pixel_format == + PIXEL_FRMT_411) ? "/root/vid411.yuv" : + "/root/vidtest.yuv"; + } else { + dev->_filename = + (dev->_pixel_format == + PIXEL_FRMT_411) ? "/root/pal411.yuv" : + "/root/pal422.yuv"; + } + } + + dev->_is_running = 0; + dev->_frame_count = 0; + dev->_file_status = RESET_STATUS; + dev->_lines_count = dev->_isNTSC ? 480 : 576; + dev->_pixel_format = pixel_format; + dev->_line_size = + (dev->_pixel_format == + PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2; + + retval = + cx25821_sram_channel_setup_upstream(dev, sram_ch, dev->_line_size, + 0); + + /* setup fifo + format */ + cx25821_set_pixelengine(dev, sram_ch, dev->_pixel_format); + + dev->upstream_riscbuf_size = risc_buffer_size * 2; + dev->upstream_databuf_size = data_frame_size * 2; + + //Allocating buffers and prepare RISC program + retval = cx25821_upstream_buffer_prepare(dev, sram_ch, dev->_line_size); + if (retval < 0) { + printk(KERN_ERR + "%s: Failed to set up Video upstream buffers!\n", + dev->name); + goto error; + } + + cx25821_start_video_dma_upstream(dev, sram_ch); + + return 0; + + error: + cx25821_dev_unregister(dev); + + return err; +} diff --git a/drivers/staging/cx25821/cx25821-video-upstream.h b/drivers/staging/cx25821/cx25821-video-upstream.h new file mode 100644 index 000000000000..cc9f93842514 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-video-upstream.h @@ -0,0 +1,109 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#define OUTPUT_FRMT_656 0 +#define OPEN_FILE_1 0 +#define NUM_PROGS 8 +#define NUM_FRAMES 2 +#define ODD_FIELD 0 +#define EVEN_FIELD 1 +#define TOP_OFFSET 0 +#define FIFO_DISABLE 0 +#define FIFO_ENABLE 1 +#define TEST_FRAMES 5 +#define END_OF_FILE 0 +#define IN_PROGRESS 1 +#define RESET_STATUS -1 +#define NUM_NO_OPS 5 + +// PAL and NTSC line sizes and number of lines. +#define WIDTH_D1 720 +#define NTSC_LINES_PER_FRAME 480 +#define PAL_LINES_PER_FRAME 576 +#define PAL_LINE_SZ 1440 +#define Y422_LINE_SZ 1440 +#define Y411_LINE_SZ 1080 +#define NTSC_FIELD_HEIGHT 240 +#define NTSC_ODD_FLD_LINES 241 +#define PAL_FIELD_HEIGHT 288 + +#define FRAME_SIZE_NTSC_Y422 (NTSC_LINES_PER_FRAME * Y422_LINE_SZ) +#define FRAME_SIZE_NTSC_Y411 (NTSC_LINES_PER_FRAME * Y411_LINE_SZ) +#define FRAME_SIZE_PAL_Y422 (PAL_LINES_PER_FRAME * Y422_LINE_SZ) +#define FRAME_SIZE_PAL_Y411 (PAL_LINES_PER_FRAME * Y411_LINE_SZ) + +#define NTSC_DATA_BUF_SZ (Y422_LINE_SZ * NTSC_LINES_PER_FRAME) +#define PAL_DATA_BUF_SZ (Y422_LINE_SZ * PAL_LINES_PER_FRAME) + +#define RISC_WRITECR_INSTRUCTION_SIZE 16 +#define RISC_SYNC_INSTRUCTION_SIZE 4 +#define JUMP_INSTRUCTION_SIZE 12 +#define MAXSIZE_NO_OPS 36 +#define DWORD_SIZE 4 + +#define USE_RISC_NOOP_VIDEO 1 + +#ifdef USE_RISC_NOOP_VIDEO +#define PAL_US_VID_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \ + RISC_SYNC_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE) + +#define PAL_RISC_BUF_SIZE (2 * PAL_US_VID_PROG_SIZE) + +#define PAL_VID_PROG_SIZE ((PAL_FIELD_HEIGHT*2) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \ + RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE + 2*NUM_NO_OPS*DWORD_SIZE) + +#define ODD_FLD_PAL_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + \ + RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE) + +#define ODD_FLD_NTSC_PROG_SIZE ((NTSC_ODD_FLD_LINES) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + \ + RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE) + +#define NTSC_US_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \ + JUMP_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE) + +#define NTSC_RISC_BUF_SIZE (2 * (RISC_SYNC_INSTRUCTION_SIZE + NTSC_US_VID_PROG_SIZE)) + +#define FRAME1_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + NTSC_FIELD_HEIGHT) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \ + RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE + 2*NUM_NO_OPS*DWORD_SIZE) + +#endif + +#ifndef USE_RISC_NOOP_VIDEO +#define PAL_US_VID_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \ + RISC_SYNC_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE) + +#define PAL_RISC_BUF_SIZE (2 * PAL_US_VID_PROG_SIZE) + +#define PAL_VID_PROG_SIZE ((PAL_FIELD_HEIGHT*2) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \ + RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE ) + +#define ODD_FLD_PAL_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE ) +#define ODD_FLD_NTSC_PROG_SIZE ((NTSC_ODD_FLD_LINES) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE ) + +#define NTSC_US_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE) +#define NTSC_RISC_BUF_SIZE ( 2 * (RISC_SYNC_INSTRUCTION_SIZE + NTSC_US_VID_PROG_SIZE) ) +#define FRAME1_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + NTSC_FIELD_HEIGHT) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \ + RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE ) +#endif diff --git a/drivers/staging/cx25821/cx25821-video.c b/drivers/staging/cx25821/cx25821-video.c new file mode 100644 index 000000000000..8834bc80a5ab --- /dev/null +++ b/drivers/staging/cx25821/cx25821-video.c @@ -0,0 +1,1299 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821-video.h" + +MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards"); +MODULE_AUTHOR("Steven Toth "); +MODULE_LICENSE("GPL"); + +static unsigned int video_nr[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET }; +static unsigned int radio_nr[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET }; + +module_param_array(video_nr, int, NULL, 0444); +module_param_array(radio_nr, int, NULL, 0444); + +MODULE_PARM_DESC(video_nr, "video device numbers"); +MODULE_PARM_DESC(radio_nr, "radio device numbers"); + +static unsigned int video_debug = VIDEO_DEBUG; +module_param(video_debug, int, 0644); +MODULE_PARM_DESC(video_debug, "enable debug messages [video]"); + +static unsigned int irq_debug; +module_param(irq_debug, int, 0644); +MODULE_PARM_DESC(irq_debug, "enable debug messages [IRQ handler]"); + +unsigned int vid_limit = 16; +module_param(vid_limit, int, 0644); +MODULE_PARM_DESC(vid_limit, "capture memory limit in megabytes"); + +static void init_controls(struct cx25821_dev *dev, int chan_num); + +#define FORMAT_FLAGS_PACKED 0x01 + +struct cx25821_fmt formats[] = { + { + .name = "8 bpp, gray", + .fourcc = V4L2_PIX_FMT_GREY, + .depth = 8, + .flags = FORMAT_FLAGS_PACKED, + }, { + .name = "4:1:1, packed, Y41P", + .fourcc = V4L2_PIX_FMT_Y41P, + .depth = 12, + .flags = FORMAT_FLAGS_PACKED, + }, { + .name = "4:2:2, packed, YUYV", + .fourcc = V4L2_PIX_FMT_YUYV, + .depth = 16, + .flags = FORMAT_FLAGS_PACKED, + }, { + .name = "4:2:2, packed, UYVY", + .fourcc = V4L2_PIX_FMT_UYVY, + .depth = 16, + .flags = FORMAT_FLAGS_PACKED, + }, { + .name = "4:2:0, YUV", + .fourcc = V4L2_PIX_FMT_YUV420, + .depth = 12, + .flags = FORMAT_FLAGS_PACKED, + }, +}; + +int get_format_size(void) +{ + return ARRAY_SIZE(formats); +} + +struct cx25821_fmt *format_by_fourcc(unsigned int fourcc) +{ + unsigned int i; + + if (fourcc == V4L2_PIX_FMT_Y41P || fourcc == V4L2_PIX_FMT_YUV411P) { + return formats + 1; + } + + for (i = 0; i < ARRAY_SIZE(formats); i++) + if (formats[i].fourcc == fourcc) + return formats + i; + + printk(KERN_ERR "%s(0x%08x) NOT FOUND\n", __func__, fourcc); + return NULL; +} + +void dump_video_queue(struct cx25821_dev *dev, struct cx25821_dmaqueue *q) +{ + struct cx25821_buffer *buf; + struct list_head *item; + dprintk(1, "%s()\n", __func__); + + if (!list_empty(&q->active)) { + list_for_each(item, &q->active) + buf = list_entry(item, struct cx25821_buffer, vb.queue); + } + + if (!list_empty(&q->queued)) { + list_for_each(item, &q->queued) + buf = list_entry(item, struct cx25821_buffer, vb.queue); + } + +} + +void cx25821_video_wakeup(struct cx25821_dev *dev, struct cx25821_dmaqueue *q, + u32 count) +{ + struct cx25821_buffer *buf; + int bc; + + for (bc = 0;; bc++) { + if (list_empty(&q->active)) { + dprintk(1, "bc=%d (=0: active empty)\n", bc); + break; + } + + buf = + list_entry(q->active.next, struct cx25821_buffer, vb.queue); + + /* count comes from the hw and it is 16bit wide -- + * this trick handles wrap-arounds correctly for + * up to 32767 buffers in flight... */ + if ((s16) (count - buf->count) < 0) { + break; + } + + do_gettimeofday(&buf->vb.ts); + buf->vb.state = VIDEOBUF_DONE; + list_del(&buf->vb.queue); + wake_up(&buf->vb.done); + } + + if (list_empty(&q->active)) + del_timer(&q->timeout); + else + mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT); + if (bc != 1) + printk(KERN_ERR "%s: %d buffers handled (should be 1)\n", + __func__, bc); +} + +#ifdef TUNER_FLAG +int cx25821_set_tvnorm(struct cx25821_dev *dev, v4l2_std_id norm) +{ + dprintk(1, "%s(norm = 0x%08x) name: [%s]\n", __func__, + (unsigned int)norm, v4l2_norm_to_name(norm)); + + dev->tvnorm = norm; + + /* Tell the internal A/V decoder */ + cx25821_call_all(dev, core, s_std, norm); + + return 0; +} +#endif + +struct video_device *cx25821_vdev_init(struct cx25821_dev *dev, + struct pci_dev *pci, + struct video_device *template, + char *type) +{ + struct video_device *vfd; + dprintk(1, "%s()\n", __func__); + + vfd = video_device_alloc(); + if (NULL == vfd) + return NULL; + *vfd = *template; + vfd->minor = -1; + vfd->v4l2_dev = &dev->v4l2_dev; + vfd->release = video_device_release; + snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name, type, + cx25821_boards[dev->board].name); + return vfd; +} + +/* +static int cx25821_ctrl_query(struct v4l2_queryctrl *qctrl) +{ + int i; + + if (qctrl->id < V4L2_CID_BASE || qctrl->id >= V4L2_CID_LASTP1) + return -EINVAL; + for (i = 0; i < CX25821_CTLS; i++) + if (cx25821_ctls[i].v.id == qctrl->id) + break; + if (i == CX25821_CTLS) { + *qctrl = no_ctl; + return 0; + } + *qctrl = cx25821_ctls[i].v; + return 0; +} +*/ + +// resource management +int res_get(struct cx25821_dev *dev, struct cx25821_fh *fh, unsigned int bit) +{ + dprintk(1, "%s()\n", __func__); + if (fh->resources & bit) + /* have it already allocated */ + return 1; + + /* is it free? */ + mutex_lock(&dev->lock); + if (dev->resources & bit) { + /* no, someone else uses it */ + mutex_unlock(&dev->lock); + return 0; + } + /* it's free, grab it */ + fh->resources |= bit; + dev->resources |= bit; + dprintk(1, "res: get %d\n", bit); + mutex_unlock(&dev->lock); + return 1; +} + +int res_check(struct cx25821_fh *fh, unsigned int bit) +{ + return fh->resources & bit; +} + +int res_locked(struct cx25821_dev *dev, unsigned int bit) +{ + return dev->resources & bit; +} + +void res_free(struct cx25821_dev *dev, struct cx25821_fh *fh, unsigned int bits) +{ + BUG_ON((fh->resources & bits) != bits); + dprintk(1, "%s()\n", __func__); + + mutex_lock(&dev->lock); + fh->resources &= ~bits; + dev->resources &= ~bits; + dprintk(1, "res: put %d\n", bits); + mutex_unlock(&dev->lock); +} + +int cx25821_video_mux(struct cx25821_dev *dev, unsigned int input) +{ + struct v4l2_routing route; + memset(&route, 0, sizeof(route)); + + dprintk(1, "%s() video_mux: %d [vmux=%d, gpio=0x%x,0x%x,0x%x,0x%x]\n", + __func__, input, INPUT(input)->vmux, INPUT(input)->gpio0, + INPUT(input)->gpio1, INPUT(input)->gpio2, INPUT(input)->gpio3); + dev->input = input; + + route.input = INPUT(input)->vmux; + + /* Tell the internal A/V decoder */ + cx25821_call_all(dev, video, s_routing, INPUT(input)->vmux, 0, 0); + + return 0; +} + +int cx25821_start_video_dma(struct cx25821_dev *dev, + struct cx25821_dmaqueue *q, + struct cx25821_buffer *buf, + struct sram_channel *channel) +{ + int tmp = 0; + + /* setup fifo + format */ + cx25821_sram_channel_setup(dev, channel, buf->bpl, buf->risc.dma); + + /* reset counter */ + cx_write(channel->gpcnt_ctl, 3); + q->count = 1; + + /* enable irq */ + cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << channel->i)); + cx_set(channel->int_msk, 0x11); + + /* start dma */ + cx_write(channel->dma_ctl, 0x11); /* FIFO and RISC enable */ + + /* make sure upstream setting if any is reversed */ + tmp = cx_read(VID_CH_MODE_SEL); + cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00); + + return 0; +} + +int cx25821_restart_video_queue(struct cx25821_dev *dev, + struct cx25821_dmaqueue *q, + struct sram_channel *channel) +{ + struct cx25821_buffer *buf, *prev; + struct list_head *item; + + if (!list_empty(&q->active)) { + buf = + list_entry(q->active.next, struct cx25821_buffer, vb.queue); + + cx25821_start_video_dma(dev, q, buf, channel); + + list_for_each(item, &q->active) { + buf = list_entry(item, struct cx25821_buffer, vb.queue); + buf->count = q->count++; + } + + mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT); + return 0; + } + + prev = NULL; + for (;;) { + if (list_empty(&q->queued)) + return 0; + + buf = + list_entry(q->queued.next, struct cx25821_buffer, vb.queue); + + if (NULL == prev) { + list_move_tail(&buf->vb.queue, &q->active); + cx25821_start_video_dma(dev, q, buf, channel); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT); + } else if (prev->vb.width == buf->vb.width && + prev->vb.height == buf->vb.height && + prev->fmt == buf->fmt) { + list_move_tail(&buf->vb.queue, &q->active); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); + prev->risc.jmp[2] = cpu_to_le32(0); /* Bits 63 - 32 */ + } else { + return 0; + } + prev = buf; + } +} + +void cx25821_vid_timeout(unsigned long data) +{ + struct cx25821_data *timeout_data = (struct cx25821_data *)data; + struct cx25821_dev *dev = timeout_data->dev; + struct sram_channel *channel = timeout_data->channel; + struct cx25821_dmaqueue *q = &dev->vidq[channel->i]; + struct cx25821_buffer *buf; + unsigned long flags; + + //cx25821_sram_channel_dump(dev, channel); + cx_clear(channel->dma_ctl, 0x11); + + spin_lock_irqsave(&dev->slock, flags); + while (!list_empty(&q->active)) { + buf = + list_entry(q->active.next, struct cx25821_buffer, vb.queue); + list_del(&buf->vb.queue); + + buf->vb.state = VIDEOBUF_ERROR; + wake_up(&buf->vb.done); + } + + cx25821_restart_video_queue(dev, q, channel); + spin_unlock_irqrestore(&dev->slock, flags); +} + +int cx25821_video_irq(struct cx25821_dev *dev, int chan_num, u32 status) +{ + u32 count = 0; + int handled = 0; + u32 mask; + struct sram_channel *channel = &dev->sram_channels[chan_num]; + + mask = cx_read(channel->int_msk); + if (0 == (status & mask)) + return handled; + + cx_write(channel->int_stat, status); + + /* risc op code error */ + if (status & (1 << 16)) { + printk(KERN_WARNING "%s, %s: video risc op code error\n", + dev->name, channel->name); + cx_clear(channel->dma_ctl, 0x11); + cx25821_sram_channel_dump(dev, channel); + } + + /* risc1 y */ + if (status & FLD_VID_DST_RISC1) { + spin_lock(&dev->slock); + count = cx_read(channel->gpcnt); + cx25821_video_wakeup(dev, &dev->vidq[channel->i], count); + spin_unlock(&dev->slock); + handled++; + } + + /* risc2 y */ + if (status & 0x10) { + dprintk(2, "stopper video\n"); + spin_lock(&dev->slock); + cx25821_restart_video_queue(dev, &dev->vidq[channel->i], + channel); + spin_unlock(&dev->slock); + handled++; + } + return handled; +} + +void cx25821_videoioctl_unregister(struct cx25821_dev *dev) +{ + if (dev->ioctl_dev) { + if (dev->ioctl_dev->minor != -1) + video_unregister_device(dev->ioctl_dev); + else + video_device_release(dev->ioctl_dev); + + dev->ioctl_dev = NULL; + } +} + +void cx25821_video_unregister(struct cx25821_dev *dev, int chan_num) +{ + cx_clear(PCI_INT_MSK, 1); + + if (dev->video_dev[chan_num]) { + if (-1 != dev->video_dev[chan_num]->minor) + video_unregister_device(dev->video_dev[chan_num]); + else + video_device_release(dev->video_dev[chan_num]); + + dev->video_dev[chan_num] = NULL; + + btcx_riscmem_free(dev->pci, &dev->vidq[chan_num].stopper); + + printk(KERN_WARNING "device %d released!\n", chan_num); + } + +} + +int cx25821_video_register(struct cx25821_dev *dev, int chan_num, + struct video_device *video_template) +{ + int err; + + spin_lock_init(&dev->slock); + + //printk(KERN_WARNING "Channel %d\n", chan_num); + +#ifdef TUNER_FLAG + dev->tvnorm = video_template->current_norm; +#endif + + /* init video dma queues */ + dev->timeout_data[chan_num].dev = dev; + dev->timeout_data[chan_num].channel = &dev->sram_channels[chan_num]; + INIT_LIST_HEAD(&dev->vidq[chan_num].active); + INIT_LIST_HEAD(&dev->vidq[chan_num].queued); + dev->vidq[chan_num].timeout.function = cx25821_vid_timeout; + dev->vidq[chan_num].timeout.data = + (unsigned long)&dev->timeout_data[chan_num]; + init_timer(&dev->vidq[chan_num].timeout); + cx25821_risc_stopper(dev->pci, &dev->vidq[chan_num].stopper, + dev->sram_channels[chan_num].dma_ctl, 0x11, 0); + + /* register v4l devices */ + dev->video_dev[chan_num] = + cx25821_vdev_init(dev, dev->pci, video_template, "video"); + err = + video_register_device(dev->video_dev[chan_num], VFL_TYPE_GRABBER, + video_nr[dev->nr]); + + if (err < 0) { + goto fail_unreg; + } + //set PCI interrupt + cx_set(PCI_INT_MSK, 0xff); + + /* initial device configuration */ + mutex_lock(&dev->lock); +#ifdef TUNER_FLAG + cx25821_set_tvnorm(dev, dev->tvnorm); +#endif + mutex_unlock(&dev->lock); + + init_controls(dev, chan_num); + + return 0; + + fail_unreg: + cx25821_video_unregister(dev, chan_num); + return err; +} + +int buffer_setup(struct videobuf_queue *q, unsigned int *count, + unsigned int *size) +{ + struct cx25821_fh *fh = q->priv_data; + + *size = fh->fmt->depth * fh->width * fh->height >> 3; + + if (0 == *count) + *count = 32; + + while (*size * *count > vid_limit * 1024 * 1024) + (*count)--; + + return 0; +} + +int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb, + enum v4l2_field field) +{ + struct cx25821_fh *fh = q->priv_data; + struct cx25821_dev *dev = fh->dev; + struct cx25821_buffer *buf = + container_of(vb, struct cx25821_buffer, vb); + int rc, init_buffer = 0; + u32 line0_offset, line1_offset; + struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); + int bpl_local = LINE_SIZE_D1; + int channel_opened = 0; + + BUG_ON(NULL == fh->fmt); + if (fh->width < 48 || fh->width > 720 || + fh->height < 32 || fh->height > 576) + return -EINVAL; + + buf->vb.size = (fh->width * fh->height * fh->fmt->depth) >> 3; + + if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size) + return -EINVAL; + + if (buf->fmt != fh->fmt || + buf->vb.width != fh->width || + buf->vb.height != fh->height || buf->vb.field != field) { + buf->fmt = fh->fmt; + buf->vb.width = fh->width; + buf->vb.height = fh->height; + buf->vb.field = field; + init_buffer = 1; + } + + if (VIDEOBUF_NEEDS_INIT == buf->vb.state) { + init_buffer = 1; + rc = videobuf_iolock(q, &buf->vb, NULL); + if (0 != rc) { + printk(KERN_DEBUG "videobuf_iolock failed!\n"); + goto fail; + } + } + + dprintk(1, "init_buffer=%d\n", init_buffer); + + if (init_buffer) { + + channel_opened = dev->channel_opened; + channel_opened = (channel_opened < 0 + || channel_opened > 7) ? 7 : channel_opened; + + if (dev->pixel_formats[channel_opened] == PIXEL_FRMT_411) + buf->bpl = (buf->fmt->depth * buf->vb.width) >> 3; + else + buf->bpl = (buf->fmt->depth >> 3) * (buf->vb.width); + + if (dev->pixel_formats[channel_opened] == PIXEL_FRMT_411) { + bpl_local = buf->bpl; + } else { + bpl_local = buf->bpl; //Default + + if (channel_opened >= 0 && channel_opened <= 7) { + if (dev->use_cif_resolution[channel_opened]) { + if (dev->tvnorm & V4L2_STD_PAL_BG + || dev->tvnorm & V4L2_STD_PAL_DK) + bpl_local = 352 << 1; + else + bpl_local = + dev-> + cif_width[channel_opened] << + 1; + } + } + } + + switch (buf->vb.field) { + case V4L2_FIELD_TOP: + cx25821_risc_buffer(dev->pci, &buf->risc, + dma->sglist, 0, UNSET, + buf->bpl, 0, buf->vb.height); + break; + case V4L2_FIELD_BOTTOM: + cx25821_risc_buffer(dev->pci, &buf->risc, + dma->sglist, UNSET, 0, + buf->bpl, 0, buf->vb.height); + break; + case V4L2_FIELD_INTERLACED: + /* All other formats are top field first */ + line0_offset = 0; + line1_offset = buf->bpl; + dprintk(1, "top field first\n"); + + cx25821_risc_buffer(dev->pci, &buf->risc, + dma->sglist, line0_offset, + bpl_local, bpl_local, bpl_local, + buf->vb.height >> 1); + break; + case V4L2_FIELD_SEQ_TB: + cx25821_risc_buffer(dev->pci, &buf->risc, + dma->sglist, + 0, buf->bpl * (buf->vb.height >> 1), + buf->bpl, 0, buf->vb.height >> 1); + break; + case V4L2_FIELD_SEQ_BT: + cx25821_risc_buffer(dev->pci, &buf->risc, + dma->sglist, + buf->bpl * (buf->vb.height >> 1), 0, + buf->bpl, 0, buf->vb.height >> 1); + break; + default: + BUG(); + } + } + + dprintk(2, "[%p/%d] buffer_prep - %dx%d %dbpp \"%s\" - dma=0x%08lx\n", + buf, buf->vb.i, fh->width, fh->height, fh->fmt->depth, + fh->fmt->name, (unsigned long)buf->risc.dma); + + buf->vb.state = VIDEOBUF_PREPARED; + + return 0; + + fail: + cx25821_free_buffer(q, buf); + return rc; +} + +void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb) +{ + struct cx25821_buffer *buf = + container_of(vb, struct cx25821_buffer, vb); + + cx25821_free_buffer(q, buf); +} + +struct videobuf_queue *get_queue(struct cx25821_fh *fh) +{ + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + return &fh->vidq; + default: + BUG(); + return NULL; + } +} + +int get_resource(struct cx25821_fh *fh, int resource) +{ + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + return resource; + default: + BUG(); + return 0; + } +} + +int video_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct cx25821_fh *fh = file->private_data; + + return videobuf_mmap_mapper(get_queue(fh), vma); +} + +/* VIDEO IOCTLS */ +int vidioc_g_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) +{ + struct cx25821_fh *fh = priv; + + f->fmt.pix.width = fh->width; + f->fmt.pix.height = fh->height; + f->fmt.pix.field = fh->vidq.field; + f->fmt.pix.pixelformat = fh->fmt->fourcc; + f->fmt.pix.bytesperline = (f->fmt.pix.width * fh->fmt->depth) >> 3; + f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; + + return 0; +} + +int vidioc_try_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) +{ + struct cx25821_fmt *fmt; + enum v4l2_field field; + unsigned int maxw, maxh; + + fmt = format_by_fourcc(f->fmt.pix.pixelformat); + if (NULL == fmt) + return -EINVAL; + + field = f->fmt.pix.field; + maxw = 720; + maxh = 576; + + if (V4L2_FIELD_ANY == field) { + field = (f->fmt.pix.height > maxh / 2) + ? V4L2_FIELD_INTERLACED : V4L2_FIELD_TOP; + } + + switch (field) { + case V4L2_FIELD_TOP: + case V4L2_FIELD_BOTTOM: + maxh = maxh / 2; + break; + case V4L2_FIELD_INTERLACED: + break; + default: + return -EINVAL; + } + + f->fmt.pix.field = field; + if (f->fmt.pix.height < 32) + f->fmt.pix.height = 32; + if (f->fmt.pix.height > maxh) + f->fmt.pix.height = maxh; + if (f->fmt.pix.width < 48) + f->fmt.pix.width = 48; + if (f->fmt.pix.width > maxw) + f->fmt.pix.width = maxw; + f->fmt.pix.width &= ~0x03; + f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3; + f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; + + return 0; +} + +int vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + + strcpy(cap->driver, "cx25821"); + strlcpy(cap->card, cx25821_boards[dev->board].name, sizeof(cap->card)); + sprintf(cap->bus_info, "PCIe:%s", pci_name(dev->pci)); + cap->version = CX25821_VERSION_CODE; + cap->capabilities = + V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | V4L2_CAP_STREAMING; + if (UNSET != dev->tuner_type) + cap->capabilities |= V4L2_CAP_TUNER; + return 0; +} + +int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + if (unlikely(f->index >= ARRAY_SIZE(formats))) + return -EINVAL; + + strlcpy(f->description, formats[f->index].name, sizeof(f->description)); + f->pixelformat = formats[f->index].fourcc; + + return 0; +} + +#ifdef CONFIG_VIDEO_V4L1_COMPAT +int vidiocgmbuf(struct file *file, void *priv, struct video_mbuf *mbuf) +{ + struct cx25821_fh *fh = priv; + struct videobuf_queue *q; + struct v4l2_requestbuffers req; + unsigned int i; + int err; + + q = get_queue(fh); + memset(&req, 0, sizeof(req)); + req.type = q->type; + req.count = 8; + req.memory = V4L2_MEMORY_MMAP; + err = videobuf_reqbufs(q, &req); + if (err < 0) + return err; + + mbuf->frames = req.count; + mbuf->size = 0; + for (i = 0; i < mbuf->frames; i++) { + mbuf->offsets[i] = q->bufs[i]->boff; + mbuf->size += q->bufs[i]->bsize; + } + return 0; +} +#endif + +int vidioc_reqbufs(struct file *file, void *priv, struct v4l2_requestbuffers *p) +{ + struct cx25821_fh *fh = priv; + return videobuf_reqbufs(get_queue(fh), p); +} + +int vidioc_querybuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct cx25821_fh *fh = priv; + return videobuf_querybuf(get_queue(fh), p); +} + +int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct cx25821_fh *fh = priv; + return videobuf_qbuf(get_queue(fh), p); +} + +int vidioc_g_priority(struct file *file, void *f, enum v4l2_priority *p) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)f)->dev; + + *p = v4l2_prio_max(&dev->prio); + + return 0; +} + +int vidioc_s_priority(struct file *file, void *f, enum v4l2_priority prio) +{ + struct cx25821_fh *fh = f; + struct cx25821_dev *dev = ((struct cx25821_fh *)f)->dev; + + return v4l2_prio_change(&dev->prio, &fh->prio, prio); +} + +#ifdef TUNER_FLAG +int vidioc_s_std(struct file *file, void *priv, v4l2_std_id * tvnorms) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + + dprintk(1, "%s()\n", __func__); + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + if (dev->tvnorm == *tvnorms) { + return 0; + } + + mutex_lock(&dev->lock); + cx25821_set_tvnorm(dev, *tvnorms); + mutex_unlock(&dev->lock); + + medusa_set_videostandard(dev); + + return 0; +} +#endif + +int cx25821_enum_input(struct cx25821_dev *dev, struct v4l2_input *i) +{ + static const char *iname[] = { + [CX25821_VMUX_COMPOSITE] = "Composite", + [CX25821_VMUX_SVIDEO] = "S-Video", + [CX25821_VMUX_DEBUG] = "for debug only", + }; + unsigned int n; + dprintk(1, "%s()\n", __func__); + + n = i->index; + if (n > 2) + return -EINVAL; + + if (0 == INPUT(n)->type) + return -EINVAL; + + memset(i, 0, sizeof(*i)); + i->index = n; + i->type = V4L2_INPUT_TYPE_CAMERA; + strcpy(i->name, iname[INPUT(n)->type]); + + i->std = CX25821_NORMS; + return 0; +} + +int vidioc_enum_input(struct file *file, void *priv, struct v4l2_input *i) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + dprintk(1, "%s()\n", __func__); + return cx25821_enum_input(dev, i); +} + +int vidioc_g_input(struct file *file, void *priv, unsigned int *i) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + + *i = dev->input; + dprintk(1, "%s() returns %d\n", __func__, *i); + return 0; +} + +int vidioc_s_input(struct file *file, void *priv, unsigned int i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + + dprintk(1, "%s(%d)\n", __func__, i); + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + if (i > 2) { + dprintk(1, "%s() -EINVAL\n", __func__); + return -EINVAL; + } + + mutex_lock(&dev->lock); + cx25821_video_mux(dev, i); + mutex_unlock(&dev->lock); + return 0; +} + +#ifdef TUNER_FLAG +int vidioc_g_frequency(struct file *file, void *priv, struct v4l2_frequency *f) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + + f->frequency = dev->freq; + + cx25821_call_all(dev, tuner, g_frequency, f); + + return 0; +} + +int cx25821_set_freq(struct cx25821_dev *dev, struct v4l2_frequency *f) +{ + mutex_lock(&dev->lock); + dev->freq = f->frequency; + + cx25821_call_all(dev, tuner, s_frequency, f); + + /* When changing channels it is required to reset TVAUDIO */ + msleep(10); + + mutex_unlock(&dev->lock); + + return 0; +} + +int vidioc_s_frequency(struct file *file, void *priv, struct v4l2_frequency *f) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + return cx25821_set_freq(dev, f); +} +#endif + +#ifdef CONFIG_VIDEO_ADV_DEBUG +int vidioc_g_register(struct file *file, void *fh, + struct v4l2_dbg_register *reg) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)fh)->dev; + + if (!v4l2_chip_match_host(®->match)) + return -EINVAL; + + cx25821_call_all(dev, core, g_register, reg); + + return 0; +} + +int vidioc_s_register(struct file *file, void *fh, + struct v4l2_dbg_register *reg) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)fh)->dev; + + if (!v4l2_chip_match_host(®->match)) + return -EINVAL; + + cx25821_call_all(dev, core, s_register, reg); + + return 0; +} + +#endif + +#ifdef TUNER_FLAG +int vidioc_g_tuner(struct file *file, void *priv, struct v4l2_tuner *t) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + + if (unlikely(UNSET == dev->tuner_type)) + return -EINVAL; + if (0 != t->index) + return -EINVAL; + + strcpy(t->name, "Television"); + t->type = V4L2_TUNER_ANALOG_TV; + t->capability = V4L2_TUNER_CAP_NORM; + t->rangehigh = 0xffffffffUL; + + t->signal = 0xffff; /* LOCKED */ + return 0; +} + +int vidioc_s_tuner(struct file *file, void *priv, struct v4l2_tuner *t) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + struct cx25821_fh *fh = priv; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + dprintk(1, "%s()\n", __func__); + if (UNSET == dev->tuner_type) + return -EINVAL; + if (0 != t->index) + return -EINVAL; + + return 0; +} + +#endif +// ****************************************************************************************** +static const struct v4l2_queryctrl no_ctl = { + .name = "42", + .flags = V4L2_CTRL_FLAG_DISABLED, +}; + +static struct v4l2_queryctrl cx25821_ctls[] = { + /* --- video --- */ + { + .id = V4L2_CID_BRIGHTNESS, + .name = "Brightness", + .minimum = 0, + .maximum = 10000, + .step = 1, + .default_value = 6200, + .type = V4L2_CTRL_TYPE_INTEGER, + }, { + .id = V4L2_CID_CONTRAST, + .name = "Contrast", + .minimum = 0, + .maximum = 10000, + .step = 1, + .default_value = 5000, + .type = V4L2_CTRL_TYPE_INTEGER, + }, { + .id = V4L2_CID_SATURATION, + .name = "Saturation", + .minimum = 0, + .maximum = 10000, + .step = 1, + .default_value = 5000, + .type = V4L2_CTRL_TYPE_INTEGER, + }, { + .id = V4L2_CID_HUE, + .name = "Hue", + .minimum = 0, + .maximum = 10000, + .step = 1, + .default_value = 5000, + .type = V4L2_CTRL_TYPE_INTEGER, + } +}; +static const int CX25821_CTLS = ARRAY_SIZE(cx25821_ctls); + +static int cx25821_ctrl_query(struct v4l2_queryctrl *qctrl) +{ + int i; + + if (qctrl->id < V4L2_CID_BASE || qctrl->id >= V4L2_CID_LASTP1) + return -EINVAL; + for (i = 0; i < CX25821_CTLS; i++) + if (cx25821_ctls[i].id == qctrl->id) + break; + if (i == CX25821_CTLS) { + *qctrl = no_ctl; + return 0; + } + *qctrl = cx25821_ctls[i]; + return 0; +} + +int vidioc_queryctrl(struct file *file, void *priv, + struct v4l2_queryctrl *qctrl) +{ + return cx25821_ctrl_query(qctrl); +} + +/* ------------------------------------------------------------------ */ +/* VIDEO CTRL IOCTLS */ + +static const struct v4l2_queryctrl *ctrl_by_id(unsigned int id) +{ + unsigned int i; + + for (i = 0; i < CX25821_CTLS; i++) + if (cx25821_ctls[i].id == id) + return cx25821_ctls + i; + return NULL; +} + +int vidioc_g_ctrl(struct file *file, void *priv, struct v4l2_control *ctl) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + + const struct v4l2_queryctrl *ctrl; + + ctrl = ctrl_by_id(ctl->id); + + if (NULL == ctrl) + return -EINVAL; + switch (ctl->id) { + case V4L2_CID_BRIGHTNESS: + ctl->value = dev->ctl_bright; + break; + case V4L2_CID_HUE: + ctl->value = dev->ctl_hue; + break; + case V4L2_CID_CONTRAST: + ctl->value = dev->ctl_contrast; + break; + case V4L2_CID_SATURATION: + ctl->value = dev->ctl_saturation; + break; + } + return 0; +} + +int cx25821_set_control(struct cx25821_dev *dev, + struct v4l2_control *ctl, int chan_num) +{ + int err; + const struct v4l2_queryctrl *ctrl; + + err = -EINVAL; + + ctrl = ctrl_by_id(ctl->id); + + if (NULL == ctrl) + return err; + + switch (ctrl->type) { + case V4L2_CTRL_TYPE_BOOLEAN: + case V4L2_CTRL_TYPE_MENU: + case V4L2_CTRL_TYPE_INTEGER: + if (ctl->value < ctrl->minimum) + ctl->value = ctrl->minimum; + if (ctl->value > ctrl->maximum) + ctl->value = ctrl->maximum; + break; + default: + /* nothing */ ; + }; + + switch (ctl->id) { + case V4L2_CID_BRIGHTNESS: + dev->ctl_bright = ctl->value; + medusa_set_brightness(dev, ctl->value, chan_num); + break; + case V4L2_CID_HUE: + dev->ctl_hue = ctl->value; + medusa_set_hue(dev, ctl->value, chan_num); + break; + case V4L2_CID_CONTRAST: + dev->ctl_contrast = ctl->value; + medusa_set_contrast(dev, ctl->value, chan_num); + break; + case V4L2_CID_SATURATION: + dev->ctl_saturation = ctl->value; + medusa_set_saturation(dev, ctl->value, chan_num); + break; + } + + err = 0; + + return err; +} + +static void init_controls(struct cx25821_dev *dev, int chan_num) +{ + struct v4l2_control ctrl; + int i; + for (i = 0; i < CX25821_CTLS; i++) { + ctrl.id = cx25821_ctls[i].id; + ctrl.value = cx25821_ctls[i].default_value; + + cx25821_set_control(dev, &ctrl, chan_num); + } +} + +int vidioc_cropcap(struct file *file, void *priv, struct v4l2_cropcap *cropcap) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + + if (cropcap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + cropcap->bounds.top = cropcap->bounds.left = 0; + cropcap->bounds.width = 720; + cropcap->bounds.height = dev->tvnorm == V4L2_STD_PAL_BG ? 576 : 480; + cropcap->pixelaspect.numerator = + dev->tvnorm == V4L2_STD_PAL_BG ? 59 : 10; + cropcap->pixelaspect.denominator = + dev->tvnorm == V4L2_STD_PAL_BG ? 54 : 11; + cropcap->defrect = cropcap->bounds; + return 0; +} + +int vidioc_s_crop(struct file *file, void *priv, struct v4l2_crop *crop) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + struct cx25821_fh *fh = priv; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + // vidioc_s_crop not supported + return -EINVAL; +} + +int vidioc_g_crop(struct file *file, void *priv, struct v4l2_crop *crop) +{ + // vidioc_g_crop not supported + return -EINVAL; +} + +int vidioc_querystd(struct file *file, void *priv, v4l2_std_id * norm) +{ + // medusa does not support video standard sensing of current input + *norm = CX25821_NORMS; + + return 0; +} + +int is_valid_width(u32 width, v4l2_std_id tvnorm) +{ + if (tvnorm == V4L2_STD_PAL_BG) { + if (width == 352 || width == 720) + return 1; + else + return 0; + } + + if (tvnorm == V4L2_STD_NTSC_M) { + if (width == 320 || width == 352 || width == 720) + return 1; + else + return 0; + } + return 0; +} + +int is_valid_height(u32 height, v4l2_std_id tvnorm) +{ + if (tvnorm == V4L2_STD_PAL_BG) { + if (height == 576 || height == 288) + return 1; + else + return 0; + } + + if (tvnorm == V4L2_STD_NTSC_M) { + if (height == 480 || height == 240) + return 1; + else + return 0; + } + + return 0; +} diff --git a/drivers/staging/cx25821/cx25821-video.h b/drivers/staging/cx25821/cx25821-video.h new file mode 100644 index 000000000000..4417ff5d90d4 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-video.h @@ -0,0 +1,194 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef CX25821_VIDEO_H_ +#define CX25821_VIDEO_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cx25821.h" +#include +#include + +#ifdef CONFIG_VIDEO_V4L1_COMPAT +/* Include V4L1 specific functions. Should be removed soon */ +#include +#endif + +#define TUNER_FLAG + +#define VIDEO_DEBUG 0 + +#define dprintk(level, fmt, arg...)\ + do { if (VIDEO_DEBUG >= level)\ + printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\ + } while (0) + +//For IOCTL to identify running upstream +#define UPSTREAM_START_VIDEO 700 +#define UPSTREAM_STOP_VIDEO 701 +#define UPSTREAM_START_AUDIO 702 +#define UPSTREAM_STOP_AUDIO 703 +#define UPSTREAM_DUMP_REGISTERS 702 +#define SET_VIDEO_STD 800 +#define SET_PIXEL_FORMAT 1000 +#define ENABLE_CIF_RESOLUTION 1001 + +#define REG_READ 900 +#define REG_WRITE 901 +#define MEDUSA_READ 910 +#define MEDUSA_WRITE 911 + +extern struct sram_channel *channel0; +extern struct sram_channel *channel1; +extern struct sram_channel *channel2; +extern struct sram_channel *channel3; +extern struct sram_channel *channel4; +extern struct sram_channel *channel5; +extern struct sram_channel *channel6; +extern struct sram_channel *channel7; +extern struct sram_channel *channel9; +extern struct sram_channel *channel10; +extern struct sram_channel *channel11; +extern struct video_device cx25821_video_template0; +extern struct video_device cx25821_video_template1; +extern struct video_device cx25821_video_template2; +extern struct video_device cx25821_video_template3; +extern struct video_device cx25821_video_template4; +extern struct video_device cx25821_video_template5; +extern struct video_device cx25821_video_template6; +extern struct video_device cx25821_video_template7; +extern struct video_device cx25821_video_template9; +extern struct video_device cx25821_video_template10; +extern struct video_device cx25821_video_template11; +extern struct video_device cx25821_videoioctl_template; +//extern const u32 *ctrl_classes[]; + +extern unsigned int vid_limit; + +#define FORMAT_FLAGS_PACKED 0x01 +extern struct cx25821_fmt formats[]; +extern struct cx25821_fmt *format_by_fourcc(unsigned int fourcc); +extern struct cx25821_data timeout_data[MAX_VID_CHANNEL_NUM]; + +extern void dump_video_queue(struct cx25821_dev *dev, + struct cx25821_dmaqueue *q); +extern void cx25821_video_wakeup(struct cx25821_dev *dev, + struct cx25821_dmaqueue *q, u32 count); + +#ifdef TUNER_FLAG +extern int cx25821_set_tvnorm(struct cx25821_dev *dev, v4l2_std_id norm); +#endif + +extern int res_get(struct cx25821_dev *dev, struct cx25821_fh *fh, + unsigned int bit); +extern int res_check(struct cx25821_fh *fh, unsigned int bit); +extern int res_locked(struct cx25821_dev *dev, unsigned int bit); +extern void res_free(struct cx25821_dev *dev, struct cx25821_fh *fh, + unsigned int bits); +extern int cx25821_video_mux(struct cx25821_dev *dev, unsigned int input); +extern int cx25821_start_video_dma(struct cx25821_dev *dev, + struct cx25821_dmaqueue *q, + struct cx25821_buffer *buf, + struct sram_channel *channel); + +extern int cx25821_set_scale(struct cx25821_dev *dev, unsigned int width, + unsigned int height, enum v4l2_field field); +extern int cx25821_video_irq(struct cx25821_dev *dev, int chan_num, u32 status); +extern void cx25821_video_unregister(struct cx25821_dev *dev, int chan_num); +extern int cx25821_video_register(struct cx25821_dev *dev, int chan_num, + struct video_device *video_template); +extern int get_format_size(void); + +extern int buffer_setup(struct videobuf_queue *q, unsigned int *count, + unsigned int *size); +extern int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb, + enum v4l2_field field); +extern void buffer_release(struct videobuf_queue *q, + struct videobuf_buffer *vb); +extern struct videobuf_queue *get_queue(struct cx25821_fh *fh); +extern int get_resource(struct cx25821_fh *fh, int resource); +extern int video_mmap(struct file *file, struct vm_area_struct *vma); +extern int vidioc_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f); +extern int vidioc_querycap(struct file *file, void *priv, + struct v4l2_capability *cap); +extern int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f); +extern int vidiocgmbuf(struct file *file, void *priv, struct video_mbuf *mbuf); +extern int vidioc_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *p); +extern int vidioc_querybuf(struct file *file, void *priv, + struct v4l2_buffer *p); +extern int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *p); +extern int vidioc_s_std(struct file *file, void *priv, v4l2_std_id * tvnorms); +extern int cx25821_enum_input(struct cx25821_dev *dev, struct v4l2_input *i); +extern int vidioc_enum_input(struct file *file, void *priv, + struct v4l2_input *i); +extern int vidioc_g_input(struct file *file, void *priv, unsigned int *i); +extern int vidioc_s_input(struct file *file, void *priv, unsigned int i); +extern int vidioc_g_ctrl(struct file *file, void *priv, + struct v4l2_control *ctl); +extern int vidioc_g_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f); +extern int vidioc_g_frequency(struct file *file, void *priv, + struct v4l2_frequency *f); +extern int cx25821_set_freq(struct cx25821_dev *dev, struct v4l2_frequency *f); +extern int vidioc_s_frequency(struct file *file, void *priv, + struct v4l2_frequency *f); +extern int vidioc_g_register(struct file *file, void *fh, + struct v4l2_dbg_register *reg); +extern int vidioc_s_register(struct file *file, void *fh, + struct v4l2_dbg_register *reg); +extern int vidioc_g_tuner(struct file *file, void *priv, struct v4l2_tuner *t); +extern int vidioc_s_tuner(struct file *file, void *priv, struct v4l2_tuner *t); + +extern int is_valid_width(u32 width, v4l2_std_id tvnorm); +extern int is_valid_height(u32 height, v4l2_std_id tvnorm); + +extern int vidioc_g_priority(struct file *file, void *f, enum v4l2_priority *p); +extern int vidioc_s_priority(struct file *file, void *f, + enum v4l2_priority prio); + +extern int vidioc_queryctrl(struct file *file, void *priv, + struct v4l2_queryctrl *qctrl); +extern int cx25821_set_control(struct cx25821_dev *dev, + struct v4l2_control *ctrl, int chan_num); + +extern int vidioc_cropcap(struct file *file, void *fh, + struct v4l2_cropcap *cropcap); +extern int vidioc_s_crop(struct file *file, void *priv, struct v4l2_crop *crop); +extern int vidioc_g_crop(struct file *file, void *priv, struct v4l2_crop *crop); + +extern int vidioc_querystd(struct file *file, void *priv, v4l2_std_id * norm); +#endif diff --git a/drivers/staging/cx25821/cx25821-video0.c b/drivers/staging/cx25821/cx25821-video0.c new file mode 100644 index 000000000000..950fac1d7003 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-video0.c @@ -0,0 +1,451 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821-video.h" + +static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct cx25821_buffer *buf = + container_of(vb, struct cx25821_buffer, vb); + struct cx25821_buffer *prev; + struct cx25821_fh *fh = vq->priv_data; + struct cx25821_dev *dev = fh->dev; + struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH00]; + + /* add jump to stopper */ + buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); + buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); + buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ + + dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); + + if (!list_empty(&q->queued)) { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, + buf->vb.i); + + } else if (list_empty(&q->active)) { + list_add_tail(&buf->vb.queue, &q->active); + cx25821_start_video_dma(dev, q, buf, + &dev->sram_channels[SRAM_CH00]); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT); + dprintk(2, + "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", + buf, buf->vb.i, buf->count, q->count); + } else { + prev = + list_entry(q->active.prev, struct cx25821_buffer, vb.queue); + if (prev->vb.width == buf->vb.width + && prev->vb.height == buf->vb.height + && prev->fmt == buf->fmt) { + list_add_tail(&buf->vb.queue, &q->active); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); + + /* 64 bit bits 63-32 */ + prev->risc.jmp[2] = cpu_to_le32(0); + dprintk(2, + "[%p/%d] buffer_queue - append to active, buf->count=%d\n", + buf, buf->vb.i, buf->count); + + } else { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, + buf->vb.i); + } + } + + if (list_empty(&q->active)) { + dprintk(2, "active queue empty!\n"); + } +} + +static struct videobuf_queue_ops cx25821_video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +static int video_open(struct file *file) +{ + int minor = video_devdata(file)->minor; + struct cx25821_dev *h, *dev = NULL; + struct cx25821_fh *fh; + struct list_head *list; + enum v4l2_buf_type type = 0; + u32 pix_format; + + lock_kernel(); + list_for_each(list, &cx25821_devlist) { + h = list_entry(list, struct cx25821_dev, devlist); + + if (h->video_dev[SRAM_CH00] + && h->video_dev[SRAM_CH00]->minor == minor) { + dev = h; + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + } + } + + if (NULL == dev) { + unlock_kernel(); + return -ENODEV; + } + + printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); + + /* allocate + initialize per filehandle data */ + fh = kzalloc(sizeof(*fh), GFP_KERNEL); + if (NULL == fh) { + unlock_kernel(); + return -ENOMEM; + } + + file->private_data = fh; + fh->dev = dev; + fh->type = type; + fh->width = 720; + + if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) + fh->height = 576; + else + fh->height = 480; + + dev->channel_opened = SRAM_CH00; + pix_format = + (dev->pixel_formats[dev->channel_opened] == + PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV; + fh->fmt = format_by_fourcc(pix_format); + + v4l2_prio_open(&dev->prio, &fh->prio); + + videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, + &dev->pci->dev, &dev->slock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_INTERLACED, + sizeof(struct cx25821_buffer), fh); + + dprintk(1, "post videobuf_queue_init()\n"); + unlock_kernel(); + + return 0; +} + +static ssize_t video_read(struct file *file, char __user * data, size_t count, + loff_t * ppos) +{ + struct cx25821_fh *fh = file->private_data; + + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + if (res_locked(fh->dev, RESOURCE_VIDEO0)) + return -EBUSY; + + return videobuf_read_one(&fh->vidq, data, count, ppos, + file->f_flags & O_NONBLOCK); + + default: + BUG(); + return 0; + } +} + +static unsigned int video_poll(struct file *file, + struct poll_table_struct *wait) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_buffer *buf; + + if (res_check(fh, RESOURCE_VIDEO0)) { + /* streaming capture */ + if (list_empty(&fh->vidq.stream)) + return POLLERR; + buf = list_entry(fh->vidq.stream.next, + struct cx25821_buffer, vb.stream); + } else { + /* read() capture */ + buf = (struct cx25821_buffer *)fh->vidq.read_buf; + if (NULL == buf) + return POLLERR; + } + + poll_wait(file, &buf->vb.done, wait); + if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) { + if (buf->vb.state == VIDEOBUF_DONE) { + struct cx25821_dev *dev = fh->dev; + + if (dev && dev->use_cif_resolution[SRAM_CH00]) { + u8 cam_id = *((char *)buf->vb.baddr + 3); + memcpy((char *)buf->vb.baddr, + (char *)buf->vb.baddr + (fh->width * 2), + (fh->width * 2)); + *((char *)buf->vb.baddr + 3) = cam_id; + } + } + + return POLLIN | POLLRDNORM; + } + + return 0; +} + +static int video_release(struct file *file) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_dev *dev = fh->dev; + + //stop the risc engine and fifo + cx_write(channel0->dma_ctl, 0); /* FIFO and RISC disable */ + + /* stop video capture */ + if (res_check(fh, RESOURCE_VIDEO0)) { + videobuf_queue_cancel(&fh->vidq); + res_free(dev, fh, RESOURCE_VIDEO0); + } + + if (fh->vidq.read_buf) { + buffer_release(&fh->vidq, fh->vidq.read_buf); + kfree(fh->vidq.read_buf); + } + + videobuf_mmap_free(&fh->vidq); + + v4l2_prio_close(&dev->prio, &fh->prio); + file->private_data = NULL; + kfree(fh); + + return 0; +} + +static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + + if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) { + return -EINVAL; + } + + if (unlikely(i != fh->type)) { + return -EINVAL; + } + + if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO0)))) { + return -EBUSY; + } + + return videobuf_streamon(get_queue(fh)); +} + +static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + int err, res; + + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + if (i != fh->type) + return -EINVAL; + + res = get_resource(fh, RESOURCE_VIDEO0); + err = videobuf_streamoff(get_queue(fh)); + if (err < 0) + return err; + res_free(dev, fh, res); + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + int pix_format = PIXEL_FRMT_422; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + dprintk(2, "%s()\n", __func__); + err = vidioc_try_fmt_vid_cap(file, priv, f); + + if (0 != err) + return err; + + fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); + fh->vidq.field = f->fmt.pix.field; + + // check if width and height is valid based on set standard + if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) { + fh->width = f->fmt.pix.width; + } + + if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) { + fh->height = f->fmt.pix.height; + } + + if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) + pix_format = PIXEL_FRMT_411; + else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) + pix_format = PIXEL_FRMT_422; + else + return -EINVAL; + + cx25821_set_pixel_format(dev, SRAM_CH00, pix_format); + + // check if cif resolution + if (fh->width == 320 || fh->width == 352) { + dev->use_cif_resolution[SRAM_CH00] = 1; + } else { + dev->use_cif_resolution[SRAM_CH00] = 0; + } + dev->cif_width[SRAM_CH00] = fh->width; + medusa_set_resolution(dev, fh->width, SRAM_CH00); + + dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, + fh->height, fh->vidq.field); + cx25821_call_all(dev, video, s_fmt, f); + + return 0; +} + +static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + int ret_val = 0; + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + + ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); + + p->sequence = dev->vidq[SRAM_CH00].count; + + return ret_val; +} + +static int vidioc_log_status(struct file *file, void *priv) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + char name[32 + 2]; + + struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH00]; + u32 tmp = 0; + + snprintf(name, sizeof(name), "%s/2", dev->name); + printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", + dev->name); + cx25821_call_all(dev, core, log_status); + tmp = cx_read(sram_ch->dma_ctl); + printk(KERN_INFO "Video input 0 is %s\n", + (tmp & 0x11) ? "streaming" : "stopped"); + printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", + dev->name); + return 0; +} + +static int vidioc_s_ctrl(struct file *file, void *priv, + struct v4l2_control *ctl) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + return cx25821_set_control(dev, ctl, SRAM_CH00); +} + +// exported stuff +static const struct v4l2_file_operations video_fops = { + .owner = THIS_MODULE, + .open = video_open, + .release = video_release, + .read = video_read, + .poll = video_poll, + .mmap = video_mmap, + .ioctl = video_ioctl2, +}; + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, +#ifdef TUNER_FLAG + .vidioc_s_std = vidioc_s_std, + .vidioc_querystd = vidioc_querystd, +#endif + .vidioc_cropcap = vidioc_cropcap, + .vidioc_s_crop = vidioc_s_crop, + .vidioc_g_crop = vidioc_g_crop, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_g_ctrl = vidioc_g_ctrl, + .vidioc_s_ctrl = vidioc_s_ctrl, + .vidioc_queryctrl = vidioc_queryctrl, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_log_status = vidioc_log_status, + .vidioc_g_priority = vidioc_g_priority, + .vidioc_s_priority = vidioc_s_priority, +#ifdef CONFIG_VIDEO_V4L1_COMPAT + .vidiocgmbuf = vidiocgmbuf, +#endif +#ifdef TUNER_FLAG + .vidioc_g_tuner = vidioc_g_tuner, + .vidioc_s_tuner = vidioc_s_tuner, + .vidioc_g_frequency = vidioc_g_frequency, + .vidioc_s_frequency = vidioc_s_frequency, +#endif +#ifdef CONFIG_VIDEO_ADV_DEBUG + .vidioc_g_register = vidioc_g_register, + .vidioc_s_register = vidioc_s_register, +#endif +}; + +struct video_device cx25821_video_template0 = { + .name = "cx25821-video", + .fops = &video_fops, + .minor = -1, + .ioctl_ops = &video_ioctl_ops, + .tvnorms = CX25821_NORMS, + .current_norm = V4L2_STD_NTSC_M, +}; diff --git a/drivers/staging/cx25821/cx25821-video1.c b/drivers/staging/cx25821/cx25821-video1.c new file mode 100644 index 000000000000..a4dddc684adf --- /dev/null +++ b/drivers/staging/cx25821/cx25821-video1.c @@ -0,0 +1,451 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821-video.h" + +static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct cx25821_buffer *buf = + container_of(vb, struct cx25821_buffer, vb); + struct cx25821_buffer *prev; + struct cx25821_fh *fh = vq->priv_data; + struct cx25821_dev *dev = fh->dev; + struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH01]; + + /* add jump to stopper */ + buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); + buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); + buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ + + dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); + + if (!list_empty(&q->queued)) { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, + buf->vb.i); + + } else if (list_empty(&q->active)) { + list_add_tail(&buf->vb.queue, &q->active); + cx25821_start_video_dma(dev, q, buf, + &dev->sram_channels[SRAM_CH01]); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT); + dprintk(2, + "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", + buf, buf->vb.i, buf->count, q->count); + } else { + prev = + list_entry(q->active.prev, struct cx25821_buffer, vb.queue); + if (prev->vb.width == buf->vb.width + && prev->vb.height == buf->vb.height + && prev->fmt == buf->fmt) { + list_add_tail(&buf->vb.queue, &q->active); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); + + /* 64 bit bits 63-32 */ + prev->risc.jmp[2] = cpu_to_le32(0); + dprintk(2, + "[%p/%d] buffer_queue - append to active, buf->count=%d\n", + buf, buf->vb.i, buf->count); + + } else { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, + buf->vb.i); + } + } + + if (list_empty(&q->active)) { + dprintk(2, "active queue empty!\n"); + } +} + +static struct videobuf_queue_ops cx25821_video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +static int video_open(struct file *file) +{ + int minor = video_devdata(file)->minor; + struct cx25821_dev *h, *dev = NULL; + struct cx25821_fh *fh; + struct list_head *list; + enum v4l2_buf_type type = 0; + u32 pix_format; + + lock_kernel(); + list_for_each(list, &cx25821_devlist) { + h = list_entry(list, struct cx25821_dev, devlist); + + if (h->video_dev[SRAM_CH01] + && h->video_dev[SRAM_CH01]->minor == minor) { + dev = h; + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + } + } + + if (NULL == dev) { + unlock_kernel(); + return -ENODEV; + } + + printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); + + /* allocate + initialize per filehandle data */ + fh = kzalloc(sizeof(*fh), GFP_KERNEL); + if (NULL == fh) { + unlock_kernel(); + return -ENOMEM; + } + + file->private_data = fh; + fh->dev = dev; + fh->type = type; + fh->width = 720; + + if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) + fh->height = 576; + else + fh->height = 480; + + dev->channel_opened = SRAM_CH01; + pix_format = + (dev->pixel_formats[dev->channel_opened] == + PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV; + fh->fmt = format_by_fourcc(pix_format); + + v4l2_prio_open(&dev->prio, &fh->prio); + + videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, + &dev->pci->dev, &dev->slock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_INTERLACED, + sizeof(struct cx25821_buffer), fh); + + dprintk(1, "post videobuf_queue_init()\n"); + unlock_kernel(); + + return 0; +} + +static ssize_t video_read(struct file *file, char __user * data, size_t count, + loff_t * ppos) +{ + struct cx25821_fh *fh = file->private_data; + + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + if (res_locked(fh->dev, RESOURCE_VIDEO1)) + return -EBUSY; + + return videobuf_read_one(&fh->vidq, data, count, ppos, + file->f_flags & O_NONBLOCK); + + default: + BUG(); + return 0; + } +} + +static unsigned int video_poll(struct file *file, + struct poll_table_struct *wait) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_buffer *buf; + + if (res_check(fh, RESOURCE_VIDEO1)) { + /* streaming capture */ + if (list_empty(&fh->vidq.stream)) + return POLLERR; + buf = list_entry(fh->vidq.stream.next, + struct cx25821_buffer, vb.stream); + } else { + /* read() capture */ + buf = (struct cx25821_buffer *)fh->vidq.read_buf; + if (NULL == buf) + return POLLERR; + } + + poll_wait(file, &buf->vb.done, wait); + if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) { + if (buf->vb.state == VIDEOBUF_DONE) { + struct cx25821_dev *dev = fh->dev; + + if (dev && dev->use_cif_resolution[SRAM_CH01]) { + u8 cam_id = *((char *)buf->vb.baddr + 3); + memcpy((char *)buf->vb.baddr, + (char *)buf->vb.baddr + (fh->width * 2), + (fh->width * 2)); + *((char *)buf->vb.baddr + 3) = cam_id; + } + } + + return POLLIN | POLLRDNORM; + } + + return 0; +} + +static int video_release(struct file *file) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_dev *dev = fh->dev; + + //stop the risc engine and fifo + cx_write(channel1->dma_ctl, 0); /* FIFO and RISC disable */ + + /* stop video capture */ + if (res_check(fh, RESOURCE_VIDEO1)) { + videobuf_queue_cancel(&fh->vidq); + res_free(dev, fh, RESOURCE_VIDEO1); + } + + if (fh->vidq.read_buf) { + buffer_release(&fh->vidq, fh->vidq.read_buf); + kfree(fh->vidq.read_buf); + } + + videobuf_mmap_free(&fh->vidq); + + v4l2_prio_close(&dev->prio, &fh->prio); + file->private_data = NULL; + kfree(fh); + + return 0; +} + +static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + + if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) { + return -EINVAL; + } + + if (unlikely(i != fh->type)) { + return -EINVAL; + } + + if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO1)))) { + return -EBUSY; + } + + return videobuf_streamon(get_queue(fh)); +} + +static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + int err, res; + + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + if (i != fh->type) + return -EINVAL; + + res = get_resource(fh, RESOURCE_VIDEO1); + err = videobuf_streamoff(get_queue(fh)); + if (err < 0) + return err; + res_free(dev, fh, res); + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + int pix_format = 0; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + dprintk(2, "%s()\n", __func__); + err = vidioc_try_fmt_vid_cap(file, priv, f); + + if (0 != err) + return err; + + fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); + fh->vidq.field = f->fmt.pix.field; + + // check if width and height is valid based on set standard + if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) { + fh->width = f->fmt.pix.width; + } + + if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) { + fh->height = f->fmt.pix.height; + } + + if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) + pix_format = PIXEL_FRMT_411; + else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) + pix_format = PIXEL_FRMT_422; + else + return -EINVAL; + + cx25821_set_pixel_format(dev, SRAM_CH01, pix_format); + + // check if cif resolution + if (fh->width == 320 || fh->width == 352) { + dev->use_cif_resolution[SRAM_CH01] = 1; + } else { + dev->use_cif_resolution[SRAM_CH01] = 0; + } + dev->cif_width[SRAM_CH01] = fh->width; + medusa_set_resolution(dev, fh->width, SRAM_CH01); + + dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, + fh->height, fh->vidq.field); + cx25821_call_all(dev, video, s_fmt, f); + + return 0; +} + +static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + int ret_val = 0; + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + + ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); + + p->sequence = dev->vidq[SRAM_CH01].count; + + return ret_val; +} + +static int vidioc_log_status(struct file *file, void *priv) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + char name[32 + 2]; + + struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH01]; + u32 tmp = 0; + + snprintf(name, sizeof(name), "%s/2", dev->name); + printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", + dev->name); + cx25821_call_all(dev, core, log_status); + tmp = cx_read(sram_ch->dma_ctl); + printk(KERN_INFO "Video input 1 is %s\n", + (tmp & 0x11) ? "streaming" : "stopped"); + printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", + dev->name); + return 0; +} + +static int vidioc_s_ctrl(struct file *file, void *priv, + struct v4l2_control *ctl) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + return cx25821_set_control(dev, ctl, SRAM_CH01); +} + +//exported stuff +static const struct v4l2_file_operations video_fops = { + .owner = THIS_MODULE, + .open = video_open, + .release = video_release, + .read = video_read, + .poll = video_poll, + .mmap = video_mmap, + .ioctl = video_ioctl2, +}; + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, +#ifdef TUNER_FLAG + .vidioc_s_std = vidioc_s_std, + .vidioc_querystd = vidioc_querystd, +#endif + .vidioc_cropcap = vidioc_cropcap, + .vidioc_s_crop = vidioc_s_crop, + .vidioc_g_crop = vidioc_g_crop, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_g_ctrl = vidioc_g_ctrl, + .vidioc_s_ctrl = vidioc_s_ctrl, + .vidioc_queryctrl = vidioc_queryctrl, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_log_status = vidioc_log_status, + .vidioc_g_priority = vidioc_g_priority, + .vidioc_s_priority = vidioc_s_priority, +#ifdef CONFIG_VIDEO_V4L1_COMPAT + .vidiocgmbuf = vidiocgmbuf, +#endif +#ifdef TUNER_FLAG + .vidioc_g_tuner = vidioc_g_tuner, + .vidioc_s_tuner = vidioc_s_tuner, + .vidioc_g_frequency = vidioc_g_frequency, + .vidioc_s_frequency = vidioc_s_frequency, +#endif +#ifdef CONFIG_VIDEO_ADV_DEBUG + .vidioc_g_register = vidioc_g_register, + .vidioc_s_register = vidioc_s_register, +#endif +}; + +struct video_device cx25821_video_template1 = { + .name = "cx25821-video", + .fops = &video_fops, + .minor = -1, + .ioctl_ops = &video_ioctl_ops, + .tvnorms = CX25821_NORMS, + .current_norm = V4L2_STD_NTSC_M, +}; diff --git a/drivers/staging/cx25821/cx25821-video2.c b/drivers/staging/cx25821/cx25821-video2.c new file mode 100644 index 000000000000..8e04e253f5d9 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-video2.c @@ -0,0 +1,452 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821-video.h" + +static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct cx25821_buffer *buf = + container_of(vb, struct cx25821_buffer, vb); + struct cx25821_buffer *prev; + struct cx25821_fh *fh = vq->priv_data; + struct cx25821_dev *dev = fh->dev; + struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH02]; + + /* add jump to stopper */ + buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); + buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); + buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ + + dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); + + if (!list_empty(&q->queued)) { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, + buf->vb.i); + + } else if (list_empty(&q->active)) { + list_add_tail(&buf->vb.queue, &q->active); + cx25821_start_video_dma(dev, q, buf, + &dev->sram_channels[SRAM_CH02]); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT); + dprintk(2, + "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", + buf, buf->vb.i, buf->count, q->count); + } else { + prev = + list_entry(q->active.prev, struct cx25821_buffer, vb.queue); + if (prev->vb.width == buf->vb.width + && prev->vb.height == buf->vb.height + && prev->fmt == buf->fmt) { + list_add_tail(&buf->vb.queue, &q->active); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); + + /* 64 bit bits 63-32 */ + prev->risc.jmp[2] = cpu_to_le32(0); + dprintk(2, + "[%p/%d] buffer_queue - append to active, buf->count=%d\n", + buf, buf->vb.i, buf->count); + + } else { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, + buf->vb.i); + } + } + + if (list_empty(&q->active)) { + dprintk(2, "active queue empty!\n"); + } +} + +static struct videobuf_queue_ops cx25821_video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +static int video_open(struct file *file) +{ + int minor = video_devdata(file)->minor; + struct cx25821_dev *h, *dev = NULL; + struct cx25821_fh *fh; + struct list_head *list; + enum v4l2_buf_type type = 0; + u32 pix_format; + + lock_kernel(); + list_for_each(list, &cx25821_devlist) { + h = list_entry(list, struct cx25821_dev, devlist); + + if (h->video_dev[SRAM_CH02] + && h->video_dev[SRAM_CH02]->minor == minor) { + dev = h; + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + } + } + + if (NULL == dev) { + unlock_kernel(); + return -ENODEV; + } + + printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); + + /* allocate + initialize per filehandle data */ + fh = kzalloc(sizeof(*fh), GFP_KERNEL); + if (NULL == fh) { + unlock_kernel(); + return -ENOMEM; + } + file->private_data = fh; + fh->dev = dev; + fh->type = type; + fh->width = 720; + + if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) + fh->height = 576; + else + fh->height = 480; + + dev->channel_opened = SRAM_CH02; + pix_format = + (dev->pixel_formats[dev->channel_opened] == + PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV; + fh->fmt = format_by_fourcc(pix_format); + + v4l2_prio_open(&dev->prio, &fh->prio); + + videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, + &dev->pci->dev, &dev->slock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_INTERLACED, + sizeof(struct cx25821_buffer), fh); + + dprintk(1, "post videobuf_queue_init()\n"); + unlock_kernel(); + + return 0; +} + +static ssize_t video_read(struct file *file, char __user * data, size_t count, + loff_t * ppos) +{ + struct cx25821_fh *fh = file->private_data; + + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + if (res_locked(fh->dev, RESOURCE_VIDEO2)) + return -EBUSY; + + return videobuf_read_one(&fh->vidq, data, count, ppos, + file->f_flags & O_NONBLOCK); + + default: + BUG(); + return 0; + } +} + +static unsigned int video_poll(struct file *file, + struct poll_table_struct *wait) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_buffer *buf; + + if (res_check(fh, RESOURCE_VIDEO2)) { + /* streaming capture */ + if (list_empty(&fh->vidq.stream)) + return POLLERR; + buf = list_entry(fh->vidq.stream.next, + struct cx25821_buffer, vb.stream); + } else { + /* read() capture */ + buf = (struct cx25821_buffer *)fh->vidq.read_buf; + if (NULL == buf) + return POLLERR; + } + + poll_wait(file, &buf->vb.done, wait); + if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) { + if (buf->vb.state == VIDEOBUF_DONE) { + struct cx25821_dev *dev = fh->dev; + + if (dev && dev->use_cif_resolution[SRAM_CH02]) { + u8 cam_id = *((char *)buf->vb.baddr + 3); + memcpy((char *)buf->vb.baddr, + (char *)buf->vb.baddr + (fh->width * 2), + (fh->width * 2)); + *((char *)buf->vb.baddr + 3) = cam_id; + } + } + + return POLLIN | POLLRDNORM; + } + + return 0; +} + +static int video_release(struct file *file) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_dev *dev = fh->dev; + + //stop the risc engine and fifo + cx_write(channel2->dma_ctl, 0); /* FIFO and RISC disable */ + + /* stop video capture */ + if (res_check(fh, RESOURCE_VIDEO2)) { + videobuf_queue_cancel(&fh->vidq); + res_free(dev, fh, RESOURCE_VIDEO2); + } + + if (fh->vidq.read_buf) { + buffer_release(&fh->vidq, fh->vidq.read_buf); + kfree(fh->vidq.read_buf); + } + + videobuf_mmap_free(&fh->vidq); + + v4l2_prio_close(&dev->prio, &fh->prio); + file->private_data = NULL; + kfree(fh); + + return 0; +} + +static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + + if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) { + return -EINVAL; + } + + if (unlikely(i != fh->type)) { + return -EINVAL; + } + + if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO2)))) { + return -EBUSY; + } + + return videobuf_streamon(get_queue(fh)); +} + +static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + int err, res; + + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + if (i != fh->type) + return -EINVAL; + + res = get_resource(fh, RESOURCE_VIDEO2); + err = videobuf_streamoff(get_queue(fh)); + if (err < 0) + return err; + res_free(dev, fh, res); + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + int pix_format = 0; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + dprintk(2, "%s()\n", __func__); + err = vidioc_try_fmt_vid_cap(file, priv, f); + + if (0 != err) + return err; + + fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); + fh->vidq.field = f->fmt.pix.field; + + // check if width and height is valid based on set standard + if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) { + fh->width = f->fmt.pix.width; + } + + if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) { + fh->height = f->fmt.pix.height; + } + + if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) + pix_format = PIXEL_FRMT_411; + else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) + pix_format = PIXEL_FRMT_422; + else + return -EINVAL; + + cx25821_set_pixel_format(dev, SRAM_CH02, pix_format); + + // check if cif resolution + if (fh->width == 320 || fh->width == 352) { + dev->use_cif_resolution[SRAM_CH02] = 1; + } else { + dev->use_cif_resolution[SRAM_CH02] = 0; + } + dev->cif_width[SRAM_CH02] = fh->width; + medusa_set_resolution(dev, fh->width, SRAM_CH02); + + dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, + fh->height, fh->vidq.field); + cx25821_call_all(dev, video, s_fmt, f); + + return 0; +} + +static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + int ret_val = 0; + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + + ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); + + p->sequence = dev->vidq[SRAM_CH02].count; + + return ret_val; +} + +static int vidioc_log_status(struct file *file, void *priv) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + char name[32 + 2]; + + struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH02]; + u32 tmp = 0; + + snprintf(name, sizeof(name), "%s/2", dev->name); + printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", + dev->name); + + cx25821_call_all(dev, core, log_status); + + tmp = cx_read(sram_ch->dma_ctl); + printk(KERN_INFO "Video input 2 is %s\n", + (tmp & 0x11) ? "streaming" : "stopped"); + printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", + dev->name); + return 0; +} + +static int vidioc_s_ctrl(struct file *file, void *priv, + struct v4l2_control *ctl) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + return cx25821_set_control(dev, ctl, SRAM_CH02); +} + +// exported stuff +static const struct v4l2_file_operations video_fops = { + .owner = THIS_MODULE, + .open = video_open, + .release = video_release, + .read = video_read, + .poll = video_poll, + .mmap = video_mmap, + .ioctl = video_ioctl2, +}; + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, +#ifdef TUNER_FLAG + .vidioc_s_std = vidioc_s_std, + .vidioc_querystd = vidioc_querystd, +#endif + .vidioc_cropcap = vidioc_cropcap, + .vidioc_s_crop = vidioc_s_crop, + .vidioc_g_crop = vidioc_g_crop, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_g_ctrl = vidioc_g_ctrl, + .vidioc_s_ctrl = vidioc_s_ctrl, + .vidioc_queryctrl = vidioc_queryctrl, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_log_status = vidioc_log_status, + .vidioc_g_priority = vidioc_g_priority, + .vidioc_s_priority = vidioc_s_priority, +#ifdef CONFIG_VIDEO_V4L1_COMPAT + .vidiocgmbuf = vidiocgmbuf, +#endif +#ifdef TUNER_FLAG + .vidioc_g_tuner = vidioc_g_tuner, + .vidioc_s_tuner = vidioc_s_tuner, + .vidioc_g_frequency = vidioc_g_frequency, + .vidioc_s_frequency = vidioc_s_frequency, +#endif +#ifdef CONFIG_VIDEO_ADV_DEBUG + .vidioc_g_register = vidioc_g_register, + .vidioc_s_register = vidioc_s_register, +#endif +}; + +struct video_device cx25821_video_template2 = { + .name = "cx25821-video", + .fops = &video_fops, + .minor = -1, + .ioctl_ops = &video_ioctl_ops, + .tvnorms = CX25821_NORMS, + .current_norm = V4L2_STD_NTSC_M, +}; diff --git a/drivers/staging/cx25821/cx25821-video3.c b/drivers/staging/cx25821/cx25821-video3.c new file mode 100644 index 000000000000..8801a8ead904 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-video3.c @@ -0,0 +1,451 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821-video.h" + +static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct cx25821_buffer *buf = + container_of(vb, struct cx25821_buffer, vb); + struct cx25821_buffer *prev; + struct cx25821_fh *fh = vq->priv_data; + struct cx25821_dev *dev = fh->dev; + struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH03]; + + /* add jump to stopper */ + buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); + buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); + buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ + + dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); + + if (!list_empty(&q->queued)) { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, + buf->vb.i); + + } else if (list_empty(&q->active)) { + list_add_tail(&buf->vb.queue, &q->active); + cx25821_start_video_dma(dev, q, buf, + &dev->sram_channels[SRAM_CH03]); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT); + dprintk(2, + "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", + buf, buf->vb.i, buf->count, q->count); + } else { + prev = + list_entry(q->active.prev, struct cx25821_buffer, vb.queue); + if (prev->vb.width == buf->vb.width + && prev->vb.height == buf->vb.height + && prev->fmt == buf->fmt) { + list_add_tail(&buf->vb.queue, &q->active); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); + + /* 64 bit bits 63-32 */ + prev->risc.jmp[2] = cpu_to_le32(0); + dprintk(2, + "[%p/%d] buffer_queue - append to active, buf->count=%d\n", + buf, buf->vb.i, buf->count); + + } else { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, + buf->vb.i); + } + } + + if (list_empty(&q->active)) { + dprintk(2, "active queue empty!\n"); + } +} + +static struct videobuf_queue_ops cx25821_video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +static int video_open(struct file *file) +{ + int minor = video_devdata(file)->minor; + struct cx25821_dev *h, *dev = NULL; + struct cx25821_fh *fh; + struct list_head *list; + enum v4l2_buf_type type = 0; + u32 pix_format; + + lock_kernel(); + list_for_each(list, &cx25821_devlist) { + h = list_entry(list, struct cx25821_dev, devlist); + + if (h->video_dev[SRAM_CH03] + && h->video_dev[SRAM_CH03]->minor == minor) { + dev = h; + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + } + } + + if (NULL == dev) { + unlock_kernel(); + return -ENODEV; + } + + printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); + + /* allocate + initialize per filehandle data */ + fh = kzalloc(sizeof(*fh), GFP_KERNEL); + if (NULL == fh) { + unlock_kernel(); + return -ENOMEM; + } + file->private_data = fh; + fh->dev = dev; + fh->type = type; + fh->width = 720; + + if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) + fh->height = 576; + else + fh->height = 480; + + dev->channel_opened = SRAM_CH03; + pix_format = + (dev->pixel_formats[dev->channel_opened] == + PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV; + fh->fmt = format_by_fourcc(pix_format); + + v4l2_prio_open(&dev->prio, &fh->prio); + + videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, + &dev->pci->dev, &dev->slock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_INTERLACED, + sizeof(struct cx25821_buffer), fh); + + dprintk(1, "post videobuf_queue_init()\n"); + unlock_kernel(); + + return 0; +} + +static ssize_t video_read(struct file *file, char __user * data, size_t count, + loff_t * ppos) +{ + struct cx25821_fh *fh = file->private_data; + + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + if (res_locked(fh->dev, RESOURCE_VIDEO3)) + return -EBUSY; + + return videobuf_read_one(&fh->vidq, data, count, ppos, + file->f_flags & O_NONBLOCK); + + default: + BUG(); + return 0; + } +} + +static unsigned int video_poll(struct file *file, + struct poll_table_struct *wait) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_buffer *buf; + + if (res_check(fh, RESOURCE_VIDEO3)) { + /* streaming capture */ + if (list_empty(&fh->vidq.stream)) + return POLLERR; + buf = list_entry(fh->vidq.stream.next, + struct cx25821_buffer, vb.stream); + } else { + /* read() capture */ + buf = (struct cx25821_buffer *)fh->vidq.read_buf; + if (NULL == buf) + return POLLERR; + } + + poll_wait(file, &buf->vb.done, wait); + if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) { + if (buf->vb.state == VIDEOBUF_DONE) { + struct cx25821_dev *dev = fh->dev; + + if (dev && dev->use_cif_resolution[SRAM_CH03]) { + u8 cam_id = *((char *)buf->vb.baddr + 3); + memcpy((char *)buf->vb.baddr, + (char *)buf->vb.baddr + (fh->width * 2), + (fh->width * 2)); + *((char *)buf->vb.baddr + 3) = cam_id; + } + } + + return POLLIN | POLLRDNORM; + } + + return 0; +} + +static int video_release(struct file *file) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_dev *dev = fh->dev; + + //stop the risc engine and fifo + cx_write(channel3->dma_ctl, 0); /* FIFO and RISC disable */ + + /* stop video capture */ + if (res_check(fh, RESOURCE_VIDEO3)) { + videobuf_queue_cancel(&fh->vidq); + res_free(dev, fh, RESOURCE_VIDEO3); + } + + if (fh->vidq.read_buf) { + buffer_release(&fh->vidq, fh->vidq.read_buf); + kfree(fh->vidq.read_buf); + } + + videobuf_mmap_free(&fh->vidq); + + v4l2_prio_close(&dev->prio, &fh->prio); + file->private_data = NULL; + kfree(fh); + + return 0; +} + +static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + + if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) { + return -EINVAL; + } + + if (unlikely(i != fh->type)) { + return -EINVAL; + } + + if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO3)))) { + return -EBUSY; + } + + return videobuf_streamon(get_queue(fh)); +} + +static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + int err, res; + + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + if (i != fh->type) + return -EINVAL; + + res = get_resource(fh, RESOURCE_VIDEO3); + err = videobuf_streamoff(get_queue(fh)); + if (err < 0) + return err; + res_free(dev, fh, res); + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + int pix_format = 0; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + dprintk(2, "%s()\n", __func__); + err = vidioc_try_fmt_vid_cap(file, priv, f); + + if (0 != err) + return err; + + fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); + fh->vidq.field = f->fmt.pix.field; + + // check if width and height is valid based on set standard + if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) { + fh->width = f->fmt.pix.width; + } + + if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) { + fh->height = f->fmt.pix.height; + } + + if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) + pix_format = PIXEL_FRMT_411; + else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) + pix_format = PIXEL_FRMT_422; + else + return -EINVAL; + + cx25821_set_pixel_format(dev, SRAM_CH03, pix_format); + + // check if cif resolution + if (fh->width == 320 || fh->width == 352) { + dev->use_cif_resolution[SRAM_CH03] = 1; + } else { + dev->use_cif_resolution[SRAM_CH03] = 0; + } + dev->cif_width[SRAM_CH03] = fh->width; + medusa_set_resolution(dev, fh->width, SRAM_CH03); + + dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, + fh->height, fh->vidq.field); + cx25821_call_all(dev, video, s_fmt, f); + + return 0; +} + +static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + int ret_val = 0; + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + + ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); + + p->sequence = dev->vidq[SRAM_CH03].count; + + return ret_val; +} + +static int vidioc_log_status(struct file *file, void *priv) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + char name[32 + 2]; + + struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH03]; + u32 tmp = 0; + + snprintf(name, sizeof(name), "%s/2", dev->name); + printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", + dev->name); + cx25821_call_all(dev, core, log_status); + + tmp = cx_read(sram_ch->dma_ctl); + printk(KERN_INFO "Video input 3 is %s\n", + (tmp & 0x11) ? "streaming" : "stopped"); + printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", + dev->name); + return 0; +} + +static int vidioc_s_ctrl(struct file *file, void *priv, + struct v4l2_control *ctl) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + return cx25821_set_control(dev, ctl, SRAM_CH03); +} + +// exported stuff +static const struct v4l2_file_operations video_fops = { + .owner = THIS_MODULE, + .open = video_open, + .release = video_release, + .read = video_read, + .poll = video_poll, + .mmap = video_mmap, + .ioctl = video_ioctl2, +}; + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, +#ifdef TUNER_FLAG + .vidioc_s_std = vidioc_s_std, + .vidioc_querystd = vidioc_querystd, +#endif + .vidioc_cropcap = vidioc_cropcap, + .vidioc_s_crop = vidioc_s_crop, + .vidioc_g_crop = vidioc_g_crop, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_g_ctrl = vidioc_g_ctrl, + .vidioc_s_ctrl = vidioc_s_ctrl, + .vidioc_queryctrl = vidioc_queryctrl, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_log_status = vidioc_log_status, + .vidioc_g_priority = vidioc_g_priority, + .vidioc_s_priority = vidioc_s_priority, +#ifdef CONFIG_VIDEO_V4L1_COMPAT + .vidiocgmbuf = vidiocgmbuf, +#endif +#ifdef TUNER_FLAG + .vidioc_g_tuner = vidioc_g_tuner, + .vidioc_s_tuner = vidioc_s_tuner, + .vidioc_g_frequency = vidioc_g_frequency, + .vidioc_s_frequency = vidioc_s_frequency, +#endif +#ifdef CONFIG_VIDEO_ADV_DEBUG + .vidioc_g_register = vidioc_g_register, + .vidioc_s_register = vidioc_s_register, +#endif +}; + +struct video_device cx25821_video_template3 = { + .name = "cx25821-video", + .fops = &video_fops, + .minor = -1, + .ioctl_ops = &video_ioctl_ops, + .tvnorms = CX25821_NORMS, + .current_norm = V4L2_STD_NTSC_M, +}; diff --git a/drivers/staging/cx25821/cx25821-video4.c b/drivers/staging/cx25821/cx25821-video4.c new file mode 100644 index 000000000000..ab0d747138ad --- /dev/null +++ b/drivers/staging/cx25821/cx25821-video4.c @@ -0,0 +1,450 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821-video.h" + +static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct cx25821_buffer *buf = + container_of(vb, struct cx25821_buffer, vb); + struct cx25821_buffer *prev; + struct cx25821_fh *fh = vq->priv_data; + struct cx25821_dev *dev = fh->dev; + struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH04]; + + /* add jump to stopper */ + buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); + buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); + buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ + + dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); + + if (!list_empty(&q->queued)) { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, + buf->vb.i); + + } else if (list_empty(&q->active)) { + list_add_tail(&buf->vb.queue, &q->active); + cx25821_start_video_dma(dev, q, buf, + &dev->sram_channels[SRAM_CH04]); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT); + dprintk(2, + "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", + buf, buf->vb.i, buf->count, q->count); + } else { + prev = + list_entry(q->active.prev, struct cx25821_buffer, vb.queue); + if (prev->vb.width == buf->vb.width + && prev->vb.height == buf->vb.height + && prev->fmt == buf->fmt) { + list_add_tail(&buf->vb.queue, &q->active); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); + + /* 64 bit bits 63-32 */ + prev->risc.jmp[2] = cpu_to_le32(0); + dprintk(2, + "[%p/%d] buffer_queue - append to active, buf->count=%d\n", + buf, buf->vb.i, buf->count); + + } else { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, + buf->vb.i); + } + } + + if (list_empty(&q->active)) { + dprintk(2, "active queue empty!\n"); + } +} + +static struct videobuf_queue_ops cx25821_video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +static int video_open(struct file *file) +{ + int minor = video_devdata(file)->minor; + struct cx25821_dev *h, *dev = NULL; + struct cx25821_fh *fh; + struct list_head *list; + enum v4l2_buf_type type = 0; + u32 pix_format; + + lock_kernel(); + list_for_each(list, &cx25821_devlist) { + h = list_entry(list, struct cx25821_dev, devlist); + + if (h->video_dev[SRAM_CH04] + && h->video_dev[SRAM_CH04]->minor == minor) { + dev = h; + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + } + } + + if (NULL == dev) { + unlock_kernel(); + return -ENODEV; + } + + printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); + + /* allocate + initialize per filehandle data */ + fh = kzalloc(sizeof(*fh), GFP_KERNEL); + if (NULL == fh) { + unlock_kernel(); + return -ENOMEM; + } + file->private_data = fh; + fh->dev = dev; + fh->type = type; + fh->width = 720; + + if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) + fh->height = 576; + else + fh->height = 480; + + dev->channel_opened = SRAM_CH04; + pix_format = + (dev->pixel_formats[dev->channel_opened] == + PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV; + fh->fmt = format_by_fourcc(pix_format); + + v4l2_prio_open(&dev->prio, &fh->prio); + videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, + &dev->pci->dev, &dev->slock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_INTERLACED, + sizeof(struct cx25821_buffer), fh); + + dprintk(1, "post videobuf_queue_init()\n"); + unlock_kernel(); + + return 0; +} + +static ssize_t video_read(struct file *file, char __user * data, size_t count, + loff_t * ppos) +{ + struct cx25821_fh *fh = file->private_data; + + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + if (res_locked(fh->dev, RESOURCE_VIDEO4)) + return -EBUSY; + + return videobuf_read_one(&fh->vidq, data, count, ppos, + file->f_flags & O_NONBLOCK); + + default: + BUG(); + return 0; + } +} + +static unsigned int video_poll(struct file *file, + struct poll_table_struct *wait) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_buffer *buf; + + if (res_check(fh, RESOURCE_VIDEO4)) { + /* streaming capture */ + if (list_empty(&fh->vidq.stream)) + return POLLERR; + buf = list_entry(fh->vidq.stream.next, + struct cx25821_buffer, vb.stream); + } else { + /* read() capture */ + buf = (struct cx25821_buffer *)fh->vidq.read_buf; + if (NULL == buf) + return POLLERR; + } + + poll_wait(file, &buf->vb.done, wait); + if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) { + if (buf->vb.state == VIDEOBUF_DONE) { + struct cx25821_dev *dev = fh->dev; + + if (dev && dev->use_cif_resolution[SRAM_CH04]) { + u8 cam_id = *((char *)buf->vb.baddr + 3); + memcpy((char *)buf->vb.baddr, + (char *)buf->vb.baddr + (fh->width * 2), + (fh->width * 2)); + *((char *)buf->vb.baddr + 3) = cam_id; + } + } + + return POLLIN | POLLRDNORM; + } + + return 0; +} + +static int video_release(struct file *file) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_dev *dev = fh->dev; + + //stop the risc engine and fifo + cx_write(channel4->dma_ctl, 0); /* FIFO and RISC disable */ + + /* stop video capture */ + if (res_check(fh, RESOURCE_VIDEO4)) { + videobuf_queue_cancel(&fh->vidq); + res_free(dev, fh, RESOURCE_VIDEO4); + } + + if (fh->vidq.read_buf) { + buffer_release(&fh->vidq, fh->vidq.read_buf); + kfree(fh->vidq.read_buf); + } + + videobuf_mmap_free(&fh->vidq); + + v4l2_prio_close(&dev->prio, &fh->prio); + file->private_data = NULL; + kfree(fh); + + return 0; +} + +static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + + if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) { + return -EINVAL; + } + + if (unlikely(i != fh->type)) { + return -EINVAL; + } + + if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO4)))) { + return -EBUSY; + } + + return videobuf_streamon(get_queue(fh)); +} + +static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + int err, res; + + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + if (i != fh->type) + return -EINVAL; + + res = get_resource(fh, RESOURCE_VIDEO4); + err = videobuf_streamoff(get_queue(fh)); + if (err < 0) + return err; + res_free(dev, fh, res); + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + int pix_format = 0; + + // check priority + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + dprintk(2, "%s()\n", __func__); + err = vidioc_try_fmt_vid_cap(file, priv, f); + + if (0 != err) + return err; + + fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); + fh->vidq.field = f->fmt.pix.field; + + // check if width and height is valid based on set standard + if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) { + fh->width = f->fmt.pix.width; + } + + if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) { + fh->height = f->fmt.pix.height; + } + + if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) + pix_format = PIXEL_FRMT_411; + else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) + pix_format = PIXEL_FRMT_422; + else + return -EINVAL; + + cx25821_set_pixel_format(dev, SRAM_CH04, pix_format); + + // check if cif resolution + if (fh->width == 320 || fh->width == 352) { + dev->use_cif_resolution[SRAM_CH04] = 1; + } else { + dev->use_cif_resolution[SRAM_CH04] = 0; + } + dev->cif_width[SRAM_CH04] = fh->width; + medusa_set_resolution(dev, fh->width, SRAM_CH04); + + dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, + fh->height, fh->vidq.field); + cx25821_call_all(dev, video, s_fmt, f); + + return 0; +} + +static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + int ret_val = 0; + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + + ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); + + p->sequence = dev->vidq[SRAM_CH04].count; + + return ret_val; +} + +static int vidioc_log_status(struct file *file, void *priv) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + char name[32 + 2]; + + struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH04]; + u32 tmp = 0; + + snprintf(name, sizeof(name), "%s/2", dev->name); + printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", + dev->name); + cx25821_call_all(dev, core, log_status); + + tmp = cx_read(sram_ch->dma_ctl); + printk(KERN_INFO "Video input 4 is %s\n", + (tmp & 0x11) ? "streaming" : "stopped"); + printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", + dev->name); + return 0; +} + +static int vidioc_s_ctrl(struct file *file, void *priv, + struct v4l2_control *ctl) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + return cx25821_set_control(dev, ctl, SRAM_CH04); +} + +// exported stuff +static const struct v4l2_file_operations video_fops = { + .owner = THIS_MODULE, + .open = video_open, + .release = video_release, + .read = video_read, + .poll = video_poll, + .mmap = video_mmap, + .ioctl = video_ioctl2, +}; + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, +#ifdef TUNER_FLAG + .vidioc_s_std = vidioc_s_std, + .vidioc_querystd = vidioc_querystd, +#endif + .vidioc_cropcap = vidioc_cropcap, + .vidioc_s_crop = vidioc_s_crop, + .vidioc_g_crop = vidioc_g_crop, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_g_ctrl = vidioc_g_ctrl, + .vidioc_s_ctrl = vidioc_s_ctrl, + .vidioc_queryctrl = vidioc_queryctrl, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_log_status = vidioc_log_status, + .vidioc_g_priority = vidioc_g_priority, + .vidioc_s_priority = vidioc_s_priority, +#ifdef CONFIG_VIDEO_V4L1_COMPAT + .vidiocgmbuf = vidiocgmbuf, +#endif +#ifdef TUNER_FLAG + .vidioc_g_tuner = vidioc_g_tuner, + .vidioc_s_tuner = vidioc_s_tuner, + .vidioc_g_frequency = vidioc_g_frequency, + .vidioc_s_frequency = vidioc_s_frequency, +#endif +#ifdef CONFIG_VIDEO_ADV_DEBUG + .vidioc_g_register = vidioc_g_register, + .vidioc_s_register = vidioc_s_register, +#endif +}; + +struct video_device cx25821_video_template4 = { + .name = "cx25821-video", + .fops = &video_fops, + .minor = -1, + .ioctl_ops = &video_ioctl_ops, + .tvnorms = CX25821_NORMS, + .current_norm = V4L2_STD_NTSC_M, +}; diff --git a/drivers/staging/cx25821/cx25821-video5.c b/drivers/staging/cx25821/cx25821-video5.c new file mode 100644 index 000000000000..7ef0b971f5cf --- /dev/null +++ b/drivers/staging/cx25821/cx25821-video5.c @@ -0,0 +1,450 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821-video.h" + +static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct cx25821_buffer *buf = + container_of(vb, struct cx25821_buffer, vb); + struct cx25821_buffer *prev; + struct cx25821_fh *fh = vq->priv_data; + struct cx25821_dev *dev = fh->dev; + struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH05]; + + /* add jump to stopper */ + buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); + buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); + buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ + + dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); + + if (!list_empty(&q->queued)) { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, + buf->vb.i); + + } else if (list_empty(&q->active)) { + list_add_tail(&buf->vb.queue, &q->active); + cx25821_start_video_dma(dev, q, buf, + &dev->sram_channels[SRAM_CH05]); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT); + dprintk(2, + "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", + buf, buf->vb.i, buf->count, q->count); + } else { + prev = + list_entry(q->active.prev, struct cx25821_buffer, vb.queue); + if (prev->vb.width == buf->vb.width + && prev->vb.height == buf->vb.height + && prev->fmt == buf->fmt) { + list_add_tail(&buf->vb.queue, &q->active); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); + + /* 64 bit bits 63-32 */ + prev->risc.jmp[2] = cpu_to_le32(0); + dprintk(2, + "[%p/%d] buffer_queue - append to active, buf->count=%d\n", + buf, buf->vb.i, buf->count); + + } else { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, + buf->vb.i); + } + } + + if (list_empty(&q->active)) { + dprintk(2, "active queue empty!\n"); + } +} + +static struct videobuf_queue_ops cx25821_video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +static int video_open(struct file *file) +{ + int minor = video_devdata(file)->minor; + struct cx25821_dev *h, *dev = NULL; + struct cx25821_fh *fh; + struct list_head *list; + enum v4l2_buf_type type = 0; + u32 pix_format; + + lock_kernel(); + list_for_each(list, &cx25821_devlist) { + h = list_entry(list, struct cx25821_dev, devlist); + + if (h->video_dev[SRAM_CH05] + && h->video_dev[SRAM_CH05]->minor == minor) { + dev = h; + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + } + } + + if (NULL == dev) { + unlock_kernel(); + return -ENODEV; + } + + printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); + + /* allocate + initialize per filehandle data */ + fh = kzalloc(sizeof(*fh), GFP_KERNEL); + if (NULL == fh) { + unlock_kernel(); + return -ENOMEM; + } + file->private_data = fh; + fh->dev = dev; + fh->type = type; + fh->width = 720; + + if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) + fh->height = 576; + else + fh->height = 480; + + dev->channel_opened = SRAM_CH05; + pix_format = + (dev->pixel_formats[dev->channel_opened] == + PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV; + fh->fmt = format_by_fourcc(pix_format); + + v4l2_prio_open(&dev->prio, &fh->prio); + + videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, + &dev->pci->dev, &dev->slock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_INTERLACED, + sizeof(struct cx25821_buffer), fh); + + dprintk(1, "post videobuf_queue_init()\n"); + unlock_kernel(); + + return 0; +} + +static ssize_t video_read(struct file *file, char __user * data, size_t count, + loff_t * ppos) +{ + struct cx25821_fh *fh = file->private_data; + + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + if (res_locked(fh->dev, RESOURCE_VIDEO5)) + return -EBUSY; + + return videobuf_read_one(&fh->vidq, data, count, ppos, + file->f_flags & O_NONBLOCK); + + default: + BUG(); + return 0; + } +} + +static unsigned int video_poll(struct file *file, + struct poll_table_struct *wait) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_buffer *buf; + + if (res_check(fh, RESOURCE_VIDEO5)) { + /* streaming capture */ + if (list_empty(&fh->vidq.stream)) + return POLLERR; + buf = list_entry(fh->vidq.stream.next, + struct cx25821_buffer, vb.stream); + } else { + /* read() capture */ + buf = (struct cx25821_buffer *)fh->vidq.read_buf; + if (NULL == buf) + return POLLERR; + } + + poll_wait(file, &buf->vb.done, wait); + if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) { + if (buf->vb.state == VIDEOBUF_DONE) { + struct cx25821_dev *dev = fh->dev; + + if (dev && dev->use_cif_resolution[SRAM_CH05]) { + u8 cam_id = *((char *)buf->vb.baddr + 3); + memcpy((char *)buf->vb.baddr, + (char *)buf->vb.baddr + (fh->width * 2), + (fh->width * 2)); + *((char *)buf->vb.baddr + 3) = cam_id; + } + } + + return POLLIN | POLLRDNORM; + } + + return 0; +} + +static int video_release(struct file *file) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_dev *dev = fh->dev; + + //stop the risc engine and fifo + cx_write(channel5->dma_ctl, 0); /* FIFO and RISC disable */ + + /* stop video capture */ + if (res_check(fh, RESOURCE_VIDEO5)) { + videobuf_queue_cancel(&fh->vidq); + res_free(dev, fh, RESOURCE_VIDEO5); + } + + if (fh->vidq.read_buf) { + buffer_release(&fh->vidq, fh->vidq.read_buf); + kfree(fh->vidq.read_buf); + } + + videobuf_mmap_free(&fh->vidq); + + v4l2_prio_close(&dev->prio, &fh->prio); + file->private_data = NULL; + kfree(fh); + + return 0; +} + +static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + + if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) { + return -EINVAL; + } + + if (unlikely(i != fh->type)) { + return -EINVAL; + } + + if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO5)))) { + return -EBUSY; + } + + return videobuf_streamon(get_queue(fh)); +} + +static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + int err, res; + + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + if (i != fh->type) + return -EINVAL; + + res = get_resource(fh, RESOURCE_VIDEO5); + err = videobuf_streamoff(get_queue(fh)); + if (err < 0) + return err; + res_free(dev, fh, res); + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + int pix_format = 0; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + dprintk(2, "%s()\n", __func__); + err = vidioc_try_fmt_vid_cap(file, priv, f); + + if (0 != err) + return err; + + fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); + fh->vidq.field = f->fmt.pix.field; + + // check if width and height is valid based on set standard + if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) { + fh->width = f->fmt.pix.width; + } + + if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) { + fh->height = f->fmt.pix.height; + } + + if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) + pix_format = PIXEL_FRMT_411; + else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) + pix_format = PIXEL_FRMT_422; + else + return -EINVAL; + + cx25821_set_pixel_format(dev, SRAM_CH05, pix_format); + + // check if cif resolution + if (fh->width == 320 || fh->width == 352) { + dev->use_cif_resolution[SRAM_CH05] = 1; + } else { + dev->use_cif_resolution[SRAM_CH05] = 0; + } + dev->cif_width[SRAM_CH05] = fh->width; + medusa_set_resolution(dev, fh->width, SRAM_CH05); + + dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, + fh->height, fh->vidq.field); + cx25821_call_all(dev, video, s_fmt, f); + + return 0; +} + +static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + int ret_val = 0; + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + + ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); + + p->sequence = dev->vidq[SRAM_CH05].count; + + return ret_val; +} +static int vidioc_log_status(struct file *file, void *priv) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + char name[32 + 2]; + + struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH05]; + u32 tmp = 0; + + snprintf(name, sizeof(name), "%s/2", dev->name); + printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", + dev->name); + cx25821_call_all(dev, core, log_status); + + tmp = cx_read(sram_ch->dma_ctl); + printk(KERN_INFO "Video input 5 is %s\n", + (tmp & 0x11) ? "streaming" : "stopped"); + printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", + dev->name); + return 0; +} + +static int vidioc_s_ctrl(struct file *file, void *priv, + struct v4l2_control *ctl) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + return cx25821_set_control(dev, ctl, SRAM_CH05); +} + +// exported stuff +static const struct v4l2_file_operations video_fops = { + .owner = THIS_MODULE, + .open = video_open, + .release = video_release, + .read = video_read, + .poll = video_poll, + .mmap = video_mmap, + .ioctl = video_ioctl2, +}; + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, +#ifdef TUNER_FLAG + .vidioc_s_std = vidioc_s_std, + .vidioc_querystd = vidioc_querystd, +#endif + .vidioc_cropcap = vidioc_cropcap, + .vidioc_s_crop = vidioc_s_crop, + .vidioc_g_crop = vidioc_g_crop, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_g_ctrl = vidioc_g_ctrl, + .vidioc_s_ctrl = vidioc_s_ctrl, + .vidioc_queryctrl = vidioc_queryctrl, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_log_status = vidioc_log_status, + .vidioc_g_priority = vidioc_g_priority, + .vidioc_s_priority = vidioc_s_priority, +#ifdef CONFIG_VIDEO_V4L1_COMPAT + .vidiocgmbuf = vidiocgmbuf, +#endif +#ifdef TUNER_FLAG + .vidioc_g_tuner = vidioc_g_tuner, + .vidioc_s_tuner = vidioc_s_tuner, + .vidioc_g_frequency = vidioc_g_frequency, + .vidioc_s_frequency = vidioc_s_frequency, +#endif +#ifdef CONFIG_VIDEO_ADV_DEBUG + .vidioc_g_register = vidioc_g_register, + .vidioc_s_register = vidioc_s_register, +#endif +}; + +struct video_device cx25821_video_template5 = { + .name = "cx25821-video", + .fops = &video_fops, + .minor = -1, + .ioctl_ops = &video_ioctl_ops, + .tvnorms = CX25821_NORMS, + .current_norm = V4L2_STD_NTSC_M, +}; diff --git a/drivers/staging/cx25821/cx25821-video6.c b/drivers/staging/cx25821/cx25821-video6.c new file mode 100644 index 000000000000..3c41b49e2ea9 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-video6.c @@ -0,0 +1,450 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821-video.h" + +static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct cx25821_buffer *buf = + container_of(vb, struct cx25821_buffer, vb); + struct cx25821_buffer *prev; + struct cx25821_fh *fh = vq->priv_data; + struct cx25821_dev *dev = fh->dev; + struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH06]; + + /* add jump to stopper */ + buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); + buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); + buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ + + dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); + + if (!list_empty(&q->queued)) { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, + buf->vb.i); + + } else if (list_empty(&q->active)) { + list_add_tail(&buf->vb.queue, &q->active); + cx25821_start_video_dma(dev, q, buf, + &dev->sram_channels[SRAM_CH06]); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT); + dprintk(2, + "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", + buf, buf->vb.i, buf->count, q->count); + } else { + prev = + list_entry(q->active.prev, struct cx25821_buffer, vb.queue); + if (prev->vb.width == buf->vb.width + && prev->vb.height == buf->vb.height + && prev->fmt == buf->fmt) { + list_add_tail(&buf->vb.queue, &q->active); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); + + /* 64 bit bits 63-32 */ + prev->risc.jmp[2] = cpu_to_le32(0); + dprintk(2, + "[%p/%d] buffer_queue - append to active, buf->count=%d\n", + buf, buf->vb.i, buf->count); + + } else { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, + buf->vb.i); + } + } + + if (list_empty(&q->active)) { + dprintk(2, "active queue empty!\n"); + } +} + +static struct videobuf_queue_ops cx25821_video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +static int video_open(struct file *file) +{ + int minor = video_devdata(file)->minor; + struct cx25821_dev *h, *dev = NULL; + struct cx25821_fh *fh; + struct list_head *list; + enum v4l2_buf_type type = 0; + u32 pix_format; + + lock_kernel(); + list_for_each(list, &cx25821_devlist) { + h = list_entry(list, struct cx25821_dev, devlist); + + if (h->video_dev[SRAM_CH06] + && h->video_dev[SRAM_CH06]->minor == minor) { + dev = h; + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + } + } + + if (NULL == dev) { + unlock_kernel(); + return -ENODEV; + } + + printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); + + /* allocate + initialize per filehandle data */ + fh = kzalloc(sizeof(*fh), GFP_KERNEL); + if (NULL == fh) { + unlock_kernel(); + return -ENOMEM; + } + file->private_data = fh; + fh->dev = dev; + fh->type = type; + fh->width = 720; + + if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) + fh->height = 576; + else + fh->height = 480; + + dev->channel_opened = SRAM_CH06; + pix_format = + (dev->pixel_formats[dev->channel_opened] == + PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV; + fh->fmt = format_by_fourcc(pix_format); + + v4l2_prio_open(&dev->prio, &fh->prio); + + videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, + &dev->pci->dev, &dev->slock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_INTERLACED, + sizeof(struct cx25821_buffer), fh); + + dprintk(1, "post videobuf_queue_init()\n"); + unlock_kernel(); + + return 0; +} + +static ssize_t video_read(struct file *file, char __user * data, size_t count, + loff_t * ppos) +{ + struct cx25821_fh *fh = file->private_data; + + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + if (res_locked(fh->dev, RESOURCE_VIDEO6)) + return -EBUSY; + + return videobuf_read_one(&fh->vidq, data, count, ppos, + file->f_flags & O_NONBLOCK); + + default: + BUG(); + return 0; + } +} + +static unsigned int video_poll(struct file *file, + struct poll_table_struct *wait) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_buffer *buf; + + if (res_check(fh, RESOURCE_VIDEO6)) { + /* streaming capture */ + if (list_empty(&fh->vidq.stream)) + return POLLERR; + buf = list_entry(fh->vidq.stream.next, + struct cx25821_buffer, vb.stream); + } else { + /* read() capture */ + buf = (struct cx25821_buffer *)fh->vidq.read_buf; + if (NULL == buf) + return POLLERR; + } + + poll_wait(file, &buf->vb.done, wait); + if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) { + if (buf->vb.state == VIDEOBUF_DONE) { + struct cx25821_dev *dev = fh->dev; + + if (dev && dev->use_cif_resolution[SRAM_CH06]) { + u8 cam_id = *((char *)buf->vb.baddr + 3); + memcpy((char *)buf->vb.baddr, + (char *)buf->vb.baddr + (fh->width * 2), + (fh->width * 2)); + *((char *)buf->vb.baddr + 3) = cam_id; + } + } + + return POLLIN | POLLRDNORM; + } + + return 0; +} + +static int video_release(struct file *file) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_dev *dev = fh->dev; + + //stop the risc engine and fifo + cx_write(channel6->dma_ctl, 0); /* FIFO and RISC disable */ + + /* stop video capture */ + if (res_check(fh, RESOURCE_VIDEO6)) { + videobuf_queue_cancel(&fh->vidq); + res_free(dev, fh, RESOURCE_VIDEO6); + } + if (fh->vidq.read_buf) { + buffer_release(&fh->vidq, fh->vidq.read_buf); + kfree(fh->vidq.read_buf); + } + + videobuf_mmap_free(&fh->vidq); + + v4l2_prio_close(&dev->prio, &fh->prio); + file->private_data = NULL; + kfree(fh); + + return 0; +} + +static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + + if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) { + return -EINVAL; + } + + if (unlikely(i != fh->type)) { + return -EINVAL; + } + + if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO6)))) { + return -EBUSY; + } + + return videobuf_streamon(get_queue(fh)); +} + +static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + int err, res; + + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + if (i != fh->type) + return -EINVAL; + + res = get_resource(fh, RESOURCE_VIDEO6); + err = videobuf_streamoff(get_queue(fh)); + if (err < 0) + return err; + res_free(dev, fh, res); + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + int pix_format = 0; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + dprintk(2, "%s()\n", __func__); + err = vidioc_try_fmt_vid_cap(file, priv, f); + + if (0 != err) + return err; + + fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); + fh->vidq.field = f->fmt.pix.field; + + // check if width and height is valid based on set standard + if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) { + fh->width = f->fmt.pix.width; + } + + if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) { + fh->height = f->fmt.pix.height; + } + + if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) + pix_format = PIXEL_FRMT_411; + else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) + pix_format = PIXEL_FRMT_422; + else + return -EINVAL; + + cx25821_set_pixel_format(dev, SRAM_CH06, pix_format); + + // check if cif resolution + if (fh->width == 320 || fh->width == 352) { + dev->use_cif_resolution[SRAM_CH06] = 1; + } else { + dev->use_cif_resolution[SRAM_CH06] = 0; + } + dev->cif_width[SRAM_CH06] = fh->width; + medusa_set_resolution(dev, fh->width, SRAM_CH06); + + dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, + fh->height, fh->vidq.field); + cx25821_call_all(dev, video, s_fmt, f); + + return 0; +} + +static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + int ret_val = 0; + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + + ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); + + p->sequence = dev->vidq[SRAM_CH06].count; + + return ret_val; +} + +static int vidioc_log_status(struct file *file, void *priv) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + char name[32 + 2]; + + struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH06]; + u32 tmp = 0; + + snprintf(name, sizeof(name), "%s/2", dev->name); + printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", + dev->name); + cx25821_call_all(dev, core, log_status); + + tmp = cx_read(sram_ch->dma_ctl); + printk(KERN_INFO "Video input 6 is %s\n", + (tmp & 0x11) ? "streaming" : "stopped"); + printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", + dev->name); + return 0; +} + +static int vidioc_s_ctrl(struct file *file, void *priv, + struct v4l2_control *ctl) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + return cx25821_set_control(dev, ctl, SRAM_CH06); +} + +// exported stuff +static const struct v4l2_file_operations video_fops = { + .owner = THIS_MODULE, + .open = video_open, + .release = video_release, + .read = video_read, + .poll = video_poll, + .mmap = video_mmap, + .ioctl = video_ioctl2, +}; + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, +#ifdef TUNER_FLAG + .vidioc_s_std = vidioc_s_std, + .vidioc_querystd = vidioc_querystd, +#endif + .vidioc_cropcap = vidioc_cropcap, + .vidioc_s_crop = vidioc_s_crop, + .vidioc_g_crop = vidioc_g_crop, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_g_ctrl = vidioc_g_ctrl, + .vidioc_s_ctrl = vidioc_s_ctrl, + .vidioc_queryctrl = vidioc_queryctrl, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_log_status = vidioc_log_status, + .vidioc_g_priority = vidioc_g_priority, + .vidioc_s_priority = vidioc_s_priority, +#ifdef CONFIG_VIDEO_V4L1_COMPAT + .vidiocgmbuf = vidiocgmbuf, +#endif +#ifdef TUNER_FLAG + .vidioc_g_tuner = vidioc_g_tuner, + .vidioc_s_tuner = vidioc_s_tuner, + .vidioc_g_frequency = vidioc_g_frequency, + .vidioc_s_frequency = vidioc_s_frequency, +#endif +#ifdef CONFIG_VIDEO_ADV_DEBUG + .vidioc_g_register = vidioc_g_register, + .vidioc_s_register = vidioc_s_register, +#endif +}; + +struct video_device cx25821_video_template6 = { + .name = "cx25821-video", + .fops = &video_fops, + .minor = -1, + .ioctl_ops = &video_ioctl_ops, + .tvnorms = CX25821_NORMS, + .current_norm = V4L2_STD_NTSC_M, +}; diff --git a/drivers/staging/cx25821/cx25821-video7.c b/drivers/staging/cx25821/cx25821-video7.c new file mode 100644 index 000000000000..625c9b78a9cf --- /dev/null +++ b/drivers/staging/cx25821/cx25821-video7.c @@ -0,0 +1,449 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821-video.h" + +static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct cx25821_buffer *buf = + container_of(vb, struct cx25821_buffer, vb); + struct cx25821_buffer *prev; + struct cx25821_fh *fh = vq->priv_data; + struct cx25821_dev *dev = fh->dev; + struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH07]; + + /* add jump to stopper */ + buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); + buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); + buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ + + dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); + if (!list_empty(&q->queued)) { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, + buf->vb.i); + + } else if (list_empty(&q->active)) { + list_add_tail(&buf->vb.queue, &q->active); + cx25821_start_video_dma(dev, q, buf, + &dev->sram_channels[SRAM_CH07]); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT); + dprintk(2, + "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", + buf, buf->vb.i, buf->count, q->count); + } else { + prev = + list_entry(q->active.prev, struct cx25821_buffer, vb.queue); + if (prev->vb.width == buf->vb.width + && prev->vb.height == buf->vb.height + && prev->fmt == buf->fmt) { + list_add_tail(&buf->vb.queue, &q->active); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); + + /* 64 bit bits 63-32 */ + prev->risc.jmp[2] = cpu_to_le32(0); + dprintk(2, + "[%p/%d] buffer_queue - append to active, buf->count=%d\n", + buf, buf->vb.i, buf->count); + + } else { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, + buf->vb.i); + } + } + + if (list_empty(&q->active)) { + dprintk(2, "active queue empty!\n"); + } +} + +static struct videobuf_queue_ops cx25821_video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +static int video_open(struct file *file) +{ + int minor = video_devdata(file)->minor; + struct cx25821_dev *h, *dev = NULL; + struct cx25821_fh *fh; + struct list_head *list; + enum v4l2_buf_type type = 0; + u32 pix_format; + + lock_kernel(); + list_for_each(list, &cx25821_devlist) { + h = list_entry(list, struct cx25821_dev, devlist); + + if (h->video_dev[SRAM_CH07] + && h->video_dev[SRAM_CH07]->minor == minor) { + dev = h; + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + } + } + + if (NULL == dev) { + unlock_kernel(); + return -ENODEV; + } + + printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); + + /* allocate + initialize per filehandle data */ + fh = kzalloc(sizeof(*fh), GFP_KERNEL); + if (NULL == fh) { + unlock_kernel(); + return -ENOMEM; + } + file->private_data = fh; + fh->dev = dev; + fh->type = type; + fh->width = 720; + + if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) + fh->height = 576; + else + fh->height = 480; + + dev->channel_opened = SRAM_CH07; + pix_format = + (dev->pixel_formats[dev->channel_opened] == + PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV; + fh->fmt = format_by_fourcc(pix_format); + + v4l2_prio_open(&dev->prio, &fh->prio); + + videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, + &dev->pci->dev, &dev->slock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_INTERLACED, + sizeof(struct cx25821_buffer), fh); + + dprintk(1, "post videobuf_queue_init()\n"); + unlock_kernel(); + + return 0; +} + +static ssize_t video_read(struct file *file, char __user * data, size_t count, + loff_t * ppos) +{ + struct cx25821_fh *fh = file->private_data; + + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + if (res_locked(fh->dev, RESOURCE_VIDEO7)) + return -EBUSY; + + return videobuf_read_one(&fh->vidq, data, count, ppos, + file->f_flags & O_NONBLOCK); + + default: + BUG(); + return 0; + } +} + +static unsigned int video_poll(struct file *file, + struct poll_table_struct *wait) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_buffer *buf; + + if (res_check(fh, RESOURCE_VIDEO7)) { + /* streaming capture */ + if (list_empty(&fh->vidq.stream)) + return POLLERR; + buf = list_entry(fh->vidq.stream.next, + struct cx25821_buffer, vb.stream); + } else { + /* read() capture */ + buf = (struct cx25821_buffer *)fh->vidq.read_buf; + if (NULL == buf) + return POLLERR; + } + + poll_wait(file, &buf->vb.done, wait); + if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) { + if (buf->vb.state == VIDEOBUF_DONE) { + struct cx25821_dev *dev = fh->dev; + + if (dev && dev->use_cif_resolution[SRAM_CH07]) { + u8 cam_id = *((char *)buf->vb.baddr + 3); + memcpy((char *)buf->vb.baddr, + (char *)buf->vb.baddr + (fh->width * 2), + (fh->width * 2)); + *((char *)buf->vb.baddr + 3) = cam_id; + } + } + + return POLLIN | POLLRDNORM; + } + + return 0; +} + +static int video_release(struct file *file) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_dev *dev = fh->dev; + + //stop the risc engine and fifo + cx_write(channel7->dma_ctl, 0); /* FIFO and RISC disable */ + + /* stop video capture */ + if (res_check(fh, RESOURCE_VIDEO7)) { + videobuf_queue_cancel(&fh->vidq); + res_free(dev, fh, RESOURCE_VIDEO7); + } + + if (fh->vidq.read_buf) { + buffer_release(&fh->vidq, fh->vidq.read_buf); + kfree(fh->vidq.read_buf); + } + + videobuf_mmap_free(&fh->vidq); + + v4l2_prio_close(&dev->prio, &fh->prio); + file->private_data = NULL; + kfree(fh); + + return 0; +} + +static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + + if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) { + return -EINVAL; + } + + if (unlikely(i != fh->type)) { + return -EINVAL; + } + + if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO7)))) { + return -EBUSY; + } + + return videobuf_streamon(get_queue(fh)); +} + +static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + int err, res; + + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + if (i != fh->type) + return -EINVAL; + + res = get_resource(fh, RESOURCE_VIDEO7); + err = videobuf_streamoff(get_queue(fh)); + if (err < 0) + return err; + res_free(dev, fh, res); + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + int pix_format = 0; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + dprintk(2, "%s()\n", __func__); + err = vidioc_try_fmt_vid_cap(file, priv, f); + + if (0 != err) + return err; + + fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); + fh->vidq.field = f->fmt.pix.field; + + // check if width and height is valid based on set standard + if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) { + fh->width = f->fmt.pix.width; + } + + if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) { + fh->height = f->fmt.pix.height; + } + + if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) + pix_format = PIXEL_FRMT_411; + else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) + pix_format = PIXEL_FRMT_422; + else + return -EINVAL; + + cx25821_set_pixel_format(dev, SRAM_CH07, pix_format); + + // check if cif resolution + if (fh->width == 320 || fh->width == 352) { + dev->use_cif_resolution[SRAM_CH07] = 1; + } else { + dev->use_cif_resolution[SRAM_CH07] = 0; + } + dev->cif_width[SRAM_CH07] = fh->width; + medusa_set_resolution(dev, fh->width, SRAM_CH07); + + dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, + fh->height, fh->vidq.field); + cx25821_call_all(dev, video, s_fmt, f); + + return 0; +} + +static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + int ret_val = 0; + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + + ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); + + p->sequence = dev->vidq[SRAM_CH07].count; + + return ret_val; +} +static int vidioc_log_status(struct file *file, void *priv) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + char name[32 + 2]; + + struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH07]; + u32 tmp = 0; + + snprintf(name, sizeof(name), "%s/2", dev->name); + printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", + dev->name); + cx25821_call_all(dev, core, log_status); + + tmp = cx_read(sram_ch->dma_ctl); + printk(KERN_INFO "Video input 7 is %s\n", + (tmp & 0x11) ? "streaming" : "stopped"); + printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", + dev->name); + return 0; +} + +static int vidioc_s_ctrl(struct file *file, void *priv, + struct v4l2_control *ctl) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + return cx25821_set_control(dev, ctl, SRAM_CH07); +} + +// exported stuff +static const struct v4l2_file_operations video_fops = { + .owner = THIS_MODULE, + .open = video_open, + .release = video_release, + .read = video_read, + .poll = video_poll, + .mmap = video_mmap, + .ioctl = video_ioctl2, +}; + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, +#ifdef TUNER_FLAG + .vidioc_s_std = vidioc_s_std, + .vidioc_querystd = vidioc_querystd, +#endif + .vidioc_cropcap = vidioc_cropcap, + .vidioc_s_crop = vidioc_s_crop, + .vidioc_g_crop = vidioc_g_crop, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_g_ctrl = vidioc_g_ctrl, + .vidioc_s_ctrl = vidioc_s_ctrl, + .vidioc_queryctrl = vidioc_queryctrl, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_log_status = vidioc_log_status, + .vidioc_g_priority = vidioc_g_priority, + .vidioc_s_priority = vidioc_s_priority, +#ifdef CONFIG_VIDEO_V4L1_COMPAT + .vidiocgmbuf = vidiocgmbuf, +#endif +#ifdef TUNER_FLAG + .vidioc_g_tuner = vidioc_g_tuner, + .vidioc_s_tuner = vidioc_s_tuner, + .vidioc_g_frequency = vidioc_g_frequency, + .vidioc_s_frequency = vidioc_s_frequency, +#endif +#ifdef CONFIG_VIDEO_ADV_DEBUG + .vidioc_g_register = vidioc_g_register, + .vidioc_s_register = vidioc_s_register, +#endif +}; + +struct video_device cx25821_video_template7 = { + .name = "cx25821-video", + .fops = &video_fops, + .minor = -1, + .ioctl_ops = &video_ioctl_ops, + .tvnorms = CX25821_NORMS, + .current_norm = V4L2_STD_NTSC_M, +}; diff --git a/drivers/staging/cx25821/cx25821-videoioctl.c b/drivers/staging/cx25821/cx25821-videoioctl.c new file mode 100644 index 000000000000..2a312ce78c63 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-videoioctl.c @@ -0,0 +1,496 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821-video.h" + +static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct cx25821_buffer *buf = + container_of(vb, struct cx25821_buffer, vb); + struct cx25821_buffer *prev; + struct cx25821_fh *fh = vq->priv_data; + struct cx25821_dev *dev = fh->dev; + struct cx25821_dmaqueue *q = &dev->vidq[VIDEO_IOCTL_CH]; + + /* add jump to stopper */ + buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); + buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); + buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ + + dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); + + if (!list_empty(&q->queued)) { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, + buf->vb.i); + + } else if (list_empty(&q->active)) { + list_add_tail(&buf->vb.queue, &q->active); + cx25821_start_video_dma(dev, q, buf, + &dev->sram_channels[VIDEO_IOCTL_CH]); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT); + dprintk(2, + "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", + buf, buf->vb.i, buf->count, q->count); + } else { + prev = + list_entry(q->active.prev, struct cx25821_buffer, vb.queue); + if (prev->vb.width == buf->vb.width + && prev->vb.height == buf->vb.height + && prev->fmt == buf->fmt) { + list_add_tail(&buf->vb.queue, &q->active); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); + + /* 64 bit bits 63-32 */ + prev->risc.jmp[2] = cpu_to_le32(0); + dprintk(2, + "[%p/%d] buffer_queue - append to active, buf->count=%d\n", + buf, buf->vb.i, buf->count); + + } else { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, + buf->vb.i); + } + } + + if (list_empty(&q->active)) { + dprintk(2, "active queue empty!\n"); + } +} + +static struct videobuf_queue_ops cx25821_video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +static int video_open(struct file *file) +{ + int minor = video_devdata(file)->minor; + struct cx25821_dev *h, *dev = NULL; + struct cx25821_fh *fh; + struct list_head *list; + enum v4l2_buf_type type = 0; + u32 pix_format; + + lock_kernel(); + list_for_each(list, &cx25821_devlist) { + h = list_entry(list, struct cx25821_dev, devlist); + + if (h->ioctl_dev && h->ioctl_dev->minor == minor) { + dev = h; + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + } + } + + if (NULL == dev) { + unlock_kernel(); + return -ENODEV; + } + + printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); + + /* allocate + initialize per filehandle data */ + fh = kzalloc(sizeof(*fh), GFP_KERNEL); + if (NULL == fh) { + unlock_kernel(); + return -ENOMEM; + } + + file->private_data = fh; + fh->dev = dev; + fh->type = type; + fh->width = 720; + + if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) + fh->height = 576; + else + fh->height = 480; + + dev->channel_opened = VIDEO_IOCTL_CH; + pix_format = V4L2_PIX_FMT_YUYV; + fh->fmt = format_by_fourcc(pix_format); + + v4l2_prio_open(&dev->prio, &fh->prio); + + videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, + &dev->pci->dev, &dev->slock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_INTERLACED, + sizeof(struct cx25821_buffer), fh); + + dprintk(1, "post videobuf_queue_init()\n"); + unlock_kernel(); + + return 0; +} + +static ssize_t video_read(struct file *file, char __user * data, size_t count, + loff_t * ppos) +{ + struct cx25821_fh *fh = file->private_data; + + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + if (res_locked(fh->dev, RESOURCE_VIDEO_IOCTL)) + return -EBUSY; + + return videobuf_read_one(&fh->vidq, data, count, ppos, + file->f_flags & O_NONBLOCK); + + default: + BUG(); + return 0; + } +} + +static unsigned int video_poll(struct file *file, + struct poll_table_struct *wait) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_buffer *buf; + + if (res_check(fh, RESOURCE_VIDEO_IOCTL)) { + /* streaming capture */ + if (list_empty(&fh->vidq.stream)) + return POLLERR; + buf = list_entry(fh->vidq.stream.next, + struct cx25821_buffer, vb.stream); + } else { + /* read() capture */ + buf = (struct cx25821_buffer *)fh->vidq.read_buf; + if (NULL == buf) + return POLLERR; + } + + poll_wait(file, &buf->vb.done, wait); + if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) + return POLLIN | POLLRDNORM; + + return 0; +} + +static int video_release(struct file *file) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_dev *dev = fh->dev; + + /* stop video capture */ + if (res_check(fh, RESOURCE_VIDEO_IOCTL)) { + videobuf_queue_cancel(&fh->vidq); + res_free(dev, fh, RESOURCE_VIDEO_IOCTL); + } + + if (fh->vidq.read_buf) { + buffer_release(&fh->vidq, fh->vidq.read_buf); + kfree(fh->vidq.read_buf); + } + + videobuf_mmap_free(&fh->vidq); + + v4l2_prio_close(&dev->prio, &fh->prio); + + file->private_data = NULL; + kfree(fh); + + return 0; +} + +static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + + if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) { + return -EINVAL; + } + + if (unlikely(i != fh->type)) { + return -EINVAL; + } + + if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO_IOCTL)))) { + return -EBUSY; + } + + return videobuf_streamon(get_queue(fh)); +} + +static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + int err, res; + + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + if (i != fh->type) + return -EINVAL; + + res = get_resource(fh, RESOURCE_VIDEO_IOCTL); + err = videobuf_streamoff(get_queue(fh)); + if (err < 0) + return err; + res_free(dev, fh, res); + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + dprintk(2, "%s()\n", __func__); + err = vidioc_try_fmt_vid_cap(file, priv, f); + + if (0 != err) + return err; + fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); + fh->width = f->fmt.pix.width; + fh->height = f->fmt.pix.height; + fh->vidq.field = f->fmt.pix.field; + dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, + fh->height, fh->vidq.field); + cx25821_call_all(dev, video, s_fmt, f); + return 0; +} + +static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct cx25821_fh *fh = priv; + return videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); +} + +static long video_ioctl_set(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_dev *dev = fh->dev; + struct downstream_user_struct *data_from_user; + int command; + int width = 720; + int selected_channel = 0, pix_format = 0, i = 0; + int cif_enable = 0, cif_width = 0; + u32 value = 0; + + data_from_user = (struct downstream_user_struct *)arg; + + if (!data_from_user) { + printk("cx25821 in %s(): User data is INVALID. Returning.\n", + __func__); + return 0; + } + + command = data_from_user->command; + + if (command != SET_VIDEO_STD && command != SET_PIXEL_FORMAT + && command != ENABLE_CIF_RESOLUTION && command != REG_READ + && command != REG_WRITE && command != MEDUSA_READ + && command != MEDUSA_WRITE) { + return 0; + } + + switch (command) { + case SET_VIDEO_STD: + dev->tvnorm = + !strcmp(data_from_user->vid_stdname, + "PAL") ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M; + medusa_set_videostandard(dev); + break; + + case SET_PIXEL_FORMAT: + selected_channel = data_from_user->decoder_select; + pix_format = data_from_user->pixel_format; + + if (!(selected_channel <= 7 && selected_channel >= 0)) { + selected_channel -= 4; + selected_channel = selected_channel % 8; + } + + if (selected_channel >= 0) + cx25821_set_pixel_format(dev, selected_channel, + pix_format); + + break; + + case ENABLE_CIF_RESOLUTION: + selected_channel = data_from_user->decoder_select; + cif_enable = data_from_user->cif_resolution_enable; + cif_width = data_from_user->cif_width; + + if (cif_enable) { + if (dev->tvnorm & V4L2_STD_PAL_BG + || dev->tvnorm & V4L2_STD_PAL_DK) + width = 352; + else + width = (cif_width == 320 + || cif_width == 352) ? cif_width : 320; + } + + if (!(selected_channel <= 7 && selected_channel >= 0)) { + selected_channel -= 4; + selected_channel = selected_channel % 8; + } + + if (selected_channel <= 7 && selected_channel >= 0) { + dev->use_cif_resolution[selected_channel] = cif_enable; + dev->cif_width[selected_channel] = width; + } else { + for (i = 0; i < VID_CHANNEL_NUM; i++) { + dev->use_cif_resolution[i] = cif_enable; + dev->cif_width[i] = width; + } + } + + medusa_set_resolution(dev, width, selected_channel); + break; + case REG_READ: + data_from_user->reg_data = cx_read(data_from_user->reg_address); + break; + case REG_WRITE: + cx_write(data_from_user->reg_address, data_from_user->reg_data); + break; + case MEDUSA_READ: + value = + cx25821_i2c_read(&dev->i2c_bus[0], + (u16) data_from_user->reg_address, + &data_from_user->reg_data); + break; + case MEDUSA_WRITE: + cx25821_i2c_write(&dev->i2c_bus[0], + (u16) data_from_user->reg_address, + data_from_user->reg_data); + break; + } + + return 0; +} + +static int vidioc_log_status(struct file *file, void *priv) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + char name[32 + 2]; + + snprintf(name, sizeof(name), "%s/2", dev->name); + printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", + dev->name); + cx25821_call_all(dev, core, log_status); + printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", + dev->name); + return 0; +} + +static int vidioc_s_ctrl(struct file *file, void *priv, + struct v4l2_control *ctl) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + return 0; +} + +// exported stuff +static const struct v4l2_file_operations video_fops = { + .owner = THIS_MODULE, + .open = video_open, + .release = video_release, + .read = video_read, + .poll = video_poll, + .mmap = video_mmap, + .ioctl = video_ioctl_set, +}; + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, +#ifdef TUNER_FLAG + .vidioc_s_std = vidioc_s_std, + .vidioc_querystd = vidioc_querystd, +#endif + .vidioc_cropcap = vidioc_cropcap, + .vidioc_s_crop = vidioc_s_crop, + .vidioc_g_crop = vidioc_g_crop, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_g_ctrl = vidioc_g_ctrl, + .vidioc_s_ctrl = vidioc_s_ctrl, + .vidioc_queryctrl = vidioc_queryctrl, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_log_status = vidioc_log_status, + .vidioc_g_priority = vidioc_g_priority, + .vidioc_s_priority = vidioc_s_priority, +#ifdef CONFIG_VIDEO_V4L1_COMPAT + .vidiocgmbuf = vidiocgmbuf, +#endif +#ifdef TUNER_FLAG + .vidioc_g_tuner = vidioc_g_tuner, + .vidioc_s_tuner = vidioc_s_tuner, + .vidioc_g_frequency = vidioc_g_frequency, + .vidioc_s_frequency = vidioc_s_frequency, +#endif +#ifdef CONFIG_VIDEO_ADV_DEBUG + .vidioc_g_register = vidioc_g_register, + .vidioc_s_register = vidioc_s_register, +#endif +}; + +struct video_device cx25821_videoioctl_template = { + .name = "cx25821-videoioctl", + .fops = &video_fops, + .minor = -1, + .ioctl_ops = &video_ioctl_ops, + .tvnorms = CX25821_NORMS, + .current_norm = V4L2_STD_NTSC_M, +}; diff --git a/drivers/staging/cx25821/cx25821-vidups10.c b/drivers/staging/cx25821/cx25821-vidups10.c new file mode 100644 index 000000000000..77b63b060405 --- /dev/null +++ b/drivers/staging/cx25821/cx25821-vidups10.c @@ -0,0 +1,435 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821-video.h" + +static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct cx25821_buffer *buf = + container_of(vb, struct cx25821_buffer, vb); + struct cx25821_buffer *prev; + struct cx25821_fh *fh = vq->priv_data; + struct cx25821_dev *dev = fh->dev; + struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH10]; + + /* add jump to stopper */ + buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); + buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); + buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ + + dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); + + if (!list_empty(&q->queued)) { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, + buf->vb.i); + + } else if (list_empty(&q->active)) { + list_add_tail(&buf->vb.queue, &q->active); + cx25821_start_video_dma(dev, q, buf, + &dev->sram_channels[SRAM_CH10]); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT); + dprintk(2, + "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", + buf, buf->vb.i, buf->count, q->count); + } else { + prev = + list_entry(q->active.prev, struct cx25821_buffer, vb.queue); + if (prev->vb.width == buf->vb.width + && prev->vb.height == buf->vb.height + && prev->fmt == buf->fmt) { + list_add_tail(&buf->vb.queue, &q->active); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); + + /* 64 bit bits 63-32 */ + prev->risc.jmp[2] = cpu_to_le32(0); + dprintk(2, + "[%p/%d] buffer_queue - append to active, buf->count=%d\n", + buf, buf->vb.i, buf->count); + + } else { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, + buf->vb.i); + } + } + + if (list_empty(&q->active)) { + dprintk(2, "active queue empty!\n"); + } +} + +static struct videobuf_queue_ops cx25821_video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +static int video_open(struct file *file) +{ + int minor = video_devdata(file)->minor; + struct cx25821_dev *h, *dev = NULL; + struct cx25821_fh *fh; + struct list_head *list; + enum v4l2_buf_type type = 0; + + lock_kernel(); + list_for_each(list, &cx25821_devlist) { + h = list_entry(list, struct cx25821_dev, devlist); + + if (h->video_dev[SRAM_CH10] + && h->video_dev[SRAM_CH10]->minor == minor) { + dev = h; + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + } + } + + if (NULL == dev) { + unlock_kernel(); + return -ENODEV; + } + + printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); + + /* allocate + initialize per filehandle data */ + fh = kzalloc(sizeof(*fh), GFP_KERNEL); + if (NULL == fh) { + unlock_kernel(); + return -ENOMEM; + } + + file->private_data = fh; + fh->dev = dev; + fh->type = type; + fh->width = 720; + + if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) + fh->height = 576; + else + fh->height = 480; + + dev->channel_opened = 9; + fh->fmt = format_by_fourcc(V4L2_PIX_FMT_YUYV); + + v4l2_prio_open(&dev->prio, &fh->prio); + + videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, + &dev->pci->dev, &dev->slock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_INTERLACED, + sizeof(struct cx25821_buffer), fh); + + dprintk(1, "post videobuf_queue_init()\n"); + unlock_kernel(); + + return 0; +} + +static ssize_t video_read(struct file *file, char __user * data, size_t count, + loff_t * ppos) +{ + struct cx25821_fh *fh = file->private_data; + + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + if (res_locked(fh->dev, RESOURCE_VIDEO10)) + return -EBUSY; + + return videobuf_read_one(&fh->vidq, data, count, ppos, + file->f_flags & O_NONBLOCK); + + default: + BUG(); + return 0; + } +} + +static unsigned int video_poll(struct file *file, + struct poll_table_struct *wait) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_buffer *buf; + + if (res_check(fh, RESOURCE_VIDEO10)) { + /* streaming capture */ + if (list_empty(&fh->vidq.stream)) + return POLLERR; + buf = list_entry(fh->vidq.stream.next, + struct cx25821_buffer, vb.stream); + } else { + /* read() capture */ + buf = (struct cx25821_buffer *)fh->vidq.read_buf; + if (NULL == buf) + return POLLERR; + } + + poll_wait(file, &buf->vb.done, wait); + if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) + return POLLIN | POLLRDNORM; + return 0; +} + +static int video_release(struct file *file) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_dev *dev = fh->dev; + + //stop the risc engine and fifo + //cx_write(channel10->dma_ctl, 0); + + /* stop video capture */ + if (res_check(fh, RESOURCE_VIDEO10)) { + videobuf_queue_cancel(&fh->vidq); + res_free(dev, fh, RESOURCE_VIDEO10); + } + + if (fh->vidq.read_buf) { + buffer_release(&fh->vidq, fh->vidq.read_buf); + kfree(fh->vidq.read_buf); + } + + videobuf_mmap_free(&fh->vidq); + + v4l2_prio_close(&dev->prio, &fh->prio); + + file->private_data = NULL; + kfree(fh); + + return 0; +} + +static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + + if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) { + return -EINVAL; + } + + if (unlikely(i != fh->type)) { + return -EINVAL; + } + + if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO10)))) { + return -EBUSY; + } + + return videobuf_streamon(get_queue(fh)); +} + +static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + int err, res; + + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + if (i != fh->type) + return -EINVAL; + + res = get_resource(fh, RESOURCE_VIDEO10); + err = videobuf_streamoff(get_queue(fh)); + if (err < 0) + return err; + res_free(dev, fh, res); + return 0; +} + +static long video_ioctl_upstream10(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_dev *dev = fh->dev; + int command = 0; + struct upstream_user_struct *data_from_user; + + data_from_user = (struct upstream_user_struct *)arg; + + if (!data_from_user) { + printk + ("cx25821 in %s(): Upstream data is INVALID. Returning.\n", + __func__); + return 0; + } + + command = data_from_user->command; + + if (command != UPSTREAM_START_VIDEO && command != UPSTREAM_STOP_VIDEO) { + return 0; + } + + dev->input_filename_ch2 = data_from_user->input_filename; + dev->input_audiofilename = data_from_user->input_filename; + dev->vid_stdname_ch2 = data_from_user->vid_stdname; + dev->pixel_format_ch2 = data_from_user->pixel_format; + dev->channel_select_ch2 = data_from_user->channel_select; + dev->command_ch2 = data_from_user->command; + + switch (command) { + case UPSTREAM_START_VIDEO: + cx25821_start_upstream_video_ch2(dev, data_from_user); + break; + + case UPSTREAM_STOP_VIDEO: + cx25821_stop_upstream_video_ch2(dev); + break; + } + + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + dprintk(2, "%s()\n", __func__); + err = vidioc_try_fmt_vid_cap(file, priv, f); + + if (0 != err) + return err; + fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); + fh->width = f->fmt.pix.width; + fh->height = f->fmt.pix.height; + fh->vidq.field = f->fmt.pix.field; + dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, + fh->height, fh->vidq.field); + cx25821_call_all(dev, video, s_fmt, f); + return 0; +} + +static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct cx25821_fh *fh = priv; + return videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); +} + +static int vidioc_log_status(struct file *file, void *priv) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + char name[32 + 2]; + + snprintf(name, sizeof(name), "%s/2", dev->name); + printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", + dev->name); + cx25821_call_all(dev, core, log_status); + printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", + dev->name); + return 0; +} + +static int vidioc_s_ctrl(struct file *file, void *priv, + struct v4l2_control *ctl) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + return 0; +} + +//exported stuff +static const struct v4l2_file_operations video_fops = { + .owner = THIS_MODULE, + .open = video_open, + .release = video_release, + .read = video_read, + .poll = video_poll, + .mmap = video_mmap, + .ioctl = video_ioctl_upstream10, +}; + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, +#ifdef TUNER_FLAG + .vidioc_s_std = vidioc_s_std, + .vidioc_querystd = vidioc_querystd, +#endif + .vidioc_cropcap = vidioc_cropcap, + .vidioc_s_crop = vidioc_s_crop, + .vidioc_g_crop = vidioc_g_crop, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_g_ctrl = vidioc_g_ctrl, + .vidioc_s_ctrl = vidioc_s_ctrl, + .vidioc_queryctrl = vidioc_queryctrl, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_log_status = vidioc_log_status, + .vidioc_g_priority = vidioc_g_priority, + .vidioc_s_priority = vidioc_s_priority, +#ifdef CONFIG_VIDEO_V4L1_COMPAT + .vidiocgmbuf = vidiocgmbuf, +#endif +#ifdef TUNER_FLAG + .vidioc_g_tuner = vidioc_g_tuner, + .vidioc_s_tuner = vidioc_s_tuner, + .vidioc_g_frequency = vidioc_g_frequency, + .vidioc_s_frequency = vidioc_s_frequency, +#endif +#ifdef CONFIG_VIDEO_ADV_DEBUG + .vidioc_g_register = vidioc_g_register, + .vidioc_s_register = vidioc_s_register, +#endif +}; + +struct video_device cx25821_video_template10 = { + .name = "cx25821-upstream10", + .fops = &video_fops, + .minor = -1, + .ioctl_ops = &video_ioctl_ops, + .tvnorms = CX25821_NORMS, + .current_norm = V4L2_STD_NTSC_M, +}; diff --git a/drivers/staging/cx25821/cx25821-vidups9.c b/drivers/staging/cx25821/cx25821-vidups9.c new file mode 100644 index 000000000000..75c8c1eed2da --- /dev/null +++ b/drivers/staging/cx25821/cx25821-vidups9.c @@ -0,0 +1,433 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "cx25821-video.h" + +static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct cx25821_buffer *buf = + container_of(vb, struct cx25821_buffer, vb); + struct cx25821_buffer *prev; + struct cx25821_fh *fh = vq->priv_data; + struct cx25821_dev *dev = fh->dev; + struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH09]; + + /* add jump to stopper */ + buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); + buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); + buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ + + dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); + + if (!list_empty(&q->queued)) { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, + buf->vb.i); + + } else if (list_empty(&q->active)) { + list_add_tail(&buf->vb.queue, &q->active); + cx25821_start_video_dma(dev, q, buf, + &dev->sram_channels[SRAM_CH09]); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT); + dprintk(2, + "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", + buf, buf->vb.i, buf->count, q->count); + } else { + prev = + list_entry(q->active.prev, struct cx25821_buffer, vb.queue); + if (prev->vb.width == buf->vb.width + && prev->vb.height == buf->vb.height + && prev->fmt == buf->fmt) { + list_add_tail(&buf->vb.queue, &q->active); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->count = q->count++; + prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); + + /* 64 bit bits 63-32 */ + prev->risc.jmp[2] = cpu_to_le32(0); + dprintk(2, + "[%p/%d] buffer_queue - append to active, buf->count=%d\n", + buf, buf->vb.i, buf->count); + + } else { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, + buf->vb.i); + } + } + + if (list_empty(&q->active)) { + dprintk(2, "active queue empty!\n"); + } +} + +static struct videobuf_queue_ops cx25821_video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +static int video_open(struct file *file) +{ + int minor = video_devdata(file)->minor; + struct cx25821_dev *h, *dev = NULL; + struct cx25821_fh *fh; + struct list_head *list; + enum v4l2_buf_type type = 0; + + lock_kernel(); + list_for_each(list, &cx25821_devlist) { + h = list_entry(list, struct cx25821_dev, devlist); + + if (h->video_dev[SRAM_CH09] + && h->video_dev[SRAM_CH09]->minor == minor) { + dev = h; + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + } + } + + if (NULL == dev) { + unlock_kernel(); + return -ENODEV; + } + + printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); + + /* allocate + initialize per filehandle data */ + fh = kzalloc(sizeof(*fh), GFP_KERNEL); + if (NULL == fh) { + unlock_kernel(); + return -ENOMEM; + } + + file->private_data = fh; + fh->dev = dev; + fh->type = type; + fh->width = 720; + + if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) + fh->height = 576; + else + fh->height = 480; + + dev->channel_opened = 8; + fh->fmt = format_by_fourcc(V4L2_PIX_FMT_YUYV); + + v4l2_prio_open(&dev->prio, &fh->prio); + + videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, + &dev->pci->dev, &dev->slock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_INTERLACED, + sizeof(struct cx25821_buffer), fh); + + dprintk(1, "post videobuf_queue_init()\n"); + unlock_kernel(); + + return 0; +} + +static ssize_t video_read(struct file *file, char __user * data, size_t count, + loff_t * ppos) +{ + struct cx25821_fh *fh = file->private_data; + + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + if (res_locked(fh->dev, RESOURCE_VIDEO9)) + return -EBUSY; + + return videobuf_read_one(&fh->vidq, data, count, ppos, + file->f_flags & O_NONBLOCK); + + default: + BUG(); + return 0; + } +} + +static unsigned int video_poll(struct file *file, + struct poll_table_struct *wait) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_buffer *buf; + + if (res_check(fh, RESOURCE_VIDEO9)) { + /* streaming capture */ + if (list_empty(&fh->vidq.stream)) + return POLLERR; + buf = list_entry(fh->vidq.stream.next, + struct cx25821_buffer, vb.stream); + } else { + /* read() capture */ + buf = (struct cx25821_buffer *)fh->vidq.read_buf; + if (NULL == buf) + return POLLERR; + } + + poll_wait(file, &buf->vb.done, wait); + if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) + return POLLIN | POLLRDNORM; + return 0; +} + +static int video_release(struct file *file) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_dev *dev = fh->dev; + + //stop the risc engine and fifo + //cx_write(channel9->dma_ctl, 0); + + /* stop video capture */ + if (res_check(fh, RESOURCE_VIDEO9)) { + videobuf_queue_cancel(&fh->vidq); + res_free(dev, fh, RESOURCE_VIDEO9); + } + + if (fh->vidq.read_buf) { + buffer_release(&fh->vidq, fh->vidq.read_buf); + kfree(fh->vidq.read_buf); + } + + videobuf_mmap_free(&fh->vidq); + + v4l2_prio_close(&dev->prio, &fh->prio); + + file->private_data = NULL; + kfree(fh); + + return 0; +} + +static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + + if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) { + return -EINVAL; + } + + if (unlikely(i != fh->type)) { + return -EINVAL; + } + + if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO9)))) { + return -EBUSY; + } + + return videobuf_streamon(get_queue(fh)); +} + +static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = fh->dev; + int err, res; + + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + if (i != fh->type) + return -EINVAL; + + res = get_resource(fh, RESOURCE_VIDEO9); + err = videobuf_streamoff(get_queue(fh)); + if (err < 0) + return err; + res_free(dev, fh, res); + return 0; +} + +static long video_ioctl_upstream9(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct cx25821_fh *fh = file->private_data; + struct cx25821_dev *dev = fh->dev; + int command = 0; + struct upstream_user_struct *data_from_user; + + data_from_user = (struct upstream_user_struct *)arg; + + if (!data_from_user) { + printk + ("cx25821 in %s(): Upstream data is INVALID. Returning.\n", + __func__); + return 0; + } + + command = data_from_user->command; + + if (command != UPSTREAM_START_VIDEO && command != UPSTREAM_STOP_VIDEO) { + return 0; + } + + dev->input_filename = data_from_user->input_filename; + dev->input_audiofilename = data_from_user->input_filename; + dev->vid_stdname = data_from_user->vid_stdname; + dev->pixel_format = data_from_user->pixel_format; + dev->channel_select = data_from_user->channel_select; + dev->command = data_from_user->command; + + switch (command) { + case UPSTREAM_START_VIDEO: + cx25821_start_upstream_video_ch1(dev, data_from_user); + break; + + case UPSTREAM_STOP_VIDEO: + cx25821_stop_upstream_video_ch1(dev); + break; + } + + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct cx25821_fh *fh = priv; + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + int err; + + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + dprintk(2, "%s()\n", __func__); + err = vidioc_try_fmt_vid_cap(file, priv, f); + + if (0 != err) + return err; + fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); + fh->width = f->fmt.pix.width; + fh->height = f->fmt.pix.height; + fh->vidq.field = f->fmt.pix.field; + dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, + fh->height, fh->vidq.field); + cx25821_call_all(dev, video, s_fmt, f); + return 0; +} + +static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct cx25821_fh *fh = priv; + return videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); +} +static int vidioc_log_status(struct file *file, void *priv) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + char name[32 + 2]; + + snprintf(name, sizeof(name), "%s/2", dev->name); + printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", + dev->name); + cx25821_call_all(dev, core, log_status); + printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", + dev->name); + return 0; +} + +static int vidioc_s_ctrl(struct file *file, void *priv, + struct v4l2_control *ctl) +{ + struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; + struct cx25821_fh *fh = priv; + int err; + if (fh) { + err = v4l2_prio_check(&dev->prio, &fh->prio); + if (0 != err) + return err; + } + + return 0; +} + +// exported stuff +static const struct v4l2_file_operations video_fops = { + .owner = THIS_MODULE, + .open = video_open, + .release = video_release, + .read = video_read, + .poll = video_poll, + .mmap = video_mmap, + .ioctl = video_ioctl_upstream9, +}; + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, +#ifdef TUNER_FLAG + .vidioc_s_std = vidioc_s_std, + .vidioc_querystd = vidioc_querystd, +#endif + .vidioc_cropcap = vidioc_cropcap, + .vidioc_s_crop = vidioc_s_crop, + .vidioc_g_crop = vidioc_g_crop, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_g_ctrl = vidioc_g_ctrl, + .vidioc_s_ctrl = vidioc_s_ctrl, + .vidioc_queryctrl = vidioc_queryctrl, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_log_status = vidioc_log_status, + .vidioc_g_priority = vidioc_g_priority, + .vidioc_s_priority = vidioc_s_priority, +#ifdef CONFIG_VIDEO_V4L1_COMPAT + .vidiocgmbuf = vidiocgmbuf, +#endif +#ifdef TUNER_FLAG + .vidioc_g_tuner = vidioc_g_tuner, + .vidioc_s_tuner = vidioc_s_tuner, + .vidioc_g_frequency = vidioc_g_frequency, + .vidioc_s_frequency = vidioc_s_frequency, +#endif +#ifdef CONFIG_VIDEO_ADV_DEBUG + .vidioc_g_register = vidioc_g_register, + .vidioc_s_register = vidioc_s_register, +#endif +}; + +struct video_device cx25821_video_template9 = { + .name = "cx25821-upstream9", + .fops = &video_fops, + .minor = -1, + .ioctl_ops = &video_ioctl_ops, + .tvnorms = CX25821_NORMS, + .current_norm = V4L2_STD_NTSC_M, +}; diff --git a/drivers/staging/cx25821/cx25821.h b/drivers/staging/cx25821/cx25821.h new file mode 100644 index 000000000000..cf2286d83b6a --- /dev/null +++ b/drivers/staging/cx25821/cx25821.h @@ -0,0 +1,602 @@ +/* + * Driver for the Conexant CX25821 PCIe bridge + * + * Copyright (C) 2009 Conexant Systems Inc. + * Authors , + * Based on Steven Toth cx23885 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef CX25821_H_ +#define CX25821_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "btcx-risc.h" +#include "cx25821-reg.h" +#include "cx25821-medusa-reg.h" +#include "cx25821-sram.h" +#include "cx25821-audio.h" +#include "media/cx2341x.h" + +#include +#include + +#define CX25821_VERSION_CODE KERNEL_VERSION(0, 0, 106) + +#define UNSET (-1U) +#define NO_SYNC_LINE (-1U) + +#define CX25821_MAXBOARDS 2 + +#define TRUE 1 +#define FALSE 0 +#define LINE_SIZE_D1 1440 + +// Number of decoders and encoders +#define MAX_DECODERS 8 +#define MAX_ENCODERS 2 +#define QUAD_DECODERS 4 +#define MAX_CAMERAS 16 + +/* Max number of inputs by card */ +#define MAX_CX25821_INPUT 8 +#define INPUT(nr) (&cx25821_boards[dev->board].input[nr]) +#define RESOURCE_VIDEO0 1 +#define RESOURCE_VIDEO1 2 +#define RESOURCE_VIDEO2 4 +#define RESOURCE_VIDEO3 8 +#define RESOURCE_VIDEO4 16 +#define RESOURCE_VIDEO5 32 +#define RESOURCE_VIDEO6 64 +#define RESOURCE_VIDEO7 128 +#define RESOURCE_VIDEO8 256 +#define RESOURCE_VIDEO9 512 +#define RESOURCE_VIDEO10 1024 +#define RESOURCE_VIDEO11 2048 +#define RESOURCE_VIDEO_IOCTL 4096 + +#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */ + +#define UNKNOWN_BOARD 0 +#define CX25821_BOARD 1 + +/* Currently supported by the driver */ +#define CX25821_NORMS (\ + V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_M_KR | \ + V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \ + V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_H | \ + V4L2_STD_PAL_Nc ) + +#define CX25821_BOARD_CONEXANT_ATHENA10 1 +#define MAX_VID_CHANNEL_NUM 12 +#define VID_CHANNEL_NUM 8 + +struct cx25821_fmt { + char *name; + u32 fourcc; /* v4l2 format id */ + int depth; + int flags; + u32 cxformat; +}; + +struct cx25821_ctrl { + struct v4l2_queryctrl v; + u32 off; + u32 reg; + u32 mask; + u32 shift; +}; + +struct cx25821_tvnorm { + char *name; + v4l2_std_id id; + u32 cxiformat; + u32 cxoformat; +}; + +struct cx25821_fh { + struct cx25821_dev *dev; + enum v4l2_buf_type type; + int radio; + u32 resources; + + enum v4l2_priority prio; + + /* video overlay */ + struct v4l2_window win; + struct v4l2_clip *clips; + unsigned int nclips; + + /* video capture */ + struct cx25821_fmt *fmt; + unsigned int width, height; + + /* vbi capture */ + struct videobuf_queue vidq; + struct videobuf_queue vbiq; + + /* H264 Encoder specifics ONLY */ + struct videobuf_queue mpegq; + atomic_t v4l_reading; +}; + +enum cx25821_itype { + CX25821_VMUX_COMPOSITE = 1, + CX25821_VMUX_SVIDEO, + CX25821_VMUX_DEBUG, + CX25821_RADIO, +}; + +enum cx25821_src_sel_type { + CX25821_SRC_SEL_EXT_656_VIDEO = 0, + CX25821_SRC_SEL_PARALLEL_MPEG_VIDEO +}; + +/* buffer for one video frame */ +struct cx25821_buffer { + /* common v4l buffer stuff -- must be first */ + struct videobuf_buffer vb; + + /* cx25821 specific */ + unsigned int bpl; + struct btcx_riscmem risc; + struct cx25821_fmt *fmt; + u32 count; +}; + +struct cx25821_input { + enum cx25821_itype type; + unsigned int vmux; + u32 gpio0, gpio1, gpio2, gpio3; +}; + +typedef enum { + CX25821_UNDEFINED = 0, + CX25821_RAW, + CX25821_264 +} port_t; + +struct cx25821_board { + char *name; + port_t porta, portb, portc; + unsigned int tuner_type; + unsigned int radio_type; + unsigned char tuner_addr; + unsigned char radio_addr; + + u32 clk_freq; + struct cx25821_input input[2]; +}; + +struct cx25821_subid { + u16 subvendor; + u16 subdevice; + u32 card; +}; + +struct cx25821_i2c { + struct cx25821_dev *dev; + + int nr; + + /* i2c i/o */ + struct i2c_adapter i2c_adap; + struct i2c_algo_bit_data i2c_algo; + struct i2c_client i2c_client; + u32 i2c_rc; + + /* cx25821 registers used for raw addess */ + u32 i2c_period; + u32 reg_ctrl; + u32 reg_stat; + u32 reg_addr; + u32 reg_rdata; + u32 reg_wdata; +}; + +struct cx25821_dmaqueue { + struct list_head active; + struct list_head queued; + struct timer_list timeout; + struct btcx_riscmem stopper; + u32 count; +}; + +struct cx25821_data { + struct cx25821_dev *dev; + struct sram_channel *channel; +}; + +struct cx25821_dev { + struct list_head devlist; + atomic_t refcount; + struct v4l2_device v4l2_dev; + + struct v4l2_prio_state prio; + + /* pci stuff */ + struct pci_dev *pci; + unsigned char pci_rev, pci_lat; + int pci_bus, pci_slot; + u32 base_io_addr; + u32 __iomem *lmmio; + u8 __iomem *bmmio; + int pci_irqmask; + int hwrevision; + + u32 clk_freq; + + /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */ + struct cx25821_i2c i2c_bus[3]; + + int nr; + struct mutex lock; + + /* board details */ + unsigned int board; + char name[32]; + + /* sram configuration */ + struct sram_channel *sram_channels; + + /* Analog video */ + u32 resources; + unsigned int input; + u32 tvaudio; + v4l2_std_id tvnorm; + unsigned int tuner_type; + unsigned char tuner_addr; + unsigned int radio_type; + unsigned char radio_addr; + unsigned int has_radio; + unsigned int videc_type; + unsigned char videc_addr; + unsigned short _max_num_decoders; + + int ctl_bright; + int ctl_contrast; + int ctl_hue; + int ctl_saturation; + + struct cx25821_data timeout_data[MAX_VID_CHANNEL_NUM]; + + /* Analog Audio Upstream */ + int _audio_is_running; + int _audiopixel_format; + int _is_first_audio_frame; + int _audiofile_status; + int _audio_lines_count; + int _audioframe_count; + int _audio_upstream_channel_select; + int _last_index_irq; //The last interrupt index processed. + + __le32 *_risc_audio_jmp_addr; + __le32 *_risc_virt_start_addr; + __le32 *_risc_virt_addr; + dma_addr_t _risc_phys_addr; + dma_addr_t _risc_phys_start_addr; + + unsigned int _audiorisc_size; + unsigned int _audiodata_buf_size; + __le32 *_audiodata_buf_virt_addr; + dma_addr_t _audiodata_buf_phys_addr; + char *_audiofilename; + + /* V4l */ + u32 freq; + struct video_device *video_dev[MAX_VID_CHANNEL_NUM]; + struct video_device *vbi_dev; + struct video_device *radio_dev; + struct video_device *ioctl_dev; + + struct cx25821_dmaqueue vidq[MAX_VID_CHANNEL_NUM]; + spinlock_t slock; + + /* Video Upstream */ + int _line_size; + int _prog_cnt; + int _pixel_format; + int _is_first_frame; + int _is_running; + int _file_status; + int _lines_count; + int _frame_count; + int _channel_upstream_select; + unsigned int _risc_size; + + __le32 *_dma_virt_start_addr; + __le32 *_dma_virt_addr; + dma_addr_t _dma_phys_addr; + dma_addr_t _dma_phys_start_addr; + + unsigned int _data_buf_size; + __le32 *_data_buf_virt_addr; + dma_addr_t _data_buf_phys_addr; + char *_filename; + char *_defaultname; + + int _line_size_ch2; + int _prog_cnt_ch2; + int _pixel_format_ch2; + int _is_first_frame_ch2; + int _is_running_ch2; + int _file_status_ch2; + int _lines_count_ch2; + int _frame_count_ch2; + int _channel2_upstream_select; + unsigned int _risc_size_ch2; + + __le32 *_dma_virt_start_addr_ch2; + __le32 *_dma_virt_addr_ch2; + dma_addr_t _dma_phys_addr_ch2; + dma_addr_t _dma_phys_start_addr_ch2; + + unsigned int _data_buf_size_ch2; + __le32 *_data_buf_virt_addr_ch2; + dma_addr_t _data_buf_phys_addr_ch2; + char *_filename_ch2; + char *_defaultname_ch2; + + /* MPEG Encoder ONLY settings */ + u32 cx23417_mailbox; + struct cx2341x_mpeg_params mpeg_params; + struct video_device *v4l_device; + atomic_t v4l_reader_count; + struct cx25821_tvnorm encodernorm; + + u32 upstream_riscbuf_size; + u32 upstream_databuf_size; + u32 upstream_riscbuf_size_ch2; + u32 upstream_databuf_size_ch2; + u32 audio_upstream_riscbuf_size; + u32 audio_upstream_databuf_size; + int _isNTSC; + int _frame_index; + int _audioframe_index; + struct workqueue_struct *_irq_queues; + struct work_struct _irq_work_entry; + struct workqueue_struct *_irq_queues_ch2; + struct work_struct _irq_work_entry_ch2; + struct workqueue_struct *_irq_audio_queues; + struct work_struct _audio_work_entry; + char *input_filename; + char *input_filename_ch2; + int _frame_index_ch2; + int _isNTSC_ch2; + char *vid_stdname_ch2; + int pixel_format_ch2; + int channel_select_ch2; + int command_ch2; + char *input_audiofilename; + char *vid_stdname; + int pixel_format; + int channel_select; + int command; + int pixel_formats[VID_CHANNEL_NUM]; + int use_cif_resolution[VID_CHANNEL_NUM]; + int cif_width[VID_CHANNEL_NUM]; + int channel_opened; +}; + +struct upstream_user_struct { + char *input_filename; + char *vid_stdname; + int pixel_format; + int channel_select; + int command; +}; + +struct downstream_user_struct { + char *vid_stdname; + int pixel_format; + int cif_resolution_enable; + int cif_width; + int decoder_select; + int command; + int reg_address; + int reg_data; +}; + +extern struct upstream_user_struct *up_data; + +static inline struct cx25821_dev *get_cx25821(struct v4l2_device *v4l2_dev) +{ + return container_of(v4l2_dev, struct cx25821_dev, v4l2_dev); +} + +#define cx25821_call_all(dev, o, f, args...) \ + v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args) + +extern struct list_head cx25821_devlist; +extern struct cx25821_board cx25821_boards[]; +extern struct cx25821_subid cx25821_subids[]; + +#define SRAM_CH00 0 /* Video A */ +#define SRAM_CH01 1 /* Video B */ +#define SRAM_CH02 2 /* Video C */ +#define SRAM_CH03 3 /* Video D */ +#define SRAM_CH04 4 /* Video E */ +#define SRAM_CH05 5 /* Video F */ +#define SRAM_CH06 6 /* Video G */ +#define SRAM_CH07 7 /* Video H */ + +#define SRAM_CH08 8 /* Audio A */ +#define SRAM_CH09 9 /* Video Upstream I */ +#define SRAM_CH10 10 /* Video Upstream J */ +#define SRAM_CH11 11 /* Audio Upstream AUD_CHANNEL_B */ + +#define VID_UPSTREAM_SRAM_CHANNEL_I SRAM_CH09 +#define VID_UPSTREAM_SRAM_CHANNEL_J SRAM_CH10 +#define AUDIO_UPSTREAM_SRAM_CHANNEL_B SRAM_CH11 +#define VIDEO_IOCTL_CH 11 + +struct sram_channel { + char *name; + u32 i; + u32 cmds_start; + u32 ctrl_start; + u32 cdt; + u32 fifo_start; + u32 fifo_size; + u32 ptr1_reg; + u32 ptr2_reg; + u32 cnt1_reg; + u32 cnt2_reg; + u32 int_msk; + u32 int_stat; + u32 int_mstat; + u32 dma_ctl; + u32 gpcnt_ctl; + u32 gpcnt; + u32 aud_length; + u32 aud_cfg; + u32 fld_aud_fifo_en; + u32 fld_aud_risc_en; + + //For Upstream Video + u32 vid_fmt_ctl; + u32 vid_active_ctl1; + u32 vid_active_ctl2; + u32 vid_cdt_size; + + u32 vip_ctl; + u32 pix_frmt; + u32 jumponly; + u32 irq_bit; +}; +extern struct sram_channel cx25821_sram_channels[]; + +#define STATUS_SUCCESS 0 +#define STATUS_UNSUCCESSFUL -1 + +#define cx_read(reg) readl(dev->lmmio + ((reg)>>2)) +#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2)) + +#define cx_andor(reg, mask, value) \ + writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\ + ((value) & (mask)), dev->lmmio+((reg)>>2)) + +#define cx_set(reg, bit) cx_andor((reg), (bit), (bit)) +#define cx_clear(reg, bit) cx_andor((reg), (bit), 0) + +#define Set_GPIO_Bit(Bit) (1 << Bit) +#define Clear_GPIO_Bit(Bit) (~(1 << Bit)) + +#define CX25821_ERR(fmt, args...) printk(KERN_ERR "cx25821(%d): " fmt, dev->board, ## args) +#define CX25821_WARN(fmt, args...) printk(KERN_WARNING "cx25821(%d): " fmt, dev->board , ## args) +#define CX25821_INFO(fmt, args...) printk(KERN_INFO "cx25821(%d): " fmt, dev->board , ## args) + +extern int cx25821_i2c_register(struct cx25821_i2c *bus); +extern void cx25821_card_setup(struct cx25821_dev *dev); +extern int cx25821_ir_init(struct cx25821_dev *dev); +extern int cx25821_i2c_read(struct cx25821_i2c *bus, u16 reg_addr, int *value); +extern int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value); +extern int cx25821_i2c_unregister(struct cx25821_i2c *bus); +extern void cx25821_gpio_init(struct cx25821_dev *dev); +extern void cx25821_set_gpiopin_direction(struct cx25821_dev *dev, + int pin_number, int pin_logic_value); + +extern int medusa_video_init(struct cx25821_dev *dev); +extern int medusa_set_videostandard(struct cx25821_dev *dev); +extern void medusa_set_resolution(struct cx25821_dev *dev, int width, + int decoder_select); +extern int medusa_set_brightness(struct cx25821_dev *dev, int brightness, + int decoder); +extern int medusa_set_contrast(struct cx25821_dev *dev, int contrast, + int decoder); +extern int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder); +extern int medusa_set_saturation(struct cx25821_dev *dev, int saturation, + int decoder); + +extern int cx25821_sram_channel_setup(struct cx25821_dev *dev, + struct sram_channel *ch, unsigned int bpl, + u32 risc); + +extern int cx25821_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc, + struct scatterlist *sglist, + unsigned int top_offset, + unsigned int bottom_offset, + unsigned int bpl, + unsigned int padding, unsigned int lines); +extern int cx25821_risc_databuffer_audio(struct pci_dev *pci, + struct btcx_riscmem *risc, + struct scatterlist *sglist, + unsigned int bpl, + unsigned int lines, unsigned int lpi); +extern void cx25821_free_buffer(struct videobuf_queue *q, + struct cx25821_buffer *buf); +extern int cx25821_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc, + u32 reg, u32 mask, u32 value); +extern void cx25821_sram_channel_dump(struct cx25821_dev *dev, + struct sram_channel *ch); +extern void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev, + struct sram_channel *ch); + +extern struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci); +extern void cx25821_print_irqbits(char *name, char *tag, char **strings, + int len, u32 bits, u32 mask); +extern void cx25821_dev_unregister(struct cx25821_dev *dev); +extern int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev, + struct sram_channel *ch, + unsigned int bpl, u32 risc); + +extern int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, + int channel_select, int pixel_format); +extern int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, + int channel_select, int pixel_format); +extern int cx25821_audio_upstream_init(struct cx25821_dev *dev, + int channel_select); +extern void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev); +extern void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev); +extern void cx25821_free_mem_upstream_audio(struct cx25821_dev *dev); +extern void cx25821_start_upstream_video_ch1(struct cx25821_dev *dev, + struct upstream_user_struct + *up_data); +extern void cx25821_start_upstream_video_ch2(struct cx25821_dev *dev, + struct upstream_user_struct + *up_data); +extern void cx25821_start_upstream_audio(struct cx25821_dev *dev, + struct upstream_user_struct *up_data); +extern void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev); +extern void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev); +extern void cx25821_stop_upstream_audio(struct cx25821_dev *dev); +extern int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev, + struct sram_channel *ch, + unsigned int bpl, u32 risc); +extern void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel, + u32 format); +extern void cx25821_videoioctl_unregister(struct cx25821_dev *dev); +extern struct video_device *cx25821_vdev_init(struct cx25821_dev *dev, + struct pci_dev *pci, + struct video_device *template, + char *type); +#endif diff --git a/drivers/staging/go7007/Kconfig b/drivers/staging/go7007/Kconfig index ca6ade6c4b47..e47f683a323e 100644 --- a/drivers/staging/go7007/Kconfig +++ b/drivers/staging/go7007/Kconfig @@ -1,5 +1,5 @@ config VIDEO_GO7007 - tristate "Go 7007 support" + tristate "WIS GO7007 MPEG encoder support" depends on VIDEO_DEV && PCI && I2C && INPUT depends on SND select VIDEOBUF_DMA_SG @@ -10,17 +10,19 @@ config VIDEO_GO7007 select CRC32 default N ---help--- - This is a video4linux driver for some weird device... + This is a video4linux driver for the WIS GO7007 MPEG + encoder chip. To compile this driver as a module, choose M here: the module will be called go7007 config VIDEO_GO7007_USB - tristate "Go 7007 USB support" + tristate "WIS GO7007 USB support" depends on VIDEO_GO7007 && USB default N ---help--- - This is a video4linux driver for some weird device... + This is a video4linux driver for the WIS GO7007 MPEG + encoder chip over USB. To compile this driver as a module, choose M here: the module will be called go7007-usb @@ -30,8 +32,78 @@ config VIDEO_GO7007_USB_S2250_BOARD depends on VIDEO_GO7007_USB && DVB_USB default N ---help--- - This is a video4linux driver for the Sensoray 2250/2251 device + This is a video4linux driver for the Sensoray 2250/2251 device. To compile this driver as a module, choose M here: the - module will be called s2250-board + module will be called s2250 + +config VIDEO_GO7007_OV7640 + tristate "OV7640 subdev support" + depends on VIDEO_GO7007 + default N + ---help--- + This is a video4linux driver for the OV7640 sub-device. + + To compile this driver as a module, choose M here: the + module will be called wis-ov7640 + +config VIDEO_GO7007_SAA7113 + tristate "SAA7113 subdev support" + depends on VIDEO_GO7007 + default N + ---help--- + This is a video4linux driver for the SAA7113 sub-device. + + To compile this driver as a module, choose M here: the + module will be called wis-saa7113 + +config VIDEO_GO7007_SAA7115 + tristate "SAA7115 subdev support" + depends on VIDEO_GO7007 + default N + ---help--- + This is a video4linux driver for the SAA7115 sub-device. + + To compile this driver as a module, choose M here: the + module will be called wis-saa7115 + +config VIDEO_GO7007_TW9903 + tristate "TW9903 subdev support" + depends on VIDEO_GO7007 + default N + ---help--- + This is a video4linux driver for the TW9903 sub-device. + + To compile this driver as a module, choose M here: the + module will be called wis-tw9903 + +config VIDEO_GO7007_UDA1342 + tristate "UDA1342 subdev support" + depends on VIDEO_GO7007 + default N + ---help--- + This is a video4linux driver for the UDA1342 sub-device. + + To compile this driver as a module, choose M here: the + module will be called wis-uda1342 + +config VIDEO_GO7007_SONY_TUNER + tristate "Sony tuner subdev support" + depends on VIDEO_GO7007 + default N + ---help--- + This is a video4linux driver for the Sony Tuner sub-device. + + To compile this driver as a module, choose M here: the + module will be called wis-sony-tuner + +config VIDEO_GO7007_TW2804 + tristate "TW2804 subdev support" + depends on VIDEO_GO7007 + default N + ---help--- + This is a video4linux driver for the TW2804 sub-device. + + To compile this driver as a module, choose M here: the + module will be called wis-tw2804 diff --git a/drivers/staging/go7007/Makefile b/drivers/staging/go7007/Makefile index e514b4af6d06..d14ea84a01f6 100644 --- a/drivers/staging/go7007/Makefile +++ b/drivers/staging/go7007/Makefile @@ -6,22 +6,34 @@ obj-$(CONFIG_VIDEO_GO7007) += go7007.o obj-$(CONFIG_VIDEO_GO7007_USB) += go7007-usb.o obj-$(CONFIG_VIDEO_GO7007_USB_S2250_BOARD) += s2250.o +obj-$(CONFIG_VIDEO_GO7007_SAA7113) += wis-saa7113.o +obj-$(CONFIG_VIDEO_GO7007_OV7640) += wis-ov7640.o +obj-$(CONFIG_VIDEO_GO7007_SAA7115) += wis-saa7115.o +obj-$(CONFIG_VIDEO_GO7007_TW9903) += wis-tw9903.o +obj-$(CONFIG_VIDEO_GO7007_UDA1342) += wis-uda1342.o +obj-$(CONFIG_VIDEO_GO7007_SONY_TUNER) += wis-sony-tuner.o +obj-$(CONFIG_VIDEO_GO7007_TW2804) += wis-tw2804.o go7007-objs += go7007-v4l2.o go7007-driver.o go7007-i2c.o go7007-fw.o \ - snd-go7007.o wis-saa7113.o + snd-go7007.o s2250-objs += s2250-board.o s2250-loader.o -# Uncompile when the saa7134 patches get into upstream +# Uncomment when the saa7134 patches get into upstream #ifneq ($(CONFIG_VIDEO_SAA7134),) #obj-$(CONFIG_VIDEO_SAA7134) += saa7134-go7007.o -#EXTRA_CFLAGS += -Idrivers/media/video/saa7134 +#EXTRA_CFLAGS += -Idrivers/media/video/saa7134 -DSAA7134_MPEG_GO7007=3 #endif +# S2250 needs cypress ezusb loader from dvb-usb ifneq ($(CONFIG_VIDEO_GO7007_USB_S2250_BOARD),) EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-usb endif -EXTRA_CFLAGS += -Idrivers/staging/saa7134 EXTRA_CFLAGS += -Idrivers/media/dvb/frontends EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core + +# Ubuntu 8.04 has CONFIG_SND undefined, so include lum sound/config.h too +ifeq ($(CONFIG_SND),) +EXTRA_CFLAGS += -include sound/config.h +endif diff --git a/drivers/staging/go7007/go7007-driver.c b/drivers/staging/go7007/go7007-driver.c index 77b1e769ac92..472f4bb08fdc 100644 --- a/drivers/staging/go7007/go7007-driver.c +++ b/drivers/staging/go7007/go7007-driver.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include @@ -49,7 +49,7 @@ int go7007_read_interrupt(struct go7007 *go, u16 *value, u16 *data) go->hpi_ops->read_interrupt(go); if (wait_event_timeout(go->interrupt_waitq, go->interrupt_available, 5*HZ) < 0) { - printk(KERN_ERR "go7007: timeout waiting for read interrupt\n"); + v4l2_err(go->video_dev, "timeout waiting for read interrupt\n"); return -1; } if (!go->interrupt_available) @@ -97,13 +97,12 @@ static int go7007_load_encoder(struct go7007 *go) u16 intr_val, intr_data; if (request_firmware(&fw_entry, fw_name, go->dev)) { - printk(KERN_ERR - "go7007: unable to load firmware from file \"%s\"\n", - fw_name); + v4l2_err(go, "unable to load firmware from file " + "\"%s\"\n", fw_name); return -1; } if (fw_entry->size < 16 || memcmp(fw_entry->data, "WISGO7007FW", 11)) { - printk(KERN_ERR "go7007: file \"%s\" does not appear to be " + v4l2_err(go, "file \"%s\" does not appear to be " "go7007 firmware\n", fw_name); release_firmware(fw_entry); return -1; @@ -111,7 +110,7 @@ static int go7007_load_encoder(struct go7007 *go) fw_len = fw_entry->size - 16; bounce = kmalloc(fw_len, GFP_KERNEL); if (bounce == NULL) { - printk(KERN_ERR "go7007: unable to allocate %d bytes for " + v4l2_err(go, "unable to allocate %d bytes for " "firmware transfer\n", fw_len); release_firmware(fw_entry); return -1; @@ -122,7 +121,7 @@ static int go7007_load_encoder(struct go7007 *go) go7007_send_firmware(go, bounce, fw_len) < 0 || go7007_read_interrupt(go, &intr_val, &intr_data) < 0 || (intr_val & ~0x1) != 0x5a5a) { - printk(KERN_ERR "go7007: error transferring firmware\n"); + v4l2_err(go, "error transferring firmware\n"); rv = -1; } kfree(bounce); @@ -140,9 +139,9 @@ int go7007_boot_encoder(struct go7007 *go, int init_i2c) { int ret; - down(&go->hw_lock); + mutex_lock(&go->hw_lock); ret = go7007_load_encoder(go); - up(&go->hw_lock); + mutex_unlock(&go->hw_lock); if (ret < 0) return -1; if (!init_i2c) @@ -257,9 +256,9 @@ int go7007_register_encoder(struct go7007 *go) printk(KERN_INFO "go7007: registering new %s\n", go->name); - down(&go->hw_lock); + mutex_lock(&go->hw_lock); ret = go7007_init_encoder(go); - up(&go->hw_lock); + mutex_unlock(&go->hw_lock); if (ret < 0) return -1; @@ -316,7 +315,7 @@ int go7007_start_encoder(struct go7007 *go) if (go7007_send_firmware(go, fw, fw_len) < 0 || go7007_read_interrupt(go, &intr_val, &intr_data) < 0) { - printk(KERN_ERR "go7007: error transferring firmware\n"); + v4l2_err(go->video_dev, "error transferring firmware\n"); rv = -1; goto start_error; } @@ -325,7 +324,7 @@ int go7007_start_encoder(struct go7007 *go) go->parse_length = 0; go->seen_frame = 0; if (go7007_stream_start(go) < 0) { - printk(KERN_ERR "go7007: error starting stream transfer\n"); + v4l2_err(go->video_dev, "error starting stream transfer\n"); rv = -1; goto start_error; } @@ -421,7 +420,7 @@ void go7007_parse_video_stream(struct go7007 *go, u8 *buf, int length) for (i = 0; i < length; ++i) { if (go->active_buf != NULL && go->active_buf->bytesused >= GO7007_BUF_SIZE - 3) { - printk(KERN_DEBUG "go7007: dropping oversized frame\n"); + v4l2_info(go->video_dev, "dropping oversized frame\n"); go->active_buf->offset -= go->active_buf->bytesused; go->active_buf->bytesused = 0; go->active_buf->modet_active = 0; @@ -604,7 +603,7 @@ struct go7007 *go7007_alloc(struct go7007_board_info *board, struct device *dev) go->tuner_type = -1; go->channel_number = 0; go->name[0] = 0; - init_MUTEX(&go->hw_lock); + mutex_init(&go->hw_lock); init_waitqueue_head(&go->frame_waitq); spin_lock_init(&go->spinlock); go->video_dev = NULL; @@ -669,8 +668,8 @@ void go7007_remove(struct go7007 *go) if (i2c_del_adapter(&go->i2c_adapter) == 0) go->i2c_adapter_online = 0; else - printk(KERN_ERR - "go7007: error removing I2C adapter!\n"); + v4l2_err(go->video_dev, + "error removing I2C adapter!\n"); } if (go->audio_enabled) diff --git a/drivers/staging/go7007/go7007-fw.c b/drivers/staging/go7007/go7007-fw.c index 871ed43e4e05..a8bb264e0074 100644 --- a/drivers/staging/go7007/go7007-fw.c +++ b/drivers/staging/go7007/go7007-fw.c @@ -1034,7 +1034,8 @@ static int brctrl_to_package(struct go7007 *go, 0xBF1B, framelen[7], 0, 0, -#if 0 /* Remove once we don't care about matching */ +#if 0 + /* Remove once we don't care about matching */ 0x200e, 0x0000, 0xBF56, 4, 0xBF57, 0, diff --git a/drivers/staging/go7007/go7007-i2c.c b/drivers/staging/go7007/go7007-i2c.c index c82867fdd28d..b8cfa1a6eaeb 100644 --- a/drivers/staging/go7007/go7007-i2c.c +++ b/drivers/staging/go7007/go7007-i2c.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include @@ -48,7 +48,7 @@ /* There is only one I2C port on the TW2804 that feeds all four GO7007 VIPs * on the Adlink PCI-MPG24, so access is shared between all of them. */ -static DECLARE_MUTEX(adlink_mpg24_i2c_lock); +static DEFINE_MUTEX(adlink_mpg24_i2c_lock); static int go7007_i2c_xfer(struct go7007 *go, u16 addr, int read, u16 command, int flags, u8 *data) @@ -69,11 +69,11 @@ static int go7007_i2c_xfer(struct go7007 *go, u16 addr, int read, *data, command, addr); #endif - down(&go->hw_lock); + mutex_lock(&go->hw_lock); if (go->board_id == GO7007_BOARDID_ADLINK_MPG24) { /* Bridge the I2C port on this GO7007 to the shared bus */ - down(&adlink_mpg24_i2c_lock); + mutex_lock(&adlink_mpg24_i2c_lock); go7007_write_addr(go, 0x3c82, 0x0020); } @@ -134,9 +134,9 @@ i2c_done: if (go->board_id == GO7007_BOARDID_ADLINK_MPG24) { /* Isolate the I2C port on this GO7007 from the shared bus */ go7007_write_addr(go, 0x3c82, 0x0000); - up(&adlink_mpg24_i2c_lock); + mutex_unlock(&adlink_mpg24_i2c_lock); } - up(&go->hw_lock); + mutex_unlock(&go->hw_lock); return ret; } diff --git a/drivers/staging/go7007/go7007-priv.h b/drivers/staging/go7007/go7007-priv.h index 178d18119faa..ce9307e3e186 100644 --- a/drivers/staging/go7007/go7007-priv.h +++ b/drivers/staging/go7007/go7007-priv.h @@ -132,7 +132,7 @@ struct go7007_buffer { struct go7007_file { struct go7007 *go; - struct semaphore lock; + struct mutex lock; int buf_count; struct go7007_buffer *bufs; }; @@ -170,7 +170,7 @@ struct go7007 { int ref_count; enum { STATUS_INIT, STATUS_ONLINE, STATUS_SHUTDOWN } status; spinlock_t spinlock; - struct semaphore hw_lock; + struct mutex hw_lock; int streaming; int in_use; int audio_enabled; @@ -240,7 +240,7 @@ struct go7007 { unsigned short interrupt_data; }; -/* All of these must be called with the hpi_lock semaphore held! */ +/* All of these must be called with the hpi_lock mutex held! */ #define go7007_interface_reset(go) \ ((go)->hpi_ops->interface_reset(go)) #define go7007_write_interrupt(go, x, y) \ diff --git a/drivers/staging/go7007/go7007-usb.c b/drivers/staging/go7007/go7007-usb.c index aa4a9e0b9954..ecaa3c989cf4 100644 --- a/drivers/staging/go7007/go7007-usb.c +++ b/drivers/staging/go7007/go7007-usb.c @@ -33,7 +33,8 @@ static unsigned int assume_endura; module_param(assume_endura, int, 0644); -MODULE_PARM_DESC(assume_endura, "when probing fails, hardware is a Pelco Endura"); +MODULE_PARM_DESC(assume_endura, "when probing fails, " + "hardware is a Pelco Endura"); /* #define GO7007_USB_DEBUG */ /* #define GO7007_I2C_DEBUG */ /* for debugging the EZ-USB I2C adapter */ @@ -44,12 +45,12 @@ MODULE_PARM_DESC(assume_endura, "when probing fails, hardware is a Pelco Endura" /* * Pipes on EZ-USB interface: - * 0 snd - Control - * 0 rcv - Control - * 2 snd - Download firmware (control) - * 4 rcv - Read Interrupt (interrupt) - * 6 rcv - Read Video (bulk) - * 8 rcv - Read Audio (bulk) + * 0 snd - Control + * 0 rcv - Control + * 2 snd - Download firmware (control) + * 4 rcv - Read Interrupt (interrupt) + * 6 rcv - Read Video (bulk) + * 8 rcv - Read Audio (bulk) */ #define GO7007_USB_EZUSB (1<<0) @@ -62,7 +63,7 @@ struct go7007_usb_board { struct go7007_usb { struct go7007_usb_board *board; - struct semaphore i2c_lock; + struct mutex i2c_lock; struct usb_device *usbdev; struct urb *video_urbs[8]; struct urb *audio_urbs[8]; @@ -97,7 +98,7 @@ static struct go7007_usb_board board_matrix_ii = { }, }, .num_inputs = 2, - .inputs = { + .inputs = { { .video_input = 0, .name = "Composite", @@ -134,7 +135,7 @@ static struct go7007_usb_board board_matrix_reload = { }, }, .num_inputs = 2, - .inputs = { + .inputs = { { .video_input = 0, .name = "Composite", @@ -172,7 +173,7 @@ static struct go7007_usb_board board_star_trek = { }, }, .num_inputs = 2, - .inputs = { + .inputs = { { .video_input = 1, /* .audio_input = AUDIO_EXTERN, */ @@ -228,7 +229,7 @@ static struct go7007_usb_board board_px_tv402u = { }, }, .num_inputs = 3, - .inputs = { + .inputs = { { .video_input = 1, .audio_input = TVAUDIO_INPUT_EXTERN, @@ -276,7 +277,7 @@ static struct go7007_usb_board board_xmen = { }, }, .num_inputs = 1, - .inputs = { + .inputs = { { .name = "Camera", }, @@ -309,7 +310,7 @@ static struct go7007_usb_board board_matrix_revolution = { }, }, .num_inputs = 2, - .inputs = { + .inputs = { { .video_input = 2, .name = "Composite", @@ -341,7 +342,7 @@ static struct go7007_usb_board board_lifeview_lr192 = { GO7007_SENSOR_SCALING, .num_i2c_devs = 0, .num_inputs = 1, - .inputs = { + .inputs = { { .video_input = 0, .name = "Composite", @@ -367,7 +368,7 @@ static struct go7007_usb_board board_endura = { .sensor_h_offset = 8, .num_i2c_devs = 0, .num_inputs = 1, - .inputs = { + .inputs = { { .name = "Camera", }, @@ -399,7 +400,7 @@ static struct go7007_usb_board board_adlink_mpg24 = { }, }, .num_inputs = 1, - .inputs = { + .inputs = { { .name = "Composite", }, @@ -430,7 +431,7 @@ static struct go7007_usb_board board_sensoray_2250 = { }, }, .num_inputs = 2, - .inputs = { + .inputs = { { .video_input = 0, .name = "Composite", @@ -734,14 +735,15 @@ static int go7007_usb_read_interrupt(struct go7007 *go) static void go7007_usb_read_video_pipe_complete(struct urb *urb) { struct go7007 *go = (struct go7007 *)urb->context; - int r, status = urb-> status; + int r, status = urb->status; if (!go->streaming) { wake_up_interruptible(&go->frame_waitq); return; } if (status) { - printk(KERN_ERR "go7007-usb: error in video pipe: %d\n", status); + printk(KERN_ERR "go7007-usb: error in video pipe: %d\n", + status); return; } if (urb->actual_length != urb->transfer_buffer_length) { @@ -762,7 +764,8 @@ static void go7007_usb_read_audio_pipe_complete(struct urb *urb) if (!go->streaming) return; if (status) { - printk(KERN_ERR "go7007-usb: error in audio pipe: %d\n", status); + printk(KERN_ERR "go7007-usb: error in audio pipe: %d\n", + status); return; } if (urb->actual_length != urb->transfer_buffer_length) { @@ -877,7 +880,7 @@ static int go7007_usb_i2c_master_xfer(struct i2c_adapter *adapter, if (go->status == STATUS_SHUTDOWN) return -1; - down(&usb->i2c_lock); + mutex_lock(&usb->i2c_lock); for (i = 0; i < num; ++i) { /* The hardware command is "write some bytes then read some @@ -935,7 +938,7 @@ static int go7007_usb_i2c_master_xfer(struct i2c_adapter *adapter, ret = 0; i2c_done: - up(&usb->i2c_lock); + mutex_unlock(&usb->i2c_lock); return ret; } @@ -1017,7 +1020,7 @@ static int go7007_usb_probe(struct usb_interface *intf, break; case GO7007_BOARDID_SENSORAY_2250: printk(KERN_INFO "Sensoray 2250 found\n"); - name = "Sensoray 2250/2251\n"; + name = "Sensoray 2250/2251"; board = &board_sensoray_2250; break; default: @@ -1065,7 +1068,7 @@ static int go7007_usb_probe(struct usb_interface *intf, if (board->flags & GO7007_USB_EZUSB_I2C) { memcpy(&go->i2c_adapter, &go7007_usb_adap_templ, sizeof(go7007_usb_adap_templ)); - init_MUTEX(&usb->i2c_lock); + mutex_init(&usb->i2c_lock); go->i2c_adapter.dev.parent = go->dev; i2c_set_adapdata(&go->i2c_adapter, go); if (i2c_add_adapter(&go->i2c_adapter) < 0) { @@ -1096,7 +1099,7 @@ static int go7007_usb_probe(struct usb_interface *intf, usb->board = board = &board_endura; go->board_info = &board->main_info; strncpy(go->name, "Pelco Endura", - sizeof(go->name)); + sizeof(go->name)); } else { u16 channel; @@ -1154,8 +1157,7 @@ static int go7007_usb_probe(struct usb_interface *intf, * to the EZ-USB GPIO output pins */ if (go7007_usb_vendor_request(go, 0x40, 0x7f02, 0, NULL, 0, 0) < 0) { - printk(KERN_ERR - "go7007-usb: GPIO write failed!\n"); + printk(KERN_ERR "go7007-usb: GPIO write failed!\n"); goto initfail; } } diff --git a/drivers/staging/go7007/go7007-v4l2.c b/drivers/staging/go7007/go7007-v4l2.c index 06cacd37bbd8..4bd353afa596 100644 --- a/drivers/staging/go7007/go7007-v4l2.c +++ b/drivers/staging/go7007/go7007-v4l2.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include @@ -75,7 +75,7 @@ static int go7007_streamoff(struct go7007 *go) int retval = -EINVAL; unsigned long flags; - down(&go->hw_lock); + mutex_lock(&go->hw_lock); if (go->streaming) { go->streaming = 0; go7007_stream_stop(go); @@ -85,7 +85,7 @@ static int go7007_streamoff(struct go7007 *go) go7007_reset_encoder(go); retval = 0; } - up(&go->hw_lock); + mutex_unlock(&go->hw_lock); return 0; } @@ -101,7 +101,7 @@ static int go7007_open(struct file *file) return -ENOMEM; ++go->ref_count; gofh->go = go; - init_MUTEX(&gofh->lock); + mutex_init(&gofh->lock); gofh->buf_count = 0; file->private_data = gofh; return 0; @@ -383,13 +383,10 @@ static int clip_to_modet_map(struct go7007 *go, int region, } return 0; } +#endif -static int mpeg_queryctrl(u32 id, struct v4l2_queryctrl *ctrl) +static int mpeg_queryctrl(struct v4l2_queryctrl *ctrl) { - static const u32 user_ctrls[] = { - V4L2_CID_USER_CLASS, - 0 - }; static const u32 mpeg_ctrls[] = { V4L2_CID_MPEG_CLASS, V4L2_CID_MPEG_STREAM_TYPE, @@ -401,26 +398,15 @@ static int mpeg_queryctrl(u32 id, struct v4l2_queryctrl *ctrl) 0 }; static const u32 *ctrl_classes[] = { - user_ctrls, mpeg_ctrls, NULL }; - /* The ctrl may already contain the queried i2c controls, - * query the mpeg controls if the existing ctrl id is - * greater than the next mpeg ctrl id. - */ - id = v4l2_ctrl_next(ctrl_classes, id); - if (id >= ctrl->id && ctrl->name[0]) - return 0; - - memset(ctrl, 0, sizeof(*ctrl)); - ctrl->id = id; + ctrl->id = v4l2_ctrl_next(ctrl_classes, ctrl->id); switch (ctrl->id) { - case V4L2_CID_USER_CLASS: case V4L2_CID_MPEG_CLASS: - return v4l2_ctrl_query_fill_std(ctrl); + return v4l2_ctrl_query_fill(ctrl, 0, 0, 0, 0); case V4L2_CID_MPEG_STREAM_TYPE: return v4l2_ctrl_query_fill(ctrl, V4L2_MPEG_STREAM_TYPE_MPEG2_DVD, @@ -437,20 +423,21 @@ static int mpeg_queryctrl(u32 id, struct v4l2_queryctrl *ctrl) V4L2_MPEG_VIDEO_ASPECT_16x9, 1, V4L2_MPEG_VIDEO_ASPECT_1x1); case V4L2_CID_MPEG_VIDEO_GOP_SIZE: + return v4l2_ctrl_query_fill(ctrl, 0, 34, 1, 15); case V4L2_CID_MPEG_VIDEO_GOP_CLOSURE: - return v4l2_ctrl_query_fill_std(ctrl); + return v4l2_ctrl_query_fill(ctrl, 0, 1, 1, 0); case V4L2_CID_MPEG_VIDEO_BITRATE: return v4l2_ctrl_query_fill(ctrl, 64000, 10000000, 1, - 9800000); + 1500000); default: - break; + return -EINVAL; } - return -EINVAL; + return 0; } -static int mpeg_s_control(struct v4l2_control *ctrl, struct go7007 *go) +static int mpeg_s_ctrl(struct v4l2_control *ctrl, struct go7007 *go) { /* pretty sure we can't change any of these while streaming */ if (go->streaming) @@ -528,6 +515,8 @@ static int mpeg_s_control(struct v4l2_control *ctrl, struct go7007 *go) } break; case V4L2_CID_MPEG_VIDEO_GOP_SIZE: + if (ctrl->value < 0 || ctrl->value > 34) + return -EINVAL; go->gop_size = ctrl->value; break; case V4L2_CID_MPEG_VIDEO_GOP_CLOSURE: @@ -547,7 +536,7 @@ static int mpeg_s_control(struct v4l2_control *ctrl, struct go7007 *go) return 0; } -static int mpeg_g_control(struct v4l2_control *ctrl, struct go7007 *go) +static int mpeg_g_ctrl(struct v4l2_control *ctrl, struct go7007 *go) { switch (ctrl->id) { case V4L2_CID_MPEG_STREAM_TYPE: @@ -600,13 +589,11 @@ static int mpeg_g_control(struct v4l2_control *ctrl, struct go7007 *go) } return 0; } -#endif static int vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; strlcpy(cap->driver, "go7007", sizeof(cap->driver)); strlcpy(cap->card, go->name, sizeof(cap->card)); @@ -653,8 +640,7 @@ static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *fmt) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; fmt->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; fmt->fmt.pix.width = go->width; @@ -672,8 +658,7 @@ static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *fmt) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; return set_capture_size(go, fmt, 1); } @@ -681,8 +666,7 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *fmt) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; if (go->streaming) return -EBUSY; @@ -705,14 +689,14 @@ static int vidioc_reqbufs(struct file *file, void *priv, req->memory != V4L2_MEMORY_MMAP) return -EINVAL; - down(&gofh->lock); + mutex_lock(&gofh->lock); for (i = 0; i < gofh->buf_count; ++i) if (gofh->bufs[i].mapped > 0) goto unlock_and_return; - down(&go->hw_lock); + mutex_lock(&go->hw_lock); if (go->in_use > 0 && gofh->buf_count == 0) { - up(&go->hw_lock); + mutex_unlock(&go->hw_lock); goto unlock_and_return; } @@ -731,7 +715,7 @@ static int vidioc_reqbufs(struct file *file, void *priv, GFP_KERNEL); if (!gofh->bufs) { - up(&go->hw_lock); + mutex_unlock(&go->hw_lock); goto unlock_and_return; } @@ -750,8 +734,8 @@ static int vidioc_reqbufs(struct file *file, void *priv, } gofh->buf_count = count; - up(&go->hw_lock); - up(&gofh->lock); + mutex_unlock(&go->hw_lock); + mutex_unlock(&gofh->lock); memset(req, 0, sizeof(*req)); @@ -762,7 +746,7 @@ static int vidioc_reqbufs(struct file *file, void *priv, return 0; unlock_and_return: - up(&gofh->lock); + mutex_unlock(&gofh->lock); return retval; } @@ -778,7 +762,7 @@ static int vidioc_querybuf(struct file *file, void *priv, index = buf->index; - down(&gofh->lock); + mutex_lock(&gofh->lock); if (index >= gofh->buf_count) goto unlock_and_return; @@ -802,12 +786,12 @@ static int vidioc_querybuf(struct file *file, void *priv, buf->memory = V4L2_MEMORY_MMAP; buf->m.offset = index * GO7007_BUF_SIZE; buf->length = GO7007_BUF_SIZE; - up(&gofh->lock); + mutex_unlock(&gofh->lock); return 0; unlock_and_return: - up(&gofh->lock); + mutex_unlock(&gofh->lock); return retval; } @@ -824,7 +808,7 @@ static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf) buf->memory != V4L2_MEMORY_MMAP) return retval; - down(&gofh->lock); + mutex_lock(&gofh->lock); if (buf->index < 0 || buf->index >= gofh->buf_count) goto unlock_and_return; @@ -865,12 +849,12 @@ static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf) spin_lock_irqsave(&go->spinlock, flags); list_add_tail(&gobuf->stream, &go->stream); spin_unlock_irqrestore(&go->spinlock, flags); - up(&gofh->lock); + mutex_unlock(&gofh->lock); return 0; unlock_and_return: - up(&gofh->lock); + mutex_unlock(&gofh->lock); return retval; } @@ -890,7 +874,7 @@ static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf) if (buf->memory != V4L2_MEMORY_MMAP) return retval; - down(&gofh->lock); + mutex_lock(&gofh->lock); if (list_empty(&go->stream)) goto unlock_and_return; gobuf = list_entry(go->stream.next, @@ -934,11 +918,11 @@ static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf) buf->length = GO7007_BUF_SIZE; buf->reserved = gobuf->modet_active; - up(&gofh->lock); + mutex_unlock(&gofh->lock); return 0; unlock_and_return: - up(&gofh->lock); + mutex_unlock(&gofh->lock); return retval; } @@ -952,8 +936,8 @@ static int vidioc_streamon(struct file *file, void *priv, if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; - down(&gofh->lock); - down(&go->hw_lock); + mutex_lock(&gofh->lock); + mutex_lock(&go->hw_lock); if (!go->streaming) { go->streaming = 1; @@ -964,8 +948,8 @@ static int vidioc_streamon(struct file *file, void *priv, else retval = 0; } - up(&go->hw_lock); - up(&gofh->lock); + mutex_unlock(&go->hw_lock); + mutex_unlock(&gofh->lock); return retval; } @@ -978,9 +962,9 @@ static int vidioc_streamoff(struct file *file, void *priv, if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; - down(&gofh->lock); + mutex_lock(&gofh->lock); go7007_streamoff(go); - up(&gofh->lock); + mutex_unlock(&gofh->lock); return 0; } @@ -988,22 +972,20 @@ static int vidioc_streamoff(struct file *file, void *priv, static int vidioc_queryctrl(struct file *file, void *priv, struct v4l2_queryctrl *query) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; if (!go->i2c_adapter_online) return -EIO; i2c_clients_command(&go->i2c_adapter, VIDIOC_QUERYCTRL, query); - return (!query->name[0]) ? -EINVAL : 0; + return (!query->name[0]) ? mpeg_queryctrl(query) : 0; } static int vidioc_g_ctrl(struct file *file, void *priv, struct v4l2_control *ctrl) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; struct v4l2_queryctrl query; if (!go->i2c_adapter_online) @@ -1013,7 +995,7 @@ static int vidioc_g_ctrl(struct file *file, void *priv, query.id = ctrl->id; i2c_clients_command(&go->i2c_adapter, VIDIOC_QUERYCTRL, &query); if (query.name[0] == 0) - return -EINVAL; + return mpeg_g_ctrl(ctrl, go); i2c_clients_command(&go->i2c_adapter, VIDIOC_G_CTRL, ctrl); return 0; @@ -1022,8 +1004,7 @@ static int vidioc_g_ctrl(struct file *file, void *priv, static int vidioc_s_ctrl(struct file *file, void *priv, struct v4l2_control *ctrl) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; struct v4l2_queryctrl query; if (!go->i2c_adapter_online) @@ -1033,7 +1014,7 @@ static int vidioc_s_ctrl(struct file *file, void *priv, query.id = ctrl->id; i2c_clients_command(&go->i2c_adapter, VIDIOC_QUERYCTRL, &query); if (query.name[0] == 0) - return -EINVAL; + return mpeg_s_ctrl(ctrl, go); i2c_clients_command(&go->i2c_adapter, VIDIOC_S_CTRL, ctrl); return 0; @@ -1042,8 +1023,7 @@ static int vidioc_s_ctrl(struct file *file, void *priv, static int vidioc_g_parm(struct file *filp, void *priv, struct v4l2_streamparm *parm) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; struct v4l2_fract timeperframe = { .numerator = 1001 * go->fps_scale, .denominator = go->sensor_framerate, @@ -1061,8 +1041,7 @@ static int vidioc_g_parm(struct file *filp, void *priv, static int vidioc_s_parm(struct file *filp, void *priv, struct v4l2_streamparm *parm) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; unsigned int n, d; if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) @@ -1094,8 +1073,7 @@ static int vidioc_s_parm(struct file *filp, void *priv, static int vidioc_enum_framesizes(struct file *filp, void *priv, struct v4l2_frmsizeenum *fsize) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; /* Return -EINVAL, if it is a TV board */ if ((go->board_info->flags & GO7007_BOARD_HAS_TUNER) || @@ -1115,8 +1093,7 @@ static int vidioc_enum_framesizes(struct file *filp, void *priv, static int vidioc_enum_frameintervals(struct file *filp, void *priv, struct v4l2_frmivalenum *fival) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; /* Return -EINVAL, if it is a TV board */ if ((go->board_info->flags & GO7007_BOARD_HAS_TUNER) || @@ -1133,10 +1110,27 @@ static int vidioc_enum_frameintervals(struct file *filp, void *priv, return 0; } +static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *std) +{ + struct go7007 *go = ((struct go7007_file *) priv)->go; + + switch (go->standard) { + case GO7007_STD_NTSC: + *std = V4L2_STD_NTSC; + break; + case GO7007_STD_PAL: + *std = V4L2_STD_PAL; + break; + default: + return -EINVAL; + } + + return 0; +} + static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *std) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; if (go->streaming) return -EBUSY; @@ -1178,30 +1172,27 @@ static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *std) return 0; } -#if 0 - case VIDIOC_QUERYSTD: - { - v4l2_std_id *std = arg; +static int vidioc_querystd(struct file *file, void *priv, v4l2_std_id *std) +{ + struct go7007 *go = ((struct go7007_file *) priv)->go; - if ((go->board_info->flags & GO7007_BOARD_HAS_TUNER) && - go->input == go->board_info->num_inputs - 1) { - if (!go->i2c_adapter_online) - return -EIO; - i2c_clients_command(&go->i2c_adapter, - VIDIOC_QUERYSTD, arg); - } else if (go->board_info->sensor_flags & GO7007_SENSOR_TV) - *std = V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM; - else - *std = 0; - return 0; - } -#endif + if ((go->board_info->flags & GO7007_BOARD_HAS_TUNER) && + go->input == go->board_info->num_inputs - 1) { + if (!go->i2c_adapter_online) + return -EIO; + i2c_clients_command(&go->i2c_adapter, VIDIOC_QUERYSTD, std); + } else if (go->board_info->sensor_flags & GO7007_SENSOR_TV) + *std = V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM; + else + *std = 0; + + return 0; +} static int vidioc_enum_input(struct file *file, void *priv, struct v4l2_input *inp) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; if (inp->index >= go->board_info->num_inputs) return -EINVAL; @@ -1230,8 +1221,7 @@ static int vidioc_enum_input(struct file *file, void *priv, static int vidioc_g_input(struct file *file, void *priv, unsigned int *input) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; *input = go->input; @@ -1240,8 +1230,7 @@ static int vidioc_g_input(struct file *file, void *priv, unsigned int *input) static int vidioc_s_input(struct file *file, void *priv, unsigned int input) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; if (input >= go->board_info->num_inputs) return -EINVAL; @@ -1262,8 +1251,7 @@ static int vidioc_s_input(struct file *file, void *priv, unsigned int input) static int vidioc_g_tuner(struct file *file, void *priv, struct v4l2_tuner *t) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; if (!(go->board_info->flags & GO7007_BOARD_HAS_TUNER)) return -EINVAL; @@ -1281,8 +1269,7 @@ static int vidioc_g_tuner(struct file *file, void *priv, static int vidioc_s_tuner(struct file *file, void *priv, struct v4l2_tuner *t) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; if (!(go->board_info->flags & GO7007_BOARD_HAS_TUNER)) return -EINVAL; @@ -1308,8 +1295,7 @@ static int vidioc_s_tuner(struct file *file, void *priv, static int vidioc_g_frequency(struct file *file, void *priv, struct v4l2_frequency *f) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; if (!(go->board_info->flags & GO7007_BOARD_HAS_TUNER)) return -EINVAL; @@ -1324,8 +1310,7 @@ static int vidioc_g_frequency(struct file *file, void *priv, static int vidioc_s_frequency(struct file *file, void *priv, struct v4l2_frequency *f) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; if (!(go->board_info->flags & GO7007_BOARD_HAS_TUNER)) return -EINVAL; @@ -1340,8 +1325,7 @@ static int vidioc_s_frequency(struct file *file, void *priv, static int vidioc_cropcap(struct file *file, void *priv, struct v4l2_cropcap *cropcap) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; if (cropcap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; @@ -1385,8 +1369,7 @@ static int vidioc_cropcap(struct file *file, void *priv, static int vidioc_g_crop(struct file *file, void *priv, struct v4l2_crop *crop) { - struct go7007_file *gofh = priv; - struct go7007 *go = gofh->go; + struct go7007 *go = ((struct go7007_file *) priv)->go; if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; @@ -1734,18 +1717,18 @@ static int go7007_mmap(struct file *file, struct vm_area_struct *vma) return -EINVAL; /* only support VM_SHARED mapping */ if (vma->vm_end - vma->vm_start != GO7007_BUF_SIZE) return -EINVAL; /* must map exactly one full buffer */ - down(&gofh->lock); + mutex_lock(&gofh->lock); index = vma->vm_pgoff / GO7007_BUF_PAGES; if (index >= gofh->buf_count) { - up(&gofh->lock); + mutex_unlock(&gofh->lock); return -EINVAL; /* trying to map beyond requested buffers */ } if (index * GO7007_BUF_PAGES != vma->vm_pgoff) { - up(&gofh->lock); + mutex_unlock(&gofh->lock); return -EINVAL; /* offset is not aligned on buffer boundary */ } if (gofh->bufs[index].mapped > 0) { - up(&gofh->lock); + mutex_unlock(&gofh->lock); return -EBUSY; } gofh->bufs[index].mapped = 1; @@ -1754,7 +1737,7 @@ static int go7007_mmap(struct file *file, struct vm_area_struct *vma) vma->vm_flags |= VM_DONTEXPAND; vma->vm_flags &= ~VM_IO; vma->vm_private_data = &gofh->bufs[index]; - up(&gofh->lock); + mutex_unlock(&gofh->lock); return 0; } @@ -1801,7 +1784,9 @@ static const struct v4l2_ioctl_ops video_ioctl_ops = { .vidioc_querybuf = vidioc_querybuf, .vidioc_qbuf = vidioc_qbuf, .vidioc_dqbuf = vidioc_dqbuf, + .vidioc_g_std = vidioc_g_std, .vidioc_s_std = vidioc_s_std, + .vidioc_querystd = vidioc_querystd, .vidioc_enum_input = vidioc_enum_input, .vidioc_g_input = vidioc_g_input, .vidioc_s_input = vidioc_s_input, @@ -1862,7 +1847,7 @@ void go7007_v4l2_remove(struct go7007 *go) { unsigned long flags; - down(&go->hw_lock); + mutex_lock(&go->hw_lock); if (go->streaming) { go->streaming = 0; go7007_stream_stop(go); @@ -1870,7 +1855,7 @@ void go7007_v4l2_remove(struct go7007 *go) abort_queued(go); spin_unlock_irqrestore(&go->spinlock, flags); } - up(&go->hw_lock); + mutex_unlock(&go->hw_lock); if (go->video_dev) video_unregister_device(go->video_dev); } diff --git a/drivers/staging/go7007/go7007.txt b/drivers/staging/go7007/go7007.txt index 1c2907c1dc81..06a76da32128 100644 --- a/drivers/staging/go7007/go7007.txt +++ b/drivers/staging/go7007/go7007.txt @@ -2,7 +2,7 @@ This is a driver for the WIS GO7007SB multi-format video encoder. Pete Eberlein -The driver was originally released under the GPL and is currently hosted at: +The driver was orignally released under the GPL and is currently hosted at: http://nikosapi.org/wiki/index.php/WIS_Go7007_Linux_driver The go7007 firmware can be acquired from the package on the site above. @@ -24,10 +24,10 @@ These should be used instead of the non-standard GO7007 ioctls described below. -The README files from the original package appears below: +The README files from the orignal package appear below: --------------------------------------------------------------------------- - WIS GO7007SB Public Linux Driver + WIS GO7007SB Public Linux Driver --------------------------------------------------------------------------- @@ -78,23 +78,23 @@ All vendor-built kernels should already be configured properly. However, for custom-built kernels, the following options need to be enabled in the kernel as built-in or modules: - CONFIG_HOTPLUG - Support for hot-pluggable devices - CONFIG_MODULES - Enable loadable module support - CONFIG_KMOD - Automatic kernel module loading - CONFIG_FW_LOADER - Hotplug firmware loading support - CONFIG_I2C - I2C support - CONFIG_VIDEO_DEV - Video For Linux - CONFIG_SOUND - Sound card support - CONFIG_SND - Advanced Linux Sound Architecture - CONFIG_USB - Support for Host-side USB - CONFIG_USB_DEVICEFS - USB device filesystem - CONFIG_USB_EHCI_HCD - EHCI HCD (USB 2.0) support + CONFIG_HOTPLUG - Support for hot-pluggable devices + CONFIG_MODULES - Enable loadable module support + CONFIG_KMOD - Automatic kernel module loading + CONFIG_FW_LOADER - Hotplug firmware loading support + CONFIG_I2C - I2C support + CONFIG_VIDEO_DEV - Video For Linux + CONFIG_SOUND - Sound card support + CONFIG_SND - Advanced Linux Sound Architecture + CONFIG_USB - Support for Host-side USB + CONFIG_USB_DEVICEFS - USB device filesystem + CONFIG_USB_EHCI_HCD - EHCI HCD (USB 2.0) support Additionally, to use the example application, the following options need to be enabled in the ALSA section: - CONFIG_SND_MIXER_OSS - OSS Mixer API - CONFIG_SND_PCM_OSS - OSS PCM (digital audio) API + CONFIG_SND_MIXER_OSS - OSS Mixer API + CONFIG_SND_PCM_OSS - OSS PCM (digital audio) API The hotplug scripts, along with the fxload utility, must also be installed. These scripts can be obtained from . @@ -107,7 +107,7 @@ fxload and for loading firmware into the driver using the firmware agent. Most users should be able to compile the driver by simply running: - $ make + $ make in the top-level directory of the driver kit. First the kernel modules will be built, followed by the example applications. @@ -117,12 +117,12 @@ currently-running kernel, or if the module should be built for a kernel other than the currently-running kernel, an additional parameter will need to be passed to make to specify the appropriate kernel source directory: - $ make KERNELSRC=/usr/src/linux-2.6.10-custom3 + $ make KERNELSRC=/usr/src/linux-2.6.10-custom3 Once the compile completes, the driver and firmware files should be installed by running: - $ make install + $ make install The kernel modules will be placed in "/lib/modules//extra" and the firmware files will be placed in the appropriate hotplug firmware @@ -200,7 +200,7 @@ stereo audio broadcasts on the A2 carrier. To verify that the configuration has been placed in the correct location, execute: - $ modprobe -c | grep wis-sony-tuner + $ modprobe -c | grep wis-sony-tuner If the configuration line appears, then modprobe will pass the parameters correctly the next time the wis-sony-tuner module is loaded into the @@ -223,7 +223,7 @@ This application will auto-detect the V4L2 and ALSA/OSS device names of the hardware and will record video and audio to an AVI file for a specified number of seconds. For example: - $ apps/gorecord -duration 60 capture.avi + $ apps/gorecord -duration 60 capture.avi If this application does not successfully record an AVI file, the error messages produced by gorecord and recorded in the system log (usually in @@ -286,35 +286,35 @@ features of the GO7007SB encoder, which are described below: Fields in struct go7007_comp_params: - __u32 The maximum number of frames in each - gop_size Group Of Pictures; i.e. the maximum - number of frames minus one between - each key frame. + __u32 The maximum number of frames in each + gop_size Group Of Pictures; i.e. the maximum + number of frames minus one between + each key frame. - __u32 The maximum number of sequential - max_b_frames bidirectionally-predicted frames. - (B-frames are not yet supported.) + __u32 The maximum number of sequential + max_b_frames bidirectionally-predicted frames. + (B-frames are not yet supported.) - enum go7007_aspect_ratio The aspect ratio to be encoded in the - aspect_ratio meta-data of the compressed format. + enum go7007_aspect_ratio The aspect ratio to be encoded in the + aspect_ratio meta-data of the compressed format. - Choices are: - GO7007_ASPECT_RATIO_1_1 - GO7007_ASPECT_RATIO_4_3_NTSC - GO7007_ASPECT_RATIO_4_3_PAL - GO7007_ASPECT_RATIO_16_9_NTSC - GO7007_ASPECT_RATIO_16_9_PAL + Choices are: + GO7007_ASPECT_RATIO_1_1 + GO7007_ASPECT_RATIO_4_3_NTSC + GO7007_ASPECT_RATIO_4_3_PAL + GO7007_ASPECT_RATIO_16_9_NTSC + GO7007_ASPECT_RATIO_16_9_PAL - __u32 Bit-wise OR of control flags (below) - flags + __u32 Bit-wise OR of control flags (below) + flags Flags in struct go7007_comp_params: - GO7007_COMP_CLOSED_GOP Only produce self-contained GOPs, used - to produce streams appropriate for - random seeking. + GO7007_COMP_CLOSED_GOP Only produce self-contained GOPs, used + to produce streams appropriate for + random seeking. - GO7007_COMP_OMIT_SEQ_HEADER Omit the stream sequence header. + GO7007_COMP_OMIT_SEQ_HEADER Omit the stream sequence header. GO7007IOC_S_MPEG_PARAMS, GO7007IOC_G_MPEG_PARAMS @@ -337,56 +337,56 @@ features of the GO7007SB encoder, which are described below: Fields in struct go7007_mpeg_params: - enum go7007_mpeg_video_standard - mpeg_video_standard The MPEG video standard in which to - compress the video. - - Choices are: - GO7007_MPEG_VIDEO_MPEG1 - GO7007_MPEG_VIDEO_MPEG2 - GO7007_MPEG_VIDEO_MPEG4 - - __u32 Bit-wise OR of control flags (below) - flags - - __u32 The profile and level indication to be - pali stored in the sequence header. This - is only used as an indicator to the - decoder, and does not affect the MPEG - features used in the video stream. - Not valid for MPEG1. - - Choices for MPEG2 are: - GO7007_MPEG2_PROFILE_MAIN_MAIN - - Choices for MPEG4 are: - GO7007_MPEG4_PROFILE_S_L0 - GO7007_MPEG4_PROFILE_S_L1 - GO7007_MPEG4_PROFILE_S_L2 - GO7007_MPEG4_PROFILE_S_L3 - GO7007_MPEG4_PROFILE_ARTS_L1 - GO7007_MPEG4_PROFILE_ARTS_L2 - GO7007_MPEG4_PROFILE_ARTS_L3 - GO7007_MPEG4_PROFILE_ARTS_L4 - GO7007_MPEG4_PROFILE_AS_L0 - GO7007_MPEG4_PROFILE_AS_L1 - GO7007_MPEG4_PROFILE_AS_L2 - GO7007_MPEG4_PROFILE_AS_L3 - GO7007_MPEG4_PROFILE_AS_L4 - GO7007_MPEG4_PROFILE_AS_L5 + enum go7007_mpeg_video_standard + mpeg_video_standard The MPEG video standard in which to + compress the video. + + Choices are: + GO7007_MPEG_VIDEO_MPEG1 + GO7007_MPEG_VIDEO_MPEG2 + GO7007_MPEG_VIDEO_MPEG4 + + __u32 Bit-wise OR of control flags (below) + flags + + __u32 The profile and level indication to be + pali stored in the sequence header. This + is only used as an indicator to the + decoder, and does not affect the MPEG + features used in the video stream. + Not valid for MPEG1. + + Choices for MPEG2 are: + GO7007_MPEG2_PROFILE_MAIN_MAIN + + Choices for MPEG4 are: + GO7007_MPEG4_PROFILE_S_L0 + GO7007_MPEG4_PROFILE_S_L1 + GO7007_MPEG4_PROFILE_S_L2 + GO7007_MPEG4_PROFILE_S_L3 + GO7007_MPEG4_PROFILE_ARTS_L1 + GO7007_MPEG4_PROFILE_ARTS_L2 + GO7007_MPEG4_PROFILE_ARTS_L3 + GO7007_MPEG4_PROFILE_ARTS_L4 + GO7007_MPEG4_PROFILE_AS_L0 + GO7007_MPEG4_PROFILE_AS_L1 + GO7007_MPEG4_PROFILE_AS_L2 + GO7007_MPEG4_PROFILE_AS_L3 + GO7007_MPEG4_PROFILE_AS_L4 + GO7007_MPEG4_PROFILE_AS_L5 Flags in struct go7007_mpeg_params: - GO7007_MPEG_FORCE_DVD_MODE Force all compression parameters and - bitrate control settings to comply - with DVD MPEG2 stream requirements. - This overrides most compression and - bitrate settings! + GO7007_MPEG_FORCE_DVD_MODE Force all compression parameters and + bitrate control settings to comply + with DVD MPEG2 stream requirements. + This overrides most compression and + bitrate settings! - GO7007_MPEG_OMIT_GOP_HEADER Omit the GOP header. + GO7007_MPEG_OMIT_GOP_HEADER Omit the GOP header. - GO7007_MPEG_REPEAT_SEQHEADER Repeat the MPEG sequence header at - the start of each GOP. + GO7007_MPEG_REPEAT_SEQHEADER Repeat the MPEG sequence header at + the start of each GOP. GO7007IOC_S_BITRATE, GO7007IOC_G_BITRATE @@ -404,7 +404,7 @@ features of the GO7007SB encoder, which are described below: ---------------------------------------------------------------------------- - Installing the WIS PCI Voyager Driver + Installing the WIS PCI Voyager Driver --------------------------------------------------------------------------- The WIS PCI Voyager driver requires several patches to the Linux 2.6.11.x diff --git a/drivers/staging/go7007/s2250-board.c b/drivers/staging/go7007/s2250-board.c index 1706fbf06847..8c85a9c3665a 100644 --- a/drivers/staging/go7007/s2250-board.c +++ b/drivers/staging/go7007/s2250-board.c @@ -21,12 +21,10 @@ #include #include #include +#include "s2250-loader.h" #include "go7007-priv.h" #include "wis-i2c.h" -extern int s2250loader_init(void); -extern void s2250loader_cleanup(void); - #define TLV320_ADDRESS 0x34 #define VPX322_ADDR_ANALOGCONTROL1 0x02 #define VPX322_ADDR_BRIGHTNESS0 0x0127 @@ -34,7 +32,7 @@ extern void s2250loader_cleanup(void); #define VPX322_ADDR_CONTRAST0 0x0128 #define VPX322_ADDR_CONTRAST1 0x0132 #define VPX322_ADDR_HUE 0x00dc -#define VPX322_ADDR_SAT 0x0030 +#define VPX322_ADDR_SAT 0x0030 struct go7007_usb_board { unsigned int flags; @@ -43,7 +41,7 @@ struct go7007_usb_board { struct go7007_usb { struct go7007_usb_board *board; - struct semaphore i2c_lock; + struct mutex i2c_lock; struct usb_device *usbdev; struct urb *video_urbs[8]; struct urb *audio_urbs[8]; @@ -114,7 +112,7 @@ static u16 vid_regs_fp_pal[] = }; struct s2250 { - int std; + v4l2_std_id std; int input; int brightness; int contrast; @@ -165,7 +163,7 @@ static int write_reg(struct i2c_client *client, u8 reg, u8 value) return -ENOMEM; usb = go->hpi_context; - if (down_interruptible(&usb->i2c_lock) != 0) { + if (mutex_lock_interruptible(&usb->i2c_lock) != 0) { printk(KERN_INFO "i2c lock failed\n"); kfree(buf); return -EINTR; @@ -175,7 +173,7 @@ static int write_reg(struct i2c_client *client, u8 reg, u8 value) buf, 16, 1); - up(&usb->i2c_lock); + mutex_unlock(&usb->i2c_lock); kfree(buf); return rc; } @@ -203,19 +201,23 @@ static int write_reg_fp(struct i2c_client *client, u16 addr, u16 val) memset(buf, 0xcd, 6); usb = go->hpi_context; - if (down_interruptible(&usb->i2c_lock) != 0) { + if (mutex_lock_interruptible(&usb->i2c_lock) != 0) { printk(KERN_INFO "i2c lock failed\n"); + kfree(buf); return -EINTR; } - if (go7007_usb_vendor_request(go, 0x57, addr, val, buf, 16, 1) < 0) + if (go7007_usb_vendor_request(go, 0x57, addr, val, buf, 16, 1) < 0) { + kfree(buf); return -EFAULT; + } - up(&usb->i2c_lock); + mutex_unlock(&usb->i2c_lock); if (buf[0] == 0) { unsigned int subaddr, val_read; subaddr = (buf[4] << 8) + buf[5]; val_read = (buf[2] << 8) + buf[3]; + kfree(buf); if (val_read != val) { printk(KERN_INFO "invalid fp write %x %x\n", val_read, val); @@ -226,8 +228,10 @@ static int write_reg_fp(struct i2c_client *client, u16 addr, u16 val) subaddr, addr); return -EFAULT; } - } else + } else { + kfree(buf); return -EFAULT; + } /* save last 12b value */ if (addr == 0x12b) @@ -236,6 +240,45 @@ static int write_reg_fp(struct i2c_client *client, u16 addr, u16 val) return 0; } +static int read_reg_fp(struct i2c_client *client, u16 addr, u16 *val) +{ + struct go7007 *go = i2c_get_adapdata(client->adapter); + struct go7007_usb *usb; + u8 *buf; + + if (go == NULL) + return -ENODEV; + + if (go->status == STATUS_SHUTDOWN) + return -EBUSY; + + buf = kzalloc(16, GFP_KERNEL); + + if (buf == NULL) + return -ENOMEM; + + + + memset(buf, 0xcd, 6); + usb = go->hpi_context; + if (down_interruptible(&usb->i2c_lock) != 0) { + printk(KERN_INFO "i2c lock failed\n"); + kfree(buf); + return -EINTR; + } + if (go7007_usb_vendor_request(go, 0x58, addr, 0, buf, 16, 1) < 0) { + kfree(buf); + return -EFAULT; + } + up(&usb->i2c_lock); + + *val = (buf[0] << 8) | buf[1]; + kfree(buf); + + return 0; +} + + static int write_regs(struct i2c_client *client, u8 *regs) { int i; @@ -350,14 +393,42 @@ static int s2250_command(struct i2c_client *client, { struct v4l2_control *ctrl = arg; int value1; + u16 oldvalue; switch (ctrl->id) { case V4L2_CID_BRIGHTNESS: - printk(KERN_INFO "s2250: future setting\n"); - return -EINVAL; + if (ctrl->value > 100) + dec->brightness = 100; + else if (ctrl->value < 0) + dec->brightness = 0; + else + dec->brightness = ctrl->value; + value1 = (dec->brightness - 50) * 255 / 100; + read_reg_fp(client, VPX322_ADDR_BRIGHTNESS0, &oldvalue); + write_reg_fp(client, VPX322_ADDR_BRIGHTNESS0, + value1 | (oldvalue & ~0xff)); + read_reg_fp(client, VPX322_ADDR_BRIGHTNESS1, &oldvalue); + write_reg_fp(client, VPX322_ADDR_BRIGHTNESS1, + value1 | (oldvalue & ~0xff)); + write_reg_fp(client, 0x140, 0x60); + break; case V4L2_CID_CONTRAST: - printk(KERN_INFO "s2250: future setting\n"); - return -EINVAL; + if (ctrl->value > 100) + dec->contrast = 100; + else if (ctrl->value < 0) + dec->contrast = 0; + else + dec->contrast = ctrl->value; + value1 = dec->contrast * 0x40 / 100; + if (value1 > 0x3f) + value1 = 0x3f; /* max */ + read_reg_fp(client, VPX322_ADDR_CONTRAST0, &oldvalue); + write_reg_fp(client, VPX322_ADDR_CONTRAST0, + value1 | (oldvalue & ~0x3f)); + read_reg_fp(client, VPX322_ADDR_CONTRAST1, &oldvalue); + write_reg_fp(client, VPX322_ADDR_CONTRAST1, + value1 | (oldvalue & ~0x3f)); + write_reg_fp(client, 0x140, 0x60); break; case V4L2_CID_SATURATION: if (ctrl->value > 127) @@ -541,7 +612,7 @@ static int s2250_probe(struct i2c_client *client, dec->audio_input = 0; write_reg(client, 0x08, 0x02); /* Line In */ - if (down_interruptible(&usb->i2c_lock) == 0) { + if (mutex_lock_interruptible(&usb->i2c_lock) == 0) { data = kzalloc(16, GFP_KERNEL); if (data != NULL) { int rc; @@ -560,7 +631,7 @@ static int s2250_probe(struct i2c_client *client, } kfree(data); } - up(&usb->i2c_lock); + mutex_unlock(&usb->i2c_lock); } printk("s2250: initialized successfully\n"); diff --git a/drivers/staging/go7007/s2250-loader.c b/drivers/staging/go7007/s2250-loader.c index bb22347af60e..d7bf82983274 100644 --- a/drivers/staging/go7007/s2250-loader.c +++ b/drivers/staging/go7007/s2250-loader.c @@ -35,7 +35,7 @@ typedef struct device_extension_s { #define MAX_DEVICES 256 static pdevice_extension_t s2250_dev_table[MAX_DEVICES]; -static DECLARE_MUTEX(s2250_dev_table_mutex); +static DEFINE_MUTEX(s2250_dev_table_mutex); #define to_s2250loader_dev_common(d) container_of(d, device_extension_t, kref) static void s2250loader_delete(struct kref *kref) @@ -67,7 +67,7 @@ static int s2250loader_probe(struct usb_interface *interface, printk(KERN_ERR "can't handle multiple config\n"); return -1; } - down(&s2250_dev_table_mutex); + mutex_lock(&s2250_dev_table_mutex); for (minor = 0; minor < MAX_DEVICES; minor++) { if (s2250_dev_table[minor] == NULL) @@ -96,7 +96,7 @@ static int s2250loader_probe(struct usb_interface *interface, kref_init(&(s->kref)); - up(&s2250_dev_table_mutex); + mutex_unlock(&s2250_dev_table_mutex); if (request_firmware(&fw, S2250_LOADER_FIRMWARE, &usbdev->dev)) { printk(KERN_ERR @@ -128,7 +128,7 @@ static int s2250loader_probe(struct usb_interface *interface, return 0; failed: - up(&s2250_dev_table_mutex); + mutex_unlock(&s2250_dev_table_mutex); failed2: if (s) kref_put(&(s->kref), s2250loader_delete); diff --git a/drivers/staging/go7007/snd-go7007.c b/drivers/staging/go7007/snd-go7007.c index cd19be6c00e0..03c4dfc138a1 100644 --- a/drivers/staging/go7007/snd-go7007.c +++ b/drivers/staging/go7007/snd-go7007.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/staging/go7007/wis-tw9903.c b/drivers/staging/go7007/wis-tw9903.c index 6c3427bb6f4c..506dca6e942e 100644 --- a/drivers/staging/go7007/wis-tw9903.c +++ b/drivers/staging/go7007/wis-tw9903.c @@ -111,7 +111,8 @@ static int wis_tw9903_command(struct i2c_client *client, i2c_smbus_write_byte_data(client, 0x02, 0x40 | (*input << 1)); break; } -#if 0 /* The scaler on this thing seems to be horribly broken */ +#if 0 + /* The scaler on this thing seems to be horribly broken */ case DECODER_SET_RESOLUTION: { struct video_decoder_resolution *res = arg; diff --git a/drivers/staging/iio/industrialio-core.c b/drivers/staging/iio/industrialio-core.c index 660a9c1a1f3f..1fa18f255814 100644 --- a/drivers/staging/iio/industrialio-core.c +++ b/drivers/staging/iio/industrialio-core.c @@ -39,14 +39,14 @@ dev_t iio_devt; EXPORT_SYMBOL(iio_devt); #define IIO_DEV_MAX 256 -static char *iio_nodename(struct device *dev) +static char *iio_devnode(struct device *dev, mode_t *mode) { return kasprintf(GFP_KERNEL, "iio/%s", dev_name(dev)); } struct class iio_class = { .name = "iio", - .nodename = iio_nodename, + .devnode = iio_devnode, }; EXPORT_SYMBOL(iio_class); diff --git a/firmware/Makefile b/firmware/Makefile index ffe2663d49f2..5ea80b19785b 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -46,6 +46,22 @@ fw-shipped-$(CONFIG_CHELSIO_T3) += cxgb3/t3b_psram-1.1.0.bin \ cxgb3/ael2005_opt_edc.bin \ cxgb3/ael2005_twx_edc.bin \ cxgb3/ael2020_twx_edc.bin +fw-shipped-$(CONFIG_DRM_MGA) += matrox/g200_warp.fw matrox/g400_warp.fw +fw-shipped-$(CONFIG_DRM_R128) += r128/r128_cce.bin +fw-shipped-$(CONFIG_DRM_RADEON) += radeon/R100_cp.bin radeon/R200_cp.bin \ + radeon/R300_cp.bin radeon/R420_cp.bin \ + radeon/RS690_cp.bin radeon/RS600_cp.bin \ + radeon/R520_cp.bin \ + radeon/R600_pfp.bin radeon/R600_me.bin \ + radeon/RV610_pfp.bin radeon/RV610_me.bin \ + radeon/RV630_pfp.bin radeon/RV630_me.bin \ + radeon/RV620_pfp.bin radeon/RV620_me.bin \ + radeon/RV635_pfp.bin radeon/RV635_me.bin \ + radeon/RV670_pfp.bin radeon/RV670_me.bin \ + radeon/RS780_pfp.bin radeon/RS780_me.bin \ + radeon/RV770_pfp.bin radeon/RV770_me.bin \ + radeon/RV730_pfp.bin radeon/RV730_me.bin \ + radeon/RV710_pfp.bin radeon/RV710_me.bin fw-shipped-$(CONFIG_DVB_AV7110) += av7110/bootcode.bin fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin fw-shipped-$(CONFIG_E100) += e100/d101m_ucode.bin e100/d101s_ucode.bin \ diff --git a/firmware/WHENCE b/firmware/WHENCE index 82db5256a4e5..3f8c4f6bc43f 100644 --- a/firmware/WHENCE +++ b/firmware/WHENCE @@ -727,3 +727,124 @@ Found in hex form in kernel source, with the following comment: Copyright (c) 1998-2002 by Paul Davis -------------------------------------------------------------------------- + +Driver: mga - Matrox G200/G400/G550 + +File: matrox/g200_warp.fw +File: matrox/g400_warp.fw + +Licence: + +Copyright 1999 Matrox Graphics Inc. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +MATROX GRAPHICS INC., OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Found in hex form in kernel source. + +-------------------------------------------------------------------------- + +Driver: r128 - ATI Rage 128 + +File: r128/r128_cce.bin + +Licence: + +Copyright 2000 Advanced Micro Devices, Inc. + + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + +Found in decimal form in kernel source. + +-------------------------------------------------------------------------- + +Driver: radeon - ATI Radeon + +File: radeon/R100_cp.bin +File: radeon/R200_cp.bin +File: radeon/R300_cp.bin +File: radeon/R420_cp.bin +File: radeon/RS600_cp.bin +File: radeon/RS690_cp.bin +File: radeon/R520_cp.bin +File: radeon/R600_pfp.bin +File: radeon/R600_me.bin +File: radeon/RV610_pfp.bin +File: radeon/RV610_me.bin +File: radeon/RV630_pfp.bin +File: radeon/RV630_me.bin +File: radeon/RV620_pfp.bin +File: radeon/RV620_me.bin +File: radeon/RV635_pfp.bin +File: radeon/RV635_me.bin +File: radeon/RV670_pfp.bin +File: radeon/RV670_me.bin +File: radeon/RS780_pfp.bin +File: radeon/RS780_me.bin +File: radeon/RV770_pfp.bin +File: radeon/RV770_me.bin +File: radeon/RV730_pfp.bin +File: radeon/RV730_me.bin +File: radeon/RV710_pfp.bin +File: radeon/RV710_me.bin + +Licence: + + * Copyright 2007-2009 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Found in hex form in kernel source. + +-------------------------------------------------------------------------- diff --git a/firmware/matrox/g200_warp.H16 b/firmware/matrox/g200_warp.H16 new file mode 100644 index 000000000000..5064b6f01bb4 --- /dev/null +++ b/firmware/matrox/g200_warp.H16 @@ -0,0 +1,28 @@ +/* + * WARP pipes are named according to the functions they perform, where + * + * - T stands for computation of texture stage 0 + * - T2 stands for computation of both texture stage 0 and texture stage 1 + * - G stands for computation of triangle intensity (Gouraud interpolation) + * - Z stands for computation of Z buffer interpolation + * - S stands for computation of specular highlight + * - A stands for computation of the alpha channel + * - F stands for computation of vertex fog interpolation + */ +/* TGZ */ +:04B8000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E9728007EA241F20E9154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E2608015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E803800AEA17C12BBD008000E8008000E8B3689725008000E833C033AF3C274FE9573920E9281960EC2B3220E91D3B20E9B30500E0162820E9233B33AD1E2B20E91C8020E9573620E90080A0E94040D8ECFF80C0E990E200E085FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E884FF0AEA008000E8C941C8EC42E100E082FF20EA008000E8008000E8008000E8C840C0EC008000E87FFF20EA008000E8008000E8008000E871 +/* TGZF */ +:0548000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E97F8007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E26B8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E80D211AB6052131B603802AEA17C12BBD0D2005202FC021C6B3689725008000E833C033AF3C274FE91750569F008000E8370F5C9F00E02F20008000E8281960ECB30500E0008000E8233B33AD008000E8172617DF35174FE9008000E8008000E8008000E839374FE92F2F17AF008000E8008000E8008000E831804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E078FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E877FF0AEA008000E8C941C8EC42E100E075FF20EA008000E8008000E8008000E8C840C0EC008000E872FF20EA008000E8008000E8008000E8BB +/* TGZA */ +:04E80000000098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E97D8007EA241F20E9154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E26B8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D444CB6254454B603802AEA17C12BBD2D20252007C044C6B3689725008000E833C033AF3C274FE91F62579F008000E83F3D5D9F00E00720008000E8281960ECB30500E0008000E8233B33AD008000E81F261FDF9D1F4FE9008000E8008000E8008000E89E3F4FE907071FAF008000E8008000E8008000E89C804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E07AFF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E879FF0AEA008000E8C941C8EC42E100E077FF20EA008000E8008000E8008000E8C840C0EC008000E874FF20EA008000E8008000E8008000E8D9 +/* TGZAF */ +:0568000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E9838007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E26F8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E80D211AB6052131B62D444CB6254454B603802AEA17C12BBD0D2005202FC021C6B3689725008000E833C033AF3C274FE900E0252007C044C61750569F00E02D20370F5C9F00E02F201F62579F00E007203F3D5D9F008000E8008000E8281960ECB30500E0172617DF233B33AD35174FE91F261FDF9D1F4FE99E3F4FE939374FE92F2F17AF008000E807071FAF008000E831804FE9008000E89C804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E074FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E873FF0AEA008000E8C941C8EC42E100E071FF20EA008000E8008000E8008000E8C840C0EC008000E86EFF20EA008000E8008000E8008000E830 +/* TGZS */ +:05C0000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E98B8007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E2778015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D211AB0252131B00D211AB2052131B203802AEA17C12BBD2D20252005200D20B3689725008000E833C033AF2FC021C01642569F3C274FE91E62579F008000E8252131B42D211AB43F2F5D9F008000E8330500E0281960EC370F5C9F00E02F20233B33AD1E261EDFA71E4FE9172616DF2D2000E0A83F4FE92F2F1EAF252000E0A4164FE90FC021C2A6804FE91F62579F3F2F5D9F00E08F20A5374FE90F170FAF06C021C4008000E8008000E8A3804FE9062000E01F261FDFA11F4FE9A23F4FE9008000E8008000E806061FAF008000E8008000E8008000E8A0804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E06CFF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E86BFF0AEA008000E8C941C8EC42E100E069FF20EA008000E8008000E8008000E8C840C0EC008000E866FF20EA008000E8008000E8008000E85C +/* TGZSF */ +:05E0000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E98F8007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E27B8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D211AB0252131B00D211AB2052131B203802AEA17C12BBD2D20252005200D20B3689725008000E833C033AF2FC021C01642569F3C274FE91E62579F008000E8252131B42D211AB43F2F5D9F008000E8330500E0281960EC0D211AB6052131B6370F5C9F00E02F20233B33AD1E261EDFA71E4FE9172616DF2D2000E0A83F4FE92F2F1EAF252000E0A4164FE90FC021C2A6804FE91F62579F0D2005202FC021C63F2F5D9F00E00F201750569FA5374FE906C021C40F170FAF370F5C9F008000E82F2000E0A3804FE9062000E01F261FDF172617DF35174FE9A11F4FE9A23F4FE906061FAF39374FE92F2F17AF008000E8A0804FE9008000E831804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E068FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E867FF0AEA008000E8C941C8EC42E100E065FF20EA008000E8008000E8008000E8C840C0EC008000E862FF20EA008000E8008000E8008000E8F9 +/* TGZSA */ +:05E0000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E98F8007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E27B8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D211AB0252131B00D211AB2052131B203802AEA17C12BBD2D20252005200D20B3689725008000E833C033AF2FC021C01642569F3C274FE91E62579F008000E8252131B42D211AB43F2F5D9F008000E8330500E0281960EC0D444CB6054454B6370F5C9F00E02F20233B33AD1E261EDFA71E4FE9172616DF2D2000E0A83F4FE92F2F1EAF252000E0A4164FE90FC021C2A6804FE91F62579F0D200520008000E83F2F5D9F00E00F201750569FA5374FE906C021C40F170FAF370F5C9F008000E82FC044C6A3804FE9062000E01F261FDF172617DF9D174FE9A11F4FE9A23F4FE906061FAF00E0AF209E374FE92F172FAFA0804FE9008000E8008000E89C804FE9008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E068FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E867FF0AEA008000E8C941C8EC42E100E065FF20EA008000E8008000E8008000E8C840C0EC008000E862FF20EA008000E8008000E8008000E883 +/* TGZAF */ +:05B8000000008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E9948007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E2808015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D211AB0252131B00D211AB2052131B203802AEA17C12BBD2D20252005200D20B3689725008000E833C033AF2FC021C01642569F3C274FE91E62579F008000E8252131B42D211AB43F2F5D9F008000E8330500E0281960EC0D211AB6052131B6370F5C9F00E02F20233B33AD1E261EDFA71E4FE9172616DF2D2000E0A83F4FE92F2F1EAF252000E0A4164FE90FC021C2A6804FE91F62579F0D2005202FC021C62D444CB6254454B63F2F5D9F00E00F202D20252007C044C61750569FA5374FE906C021C40F170FAF370F5C9F008000E81E62579F008000E83E3D5D9F00E007202F2000E0A30F4FE9062000E01F261FDF172617DFA11F4FE91E261EDF9D1E4FE935174FE9A23F4FE906061FAF39374FE92F2F17AF07071EAFA0804FE99E3E4FE931804FE99C804FE9008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E063FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E862FF0AEA008000E8C941C8EC42E100E060FF20EA008000E8008000E8008000E8C840C0EC008000E85DFF20EA008000E8008000E8008000E8D8 +:0000000001FF diff --git a/firmware/matrox/g400_warp.H16 b/firmware/matrox/g400_warp.H16 new file mode 100644 index 000000000000..b432d1074d8d --- /dev/null +++ b/firmware/matrox/g400_warp.H16 @@ -0,0 +1,44 @@ +/* + * WARP pipes are named according to the functions they perform, where + * + * - T stands for computation of texture stage 0 + * - T2 stands for computation of both texture stage 0 and texture stage 1 + * - G stands for computation of triangle intensity (Gouraud interpolation) + * - Z stands for computation of Z buffer interpolation + * - S stands for computation of specular highlight + * - A stands for computation of the alpha channel + * - F stands for computation of vertex fog interpolation + */ +/* TGZ */ +:0338000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC31003900588015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF4A8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF32322DDF22222DDF12122DDF3A3A2DDF473747DF573D57DF3DCF74C037CF74C431532F9F348020E939E52C9F3C3D20E90A444CB0024454B02A444CB21A4454B21D803AEA0A2002203DCF74C22A201A2030502E9F32315FE938212C9F33395FE931532F9F008000E82A444CB41A4454B439E52C9F383D20E988735EE92A201A202A464EBF1A4656BF31532F9F3E304FE939E52C9F3F384FE90A474FBF024757BF31532F9F3A314FE939E52C9F3B394FE92A434BBF1A4353BF30502E9F36314FE938212C9F37394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9AFFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFD6FF20EA008000E84E334ECF573B57CF9DFF20EA57C0BFEA0080A0E90000D8EC59 +/* TGZF */ +:0360000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039005D8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF4F8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF32322DDF22222DDF12122DDF3A3A2DDF473747DF573D57DF3DCF74C037CF74C439E52C9F348020E931532F9F008000E888735EE9008000E827CF75C63C3D20E90A444CB0024454B02A444CB21A4454B220803AEA0A2002203DCF74C22A201A2030502E9F32315FE938212C9F33395FE931532F9F312720E90A444CB4024454B42A454DB61A4555B639E52C9F383D20E90A2002202A201A200A474FBF024757BF30502E9F3E304FE938212C9F3F384FE92A464EBF1A4656BF31532F9F3A314FE939E52C9F3B394FE931532F9F36304FE939E52C9F37384FE92A434BBF1A4353BF30502E9F35314FE938212C9F39394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9AAFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFD3FF20EA008000E84E334ECF573B57CF98FF20EA57C0BFEA0080A0E90000D8EC90 +/* TGZA */ +:0358000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039005C8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF4E8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF32322DDF22222DDF12122DDF3A3A2DDF473747DF573D57DF3DCF74C037CF74C431532F9F348020E939E52C9F3C3D20E927CF74C63DCF74C20A444CB0024454B02A444CB21A4454B220803AEA0A20022088735EE92A201A2030502E9F32315FE938212C9F33395FE931532F9F9C2720E90A444CB4024454B42A444CB61A4454B639E52C9F383D20E90A2002202A201A200A474FBF024757BF30502E9F3E304FE938212C9F3F384FE92A464EBF1A4656BF31532F9F3A314FE939E52C9F3B394FE931532F9F36304FE939E52C9F37384FE92A434BBF1A4353BF30502E9F9D314FE938212C9F9E394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9ABFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFD3FF20EA008000E84E334ECF573B57CF99FF20EA57C0BFEA0080A0E90000D8EC35 +/* TGZAF */ +:0380000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC31003900618015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF538007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF32322DDF22222DDF12122DDF3A3A2DDF473747DF573D57DF3DCF74C037CF74C40A444CB0024454B031532F9F343720E939E52C9F3C3D20E92A444CB21A4454B226803AEA0A20022088735EE92A201A203DCF74C227CF74C630502E9F32315FE938212C9F33395FE931532F9F9C2720E90A444CB4024454B42A444CB61A4454B639E52C9F383D20E90A2002202A201A203DCF75C6008000E830502E9F3E304FE938212C9F3F384FE90A454DB6024555B631532F9F3A314FE939E52C9F3B394FE9313D20E90A2002202A464EBF1A4656BF0A474FBF024757BF30502E9F36304FE938212C9F37384FE931532F9F9D314FE939E52C9F9E394FE92A434BBF1A4353BF30502E9F35304FE938212C9F39384FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9A6FF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFCDFF20EA008000E84E334ECF573B57CF94FF20EA57C0BFEA0080A0E90000D8EC89 +/* TGZS */ +:03A0000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC31003900658015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF578007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF473747DF573D57DF32322DDF22222DDF12122DDF3A3A2DDF27CF74C237CF74C40A444CB0024454B03DCF74C0343720E931532F9F382720E939E52C9F3C3D20E92A444CB21A4454B229803AEA0A20022027CF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA62720E939E52C9FA33D20E92A444CB41A4454B40A454DB0024555B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE92A454DB21A4555B20A454DB4024555B438212C9F3B394FE90A2002202A201A202A464EBF1A4656BF31532F9F36314FE939E52C9F37394FE930502E9FA7304FE938212C9FA8384FE90A474FBF024757BF31532F9FA4314FE939E52C9FA5394FE92A434BBF1A4353BF30502E9FA1304FE938212C9FA2384FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9A2FF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFCAFF20EA008000E84E334ECF573B57CF90FF20EA57C0BFEA0080A0E90000D8ECD8 +/* TGZSF */ +:03C8000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039006A8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF5C8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF473747DF573D57DF32322DDF22222DDF12122DDF3A3A2DDF27CF74C237CF74C40A444CB0024454B03DCF74C0343720E931532F9F382720E939E52C9F3C3D20E92A444CB21A4454B22E803AEA0A20022027CF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA62720E939E52C9FA33D20E92A444CB41A4454B40A454DB0024555B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A454DB21A4555B20A454DB4024555B427CF75C62A201A20A7304FE90A20022031532F9F312720E939E52C9FA8384FE92A454DB61A4555B630502E9F36314FE938212C9F37394FE9008000E82A201A202A464EBF1A4656BF31532F9FA4314FE939E52C9FA5394FE90A474FBF024757BF31532F9FA1304FE939E52C9FA2384FE92A434BBF1A4353BF30502E9F35314FE938212C9F39394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E99DFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFC5FF20EA008000E84E334ECF573B57CF8BFF20EA57C0BFEA0080A0E90000D8ECD3 +/* TGZSA */ +:03C8000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039006A8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF5C8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF473747DF573D57DF32322DDF22222DDF12122DDF3A3A2DDF27CF74C237CF74C40A444CB0024454B03DCF74C0343720E931532F9F382720E939E52C9F3C3D20E92A444CB21A4454B22E803AEA0A20022027CF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA62720E939E52C9FA33D20E92A444CB41A4454B40A454DB0024555B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A454DB21A4555B20A454DB4024555B427CF74C62A201A20A7304FE90A20022031532F9F9C2720E939E52C9FA8384FE92A444CB61A4454B630502E9F36314FE938212C9F37394FE9008000E82A201A202A464EBF1A4656BF31532F9FA4314FE939E52C9FA5394FE90A474FBF024757BF31532F9FA1304FE939E52C9FA2384FE92A434BBF1A4353BF30502E9F9D314FE938212C9F9E394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E99DFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFC5FF20EA008000E84E334ECF573B57CF8BFF20EA57C0BFEA0080A0E90000D8ECA0 +/* TGZSAF */ +:03E8000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039006E8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF608007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF473747DF573D57DF32322DDF22222DDF12122DDF3A3A2DDF27CF74C237CF74C40A444CB0024454B03DCF74C0343720E931532F9F382720E939E52C9F3C3D20E92A444CB21A4454B232803AEA0A20022027CF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA62720E939E52C9FA33D20E92A444CB41A4454B40A454DB0024555B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A454DB21A4555B20A454DB4024555B427CF74C62A201A20A7304FE90A20022031532F9F9C2720E939E52C9FA8384FE92A444CB61A4454B630502E9F36314FE938212C9F37394FE90A454DB6024555B63DCF75C62A201A202A464EBF1A4656BF31532F9FA4314FE939E52C9FA5394FE9313D20E90A2002200A474FBF024757BF30502E9FA1304FE938212C9FA2384FE931532F9F9D314FE939E52C9F9E394FE92A434BBF1A4353BF30502E9F35304FE938212C9F39384FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E999FF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFC1FF20EA008000E84E334ECF573B57CF87FF20EA57C0BFEA0080A0E90000D8EC83 +/* T2GZ */ +:0438000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC31003900788015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF698007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF12122DDF22222DDF32322DDF3A3A2DDF683D68DF493749DF3DCF74C037CF74C431532F9F348020E939E52C9F3C3D20E90A4454B0024464B02A4454B21A4464B225803AEA0A2002203DCF74C22A201A2030502E9F32315FE938212C9F33395FE931532F9F008000E82A4454B41A4464B439E52C9F383D20E988735EE92A201A202A4656BF1A4666BF31532F9F3E304FE939E52C9F3F384FE90A4757BF024767BF31532F9F3A314FE939E52C9F3B394FE92A4353BF1A4363BF30502E9F36314FE938212C9F37394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E99FFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFBEFF20EA008000E8583358CF693B69CF7DFF20EA57C0BFEA0080A0E90000D8ECAC +/* T2GZF */ +:0460000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039007D8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF6E8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF12122DDF22222DDF32322DDF3A3A2DDF683D68DF493749DF3DCF74C037CF74C439E52C9F348020E931532F9F008000E888735EE9008000E80FCF75C63C3D20E90A4454B0024464B02A4454B21A4464B228803AEA0A2002203DCF74C22A201A2030502E9F32315FE938212C9F33395FE931532F9F310F20E90A4454B4024464B42A4555B61A4565B639E52C9F383D20E90A2002202A201A200A4757BF024767BF30502E9F3E304FE938212C9F3F384FE92A4656BF1A4666BF31532F9F3A314FE939E52C9F3B394FE931532F9F36304FE939E52C9F37384FE92A4353BF1A4363BF30502E9F35314FE938212C9F39394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E99AFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFBBFF20EA008000E8583358CF693B69CF78FF20EA57C0BFEA0080A0E90000D8ECFB +/* T2GZA */ +:0458000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039007C8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF6D8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF12122DDF22222DDF32322DDF3A3A2DDF683D68DF493749DF3DCF74C037CF74C431532F9F348020E939E52C9F3C3D20E90A4454B0024464B02A4454B21A4464B229803AEA0A2002200FCF74C63DCF74C288735EE92A201A2030502E9F32315FE938212C9F33395FE931532F9F9C0F20E90A4454B4024464B42A4454B61A4464B639E52C9F383D20E90A2002202A201A200A4757BF024767BF30502E9F3E304FE938212C9F3F384FE92A4656BF1A4666BF31532F9F3A314FE939E52C9F3B394FE931532F9F36304FE939E52C9F37384FE92A4353BF1A4363BF30502E9F9D314FE938212C9F9E394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E99BFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFBAFF20EA008000E8583358CF693B69CF79FF20EA57C0BFEA0080A0E90000D8ECA0 +/* T2GZAF */ +:0480000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC31003900818015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF728007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF12122DDF22222DDF32322DDF3A3A2DDF683D68DF493749DF3DCF74C037CF74C40A4454B0024464B031532F9F343720E939E52C9F3C3D20E92A4454B21A4464B22E803AEA0A20022088735EE92A201A203DCF74C20FCF74C630502E9F32315FE938212C9F33395FE931532F9F9C0F20E90A4454B4024464B42A4454B61A4464B639E52C9F383D20E90A2002202A201A203DCF75C6008000E830502E9F3E304FE938212C9F3F384FE90A4555B6024565B631532F9F3A314FE939E52C9F3B394FE9313D20E90A2002202A4656BF1A4666BF0A4757BF024767BF30502E9F36304FE938212C9F37384FE931532F9F9D314FE939E52C9F9E394FE92A4353BF1A4363BF30502E9F35304FE938212C9F39384FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E996FF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFB5FF20EA008000E8583358CF693B69CF74FF20EA57C0BFEA0080A0E90000D8ECDC +/* T2GZS */ +:04A0000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC31003900858015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF768007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF683D68DF493749DF32322DDF22222DDF12122DDF3A3A2DDF0FCF74C237CF74C40A4454B0024464B03DCF74C0343720E931532F9F380F20E939E52C9F3C3D20E92A4454B21A4464B231803AEA0A2002200FCF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA60F20E939E52C9FA33D20E92A4454B41A4464B40A4555B0024565B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE92A4555B21A4565B20A4555B4024565B438212C9F3B394FE92A201A200A2002202A4656BF1A4666BF31532F9F36314FE939E52C9F37394FE930502E9FA7304FE938212C9FA8384FE90A4757BF024767BF31532F9FA4314FE939E52C9FA5394FE92A4353BF1A4363BF30502E9FA1304FE938212C9FA2384FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E992FF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFB2FF20EA008000E8583358CF693B69CF70FF20EA57C0BFEA0080A0E90000D8EC43 +/* T2GZSF */ +:04C8000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039008A8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF7B8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF683D68DF493749DF32322DDF22222DDF12122DDF3A3A2DDF0FCF74C237CF74C40A4454B0024464B03DCF74C0343720E931532F9F380F20E939E52C9F3C3D20E92A4454B21A4464B236803AEA0A2002200FCF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA60F20E939E52C9FA33D20E92A4454B41A4464B40A4555B0024565B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A4555B21A4565B20A4555B4024565B40FCF75C62A201A20A7304FE90A20022031532F9F310F20E939E52C9FA8384FE92A4555B61A4565B630502E9F36314FE938212C9F37394FE9008000E82A201A202A4656BF1A4666BF31532F9FA4314FE939E52C9FA5394FE90A4757BF024767BF31532F9FA1304FE939E52C9FA2384FE92A4353BF1A4363BF30502E9F35314FE938212C9F39394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E98DFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFADFF20EA008000E8583358CF693B69CF6BFF20EA57C0BFEA0080A0E90000D8EC56 +/* T2GZSA */ +:04C8000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039008A8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF7B8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF683D68DF493749DF32322DDF22222DDF12122DDF3A3A2DDF0FCF74C237CF74C40A4454B0024464B03DCF74C0343720E931532F9F380F20E939E52C9F3C3D20E92A4454B21A4464B236803AEA0A2002200FCF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA60F20E939E52C9FA33D20E92A4454B41A4464B40A4555B0024565B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A4555B21A4565B20A4555B4024565B40FCF74C62A201A20A7304FE90A20022031532F9F9C0F20E939E52C9FA8384FE92A4454B61A4464B630502E9F36314FE938212C9F37394FE9008000E82A201A202A4656BF1A4666BF31532F9FA4314FE939E52C9FA5394FE90A4757BF024767BF31532F9FA1304FE939E52C9FA2384FE92A4353BF1A4363BF30502E9F9D314FE938212C9F9E394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E98DFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFADFF20EA008000E8583358CF693B69CF6BFF20EA57C0BFEA0080A0E90000D8EC23 +/* T2GZSAF */ +:04E8000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039008E8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF7F8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF683D68DF493749DF32322DDF22222DDF12122DDF3A3A2DDF0FCF74C237CF74C40A4454B0024464B03DCF74C0343720E931532F9F380F20E939E52C9F3C3D20E92A4454B21A4464B23A803AEA0A2002200FCF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA60F20E939E52C9FA33D20E92A4454B41A4464B40A4555B0024565B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A4555B21A4565B20A4555B4024565B40FCF74C62A201A20A7304FE90A20022031532F9F9C0F20E939E52C9FA8384FE92A4454B61A4464B630502E9F36314FE938212C9F37394FE90A4555B6024565B63DCF75C62A201A202A4656BF1A4666BF31532F9FA4314FE939E52C9FA5394FE9313D20E90A2002200A4757BF024767BF30502E9FA1304FE938212C9FA2384FE931532F9F9D314FE939E52C9F9E394FE92A4353BF1A4363BF30502E9F35304FE938212C9F39384FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E989FF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFA9FF20EA008000E8583358CF693B69CF67FF20EA57C0BFEA0080A0E90000D8ECEE +:0000000001FF diff --git a/firmware/r128/r128_cce.bin.ihex b/firmware/r128/r128_cce.bin.ihex new file mode 100644 index 000000000000..4831315d7b99 --- /dev/null +++ b/firmware/r128/r128_cce.bin.ihex @@ -0,0 +1,129 @@ +:1000000000000000108038000000000010003800E0 +:10001000000000020000008E0000000200000091BD +:1000200000000000402E2423000000006062124FF8 +:10003000000000002E2B596D000000007677753E01 +:1000400000000000898984820000000023BC8B0D21 +:10005000000000002323232300000000238DABB405 +:1000600000000000232323230000000100B028002B +:100070000000000100032800000000010004C0008F +:100080000000000100030800000000023660300E8E +:100090000000000B00040000000000000000000051 +:1000A000000000010200151D0000000100001D0EEF +:1000B00000000001000039D900000001000019D73C +:1000C0000000000C0000001C00000001000019D618 +:1000D0000000000C0000001C0000000200000017DF +:1000E0000000000B01200000000000000100358A24 +:1000F0000000000100064000000000090000001E92 +:100100000000000108D015B4000000101910100004 +:100110000000000300002000000000000000280094 +:1001200000000001000308000000000100003D0E77 +:10013000000000010000C8000000000A0000882A3A +:10014000000000090000002A000000010200150F55 +:1001500000000002000028240000000100003D65AE +:100160000000000100003D66000000020000002BBE +:100170000000000100F32DB4000000012200D8BFF0 +:100180000000000100E088BF0000000C1333383786 +:1001900000000001020615650000000C0000003799 +:1001A00000000001020015640000000100003D662F +:1001B000000000020000002E000000040020083AA9 +:1001C0000000000100080800000000010006C0FF58 +:1001D000000000040040003D000000010007C800CE +:1001E00000000001000700FF000000030000000005 +:1001F0000000000C0000005C000000020000002E67 +:100200000000000C000000B00000000100003D767E +:100210000000000100032800000000010000480069 +:1002200000000001000208000000000106001D0E91 +:1002300000000001000248000000000100028800E8 +:100240000000000100F3C5F80000000100100000EC +:10025000000000060030004E0000000100003D6379 +:100260000000001080303DF0000000021000384314 +:1002700000000002000028430000000C000000B055 +:100280000000000100003D760000000100003D7705 +:100290000000000100003D0E0000000100003D0FC5 +:1002A000000000010050280000000006003000524D +:1002B0000000001080303DF00000000100003DF81B +:1002C00000000002000000520000000100053D0E89 +:1002D0000000000100103D0F00000002003000553A +:1002E0000000000100003D700000000100001E89B8 +:1002F0000000000100003D710000000300003D729D +:100300000000000C0000005C000000020000006221 +:100310000000000100003F280000000100003F270E +:100320000000000100003E820000000100003E8845 +:100330000000000100003E660000000100003E6772 +:100340000000000100003E760000000100003E6851 +:100350000000000100003E690000000100003E6C4A +:100360000000000000003E6D0000000100002800B9 +:1003700000000001005028000000000100003D685E +:100380000000000100030800000000060000006EED +:10039000000000010002C0000000000106303D62C4 +:1003A0000000000200000070000000020030006F3A +:1003B00000000000200038C0000000010001C0C0A3 +:1003C0000000000E0000007D0000000C0003287FEC +:1003D00000000001020015BB0000000C00030880B3 +:1003E0000000000002003DBC0000000100003DBB19 +:1003F0000000000000003DBC00000003000480007D +:100400000000000100048000000000030006C0029C +:100410000000000100B0280000000000306038003B +:100420000000000100C028000000000100B008002A +:100430000000000100D600000000000712801086B6 +:10044000000000000000280000000001000039CC7E +:1004500000000001000039CD00000001000039C992 +:1004600000000001000039CA00000000000039CB84 +:10047000000000011003B80000000001009000001F +:100480000000000110003800000000010003080017 +:100490000000000100903D1B0000000140203D0ACB +:1004A0000000000140203D0B00000001000880001A +:1004B000000000010001C0C00000000E0000009F0D +:1004C0000000000C000308800000000142203DBD38 +:1004D0000000000C0003087F0000000142003DBB4B +:1004E0000000000C000308800000000142203DBC19 +:1004F00000000002000000A20000000140203DBDFD +:100500000000000140003DBB0000000140203DBC58 +:1005100000000001000840000000000100A00000F1 +:1005200000000006003000A6000000101060380037 +:1005300000000009000000A80000000300400000C7 +:100540000000000300403D1D00000000000000000E +:1005500000000000000001000000000E000000AEDE +:10056000000000010001C0A900000001020015C741 +:100570000000000C000000B0000000000000280097 +:10058000000000010001C0AA00000001020015D215 +:10059000000000010001C0A900000003020015C70F +:1005A0000000000100003E88000000010001C0BA08 +:1005B0000000000102001728000000010001C0BB7C +:1005C000000000010200165A0000000000003E5B1F +:1005D000000000000000010000000000000010000A +:1005E000000000010006400B00000009000000BCF4 +:1005F00000000000000028000000000000000000D3 +:1006000000000000000000000000000000000000EA +:1006100000000000000000000000000000000000DA +:1006200000000000000000000000000000000000CA +:1006300000000000000000000000000000000000BA +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C000000000000000000000000000000000002A +:1006D000000000000000000000000000000000001A +:1006E000000000000000000000000000000000000A +:1006F00000000000000000000000000000000000FA +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:00000001FF diff --git a/firmware/radeon/R100_cp.bin.ihex b/firmware/radeon/R100_cp.bin.ihex new file mode 100644 index 000000000000..151647b04fc4 --- /dev/null +++ b/firmware/radeon/R100_cp.bin.ihex @@ -0,0 +1,130 @@ +:1000000000000000210070000000000020007000CF +:1000100000000004000000B400000004000000B86C +:10002000000000006F5B4D4C000000004C4C427F14 +:10003000000000005B568A92000000004CA09C6DFE +:1000400000000000AD4C4C4C000000004CE1AF3D06 +:1000500000000000D8AFAFAF00000000D64C4CDC71 +:10006000000000004CD10D1000000016000F000031 +:1000700000000000362F242D0000000400000012B4 +:1000800000000016000F000000000000362F282D91 +:1000900000000002000380E70000000204002C972B +:1000A00000000016000F000100000000333A373056 +:1000B00000000002000077EF0000000200061000C0 +:1000C0000000001A000000210000001E0000400097 +:1000D00000000002000610000000001A00000021CD +:1000E0000000001E0000400000000002000610009A +:1000F0000000001A000000210000001E0000400067 +:100100000000000400000017000000020003802B24 +:1001100000000002040067E0000000040000001777 +:1001200000000002000077E000000002000650001E +:1001300000000002000037E100000006040067E153 +:1001400000000002000077E000000002000077E1FC +:1001500000000006000077E100000000FFFFFFFF45 +:100160000000000010000000000000020003802BCF +:1001700000000006040067E0000000020000767541 +:100180000000000200007676000000020000767792 +:100190000000000600007678000000020003802CBA +:1001A00000000002040026760000000200007677BE +:1001B0000000000600007678000000180000002F04 +:1001C000000000180000002F0000000600000000E2 +:1001D000000000180000003000000018000000308F +:1001E0000000000600000000000000020160500056 +:1001F000000000020006500000000002000980001C +:1002000000000002000610000000000464C0603E10 +:1002100000000002000380E600000002040025C583 +:1002200000000016000800000000000000000000B0 +:10023000000000020400251D00000002000075807F +:100240000000000200067581000000020400258005 +:100250000000000200067581000000040000004953 +:10026000000000000000500000000002000380E6D3 +:1002700000000002040025C5000000020006100076 +:10028000000000020000750E000000020001900056 +:10029000000000140001105500000012000000557D +:1002A000000000020400250F000000040000504F71 +:1002B00000000002000380E600000002040025C5E3 +:1002C0000000000200007565000000020000756675 +:1002D000000000040000005800000002000380E657 +:1002E00000000002040025C50000000201E655B42C +:1002F000000000024401B0E40000000201C110E46B +:10030000000000182666706600000002040C2565D7 +:1003100000000018000000660000000204002564D0 +:100320000000000200007566000000040000005D8F +:1003300000000008004010690000000200101000DA +:1003400000000002000D80FF000000080080006C2B +:1003500000000002000F900000000002000E00FFED +:100360000000000600000000000000180000008FE0 +:10037000000000040000005B00000002000380E6B3 +:1003800000000002040025C5000000020000757690 +:100390000000000200065000000000020000900073 +:1003A0000000000200041000000000020C00350EE6 +:1003B0000000000200049000000000020005100090 +:1003C0000000000201E785F80000000200200000A4 +:1003D0000000000C0060007E000000020000756359 +:1003E00000000021006075F0000000042000707320 +:1003F000000000040000507300000002000380E6CB +:1004000000000002040025C500000002000075760F +:100410000000000200007577000000020000750E69 +:10042000000000020000750F0000000200A0500054 +:100430000000000C0060008300000021006075F0E7 +:1004400000000002000075F80000000400000083B6 +:1004500000000002000A750E00000002000380E6A2 +:1004600000000002040025C5000000020020750FF6 +:1004700000000004006000860000000200007570AB +:100480000000000200007571000000060000757297 +:1004900000000002000380E600000002040025C501 +:1004A00000000002000050000000000200A0500008 +:1004B0000000000200007568000000020006100045 +:1004C0000000000C00000095000000020005800004 +:1004D000000000020C60756200000004000000973C +:1004E00000000002000380E600000002040025C5B1 +:1004F000000000040060009600000000400070E56D +:1005000000000002000380E600000002040025C590 +:1005100000000002000380E50000001C000000A8AD +:1005200000000018000650AA00000002040025BBCD +:1005300000000018000610AB00000000040075BCAD +:1005400000000002000075BB00000000000075BC48 +:100550000000000600090000000000020009000081 +:1005600000000006000D800200000002000078324A +:10057000000000020000500000000002000380E7BD +:100580000000000204002C97000000020000782008 +:100590000000000200007821000000000000780048 +:1005A000000000020120000000000002200770008F +:1005B0000000000201200000000000022000700086 +:1005C0000000000200061000000000020120751B60 +:1005D000000000028040750A000000028040750B98 +:1005E000000000020011000000000002000380E58E +:1005F0000000001C000000C600000018000610AB40 +:1006000000000002844075BD00000018000610AA1A +:1006100000000002840075BB00000018000610AB4B +:1006200000000002844075BC00000004000000C906 +:1006300000000002804075BD00000002800075BB14 +:1006400000000002804075BC000000020010800025 +:1006500000000002014000000000000C006000CD1E +:100660000000002020C0700000000012000000CF39 +:100670000000000600800000000000060080751DDC +:100680000000000000000000000000020000775C95 +:100690000000000200A050000000000200661000F0 +:1006A000000000200460275D000000000000400002 +:1006B0000000000201E0083000000000210070008E +:1006C000000000006464614D00000000696874204F +:1006D00000000000000000730000000000000000A7 +:1006E000000000020000500000000002000380D063 +:1006F00000000002040025E000000000000075E199 +:10070000000000000000000100000002000380E083 +:1007100000000002040023940000000000005000CC +:1007200000000000000000000000000000000000C9 +:1007300000000000000000080000000000000004AD +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:00000001FF +/* production radeon ucode r1xx-r6xx */ diff --git a/firmware/radeon/R200_cp.bin.ihex b/firmware/radeon/R200_cp.bin.ihex new file mode 100644 index 000000000000..3a0bd73111c4 --- /dev/null +++ b/firmware/radeon/R200_cp.bin.ihex @@ -0,0 +1,130 @@ +:1000000000000000210070000000000020007000CF +:1000100000000004000000BF00000004000000C356 +:10002000000000007A685E5D000000005D5D55889C +:100030000000000068659197000000005DA19F78B6 +:10004000000000005D5D5D5D000000005DEE5D5044 +:1000500000000000F2ACACAC00000000E75DF9E984 +:1000600000000000B1DD0E1100000000E2AFAFAFF4 +:1000700000000016000F000000000000452F232D97 +:10008000000000040000001300000016000F000034 +:1000900000000000452F272D00000016000F000172 +:1000A000000000003E4D4A3700000002000077EFDC +:1000B00000000002000610000000001A00000020EE +:1000C0000000001E000040000000000200061000BA +:1000D0000000001A000000200000001E0000400088 +:1000E00000000002000610000000001A00000020BE +:1000F0000000001E00004000000000040000001688 +:10010000000000020003802A00000002040067E0F3 +:10011000000000040000001600000002000077E06C +:10012000000000020006500000000002000037E15D +:1001300000000006040067E100000002000077E014 +:1001400000000002000077E100000006000077E1F7 +:1001500000000000FFFFFFFF000000001000000093 +:100160000000000007F007F0000000020003802AF2 +:1001700000000006040067E0000000020003802C7D +:100180000000000204002741000000020400274193 +:100190000000000204002743000000020000767502 +:1001A0000000000200007676000000020000767772 +:1001B0000000000600007678000000020003802C9A +:1001C0000000000204002741000000020400274153 +:1001D00000000002040027430000000200007676C1 +:1001E000000000020000767700000006000076782C +:1001F000000000020003802B0000000204002676AD +:100200000000000200007677000000020003802C4E +:100210000000000204002741000000020400274300 +:100220000000000600007678000000020003802C29 +:1002300000000002040027410000000204002741E2 +:10024000000000020400274300000006000076784A +:10025000000000180000002F000000180000002F10 +:100260000000000600000000000000180000003739 +:100270000000001800000037000000060000000029 +:100280000000000201605000000000020006500063 +:1002900000000002000980000000000200061000BB +:1002A0000000000464C06051000000160008000057 +:1002B0000000000000000000000000020400251DF6 +:1002C0000000000200007580000000020006758139 +:1002D0000000000204002580000000020006758175 +:1002E000000000040000005A000000000000500060 +:1002F0000000000200061000000000020000750E61 +:1003000000000002000190000000001400011064D1 +:100310000000001200000064000000020400250F2D +:10032000000000040000505E00000002000075653F +:100330000000000200007566000000040000006577 +:100340000000000201E655B4000000024401B0F0D4 +:100350000000000201C110F0000000182666707154 +:1003600000000002040C2565000000180000007168 +:100370000000000204002564000000020000756611 +:100380000000000400000068000000080040107435 +:10039000000000020010100000000002000D80FFAD +:1003A000000000080080007700000002000F9000AD +:1003B00000000002000E00FF000000060000000028 +:1003C0000000001800000094000000040000006815 +:1003D00000000002000075760000000200065000D8 +:1003E0000000000200009000000000020004100065 +:1003F000000000020C00350E000000020004900016 +:1004000000000002000510000000000201E785F86E +:1004100000000002002000000000000C00600087C7 +:10042000000000020000756300000021006075F00C +:10043000000000042000707C000000040000507CDC +:1004400000000002000075760000000200007577D1 +:10045000000000020000750E000000020000750F91 +:100460000000000200A050000000000C0060008AA4 +:1004700000000021006075F000000002000075F827 +:10048000000000040000008A00000002000A750E4F +:10049000000000020020750F000000040060008DC5 +:1004A000000000020000757000000002000075717D +:1004B00000000006000075720000000200005000FD +:1004C0000000000200A0500000000002000075685B +:1004D00000000002000610000000000C0000009860 +:1004E0000000000200058000000000020C60756240 +:1004F000000000040000009A000000040060009961 +:1005000000000000400070F100000002000380F1D4 +:100510000000001C000000A700000018000650A901 +:1005200000000002040025BB00000018000610AA0D +:1005300000000000040075BC00000002000075BB54 +:1005400000000000000075BC00000006000900006B +:10055000000000020009000000000006000D8002FB +:10056000000000020000500000000002000078219E +:100570000000000000007800000000020000782168 +:10058000000000000000780000000002016650003A +:1005900000000002000A000000000002000671CC0A +:1005A000000000020286F1CD00000010000000B73C +:1005B00000000000210070000000001C000000BED0 +:1005C000000000020006500000000002000A0000C7 +:1005D000000000020006100000000002000B0000F6 +:1005E000000000023806700000000004000A00BA93 +:1005F0000000000020007000000000020120000048 +:10060000000000022007700000000002012000002E +:100610000000000020007000000000020006100032 +:10062000000000020120751B000000028040750AD6 +:10063000000000028040750B000000020011000065 +:1006400000000002000380F10000001C000000D147 +:1006500000000018000610AA00000002844075BDCA +:1006600000000018000610A900000002840075BBFD +:1006700000000018000610AA00000002844075BCAB +:1006800000000004000000D400000002804075BD9E +:1006900000000002800075BB00000002804075BCB5 +:1006A0000000000200108000000000020140000075 +:1006B0000000000C006000D80000002020C0700086 +:1006C00000000012000000DA0000000600800000B8 +:1006D000000000060080751D00000002000025BB20 +:1006E00000000004000040D4000000020000775C1D +:1006F0000000000200A05000000000020066100090 +:10070000000000200460275D0000000000004000A1 +:1007100000000002000079990000000200A05000D3 +:100720000000000200661000000000200460299B09 +:1007300000000000000040000000000201E008305E +:1007400000000000210070000000000200005000C6 +:10075000000000020003805600000002040025E0B3 +:1007600000000000000075E1000000000000000132 +:1007700000000002000380ED0000000004007394FC +:100780000000000000000000000000000000000069 +:1007900000000002000078C400000002000078C5DC +:1007A00000000002000078C600000002000079246A +:1007B00000000002000079250000000200007926F8 +:1007C00000000004000000F2000000020000792494 +:1007D00000000002000079250000000200007926D8 +:1007E00000000004000000F900000000000000000C +:1007F00000000000000000000000000000000000F9 +:00000001FF +/* production radeon ucode r1xx-r6xx */ diff --git a/firmware/radeon/R300_cp.bin.ihex b/firmware/radeon/R300_cp.bin.ihex new file mode 100644 index 000000000000..d307d56882c9 --- /dev/null +++ b/firmware/radeon/R300_cp.bin.ihex @@ -0,0 +1,130 @@ +:10000000000000004200E000000000004000E000AE +:1000100000000008000000AE00000008000000B270 +:100020000000000067554B4A000000004A4A447532 +:100030000000000055527D83000000004A8C8B6553 +:10004000000000004AEF4AF6000000004AE14A4A78 +:1000500000000000E497979700000000DB4AEBDD0A +:10006000000000009CCC4A4A00000000D1989898FB +:10007000000000004A0F9AD600000004000CA00007 +:1000800000000038000D0012000000040000E8B479 +:1000900000000038000D0014000000040000E8B665 +:1000A00000000038000D0016000000040000E854B5 +:1000B00000000038000D0018000000040000E855A2 +:1000C00000000038000D001A000000040000E8568F +:1000D00000000038000D001C000000040000E8577C +:1000E00000000038000D001E000000040000E8249D +:1000F00000000038000D0020000000040000E8258A +:1001000000000038000D0022000000040000E8306C +:1001100000000038000D0024000000040000F0C0C2 +:1001200000000038000D0026000000040000F0C1AF +:1001300000000038000D0028000000040000F0411D +:1001400000000038000D002A000000040000F184C7 +:1001500000000038000D002C000000040000F185B4 +:1001600000000038000D002E000000040000F186A1 +:1001700000000038000D0030000000040000F1878E +:1001800000000038000D0032000000040000F18083 +:1001900000000038000D0034000000040000F3935C +:1001A00000000038000D0036000000040000F38A53 +:1001B00000000038000D0038000000040000F38E3D +:1001C000000000040000E821000000040140A0003D +:1001D00000000018000000430000000400CCE8000C +:1001E00000000004001B000100000004080048009B +:1001F00000000004001B000100000004080048008B +:1002000000000004001B000100000004080048007A +:10021000000000080000003A000000000000A000FC +:10022000000000042000451D000000040000E580DF +:1002300000000004000CE581000000040800458077 +:1002400000000004000CE5810000000800000047E9 +:10025000000000000000A00000000004000C2000CE +:10026000000000040000E50E000000040003200070 +:10027000000000280002205100000024000000516E +:10028000000000040800450F000000080000A04B1B +:10029000000000040000E565000000040000E566C1 +:1002A00000000008000000520000000403CCA5B4C8 +:1002B00000000004054320000000000400022000AC +:1002C000000000304CCCE05E0000000408274565CB +:1002D000000000300000005E0000000408004564DB +:1002E000000000040000E566000000080000005562 +:1002F00000000010008020610000000400202000A9 +:1003000000000004001B00FF00000010010000645A +:1003100000000004001F200000000004001C00FF7B +:100320000000000C00000000000000300000008011 +:100330000000000800000055000000040000E57601 +:1003400000000004000CA0000000000400012000D8 +:100350000000000400082000000000041800650EE2 +:10036000000000040009200000000004000A200032 +:1003700000000004000F0000000000040040000026 +:100380000000001800000074000000040000E56395 +:10039000000000C200C0E5F900000008000000698C +:1003A000000000080000A069000000040000E576DD +:1003B000000000040000E577000000040000E50EE6 +:1003C000000000040000E50F000000040140A00050 +:1003D0000000001800000077000000C200C0E5F92E +:1003E0000000000800000077000000040014E50E83 +:1003F000000000040040E50F0000000800C0007A83 +:10040000000000040000E570000000040000E57139 +:100410000000000C0000E572000000040000A000D5 +:10042000000000040140A000000000040000E56896 +:1004300000000004000C20000000001800000084F0 +:1004400000000004000B00000000000418C0E5627A +:1004500000000008000000860000000800C00085C1 +:1004600000000004000700E30000003800000092D4 +:1004700000000030000CA09400000004080045BB00 +:1004800000000030000C2095000000000800E5BCD2 +:10049000000000040000E5BB000000000000E5BC17 +:1004A0000000000C00120000000000040012000018 +:1004B0000000000C001B0002000000040000A0006F +:1004C000000000040000E821000000000000E80037 +:1004D000000000040000E821000000000000E82EF9 +:1004E0000000000402CCA000000000040014000082 +:1004F00000000004000CE1CC00000004050DE1CD7B +:10050000000000040040000000000018000000A4EB +:100510000000000400C0A00000000008000000A1CE +:1005200000000020000000A6000000004200E000E3 +:1005300000000038000000AD00000004000CA00026 +:10054000000000040014000000000004000C200063 +:10055000000000040016000000000004700CE00021 +:1005600000000008001400A9000000004000E000A6 +:10057000000000040240000000000004400EE00003 +:100580000000000402400000000000004000E00005 +:1005900000000004000C2000000000040240E51BE5 +:1005A000000000050080E50A000000050080E50B62 +:1005B000000000040022000000000004000700E327 +:1005C00000000038000000C000000030000C209542 +:1005D000000000050880E5BD00000030000C2094FC +:1005E000000000050800E5BB00000030000C20956D +:1005F000000000050880E5BC00000008000000C302 +:10060000000000050080E5BD000000050000E5BB1E +:10061000000000050080E5BC00000004002100008F +:1006200000000004028000000000001800C000C7A5 +:10063000000000404180E00000000024000000C9EC +:100640000000000C010000000000000C0100E51D8E +:1006500000000004000045BB00000008000080C34B +:10066000000000040000F3CE000000040140A000E0 +:100670000000000400CC20000000004008C053CF60 +:100680000000000000008000000000040000F3D221 +:10069000000000040140A0000000000400CC200085 +:1006A0000000004008C053D300000000000080009C +:1006B000000000040000F39D000000040140A000C1 +:1006C0000000000400CC20000000004008C0539E41 +:1006D00000000000000080000000000403C008309B +:1006E000000000004200E000000000040000A00044 +:1006F00000000004200045E0000000000000E5E1EB +:10070000000000000000000100000004000700E0FD +:10071000000000000800E39400000000000000005A +:10072000000000040000E8C4000000040000E8C568 +:10073000000000040000E8C6000000040000E928F2 +:10074000000000040000E929000000040000E92A7C +:1007500000000008000000E4000000040000E92898 +:10076000000000040000E929000000040000E92A5C +:1007700000000008000000EB0000000402C02000A0 +:10078000000000040006000000000034000000F338 +:1007900000000008000000F00000000400008000DD +:1007A00000000000C000E0000000000000000000A9 +:1007B00000000004000C200000000004001D0018D0 +:1007C00000000004001A000100000034000000FBDB +:1007D000000000080000004A000000080500A04AD0 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:00000001FF +/* production radeon ucode r1xx-r6xx */ diff --git a/firmware/radeon/R420_cp.bin.ihex b/firmware/radeon/R420_cp.bin.ihex new file mode 100644 index 000000000000..3815891275f9 --- /dev/null +++ b/firmware/radeon/R420_cp.bin.ihex @@ -0,0 +1,130 @@ +:10000000000000004200E000000000004000E000AE +:100010000000000800000099000000080000009D9A +:10002000000000004A554B4A000000004A4A44675D +:100030000000000055526F75000000004A7E7D658B +:1000400000000000D9D3DFF6000000004AC54A4A8C +:1000500000000000C882828200000000BF4ACFC1B9 +:100060000000000087B04A4A00000000B583838387 +:10007000000000004A0F85BA00000004000CA00038 +:1000800000000038000D0012000000040000E8B479 +:1000900000000038000D0014000000040000E8B665 +:1000A00000000038000D0016000000040000E854B5 +:1000B00000000038000D0018000000040000E855A2 +:1000C00000000038000D001A000000040000E8568F +:1000D00000000038000D001C000000040000E8577C +:1000E00000000038000D001E000000040000E8249D +:1000F00000000038000D0020000000040000E8258A +:1001000000000038000D0022000000040000E8306C +:1001100000000038000D0024000000040000F0C0C2 +:1001200000000038000D0026000000040000F0C1AF +:1001300000000038000D0028000000040000F0411D +:1001400000000038000D002A000000040000F184C7 +:1001500000000038000D002C000000040000F185B4 +:1001600000000038000D002E000000040000F186A1 +:1001700000000038000D0030000000040000F1878E +:1001800000000038000D0032000000040000F18083 +:1001900000000038000D0034000000040000F3935C +:1001A00000000038000D0036000000040000F38A53 +:1001B00000000038000D0038000000040000F38E3D +:1001C000000000040000E821000000040140A0003D +:1001D00000000018000000430000000400CCE8000C +:1001E00000000004001B000100000004080048009B +:1001F00000000004001B000100000004080048008B +:1002000000000004001B000100000004080048007A +:10021000000000080000003A000000000000A000FC +:10022000000000042000451D000000040000E580DF +:1002300000000004000CE581000000040800458077 +:1002400000000004000CE5810000000800000047E9 +:10025000000000000000A00000000004000C2000CE +:10026000000000040000E50E000000040003200070 +:10027000000000280002205100000024000000516E +:10028000000000040800450F000000080000A04B1B +:10029000000000040000E565000000040000E566C1 +:1002A00000000008000000520000000403CCA5B4C8 +:1002B00000000004054320000000000400022000AC +:1002C000000000304CCCE05E0000000408274565CB +:1002D000000000300000005E0000000408004564DB +:1002E000000000040000E566000000080000005562 +:1002F00000000010008020610000000400202000A9 +:1003000000000004001B00FF00000010010000645A +:1003100000000004001F200000000004001C00FF7B +:100320000000000C0000000000000030000000721F +:100330000000000800000055000000040000E57601 +:10034000000000040000E577000000040000E50E56 +:10035000000000040000E50F000000040140A000C0 +:100360000000001800000069000000C200C0E5F9AC +:100370000000000800000069000000040014E50E01 +:10038000000000040040E50F0000000800C0006C01 +:10039000000000040000E570000000040000E571AA +:1003A0000000000C0000E572000000040000A00046 +:1003B000000000040140A000000000040000E56807 +:1003C00000000004000C200000000018000000766F +:1003D00000000004000B00000000000418C0E562EB +:1003E00000000008000000780000000800C000774E +:1003F00000000004000700C7000000380000008073 +:10040000000000040000E5BB000000000000E5BCA7 +:10041000000000040000A000000000040000E8212B +:10042000000000000000E800000000040000E821D7 +:10043000000000000000E82E0000000402CCA00034 +:10044000000000040014000000000004000CE1CCD7 +:1004500000000004050DE1CD000000040040000094 +:10046000000000180000008F0000000400C0A00081 +:10047000000000080000008C000000200000009137 +:10048000000000004200E00000000038000000987A +:1004900000000004000CA000000000040014000094 +:1004A00000000004000C2000000000040016000002 +:1004B00000000004700CE00000000008001400942C +:1004C000000000004000E0000000000402400000C6 +:1004D00000000004400EE0000000000402400000A4 +:1004E000000000004000E00000000004000C2000BC +:1004F000000000040240E51B000000050080E50A42 +:10050000000000050080E50B000000040022000050 +:1005100000000004000700C700000038000000A42D +:10052000000000050080E5BD000000050000E5BBFF +:10053000000000050080E5BC000000040021000070 +:1005400000000004028000000000001800C000ABA2 +:10055000000000404180E00000000024000000ADE9 +:100560000000000C010000000000000C0100E51D6F +:1005700000000004000045BB00000008000080A748 +:10058000000000040000F3CE000000040140A000C1 +:100590000000000400CC20000000004008C053CF41 +:1005A0000000000000008000000000040000F3D202 +:1005B000000000040140A0000000000400CC200066 +:1005C0000000004008C053D300000000000080007D +:1005D000000000040000F39D000000040140A000A2 +:1005E0000000000400CC20000000004008C0539E22 +:1005F00000000000000080000000000403C008307C +:10060000000000004200E000000000040000A00024 +:1006100000000004200045E0000000000000E5E1CB +:10062000000000000000000100000004000700C4FA +:10063000000000000800E39400000000000000003B +:10064000000000040000E8C4000000040000E8C549 +:10065000000000040000E8C6000000040000E928D3 +:10066000000000040000E929000000040000E92A5D +:1006700000000008000000C8000000040000E92895 +:10068000000000040000E929000000040000E92A3D +:1006900000000008000000CF0000000402C020009D +:1006A000000000040006000000000034000000D735 +:1006B00000000008000000D40000000400008000DA +:1006C00000000000C000E000000000040000E1CCD9 +:1006D000000000040500E1CD00000004000CA000B3 +:1006E00000000034000000DE00000008000000DA16 +:1006F000000000000000A000000000040019E1CC90 +:1007000000000004001B0001000000040500A00020 +:1007100000000004080041CD00000004000CA0000F +:1007200000000034000000FB000000080000004A48 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B00000000004000C200000000004001D0018D0 +:1007C00000000004001A000100000034000000FBDB +:1007D000000000080000004A000000080500A04AD0 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:00000001FF +/* production radeon ucode r1xx-r6xx */ diff --git a/firmware/radeon/R520_cp.bin.ihex b/firmware/radeon/R520_cp.bin.ihex new file mode 100644 index 000000000000..372ff82a0143 --- /dev/null +++ b/firmware/radeon/R520_cp.bin.ihex @@ -0,0 +1,130 @@ +:10000000000000004200E000000000004000E000AE +:100010000000000800000099000000080000009D9A +:10002000000000004A554B4A000000004A4A44675D +:100030000000000055526F75000000004A7E7D658B +:1000400000000000E0DAE6F6000000004AC54A4A77 +:1000500000000000C882828200000000BF4ACFC1B9 +:100060000000000087B04AD500000000B5838383FC +:10007000000000004A0F85BA00000004000CA00038 +:1000800000000038000D0012000000040000E8B479 +:1000900000000038000D0014000000040000E8B665 +:1000A00000000038000D0016000000040000E854B5 +:1000B00000000038000D0018000000040000E855A2 +:1000C00000000038000D001A000000040000E8568F +:1000D00000000038000D001C000000040000E8577C +:1000E00000000038000D001E000000040000E8249D +:1000F00000000038000D0020000000040000E8258A +:1001000000000038000D0022000000040000E8306C +:1001100000000038000D0024000000040000F0C0C2 +:1001200000000038000D0026000000040000F0C1AF +:1001300000000038000D0028000000040000E0006E +:1001400000000038000D002A000000040000E0005C +:1001500000000038000D002C000000040000E0004A +:1001600000000038000D002E000000040000E00038 +:1001700000000038000D0030000000040000E00026 +:1001800000000038000D0032000000040000F18083 +:1001900000000038000D0034000000040000F3935C +:1001A00000000038000D0036000000040000F38A53 +:1001B00000000038000D0038000000040000F38E3D +:1001C000000000040000E821000000040140A0003D +:1001D00000000018000000430000000400CCE8000C +:1001E00000000004001B000100000004080048009B +:1001F00000000004001B000100000004080048008B +:1002000000000004001B000100000004080048007A +:10021000000000080000003A000000000000A000FC +:10022000000000042000451D000000040000E580DF +:1002300000000004000CE581000000040800458077 +:1002400000000004000CE5810000000800000047E9 +:10025000000000000000A00000000004000C2000CE +:10026000000000040000E50E000000040003200070 +:10027000000000280002205100000024000000516E +:10028000000000040800450F000000080000A04B1B +:10029000000000040000E565000000040000E566C1 +:1002A00000000008000000520000000403CCA5B4C8 +:1002B00000000004054320000000000400022000AC +:1002C000000000304CCCE05E0000000408274565CB +:1002D000000000300000005E0000000408004564DB +:1002E000000000040000E566000000080000005562 +:1002F00000000010008020610000000400202000A9 +:1003000000000004001B00FF00000010010000645A +:1003100000000004001F200000000004001C00FF7B +:100320000000000C0000000000000030000000721F +:100330000000000800000055000000040000E57601 +:10034000000000040000E577000000040000E50E56 +:10035000000000040000E50F000000040140A000C0 +:100360000000001800000069000000C200C0E5F9AC +:100370000000000800000069000000040014E50E01 +:10038000000000040040E50F0000000800C0006C01 +:10039000000000040000E570000000040000E571AA +:1003A0000000000C0000E572000000040000A00046 +:1003B000000000040140A000000000040000E56807 +:1003C00000000004000C200000000018000000766F +:1003D00000000004000B00000000000418C0E562EB +:1003E00000000008000000780000000800C000774E +:1003F00000000004000700C7000000380000008073 +:10040000000000040000E5BB000000000000E5BCA7 +:10041000000000040000A000000000040000E8212B +:10042000000000000000E800000000040000E821D7 +:10043000000000000000E82E0000000402CCA00034 +:10044000000000040014000000000004000CE1CCD7 +:1004500000000004050DE1CD000000040040000094 +:10046000000000180000008F0000000400C0A00081 +:10047000000000080000008C000000200000009137 +:10048000000000004200E00000000038000000987A +:1004900000000004000CA000000000040014000094 +:1004A00000000004000C2000000000040016000002 +:1004B00000000004700CE00000000008001400942C +:1004C000000000004000E0000000000402400000C6 +:1004D00000000004400EE0000000000402400000A4 +:1004E000000000004000E00000000004000C2000BC +:1004F000000000040240E51B000000050080E50A42 +:10050000000000050080E50B000000040022000050 +:1005100000000004000700C700000038000000A42D +:10052000000000050080E5BD000000050000E5BBFF +:10053000000000050080E5BC000000040021000070 +:1005400000000004028000000000001800C000ABA2 +:10055000000000404180E00000000024000000ADE9 +:100560000000000C010000000000000C0100E51D6F +:1005700000000004000045BB00000008000080A748 +:10058000000000040000F3CE000000040140A000C1 +:100590000000000400CC20000000004008C053CF41 +:1005A0000000000000008000000000040000F3D202 +:1005B000000000040140A0000000000400CC200066 +:1005C0000000004008C053D300000000000080007D +:1005D000000000040000F39D000000040140A000A2 +:1005E0000000000400CC20000000004008C0539E22 +:1005F00000000000000080000000000403C008307C +:10060000000000004200E000000000040000A00024 +:1006100000000004200045E0000000000000E5E1CB +:10062000000000000000000100000004000700C4FA +:10063000000000000800E39400000000000000003B +:10064000000000040000E8C4000000040000E8C549 +:10065000000000040000E8C6000000040000E928D3 +:10066000000000040000E929000000040000E92A5D +:1006700000000008000000C8000000040000E92895 +:10068000000000040000E929000000040000E92A3D +:1006900000000008000000CF00000000DEADBEEF4B +:1006A000000000000000011600000004000700D355 +:1006B00000000004080050E700000004000700D418 +:1006C000000000040800401C000000000000E01DC5 +:1006D0000000000402C0200000000004000600002A +:1006E00000000034000000DE00000008000000DB15 +:1006F000000000040000800000000000C000E000D6 +:10070000000000040000E1CC000000040500E1CD81 +:1007100000000004000CA00000000034000000E510 +:1007200000000008000000E1000000000000A00040 +:10073000000000040019E1CC00000004001B0001CF +:10074000000000040500A00000000004080041CDE6 +:1007500000000004000CA00000000034000000FBBA +:10076000000000080000004A000000000000000037 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B00000000004000C200000000004001D0018D0 +:1007C00000000004001A000100000034000000FBDB +:1007D000000000080000004A000000080500A04AD0 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:00000001FF +/* production radeon ucode r1xx-r6xx */ diff --git a/firmware/radeon/R600_me.bin.ihex b/firmware/radeon/R600_me.bin.ihex new file mode 100644 index 000000000000..30d4c14a308d --- /dev/null +++ b/firmware/radeon/R600_me.bin.ihex @@ -0,0 +1,1345 @@ +:1000000000000000C020040000000000000000000C +:1000100000A0000A000000000000FFFF00284621A9 +:100020000000000000000000D900480000000000AF +:1000300000000000C02004000000000000000000DC +:1000400000A0000A000000000000000000E0000026 +:100050000000000000010000C02946200000000050 +:1000600000000000D900480000000000000000006F +:10007000C0200400000000000000000000A0000AF2 +:10008000000000008100000000204411000000007A +:1000900000000001002048110000000000042004BE +:1000A0000060441100000614000000000060000021 +:1000B000000005B20000000000600000000005C55F +:1000C00000000000C02008000000000000000F0039 +:1000D000002816220000000000000008002116255C +:1000E0000000000000000020002036250000000075 +:1000F0008D000000002044110000000000000004FA +:10010000002F022500000000000000000CE00000AD +:1001100000000018004120000040481100000019B4 +:100120000042200000204811000000008E00000066 +:1001300000204411000000000000003100204A2D82 +:1001400000000000900000000020441100000000AA +:100150000000000000204805000000000000000C26 +:1001600000211622000000000000000300281625D0 +:10017000000000000000001900211A220000000009 +:100180000000000400281A26000000000000000003 +:10019000002914C5000000000000002100203625C1 +:1001A0000000000000000000003A140200000000FF +:1001B00000000016002116250000000000000003CA +:1001C00000281625000000000000001D00200E2D54 +:1001D00000000000FFFFFFFC00280E2300000000CD +:1001E00000000000002914A3000000000000001D12 +:1001F00000203625000000000000800000280E22AC +:10020000000000000000000700220E230000000094 +:10021000000000000029386E0000000020000000EF +:1002200000280E22000000000000000600210E231E +:1002300000000000000000000029386E00000000EF +:100240000000000000220222000000000000000068 +:1002500014E0000000000038000000002EE0000064 +:1002600000000035000000002CE000000000003716 +:100270000000000000400E2D0000003900000008C2 +:1002800000200E2D00000000000000090040122D8B +:10029000000000460000000100400E2D0000003963 +:1002A00000000000C0200C0000000000003FFFFC28 +:1002B0000028122300000000000000020022122487 +:1002C000000000000000001F00211E2300000000AD +:1002D0000000000014E000000000003E00000008E4 +:1002E00000401C11000000410000000D00201E2DE8 +:1002F000000000000000000F00281E270000000082 +:100300000000000300221E27000000007FC0000044 +:1003100000281A23000000000000001400211A2603 +:10032000000000000000000100331A260000000059 +:100330000000000800221A26000000000000000053 +:1003400000290CC700000000000000300020362407 +:100350000000000000007F000028122100000000C3 +:1003600000001400002F0224000000000000000024 +:100370000CE000000000004B0000000100290E23EB +:1003800000000000000000100020362300000000E4 +:100390000000E0000020441100000000FFF8000011 +:1003A00000294A230000000000000000003A2C024F +:1003B000000000000000000200220E2B00000000E0 +:1003C000FC00000000280E230000000000000011C7 +:1003D000002036230000000000001FFF00294A23F0 +:1003E000000000000000003000204A2D0000000046 +:1003F0000000000000204811000000000000003252 +:1004000000200E2D00000000060A020000294A23E9 +:100410000000000000000000002048110000000063 +:100420000000000000204811000000000000000152 +:1004300000210222000000000000000014E0000083 +:1004400000000061000000002EE000000000005FDE +:10045000000000002CE000000000005E0000000032 +:1004600000400E2D000000620000000100400E2D33 +:10047000000000620000000A00200E2D00000000B5 +:100480000000000B0040122D0000006A0000000078 +:10049000C0200C0000000000003FFFFC00281223D9 +:1004A00000000000000000020022122400000000F2 +:1004B0007FC0000000281623000000000000001488 +:1004C0000021162500000000000000010033162561 +:1004D000000000008000000000280E230000000043 +:1004E0000000000000290CA3000000003FFFFC00FA +:1004F00000290E23000000000000001F00211E2321 +:10050000000000000000000014E000000000006D8A +:100510000000010000401C11000000700000000DF0 +:1005200000201E2D00000000000000F000281E2703 +:10053000000000000000000400221E270000000050 +:100540008100000000204411000000000000000DA8 +:100550000020481100000000FFFFF0FF00281A30C3 +:10056000000000000000A02800204411000000004E +:1005700000000000002948E6000000000000A0186C +:1005800000204411000000003FFFFFFF00284A2325 +:10059000000000000000A010002044110000000036 +:1005A0000000000000204804000000000000002DB2 +:1005B0000020162D0000000000000000002F00A306 +:1005C00000000000000000000CC0000000000080DF +:1005D0000000002E0020162D00000000000000008A +:1005E000002F00A400000000000000000CC000006C +:1005F00000000081000000000040000000000087B3 +:100600000000002D00203623000000000000002E16 +:1006100000203624000000000000001D00201E2DD8 +:10062000000000000000000200210227000000007E +:100630000000000014E0000000000087000000003F +:1006400000600000000005ED0000000000600000F8 +:10065000000005E10000000200210E220000000061 +:100660000000000014C000000000008A0000001814 +:10067000C040362000000090000000002EE0000086 +:100680000000008E000000002CE000000000008D43 +:100690000000000200400E2D0000008F000000034B +:1006A00000400E2D0000008F0000000C00200E2DD9 +:1006B00000000000000000180020362300000000A9 +:1006C0000000000300210E220000000000000000D6 +:1006D00014C00000000000950000A00C0020441190 +:1006E0000000000000000000C020480000000000E2 +:1006F00000000000C04048000000009D0000A00C69 +:1007000000204411000000000000000000204811FB +:1007100000000000000000002EE000000000009B30 +:10072000000000002CE000000000009A0000000221 +:1007300000400E2D0000009C0000000300400E2D24 +:100740000000009C0000000C00200E2D00000000A6 +:10075000000000000020480300000000000000002E +:10076000003A0C0200000000003F000000280E23A9 +:10077000000000000000001000210E230000000017 +:100780000000001300203623000000000000001EBF +:100790000021022B000000000000000014C0000037 +:1007A000000000A40000001CC02036200000000053 +:1007B0000000001F0021022B0000000000000000CC +:1007C00014C00000000000A70000001BC02036205D +:1007D000000000000000000800210E2B00000000B7 +:1007E0000000007F00280E23000000000000000031 +:1007F000002F022300000000000000000CE00000B9 +:10080000000000DB000000002700000000000000E6 +:1008100000000000006000000000028C8100000069 +:1008200000204411000000000000000600204811D4 +:10083000000000000000000C00221E30000000003C +:100840009980000000204411000000000000000416 +:100850000020122D000000000000000800221224D9 +:10086000000000000000001000201811000000002F +:100870000000000000291CE400000000000000004F +:1008800000604807000001289B0000000020441180 +:1008900000000000000000000020480200000000EE +:1008A0009C00000000204411000000000000000037 +:1008B0000033146F000000000000000100333E23ED +:1008C0000000000000000000D90048000000000007 +:1008D0000000000000203C05000000008100000036 +:1008E00000204411000000000000000E002048110C +:1008F00000000000000000000020101000000000B8 +:100900000000E00700204411000000000000000F7C +:100910000021022B000000000000000014C00000B5 +:10092000000000C500F8FF0800204811000000008A +:100930009800000000404811000000D6000000F0C0 +:1009400000280E2200000000000000A0002F02235B +:1009500000000000000000000CC00000000000D4F7 +:100960000000001300200E2D000000000000000118 +:10097000002F022300000000000000000CE0000037 +:10098000000000CF00000002002F02230000000042 +:10099000000000000CE00000000000CE00003F005E +:1009A00000400C11000000D000001F0000400C119E +:1009B000000000D000000F0000200C11000000001B +:1009C0000038000900294A23000000003F00000011 +:1009D00000280E2B000000000000000200220E2361 +:1009E000000000000000000700494A23000000D674 +:1009F00000380F09002048110000000068000007BF +:100A000000204811000000000000000800214A27D3 +:100A1000000000000000000000204811000000005D +:100A2000060A020000294A2400000000000000001D +:100A300000204811000000000000000000204811C4 +:100A4000000000000000A20200204411000000008D +:100A500000FF000000284A220000000000000030D3 +:100A600000200E2D000000000000002E0020122D9E +:100A70000000000000000000002F008300000000C4 +:100A8000000000000CE00000000000E30000000097 +:100A900000600000000005E70000000000400000CA +:100AA000000000E40000000000600000000005EA13 +:100AB000000000070020222D0000000000000005BB +:100AC00000220E22000000000010000000280E236B +:100AD0000000000000000000002920680000000065 +:100AE00000000000003A0C0200000000000000EFCF +:100AF00000280E23000000000000000000292068EC +:100B0000000000000000001D00200E2D000000006D +:100B1000000000030021022300000000000000008C +:100B200014E00000000000F10000000B002102288A +:100B3000000000000000000014C00000000000F1F0 +:100B40000000040000292228000000000000001A14 +:100B500000203628000000000000001C00210E22AA +:100B6000000000000000000014C00000000000F6BB +:100B70000000A30C00204411000000000000000051 +:100B800000204811000000000000001E00210E227D +:100B9000000000000000000014C00000000001047C +:100BA0000000A30F0020441100000000000000130B +:100BB00000200E2D0000000000000001002F022385 +:100BC00000000000000000000CC00000000000FD5C +:100BD000FFFFFFFF00404811000001040000000279 +:100BE000002F022300000000000000000CC00000E5 +:100BF000000001000000FFFF004048110000010458 +:100C000000000004002F022300000000000000008C +:100C10000CC0000000000103000000FF004048116C +:100C20000000010400000001002048110000000045 +:100C30000002C40000204411000000000000001F5A +:100C400000210E22000000000000000014C000007F +:100C50000000010B0000001040210E2000000000E9 +:100C600000000019002036230000000000000018DA +:100C700040224A200000000000000010C0424A202C +:100C80000000010D0000000000200C110000000019 +:100C900000000019002036230000000000000000C2 +:100CA0000020481100000000000000000020481152 +:100CB000000000000000000A0020101100000000E9 +:100CC00000000000002F02240000000000000000CF +:100CD0000CE000000000011400000000002048119A +:100CE0000000000000000001005312240000011069 +:100CF000FFBFFFFF00283A2E000000000000001B8D +:100D000000210222000000000000000014C00000CA +:100D100000000127810000000020441100000000B5 +:100D20000000000D00204811000000000000001825 +:100D300000220E3000000000FC00000000280E23FE +:100D400000000000810000000020441100000000AD +:100D50000000000E0020481100000000000000000C +:100D600000201010000000000000E00E00204411E0 +:100D70000000000007F8FF080020481100000000F4 +:100D80000000000000294A230000000000000024A9 +:100D900000201E2D000000000000000800214A274E +:100DA00000000000000000000020481100000000CA +:100DB000060A020000294A2400000000000000008A +:100DC0000020481100000000000000000020481131 +:100DD0000000000000000000008000000000000093 +:100DE000810000000020441100000000000000010C +:100DF00000204811000000000000217C0020441168 +:100E000000000000008000000020481100000000E9 +:100E1000000000000020480600000000000000085C +:100E200000214A2700000000000000001700000019 +:100E3000000000000004217F00604411000006143F +:100E40000000001F00210230000000000000000030 +:100E500014C00000000006130000000400404C1104 +:100E60000000012E00000000006000000000000BE8 +:100E70000000000000600411000002FE00000000FD +:100E800000200411000000000000000000600811B4 +:100E90000000019F00000000006000000000015100 +:100EA0000000FFFF40280E2000000000000000109E +:100EB000C0211220000000000000FFFF4028062093 +:100EC0000000000000000010C0210A200000000007 +:100ED0000000000000341461000000000000000069 +:100EE00000741882000002A40001A1FD00604411FA +:100EF000000002C900003FFF002F022F0000000089 +:100F0000000000000CC000000000013800000000DC +:100F1000C04004000000000100000000006000006C +:100F20000000000B0000000000600411000002FE41 +:100F3000000000000020041100000000000000007C +:100F4000006008110000019F00003FFF002F022FEA +:100F500000000000000000000CE0000000000000A5 +:100F600000000000006000000000015100000010BF +:100F700040210E20000000000000FFFFC0281220CA +:100F800000000000000000104021162000000000BA +:100F90000000FFFFC0681A20000002A40001A1FDAC +:100FA00000604411000002C900003FFF002F022F23 +:100FB00000000000000000000CC00000000001491B +:100FC00000000000C0400400000000010000225C9E +:100FD00000204411000000000000000100300A2F32 +:100FE000000000000000000100210A2200000000B3 +:100FF0000000000300384A220000000000002256D2 +:1010000000204411000000000000001A00204811D8 +:10101000000000000000A1FC0020441100000000BE +:1010200000000001008048110000000000000000E6 +:10103000006000000000000B0000000000600000E5 +:101040000000017C00000000006000000000018D35 +:1010500000003FFF002F022F0000000000000000F2 +:101060000CE00000000000000000000000202C0840 +:10107000000000000000000000202411000000001B +:10108000000000000020281100000000000022568F +:10109000002044110000000000000016002048114C +:1010A000000000000000225C00204411000000004D +:1010B00000000003002048110000000093800000A1 +:1010C00000204411000000000000000200221E2940 +:1010D0000000000000000000007048EB00000189E3 +:1010E0000000000000600000000002A400000001F9 +:1010F000403306200000000000000000C03024093A +:101100000000000000003FFF002F022F0000000041 +:10111000000000000CE000000000000000000000E3 +:10112000006000000000028C9500000000204411C7 +:101130000000000000000000002F0221000000005D +:10114000000000000CE0000000000173000000003F +:10115000C0204800000000000000000100530621EC +:101160000000016F92000000002044110000000008 +:1011700000000000C0604800000001840001A1FDE3 +:101180000020441100000000000000130020062D84 +:1011900000000000000000000078042A000002E4C3 +:1011A00000000000002028090000000000003FFFB0 +:1011B000002F022F00000000000000000CC0000003 +:1011C0000000016500000000C040040000000001B4 +:1011D0000000021000600411000002FE00003FFF4A +:1011E000002F022F00000000000000000CE00000B3 +:1011F000000001810000001BC0203620000000001C +:101200000000001CC0203620000000003F800000CD +:1012100000200411000000004600000000600811DA +:101220000000019F0000000000800000000000009E +:101230000000A1FC002044110000000000003FFF5E +:10124000002F022F00000000000000000CC0000072 +:10125000000001880000000100804811000000002B +:101260000000002100804811000000000000FFFF86 +:1012700040280E200000000000000010C0211220B5 +:10128000000000000000FFFF4028162000000000C2 +:1012900000000010C0811A20000000008100000042 +:1012A000002044110000000000000006002048114A +:1012B000000000000000000800221E3000000000B6 +:1012C0000000003200201A2D000000000000E000A5 +:1012D0000020441100000000FFFBFF09002048111E +:1012E00000000000000000110020222D000000007E +:1012F00000001FFF00294A2800000000000000062F +:101300000020222D0000000000000000002920E83D +:10131000000000000000000000204808000000005D +:10132000000000000020481100000000060A020032 +:1013300000294A260000000000000000002048119B +:101340000000000000000000002048110000000024 +:10135000000001000020181100000000000000083B +:1013600000621E28000001280000000800822228D8 +:10137000000000000002C000002044110000000036 +:101380000000001B00600E2D000001AA0000001CE0 +:1013900000600E2D000001AA0000C00800204411CA +:1013A000000000000000001D00200E2D00000000C5 +:1013B0000000000014C00000000001A600000000B2 +:1013C000002004110000000000000000002048017F +:1013D000000000003900000000204811000000005B +:1013E0000000000000204811000000000000000084 +:1013F00000804802000000000000002000202E2D88 +:101400000000000000000000003B0D630000000031 +:101410000000000800224A23000000000000001025 +:1014200000224A23000000000000001800224A2386 +:1014300000000000000000000080480300000000E1 +:1014400000000000006000000000000B0000100021 +:1014500000600411000002FE0000000000200411E2 +:101460000000000000000000006008110000019F63 +:10147000000000070021062F0000000000000019F6 +:1014800000200A2D000000000000000100202C11A7 +:10149000000000000000FFFF4028222000000000A4 +:1014A0000000000F002622280000000000000010AD +:1014B00040212620000000000000000F0026262901 +:1014C00000000000000000000020280200000000D2 +:1014D0000000225600204411000000000000001B04 +:1014E000002048110000000000000000002F022131 +:1014F00000000000000000000CE00000000001CD32 +:101500000000225C00204411000000000000008167 +:1015100000204811000000000000A1FC0020441140 +:101520000000000000000001002048110000000041 +:101530000000008000201C110000000000000000DE +:10154000002F022700000000000000000CE0000057 +:10155000000001C90000000000600000000001D68A +:101560000000000100531E27000001C5000000011B +:1015700000202C11000000000000001F00280A229B +:10158000000000000000001F00282A2A00000000C0 +:101590000000000100530621000001BE0000225C93 +:1015A00000204411000000000000000200304A2F1B +:1015B000000000000000A1FC002044110000000019 +:1015C00000000001002048110000000000000001A0 +:1015D00000301E2F0000000000000000002F022736 +:1015E00000000000000000000CE00000000000000F +:1015F0000000000000600000000001D600000001B3 +:1016000000531E27000001D20000FFFF40280E20DB +:10161000000000000000000F00260E230000000064 +:1016200000000010C0211220000000000000000F88 +:101630000026122400000000000000000020141109 +:10164000000000000000000000601811000002A46B +:101650000001A1FD00204411000000000000000076 +:10166000002F022B00000000000000000CE0000032 +:10167000000001E500000010002216280000000014 +:10168000FFFF000000281625000000000000FFFFFB +:1016900000281A290000000000000000002948C5A9 +:1016A00000000000000000000020480A00000000C8 +:1016B0000000000000202C110000000000000010BD +:1016C0000022162300000000FFFF0000002816255E +:1016D000000000000000FFFF00281A2400000000A6 +:1016E00000000000002948C50000000000000000C4 +:1016F00000731503000001F200000000002018052F +:10170000000000000000000000731524000001F23A +:1017100000000000002D14C50000000000000000C3 +:10172000003008A200000000000000000020480275 +:10173000000000000000000000202802000000005F +:101740000000000000202003000000000000000056 +:1017500000802404000000000000000F002102258A +:10176000000000000000000014C00000000006138C +:1017700000000000002B1405000000000000000124 +:10178000009016250000000000000000006000002E +:101790000000000B0000000000600411000002FEC9 +:1017A0000000000000200411000000000000000004 +:1017B000006008110000019F000022560020441123 +:1017C000000000000000001A00294A22000000006A +:1017D00000000000C02000000000000000003FFFEB +:1017E000002F022F00000000000000000CE00000AD +:1017F0000000000000000000C02004000000000005 +:101800000000225C002044110000000000000003E2 +:1018100000384A21000000000000A1FC0020441113 +:10182000000000000000000100204811000000003E +:101830000000FFFF40281220000000000000001000 +:10184000C0211A20000000000000FFFF40280E20E9 +:101850000000000000000010C02116200000000061 +:101860000000000000741465000002A40001A1FD46 +:1018700000604411000002C900000001003306218D +:101880000000000000000000002F02210000000006 +:10189000000000000CC000000000020600003FFF36 +:1018A000002F022F00000000000000000CC000000C +:1018B000000001FF00000000C04004000000000123 +:1018C0000000000000600000000005C500000000EE +:1018D0000040040F00000200000000000060000053 +:1018E000000005B20000000000600000000005C517 +:1018F0000000021000600411000002FE0000000061 +:10190000006000000000018D000000000060000089 +:10191000000001890000000000600000000002A437 +:1019200000000000006000000000028C93800000B6 +:1019300000204411000000000000000000204808C2 +:10194000000000009500000000204411000000008D +:1019500000000000002F022F000000000000000027 +:101960000CE000000000021F00000000C040480022 +:101970000000021C92000000002044110000000042 +:1019800000000000C02048000000000000002256B7 +:101990000020441100000000000000160020481143 +:1019A000000000000000225C002044110000000044 +:1019B0000000000300204811000000000000A1FC0E +:1019C0000020441100000000000000010020481128 +:1019D000000000000001A1FD0020441100000000F3 +:1019E0000000000000600411000002E4000000009C +:1019F000C040040000000001000000000060000082 +:101A0000000005B20000A00C0020441100000000FE +:101A100000000000C020480000000000000000009E +:101A2000C04048000000000000000000006000000E +:101A30000000000B0000001840210A2000000000F8 +:101A400000000003002F0222000000000000000040 +:101A50000AE00000000002350000001A0020222DDC +:101A600000000000000801010029222800000000F9 +:101A70000000001A00203628000000000000A30C1F +:101A8000002044110000000000000000C0204800B9 +:101A90000000000000000000C0204800000000001E +:101AA00000000000C04048000000023A00000000B2 +:101AB000006000000000000B000000100060041136 +:101AC000000002FE3F800000002004110000000022 +:101AD00000000000006008110000019F0000225C6F +:101AE0000020441100000000000000030020481105 +:101AF000000000000000000000600000000002651F +:101B00000000001D00201E2D00000000000000014C +:101B100000211E27000000000000000014E000006B +:101B2000000002530000001800201E2D00000000DD +:101B30000000FFFF00281E2700000000000000003A +:101B400000341C27000000000000000012C000004C +:101B5000000002480000000000201C1100000000EE +:101B600000000000002F00E5000000000000000061 +:101B700008C000000000024B000000000020140715 +:101B8000000000000000001800201E2D00000000D2 +:101B90000000001000211E270000000000000000CF +:101BA00000341C47000000000000000012C00000CC +:101BB000000002500000000000201C110000000086 +:101BC00000000000002F00E6000000000000000000 +:101BD00008C00000000002530000000000201807A9 +:101BE000000000000000000000600000000002AAE9 +:101BF00000002256002044110000000000000000F8 +:101C000000342023000000000000000012C000008B +:101C10000000025B000000000034204400000000CF +:101C20000000000012C000000000025A0000001670 +:101C3000004048110000025F0000001800404811F9 +:101C40000000025F0000000000342044000000009B +:101C50000000000012C000000000025E000000173B +:101C6000004048110000025F0000001900204811E8 +:101C7000000000000000A1FC002044110000000052 +:101C80000000000100204811000000000001A1FD3B +:101C900000604411000002D200003FFF002F022F1D +:101CA00000000000000000000CC000000000023F27 +:101CB00000000000C040040000000001000000100F +:101CC00040210620000000000000FFFFC0280A207D +:101CD000000000000000001040210E200000000065 +:101CE0000000FFFFC02812200000000000000010CC +:101CF00040211620000000000000FFFFC0881A20CD +:101D000000000000810000000020441100000000DD +:101D10000000000100204811000000000004200421 +:101D20000060441100000614000000000060000084 +:101D3000000005B200000000C06000000000028C3E +:101D40000000000500200A2D00000000000000082F +:101D500000220A22000000000000003400201A2D9A +:101D6000000000000000002400201E2D00000000E4 +:101D70000000700000281E27000000000000000086 +:101D800000311CE6000000000000003300201A2D86 +:101D9000000000000000000C00221A2600000000D5 +:101DA00000000000002F00E600000000000000001E +:101DB00006E000000000027B0000000000201C1173 +:101DC000000000000000000000200C1100000000D6 +:101DD0000000003400203623000000000000001046 +:101DE00000201811000000000000000000691CE243 +:101DF0000000012893800000002044110000000032 +:101E000000000000002048070000000095000000CE +:101E1000002044110000000000000000002F022FED +:101E200000000000000000000CE00000000002863E +:101E30000000000100333E2F000000000000000001 +:101E4000D90048000000000092000000002044116A +:101E50000000000000000000C0204800000000005A +:101E60000000002400403627000000000000000CA5 +:101E7000C0220A20000000000000003200203622AC +:101E80000000000000000031C040362000000000CB +:101E90000000A2A40020441100000000000000097E +:101EA0000020481100000000A100000000204411A3 +:101EB0000000000000000001008048110000000048 +:101EC0000000002900201E2D00000000000000007E +:101ED000002C1CE300000000000000290020362731 +:101EE000000000000000002A00201E2D000000005D +:101EF00000000000002C1CE4000000000000002A8C +:101F000000203627000000000000002B00201E2DBE +:101F10000000000000000000003120A300000000CD +:101F200000000000002D1D07000000000000002B35 +:101F300000203627000000000000002C00201E2D8D +:101F40000000000000000000003120C4000000007C +:101F500000000000002D1D07000000000000002C04 +:101F600000803627000000000000002900203623F2 +:101F7000000000000000002A0020362400000000BD +:101F80000000000000311CA3000000000000002B36 +:101F900000203627000000000000000000311CC4B3 +:101FA000000000000000002C008036270000000028 +:101FB000000000220020362700000000000000235F +:101FC00000203628000000000000001D00201E2D0B +:101FD00000000000000000020021022700000000B5 +:101FE0000000000014C00000000002C50000000056 +:101FF00000400000000002C200000022002036273E +:10200000000000000000002300203628000000002F +:102010000000001D00201E2D000000000000000236 +:1020200000210227000000000000000014E0000072 +:10203000000002C20000000300210227000000008F +:102040000000000014E00000000002C50000002BAA +:1020500000201E2D0000000000000000002E00E106 +:10206000000000000000000002C00000000002C5E7 +:102070000000002900201E2D0000000000000000CC +:10208000003120A10000000000000000002E00E848 +:10209000000000000000000006C00000000002C5B3 +:1020A0000000002C00201E2D000000000000000099 +:1020B000002E00E2000000000000000002C000004E +:1020C000000002C50000002A00201E2D00000000B4 +:1020D00000000000003120C20000000000000000ED +:1020E000002E00E8000000000000000006C0000014 +:1020F000000002C50000000000600000000005EDC7 +:1021000000000000006000000000029E00000000CF +:1021100000400000000002C7000000000060000056 +:102120000000029E0000000000600000000005E4C6 +:102130000000000000400000000002C70000000096 +:10214000006000000000029000000000004000005D +:10215000000002C70000002200201E2D0000000029 +:10216000000000230080222D00000000000000106D +:1021700000221E2300000000000000000029488704 +:10218000000000000000000000311CA3000000005F +:102190000000001000221E270000000000000000C8 +:1021A00000294887000000000000001000221E23C4 +:1021B0000000000000000000003120C4000000000A +:1021C0000000FFFF0028222800000000000000009F +:1021D00000894907000000000000001000221E23B3 +:1021E00000000000000000000029488700000000F7 +:1021F0000000001000221E2100000000000000006E +:1022000000294847000000000000000000311CA326 +:10221000000000000000001000221E270000000047 +:1022200000000000002948870000000000000000B6 +:1022300000311CA1000000000000001000221E2739 +:1022400000000000000000000029484700000000D6 +:102250000000001000221E2300000000000000000B +:10226000003120C4000000000000FFFF00282228E9 +:1022700000000000000000000029490700000000E5 +:102280000000001000221E210000000000000000DD +:10229000003120C2000000000000FFFF00282228BB +:1022A0000000000000000000008949070000000055 +:1022B0000000001000221E230000000000000000AB +:1022C00000294887000000000000000100220A21C8 +:1022D0000000000000000000003308A20000000021 +:1022E0000000001000221E2200000000000000106C +:1022F0000021222200000000000000000029490700 +:10230000000000000000000000311CA300000000DD +:102310000000001000221E27000000000000000046 +:1023200000294887000000000000000100220A2167 +:102330000000000000000000003008A200000000C3 +:102340000000001000221E2200000000000000100B +:10235000002122220000000000000000002949079F +:10236000000000000000001000221E2300000000FA +:1023700000000000003120C4000000000000FFFF4A +:102380000028222800000000000000000029490762 +:102390000000000000000000003808C50000000038 +:1023A00000000000003008410000000000000001B3 +:1023B00000220A220000000000000000003308A2F2 +:1023C000000000000000001000221E22000000009B +:1023D0000000001000212222000000000000000088 +:1023E00000894907000000000000001D0020222D88 +:1023F000000000000000000014C000000000030105 +:10240000FFFFFFEF00280621000000000000001A77 +:102410000020222D000000000000F8E00020441100 +:102420000000000000000000002949010000000039 +:1024300000000000008949010000000000000000C9 +:10244000002048110000000000000000002048119A +:1024500000000000060A0200008048110000000091 +:1024600000000000C02000000000000097000000F5 +:10247000C02044110000000000000000C0204811EE +:10248000000000008A00000000204411000000004D +:102490000000000000204811000000000000225C45 +:1024A000002044110000000000000000C02048008F +:1024B000000000000000A1FC00204411000000000A +:1024C00000000000C02048000000000000000000E4 +:1024D000C0200400000000000000000000A0000A6E +:1024E00000000000970000000020441100000000E0 +:1024F0000000000000204811000000008A000000D9 +:1025000000204411000000000000000000204811DD +:10251000000000000000225C0020441100000000C8 +:1025200000000000C0204800000000000000A1FCE6 +:10253000002044110000000000000000C0204800FE +:102540000000000000000000C020040000000000A7 +:102550000000000000A0000A00000000970000003A +:10256000002044110000000000000000002048117D +:10257000000000008A00000000204411000000005C +:102580000000000000204811000000000000225C54 +:10259000002044110000000000000000C02048009E +:1025A000000000000000A1FC002044110000000019 +:1025B00000000000C0204800000000000001A1FD54 +:1025C000002044110000000000000000D900480075 +:1025D0000000000000000000C02004000000000017 +:1025E0000000000000A0000A0000000000002257C8 +:1025F000002044110000000000000003C0484A20F1 +:10260000000000000000225D0020441100000000D6 +:1026100000000000C0404800000000000000000072 +:1026200000600000000005C500000000C020080098 +:10263000000000000000225C0020441100000000A7 +:102640000000000300384A22000000000000A1FC46 +:10265000002044110000000000000000C0204800DD +:10266000000000000001A1FD002044110000000056 +:1026700000000000002F0222000000000000000007 +:102680000CE00000000000000000000040204800B6 +:10269000000000000000000140304A20000000005F +:1026A00000000002C0304A200000000000000001CD +:1026B00000530A22000003340000003FC0280A2013 +:1026C0000000000081000000002044110000000014 +:1026D000000000010020481100000000000021F867 +:1026E00000204411000000000000001700204811E5 +:1026F00000000000000421F90060441100000614ED +:102700000000001100210230000000000000000065 +:1027100014E000000000033D00000014002F02221E +:1027200000000000000000000CC000000000035189 +:102730000000201000204411000000000000800074 +:1027400000204811000000000001A2A40020441154 +:102750000000000000000000002048110000000000 +:1027600000000016006048110000035E0000210018 +:10277000002044110000000000000000C0204800BC +:102780000000000000000000C02048000000000021 +:1027900000000000C0204800000000000000000011 +:1027A000C0204800000000000001A2A40020441145 +:1027B00000000000000000000020481100000000A0 +:1027C000000000000040480200000000000000047B +:1027D000002F022200000000000000000CC00000DA +:1027E00000000355000020100020441100000000EC +:1027F000000080000040481100000349000000284C +:10280000002F022200000000000000000CE0000089 +:1028100000000349000021040020441100000000D2 +:1028200000000000C0204800000000000000000080 +:10283000C02048000000000000000000C020480048 +:102840000000000000000000C02048000000000060 +:102850000000A2A4002044110000000000000000BD +:10286000004048020000000000000035002036262D +:1028700000000000000000490020181100000000C6 +:1028800000000000002048110000000000000001CE +:1028900000331A260000000000000000002F02266E +:1028A00000000000000000000CC0000000000360F9 +:1028B0000000003500801A2D000000000000003FDD +:1028C000C0280A200000000000000015002F02228E +:1028D00000000000000000000CE000000000037693 +:1028E0000000001E002F0222000000000000000077 +:1028F0000CE000000000038000000020002F0222F6 +:1029000000000000000000000CE000000000038C4C +:102910000000000F002F0222000000000000000055 +:102920000CE000000000039800000010002F0222BD +:1029300000000000000000000CE000000000039810 +:1029400000000006002F022200000000000000002E +:102950000CE000000000039A00000016002F022285 +:1029600000000000000000000CE000000000039FD9 +:102970000000A2A40020441100000000000000009C +:1029800000404802000000000800000000290A2260 +:10299000000000000000000340210E2000000000A5 +:1029A0000000000CC0211220000000000008000000 +:1029B000002812240000000000000014C02216208D +:1029C0000000000000000000002914A40000000026 +:1029D0000000A2A40020441100000000000000003C +:1029E000002948A2000000000000A1FE00204411C0 +:1029F000000000000000000000404803000000004C +:102A000081000000002044110000000000000001CF +:102A10000020481100000000000021F800204411AF +:102A20000000000000000015002048110000000018 +:102A3000000421F900604411000006140000001594 +:102A400000210230000000000000000014E000003F +:102A5000000003820000210E00204411000000004D +:102A600000000000C020480000000000000000003E +:102A7000C0204800000000000000A2A40020441173 +:102A800000000000000000000040480200000000BC +:102A9000810000000020441100000000000000013F +:102AA0000020481100000000000021F8002044111F +:102AB0000000000000000016002048110000000087 +:102AC000000421F900604411000006140000000316 +:102AD00000210230000000000000000014E00000AF +:102AE0000000038E000021080020441100000000B7 +:102AF00000000000C02048000000000000000000AE +:102B0000C0204800000000000000A2A400204411E2 +:102B1000000000000000000000404802000000002B +:102B20000000201000204411000000000000800080 +:102B30000040481100000000000020100020441157 +:102B4000000000000000800000204811000000008C +:102B50000001A2A4002044110000000000000000B9 +:102B6000002048110000000000000006004048114D +:102B700000000000000020100020441100000000B0 +:102B80000000800000204811000000000001A2A405 +:102B90000020441100000000000000000020481147 +:102BA0000000000000000016006048110000035EF5 +:102BB0000000001600404811000000000000000066 +:102BC000C02008000000000000000000C0200C0031 +:102BD000000000000000001D002102230000000092 +:102BE0000000000014E00000000003B981000000B4 +:102BF00000204411000000000000000100204811E6 +:102C000000000000000021F8002044110000000036 +:102C1000000000170020481100000000000421F906 +:102C20000060441100000614000000110021023071 +:102C3000000000000000000014E00000000003ABF2 +:102C400000002100002044110000000000000000EE +:102C5000002048020000000000000000002048039F +:102C600000000000BABECAFE0020481100000000AB +:102C7000CAFEBABE0020481100000000000020106B +:102C800000204411000000000000800000204811D6 +:102C9000000000000000A2A4002044110000000079 +:102CA00000000004004048110000000000002170F6 +:102CB0000020441100000000000000000020480235 +:102CC0000000000000000000002048030000000099 +:102CD0008100000000204411000000000000000AF4 +:102CE000002048110000000000000000002000103B +:102CF000000000000000000014C00000000003BE3F +:102D00008C0000000020441100000000CAFEBABE82 +:102D10000040481100000000810000000020441124 +:102D20000000000000000001002048110000000029 +:102D300000003FFF40280A20000000008000000043 +:102D400040280E200000000040000000C028122093 +:102D50000000000000040000006946220000061484 +:102D6000000000000020141000000000000000001F +:102D7000002F022300000000000000000CC0000033 +:102D8000000003CC00000000C0401800000003CF8A +:102D900000003FFFC0281A200000000000040000CF +:102DA00000694626000006140000000000201810EC +:102DB0000000000000000000002F022400000000BE +:102DC000000000000CC00000000003D20000000062 +:102DD000C0401C00000003D500003FFFC0281E209B +:102DE00000000000000400000069462700000614EF +:102DF0000000000000201C10000000000000000087 +:102E0000002044020000000000000000002820C54F +:102E10000000000000000000004948E80000000039 +:102E2000A580000000200811000000000000200024 +:102E300000200C110000000083000000006044111D +:102E4000000003FD0000000000204402000000001C +:102E500000000000C020480000000000000000004A +:102E600040204800000000000000001FC021022098 +:102E7000000000000000000014C00000000003E299 +:102E8000000020100020441100000000000080001D +:102E900000204811000000000000FFFFC048122081 +:102EA000000003EAA78000000020081100000000D5 +:102EB0000000A00000200C110000000083000000B2 +:102EC00000604411000003FD0000000000204402E7 +:102ED0000000000000000000C020480000000000CA +:102EE00000000000C0204800000000000000FFFFBC +:102EF000C0281220000000008300000000204411C0 +:102F000000000000000000000030488300000000C6 +:102F100084000000002044110000000000000000B8 +:102F2000C020480000000000000000001D0000005C +:102F3000000000008300000000604411000003FD59 +:102F400000000000C040040000000001A980000053 +:102F500000200811000000000000C00000400C111B +:102F6000000003E5AB800000002008110000000015 +:102F70000000F8E000400C11000003E5AD80000007 +:102F800000200811000000000000F88000400C1133 +:102F9000000003E5B38000000020081100000000DD +:102FA0000000F3FC00400C11000003E5AF800000BE +:102FB00000200811000000000000E00000400C119B +:102FC000000003E5B18000000020081100000000AF +:102FD0000000F00000400C11000003E58300000039 +:102FE000002044110000000000002148002048118A +:102FF00000000000840000000020441100000000D8 +:1030000000000000C0204800000000000000000098 +:103010001D00000000000000000000000080000013 +:103020000000000000182000C03046200000000012 +:1030300000000000D900480000000000000000006F +:10304000C0200400000000000000000000A0000AF2 +:10305000000000000018A000C03046200000000062 +:1030600000000000D900480000000000000000003F +:10307000C0200400000000000000000000A0000AC2 +:10308000000000000018C000C03046200000000012 +:1030900000000000D900480000000000000000000F +:1030A000C0200400000000000000000000A0000A92 +:1030B000000000000018F8E0C030462000000000CA +:1030C00000000000D90048000000000000000000DF +:1030D000C0200400000000000000000000A0000A62 +:1030E000000000000018F880C030462000000000FA +:1030F00000000000D90048000000000000000000AF +:10310000C0200400000000000000000000A0000A31 +:10311000000000000018E000C03046200000000061 +:1031200000000000D900480000000000000000007E +:10313000C0200400000000000000000000A0000A01 +:10314000000000000018F000C03046200000000021 +:1031500000000000D900480000000000000000004E +:10316000C0200400000000000000000000A0000AD1 +:10317000000000000018F3FCC030462000000000F2 +:1031800000000000D900480000000000000000001E +:10319000C0200400000000000000000000A0000AA1 +:1031A0000000000086000000002044110000000024 +:1031B0000000000000404801000000008500000001 +:1031C0000020441100000000000000000040480101 +:1031D000000000000000217C0020441100000000DD +:1031E00000000000C02048000000000000000000B7 +:1031F000C02048000000000000000000C02048007F +:1032000000000000810000000020441100000000C8 +:103210000000000100204811000000000000000034 +:10322000C02008000000000000000000170000009F +:10323000000000000004217F00604411000006141B +:103240000000001F0021023000000000000000000C +:1032500014C00000000000000000000000404C020C +:103260000000042E00000000C0200C000000000040 +:1032700000000000C020100000000000000000005E +:10328000C02014000000000000000000C020180052 +:103290000000000000000000C0201C000000000032 +:1032A00000007F0000280A21000000000000450007 +:1032B000002F022200000000000000000CE00000CF +:1032C0000000043C00000000C020200000000000BE +:1032D00000000000170000000000000000000010C7 +:1032E00000280A230000000000000010002F022226 +:1032F00000000000000000000CE00000000004449A +:1033000081000000002044110000000000000001C6 +:10331000002048110000000000040000006946245D +:103320000000061400000000004000000000044DF2 +:103330008100000000204411000000000000000097 +:1033400000204811000000000000216D0020441101 +:103350000000000000000000002048040000000001 +:1033600000000000002048050000000000000000F0 +:103370001AC00000000004499E0000000020441113 +:1033800000000000CAFEBABE002048110000000084 +:10339000000000001AE000000000044C00000000E3 +:1033A000002824F0000000000000000700280A2385 +:1033B0000000000000000001002F022200000000B9 +:1033C000000000000AE000000000045400000000BB +:1033D000002F00C9000000000000000004E0000011 +:1033E0000000046D00000000004000000000047AAE +:1033F00000000002002F0222000000000000000078 +:103400000AE000000000045900000000002F00C97D +:10341000000000000000000002E000000000046D59 +:1034200000000000004000000000047A00000003DB +:10343000002F022200000000000000000AE000004F +:103440000000045E00000000002F00C90000000022 +:10345000000000000CE000000000046D000000000F +:10346000004000000000047A00000004002F022247 +:1034700000000000000000000AE0000000000463FB +:1034800000000000002F00C9000000000000000044 +:103490000AE000000000046D000000000040000091 +:1034A0000000047A00000005002F02220000000046 +:1034B000000000000AE000000000046800000000B6 +:1034C000002F00C9000000000000000006E000001E +:1034D0000000046D00000000004000000000047ABD +:1034E00000000006002F0222000000000000000083 +:1034F0000AE000000000046D00000000002F00C979 +:10350000000000000000000008E000000000046D62 +:1035100000000000004000000000047A00007F006E +:1035200000280A210000000000004500002F0222B0 +:1035300000000000000000000AE0000000000000A1 +:103540000000000800210A23000000000000000025 +:1035500014C000000000047700002169002044111D +:103560000000000000000000C02048000000000033 +:1035700000000000C0204800000000000000000023 +:10358000C020480000000000CAFEBABE004048113A +:103590000000000000000000C02044000000000007 +:1035A00000000000C020000000000000000000003B +:1035B000C04048000000000000007F0000280A21F1 +:1035C0000000000000004500002F02220000000063 +:1035D000000000000AE0000000000480000000007D +:1035E000C02000000000000000000000C02000001B +:1035F0000000000000000000C040000000000000CB +:103600000000000000404C080000043C00000000E6 +:10361000C0200800000000000000001040210E2023 +:1036200000000000000000114021122000000000F6 +:103630000000001240211620000000000000216957 +:10364000002044110000000000000000002048029B +:103650000000000000000000002102250000000022 +:103660000000000014E000000000048A00040000D4 +:10367000C0494A200000048BFFFBFFFFC0284A20FE +:1036800000000000000000000021022300000000F4 +:103690000000000014E0000000000497000000009B +:1036A000C02048000000000000000000C0204800CA +:1036B00000000000000000000021022400000000C3 +:1036C0000000000014C000000000000081000000A5 +:1036D00000204411000000000000000C00204811F0 +:1036E00000000000000000000020001000000000AA +:1036F0000000000014C0000000000493A0000000BF +:103700000020441100000000CAFEBABE004048116B +:1037100000000000810000000020441100000000B3 +:103720000000000400204811000000000000216B90 +:10373000002044110000000000000000C0204810DC +:103740000000000081000000002044110000000083 +:103750000000000500204811000000000000216C5E +:10376000002044110000000000000000C0204810AC +:103770000000000000000000002F022400000000F4 +:10378000000000000CE0000000000000000000004D +:10379000004000000000049100000000C0210A2049 +:1037A000000000000000000014C00000000004AE93 +:1037B0008100000000204411000000000000000013 +:1037C00000204811000000000000216D002044117D +:1037D0000000000000000000C020480000000000C1 +:1037E00000000000C02048000000000000000000B1 +:1037F0001AC00000000004A99E000000002044112F +:1038000000000000CAFEBABE0020481100000000FF +:10381000000000001AE00000000004AC00000000FE +:1038200000400000000004B28100000000204411AC +:10383000000000000000000100204811000000000E +:1038400000040000C0294620000000000000000025 +:10385000C0600000000006140000000100210222E8 +:10386000000000000000000014C00000000004B9C7 +:103870000000216900204411000000000000000049 +:10388000C02048000000000000000000C0204800E8 +:1038900000000000000000000020481000000000B0 +:1038A000CAFEBABE0040481100000000000000003F +:1038B000C02044000000000000000000C04048108C +:1038C0000000000081000000002044110000000002 +:1038D000000000010020481100000000000021F855 +:1038E00000204411000000000000000D00204811DD +:1038F00000000000000421F90060441100000614DB +:103900000000000000210230000000000000000064 +:1039100014C00000000004BB0000218000204411FE +:103920000000000000000000C0204800000000006F +:1039300000000000C02000000000000000000000A7 +:10394000C02048000000000000000000C02000006F +:103950000000000000000000C0404800000000001F +:103960000000000300333E2F0000000000000001B3 +:1039700000210221000000000000000014E000000F +:10398000000004EB0000003500200A2D00000000BC +:103990000004000018E00C11000004DA000000012F +:1039A00000333E2F00000000000021690020441178 +:1039B000000000000000000000204802000000009D +:1039C0000000000000204803000000000000000884 +:1039D00000300A220000000000000000C020480063 +:1039E0000000000000000000C020480000000000AF +:1039F00000002169002044110000000000000000C8 +:103A000000204802000000000000000000204803E1 +:103A1000000000000000000800300A220000000042 +:103A200000000000C020480000000000000000006E +:103A3000D8C04800000004CE0000216900204411D5 +:103A4000000000000000000000204802000000000C +:103A500000000000002048030000000000000008F3 +:103A600000300A220000000000000000C0204800D2 +:103A70000000000000000000C0204800000000001E +:103A8000000000360020122D0000000000000000A1 +:103A900000290C830000000000002169002044116F +:103AA00000000000000000000020480200000000AC +:103AB0000000000000204803000000000000000893 +:103AC00000300A220000000000000000C020480072 +:103AD0000000000000000000C020480000000000BE +:103AE000000000110021022400000000000000007E +:103AF00014C00000000000000000000000400000B2 +:103B00000000049100000035C020362000000000B5 +:103B100000000036C0403620000000000000304A9F +:103B20000020441100000000E0000000C0484A20CE +:103B3000000000000000000F002102210000000032 +:103B40000000000014C00000000004F200000000AB +:103B5000006000000000000B00000000D900000021 +:103B60000000000000000000C04004000000000150 +:103B7000810000000020441100000000000000024D +:103B80000020481100000000000000FF00280E3057 +:103B90000000000000000000002F022300000000D1 +:103BA000000000000CC00000000004F6000000004F +:103BB000C0200800000000000000000014C0000049 +:103BC0000000050B0000000000200C1100000000A8 +:103BD0000000002400203623000000000000003414 +:103BE00000203623000000000000003200203623B1 +:103BF000000000000000003100203623000000001B +:103C00000000001D00203623000000000000002DF1 +:103C100000203623000000000000002E0020362384 +:103C2000000000000000001B002036230000000000 +:103C30000000001C0020362300000000FFFFE00011 +:103C400000200C1100000000000000290020362395 +:103C5000000000000000002A0020362300000000C1 +:103C600000001FFF00200C11000000000000002BCE +:103C700000203623000000000000002C0020362326 +:103C800000000000F1FFFFFF00283A2E00000000B6 +:103C90000000001AC0220E200000000000000000FA +:103CA0000029386E0000000081000000002044114F +:103CB0000000000000000006002048110000000085 +:103CC0000000003340203620000000008700000084 +:103CD000002044110000000000000000C020480047 +:103CE000000000000000A1F40020441100000000CA +:103CF0000000000000204810000000009D000000AF +:103D000000204411000000000000001F40214A2054 +:103D10000000000096000000002044110000000098 +:103D200000000000C020480000000000000000006B +:103D3000C0200C000000000000000000C0201000A7 +:103D4000000000000000001F0021162400000000F9 +:103D50000000000014C0000000000000000000256A +:103D600000203623000000000000000300281E236E +:103D700000000000000000080022222300000000D4 +:103D8000FFFFF000002822280000000000000000D3 +:103D9000002920E80000000000000027002036284D +:103DA000000000000000001800211E230000000099 +:103DB000000000280020362700000000000000025C +:103DC000002216240000000000000000003014A8AB +:103DD0000000000000000026002036250000000042 +:103DE0000000000300211A24000000001000000061 +:103DF00000281A2600000000EFFFFFFF00283A2EDF +:103E00000000000000000000004938CE000006025B +:103E10000000000140280A20000000000000000609 +:103E200040280E200000000000000300C0281220DF +:103E30000000000000000008002112240000000023 +:103E400000000000C020162000000000000000005C +:103E5000C0201A2000000000000000000021022203 +:103E6000000000000000000014C000000000054138 +:103E7000810000000020441100000000000000014B +:103E800000204811000000000000225800300A24E1 +:103E90000000000000040000006946220000061433 +:103EA0000000216900204411000000000000000013 +:103EB00000204805000000000002000000294A26FA +:103EC000000000000000000000204810000000007A +:103ED000CAFEBABE00204811000000000000000227 +:103EE000002F022300000000000000000CC00000B2 +:103EF0000000054900000000C0201C100000000068 +:103F000000000000C04000000000055B000000024F +:103F1000002F022300000000000000000CC0000081 +:103F2000000005498100000000204411000000004D +:103F3000000000010020481100000000000022588D +:103F400000300A240000000000040000006946223E +:103F50000000061400000000C0201C10000000003B +:103F600000000000C04000000000055B00000000F1 +:103F7000002F022300000000000000000CC0000021 +:103F80000000054D00000000C0201C0000000000E3 +:103F900000000000C04000000000055B00000004BD +:103FA000002F022300000000000000000CC00000F1 +:103FB00000000559810000000020441100000000AD +:103FC0000000000000204811000000000000216DEA +:103FD000002044110000000000000000C020480044 +:103FE0000000000000000000C020480000000000A9 +:103FF000000000001AC00000000005549E000000F0 +:104000000020441100000000CAFEBABE0020481182 +:1040100000000000000000001AE00000000005574A +:104020000000000000401C100000055B00000000C4 +:10403000C02000000000000000000000C0400000A0 +:1040400000000000000000000EE000000000055D20 +:104050000000000000600000000005A40000000057 +:10406000002F022400000000000000000CC000002F +:104070000000056D0000A2B7002044110000000000 +:104080000000000000204807000000008100000040 +:104090000020441100000000000000010020481131 +:1040A000000000000004A2B60060441100000614E5 +:1040B0000000001A0021223000000000000000066D +:1040C00000222630000000000000A2C4002044119D +:1040D0000000000000000000003048E9000000007F +:1040E0000000000000E000000000056B0000A2D10D +:1040F00000204411000000000000000000404808BB +:10410000000000000000A2D10020441100000000C7 +:104110000000000100504A280000000000000001DB +:10412000002F022400000000000000000CC000006E +:104130000000057D0000A2BB00204411000000002B +:10414000000000000020480700000000810000007F +:104150000020441100000000000000010020481170 +:10416000000000000004A2BA006044110000061420 +:104170000000001A002122300000000000000006AC +:1041800000222630000000000000A2C500204411DB +:104190000000000000000000003048E900000000BE +:1041A0000000000000E000000000057B0000A2D23B +:1041B00000204411000000000000000000404808FA +:1041C000000000000000A2D2002044110000000006 +:1041D0000000000100504A2800000000000000021A +:1041E000002F022400000000000000000CC00000AE +:1041F0000000058D0000A2BF002044110000000057 +:1042000000000000002048070000000081000000BE +:1042100000204411000000000000000100204811AF +:10422000000000000004A2BE00604411000006145B +:104230000000001A002122300000000000000006EB +:1042400000222630000000000000A2C60020441119 +:104250000000000000000000003048E900000000FD +:104260000000000000E000000000058B0000A2D369 +:104270000020441100000000000000000040480839 +:10428000000000000000A2D3002044110000000044 +:104290000000000100504A28000000000000A2C3F6 +:1042A000002044110000000000000000002048072A +:1042B0000000000081000000002044110000000008 +:1042C0000000000100204811000000000004A2C20C +:1042D00000604411000006140000001A0021223082 +:1042E0000000000000000006002226300000000050 +:1042F0000000A2C7002044110000000000000000E0 +:10430000003048E9000000000000000000E000006C +:10431000000005990000A2D4002044110000000014 +:104320000000000000404808000000000000A2D487 +:1043300000204411000000000000000100504A2845 +:104340000000000085000000002044110000000073 +:104350000000000000204801000000000000304A7A +:10436000002044110000000001000000002048115E +:104370000000000000000000004000000000059F59 +:10438000A4000000C0204411000000000000000054 +:10439000C04048000000000000000000C0600000B5 +:1043A000000005A400000000C0400400000000015F +:1043B0000001A2A400204411000000000000000041 +:1043C00000204811000000000000000000204811FB +:1043D0000000000000000000002048110000000064 +:1043E000000000000020481100000000000000054F +:1043F00000204811000000000000A1F4002044113A +:104400000000000000000000002048110000000033 +:10441000880000000020441100000000000000019E +:104420000020481100000000FF000000002044119F +:104430000000000000000000002048110000000003 +:1044400000000001002048110000000000000002F0 +:104450000080481100000000000000000EE0000095 +:10446000000005B700001000002008110000000047 +:104470000000003400203622000000000000000090 +:1044800000600000000005BB0000000000600000AC +:10449000000005A498000000002044110000000066 +:1044A0000000000000804811000000000000000033 +:1044B000C0600000000005BB00000000C040040018 +:1044C000000000010000A2A4002044110000000030 +:1044D00000000022002048110000000089000000B8 +:1044E00000204411000000000000000100204811DD +:1044F00000000000FF000000002044110000000048 +:104500000000000000204811000000000000000131 +:104510000020481100000000000000020080481147 +:10452000000000000000217AC020441100000000BB +:10453000000000000040481100000000970000004B +:10454000002044110000000000000000002048117D +:10455000000000008A00000000204411000000005C +:10456000000000000020481100000000FF000000D3 +:10457000002044110000000000000000002048114D +:1045800000000000000000010020481100000000B1 +:104590000000000200804811000000000000000040 +:1045A00000600000000005E1000020100020441120 +:1045B0000000000000008000002048110000000002 +:1045C0000001A2A4C020441100000000000000006F +:1045D0000020481100000000000000160060481193 +:1045E0000000035E000000160020481100000000DB +:1045F0000000201000204411000000000001000015 +:10460000002048110000000081000000002044113B +:104610000000000000000001002048110000000020 +:104620000000217C002044110000000009800000EF +:104630000020481100000000FFFFFFFF002048118C +:1046400000000000000000000020481100000000F1 +:104650000000000017000000000000000004217F9F +:1046600000604411000006140000001F0021023009 +:10467000000000000000000014C000000000000066 +:104680000000000400404C11000005DC0000001D8B +:1046900000201E2D000000000000000400291E273D +:1046A000000000000000001D008036270000000010 +:1046B0000000001D00201E2D00000000FFFFFFFB7A +:1046C00000281E27000000000000001D0080362783 +:1046D000000000000000001D00201E2D0000000052 +:1046E0000000000800291E27000000000000001D37 +:1046F00000803627000000000000001D00201E2D55 +:1047000000000000FFFFFFF700281E270000000048 +:104710000000001D0080362700000000000020106F +:10472000002044110000000000008000002048111B +:10473000000000000001A2A40020441100000000BD +:1047400000000000002048110000000000000016DA +:10475000006048110000035E0000001600204811B0 +:1047600000000000000020100020441100000000A4 +:104770000001000000204811000000000000217C22 +:1047800000204411000000000180000000204811BA +:104790000000000000FFFFFF0020481100000000A3 +:1047A0000000000000204811000000000000000090 +:1047B00017000000000000008100000000204411EC +:1047C000000000000000000100204811000000006F +:1047D0000004217F00604411000006140000000066 +:1047E00000200010000000000000000014C00000C5 +:1047F000000006130000001000404C11000005F9F5 +:1048000000000000C02004000000000000000000C4 +:1048100038C00000000000000000002500200A2D24 +:10482000000000000000002600200E2D0000000007 +:10483000000000270020122D0000000000000028CA +:104840000020162D00000000000021690020441106 +:1048500000000000000000000020480400000000EC +:1048600000000000002048050000000000000000DB +:104870000020480100000000CAFEBABE0020481116 +:1048800000000000000000040030122400000000BE +:1048900000000000002F0064000000000000000085 +:1048A0000CC00000000006120000000300281A22BD +:1048B000000000000000000800221222000000009A +:1048C000FFFFF0000028122400000000000000009C +:1048D000002910C40000000000000027004036241A +:1048E0000000000000000000008000000000000048 +:1048F000000000001AC00000000006149F00000025 +:104900000020441100000000CAFEBABE0020481179 +:1049100000000000000000001AE000000000061780 +:104920000000000000800000000000000000000007 +:10493000006000000000000B000010000060041187 +:10494000000002FE00000000002004110000000032 +:1049500000000000006008110000019F0000225CC0 +:104960000020441100000000000000030020481156 +:10497000000000000000225600204411000000004A +:104980000000001B00204811000000000000A1FCF6 +:104990000020441100000000000000010020481128 +:1049A000000000000001A1FDC02044110000000033 +:1049B0000000002900201E2D000000000000001053 +:1049C00000221E27000000000000002C0020222DE5 +:1049D000000000000000FFFF002822280000000067 +:1049E000000000000029490700000000000000004E +:1049F00000204811000000000000002A0020222DA5 +:104A0000000000000000FFFF002822280000000036 +:104A1000000000000029490700000000000000001D +:104A200000204811000000000000002B00201E2D77 +:104A3000000000000000001000221E2700000000FF +:104A400000000000002949070000000000000000ED +:104A500000404811000000000000000000000000BD +:104A60000000000000000000000000000000000046 +:104A70000000000000000000000000000000000036 +:104A80000000000000000000000000000000000026 +:104A90000000000000000000000000000000000016 +:104AA0000000000000000000000000000000000006 +:104AB00000000000000000000000000000000000F6 +:104AC00000000000000000000000000000000000E6 +:104AD00000000000000000000000000000000000D6 +:104AE00000000000000000000000000000000000C6 +:104AF00000000000000000000000000000000000B6 +:104B000000000000000000000000000000000000A5 +:104B10000000000000000000000000000000000095 +:104B20000000000000000000000000000000000085 +:104B30000000000000000000000000000000000075 +:104B40000000000000000000000000000000000065 +:104B50000000000000000000000000000000000055 +:104B60000000000000000000000000000000000045 +:104B70000000000000000000000000000000000035 +:104B80000000000000000000000000000000000025 +:104B90000000000000000000000000000000000015 +:104BA0000000000000000000000000000000000005 +:104BB00000000000000000000000000000000000F5 +:104BC00000000000000000000000000000000000E5 +:104BD00000000000000000000000000000000000D5 +:104BE00000000000000000000000000000000000C5 +:104BF00000000000000000000000000000000000B5 +:104C000000000000000000000000000000000000A4 +:104C10000000000000000000000000000000000094 +:104C20000000000000000000000000000000000084 +:104C30000000000000000000000000000000000074 +:104C40000000000000000000000000000000000064 +:104C50000000000000000000000000000000000054 +:104C60000000000000000000000000000000000044 +:104C70000000000000000000000000000000000034 +:104C80000000000000000000000000000000000024 +:104C90000000000000000000000000000000000014 +:104CA0000000000000000000000000000000000004 +:104CB00000000000000000000000000000000000F4 +:104CC00000000000000000000000000000000000E4 +:104CD00000000000000000000000000000000000D4 +:104CE00000000000000000000000000000000000C4 +:104CF00000000000000000000000000000000000B4 +:104D000000000000000000000000000000000000A3 +:104D10000000000000000000000000000000000093 +:104D20000000000000000000000000000000000083 +:104D30000000000000000000000000000000000073 +:104D40000000000000000000000000000000000063 +:104D50000000000000000000000000000000000053 +:104D60000000000000000000000000000000000043 +:104D70000000000000000000000000000000000033 +:104D80000000000000000000000000000000000023 +:104D90000000000000000000000000000000000013 +:104DA0000000000000000000000000000000000003 +:104DB00000000000000000000000000000000000F3 +:104DC00000000000000000000000000000000000E3 +:104DD00000000000000000000000000000000000D3 +:104DE00000000000000000000000000000000000C3 +:104DF00000000000000000000000000000000000B3 +:104E000000000000000000000000000000000000A2 +:104E10000000000000000000000000000000000092 +:104E20000000000000000000000000000000000082 +:104E30000000000000000000000000000000000072 +:104E40000000000000000000000000000000000062 +:104E50000000000000000000000000000000000052 +:104E60000000000000000000000000000000000042 +:104E70000000000000000000000000000000000032 +:104E80000000000000000000000000000000000022 +:104E90000000000000000000000000000000000012 +:104EA0000000000000000000000000000000000002 +:104EB00000000000000000000000000000000000F2 +:104EC00000000000000000000000000000000000E2 +:104ED00000000000000000000000000000000000D2 +:104EE00000000000000000000000000000000000C2 +:104EF00000000000000000000000000000000000B2 +:104F000000000000000000000000000000000000A1 +:104F10000000000000000000000000000000000091 +:104F20000000000000000000000000000000000081 +:104F30000000000000000000000000000000000071 +:104F40000000000000000000000000000000000061 +:104F50000000000000000000000000000000000051 +:104F60000000000000000000000000000000000041 +:104F70000000000000000000000000000000000031 +:104F80000000000000000000000000000000000021 +:104F90000000000000000000000000000000000011 +:104FA0000000000000000000000000000000000001 +:104FB00000000000000000000000000000000000F1 +:104FC00000000000000000000000000000000000E1 +:104FD00000000000000000000000000000000000D1 +:104FE00000000000000000000000000000000000C1 +:104FF00000000000000000000000000000000000B1 +:1050000000000000000000000000000000000000A0 +:105010000000000000000000000000000000000090 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B000013304EF059B02390000000001B00159E1 +:1052C0000425059B00000000021201F6023901428C +:1052D000000000000210022E0289022A00000000D5 +:1052E00003C2059B059B059B0000000005CD05CE74 +:1052F0000308059B00000000059B05A00309032986 +:10530000000000000313026B032B031D00000000CC +:10531000059B059B059B059B00000000059B052C3C +:10532000059B059B0000000003A5059B04A2032D1F +:1053300000000000048104330423059B00000000EA +:1053400004BB04ED042704C800000000043304F487 +:10535000033A036500000000059B059B059B059B28 +:1053600000000000059B059B059B059B00000000BD +:10537000059B059B05B905A200000000059B059B48 +:105380000007059B00000000059B059B059B059BF6 +:1053900000000000059B059B059B059B000000008D +:1053A00003E303D803F303F10000000003F903F55E +:1053B00003F703FB0000000004070403040F040BC1 +:1053C0000000000004170413041F041B0000000069 +:1053D000059B059B059B059B00000000059B059B0D +:1053E000059B059B00000000059B059B059B059BFD +:1053F0000000000000020600061900060000000080 +:00000001FF diff --git a/firmware/radeon/R600_pfp.bin.ihex b/firmware/radeon/R600_pfp.bin.ihex new file mode 100644 index 000000000000..52361086c280 --- /dev/null +++ b/firmware/radeon/R600_pfp.bin.ihex @@ -0,0 +1,145 @@ +:1000000000D4007100D4007200CA040000A00000F7 +:10001000007E828B0080000300CA040000D4401ED2 +:1000200000EE001E00CA040000A00000007E828BCB +:1000300000C4183800CA240000CA2800009581A80E +:1000400000C41C3A00C3C00000CA080000CA0C006B +:10005000007C744B00C200050099C00000C41C3A2B +:10006000007C744C00C0FFF000042C0400309002AF +:10007000007D250000351402007D350B002554035A +:10008000007CD58000259C030095C00400D5001B92 +:10009000007EDDC1007D9D8000D6801B00D5801BC9 +:1000A00000D4401E00D5401E00D6401E00D6801E43 +:1000B00000D4801E00D4C01E009783D400D5C01E7B +:1000C00000CA08000080001B00CA0C0000E4011EEA +:1000D00000D4001E0080000D00C4183800E4013E6A +:1000E00000D4001E0080000D00C4183800D4401E4B +:1000F00000EE001E00CA040000A00000007E828BFB +:1001000000E4011E00D4001E00D4401E00EE001EBC +:1001100000CA040000A00000007E828B00E4013EC3 +:1001200000D4001E00D4401E00EE001E00CA0400D1 +:1001300000A00000007E828B00CA180000D4401E80 +:1001400000D5801E0080005400D4007300D4401EEF +:1001500000CA080000CA0C0000CA100000D48019B0 +:1001600000D4C01800D5001700D4801E00D4C01ED3 +:1001700000D5001E00E2001E00CA040000A000001E +:10018000007E828B00CA080000D4806000D4401E2C +:100190000080000200D4801E00CA080000D48061E4 +:1001A00000D4401E0080000200D4801E00CA080057 +:1001B00000CA0C0000D4401E00D4801600D4C01623 +:1001C00000D4801E008001B900D4C01E00C6083EC5 +:1001D00000CA0C0000CA10000094800400CA140079 +:1001E00000E420F300D4201300D5606500D4E01CA7 +:1001F00000D5201C00D5601C0080000200062001F4 +:1002000000C6083E00CA0C0000CA1000009483F724 +:1002100000CA140000E420F30080007A00D4201308 +:1002200000C6083E00CA0C0000CA1000009883EF08 +:1002300000CA140000D400640080008E000000009A +:1002400000C4143200C6183E00C4082F00954005B3 +:1002500000C40C3000D4401E0080000200EE001EDE +:10026000009583F500C4103100D4403300D52065DB +:1002700000D4A01C00D4E01C00D5201C00D40073C6 +:1002800000E4015E00D4001E008001B900062001D8 +:10029000000A200100D6007400C4083600C61040D1 +:1002A0000098800700CC38350095010F00D4001F5E +:1002B00000D460620080000200D4206200CC1433BD +:1002C000008401BC00D4007000D5401E00800002F4 +:1002D00000EE001E00CA0C0000CA100000D4C01AB4 +:1002E000008401BC00D5001A00CC04430035101F67 +:1002F000002C9401007D098B00984005007D15CBF2 +:1003000000D4001A008001B900D4006D003444010B +:1003100000CC0C440098403A00CC2C460095800458 +:1003200000CC0445008001B900D4001A00D4C01AE2 +:1003300000282801008400F300CC10030098801BE3 +:100340000004380C008400F300CC100300988017E0 +:1003500000043808008400F300CC100300988013D8 +:1003600000043804008400F300CC100300988014CB +:1003700000CC1047009A800900CC1448009840DA5D +:1003800000D4006D00CC184400D5001A00D5401AE6 +:10039000008000CC00D5801A0096C0D300D4006D38 +:1003A000008001B900D4006E009AC00300D4006D33 +:1003B00000D4006E0080000200EC007F009AC0CAEA +:1003C00000D4006D008001B900D4006E00CC14038D +:1003D00000CC180300CC1C03007D9103007DD58365 +:1003E000007D190C0035CC1F0035701F007CF0CB50 +:1003F000007CD08B00880000007E8E8B0095C004AE +:1004000000D4006E008001B900D4001A00D4C01AD4 +:1004100000CC080300CC0C0300CC100300CC140368 +:1004200000CC180300CC1C0300CC240300CC280310 +:100430000035C41F0036B01F007C704B0034F01F25 +:10044000007C704B0035701F007C704B007D8881F4 +:10045000007DCCC1007E5101007E9541007C9082E0 +:10046000007CD4C2007C848B009AC003007C8C8BFF +:10047000002C88010098809C00D4006D0098409A60 +:1004800000D4006E00CC084700CC0C4800CC1044CF +:1004900000D4801A00D4C01A0080010400D5001ACC +:1004A00000CC083200D40032009482D800CA0C007C +:1004B00000D4401E0080000200D4001E00E4011E93 +:1004C00000D4001E00CA080000CA0C0000CA1000B8 +:1004D00000D4401E00CA140000D4801E00D4C01EE8 +:1004E00000D5001E00D5401E00D54034008000021B +:1004F00000EE001E0028040400E2001A00E2001AC8 +:1005000000D4401A00CA380000CC080300CC0C0309 +:1005100000CC0C0300CC0C03009882BC000000004F +:10052000008401BC00D7806F0080000200EE001F35 +:1005300000CA040000C2FF0000CC083400C13FFF25 +:10054000007C74CB007CC90B007D010F009902AFC9 +:10055000007C738B008401BC00D7806F0080000298 +:1005600000EE001F00CA080000281900007D898BDA +:10057000009580140028140400CA0C0000CA100062 +:1005800000CA1C0000CA240000E2001F00D4C01AE8 +:1005900000D5001A00D5401A00CC180300CC2C035B +:1005A00000CC2C0300CC2C03007DA58B007D9C4748 +:1005B00000984296000000000080016400D4C01A38 +:1005C00000D4401E00D4801E0080000200EE001EF9 +:1005D00000E4011E00D4001E00D4401E00EE001EE8 +:1005E00000CA040000A00000007E828B00E4013EEF +:1005F00000D4001E00D4401E00EE001E00CA0400FD +:1006000000A00000007E828B00CA080000248C0637 +:10061000000CCC060098C00600CC104900990004DC +:1006200000D4007100E4011E00D4001E00D4401E5E +:1006300000D4801E0080000200EE001E00CA0800E8 +:1006400000CA0C000034D018002510010095001FCE +:1006500000C17FFF00CA100000CA140000CA1800C1 +:1006600000D4801D00D4C01D007DB18B00C14202AA +:1006700000C2C00100D5801D0034DC0E007D5D4C41 +:10068000007F734C00D7401E00D5001E00D5401ED1 +:1006900000C1420000C2C00000099C010031DC1012 +:1006A000007F5F4C007F734C007D838000D5806F9E +:1006B00000D5806600D7401E00EC005E00C8240212 +:1006C000008001B900D6007400D4401E00D4801E02 +:1006D00000D4C01E0080000200EE001E0080000258 +:1006E00000EE001F00D4001F0080000200D4001F95 +:1006F00000D4001F0088000000D4001F000000008C +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:10080000000101740002017B0003009000040080DD +:100810000005000500060040000700330008012F16 +:1008200000090047000A0037001001B7001700A4B4 +:100830000022013D0023014C002000B500240128C6 +:100840000027004E0028006B002A0061002B005397 +:10085000002F00660032008800340182003C0159FC +:10086000003F00730041018F0044013100550176C3 +:100870000056017D0060000C006100350062003907 +:1008800000630039006400390065003900660039F2 +:10089000006700390068003B00690042006A0049B7 +:1008A000006B0049006C0049006D0049006E004972 +:1008B000006F0049007301B7000000070000000747 +:1008C000000000070000000700000007000000070C +:1008D00000000007000000070000000700000007FC +:1008E00000000007000000070000000700000007EC +:1008F00000000007000000070000000700000007DC +:00000001FF diff --git a/firmware/radeon/RS600_cp.bin.ihex b/firmware/radeon/RS600_cp.bin.ihex new file mode 100644 index 000000000000..4a895016aca4 --- /dev/null +++ b/firmware/radeon/RS600_cp.bin.ihex @@ -0,0 +1,130 @@ +:10000000000000004200E000000000004000E000AE +:1000100000000008000000A000000008000000A48C +:10002000000000004A554B4A000000004A4A44675D +:100030000000000055526F75000000004A7E7D658B +:10004000000000004AE74AF6000000004AD34A4A8E +:1000500000000000D689898900000000CD4ADDCF6C +:10006000000000008EBE4AE200000000C38A8A8AB7 +:10007000000000004A0F8CC800000004000CA00023 +:1000800000000038000D0012000000040000E8B479 +:1000900000000038000D0014000000040000E8B665 +:1000A00000000038000D0016000000040000E854B5 +:1000B00000000038000D0018000000040000E855A2 +:1000C00000000038000D001A000000040000E8568F +:1000D00000000038000D001C000000040000E8577C +:1000E00000000038000D001E000000040000E8249D +:1000F00000000038000D0020000000040000E8258A +:1001000000000038000D0022000000040000E8306C +:1001100000000038000D0024000000040000F0C0C2 +:1001200000000038000D0026000000040000F0C1AF +:1001300000000038000D0028000000040000F0411D +:1001400000000038000D002A000000040000F184C7 +:1001500000000038000D002C000000040000F185B4 +:1001600000000038000D002E000000040000F186A1 +:1001700000000038000D0030000000040000F1878E +:1001800000000038000D0032000000040000F18083 +:1001900000000038000D0034000000040000F3935C +:1001A00000000038000D0036000000040000F38A53 +:1001B00000000038000D0038000000040000F38E3D +:1001C000000000040000E821000000040140A0003D +:1001D00000000018000000430000000400CCE8000C +:1001E00000000004001B000100000004080048009B +:1001F00000000004001B000100000004080048008B +:1002000000000004001B000100000004080048007A +:10021000000000080000003A000000000000A000FC +:10022000000000042000451D000000040000E580DF +:1002300000000004000CE581000000040800458077 +:1002400000000004000CE5810000000800000047E9 +:10025000000000000000A00000000004000C2000CE +:10026000000000040000E50E000000040003200070 +:10027000000000280002205100000024000000516E +:10028000000000040800450F000000080000A04B1B +:10029000000000040000E565000000040000E566C1 +:1002A00000000008000000520000000403CCA5B4C8 +:1002B00000000004054320000000000400022000AC +:1002C000000000304CCCE05E0000000408274565CB +:1002D000000000300000005E0000000408004564DB +:1002E000000000040000E566000000080000005562 +:1002F00000000010008020610000000400202000A9 +:1003000000000004001B00FF00000010010000645A +:1003100000000004001F200000000004001C00FF7B +:100320000000000C0000000000000030000000721F +:100330000000000800000055000000040000E57601 +:10034000000000040000E577000000040000E50E56 +:10035000000000040000E50F000000040140A000C0 +:100360000000001800000069000000C200C0E5F9AC +:100370000000000800000069000000040014E50E01 +:10038000000000040040E50F0000000800C0006C01 +:10039000000000040000E570000000040000E571AA +:1003A0000000000C0000E572000000040000A00046 +:1003B000000000040140A000000000040000E56807 +:1003C00000000004000C200000000018000000766F +:1003D00000000004000B00000000000418C0E562EB +:1003E00000000008000000780000000800C000774E +:1003F00000000004000700D5000000380000008461 +:1004000000000030000CA08600000004080045BB7E +:1004100000000030000C2087000000000800E5BC50 +:10042000000000040000E5BB000000000000E5BC87 +:100430000000000C00120000000000040012000088 +:100440000000000C001B0002000000040000A000DF +:10045000000000040000E821000000000000E800A7 +:10046000000000040000E821000000000000E82E69 +:100470000000000402CCA0000000000400140000F2 +:1004800000000004000CE1CC00000004050DE1CDEB +:10049000000000040040000000000018000000966A +:1004A0000000000400C0A00000000008000000934D +:1004B0000000002000000098000000004200E00062 +:1004C000000000380000009F00000004000CA000A5 +:1004D000000000040014000000000004000C2000D4 +:1004E000000000040016000000000004700CE00092 +:1004F000000000080014009B000000004000E00025 +:10050000000000040240000000000004400EE00073 +:100510000000000402400000000000004000E00075 +:1005200000000004000C2000000000040240E51B55 +:10053000000000050080E50A000000050080E50BD2 +:10054000000000040022000000000004000700D5A5 +:1005500000000038000000B200000030000C2087CE +:10056000000000050880E5BD00000030000C20867A +:10057000000000050800E5BB00000030000C2087EB +:10058000000000050880E5BC00000008000000B580 +:10059000000000050080E5BD000000050000E5BB8F +:1005A000000000050080E5BC000000040021000000 +:1005B00000000004028000000000001800C000B924 +:1005C000000000404180E00000000024000000BB6B +:1005D0000000000C010000000000000C0100E51DFF +:1005E00000000004000045BB00000008000080B5CA +:1005F000000000040000F3CE000000040140A00051 +:100600000000000400CC20000000004008C053CFD0 +:100610000000000000008000000000040000F3D291 +:10062000000000040140A0000000000400CC2000F5 +:100630000000004008C053D300000000000080000C +:10064000000000040000F39D000000040140A00031 +:100650000000000400CC20000000004008C0539EB1 +:1006600000000000000080000000000403C008300B +:10067000000000004200E000000000040000A000B4 +:1006800000000004200045E0000000000000E5E15B +:10069000000000000000000100000004000700D27C +:1006A000000000000800E3940000000000000000CB +:1006B000000000040000E8C4000000040000E8C5D9 +:1006C000000000040000E8C6000000040000E92863 +:1006D000000000040000E929000000040000E92AED +:1006E00000000008000000D6000000040000E92817 +:1006F000000000040000E929000000040000E92ACD +:1007000000000008000000DD0000000000E001160D +:1007100000000004000700E1000000040800401C85 +:1007200000000004200050E7000000040000E01D6D +:1007300000000008000000E40000000402C02000E7 +:10074000000000040006000000000034000000EB80 +:1007500000000008000000E8000000040000800025 +:1007600000000000C000E0000000000000000000E9 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B00000000004000C200000000004001D0018D0 +:1007C00000000004001A000100000034000000FBDB +:1007D000000000080000004A000000080500A04AD0 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:00000001FF +/* production radeon ucode r1xx-r6xx */ diff --git a/firmware/radeon/RS690_cp.bin.ihex b/firmware/radeon/RS690_cp.bin.ihex new file mode 100644 index 000000000000..689627441d8b --- /dev/null +++ b/firmware/radeon/RS690_cp.bin.ihex @@ -0,0 +1,130 @@ +:1000000000000008000000DD00000008000000DF24 +:1000100000000008000000A000000008000000A48C +:10002000000000004A554B4A000000004A4A44675D +:100030000000000055526F75000000004A7E7D658B +:10004000000000004AD74AF6000000004AC94A4AA8 +:1000500000000000CC89898900000000C34AD3C594 +:10006000000000008E4A4A4A000000004A8A8A8A3C +:10007000000000004A0F8C4A00000004000CA000A1 +:1000800000000038000D0012000000040000E8B479 +:1000900000000038000D0014000000040000E8B665 +:1000A00000000038000D0016000000040000E854B5 +:1000B00000000038000D0018000000040000E855A2 +:1000C00000000038000D001A000000040000E8568F +:1000D00000000038000D001C000000040000E8577C +:1000E00000000038000D001E000000040000E8249D +:1000F00000000038000D0020000000040000E8258A +:1001000000000038000D0022000000040000E8306C +:1001100000000038000D0024000000040000F0C0C2 +:1001200000000038000D0026000000040000F0C1AF +:1001300000000038000D0028000000040000F0411D +:1001400000000038000D002A000000040000F184C7 +:1001500000000038000D002C000000040000F185B4 +:1001600000000038000D002E000000040000F186A1 +:1001700000000038000D0030000000040000F1878E +:1001800000000038000D0032000000040000F18083 +:1001900000000038000D0034000000040000F3935C +:1001A00000000038000D0036000000040000F38A53 +:1001B00000000038000D0038000000040000F38E3D +:1001C000000000040000E821000000040140A0003D +:1001D00000000018000000430000000400CCE8000C +:1001E00000000004001B000100000004080048009B +:1001F00000000004001B000100000004080048008B +:1002000000000004001B000100000004080048007A +:10021000000000080000003A000000000000A000FC +:10022000000000042000451D000000040000E580DF +:1002300000000004000CE581000000040800458077 +:1002400000000004000CE5810000000800000047E9 +:10025000000000000000A00000000004000C2000CE +:10026000000000040000E50E000000040003200070 +:10027000000000280002205100000024000000516E +:10028000000000040800450F000000080000A04B1B +:10029000000000040000E565000000040000E566C1 +:1002A00000000008000000520000000403CCA5B4C8 +:1002B00000000004054320000000000400022000AC +:1002C000000000304CCCE05E0000000408274565CB +:1002D000000000300000005E0000000408004564DB +:1002E000000000040000E566000000080000005562 +:1002F00000000010008020610000000400202000A9 +:1003000000000004001B00FF00000010010000645A +:1003100000000004001F200000000004001C00FF7B +:100320000000000C0000000000000030000000721F +:100330000000000800000055000000040000E57601 +:10034000000000040000E577000000040000E50E56 +:10035000000000040000E50F000000040140A000C0 +:100360000000001800000069000000C200C0E5F9AC +:100370000000000800000069000000040014E50E01 +:10038000000000040040E50F0000000800C0006C01 +:10039000000000040000E570000000040000E571AA +:1003A0000000000C0000E572000000040000A00046 +:1003B000000000040140A000000000040000E56807 +:1003C00000000004000C200000000018000000766F +:1003D00000000004000B00000000000418C0E562EB +:1003E00000000008000000780000000800C000774E +:1003F00000000004000700CB00000038000000846B +:1004000000000030000CA08600000004080045BB7E +:1004100000000030000C2087000000000800E5BC50 +:10042000000000040000E5BB000000000000E5BC87 +:100430000000000C00120000000000040012000088 +:100440000000000C001B0002000000040000A000DF +:10045000000000040000E821000000000000E800A7 +:10046000000000040000E821000000000000E82E69 +:100470000000000402CCA0000000000400140000F2 +:1004800000000004000CE1CC00000004050DE1CDEB +:10049000000000040040000000000018000000966A +:1004A0000000000400C0A00000000008000000934D +:1004B0000000002000000098000000004200E00062 +:1004C000000000380000009F00000004000CA000A5 +:1004D000000000040014000000000004000C2000D4 +:1004E000000000040016000000000004700CE00092 +:1004F000000000080014009B000000004000E00025 +:10050000000000040240000000000004400EE00073 +:100510000000000402400000000000004000E00075 +:100520000000002C0010000000000000000040004F +:1005300000000004080045C8000000040024000575 +:100540000000000408004D0B00000004000C200017 +:10055000000000040240E51B000000050080E50AE1 +:10056000000000050080E50B0000000400220000F0 +:1005700000000004000700CB00000038000000B7B6 +:1005800000000030000C2087000000050880E5BD59 +:1005900000000030000C2086000000050800E5BBCC +:1005A00000000030000C2087000000050880E5BC3A +:1005B00000000008000000BA000000050080E5BD52 +:1005C000000000050000E5BB000000050080E5BC60 +:1005D0000000000400210000000000040280000070 +:1005E0000000001800C000BE000000404180E00094 +:1005F00000000024000000C00000000C010000000A +:100600000000000C0100E51D00000004000045BBD7 +:1006100000000008000080BA0000000403C0083099 +:10062000000000004200E000000000040000A00004 +:1006300000000004200045E0000000000000E5E1AB +:10064000000000000000000100000004000700C8D6 +:10065000000000000800E39400000000000000001B +:10066000000000040000E8C4000000040000E8C529 +:10067000000000040000E8C6000000040000E928B3 +:10068000000000040000E929000000040000E92A3D +:1006900000000008000000CC000000040000E92871 +:1006A000000000040000E929000000040000E92A1D +:1006B00000000008000000D30000000402C0200079 +:1006C000000000040006000000000034000000DB11 +:1006D00000000008000000D80000000400008000B6 +:1006E00000000000C000E00000000030000000E159 +:1006F000000000004200E00000000030000000E1C7 +:10070000000000004000E000000000040025001B85 +:100710000000000400230000000000040025000584 +:1007200000000034000000E60000000C00000000A3 +:10073000000000040024400000000004080045C838 +:1007400000000004002400050000000C08004D0B10 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B00000000004000C200000000004001D0018D0 +:1007C00000000004001A000100000034000000FBDB +:1007D000000000080000004A000000080500A04AD0 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:00000001FF +/* production radeon ucode r1xx-r6xx */ diff --git a/firmware/radeon/RS780_me.bin.ihex b/firmware/radeon/RS780_me.bin.ihex new file mode 100644 index 000000000000..6479c106b91f --- /dev/null +++ b/firmware/radeon/RS780_me.bin.ihex @@ -0,0 +1,1345 @@ +:1000000000000000C020040000000000000000000C +:1000100000A0000A000000000000FFFF00284621A9 +:100020000000000000000000D900480000000000AF +:1000300000000000C02004000000000000000000DC +:1000400000A0000A000000000000000000E0000026 +:100050000000000000010000C02946200000000050 +:1000600000000000D900480000000000000000006F +:10007000C0200400000000000000000000A0000AF2 +:10008000000000008100000000204411000000007A +:1000900000000001002048110000000000042004BE +:1000A0000060441100000622000000000060000013 +:1000B000000005D10000000000600000000005DE27 +:1000C00000000000C02008000000000000000F0039 +:1000D000002816220000000000000008002116255C +:1000E000000000000000001800203625000000007D +:1000F0008D000000002044110000000000000004FA +:10010000002F022500000000000000000CE00000AD +:1001100000000018004120000040481100000019B4 +:100120000042200000204811000000008E00000066 +:1001300000204411000000000000002800204A2D8B +:1001400000000000900000000020441100000000AA +:100150000000000000204805000000000000000C26 +:1001600000211622000000000000000300281625D0 +:10017000000000000000001900211A220000000009 +:100180000000000400281A26000000000000000003 +:10019000002914C5000000000000001900203625C9 +:1001A0000000000000000000003A140200000000FF +:1001B00000000016002116250000000000000003CA +:1001C00000281625000000000000001700200E2D5A +:1001D00000000000FFFFFFFC00280E2300000000CD +:1001E00000000000002914A3000000000000001718 +:1001F00000203625000000000000800000280E22AC +:10020000000000000000000700220E230000000094 +:10021000000000000029386E0000000020000000EF +:1002200000280E22000000000000000600210E231E +:1002300000000000000000000029386E00000000EF +:100240000000000000220222000000000000000068 +:1002500014E0000000000038000000002EE0000064 +:1002600000000035000000002CE000000000003716 +:100270000000000000400E2D0000003900000008C2 +:1002800000200E2D00000000000000090040122D8B +:10029000000000460000000100400E2D0000003963 +:1002A00000000000C0200C0000000000003FFFFC28 +:1002B0000028122300000000000000020022122487 +:1002C000000000000000001F00211E2300000000AD +:1002D0000000000014E000000000003E00000008E4 +:1002E00000401C11000000410000000D00201E2DE8 +:1002F000000000000000000F00281E270000000082 +:100300000000000300221E27000000007FC0000044 +:1003100000281A23000000000000001400211A2603 +:10032000000000000000000100331A260000000059 +:100330000000000800221A26000000000000000053 +:1003400000290CC700000000000000270020362410 +:100350000000000000007F000028122100000000C3 +:1003600000001400002F0224000000000000000024 +:100370000CE000000000004B0000000100290E23EB +:10038000000000000000000E0020362300000000E6 +:100390000000E0000020441100000000FFF8000011 +:1003A00000294A230000000000000000003A2C024F +:1003B000000000000000000200220E2B00000000E0 +:1003C000FC00000000280E23000000000000000FC9 +:1003D000002036230000000000001FFF00294A23F0 +:1003E000000000000000002700204A2D000000004F +:1003F000000000000020481100000000000000295B +:1004000000200E2D00000000060A020000294A23E9 +:100410000000000000000000002048110000000063 +:100420000000000000204811000000000000000152 +:1004300000210222000000000000000014E0000083 +:1004400000000061000000002EE000000000005FDE +:10045000000000002CE000000000005E0000000032 +:1004600000400E2D000000620000000100400E2D33 +:10047000000000620000000A00200E2D00000000B5 +:100480000000000B0040122D0000006A0000000078 +:10049000C0200C0000000000003FFFFC00281223D9 +:1004A00000000000000000020022122400000000F2 +:1004B0007FC0000000281623000000000000001488 +:1004C0000021162500000000000000010033162561 +:1004D000000000008000000000280E230000000043 +:1004E0000000000000290CA3000000003FFFFC00FA +:1004F00000290E23000000000000001F00211E2321 +:10050000000000000000000014E000000000006D8A +:100510000000010000401C11000000700000000DF0 +:1005200000201E2D00000000000000F000281E2703 +:10053000000000000000000400221E270000000050 +:100540008100000000204411000000000000000DA8 +:100550000020481100000000FFFFF0FF00281A30C3 +:10056000000000000000A02800204411000000004E +:1005700000000000002948E6000000000000A0186C +:1005800000204411000000003FFFFFFF00284A2325 +:10059000000000000000A010002044110000000036 +:1005A00000000000002048040000000000000030AF +:1005B0000020162D00000000000000020029162572 +:1005C0000000000000000030002036250000000080 +:1005D000000000250020162D000000000000000093 +:1005E000002F00A300000000000000000CC000006D +:1005F00000000083000000260020162D00000000EF +:1006000000000000002F00A4000000000000000017 +:100610000CC000000000008400000000004000004A +:100620000000008A000000250020362300000000A2 +:100630000000002600203624000000000000001703 +:1006400000201E2D000000000000000200210227F3 +:10065000000000000000000014E000000000008A1C +:100660000000000000600000000005FF0000000026 +:1006700000600000000005F30000000200210E22CF +:10068000000000000000000014C000000000008D09 +:1006900000000012C040362000000093000000005F +:1006A0002EE0000000000091000000002CE000009F +:1006B000000000900000000200400E2D000000929B +:1006C0000000000300400E2D000000920000000C0E +:1006D00000200E2D00000000000000120020362334 +:1006E000000000000000000300210E2200000000B6 +:1006F0000000000014C00000000000980000A00CE2 +:10070000002044110000000000000000C02048004C +:100710000000000000000000C0404800000000A0F1 +:100720000000A00C002044110000000000000000A8 +:100730000020481100000000000000002EE0000032 +:100740000000009E000000002CE000000000009D62 +:100750000000000200400E2D0000009F000000037A +:1007600000400E2D0000009F0000000C00200E2D08 +:10077000000000000000000000204803000000000E +:1007800000000000003A0C0200000000003F0000E2 +:1007900000280E23000000000000001000210E239E +:1007A00000000000000000110020362300000000BF +:1007B0000000001E0021022B0000000000000000CD +:1007C00014C00000000000A700000016C020362062 +:1007D000000000000000001F0021022B00000000AC +:1007E0000000000014C00000000000AA0000001576 +:1007F000C0203620000000000000000800210E2B61 +:10080000000000000000007F00280E230000000010 +:1008100000000000002F0223000000000000000084 +:100820000CE00000000000E10000000027000000D4 +:10083000000000000000000000600000000002A3B3 +:1008400000000001002F0223000000000000000053 +:100850000AE00000000000B300000000006000009B +:100860000000013A81000000002044110000000057 +:100870000000000600204811000000000000000CED +:1008800000221E300000000099800000002044116A +:1008900000000000000000040020122D00000000F5 +:1008A00000000008002212240000000000000010D8 +:1008B00000201811000000000000000000291CE4C6 +:1008C0000000000000000000006048070000012F49 +:1008D0009B00000000204411000000000000000008 +:1008E00000204802000000009C000000002044118D +:1008F00000000000000000000033146F0000000042 +:100900000000000100333E23000000000000000052 +:10091000D9004800000000000000000000203C0555 +:1009200000000000810000000020441100000000D1 +:100930000000000E00204811000000000000000030 +:1009400000201010000000000000E007002044110B +:10095000000000000000000F0021022B000000003A +:100960000000000014C00000000000CB00F8FF08E9 +:1009700000204811000000009800000000404811CD +:10098000000000DC000000F000280E220000000043 +:10099000000000A0002F0223000000000000000063 +:1009A0000CC00000000000DA0000001100200E2D35 +:1009B0000000000000000001002F022300000000E2 +:1009C000000000000CE00000000000D50000000264 +:1009D000002F022300000000000000000CE00000D7 +:1009E000000000D400003F0000400C11000000D6C1 +:1009F00000001F0000400C11000000D600000F0096 +:100A000000200C11000000000038000900294A23D2 +:100A1000000000003F00000000280E2B0000000036 +:100A20000000000200220E2300000000000000076A +:100A300000494A23000000DC00380F09002048115B +:100A400000000000680000070020481100000000BE +:100A50000000000800214A270000000000000000FC +:100A60000020481100000000060A020000294A2464 +:100A700000000000000000000020481100000000FD +:100A80000000000000204811000000000000A20249 +:100A9000002044110000000000FF000000280E228A +:100AA000000000000000008000294A230000000030 +:100AB0000000002700200E2D00000000000000268E +:100AC0000020122D0000000000000000002F008315 +:100AD00000000000000000000CE00000000000EA40 +:100AE0000000000000600000000005F900000000A8 +:100AF00000400000000000EB00000000006000006B +:100B0000000005FC000000070020222D000000006E +:100B10000000000500220E2200000000001000006E +:100B200000280E23000000000000000000292068BB +:100B30000000000000000000003A0C02000000006D +:100B4000000000EF00280E2300000000000000005D +:100B500000292068000000000000001700200E2D72 +:100B6000000000000000000300210223000000003C +:100B70000000000014E00000000000F80000000B7E +:100B800000210228000000000000000014C0000046 +:100B9000000000F8000004000029222800000000E6 +:100BA0000000001400203628000000000000001C97 +:100BB00000210E22000000000000000014C0000010 +:100BC000000000FD0000A30C002044110000000004 +:100BD0000000000000204811000000000000001E7E +:100BE00000210E22000000000000000014C00000E0 +:100BF0000000010B0000A30F0020441100000000C2 +:100C00000000001100200E2D000000000000000177 +:100C1000002F022300000000000000000CC00000B4 +:100C200000000104FFFFFFFF004048110000010B1E +:100C300000000002002F022300000000000000005E +:100C40000CC00000000001070000FFFF0040481139 +:100C50000000010B00000004002F02230000000030 +:100C6000000000000CC000000000010A000000FFAE +:100C7000004048110000010B000000010020481155 +:100C8000000000000002C400002044110000000029 +:100C90000000001F00210E220000000000000000E4 +:100CA00014C00000000001120000001040210E20BE +:100CB00000000000000000130020362300000000A8 +:100CC0000000001840224A20000000000000001030 +:100CD000C0424A20000001140000000000200C1156 +:100CE0000000000000000013002036230000000078 +:100CF000000000000020481100000000000000007B +:100D000000204811000000000000000A002010111F +:100D10000000000000000000002F0224000000007E +:100D2000000000000CE000000000011B00000000BB +:100D300000204811000000000000000100531224B0 +:100D400000000117FFBFFFFF00283A2E000000003F +:100D50000000001B00210222000000000000000033 +:100D600014C000000000012E81000000002044118A +:100D7000000000000000000D0020481100000000ED +:100D80000000001800220E3000000000FC000000EF +:100D900000280E2300000000810000000020441104 +:100DA000000000000000000E0020481100000000BC +:100DB0000000000000201010000000000000E00E05 +:100DC000002044110000000007F8FF08002048112F +:100DD000000000000000000000294A23000000007D +:100DE0000000001C00201E2D000000000000000874 +:100DF00000214A27000000000000000000204811E8 +:100E000000000000060A020000294A240000000039 +:100E10000000000000204811000000000000000059 +:100E200000204811000000000000000000800000C9 +:100E300000000000810000000020441100000000BC +:100E40000000000100204811000000000000217C8B +:100E50000020441100000000008000000020481124 +:100E60000000000000000000002048060000000014 +:100E70000000000800214A270000000000000000D8 +:100E800017000000000000000004217F00604411F2 +:100E9000000006220000001F0021023000000000B8 +:100EA0000000000014C00000000006210000000443 +:100EB00000404C1100000135810000000020441169 +:100EC00000000000000000010020481100000000A8 +:100ED000000021F800204411000000000000001C68 +:100EE0000020481100000000000421F900604411B6 +:100EF0000000062200000011002102300000000066 +:100F00000000000014E000000000013C00000000B0 +:100F100000800000000000000000000000600000F1 +:100F20000000000B00000000006004110000031529 +:100F3000000000000020041100000000000000007C +:100F400000600811000001B2000000000060000015 +:100F5000000001600000FFFF40280E20000000009C +:100F600000000010C0211220000000000000FFFF60 +:100F7000402806200000000000000010C0210A20C8 +:100F800000000000000000000034146100000000B8 +:100F90000000000000741882000002BB0001A1FDE7 +:100FA00000604411000002E000003FFF002F022F0C +:100FB00000000000000000000CC00000000001471D +:100FC00000000000C040040000000001000000001C +:100FD000006000000000000B000000000060041131 +:100FE00000000315000000000020041100000000B4 +:100FF0000000000000600811000001B200003FFF87 +:10100000002F022F00000000000000000CE0000094 +:10101000000000000000000000600000000001600F +:101020000000001040210E20000000000000FFFF23 +:10103000C0281220000000000000001040211620EF +:10104000000000000000FFFFC0681A20000002BB83 +:101050000001A1FD00604411000002E000003FFF1C +:10106000002F022F00000000000000000CC0000054 +:101070000000015800000000C04004000000000112 +:101080000000225C0020441100000000000000016C +:1010900000300A2F000000000000000100210A2299 +:1010A000000000000000000300384A220000000099 +:1010B0000000225600204411000000000000001A29 +:1010C00000204811000000000000A1FC0020441195 +:1010D0000000000000000001008048110000000036 +:1010E00000000000006000000000000B0000000095 +:1010F000006000000000018F0000000000600000A0 +:10110000000001A000003FFF002F022F00000000A0 +:10111000000000000CE000000000000000000000E3 +:1011200000202C0800000000000000000020241116 +:101130000000000000000000002028110000000056 +:10114000000022560020441100000000000000169C +:1011500000204811000000000000225C0020441123 +:101160000000000000000003002048110000000003 +:1011700093800000002044110000000000000002E5 +:1011800000221E290000000000000000007048EB53 +:101190000000019C0000000000600000000002BB95 +:1011A00000000001403306200000000000000000A5 +:1011B000C03024090000000000003FFF002F022F74 +:1011C00000000000000000000CE000000000000033 +:1011D0000000000000600000000002A3000000000A +:1011E000002F022100000000000000000AE00000C3 +:1011F0000000018100000000006000000000013AD2 +:101200000000000000400000000001869500000082 +:10121000002044110000000000000000002F022107 +:1012200000000000000000000CE00000000001864B +:1012300000000000C0204800000000000000000185 +:10124000005306210000018292000000002044119A +:101250000000000000000000C0604800000001978E +:101260000001A1FD00204411000000000000001159 +:101270000020062D00000000000000000078042A75 +:10128000000002FB00000000002028090000000010 +:1012900000003FFF002F022F0000000000000000B0 +:1012A0000CC000000000017400000000C0400400F9 +:1012B000000000010000021000600411000003158E +:1012C00000003FFF002F022F000000000000000080 +:1012D0000CE000000000019400000015C020362042 +:1012E0000000000000000016C020362000000000B2 +:1012F0003F800000002004110000000046000000B4 +:1013000000600811000001B2000000000080000031 +:10131000000000000000A1FC0020441100000000BB +:1013200000003FFF002F022F00000000000000001F +:101330000CC000000000019B00000001008048116B +:1013400000000000000000210080481100000000A3 +:101350000000FFFF40280E200000000000000010E9 +:10136000C0211220000000000000FFFF40281620CE +:101370000000000000000010C0811A2000000000E2 +:101380008100000000204411000000000000000661 +:1013900000204811000000000000000800221E305C +:1013A000000000000000002900201A2D00000000AD +:1013B0000000E0000020441100000000FFFBFF09D6 +:1013C00000204811000000000000000F0020222D26 +:1013D0000000000000001FFF00294A280000000054 +:1013E000000000060020222D000000000000000088 +:1013F000002920E80000000000000000002048084C +:101400000000000000000000002048110000000063 +:10141000060A020000294A26000000000000000021 +:1014200000204811000000000000000000204811CA +:101430000000000000000100002018110000000062 +:101440000000000800621E280000012F00000008B4 +:1014500000822228000000000002C0000020441189 +:10146000000000000000001500600E2D000001BD0E +:101470000000001600600E2D000001BD0000C00835 +:1014800000204411000000000000001700200E2D75 +:10149000000000000000000014C00000000001B9BE +:1014A0000000000000200411000000000000000007 +:1014B0000020480100000000390000000020481111 +:1014C00000000000000000000020481100000000A3 +:1014D000000000000080480200000000000000182A +:1014E00000202E2D0000000000000000003B0D63D6 +:1014F000000000000000000800224A230000000055 +:101500000000001000224A23000000000000001824 +:1015100000224A2300000000000000000080480371 +:101520000000000000000000006000000000000B50 +:10153000000010000060041100000315000000000E +:1015400000200411000000000000000000600811ED +:10155000000001B2000000070021062F000000007B +:101560000000001300200A2D000000000000000110 +:1015700000202C11000000000000FFFF4028222066 +:10158000000000000000000F0026222800000000DC +:101590000000001040212620000000000000000F85 +:1015A000002626290000000000000000002028027C +:1015B000000000000000225600204411000000003E +:1015C0000000001B00204811000000000000000087 +:1015D000002F022100000000000000000CE00000CD +:1015E000000001E00000225C002044110000000027 +:1015F0000000008100204811000000000000A1FC54 +:1016000000204411000000000000000100204811EB +:10161000000000000000008000201C1100000000FD +:1016200000000000002F0227000000000000000062 +:101630000CE00000000001DC000000000060000081 +:10164000000001E90000000100531E27000001D83E +:101650000000000100202C11000000000000001F0D +:1016600000280A22000000000000001F00282A2A8B +:10167000000000000000000100530621000001D11D +:101680000000225C00204411000000000000000265 +:1016900000304A2F000000000000A1FC002044118F +:1016A00000000000000000010020481100000000C0 +:1016B0000000000100301E2F0000000000000000AC +:1016C000002F022700000000000000000CE00000D6 +:1016D000000000000000000000600000000001E9C0 +:1016E0000000000100531E27000001E50000FFFF7D +:1016F00040280E20000000000000000F00260E23EE +:101700000000000000000010C021122000000000B6 +:101710000000000F0026122400000000000000005E +:1017200000201411000000000000000000601811EB +:10173000000002BB0001A1FD0020441100000000D8 +:1017400000000000002F022B00000000000000003D +:101750000CE00000000001F8000000100022162834 +:1017600000000000FFFF0000002816250000000018 +:101770000000FFFF00281A29000000000000000000 +:10178000002948C500000000000000000020480AB1 +:10179000000000000000000000202C1100000000EC +:1017A000000000100022162300000000FFFF0000D0 +:1017B00000281625000000000000FFFF00281A2462 +:1017C0000000000000000000002948C500000000E3 +:1017D0000000000000731503000002050000000077 +:1017E0000020180500000000000000000073152410 +:1017F0000000020500000000002D14C500000000DC +:1018000000000000003008A20000000000000000FE +:101810000020480200000000000000000020280214 +:101820000000000000000000002020030000000075 +:101830000000000000802404000000000000000FF1 +:1018400000210225000000000000000014C000007C +:101850000000062100000000002B1405000000001D +:1018600000000001009016250000000000000000AC +:10187000006000000000000B000000000060041188 +:10188000000003150000000000200411000000000B +:101890000000000000600811000001B200002256A4 +:1018A00000204411000000000000001A00294A2214 +:1018B0000000000000000000C02000000000000048 +:1018C00000003FFF002F022F00000000000000007A +:1018D0000CE000000000000000000000C020040038 +:1018E000000000000000225C002044110000000005 +:1018F0000000000300384A21000000000000A1FCA5 +:1019000000204411000000000000000100204811E8 +:10191000000000000000FFFF40281220000000002F +:1019200000000010C0211A20000000000000FFFF8E +:1019300040280E200000000000000010C0211620EA +:10194000000000000000000000741465000002BBED +:101950000001A1FD00604411000002E00000000150 +:10196000003306210000000000000000002F0221CB +:1019700000000000000000000CC000000000021980 +:1019800000003FFF002F022F0000000000000000B9 +:101990000CC000000000021200000000C040040063 +:1019A000000000010000000000600000000005DEF3 +:1019B000000000000040040F0000021300000000BF +:1019C00000600000000005D1000000000060000081 +:1019D000000005DE00000210006004110000031585 +:1019E0000000000000600000000001A000000000F6 +:1019F000006000000000019C00000000006000008A +:101A0000000002BB0000000000600000000002A314 +:101A1000938000000020441100000000000000003E +:101A2000002048080000000000000000002F022FE6 +:101A300000000000000000000AE000000000023288 +:101A400000000000006000000000013A00000000FB +:101A50000040000000000236950000000020441104 +:101A60000000000000000000002F022F0000000016 +:101A7000000000000CE00000000002360000000042 +:101A8000C0404800000002339200000000204411D2 +:101A90000000000000000000C0204800000000001E +:101AA0000000225600204411000000000000001633 +:101AB00000204811000000000000225C00204411BA +:101AC000000000000000000300204811000000009A +:101AD0000000A1FC002044110000000000000001F3 +:101AE00000204811000000000001A1FD0020441169 +:101AF000000000000000000000600411000002FB74 +:101B000000000000C04004000000000100000000D0 +:101B100000600000000005D10000A00C002044116E +:101B20000000000000000000C0204800000000008D +:101B300000000000C040480000000000000000005D +:101B4000006000000000000B0000001840210A2087 +:101B50000000000000000003002F0222000000002F +:101B6000000000000AE000000000024C0000001429 +:101B70000020222D00000000000801010029222879 +:101B800000000000000000140020362800000000C3 +:101B90000000A30C00204411000000000000000021 +:101BA000C02048000000000000000000C0204800E5 +:101BB0000000000000000000C0404800000002518A +:101BC00000000000006000000000000B000000109A +:101BD00000600411000003153F8000000020041184 +:101BE000000000000000000000600811000001B2C9 +:101BF0000000225C002044110000000000000003EF +:101C000000204811000000000000000000600000FB +:101C10000000027C0000001700201E2D00000000C4 +:101C20000000000100211E2700000000000000004D +:101C300014E000000000026A0000001200201E2DC7 +:101C4000000000000000FFFF00281E270000000029 +:101C50000000000000341C2700000000000000000D +:101C600012C000000000025F0000000000201C11F4 +:101C70000000000000000000002F00E50000000050 +:101C80000000000008C00000000002620000000028 +:101C900000201407000000000000001200201E2D8C +:101CA000000000000000001000211E2700000000BE +:101CB0000000000000341C4700000000000000008D +:101CC00012C00000000002670000000000201C118C +:101CD0000000000000000000002F00E600000000EF +:101CE0000000000008C000000000026A00000000C0 +:101CF0000020180700000000000000000060000045 +:101D0000000002C100002256002044110000000023 +:101D1000000000000034202300000000000000004C +:101D200012C00000000002720000000000342044D5 +:101D3000000000000000000012C00000000002715E +:101D40000000001600404811000002760000001854 +:101D500000404811000002760000000000342044DA +:101D6000000000000000000012C00000000002752A +:101D70000000001700404811000002760000001922 +:101D800000204811000000000000A1FC00204411C8 +:101D900000000000000000010020481100000000C9 +:101DA0000001A1FD00604411000002E900003FFFB6 +:101DB000002F022F00000000000000000CC00000F7 +:101DC0000000025600000000C040040000000001B6 +:101DD0000000001040210620000000000000FFFF6E +:101DE000C0280A20000000000000001040210E2042 +:101DF000000000000000FFFFC028122000000000CB +:101E00000000001040211620000000000000FFFF2D +:101E1000C0881A200000000081000000002044114A +:101E20000000000000000001002048110000000038 +:101E3000000420040060441100000622000000009D +:101E400000600000000005D100000000C06000003C +:101E5000000002A30000000500200A2D0000000081 +:101E60000000000800220A22000000000000002BF1 +:101E700000201A2D000000000000001C00201E2D74 +:101E8000000000000000700000281E270000000075 +:101E90000000000000311CE6000000000000002AE5 +:101EA00000201A2D000000000000000C00221A265D +:101EB0000000000000000000002F00E6000000000D +:101EC0000000000006E00000000002920000000098 +:101ED00000201C11000000000000000000200C1178 +:101EE000000000000000002B00203623000000004E +:101EF0000000001000201811000000000000000089 +:101F000000691CE20000012F9380000000204411B2 +:101F10000000000000000000002048070000000052 +:101F200095000000002044110000000000000000A7 +:101F3000002F022F00000000000000000CE0000055 +:101F40000000029D0000000100333E2F0000000051 +:101F500000000000D90048000000000092000000CE +:101F6000002044110000000000000000C0204800D4 +:101F7000000000000000001C0040362700000000A8 +:101F80000000000CC0220A20000000000000002910 +:101F9000002036220000000000000028C04036204B +:101FA000000000000000A2A4002044110000000076 +:101FB000000000090020481100000000A1000000FE +:101FC00000204411000000000000000100804811C2 +:101FD000000000000000002100201E2D0000000075 +:101FE00000000000002C1CE30000000000000021A5 +:101FF00000203627000000000000002200201E2DD7 +:102000000000000000000000002C1CE400000000A4 +:1020100000000022002036270000000000000023FE +:1020200000201E2D0000000000000000003120A351 +:102030000000000000000000002D1D07000000004F +:1020400000000023002036270000000000000024CC +:1020500000201E2D0000000000000000003120C400 +:102060000000000000000000002D1D07000000001F +:10207000000000240080362700000000000000213E +:10208000002036230000000000000022002036243B +:10209000000000000000000000311CA30000000050 +:1020A0000000002300203627000000000000000090 +:1020B00000311CC40000000000000024008036270E +:1020C000000000000000001A002036270000000079 +:1020D0000000001B00203628000000000000001750 +:1020E00000201E2D00000000000000020021022739 +:1020F000000000000000000014C00000000002DC2E +:102100000000000000400000000002D90000001A9A +:1021100000203627000000000000001B00203628A9 +:10212000000000000000001700201E2D000000002D +:102130000000000200210227000000000000000053 +:1021400014E00000000002D9000000030021022773 +:10215000000000000000000014E00000000002DCAD +:102160000000002300201E2D0000000000000000E1 +:10217000002E00E1000000000000000002C000008E +:10218000000002DC0000002100201E2D00000000E5 +:1021900000000000003120A100000000000000004D +:1021A000002E00E8000000000000000006C0000053 +:1021B000000002DC0000002400201E2D00000000B2 +:1021C00000000000002E00E20000000000000000FF +:1021D00002C00000000002DC0000002200201E2DD2 +:1021E0000000000000000000003120C200000000DC +:1021F00000000000002E00E80000000000000000C9 +:1022000006C00000000002DC0000000000600000CA +:10221000000005FF0000000000600000000002B5A3 +:102220000000000000400000000002DE000000008E +:1022300000600000000002B5000000000060000027 +:10224000000005F60000000000400000000002DE73 +:102250000000000000600000000002A70000000075 +:1022600000400000000002DE0000001A00201E2DC9 +:10227000000000000000001B0080222D0000000074 +:102280000000001000221E230000000000000000DB +:1022900000294887000000000000000000311CA356 +:1022A000000000000000001000221E2700000000B7 +:1022B0000000000000294887000000000000001016 +:1022C00000221E230000000000000000003120C496 +:1022D000000000000000FFFF00282228000000008E +:1022E0000000000000894907000000000000001005 +:1022F00000221E2300000000000000000029488783 +:10230000000000000000001000221E21000000005C +:102310000000000000294847000000000000000005 +:1023200000311CA3000000000000001000221E2746 +:1023300000000000000000000029488700000000A5 +:102340000000000000311CA100000000000000108F +:1023500000221E270000000000000000002948475E +:10236000000000000000001000221E2300000000FA +:1023700000000000003120C4000000000000FFFF4A +:102380000028222800000000000000000029490762 +:10239000000000000000001000221E2100000000CC +:1023A00000000000003120C2000000000000FFFF1C +:1023B00000282228000000000000000000894907D2 +:1023C000000000000000001000221E23000000009A +:1023D0000000000000294887000000000000000104 +:1023E00000220A210000000000000000003308A2C3 +:1023F000000000000000001000221E22000000006B +:102400000000001000212222000000000000000057 +:1024100000294907000000000000000000311CA353 +:10242000000000000000001000221E270000000035 +:1024300000000000002948870000000000000001A3 +:1024400000220A210000000000000000003008A265 +:10245000000000000000001000221E22000000000A +:1024600000000010002122220000000000000000F7 +:1024700000294907000000000000001000221E2370 +:102480000000000000000000003120C40000000037 +:102490000000FFFF002822280000000000000000CC +:1024A000002949070000000000000000003808C5AE +:1024B00000000000000000000030084100000000A3 +:1024C0000000000100220A220000000000000000BD +:1024D000003308A2000000000000001000221E22AD +:1024E0000000000000000010002122220000000077 +:1024F00000000000008949070000000000000017EC +:102500000020222D000000000000000014C0000088 +:1025100000000318FFFFFFEF002806210000000065 +:10252000000000140020222D000000000000F8E050 +:1025300000204411000000000000000000294901B3 +:1025400000000000000000000089490100000000B8 +:102550000000000000204811000000000000000002 +:102560000020481100000000060A02000080481107 +:102570000000000000000000C0200000000000007B +:1025800097000000C020441100000000000000007F +:10259000C0204811000000008A0000000020441103 +:1025A00000000000000000000020481100000000B2 +:1025B0000000225C00204411000000000000000028 +:1025C000C0204800000000000000A1FC00204411D1 +:1025D0000000000000000000C020480000000000D3 +:1025E00000000000C0200400000000000000000007 +:1025F00000A0000A0000000097000000C020441165 +:102600000000000000000000C02048110000000091 +:102610008A000000C02044110000000000000000FB +:1026200000204811000000000000225C002044113E +:102630000000000000000000C02048000000000072 +:102640000000A1FC00204411000000000000000078 +:10265000C02048000000000000000000C02004006E +:10266000000000000000000000A0000A00000000C0 +:10267000970000000020441100000000000000004E +:1026800000204811000000008A00000000204411D2 +:1026900000000000000000000020481100000000C1 +:1026A0000000225C00204411000000000000000037 +:1026B000C0204800000000000000A1FC00204411E0 +:1026C0000000000000000000C020480000000000E2 +:1026D00000000000C0200400000000000000000016 +:1026E00000A0000A00000000970000000020441134 +:1026F0000000000000000000002048110000000061 +:102700008A000000002044110000000000000000CA +:1027100000204811000000000000225C002044114D +:102720000000000000000000C02048000000000081 +:102730000000A1FC00204411000000000000000087 +:10274000C0204800000000000001A1FD002044114D +:102750000000000000000000D90048000000000058 +:1027600000000000C0200400000000000000000085 +:1027700000A0000A000000000000225700204411C1 +:102780000000000000000003C0484A2000000000D4 +:102790000000225D00204411000000000000000045 +:1027A000C040480000000000000000000060000081 +:1027B000000005DE00000000C0200800000000004E +:1027C0000000225C00204411000000000000000313 +:1027D00000384A22000000000000A1FC0020441143 +:1027E0000000000000000000C020480000000000C1 +:1027F0000001A1FD002044110000000000000000C5 +:10280000002F022200000000000000000CE0000089 +:102810000000000000000000402048000000000010 +:102820000000000140304A200000000000000002CB +:10283000C0304A20000000000000000100530A22BE +:10284000000003550000003FC0280A2000000000DF +:102850008100000000204411000000000000000181 +:102860000020481100000000000021F80020441161 +:1028700000000000000000180020481100000000C7 +:10288000000421F90060441100000622000000113C +:1028900000210230000000000000000014E00000F1 +:1028A0000000035E00000014002F02220000000060 +:1028B000000000000CC000000000036C0001A2A496 +:1028C00000204411000000000000000000604802E9 +:1028D00000000374000021000020441100000000EB +:1028E00000000000C02048000000000000000000C0 +:1028F000C02048000000000000000000C020480088 +:102900000000000000000000C0404800000000007F +:1029100000000004002F0222000000000000000060 +:102920000CC00000000003700001A2A400204411AC +:1029300000000000000000000040480200000367A3 +:1029400000000028002F022200000000000000000C +:102950000CC00000000005BA0001A2A40020441130 +:102960000000000000000000004048020000036773 +:102970000000002C00203626000000000000004966 +:1029800000201811000000000000003F0020481146 +:10299000000000000000000100331A2600000000C3 +:1029A00000000000002F02260000000000000000D0 +:1029B0000CC00000000003760000002C00801A2DDF +:1029C000000000000000003FC0280A2000000000B6 +:1029D00000000015002F022200000000000000008F +:1029E0000CE000000000038C00000006002F022213 +:1029F00000000000000000000CE00000000003B731 +:102A000000000016002F022200000000000000005D +:102A10000CE00000000003B900000020002F02229B +:102A200000000000000000000CE00000000003A215 +:102A30000000000F002F0222000000000000000034 +:102A40000CE00000000003AE00000010002F022286 +:102A500000000000000000000CE00000000003AED9 +:102A60000000001E002F02220000000000000000F5 +:102A70000CE00000000003960000A2A40020441116 +:102A800000000000000000000040480200000000BC +:102A90000800000000290A220000000000000003D6 +:102AA00040210E20000000000000000CC021122078 +:102AB00000000000000800000028122400000000B0 +:102AC00000000014C02216200000000000000000DA +:102AD000002914A4000000000000A2A4002044115A +:102AE0000000000000000000002948A200000000D3 +:102AF0000000A1FE002044110000000000000000C2 +:102B00000040480300000000810000000020441144 +:102B1000000000000000000100204811000000003B +:102B2000000021F800204411000000000000001601 +:102B30000020481100000000000421F90060441149 +:102B400000000622000000150021023000000000F5 +:102B50000000000014E00000000003980000210EB7 +:102B6000002044110000000000000000C0204800C8 +:102B70000000000000000000C0204800000000002D +:102B80000000A2A40020441100000000000000008A +:102B900000404802000000008100000000204411B5 +:102BA00000000000000000010020481100000000AB +:102BB000000021F800204411000000000000001770 +:102BC0000020481100000000000421F900604411B9 +:102BD0000000062200000003002102300000000077 +:102BE0000000000014E00000000003A40000210821 +:102BF000002044110000000000000000C020480038 +:102C00000000000000000000C0204800000000009C +:102C10000000A2A4002044110000000000000000F9 +:102C200000404802000000000000A2A4002044115F +:102C3000000000000000000000204802000000002A +:102C4000800000000020441100000000000000008F +:102C50000020481100000000810000000020441105 +:102C600000000000000000100020481100000000DB +:102C70000000000000200010000000000000000024 +:102C800014C00000000003B4000000000040000079 +:102C9000000000000001A2A4002044110000000078 +:102CA0000000000600404811000000000001A2A43E +:102CB00000204411000000000000001600604811D0 +:102CC000000003740000000000400000000000004D +:102CD00000000000C020080000000000000000000C +:102CE000C0200C00000000000000001D0021022395 +:102CF000000000000000000014E00000000003CE0F +:102D000081000000002044110000000000000001CC +:102D10000020481100000000000021F800204411AC +:102D20000000000000000018002048110000000012 +:102D3000000421F900604411000006220000001187 +:102D400000210230000000000000000014E000003C +:102D5000000003C200002100002044110000000018 +:102D600000000000002048020000000000000000F9 +:102D70000020480300000000BABECAFE002048112F +:102D800000000000CAFEBABE00204811000000008A +:102D90000000A2A400204411000000000000000474 +:102DA0000040481100000000000021700020441184 +:102DB00000000000000000000020480200000000A9 +:102DC0000000000000204803000000008100000017 +:102DD00000204411000000000000000A00204811FB +:102DE00000000000000000000020001000000000B3 +:102DF0000000000014C00000000003D38C0000009D +:102E00000020441100000000CAFEBABE0040481174 +:102E100000000000810000000020441100000000BC +:102E200000000001002048110000000000003FFFEA +:102E300040280A20000000008000000040280E20EA +:102E40000000000040000000C02812200000000028 +:102E50000004000000694622000006220000000075 +:102E6000002014100000000000000000002F0223CA +:102E700000000000000000000CC00000000003E1A2 +:102E800000000000C0401800000003E400003FFF05 +:102E9000C0281A2000000000000400000069462637 +:102EA00000000622000000000020181000000000B2 +:102EB00000000000002F02240000000000000000BD +:102EC0000CC00000000003E700000000C0401C0030 +:102ED000000003EA00003FFFC0281E2000000000A1 +:102EE00000040000006946270000062200000000E0 +:102EF00000201C1000000000000000000020440220 +:102F00000000000000000000002820C500000000B4 +:102F100000000000004948E800000000A580000013 +:102F200000200811000000000000200000200C110B +:102F30000000000083000000006044110000041243 +:102F4000000000000020440200000000000000001B +:102F5000C0204800000000000000000040204800A1 +:102F6000000000000000001FC0210220000000003F +:102F70000000000014C00000000003F70000201053 +:102F800000204411000000000000800000204811D3 +:102F9000000000000000FFFFC0481220000003FFF7 +:102FA000A780000000200811000000000000A00021 +:102FB00000200C110000000083000000006044119C +:102FC0000000041200000000002044020000000085 +:102FD00000000000C02048000000000000000000C9 +:102FE000C0204800000000000000FFFFC0281220A1 +:102FF00000000000830000000020441100000000D9 +:103000000000000000304883000000008400000041 +:10301000002044110000000000000000C020480013 +:1030200000000000000000001D0000000000000083 +:103030008300000000604411000004120000000042 +:10304000C040040000000001A98000000020081119 +:10305000000000000000C00000400C11000003FA56 +:10306000AB80000000200811000000000000F8E024 +:1030700000400C11000003FAAD8000000020081190 +:10308000000000000000F88000400C11000003FA6E +:10309000B380000000200811000000000000F3FCD5 +:1030A00000400C11000003FAAF800000002008115E +:1030B000000000000000E00000400C11000003FAD6 +:1030C000B180000000200811000000000000F000A6 +:1030D00000400C11000003FA83000000002044119E +:1030E00000000000000021480020481100000000FE +:1030F00084000000002044110000000000000000D7 +:10310000C020480000000000000000001D0000007A +:10311000000000000000000000800000000000002F +:1031200001182000C0304620000000000000000010 +:10313000D90048000000000000000000C02004008A +:10314000000000000000000000A0000A00000000D5 +:103150000218A000C030462000000000000000005F +:10316000D90048000000000000000000C02004005A +:10317000000000000000000000A0000A00000000A5 +:103180000318C000C030462000000000000000000E +:10319000D90048000000000000000000C02004002A +:1031A000000000000000000000A0000A0000000075 +:1031B0000418F8E0C03046200000000000000000C5 +:1031C000D90048000000000000000000C0200400FA +:1031D000000000000000000000A0000A0000000045 +:1031E0000518F880C03046200000000000000000F4 +:1031F000D90048000000000000000000C0200400CA +:10320000000000000000000000A0000A0000000014 +:103210000618E000C030462000000000000000005A +:10322000D90048000000000000000000C020040099 +:10323000000000000000000000A0000A00000000E4 +:103240000718F000C0304620000000000000000019 +:10325000D90048000000000000000000C020040069 +:10326000000000000000000000A0000A00000000B4 +:103270000818F3FCC03046200000000000000000E9 +:10328000D90048000000000000000000C020040039 +:10329000000000000000000000A0000A0000000084 +:1032A00000000033C0300A200000000000000000D1 +:1032B000C0403440000000000000003000200A2D13 +:1032C0000000000000000000C0290C4000000000C9 +:1032D0000000003000203623000000000000000045 +:1032E000C0200400000000000000000000A0000A50 +:1032F00000000000860000000020441100000000D3 +:1033000000000000004048010000000085000000AF +:10331000C0204411000000000000000000404801EF +:10332000000000000000217C00204411000000008B +:1033300000000018402102200000000000000000F2 +:1033400014C000000000044700800000C0494A206B +:103350000000044800000000C020480000000000F9 +:1033600000000000C0204800000000000000000035 +:10337000C02048000000000081000000002044112F +:1033800000000000000000010020481100000000C3 +:1033900000000000C0200800000000000000000441 +:1033A000002F0222000000000000000006E00000E4 +:1033B000000004500000000400200811000000007C +:1033C0000000000017000000000000000004217F42 +:1033D00000604411000006220000001F002102309E +:1033E000000000000000000014C000000000000009 +:1033F0000000000000404C020000045000000000EB +:10340000C0200C000000000000000000C0201000E0 +:103410000000000000000000C020140000000000B8 +:1034200000000000C02018000000000000000000A4 +:10343000C0201C000000000000007F0000280A21BE +:103440000000000000004500002F022200000000E4 +:10345000000000000CE0000000000461000000001B +:10346000C02020000000000000000004002F0228FF +:10347000000000000000000006E000000000046101 +:1034800000000004002020110000000000000000E7 +:1034900017000000000000000000001000280A23B0 +:1034A0000000000000000010002F022200000000B9 +:1034B000000000000CE00000000004698100000032 +:1034C000002044110000000000000001002048110D +:1034D00000000000000400000069462400000622ED +:1034E00000000000004000000000046E81000000A9 +:1034F00000204411000000000000000000204811DE +:10350000000000000000216D0020441100000000B8 +:10351000000000000020480400000000000000003F +:10352000006048050000062700000000002824F085 +:10353000000000000000000700280A23000000002F +:1035400000000001002F0222000000000000000027 +:103550000AE000000000047500000000002F00C910 +:10356000000000000000000004E000000000048EE5 +:1035700000000000004000000000049B000000026A +:10358000002F022200000000000000000AE00000FE +:103590000000047A00000000002F00C900000000B5 +:1035A0000000000002E000000000048E00000000A7 +:1035B000004000000000049B00000003002F0222D6 +:1035C00000000000000000000AE000000000047F8E +:1035D00000000000002F00C90000000000000000F3 +:1035E0000CE000000000048E00000000004000001D +:1035F0000000049B00000004002F022200000000D5 +:10360000000000000AE00000000004840000000048 +:10361000002F00C900000000000000000AE00000C8 +:103620000000048E00000000004000000000049B29 +:1036300000000005002F0222000000000000000032 +:103640000AE000000000048900000000002F00C90B +:10365000000000000000000006E000000000048EF2 +:1036600000000000004000000000049B0000000675 +:10367000002F022200000000000000000AE000000D +:103680000000048E00000000002F00C900000000B0 +:103690000000000008E000000000048E00000000B0 +:1036A000004000000000049B00007F0000280A2169 +:1036B0000000000000004500002F02220000000072 +:1036C000000000000AE00000000000000000000808 +:1036D00000210A23000000000000000014C00000C8 +:1036E000000004980000216900204411000000003F +:1036F00000000000C02048000000000000000000A2 +:10370000C02048000000000000000000C020480069 +:1037100000000000CAFEBABE0040481100000000D0 +:1037200000000000C0204400000000000000000075 +:10373000C02000000000000000000000C040480061 +:103740000000000000007F0000280A2100000000A7 +:1037500000004500002F02220000000000000000D1 +:103760000AE00000000004A100000000C0200000EA +:103770000000000000000000C02000000000000069 +:1037800000000000C0400000000000000000000039 +:1037900000404C080000046100000000C020080048 +:1037A000000000000000001040210E20000000007A +:1037B0000000001140211220000000000000001253 +:1037C0004021162000000000000021690020441163 +:1037D000000000000000000000204802000000007F +:1037E0000000000000210225000000000000000091 +:1037F00014E00000000004AB00040000C0494A20AF +:10380000000004ACFFFBFFFFC0284A2000000000BE +:103810000000000000210223000000000000000062 +:1038200014E00000000004B800000000C0204800C0 +:103830000000000000000000C02048000000000060 +:103840000000000000210224000000000000000031 +:1038500014C000000000000081000000002044119E +:10386000000000000000000C0020481100000000D3 +:103870000000000000200010000000000000000018 +:1038800014C00000000004B4A00000000020441197 +:1038900000000000CAFEBABE00404811000000004F +:1038A000810000000020441100000000000000041E +:1038B00000204811000000000000216B002044118E +:1038C0000000000000000000C020481000000000C0 +:1038D00081000000002044110000000000000005ED +:1038E00000204811000000000000216C002044115D +:1038F0000000000000000000C02048100000000090 +:1039000000000000002F0224000000000000000062 +:103910000CE000000000000000000000004000007B +:10392000000004B200000000C0210A2000000000D6 +:103930000000000014C00000000004CB8100000063 +:103940000020441100000000000000000020481189 +:10395000000000000000216D002044110000000064 +:1039600000000000C020480000000000000000002F +:10397000C060480000000627000000000040000072 +:10398000000004CF8100000000204411000000006E +:1039900000000001002048110000000000040000A9 +:1039A000C02946200000000000000000C0600000A8 +:1039B0000000062200000001002102220000000099 +:1039C0000000000014C00000000004D600002169BF +:1039D000002044110000000000000000C02048004A +:1039E0000000000000000000C020480000000000AF +:1039F000000000000020481000000000CAFEBABE0F +:103A0000004048110000000000000000C0204400F9 +:103A10000000000000000000C0404810000000004E +:103A2000810000000020441100000000000000019F +:103A30000020481100000000000021F8002044117F +:103A4000000000000000000E0020481100000000EF +:103A5000000421F90060441100000622000000006B +:103A600000210230000000000000000014C000002F +:103A7000000004D800002180002044110000000054 +:103A800000000000C020480000000000000000000E +:103A9000C02000000000000000000000C02048001E +:103AA0000000000000000000C02000000000000036 +:103AB00000000000C04048000000000000000003BB +:103AC00000333E2F00000000000000010021022111 +:103AD000000000000000000014E0000000000508E5 +:103AE0000000002C00200A2D00000000000400004F +:103AF00018E00C11000004F70000000100333E2F15 +:103B000000000000000021690020441100000000B6 +:103B1000000000000020480200000000000000003B +:103B200000204803000000000000000800300A22C6 +:103B30000000000000000000C0204800000000005D +:103B400000000000C02048000000000000002169C3 +:103B50000020441100000000000000000020480286 +:103B600000000000000000000020480300000000EA +:103B70000000000800300A220000000000000000E1 +:103B8000C02048000000000000000000D8C048002D +:103B9000000004EB00002169002044110000000037 +:103BA00000000000002048020000000000000000AB +:103BB00000204803000000000000000800300A2236 +:103BC0000000000000000000C020480000000000CD +:103BD00000000000C0204800000000000000002D90 +:103BE0000020122D000000000000000000290C83BE +:103BF00000000000000021690020441100000000C6 +:103C0000000000000020480200000000000000004A +:103C100000204803000000000000000800300A22D5 +:103C20000000000000000000C0204800000000006C +:103C300000000000C020480000000000000000114B +:103C400000210224000000000000000014C0000059 +:103C5000000000000000000000400000000004B26E +:103C60000000002CC0203620000000000000002DC5 +:103C7000C0403620000000000000000F002102219B +:103C8000000000000000000014C000000000050D4E +:103C900000000000006000000000000B00000000B9 +:103CA000D90000000000000000000000C040040037 +:103CB00000000001B50000000020441100000000D9 +:103CC000000020000020481100000000B6000000A5 +:103CD00000204411000000000000A0000020481156 +:103CE00000000000B70000000020441100000000A8 +:103CF0000000C0000020481100000000B8000000D3 +:103D000000204411000000000000F8E000204811ED +:103D100000000000B9000000002044110000000075 +:103D20000000F8800020481100000000BA000000E8 +:103D300000204411000000000000E00000204811B5 +:103D400000000000BB000000002044110000000043 +:103D50000000F0000020481100000000BC0000003E +:103D600000204411000000000000F3FC0020481176 +:103D7000000000008100000000204411000000004D +:103D8000000000020020481100000000000000FFB9 +:103D900000280E300000000000000000002F022369 +:103DA00000000000000000000CC000000000052121 +:103DB00000000000C020080000000000000000001B +:103DC00014C00000000005360000000000200C11A7 +:103DD000000000000000001C00203623000000004E +:103DE0000000002B00203623000000000000002906 +:103DF00000203623000000000000002800203623A9 +:103E00000000000000000017002036230000000022 +:103E100000000025002036230000000000000026DE +:103E2000002036230000000000000015002036238B +:103E300000000000000000160020362300000000F3 +:103E4000FFFFE00000200C11000000000000002136 +:103E5000002036230000000000000022002036234E +:103E60000000000000001FFF00200C1100000000F7 +:103E70000000002300203623000000000000002482 +:103E80000020362300000000F1FFFFFF00283A2E3B +:103E9000000000000000001AC0220E2000000000F8 +:103EA000000000000029386E0000000081000000C2 +:103EB000002044110000000000000006002048110E +:103EC000000000000000002A402036200000000012 +:103ED00087000000002044110000000000000000E6 +:103EE000C0204800000000000000A1F400204411A0 +:103EF000000000000000000000204810000000004A +:103F00009D00000000204411000000000000001F80 +:103F100040214A20000000009600000000204411CB +:103F20000000000000000000C02048000000000069 +:103F300000000000C0200C00000000000000000095 +:103F4000C0201000000000000000001F0021162407 +:103F5000000000000000000014C00000000000008D +:103F60000000001D002036230000000000000003B8 +:103F700000281E2300000000000000080022222369 +:103F800000000000FFFFF0000028222800000000D1 +:103F900000000000002920E8000000000000001FD1 +:103FA00000203628000000000000001800211E2319 +:103FB0000000000000000020002036270000000064 +:103FC0000000000200221624000000000000000093 +:103FD000003014A8000000000000001E002036255C +:103FE000000000000000000300211A24000000006F +:103FF0001000000000281A2600000000EFFFFFFF5D +:1040000000283A2E0000000000000000004938CED1 +:10401000000006100000000140280A2000000000F7 +:104020000000000640280E200000000000000300F1 +:10403000C028122000000000000000080021122407 +:104040000000000000000000C0201620000000005A +:1040500000000000C0201A20000000000000000046 +:1040600000210222000000000000000014C0000037 +:104070000000056C810000000020441100000000D9 +:10408000000000010020481100000000000022583C +:1040900000300A24000000000004000000694622ED +:1040A00000000622000021690020441100000000E9 +:1040B0000000000000204805000000000002000091 +:1040C00000294A26000000000000000000204810DF +:1040D00000000000CAFEBABE002048110000000027 +:1040E00000000002002F022300000000000000007A +:1040F0000CC000000000057400000000C0201C106F +:104100000000000000000000C04000000000058228 +:1041100000000002002F0223000000000000000049 +:104120000CC0000000000574810000000020441154 +:104130000000000000000001002048110000000005 +:104140000000225800300A24000000000004000093 +:10415000006946220000062200000000C0201C105A +:104160000000000000000000C040000000000582C8 +:1041700000000000002F02230000000000000000EB +:104180000CC000000000057800000000C0201C00EA +:104190000000000000000000C04000000000058298 +:1041A00000000004002F02230000000000000000B7 +:1041B0000CC00000000005808100000000204411B8 +:1041C0000000000000000000002048110000000076 +:1041D0000000216D002044110000000000000000DC +:1041E000C02048000000000000000000C06048003F +:1041F000000006270000000000401C10000005829F +:1042000000000000C02000000000000000000000CE +:10421000C040000000000000000000000EE00000B0 +:10422000000005840000000000600000000005C3DD +:1042300000000000002F0224000000000000000029 +:104240000CC00000000005920000A2B7002044113D +:1042500000000000000000000020480700000000EF +:10426000000000330020262D000000000000001A8E +:10427000002122290000000000000006002226295B +:10428000000000000000A2C4002044110000000053 +:1042900000000000003048E90000000000000000BD +:1042A00000E00000000005900000A2D100204411B1 +:1042B000000000000000000000404808000000006E +:1042C0000000A2D100204411000000000000000105 +:1042D00000504A280000000000000001002F0224C6 +:1042E00000000000000000000CC00000000005A05D +:1042F0000000A2BB002044110000000000000000EC +:104300000020480700000000000000340020262D97 +:10431000000000000000001A002122290000000017 +:104320000000000600222629000000000000A2C5AF +:10433000002044110000000000000000003048E9A7 +:10434000000000000000000000E000000000059EEA +:104350000000A2D200204411000000000000000074 +:1043600000404808000000000000A2D200204411D4 +:10437000000000000000000100504A28000000007A +:1043800000000002002F02240000000000000000D6 +:104390000CC00000000005AE0000A2BF00204411C8 +:1043A000000000000000000000204807000000009E +:1043B000000000350020262D000000000000001A3B +:1043C000002122290000000000000006002226290A +:1043D000000000000000A2C6002044110000000000 +:1043E00000000000003048E900000000000000006C +:1043F00000E00000000005AC0000A2D30020441142 +:10440000000000000000000000404808000000001C +:104410000000A2D3002044110000000000000001B1 +:1044200000504A28000000000000A2C300204411F0 +:10443000000000000000000000204807000000000D +:10444000000000360020262D000000000000001AA9 +:104450000021222900000000000000060022262979 +:10446000000000000000A2C700204411000000006E +:1044700000000000003048E90000000000000000DB +:1044800000E00000000005B80000A2D400204411A4 +:10449000000000000000000000404808000000008C +:1044A0000000A2D400204411000000000000000120 +:1044B00000504A2800000000850000000020441140 +:1044C0000000000000000000002048010000000083 +:1044D0000000304A002044110000000001000000EC +:1044E0000020481100000000000000000040000013 +:1044F000000005BEA4000000C02044110000000020 +:1045000000000000C0404800000000000000000063 +:10451000C0600000000005C300000000C0400400AF +:10452000000000010001A2A40020441100000000CE +:104530000000003F00204811000000000000003F84 +:1045400000204811000000000000003F002048113A +:10455000000000000000003F0020481100000000A3 +:104560000000000500204811000000000000A1F438 +:10457000002044110000000000000000002048114D +:10458000000000008800000000204411000000002E +:10459000000000010020481100000000FF000000A2 +:1045A000002044110000000000000000002048111D +:1045B0000000000000000001002048110000000081 +:1045C0000000000200804811000000000000000010 +:1045D0000EE00000000005D60000100000200811C9 +:1045E000000000000000002B002036220000000028 +:1045F0000000000000600000000005DA000000007C +:1046000000600000000005C3980000000020441175 +:1046100000000000000000000080481100000000C1 +:1046200000000000C0600000000005DA000000008B +:10463000C0400400000000010000A2A400204411BA +:1046400000000000000000220020481100000000CF +:10465000890000000020441100000000000000015B +:1046600000404811000005CD9700000000204411D3 +:1046700000000000000000000020481100000000C1 +:104680008A0000000020441100000000000000002B +:1046900000404811000005CD00000000006000004F +:1046A000000005F30001A2A4C02044110000000096 +:1046B0000000001600604811000003740000201084 +:1046C00000204411000000000001000000204811FB +:1046D00000000000810000000020441100000000E4 +:1046E0000000000100204811000000000000217CB3 +:1046F0000020441100000000098000000020481143 +:1047000000000000FFFFFFFF002048110000000034 +:104710000000000000204811000000000000000020 +:1047200017000000000000000004217F0060441119 +:10473000000006220000001F0021023000000000DF +:104740000000000014C00000000000000000000491 +:1047500000404C11000005ED00000000004000008A +:10476000000000000000001700201E2D00000000C7 +:104770000000000400291E270000000000000017B0 +:1047800000803627000000000000001700201E2DCA +:1047900000000000FFFFFFFB00281E2700000000B4 +:1047A00000000017008036270000000000000017FE +:1047B00000201E2D000000000000000800291E2718 +:1047C00000000000000000170080362700000000F5 +:1047D0000000001700201E2D00000000FFFFFFF763 +:1047E00000281E2700000000000000170080362768 +:1047F000000000000001A2A40020441100000000FD +:104800000000001600604811000003740000201032 +:1048100000204411000000000001000000204811A9 +:10482000000000000000217C002044110000000076 +:10483000018000000020481100000000FFFFFFFF82 +:104840000020481100000000000000000020481176 +:104850000000000000000000170000000000000041 +:104860008100000000204411000000000000000151 +:1048700000204811000000000004217F0060441166 +:10488000000006220000001F00210230000000008E +:104890000000000014C0000000000621000000100D +:1048A00000404C110000060700000000C02004007A +:1048B000000000000000000038C000000000000000 +:1048C0000000001D00200A2D000000000000001E56 +:1048D00000200E2D000000000000001F0020122DFF +:1048E00000000000000000200020162D0000000045 +:1048F00000002169002044110000000000000000B9 +:1049000000204804000000000000000000204805CE +:10491000000000000000000000204801000000002E +:10492000CAFEBABE002048110000000000000004CA +:10493000003012240000000000000000002F00647E +:1049400000000000000000000CC000000000062075 +:104950000000000300281A220000000000000008E8 +:104960000022122200000000FFFFF00000281224A5 +:104970000000000000000000002910C4000000003A +:104980000000001F0040362400000000000000006E +:104990000080000000000000000000001AC00000BD +:1049A000000006229F0000000020441100000000CB +:1049B000CAFEBABE0020481100000000000000003E +:1049C0001AE0000000000625000000000080000042 +:1049D00000000000000000001AC0000000000627D0 +:1049E0009E0000000020441100000000CAFEBABE74 +:1049F0000020481100000000000000001AE0000044 +:104A00000000062A000000000080000000000000F6 +:104A100000000000006000000000000B000010001B +:104A200000600411000003150000000000200411C4 +:104A3000000000000000000000600811000001B24A +:104A40000000225C00204411000000000000000370 +:104A500000204811000000000000225600204411F0 +:104A6000000000000000001B0020481100000000B2 +:104A70000000A1FC00204411000000000000000123 +:104A800000204811000000000001A1FDC0204411D9 +:104A9000000000000000002100201E2D000000008A +:104AA0000000001000221E2700000000000000246B +:104AB0000020222D000000000000FFFF0028222817 +:104AC000000000000000000000294907000000006D +:104AD000000000000020481100000000000000223B +:104AE0000020222D000000000000FFFF00282228E7 +:104AF000000000000000000000294907000000003D +:104B00000000000000204811000000000000002309 +:104B100000201E2D000000000000001000221E27B3 +:104B2000000000000000000000294907000000000C +:104B300000000000004048110000000000000000DC +:104B40000000000000000000000000000000000065 +:104B50000000000000000000000000000000000055 +:104B60000000000000000000000000000000000045 +:104B70000000000000000000000000000000000035 +:104B80000000000000000000000000000000000025 +:104B90000000000000000000000000000000000015 +:104BA0000000000000000000000000000000000005 +:104BB00000000000000000000000000000000000F5 +:104BC00000000000000000000000000000000000E5 +:104BD00000000000000000000000000000000000D5 +:104BE00000000000000000000000000000000000C5 +:104BF00000000000000000000000000000000000B5 +:104C000000000000000000000000000000000000A4 +:104C10000000000000000000000000000000000094 +:104C20000000000000000000000000000000000084 +:104C30000000000000000000000000000000000074 +:104C40000000000000000000000000000000000064 +:104C50000000000000000000000000000000000054 +:104C60000000000000000000000000000000000044 +:104C70000000000000000000000000000000000034 +:104C80000000000000000000000000000000000024 +:104C90000000000000000000000000000000000014 +:104CA0000000000000000000000000000000000004 +:104CB00000000000000000000000000000000000F4 +:104CC00000000000000000000000000000000000E4 +:104CD00000000000000000000000000000000000D4 +:104CE00000000000000000000000000000000000C4 +:104CF00000000000000000000000000000000000B4 +:104D000000000000000000000000000000000000A3 +:104D10000000000000000000000000000000000093 +:104D20000000000000000000000000000000000083 +:104D30000000000000000000000000000000000073 +:104D40000000000000000000000000000000000063 +:104D50000000000000000000000000000000000053 +:104D60000000000000000000000000000000000043 +:104D70000000000000000000000000000000000033 +:104D80000000000000000000000000000000000023 +:104D90000000000000000000000000000000000013 +:104DA0000000000000000000000000000000000003 +:104DB00000000000000000000000000000000000F3 +:104DC00000000000000000000000000000000000E3 +:104DD00000000000000000000000000000000000D3 +:104DE00000000000000000000000000000000000C3 +:104DF00000000000000000000000000000000000B3 +:104E000000000000000000000000000000000000A2 +:104E10000000000000000000000000000000000092 +:104E20000000000000000000000000000000000082 +:104E30000000000000000000000000000000000072 +:104E40000000000000000000000000000000000062 +:104E50000000000000000000000000000000000052 +:104E60000000000000000000000000000000000042 +:104E70000000000000000000000000000000000032 +:104E80000000000000000000000000000000000022 +:104E90000000000000000000000000000000000012 +:104EA0000000000000000000000000000000000002 +:104EB00000000000000000000000000000000000F2 +:104EC00000000000000000000000000000000000E2 +:104ED00000000000000000000000000000000000D2 +:104EE00000000000000000000000000000000000C2 +:104EF00000000000000000000000000000000000B2 +:104F000000000000000000000000000000000000A1 +:104F10000000000000000000000000000000000091 +:104F20000000000000000000000000000000000081 +:104F30000000000000000000000000000000000071 +:104F40000000000000000000000000000000000061 +:104F50000000000000000000000000000000000051 +:104F60000000000000000000000000000000000041 +:104F70000000000000000000000000000000000031 +:104F80000000000000000000000000000000000021 +:104F90000000000000000000000000000000000011 +:104FA0000000000000000000000000000000000001 +:104FB00000000000000000000000000000000000F1 +:104FC00000000000000000000000000000000000E1 +:104FD00000000000000000000000000000000000D1 +:104FE00000000000000000000000000000000000C1 +:104FF00000000000000000000000000000000000B1 +:1050000000000000000000000000000000000000A0 +:105010000000000000000000000000000000000090 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B0000142050A05BA02500000000001C301685E +:1052C000044105BA00000000022502090250015104 +:1052D000000000000223024502A00241000000007D +:1052E00003D705BA05BA05BA0000000005E205E3D8 +:1052F000031F05BA00000000032005BF0320034A76 +:105300000000000003340282034C033E0000000052 +:1053100005BA05BA05BA05BA0000000005BA055776 +:1053200005BA032A0000000003BC05BA04C3034EFB +:105330000000000004A20455043F05BA000000006C +:1053400004D805BA044304E5000000000455050F25 +:10535000035B037B0000000005BA05BA05BA05BA75 +:105360000000000005BA05BA05BA05BA0000000041 +:1053700005BA05BA05D805C10000000005BA05BA8E +:10538000000705BA0000000005BA05BA05BA05BA5B +:105390000000000005BA05BA05BA05BA0000000011 +:1053A00003F803ED0408040600000000040E040ADC +:1053B000040C041000000000041C04180424042041 +:1053C00000000000042C0428043404300000000015 +:1053D00005BA05BA043A04380000000005BA05BA57 +:1053E00005BA05BA0000000005BA05BA05BA05BA43 +:1053F000000000000002060E062C0006000000005F +:00000001FF diff --git a/firmware/radeon/RS780_pfp.bin.ihex b/firmware/radeon/RS780_pfp.bin.ihex new file mode 100644 index 000000000000..40880411e785 --- /dev/null +++ b/firmware/radeon/RS780_pfp.bin.ihex @@ -0,0 +1,145 @@ +:1000000000CA040000A00000007E828B007C038BED +:10001000008001DB007C038B00D4401E00EE001E3C +:1000200000CA040000A00000007E828B00C41838C3 +:1000300000CA240000CA2800009581CB00C41C3AE5 +:1000400000C3C00000CA080000CA0C00007C744B4A +:1000500000C200050099C00000C41C3A007C744C2A +:1000600000C0FFE000042C0800309002007D250055 +:1000700000351402007D350B00255407007CD58027 +:1000800000259C070095C00400D5001B007EDDC143 +:10009000007D9D8000D6801B00D5801B00D4401EB3 +:1000A00000D5401E00D6401E00D6801E00D4801E03 +:1000B00000D4C01E009783D300D5C01E00CA08001C +:1000C0000080001A00CA0C0000E4011E00D4001ECB +:1000D0000080000C00C4183800E4013E00D4001E6B +:1000E0000080000C00C4183800D4401E00EE001E32 +:1000F00000CA040000A00000007E828B00E4011E04 +:1001000000D4001E00D4401E00EE001E00CA0400F1 +:1001100000A00000007E828B00E4013E00D4001E9F +:1001200000D4401E00EE001E00CA040000A0000023 +:10013000007E828B00CA080000CA0C00008001DB30 +:1001400000D4802400CA0800007C00C000C8142528 +:1001500000C81824007C9488007C988000C20003AA +:1001600000D40075007C744C0080006400D4401EF4 +:1001700000CA180000D4401E00D5801E0080006216 +:1001800000D4007500D4401E00CA080000CA0C004C +:1001900000CA100000D4801900D4C01800D5001780 +:1001A00000D4801E00D4C01E00D5001E00E2001E38 +:1001B00000CA040000A00000007E828B00D40075FD +:1001C00000D4401E00CA080000CA0C0000CA10007B +:1001D00000D4801900D4C01800D5001700D4801EA8 +:1001E00000D4C01E00D5001E00EE001E00CA040090 +:1001F00000A00000007E828B00CA080000248C0151 +:1002000000D480600094C0030004100100041002B8 +:1002100000D5002500D4401E0080000000D4801EC0 +:1002200000CA080000D4806100D4401E0080000095 +:1002300000D4801E00CA080000CA0C0000D4401E72 +:1002400000D4801600D4C01600D4801E008001DBCC +:1002500000D4C01E00C6084300CA0C0000CA10002B +:100260000094800400CA140000E420F300D420139A +:1002700000D5606500D4E01C00D5201C00D5601CB2 +:10028000008000000006200100C6084300CA0C00E0 +:1002900000CA1000009483F700CA140000E420F3A1 +:1002A0000080009C00D4201300C6084300CA0C0044 +:1002B00000CA1000009883EF00CA140000D4006444 +:1002C000008000B00000000000C4143200C61843D3 +:1002D00000C4082F0095400500C40C3000D4401E17 +:1002E0000080000000EE001E009583F500C4103170 +:1002F00000D4403300D5206500D4A01C00D4E01CFD +:1003000000D5201C00E4015E00D4001E0080000027 +:100310000006200100CA1800000A200100D600765D +:1003200000C408360098800700C6104500950110EB +:1003300000D4001F00D460620080000000D420625E +:1003400000CC383500CC1433008401DE00D40072B8 +:1003500000D5401E0080000000EE001E00E2001AE2 +:10036000008401DE00E2001A00CC104B00CC0447F0 +:10037000002C9401007D098B00984005007D15CB71 +:1003800000D4001A008001DB00D4006D0034440169 +:1003900000CC0C480098403A00CC2C4A00958004D0 +:1003A00000CC0449008001DB00D4001A00D4C01A3C +:1003B000002828010084011300CC10030098801B42 +:1003C0000004380C0084011300CC1003009880173F +:1003D000000438080084011300CC10030098801337 +:1003E000000438040084011300CC1003009880142A +:1003F00000CC104C009A800900CC144D009840DCD1 +:1004000000D4006D00CC184800D5001A00D5401A61 +:10041000008000EC00D5801A0096C0D500D4006D95 +:10042000008001DB00D4006E009AC00300D4006D90 +:1004300000D4006E0080000000EC007F009AC0CC69 +:1004400000D4006D008001DB00D4006E00CC1403EA +:1004500000CC180300CC1C03007D9103007DD583E4 +:10046000007D190C0035CC1F0035701F007CF0CBCF +:10047000007CD08B00880000007E8E8B0095C0042D +:1004800000D4006E008001DB00D4001A00D4C01A32 +:1004900000CC080300CC0C0300CC100300CC1403E8 +:1004A00000CC180300CC1C0300CC240300CC280390 +:1004B0000035C41F0036B01F007C704B0034F01FA5 +:1004C000007C704B0035701F007C704B007D888174 +:1004D000007DCCC1007E5101007E9541007C908260 +:1004E000007CD4C2007C848B009AC003007C8C8B7F +:1004F000002C88010098809E00D4006D0098409CDC +:1005000000D4006E00CC084C00CC0C4D00CC104840 +:1005100000D4801A00D4C01A0080012400D5001A2B +:1005200000CC083200D40032009482B600CA0C001D +:1005300000D4401E0080000000D4001E00E4011E14 +:1005400000D4001E00CA080000CA0C0000CA100037 +:1005500000D4401E00CA140000D4801E00D4C01E67 +:1005600000D5001E00D5401E00D54034008000009C +:1005700000EE001E0028040400E2001A00E2001A47 +:1005800000D4401A00CA380000CC080300CC0C0389 +:1005900000CC0C0300CC0C030098829A00000000F1 +:1005A000008401DE00D7A06F0080000000EE001F75 +:1005B00000CA040000C2FF0000CC083400C13FFFA5 +:1005C000007C74CB007CC90B007D010F0099028D6B +:1005D000007C738B008401DE00D7A06F00800000D8 +:1005E00000EE001F00CA080000281900007D898B5A +:1005F000009580140028140400CA0C0000CA1000E2 +:1006000000CA1C0000CA240000E2001F00D4C01A67 +:1006100000D5001A00D5401A00CC180300CC2C03DA +:1006200000CC2C0300CC2C03007DA58B007D9C47C7 +:1006300000984274000000000080018400D4C01AB9 +:1006400000D4401E00D4801E0080000000EE001E7A +:1006500000E4011E00D4001E00D4401E00EE001E67 +:1006600000CA040000A00000007E828B00E4013E6E +:1006700000D4001E00D4401E00EE001E00CA04007C +:1006800000A00000007E828B00CA080000248C06B7 +:10069000000CCC060098C00600CC104E0099000457 +:1006A00000D4007300E4011E00D4001E00D4401EDC +:1006B00000D4801E0080000000EE001E00CA08006A +:1006C00000CA0C000034D01800251001009500214C +:1006D00000C17FFF00CA100000CA140000CA180041 +:1006E00000D4801D00D4C01D007DB18B00C142022A +:1006F00000C2C00100D5801D0034DC0E007D5D4CC1 +:10070000007F734C00D7401E00D5001E00D5401E50 +:1007100000C1420000C2C00000099C010031DC1091 +:10072000007F5F4C007F734C00042802007D8380B3 +:1007300000D5A86F00D5806600D7401E00EC005E93 +:1007400000C8240200C82402008001DB00D6007625 +:1007500000D4401E00D4801E00D4C01E00800000C3 +:1007600000EE001E0080000000EE001F00D4001FFD +:100770000080000000D4001F00D4001F008800008B +:1007800000D4001F00000000000000000000000076 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:10080000000101940002019B000300B2000400A259 +:10081000000500030006003F000700320008014FFA +:1008200000090046000A0036001001D9001700C573 +:100830000022015D0023016C002000D70024014844 +:100840000026004D0027005C0028008D0029005183 +:10085000002A007E002B0061002F0088003200AAD1 +:10086000003401A20036006F003C0179003F009582 +:10087000004101AF00440151005501960056019D11 +:100880000060000B00610034006200380063003833 +:1008900000640038006500380066003800670038E2 +:1008A0000068003A00690041006A0048006B004897 +:1008B000006C0048006D0048006E0048006F004862 +:1008C000007301D9000000060000000600000006C9 +:1008D0000000000600000006000000060000000600 +:1008E00000000006000000060000000600000006F0 +:1008F00000000006000000060000000600000006E0 +:00000001FF diff --git a/firmware/radeon/RV610_me.bin.ihex b/firmware/radeon/RV610_me.bin.ihex new file mode 100644 index 000000000000..ba19ed892920 --- /dev/null +++ b/firmware/radeon/RV610_me.bin.ihex @@ -0,0 +1,1345 @@ +:1000000000000000C020040000000000000000000C +:1000100000A0000A000000000000FFFF00284621A9 +:100020000000000000000000D900480000000000AF +:1000300000000000C02004000000000000000000DC +:1000400000A0000A000000000000000000E0000026 +:100050000000000000010000C02946200000000050 +:1000600000000000D900480000000000000000006F +:10007000C0200400000000000000000000A0000AF2 +:10008000000000008100000000204411000000007A +:1000900000000001002048110000000000042004BE +:1000A000006044110000068D0000000000600000A8 +:1000B000000006310000000000600000000006455E +:1000C00000000000C02008000000000000000F0039 +:1000D000002816220000000000000008002116255C +:1000E000000000000000001800203625000000007D +:1000F0008D000000002044110000000000000004FA +:10010000002F022500000000000000000CE00000AD +:1001100000000018004120000040481100000019B4 +:100120000042200000204811000000008E00000066 +:1001300000204411000000000000002800204A2D8B +:1001400000000000900000000020441100000000AA +:100150000000000000204805000000000000000C26 +:1001600000211622000000000000000300281625D0 +:10017000000000000000001900211A220000000009 +:100180000000000400281A26000000000000000003 +:10019000002914C5000000000000001900203625C9 +:1001A0000000000000000000003A140200000000FF +:1001B00000000016002116250000000000000003CA +:1001C00000281625000000000000001700200E2D5A +:1001D00000000000FFFFFFFC00280E2300000000CD +:1001E00000000000002914A3000000000000001718 +:1001F00000203625000000000000800000280E22AC +:10020000000000000000000700220E230000000094 +:10021000000000000029386E0000000020000000EF +:1002200000280E22000000000000000600210E231E +:1002300000000000000000000029386E00000000EF +:100240000000000000220222000000000000000068 +:1002500014E0000000000038000000002EE0000064 +:1002600000000035000000002CE000000000003716 +:100270000000000000400E2D0000003900000008C2 +:1002800000200E2D00000000000000090040122D8B +:10029000000000460000000100400E2D0000003963 +:1002A00000000000C0200C0000000000003FFFFC28 +:1002B0000028122300000000000000020022122487 +:1002C000000000000000001F00211E2300000000AD +:1002D0000000000014E000000000003E00000008E4 +:1002E00000401C11000000410000000D00201E2DE8 +:1002F000000000000000000F00281E270000000082 +:100300000000000300221E27000000007FC0000044 +:1003100000281A23000000000000001400211A2603 +:10032000000000000000000100331A260000000059 +:100330000000000800221A26000000000000000053 +:1003400000290CC700000000000000270020362410 +:100350000000000000007F000028122100000000C3 +:1003600000001400002F0224000000000000000024 +:100370000CE000000000004B0000000100290E23EB +:10038000000000000000000E0020362300000000E6 +:100390000000E0000020441100000000FFF8000011 +:1003A00000294A230000000000000000003A2C024F +:1003B000000000000000000200220E2B00000000E0 +:1003C000FC00000000280E23000000000000000FC9 +:1003D000002036230000000000001FFF00294A23F0 +:1003E000000000000000002700204A2D000000004F +:1003F000000000000020481100000000000000295B +:1004000000200E2D00000000060A020000294A23E9 +:100410000000000000000000002048110000000063 +:100420000000000000204811000000000000000152 +:1004300000210222000000000000000014E0000083 +:1004400000000061000000002EE000000000005FDE +:10045000000000002CE000000000005E0000000032 +:1004600000400E2D000000620000000100400E2D33 +:10047000000000620000000A00200E2D00000000B5 +:100480000000000B0040122D0000006A0000000078 +:10049000C0200C0000000000003FFFFC00281223D9 +:1004A00000000000000000020022122400000000F2 +:1004B0007FC0000000281623000000000000001488 +:1004C0000021162500000000000000010033162561 +:1004D000000000008000000000280E230000000043 +:1004E0000000000000290CA3000000003FFFFC00FA +:1004F00000290E23000000000000001F00211E2321 +:10050000000000000000000014E000000000006D8A +:100510000000010000401C11000000700000000DF0 +:1005200000201E2D00000000000000F000281E2703 +:10053000000000000000000400221E270000000050 +:100540008100000000204411000000000000000DA8 +:100550000020481100000000FFFFF0FF00281A30C3 +:10056000000000000000A02800204411000000004E +:1005700000000000002948E6000000000000A0186C +:1005800000204411000000003FFFFFFF00284A2325 +:10059000000000000000A010002044110000000036 +:1005A00000000000002048040000000000000030AF +:1005B0000020162D00000000000000020029162572 +:1005C0000000000000000030002036250000000080 +:1005D000000000250020162D000000000000000093 +:1005E000002F00A300000000000000000CC000006D +:1005F00000000083000000260020162D00000000EF +:1006000000000000002F00A4000000000000000017 +:100610000CC000000000008400000000004000004A +:100620000000008A000000250020362300000000A2 +:100630000000002600203624000000000000001703 +:1006400000201E2D000000000000000200210227F3 +:10065000000000000000000014E000000000008A1C +:1006600000000000006000000000066800000000BC +:10067000006000000000065C0000000200210E2265 +:10068000000000000000000014C000000000008D09 +:1006900000000012C040362000000093000000005F +:1006A0002EE0000000000091000000002CE000009F +:1006B000000000900000000200400E2D000000929B +:1006C0000000000300400E2D000000920000000C0E +:1006D00000200E2D00000000000000120020362334 +:1006E000000000000000000300210E2200000000B6 +:1006F0000000000014C00000000000980000A00CE2 +:10070000002044110000000000000000C02048004C +:100710000000000000000000C0404800000000A0F1 +:100720000000A00C002044110000000000000000A8 +:100730000020481100000000000000002EE0000032 +:100740000000009E000000002CE000000000009D62 +:100750000000000200400E2D0000009F000000037A +:1007600000400E2D0000009F0000000C00200E2D08 +:10077000000000000000000000204803000000000E +:1007800000000000003A0C0200000000003F0000E2 +:1007900000280E23000000000000001000210E239E +:1007A00000000000000000110020362300000000BF +:1007B0000000001E0021022B0000000000000000CD +:1007C00014C00000000000A700000016C020362062 +:1007D000000000000000001F0021022B00000000AC +:1007E0000000000014C00000000000AA0000001576 +:1007F000C0203620000000000000000800210E2B61 +:10080000000000000000007F00280E230000000010 +:1008100000000000002F0223000000000000000084 +:100820000CE00000000000E10000000027000000D4 +:10083000000000000000000000600000000002A3B3 +:1008400000000001002F0223000000000000000053 +:100850000AE00000000000B300000000006000009B +:100860000000013A81000000002044110000000057 +:100870000000000600204811000000000000000CED +:1008800000221E300000000099800000002044116A +:1008900000000000000000040020122D00000000F5 +:1008A00000000008002212240000000000000010D8 +:1008B00000201811000000000000000000291CE4C6 +:1008C0000000000000000000006048070000012F49 +:1008D0009B00000000204411000000000000000008 +:1008E00000204802000000009C000000002044118D +:1008F00000000000000000000033146F0000000042 +:100900000000000100333E23000000000000000052 +:10091000D9004800000000000000000000203C0555 +:1009200000000000810000000020441100000000D1 +:100930000000000E00204811000000000000000030 +:1009400000201010000000000000E007002044110B +:10095000000000000000000F0021022B000000003A +:100960000000000014C00000000000CB00F8FF08E9 +:1009700000204811000000009800000000404811CD +:10098000000000DC000000F000280E220000000043 +:10099000000000A0002F0223000000000000000063 +:1009A0000CC00000000000DA0000001100200E2D35 +:1009B0000000000000000001002F022300000000E2 +:1009C000000000000CE00000000000D50000000264 +:1009D000002F022300000000000000000CE00000D7 +:1009E000000000D400003F0000400C11000000D6C1 +:1009F00000001F0000400C11000000D600000F0096 +:100A000000200C11000000000038000900294A23D2 +:100A1000000000003F00000000280E2B0000000036 +:100A20000000000200220E2300000000000000076A +:100A300000494A23000000DC00380F09002048115B +:100A400000000000680000070020481100000000BE +:100A50000000000800214A270000000000000000FC +:100A60000020481100000000060A020000294A2464 +:100A700000000000000000000020481100000000FD +:100A80000000000000204811000000000000A20249 +:100A9000002044110000000000FF000000280E228A +:100AA000000000000000008000294A230000000030 +:100AB0000000002700200E2D00000000000000268E +:100AC0000020122D0000000000000000002F008315 +:100AD00000000000000000000CE00000000000EA40 +:100AE000000000000060000000000662000000003E +:100AF00000400000000000EB00000000006000006B +:100B000000000665000000070020222D0000000004 +:100B10000000000500220E2200000000001000006E +:100B200000280E23000000000000000000292068BB +:100B30000000000000000000003A0C02000000006D +:100B4000000000EF00280E2300000000000000005D +:100B500000292068000000000000001700200E2D72 +:100B6000000000000000000300210223000000003C +:100B70000000000014E00000000000F80000000B7E +:100B800000210228000000000000000014C0000046 +:100B9000000000F8000004000029222800000000E6 +:100BA0000000001400203628000000000000001C97 +:100BB00000210E22000000000000000014C0000010 +:100BC000000000FD0000A30C002044110000000004 +:100BD0000000000000204811000000000000001E7E +:100BE00000210E22000000000000000014C00000E0 +:100BF0000000010B0000A30F0020441100000000C2 +:100C00000000001100200E2D000000000000000177 +:100C1000002F022300000000000000000CC00000B4 +:100C200000000104FFFFFFFF004048110000010B1E +:100C300000000002002F022300000000000000005E +:100C40000CC00000000001070000FFFF0040481139 +:100C50000000010B00000004002F02230000000030 +:100C6000000000000CC000000000010A000000FFAE +:100C7000004048110000010B000000010020481155 +:100C8000000000000002C400002044110000000029 +:100C90000000001F00210E220000000000000000E4 +:100CA00014C00000000001120000001040210E20BE +:100CB00000000000000000130020362300000000A8 +:100CC0000000001840224A20000000000000001030 +:100CD000C0424A20000001140000000000200C1156 +:100CE0000000000000000013002036230000000078 +:100CF000000000000020481100000000000000007B +:100D000000204811000000000000000A002010111F +:100D10000000000000000000002F0224000000007E +:100D2000000000000CE000000000011B00000000BB +:100D300000204811000000000000000100531224B0 +:100D400000000117FFBFFFFF00283A2E000000003F +:100D50000000001B00210222000000000000000033 +:100D600014C000000000012E81000000002044118A +:100D7000000000000000000D0020481100000000ED +:100D80000000001800220E3000000000FC000000EF +:100D900000280E2300000000810000000020441104 +:100DA000000000000000000E0020481100000000BC +:100DB0000000000000201010000000000000E00E05 +:100DC000002044110000000007F8FF08002048112F +:100DD000000000000000000000294A23000000007D +:100DE0000000001C00201E2D000000000000000874 +:100DF00000214A27000000000000000000204811E8 +:100E000000000000060A020000294A240000000039 +:100E10000000000000204811000000000000000059 +:100E200000204811000000000000000000800000C9 +:100E300000000000810000000020441100000000BC +:100E40000000000100204811000000000000217C8B +:100E50000020441100000000008000000020481124 +:100E60000000000000000000002048060000000014 +:100E70000000000800214A270000000000000000D8 +:100E800017000000000000000004217F00604411F2 +:100E90000000068D0000001F00210230000000004D +:100EA0000000000014C000000000068C00000004D8 +:100EB00000404C1100000135810000000020441169 +:100EC00000000000000000010020481100000000A8 +:100ED000000021F800204411000000000000001C68 +:100EE0000020481100000000000421F900604411B6 +:100EF0000000068D000000110021023000000000FB +:100F00000000000014E000000000013C00000000B0 +:100F100000800000000000000000000000600000F1 +:100F20000000000B00000000006004110000031529 +:100F3000000000000020041100000000000000007C +:100F400000600811000001B2000000000060000015 +:100F5000000001600000FFFF40280E20000000009C +:100F600000000010C0211220000000000000FFFF60 +:100F7000402806200000000000000010C0210A20C8 +:100F800000000000000000000034146100000000B8 +:100F90000000000000741882000002BB0001A1FDE7 +:100FA00000604411000002E000003FFF002F022F0C +:100FB00000000000000000000CC00000000001471D +:100FC00000000000C040040000000001000000001C +:100FD000006000000000000B000000000060041131 +:100FE00000000315000000000020041100000000B4 +:100FF0000000000000600811000001B200003FFF87 +:10100000002F022F00000000000000000CE0000094 +:10101000000000000000000000600000000001600F +:101020000000001040210E20000000000000FFFF23 +:10103000C0281220000000000000001040211620EF +:10104000000000000000FFFFC0681A20000002BB83 +:101050000001A1FD00604411000002E000003FFF1C +:10106000002F022F00000000000000000CC0000054 +:101070000000015800000000C04004000000000112 +:101080000000225C0020441100000000000000016C +:1010900000300A2F000000000000000100210A2299 +:1010A000000000000000000300384A220000000099 +:1010B0000000225600204411000000000000001A29 +:1010C00000204811000000000000A1FC0020441195 +:1010D0000000000000000001008048110000000036 +:1010E00000000000006000000000000B0000000095 +:1010F000006000000000018F0000000000600000A0 +:10110000000001A000003FFF002F022F00000000A0 +:10111000000000000CE000000000000000000000E3 +:1011200000202C0800000000000000000020241116 +:101130000000000000000000002028110000000056 +:10114000000022560020441100000000000000169C +:1011500000204811000000000000225C0020441123 +:101160000000000000000003002048110000000003 +:1011700093800000002044110000000000000002E5 +:1011800000221E290000000000000000007048EB53 +:101190000000019C0000000000600000000002BB95 +:1011A00000000001403306200000000000000000A5 +:1011B000C03024090000000000003FFF002F022F74 +:1011C00000000000000000000CE000000000000033 +:1011D0000000000000600000000002A3000000000A +:1011E000002F022100000000000000000AE00000C3 +:1011F0000000018100000000006000000000013AD2 +:101200000000000000400000000001869500000082 +:10121000002044110000000000000000002F022107 +:1012200000000000000000000CE00000000001864B +:1012300000000000C0204800000000000000000185 +:10124000005306210000018292000000002044119A +:101250000000000000000000C0604800000001978E +:101260000001A1FD00204411000000000000001159 +:101270000020062D00000000000000000078042A75 +:10128000000002FB00000000002028090000000010 +:1012900000003FFF002F022F0000000000000000B0 +:1012A0000CC000000000017400000000C0400400F9 +:1012B000000000010000021000600411000003158E +:1012C00000003FFF002F022F000000000000000080 +:1012D0000CE000000000019400000015C020362042 +:1012E0000000000000000016C020362000000000B2 +:1012F0003F800000002004110000000046000000B4 +:1013000000600811000001B2000000000080000031 +:10131000000000000000A1FC0020441100000000BB +:1013200000003FFF002F022F00000000000000001F +:101330000CC000000000019B00000001008048116B +:1013400000000000000000210080481100000000A3 +:101350000000FFFF40280E200000000000000010E9 +:10136000C0211220000000000000FFFF40281620CE +:101370000000000000000010C0811A2000000000E2 +:101380008100000000204411000000000000000661 +:1013900000204811000000000000000800221E305C +:1013A000000000000000002900201A2D00000000AD +:1013B0000000E0000020441100000000FFFBFF09D6 +:1013C00000204811000000000000000F0020222D26 +:1013D0000000000000001FFF00294A280000000054 +:1013E000000000060020222D000000000000000088 +:1013F000002920E80000000000000000002048084C +:101400000000000000000000002048110000000063 +:10141000060A020000294A26000000000000000021 +:1014200000204811000000000000000000204811CA +:101430000000000000000100002018110000000062 +:101440000000000800621E280000012F00000008B4 +:1014500000822228000000000002C0000020441189 +:10146000000000000000001500600E2D000001BD0E +:101470000000001600600E2D000001BD0000C00835 +:1014800000204411000000000000001700200E2D75 +:10149000000000000000000014C00000000001B9BE +:1014A0000000000000200411000000000000000007 +:1014B0000020480100000000390000000020481111 +:1014C00000000000000000000020481100000000A3 +:1014D000000000000080480200000000000000182A +:1014E00000202E2D0000000000000000003B0D63D6 +:1014F000000000000000000800224A230000000055 +:101500000000001000224A23000000000000001824 +:1015100000224A2300000000000000000080480371 +:101520000000000000000000006000000000000B50 +:10153000000010000060041100000315000000000E +:1015400000200411000000000000000000600811ED +:10155000000001B2000000070021062F000000007B +:101560000000001300200A2D000000000000000110 +:1015700000202C11000000000000FFFF4028222066 +:10158000000000000000000F0026222800000000DC +:101590000000001040212620000000000000000F85 +:1015A000002626290000000000000000002028027C +:1015B000000000000000225600204411000000003E +:1015C0000000001B00204811000000000000000087 +:1015D000002F022100000000000000000CE00000CD +:1015E000000001E00000225C002044110000000027 +:1015F0000000008100204811000000000000A1FC54 +:1016000000204411000000000000000100204811EB +:10161000000000000000008000201C1100000000FD +:1016200000000000002F0227000000000000000062 +:101630000CE00000000001DC000000000060000081 +:10164000000001E90000000100531E27000001D83E +:101650000000000100202C11000000000000001F0D +:1016600000280A22000000000000001F00282A2A8B +:10167000000000000000000100530621000001D11D +:101680000000225C00204411000000000000000265 +:1016900000304A2F000000000000A1FC002044118F +:1016A00000000000000000010020481100000000C0 +:1016B0000000000100301E2F0000000000000000AC +:1016C000002F022700000000000000000CE00000D6 +:1016D000000000000000000000600000000001E9C0 +:1016E0000000000100531E27000001E50000FFFF7D +:1016F00040280E20000000000000000F00260E23EE +:101700000000000000000010C021122000000000B6 +:101710000000000F0026122400000000000000005E +:1017200000201411000000000000000000601811EB +:10173000000002BB0001A1FD0020441100000000D8 +:1017400000000000002F022B00000000000000003D +:101750000CE00000000001F8000000100022162834 +:1017600000000000FFFF0000002816250000000018 +:101770000000FFFF00281A29000000000000000000 +:10178000002948C500000000000000000020480AB1 +:10179000000000000000000000202C1100000000EC +:1017A000000000100022162300000000FFFF0000D0 +:1017B00000281625000000000000FFFF00281A2462 +:1017C0000000000000000000002948C500000000E3 +:1017D0000000000000731503000002050000000077 +:1017E0000020180500000000000000000073152410 +:1017F0000000020500000000002D14C500000000DC +:1018000000000000003008A20000000000000000FE +:101810000020480200000000000000000020280214 +:101820000000000000000000002020030000000075 +:101830000000000000802404000000000000000FF1 +:1018400000210225000000000000000014C000007C +:101850000000068C00000000002B140500000000B2 +:1018600000000001009016250000000000000000AC +:10187000006000000000000B000000000060041188 +:10188000000003150000000000200411000000000B +:101890000000000000600811000001B200002256A4 +:1018A00000204411000000000000001A00294A2214 +:1018B0000000000000000000C02000000000000048 +:1018C00000003FFF002F022F00000000000000007A +:1018D0000CE000000000000000000000C020040038 +:1018E000000000000000225C002044110000000005 +:1018F0000000000300384A21000000000000A1FCA5 +:1019000000204411000000000000000100204811E8 +:10191000000000000000FFFF40281220000000002F +:1019200000000010C0211A20000000000000FFFF8E +:1019300040280E200000000000000010C0211620EA +:10194000000000000000000000741465000002BBED +:101950000001A1FD00604411000002E00000000150 +:10196000003306210000000000000000002F0221CB +:1019700000000000000000000CC000000000021980 +:1019800000003FFF002F022F0000000000000000B9 +:101990000CC000000000021200000000C040040063 +:1019A000000000010000000000600000000006458B +:1019B000000000000040040F0000021300000000BF +:1019C0000060000000000631000000000060000020 +:1019D000000006450000021000600411000003151D +:1019E0000000000000600000000001A000000000F6 +:1019F000006000000000019C00000000006000008A +:101A0000000002BB0000000000600000000002A314 +:101A1000938000000020441100000000000000003E +:101A2000002048080000000000000000002F022FE6 +:101A300000000000000000000AE000000000023288 +:101A400000000000006000000000013A00000000FB +:101A50000040000000000236950000000020441104 +:101A60000000000000000000002F022F0000000016 +:101A7000000000000CE00000000002360000000042 +:101A8000C0404800000002339200000000204411D2 +:101A90000000000000000000C0204800000000001E +:101AA0000000225600204411000000000000001633 +:101AB00000204811000000000000225C00204411BA +:101AC000000000000000000300204811000000009A +:101AD0000000A1FC002044110000000000000001F3 +:101AE00000204811000000000001A1FD0020441169 +:101AF000000000000000000000600411000002FB74 +:101B000000000000C04004000000000100000000D0 +:101B100000600000000006310000A00C002044110D +:101B20000000000000000000C0204800000000008D +:101B300000000000C040480000000000000000005D +:101B4000006000000000000B0000001840210A2087 +:101B50000000000000000003002F0222000000002F +:101B6000000000000AE000000000024C0000001429 +:101B70000020222D00000000000801010029222879 +:101B800000000000000000140020362800000000C3 +:101B90000000A30C00204411000000000000000021 +:101BA000C02048000000000000000000C0204800E5 +:101BB0000000000000000000C0404800000002518A +:101BC00000000000006000000000000B000000109A +:101BD00000600411000003153F8000000020041184 +:101BE000000000000000000000600811000001B2C9 +:101BF0000000225C002044110000000000000003EF +:101C000000204811000000000000000000600000FB +:101C10000000027C0000001700201E2D00000000C4 +:101C20000000000100211E2700000000000000004D +:101C300014E000000000026A0000001200201E2DC7 +:101C4000000000000000FFFF00281E270000000029 +:101C50000000000000341C2700000000000000000D +:101C600012C000000000025F0000000000201C11F4 +:101C70000000000000000000002F00E50000000050 +:101C80000000000008C00000000002620000000028 +:101C900000201407000000000000001200201E2D8C +:101CA000000000000000001000211E2700000000BE +:101CB0000000000000341C4700000000000000008D +:101CC00012C00000000002670000000000201C118C +:101CD0000000000000000000002F00E600000000EF +:101CE0000000000008C000000000026A00000000C0 +:101CF0000020180700000000000000000060000045 +:101D0000000002C100002256002044110000000023 +:101D1000000000000034202300000000000000004C +:101D200012C00000000002720000000000342044D5 +:101D3000000000000000000012C00000000002715E +:101D40000000001600404811000002760000001854 +:101D500000404811000002760000000000342044DA +:101D6000000000000000000012C00000000002752A +:101D70000000001700404811000002760000001922 +:101D800000204811000000000000A1FC00204411C8 +:101D900000000000000000010020481100000000C9 +:101DA0000001A1FD00604411000002E900003FFFB6 +:101DB000002F022F00000000000000000CC00000F7 +:101DC0000000025600000000C040040000000001B6 +:101DD0000000001040210620000000000000FFFF6E +:101DE000C0280A20000000000000001040210E2042 +:101DF000000000000000FFFFC028122000000000CB +:101E00000000001040211620000000000000FFFF2D +:101E1000C0881A200000000081000000002044114A +:101E20000000000000000001002048110000000038 +:101E300000042004006044110000068D0000000032 +:101E4000006000000000063100000000C0600000DB +:101E5000000002A30000000500200A2D0000000081 +:101E60000000000800220A22000000000000002BF1 +:101E700000201A2D000000000000001C00201E2D74 +:101E8000000000000000700000281E270000000075 +:101E90000000000000311CE6000000000000002AE5 +:101EA00000201A2D000000000000000C00221A265D +:101EB0000000000000000000002F00E6000000000D +:101EC0000000000006E00000000002920000000098 +:101ED00000201C11000000000000000000200C1178 +:101EE000000000000000002B00203623000000004E +:101EF0000000001000201811000000000000000089 +:101F000000691CE20000012F9380000000204411B2 +:101F10000000000000000000002048070000000052 +:101F200095000000002044110000000000000000A7 +:101F3000002F022F00000000000000000CE0000055 +:101F40000000029D0000000100333E2F0000000051 +:101F500000000000D90048000000000092000000CE +:101F6000002044110000000000000000C0204800D4 +:101F7000000000000000001C0040362700000000A8 +:101F80000000000CC0220A20000000000000002910 +:101F9000002036220000000000000028C04036204B +:101FA000000000000000A2A4002044110000000076 +:101FB000000000090020481100000000A1000000FE +:101FC00000204411000000000000000100804811C2 +:101FD000000000000000002100201E2D0000000075 +:101FE00000000000002C1CE30000000000000021A5 +:101FF00000203627000000000000002200201E2DD7 +:102000000000000000000000002C1CE400000000A4 +:1020100000000022002036270000000000000023FE +:1020200000201E2D0000000000000000003120A351 +:102030000000000000000000002D1D07000000004F +:1020400000000023002036270000000000000024CC +:1020500000201E2D0000000000000000003120C400 +:102060000000000000000000002D1D07000000001F +:10207000000000240080362700000000000000213E +:10208000002036230000000000000022002036243B +:10209000000000000000000000311CA30000000050 +:1020A0000000002300203627000000000000000090 +:1020B00000311CC40000000000000024008036270E +:1020C000000000000000001A002036270000000079 +:1020D0000000001B00203628000000000000001750 +:1020E00000201E2D00000000000000020021022739 +:1020F000000000000000000014C00000000002DC2E +:102100000000000000400000000002D90000001A9A +:1021100000203627000000000000001B00203628A9 +:10212000000000000000001700201E2D000000002D +:102130000000000200210227000000000000000053 +:1021400014E00000000002D9000000030021022773 +:10215000000000000000000014E00000000002DCAD +:102160000000002300201E2D0000000000000000E1 +:10217000002E00E1000000000000000002C000008E +:10218000000002DC0000002100201E2D00000000E5 +:1021900000000000003120A100000000000000004D +:1021A000002E00E8000000000000000006C0000053 +:1021B000000002DC0000002400201E2D00000000B2 +:1021C00000000000002E00E20000000000000000FF +:1021D00002C00000000002DC0000002200201E2DD2 +:1021E0000000000000000000003120C200000000DC +:1021F00000000000002E00E80000000000000000C9 +:1022000006C00000000002DC0000000000600000CA +:10221000000006680000000000600000000002B539 +:102220000000000000400000000002DE000000008E +:1022300000600000000002B5000000000060000027 +:102240000000065F0000000000400000000002DE09 +:102250000000000000600000000002A70000000075 +:1022600000400000000002DE0000001A00201E2DC9 +:10227000000000000000001B0080222D0000000074 +:102280000000001000221E230000000000000000DB +:1022900000294887000000000000000000311CA356 +:1022A000000000000000001000221E2700000000B7 +:1022B0000000000000294887000000000000001016 +:1022C00000221E230000000000000000003120C496 +:1022D000000000000000FFFF00282228000000008E +:1022E0000000000000894907000000000000001005 +:1022F00000221E2300000000000000000029488783 +:10230000000000000000001000221E21000000005C +:102310000000000000294847000000000000000005 +:1023200000311CA3000000000000001000221E2746 +:1023300000000000000000000029488700000000A5 +:102340000000000000311CA100000000000000108F +:1023500000221E270000000000000000002948475E +:10236000000000000000001000221E2300000000FA +:1023700000000000003120C4000000000000FFFF4A +:102380000028222800000000000000000029490762 +:10239000000000000000001000221E2100000000CC +:1023A00000000000003120C2000000000000FFFF1C +:1023B00000282228000000000000000000894907D2 +:1023C000000000000000001000221E23000000009A +:1023D0000000000000294887000000000000000104 +:1023E00000220A210000000000000000003308A2C3 +:1023F000000000000000001000221E22000000006B +:102400000000001000212222000000000000000057 +:1024100000294907000000000000000000311CA353 +:10242000000000000000001000221E270000000035 +:1024300000000000002948870000000000000001A3 +:1024400000220A210000000000000000003008A265 +:10245000000000000000001000221E22000000000A +:1024600000000010002122220000000000000000F7 +:1024700000294907000000000000001000221E2370 +:102480000000000000000000003120C40000000037 +:102490000000FFFF002822280000000000000000CC +:1024A000002949070000000000000000003808C5AE +:1024B00000000000000000000030084100000000A3 +:1024C0000000000100220A220000000000000000BD +:1024D000003308A2000000000000001000221E22AD +:1024E0000000000000000010002122220000000077 +:1024F00000000000008949070000000000000017EC +:102500000020222D000000000000000014C0000088 +:1025100000000318FFFFFFEF002806210000000065 +:10252000000000140020222D000000000000F8E050 +:1025300000204411000000000000000000294901B3 +:1025400000000000000000000089490100000000B8 +:102550000000000000204811000000000000000002 +:102560000020481100000000060A02000080481107 +:102570000000000000000000C0200000000000007B +:1025800097000000C020441100000000000000007F +:10259000C0204811000000008A0000000020441103 +:1025A00000000000000000000020481100000000B2 +:1025B0000000225C00204411000000000000000028 +:1025C000C0204800000000000000A1FC00204411D1 +:1025D0000000000000000000C020480000000000D3 +:1025E00000000000C0200400000000000000000007 +:1025F00000A0000A00000000970000000020441125 +:102600000000000000000000002048110000000051 +:102610008A000000002044110000000000000000BB +:1026200000204811000000000000225C002044113E +:102630000000000000000000C02048000000000072 +:102640000000A1FC00204411000000000000000078 +:10265000C02048000000000000000000C02004006E +:10266000000000000000000000A0000A00000000C0 +:10267000970000000020441100000000000000004E +:1026800000204811000000008A00000000204411D2 +:1026900000000000000000000020481100000000C1 +:1026A0000000225C00204411000000000000000037 +:1026B000C0204800000000000000A1FC00204411E0 +:1026C0000000000000000000C020480000000000E2 +:1026D0000001A1FD002044110000000000000000E6 +:1026E000D90048000000000000000000C0200400E5 +:1026F000000000000000000000A0000A0000000030 +:1027000000002257002044110000000000000003D8 +:10271000C0484A20000000000000225D0020441153 +:102720000000000000000000C04048000000000061 +:1027300000000000006000000000064500000000EE +:10274000C0200800000000000000225C00204411AE +:10275000000000000000000300384A2200000000D2 +:102760000000A1FC00204411000000000000000057 +:10277000C0204800000000000001A1FD002044111D +:102780000000000000000000002F022200000000F6 +:10279000000000000CE0000000000000000000004D +:1027A00040204800000000000000000140304A20A6 +:1027B0000000000000000002C0304A2000000000BD +:1027C0000000000100530A220000034B0000003FFC +:1027D000C0280A20000000008100000000204411F1 +:1027E000000000000000000100204811000000006F +:1027F000000021F800204411000000000000001833 +:102800000020481100000000000421F9006044117C +:102810000000068D000000110021023000000000C1 +:102820000000000014E00000000003540000001449 +:10283000002F022200000000000000000CC0000079 +:10284000000003640000201000204411000000007C +:102850000000800000204811000000000001A2A438 +:102860000020441100000000000000000060480249 +:102870000000036E00002100002044110000000051 +:1028800000000000C0204800000000000000000020 +:10289000C02048000000000000000000C0204800E8 +:1028A0000000000000000000C040480000000000E0 +:1028B00000000004002F02220000000000000000C1 +:1028C0000CC000000000036A00002010002044112A +:1028D00000000000000080000020481100000000FF +:1028E0000001A2A40020441100000000000000002C +:1028F000004048020000035F00000028002F022271 +:1029000000000000000000000CC00000000005C036 +:102910000001A2A4002044110000000000000000FB +:10292000004048020000035F0000002C0020362613 +:102930000000000000000049002018110000000005 +:102940000000003F002048110000000000000001CE +:1029500000331A260000000000000000002F0226AD +:1029600000000000000000000CC000000000037028 +:102970000000002C00801A2D000000000000003F25 +:10298000C0280A200000000000000015002F0222CD +:1029900000000000000000000CE0000000000386C2 +:1029A00000000006002F02220000000000000000CE +:1029B0000CE00000000003B100000016002F02220E +:1029C00000000000000000000CE00000000003B563 +:1029D00000000020002F0222000000000000000084 +:1029E0000CE000000000039C0000000F002F0222FA +:1029F00000000000000000000CE00000000003A840 +:102A000000000010002F0222000000000000000063 +:102A10000CE00000000003A80000001E002F0222AE +:102A200000000000000000000CE000000000039027 +:102A30000000A2A4002044110000000000000000DB +:102A400000404802000000000800000000290A229F +:102A5000000000000000000340210E2000000000E4 +:102A60000000000CC021122000000000000800003F +:102A7000002812240000000000000014C0221620CC +:102A80000000000000000000002914A40000000065 +:102A90000000A2A40020441100000000000000007B +:102AA000002948A2000000000000A1FE00204411FF +:102AB000000000000000000000404803000000008B +:102AC000810000000020441100000000000000010F +:102AD0000020481100000000000021F800204411EF +:102AE0000000000000000016002048110000000057 +:102AF000000421F9006044110000068D000000155B +:102B000000210230000000000000000014E000007E +:102B1000000003920000210E00204411000000007C +:102B200000000000C020480000000000000000007D +:102B3000C0204800000000000000A2A400204411B2 +:102B400000000000000000000040480200000000FB +:102B5000810000000020441100000000000000017E +:102B60000020481100000000000021F8002044115E +:102B700000000000000000170020481100000000C5 +:102B8000000421F9006044110000068D00000003DC +:102B900000210230000000000000000014E00000EE +:102BA0000000039E000021080020441100000000E6 +:102BB00000000000C02048000000000000000000ED +:102BC000C0204800000000000000A2A40020441122 +:102BD000000000000000000000404802000000006B +:102BE0000000A2A40020441100000000000000002A +:102BF0000020480200000000800000000020441176 +:102C0000000000000000000000204811000000004B +:102C100081000000002044110000000000000010AE +:102C200000204811000000000000000000200010FB +:102C3000000000000000000014C00000000003AE0F +:102C40000000000000400000000000000000201014 +:102C50000020441100000000000080000020481106 +:102C6000000000000001A2A40020441100000000A8 +:102C70000000000600404811000000000000201085 +:102C800000204411000000000000800000204811D6 +:102C9000000000000001A2A4002044110000000078 +:102CA00000000016006048110000036E00000000E4 +:102CB000004000000000000000000000C0200800EC +:102CC0000000000000000000C0200C000000000018 +:102CD0000000001D00210223000000000000000091 +:102CE00014E00000000003CE810000000020441129 +:102CF000000000000000000100204811000000005A +:102D0000000021F80020441100000000000000181D +:102D10000020481100000000000421F90060441167 +:102D20000000068D000000110021023000000000AC +:102D30000000000014E00000000003C000002100BB +:102D400000204411000000000000000000204802A4 +:102D50000000000000000000002048030000000008 +:102D6000BABECAFE0020481100000000CAFEBABE6A +:102D70000020481100000000000020100020441135 +:102D8000000000000000800000204811000000004A +:102D90000000A2A400204411000000000000000474 +:102DA0000040481100000000000021700020441184 +:102DB00000000000000000000020480200000000A9 +:102DC0000000000000204803000000008100000017 +:102DD00000204411000000000000000A00204811FB +:102DE00000000000000000000020001000000000B3 +:102DF0000000000014C00000000003D38C0000009D +:102E00000020441100000000CAFEBABE0040481174 +:102E100000000000810000000020441100000000BC +:102E200000000001002048110000000000003FFFEA +:102E300040280A20000000008000000040280E20EA +:102E40000000000040000000C02812200000000028 +:102E500000040000006946220000068D000000000A +:102E6000002014100000000000000000002F0223CA +:102E700000000000000000000CC00000000003E1A2 +:102E800000000000C0401800000003E400003FFF05 +:102E9000C0281A2000000000000400000069462637 +:102EA0000000068D00000000002018100000000047 +:102EB00000000000002F02240000000000000000BD +:102EC0000CC00000000003E700000000C0401C0030 +:102ED000000003EA00003FFFC0281E2000000000A1 +:102EE00000040000006946270000068D0000000075 +:102EF00000201C1000000000000000000020440220 +:102F00000000000000000000002820C500000000B4 +:102F100000000000004948E800000000A580000013 +:102F200000200811000000000000200000200C110B +:102F30000000000083000000006044110000041243 +:102F4000000000000020440200000000000000001B +:102F5000C0204800000000000000000040204800A1 +:102F6000000000000000001FC0210220000000003F +:102F70000000000014C00000000003F70000201053 +:102F800000204411000000000000800000204811D3 +:102F9000000000000000FFFFC0481220000003FFF7 +:102FA000A780000000200811000000000000A00021 +:102FB00000200C110000000083000000006044119C +:102FC0000000041200000000002044020000000085 +:102FD00000000000C02048000000000000000000C9 +:102FE000C0204800000000000000FFFFC0281220A1 +:102FF00000000000830000000020441100000000D9 +:103000000000000000304883000000008400000041 +:10301000002044110000000000000000C020480013 +:1030200000000000000000001D0000000000000083 +:103030008300000000604411000004120000000042 +:10304000C040040000000001A98000000020081119 +:10305000000000000000C00000400C11000003FA56 +:10306000AB80000000200811000000000000F8E024 +:1030700000400C11000003FAAD8000000020081190 +:10308000000000000000F88000400C11000003FA6E +:10309000B380000000200811000000000000F3FCD5 +:1030A00000400C11000003FAAF800000002008115E +:1030B000000000000000E00000400C11000003FAD6 +:1030C000B180000000200811000000000000F000A6 +:1030D00000400C11000003FA83000000002044119E +:1030E00000000000000021480020481100000000FE +:1030F00084000000002044110000000000000000D7 +:10310000C020480000000000000000001D0000007A +:10311000000000000000000000800000000000002F +:1031200001182000C0304620000000000000000010 +:10313000D90048000000000000000000C02004008A +:10314000000000000000000000A0000A00000000D5 +:103150000218A000C030462000000000000000005F +:10316000D90048000000000000000000C02004005A +:10317000000000000000000000A0000A00000000A5 +:103180000318C000C030462000000000000000000E +:10319000D90048000000000000000000C02004002A +:1031A000000000000000000000A0000A0000000075 +:1031B0000418F8E0C03046200000000000000000C5 +:1031C000D90048000000000000000000C0200400FA +:1031D000000000000000000000A0000A0000000045 +:1031E0000518F880C03046200000000000000000F4 +:1031F000D90048000000000000000000C0200400CA +:10320000000000000000000000A0000A0000000014 +:103210000618E000C030462000000000000000005A +:10322000D90048000000000000000000C020040099 +:10323000000000000000000000A0000A00000000E4 +:103240000718F000C0304620000000000000000019 +:10325000D90048000000000000000000C020040069 +:10326000000000000000000000A0000A00000000B4 +:103270000818F3FCC03046200000000000000000E9 +:10328000D90048000000000000000000C020040039 +:10329000000000000000000000A0000A0000000084 +:1032A0000000003000200A2D000000000000000097 +:1032B000C0290C4000000000000000300020362330 +:1032C0000000000000000000C0200400000000001A +:1032D0000000000000A0000A0000000086000000BE +:1032E00000204411000000000000000000404801E0 +:1032F0000000000085000000C02044110000000014 +:103300000000000000404801000000000000217C97 +:10331000002044110000000000000018402102209D +:10332000000000000000000014C000000000044580 +:1033300000800000C0494A20000004460000000050 +:10334000C02048000000000000000000C02048002D +:103350000000000000000000C02048000000000045 +:103360008100000000204411000000000000000166 +:10337000002048110000000000000000C0200800EC +:103380000000000000000000170000000000000026 +:103390000004217F006044110000068D0000001F22 +:1033A00000210230000000000000000014C00000F6 +:1033B000000000000000000000404C020000044B30 +:1033C00000000000C0200C00000000000000000011 +:1033D000C02010000000000000000000C020140009 +:1033E0000000000000000000C020180000000000E5 +:1033F00000000000C0201C000000000000007F0052 +:1034000000280A210000000000004500002F0222D1 +:1034100000000000000000000CE000000000045963 +:1034200000000000C020200000000000000000009C +:1034300017000000000000000000001000280A2310 +:103440000000000000000010002F02220000000019 +:10345000000000000CE0000000000461810000009A +:10346000002044110000000000000001002048116D +:103470000000000000040000006946240000068DE2 +:103480000000000000400000000004668100000011 +:10349000002044110000000000000000002048113E +:1034A000000000000000216D002044110000000019 +:1034B00000000000002048040000000000000000A0 +:1034C000006048050000069200000000002824F07B +:1034D000000000000000000700280A230000000090 +:1034E00000000001002F0222000000000000000088 +:1034F0000AE000000000046D00000000002F00C979 +:10350000000000000000000004E00000000004864D +:1035100000000000004000000000049300000002D2 +:10352000002F022200000000000000000AE000005E +:103530000000047200000000002F00C9000000001D +:103540000000000002E0000000000486000000000F +:10355000004000000000049300000003002F02223E +:1035600000000000000000000AE0000000000477F6 +:1035700000000000002F00C9000000000000000053 +:103580000CE0000000000486000000000040000085 +:103590000000049300000004002F0222000000003D +:1035A000000000000AE000000000047C00000000B1 +:1035B000002F00C900000000000000000AE0000029 +:1035C000000004860000000000400000000004939A +:1035D00000000005002F0222000000000000000093 +:1035E0000AE000000000048100000000002F00C974 +:1035F000000000000000000006E00000000004865B +:1036000000000000004000000000049300000006DD +:10361000002F022200000000000000000AE000006D +:103620000000048600000000002F00C90000000018 +:103630000000000008E00000000004860000000018 +:10364000004000000000049300007F0000280A21D1 +:103650000000000000004500002F022200000000D2 +:10366000000000000AE00000000000000000000868 +:1036700000210A23000000000000000014C0000028 +:1036800000000490000021690020441100000000A7 +:1036900000000000C0204800000000000000000002 +:1036A000C02048000000000000000000C0204800CA +:1036B00000000000CAFEBABE004048110000000031 +:1036C00000000000C02044000000000000000000D6 +:1036D000C02000000000000000000000C0404800C2 +:1036E0000000000000007F0000280A210000000008 +:1036F00000004500002F0222000000000000000032 +:103700000AE000000000049900000000C020000052 +:103710000000000000000000C020000000000000C9 +:1037200000000000C0400000000000000000000099 +:1037300000404C080000045900000000C0200800B0 +:10374000000000000000001040210E2000000000DA +:1037500000000011402112200000000000000012B3 +:1037600040211620000000000000216900204411C3 +:1037700000000000000000000020480200000000DF +:1037800000000000002102250000000000000000F1 +:1037900014E00000000004A300040000C0494A2017 +:1037A000000004A4FFFBFFFFC0284A200000000027 +:1037B00000000000002102230000000000000000C3 +:1037C00014E00000000004B000000000C020480029 +:1037D0000000000000000000C020480000000000C1 +:1037E0000000000000210224000000000000000092 +:1037F00014C00000000000008100000000204411FF +:10380000000000000000000C002048110000000033 +:103810000000000000200010000000000000000078 +:1038200014C00000000004ACA000000000204411FF +:1038300000000000CAFEBABE0040481100000000AF +:10384000810000000020441100000000000000047E +:1038500000204811000000000000216B00204411EE +:103860000000000000000000C02048100000000020 +:10387000810000000020441100000000000000054D +:1038800000204811000000000000216C00204411BD +:103890000000000000000000C020481000000000F0 +:1038A00000000000002F02240000000000000000C3 +:1038B0000CE00000000000000000000000400000DC +:1038C000000004AA00000000C0210A20000000003F +:1038D0000000000014C00000000004C381000000CC +:1038E00000204411000000000000000000204811EA +:1038F000000000000000216D0020441100000000C5 +:1039000000000000C020480000000000000000008F +:10391000C060480000000692000000000040000067 +:10392000000004C7810000000020441100000000D6 +:103930000000000100204811000000000004000009 +:10394000C02946200000000000000000C060000008 +:103950000000068D0000000100210222000000008E +:103960000000000014C00000000004CE0000216927 +:10397000002044110000000000000000C0204800AA +:103980000000000000000000C0204800000000000F +:10399000000000000020481000000000CAFEBABE6F +:1039A000004048110000000000000000C02044005A +:1039B0000000000000000000C040481000000000AF +:1039C0008100000000204411000000000000000100 +:1039D0000020481100000000000021F800204411E0 +:1039E000000000000000000E002048110000000050 +:1039F000000421F9006044110000068D0000000061 +:103A000000210230000000000000000014C000008F +:103A1000000004D0000021800020441100000000BC +:103A200000000000C020480000000000000000006E +:103A3000C02000000000000000000000C02048007E +:103A40000000000000000000C02000000000000096 +:103A500000000000C040480000000000000000031B +:103A600000333E2F00000000000000010021022171 +:103A7000000000000000000014E00000000005004D +:103A80000000002C00200A2D0000000000040000AF +:103A900018E00C11000004EF0000000100333E2F7D +:103AA0000000000000002169002044110000000017 +:103AB000000000000020480200000000000000009C +:103AC00000204803000000000000000800300A2227 +:103AD0000000000000000000C020480000000000BE +:103AE00000000000C0204800000000000000216924 +:103AF00000204411000000000000000000204802E7 +:103B0000000000000000000000204803000000004A +:103B10000000000800300A22000000000000000041 +:103B2000C02048000000000000000000D8C048008D +:103B3000000004E30000216900204411000000009F +:103B4000000000000020480200000000000000000B +:103B500000204803000000000000000800300A2296 +:103B60000000000000000000C0204800000000002D +:103B700000000000C0204800000000000000002DF0 +:103B80000020122D000000000000000000290C831E +:103B90000000000000002169002044110000000026 +:103BA00000000000002048020000000000000000AB +:103BB00000204803000000000000000800300A2236 +:103BC0000000000000000000C020480000000000CD +:103BD00000000000C02048000000000000000011AC +:103BE00000210224000000000000000014C00000BA +:103BF000000000000000000000400000000004AAD7 +:103C00000000002CC0203620000000000000002D25 +:103C1000C0403620000000000000000F00210221FB +:103C2000000000000000000014C0000000000505B6 +:103C300000000000006000000000000B0000000019 +:103C4000D90000000000000000000000C040040097 +:103C500000000001B5000000002044110000000039 +:103C6000000020000020481100000000B600000005 +:103C700000204411000000000000A00000204811B6 +:103C800000000000B7000000002044110000000008 +:103C90000000C0000020481100000000B800000033 +:103CA00000204411000000000000F8E0002048114E +:103CB00000000000B90000000020441100000000D6 +:103CC0000000F8800020481100000000BA00000049 +:103CD00000204411000000000000E0000020481116 +:103CE00000000000BB0000000020441100000000A4 +:103CF0000000F0000020481100000000BC0000009F +:103D000000204411000000000000F3FC00204811D6 +:103D100000000000810000000020441100000000AD +:103D2000000000020020481100000000000000FF19 +:103D300000280E300000000000000000002F0223C9 +:103D400000000000000000000CC000000000051989 +:103D500000000000C020080000000000000000007B +:103D600014C000000000052E0000000000200C110F +:103D7000000000000000001C0020362300000000AE +:103D80000000002B00203623000000000000002966 +:103D90000020362300000000000000280020362309 +:103DA0000000000000000017002036230000000083 +:103DB000000000250020362300000000000000263F +:103DC00000203623000000000000001500203623EC +:103DD0000000000000000016002036230000000054 +:103DE000FFFFE00000200C11000000000000002197 +:103DF00000203623000000000000002200203623AF +:103E00000000000000001FFF00200C110000000057 +:103E100000000023002036230000000000000024E2 +:103E20000020362300000000F1FFFFFF00283A2E9B +:103E3000000000000000001AC0220E200000000058 +:103E4000000000000029386E000000008100000022 +:103E5000002044110000000000000006002048116E +:103E6000000000000000002A402036200000000072 +:103E70008700000000204411000000000000000046 +:103E8000C0204800000000000000A1F40020441100 +:103E900000000000000000000020481000000000AA +:103EA0000000000000200C110000000000000030A5 +:103EB00000203623000000009D0000000020441177 +:103EC000000000000000001F40214A200000000008 +:103ED00096000000002044110000000000000000D7 +:103EE000C02048000000000000000000C0200C00BE +:103EF0000000000000000000C020100000000000D2 +:103F00000000001F00211624000000000000000037 +:103F100014C00000000000000000001D0020362337 +:103F2000000000000000000300281E230000000025 +:103F3000000000080022222300000000FFFFF00024 +:103F4000002822280000000000000000002920E8CE +:103F5000000000000000001F0020362800000000C4 +:103F60000000001800211E230000000000000020B7 +:103F70000020362700000000000000020022162466 +:103F80000000000000000000003014A80000000045 +:103F90000000001E00203625000000000000000385 +:103FA00000211A24000000001000000000281A263A +:103FB00000000000EFFFFFFF00283A2E0000000085 +:103FC00000000000004938CE0000067B0000000120 +:103FD00040280A20000000000000000640280E20B3 +:103FE0000000000000000300C028122000000000B4 +:103FF0000000000800211224000000000000000062 +:10400000C02016200000000000000000C0201A2080 +:10401000000000000000000000210222000000005B +:104020000000000014C000000000056681000000D0 +:104030000020441100000000000000010020481191 +:10404000000000000000225800300A240000000098 +:1040500000040000006946220000068D000021696E +:10406000002044110000000000000000002048056E +:10407000000000000002000000294A2600000000A5 +:10408000000000000020481000000000CAFEBABE78 +:10409000002048110000000000000002002F022351 +:1040A00000000000000000000CC000000000056ED1 +:1040B00000000000C0201C100000000000000000F4 +:1040C000C04000000000057C00000002002F022319 +:1040D00000000000000000000CC000000000056EA1 +:1040E00081000000002044110000000000000001D9 +:1040F00000204811000000000000225800300A246F +:104100000000000000040000006946220000068D47 +:1041100000000000C0201C10000000000000000093 +:10412000C04000000000057C00000000002F0223BA +:1041300000000000000000000CC00000000005723C +:1041400000000000C0201C00000000000000000073 +:10415000C04000000000057C00000004002F022386 +:1041600000000000000000000CC000000000057A04 +:104170008100000000204411000000000000000049 +:1041800000204811000000000000216D00204411B3 +:104190000000000000000000C020480000000000F7 +:1041A00000000000C060480000000692000000000F +:1041B00000401C100000057C00000000C020000032 +:1041C0000000000000000000C040000000000000EF +:1041D000000000000EE000000000057E000000006E +:1041E00000600000000005C900000000002F02244C +:1041F00000000000000000000CC000000000058F5F +:104200000000A2B7002044110000000000000000E0 +:104210000020480700000000810000000020441139 +:104220000000000000000001002048110000000014 +:104230000004A2B6006044110000068D0000001AC0 +:10424000002122300000000000000006002226307D +:104250000000000000042004006044110000068DEE +:104260000000A2C400204411000000000000000073 +:10427000003048E9000000000000000000E00000FD +:104280000000058D0000A2D10020441100000000B4 +:104290000000000000404808000000000000A2D11B +:1042A00000204411000000000000000100504A28D6 +:1042B0000000000000000001002F022400000000A8 +:1042C000000000000CC00000000005A00000A2BB20 +:1042D00000204411000000000000000000204807FA +:1042E00000000000810000000020441100000000D8 +:1042F0000000000100204811000000000004A2BAE4 +:10430000006044110000068D0000001A00212230D8 +:10431000000000000000000600222630000000001F +:1043200000042004006044110000068D0000A2C5B6 +:10433000002044110000000000000000003048E9A7 +:10434000000000000000000000E000000000059EEA +:104350000000A2D200204411000000000000000074 +:1043600000404808000000000000A2D200204411D4 +:10437000000000000000000100504A28000000007A +:1043800000000002002F02240000000000000000D6 +:104390000CC00000000005B10000A2BF00204411C5 +:1043A000000000000000000000204807000000009E +:1043B0008100000000204411000000000000000106 +:1043C00000204811000000000004A2BE006044115B +:1043D0000000068D0000001A0021223000000000BD +:1043E0000000000600222630000000000004200427 +:1043F000006044110000068D0000A2C60020441198 +:104400000000000000000000003048E9000000004B +:104410000000000000E00000000005AF0000A2D393 +:104420000020441100000000000000000040480887 +:10443000000000000000A2D3002044110000000092 +:104440000000000100504A28000000000000A2C344 +:104450000020441100000000000000000020480778 +:104460000000000081000000002044110000000056 +:104470000000000100204811000000000004A2C25A +:10448000006044110000068D0000001A0021223057 +:10449000000000000000000600222630000000009E +:1044A00000042004006044110000068D0000A2C733 +:1044B000002044110000000000000000003048E926 +:1044C000000000000000000000E00000000005BE49 +:1044D0000000A2D4002044110000000000000000F1 +:1044E00000404808000000000000A2D40020441151 +:1044F000000000000000000100504A2800000000F9 +:1045000085000000002044110000000000000000B1 +:1045100000204801000000000000304A0020441143 +:104520000000000001000000002048110000000011 +:104530000000000000400000000005C4A4000000CE +:10454000C02044110000000000000000C0404800EE +:104550000000000000000000C0600000000005C96D +:1045600000000000C0400400000000010000002C1A +:1045700000203621000000008100000000204411CE +:1045800000000000000000060020481100000000AC +:1045900000000000002F02300000000000000000BA +:1045A0000CC00000000005D0000000000020041135 +:1045B000000000000000003000403621000005E34C +:1045C000000000300020062D0000000000007E00EA +:1045D000002806210000000000000000002F02213A +:1045E00000000000000000000CE00000000005E3F7 +:1045F00081000000002044110000000000000001C4 +:1046000000204811000000000004A0920060441146 +:104610000000068D00000031002036300000000050 +:104620000004A093006044110000068D00000032D9 +:1046300000203630000000000004A2B600604411E3 +:104640000000068D0000003300203630000000001E +:104650000004A2BA006044110000068D000000347E +:1046600000203630000000000004A2BE00604411AB +:104670000000068D000000350020363000000000EC +:104680000004A2C2006044110000068D0000003644 +:1046900000203630000000000004200400604411B7 +:1046A0000000068D0001A2A40020441100000000BB +:1046B0000000003F00204811000000000000003F03 +:1046C00000204811000000000000003F00204811B9 +:1046D000000000000000003F002048110000000022 +:1046E0000000000500204811000000000000A1F4B7 +:1046F00000204411000000000000000000204811CC +:1047000000000000880000000020441100000000AC +:10471000000000010020481100000000810000009E +:104720000020441100000000000000060020481195 +:104730000000000000000001002F02300000000017 +:10474000000000000CE000000000062C000000301B +:104750000020062D0000000000000000002F0221B4 +:1047600000000000000000000CE000000000062C2B +:104770008100000000204411000000000000000142 +:10478000002048110000000000007E0000280621E3 +:104790000000000000000000002F022100000000C7 +:1047A000000000000CE00000000006050000A092E0 +:1047B00000204411000000000000003100204A2DBC +:1047C000000000000000A093002044110000000041 +:1047D0000000003200204A2D000000000000A2B6B8 +:1047E00000204411000000000000003300204A2D8A +:1047F000000000000000A2BA0020441100000000E8 +:104800000000003400204A2D000000000000A2BE7D +:1048100000204411000000000000003500204A2D57 +:10482000000000000000A2C20020441100000000AF +:104830000000003600204A2D00000000000000307B +:104840000020062D00000000000001FF00280621C6 +:104850000000000000000000002F02210000000006 +:10486000000000000CE000000000062B000000002B +:1048700000210221000000000000000014C0000020 +:104880000000060E0004A003006044110000068D25 +:104890000000A00300204411000000000000000000 +:1048A0000020481000000000000000010021062147 +:1048B000000000000000000014C00000000006130B +:1048C0000004A010006044110000068D0000A0103C +:1048D00000204411000000000000000000204810EB +:1048E000000000000000000100210621000000007F +:1048F00000000000002F0221000000000000000066 +:104900000CE000000000062B0004A0110060441120 +:104910000000068D0000A0110020441100000000DE +:104920000000000000204810000000000004A01259 +:10493000006044110000068D0000A0120020441108 +:1049400000000000000000000020481000000000EF +:104950000004A013006044110000068D0000A013A5 +:10496000002044110000000000000000002048105A +:10497000000000000004A014006044110000068D37 +:104980000000A014002044110000000000000000FE +:1049900000204810000000000004A0150060441131 +:1049A0000000068D0000A01500204411000000004A +:1049B0000000000000204810000000000004A016C5 +:1049C000006044110000068D0000A0160020441174 +:1049D000000000000000000000204810000000005F +:1049E0000004A017006044110000068D0000A0170D +:1049F00000204411000000000000000000204810CA +:104A00000000000000042004006044110000068D36 +:104A10000000002C0080062D00000000FF000000B8 +:104A20000020441100000000000000000020481198 +:104A300000000000000000010020481100000000FC +:104A4000000000020080481100000000000000008B +:104A50000EE000000000063D000000300020062DA2 +:104A600000000000000000020028062100000000F5 +:104A700000000000002F02210000000000000000E4 +:104A80000CE000000000063B810000000020441103 +:104A9000000000000000000100204811000000009C +:104AA00000042004006044110000068D0000100086 +:104AB00000200811000000000000002B002036221A +:104AC000000000000000000000600000000006413F +:104AD0000000000000600000000005C99800000010 +:104AE0000020441100000000000000000080481178 +:104AF0000000000000000000C0600000000006414F +:104B000000000000C0400400000000010000A2A45A +:104B10000020441100000000000000220020481185 +:104B20000000000089000000002044110000000087 +:104B300000000001004048110000062D9700000011 +:104B40000020441100000000000000000020481177 +:104B5000000000008A000000002044110000000056 +:104B600000000000004048110000062D0000000079 +:104B7000006000000000065C0000201000204411CE +:104B8000000000000000800000204811000000002C +:104B90000001A2A4C0204411000000000000001683 +:104BA000006048110000036E000020100020441136 +:104BB000000000000001000000204811000000007B +:104BC00081000000002044110000000000000001EE +:104BD00000204811000000000000217C002044114A +:104BE00000000000098000000020481100000000C3 +:104BF000FFFFFFFF00204811000000000000000040 +:104C00000020481100000000000000001700000014 +:104C1000000000000004217F006044110000068DA8 +:104C20000000001F00210230000000000000000012 +:104C300014C00000000000000000000400404C11FF +:104C400000000656000000000040000000000000C8 +:104C50000000001700201E2D0000000000000004CE +:104C600000291E27000000000000001700803627E2 +:104C7000000000000000001700201E2D00000000B2 +:104C8000FFFFFFFB00281E270000000000000017A8 +:104C900000803627000000000000001700201E2DB5 +:104CA000000000000000000800291E27000000008E +:104CB00000000017008036270000000000000017E9 +:104CC00000201E2D00000000FFFFFFF700281E2718 +:104CD00000000000000000170080362700000000E0 +:104CE000000020100020441100000000000080009F +:104CF00000204811000000000001A2A4002044117F +:104D00000000000000000016006048110000036E63 +:104D100000002010002044110000000000010000ED +:104D200000204811000000000000217C00204411F8 +:104D30000000000001800000002048110000000079 +:104D4000FFFFFFFF002048110000000000000000EE +:104D500000204811000000000000000017000000C3 +:104D6000000000008100000000204411000000004D +:104D70000000000100204811000000000004217F15 +:104D8000006044110000068D0000001F0021023069 +:104D9000000000000000000014C000000000068CAD +:104DA0000000001000404C110000067200000000DE +:104DB000C0200400000000000000000038C0000017 +:104DC000000000000000001D00200A2D000000006F +:104DD0000000001E00200E2D000000000000001F3B +:104DE0000020122D00000000000000200020162DE1 +:104DF00000000000000021690020441100000000B4 +:104E00000000000000204804000000000000000036 +:104E100000204805000000000000000000204801BC +:104E200000000000CAFEBABE0020481100000000C9 +:104E30000000000400301224000000000000000008 +:104E4000002F006400000000000000000CC0000003 +:104E50000000068B0000000300281A22000000005A +:104E6000000000080022122200000000FFFFF000F6 +:104E7000002812240000000000000000002910C4D7 +:104E8000000000000000001F004036240000000069 +:104E90000000000000800000000000000000000092 +:104EA0001AC000000000068D9F0000000020441181 +:104EB00000000000CAFEBABE002048110000000039 +:104EC000000000001AE00000000006900000000052 +:104ED0000080000000000000000000001AC0000078 +:104EE000000006929E000000002044110000000017 +:104EF000CAFEBABE002048110000000000000000F9 +:104F00001AE000000000069500000000008000008C +:104F10000000000000000000006000000000000B26 +:104F200000001000006004110000031500000000E4 +:104F300000200411000000000000000000600811C3 +:104F4000000001B20000225C0020441100000000BB +:104F5000000000030020481100000000000022565D +:104F600000204411000000000000001B0020481138 +:104F7000000000000000A1FC00204411000000001F +:104F80000000000100204811000000000001A1FD08 +:104F9000C0204411000000000000002100201E2D50 +:104FA000000000000000001000221E27000000008A +:104FB000000000240020222D000000000000FFFF60 +:104FC00000282228000000000000000000294907F6 +:104FD0000000000000000000002048110000000058 +:104FE000000000220020222D000000000000FFFF32 +:104FF00000282228000000000000000000294907C6 +:105000000000000000000000002048110000000027 +:105010000000002300201E2D0000000000000010F2 +:1050200000221E27000000000000000000294907A0 +:1050300000000000000000000040481100000000D7 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B0000142050205C002500000000001C3016860 +:1052C000043F05C000000000022502090250015100 +:1052D000000000000223024502A00241000000007D +:1052E00003D705C005C005C0000000000649064AF6 +:1052F000031F05C00000000005C005C503200340D2 +:1053000000000000032A0282034203340000000070 +:1053100005C005C005C005C00000000005C005515E +:1053200005C005C00000000003BA05C004BB03446B +:1053300000000000049A0450043D05C00000000075 +:1053400004D005C0044104DD00000000045005073E +:10535000035103750000000005C005C005C005C06D +:105360000000000005C005C005C005C00000000029 +:1053700005C005C0063F05C70000000005C005C008 +:10538000000705C00000000005C005C005C005C03D +:105390000000000005C005C005C005C000000000F9 +:1053A00003F803ED0408040600000000040E040ADC +:1053B000040C041000000000041C04180424042041 +:1053C00000000000042C0428043404300000000015 +:1053D00005C005C0043805C00000000005C005C0B8 +:1053E00005C005C00000000005C005C005C005C01F +:1053F0000000000000020679069700060000000089 +:00000001FF diff --git a/firmware/radeon/RV610_pfp.bin.ihex b/firmware/radeon/RV610_pfp.bin.ihex new file mode 100644 index 000000000000..f55292c97b79 --- /dev/null +++ b/firmware/radeon/RV610_pfp.bin.ihex @@ -0,0 +1,145 @@ +:1000000000CA040000A00000007E828B007C038BED +:10001000008001B8007C038B00D4401E00EE001E5F +:1000200000CA040000A00000007E828B00C41838C3 +:1000300000CA240000CA2800009581A800C41C3A08 +:1000400000C3C00000CA080000CA0C00007C744B4A +:1000500000C200050099C00000C41C3A007C744C2A +:1000600000C0FFF000042C0400309002007D250049 +:1000700000351402007D350B00255403007CD5802B +:1000800000259C030095C00400D5001B007EDDC147 +:10009000007D9D8000D6801B00D5801B00D4401EB3 +:1000A00000D5401E00D6401E00D6801E00D4801E03 +:1000B00000D4C01E009783D300D5C01E00CA08001C +:1000C0000080001A00CA0C0000E4011E00D4001ECB +:1000D0000080000C00C4183800E4013E00D4001E6B +:1000E0000080000C00C4183800D4401E00EE001E32 +:1000F00000CA040000A00000007E828B00E4011E04 +:1001000000D4001E00D4401E00EE001E00CA0400F1 +:1001100000A00000007E828B00E4013E00D4001E9F +:1001200000D4401E00EE001E00CA040000A0000023 +:10013000007E828B00CA180000D4401E00D5801EAD +:100140000080005300D4007500D4401E00CA08008F +:1001500000CA0C0000CA100000D4801900D4C018D6 +:1001600000D5001700D4801E00D4C01E00D5001E8C +:1001700000E2001E00CA040000A00000007E828B86 +:1001800000CA080000D4806000D4401E0080000037 +:1001900000D4801E00CA080000D4806100D4401E34 +:1001A0000080000000D4801E00CA080000CA0C00B5 +:1001B00000D4401E00D4801600D4C01600D4801E87 +:1001C000008001B800D4C01E00C6084300CA0C005D +:1001D00000CA10000094800400CA140000E420F358 +:1001E00000D4201300D5606500D4E01C00D5201C8D +:1001F00000D5601C008000000006200100C60843F6 +:1002000000CA0C0000CA1000009483F700CA140052 +:1002100000E420F30080007900D4201300C60843D6 +:1002200000CA0C0000CA1000009883EF00CA140036 +:1002300000D400640080008D0000000000C414326F +:1002400000C6184300C4082F0095400500C40C30B8 +:1002500000D4401E0080000000EE001E009583F5D3 +:1002600000C4103100D4403300D5206500D4A01C58 +:1002700000D4E01C00D5201C00E4015E00D4001E68 +:10028000008000000006200100CA1800000A2001BA +:1002900000D6007600C408360098800700C61045D6 +:1002A0000095011000D4001F00D46062008000009F +:1002B00000D4206200CC383500CC1433008401BB5C +:1002C00000D4007200D5401E0080000000EE001E29 +:1002D00000E2001A008401BB00E2001A00CC104BBF +:1002E00000CC0447002C9401007D098B0098400548 +:1002F000007D15CB00D4001A008001B800D4006D39 +:100300000034440100CC0C480098403A00CC2C4A00 +:100310000095800400CC0449008001B800D4001A84 +:1003200000D4C01A00282801008400F000CC10037B +:100330000098801B0004380C008400F000CC1003EF +:100340000098801700043808008400F000CC1003E7 +:100350000098801300043804008400F000CC1003DF +:100360000098801400CC104C009A800900CC144DE9 +:10037000009840DC00D4006D00CC184800D5001A6D +:1003800000D5401A008000C900D5801A0096C0D55B +:1003900000D4006D008001B800D4006E009AC00344 +:1003A00000D4006D00D4006E0080000000EC007FDF +:1003B000009AC0CC00D4006D008001B800D4006E5B +:1003C00000CC140300CC180300CC1C03007D910367 +:1003D000007DD583007D190C0035CC1F0035701FC2 +:1003E000007CF0CB007CD08B00880000007E8E8BE0 +:1003F0000095C00400D4006E008001B800D4001A3B +:1004000000D4C01A00CC080300CC0C0300CC1003AD +:1004100000CC140300CC180300CC1C0300CC240334 +:1004200000CC28030035C41F0036B01F007C704B81 +:100430000034F01F007C704B0035701F007C704B47 +:10044000007D8881007DCCC1007E5101007E9541F8 +:10045000007C9082007CD4C2007C848B009AC00314 +:10046000007C8C8B002C88010098809E00D4006D4D +:100470000098409C00D4006E00CC084C00CC0C4D81 +:1004800000CC104800D4801A00D4C01A00800101AA +:1004900000D5001A00CC083200D40032009482D972 +:1004A00000CA0C0000D4401E0080000000D4001ED2 +:1004B00000E4011E00D4001E00CA080000CA0C009F +:1004C00000CA100000D4401E00CA140000D4801ED0 +:1004D00000D4C01E00D5001E00D5401E00D54034FB +:1004E0000080000000EE001E0028040400E2001A54 +:1004F00000E2001A00D4401A00CA380000CC0803F9 +:1005000000CC0C0300CC0C0300CC0C03009882BD83 +:1005100000000000008401BB00D7A06F0080000035 +:1005200000EE001F00CA040000C2FF0000CC083427 +:1005300000C13FFF007C74CB007CC90B007D010F24 +:10054000009902B0007C738B008401BB00D7A06FC0 +:100550000080000000EE001F00CA080000281900FB +:10056000007D898B009580140028140400CA0C00BB +:1005700000CA100000CA1C0000CA240000E2001FCC +:1005800000D4C01A00D5001A00D5401A00CC1803B8 +:1005900000CC2C0300CC2C0300CC2C03007DA58BBD +:1005A000007D9C4700984297000000000080016198 +:1005B00000D4C01A00D4401E00D4801E0080000069 +:1005C00000EE001E00E4011E00D4001E00D4401EF8 +:1005D00000EE001E00CA040000A00000007E828B16 +:1005E00000E4013E00D4001E00D4401E00EE001EB8 +:1005F00000CA040000A00000007E828B00CA080030 +:1006000000248C06000CCC060098C00600CC104ECE +:100610000099000400D4007300E4011E00D4001E01 +:1006200000D4401E00D4801E0080000000EE001E9A +:1006300000CA080000CA0C000034D01800251001C0 +:100640000095002100C17FFF00CA100000CA1400FD +:1006500000CA180000D4801D00D4C01D007DB18BDD +:1006600000C1420200C2C00100D5801D0034DC0E72 +:10067000007D5D4C007F734C00D7401E00D5001EEE +:1006800000D5401E00C1420000C2C00000099C010C +:100690000031DC10007F5F4C007F734C00042802A7 +:1006A000007D838000D5A86F00D5806600D7401EEE +:1006B00000EC005E00C8240200C82402008001B8DB +:1006C00000D6007600D4401E00D4801E00D4C01E88 +:1006D0000080000000EE001E0080000000EE001F01 +:1006E00000D4001F0080000000D4001F00D4001FB1 +:1006F0000088000000D4001F00000000000000007F +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000010171000201780003008F0004007FE5 +:10081000000500030006003F000700320008012C1D +:1008200000090046000A0036001001B6001700A2B9 +:100830000022013A00230149002000B400240125D0 +:100840000027004D0028006A002A0060002B00529B +:10085000002F0065003200870034017F003C015604 +:10086000003F00720041018C0044012E00550173CD +:100870000056017A0060000B00610034006200380D +:1008800000630038006400380065003800660038F6 +:10089000006700380068003A00690041006A0048BB +:1008A000006B0048006C0048006D0048006E004876 +:1008B000006F00480000000600000006000000066F +:1008C0000000000600000006000000060000000610 +:1008D0000000000600000006000000060000000600 +:1008E00000000006000000060000000600000006F0 +:1008F00000000006000000060000000600000006E0 +:00000001FF diff --git a/firmware/radeon/RV620_me.bin.ihex b/firmware/radeon/RV620_me.bin.ihex new file mode 100644 index 000000000000..ba19ed892920 --- /dev/null +++ b/firmware/radeon/RV620_me.bin.ihex @@ -0,0 +1,1345 @@ +:1000000000000000C020040000000000000000000C +:1000100000A0000A000000000000FFFF00284621A9 +:100020000000000000000000D900480000000000AF +:1000300000000000C02004000000000000000000DC +:1000400000A0000A000000000000000000E0000026 +:100050000000000000010000C02946200000000050 +:1000600000000000D900480000000000000000006F +:10007000C0200400000000000000000000A0000AF2 +:10008000000000008100000000204411000000007A +:1000900000000001002048110000000000042004BE +:1000A000006044110000068D0000000000600000A8 +:1000B000000006310000000000600000000006455E +:1000C00000000000C02008000000000000000F0039 +:1000D000002816220000000000000008002116255C +:1000E000000000000000001800203625000000007D +:1000F0008D000000002044110000000000000004FA +:10010000002F022500000000000000000CE00000AD +:1001100000000018004120000040481100000019B4 +:100120000042200000204811000000008E00000066 +:1001300000204411000000000000002800204A2D8B +:1001400000000000900000000020441100000000AA +:100150000000000000204805000000000000000C26 +:1001600000211622000000000000000300281625D0 +:10017000000000000000001900211A220000000009 +:100180000000000400281A26000000000000000003 +:10019000002914C5000000000000001900203625C9 +:1001A0000000000000000000003A140200000000FF +:1001B00000000016002116250000000000000003CA +:1001C00000281625000000000000001700200E2D5A +:1001D00000000000FFFFFFFC00280E2300000000CD +:1001E00000000000002914A3000000000000001718 +:1001F00000203625000000000000800000280E22AC +:10020000000000000000000700220E230000000094 +:10021000000000000029386E0000000020000000EF +:1002200000280E22000000000000000600210E231E +:1002300000000000000000000029386E00000000EF +:100240000000000000220222000000000000000068 +:1002500014E0000000000038000000002EE0000064 +:1002600000000035000000002CE000000000003716 +:100270000000000000400E2D0000003900000008C2 +:1002800000200E2D00000000000000090040122D8B +:10029000000000460000000100400E2D0000003963 +:1002A00000000000C0200C0000000000003FFFFC28 +:1002B0000028122300000000000000020022122487 +:1002C000000000000000001F00211E2300000000AD +:1002D0000000000014E000000000003E00000008E4 +:1002E00000401C11000000410000000D00201E2DE8 +:1002F000000000000000000F00281E270000000082 +:100300000000000300221E27000000007FC0000044 +:1003100000281A23000000000000001400211A2603 +:10032000000000000000000100331A260000000059 +:100330000000000800221A26000000000000000053 +:1003400000290CC700000000000000270020362410 +:100350000000000000007F000028122100000000C3 +:1003600000001400002F0224000000000000000024 +:100370000CE000000000004B0000000100290E23EB +:10038000000000000000000E0020362300000000E6 +:100390000000E0000020441100000000FFF8000011 +:1003A00000294A230000000000000000003A2C024F +:1003B000000000000000000200220E2B00000000E0 +:1003C000FC00000000280E23000000000000000FC9 +:1003D000002036230000000000001FFF00294A23F0 +:1003E000000000000000002700204A2D000000004F +:1003F000000000000020481100000000000000295B +:1004000000200E2D00000000060A020000294A23E9 +:100410000000000000000000002048110000000063 +:100420000000000000204811000000000000000152 +:1004300000210222000000000000000014E0000083 +:1004400000000061000000002EE000000000005FDE +:10045000000000002CE000000000005E0000000032 +:1004600000400E2D000000620000000100400E2D33 +:10047000000000620000000A00200E2D00000000B5 +:100480000000000B0040122D0000006A0000000078 +:10049000C0200C0000000000003FFFFC00281223D9 +:1004A00000000000000000020022122400000000F2 +:1004B0007FC0000000281623000000000000001488 +:1004C0000021162500000000000000010033162561 +:1004D000000000008000000000280E230000000043 +:1004E0000000000000290CA3000000003FFFFC00FA +:1004F00000290E23000000000000001F00211E2321 +:10050000000000000000000014E000000000006D8A +:100510000000010000401C11000000700000000DF0 +:1005200000201E2D00000000000000F000281E2703 +:10053000000000000000000400221E270000000050 +:100540008100000000204411000000000000000DA8 +:100550000020481100000000FFFFF0FF00281A30C3 +:10056000000000000000A02800204411000000004E +:1005700000000000002948E6000000000000A0186C +:1005800000204411000000003FFFFFFF00284A2325 +:10059000000000000000A010002044110000000036 +:1005A00000000000002048040000000000000030AF +:1005B0000020162D00000000000000020029162572 +:1005C0000000000000000030002036250000000080 +:1005D000000000250020162D000000000000000093 +:1005E000002F00A300000000000000000CC000006D +:1005F00000000083000000260020162D00000000EF +:1006000000000000002F00A4000000000000000017 +:100610000CC000000000008400000000004000004A +:100620000000008A000000250020362300000000A2 +:100630000000002600203624000000000000001703 +:1006400000201E2D000000000000000200210227F3 +:10065000000000000000000014E000000000008A1C +:1006600000000000006000000000066800000000BC +:10067000006000000000065C0000000200210E2265 +:10068000000000000000000014C000000000008D09 +:1006900000000012C040362000000093000000005F +:1006A0002EE0000000000091000000002CE000009F +:1006B000000000900000000200400E2D000000929B +:1006C0000000000300400E2D000000920000000C0E +:1006D00000200E2D00000000000000120020362334 +:1006E000000000000000000300210E2200000000B6 +:1006F0000000000014C00000000000980000A00CE2 +:10070000002044110000000000000000C02048004C +:100710000000000000000000C0404800000000A0F1 +:100720000000A00C002044110000000000000000A8 +:100730000020481100000000000000002EE0000032 +:100740000000009E000000002CE000000000009D62 +:100750000000000200400E2D0000009F000000037A +:1007600000400E2D0000009F0000000C00200E2D08 +:10077000000000000000000000204803000000000E +:1007800000000000003A0C0200000000003F0000E2 +:1007900000280E23000000000000001000210E239E +:1007A00000000000000000110020362300000000BF +:1007B0000000001E0021022B0000000000000000CD +:1007C00014C00000000000A700000016C020362062 +:1007D000000000000000001F0021022B00000000AC +:1007E0000000000014C00000000000AA0000001576 +:1007F000C0203620000000000000000800210E2B61 +:10080000000000000000007F00280E230000000010 +:1008100000000000002F0223000000000000000084 +:100820000CE00000000000E10000000027000000D4 +:10083000000000000000000000600000000002A3B3 +:1008400000000001002F0223000000000000000053 +:100850000AE00000000000B300000000006000009B +:100860000000013A81000000002044110000000057 +:100870000000000600204811000000000000000CED +:1008800000221E300000000099800000002044116A +:1008900000000000000000040020122D00000000F5 +:1008A00000000008002212240000000000000010D8 +:1008B00000201811000000000000000000291CE4C6 +:1008C0000000000000000000006048070000012F49 +:1008D0009B00000000204411000000000000000008 +:1008E00000204802000000009C000000002044118D +:1008F00000000000000000000033146F0000000042 +:100900000000000100333E23000000000000000052 +:10091000D9004800000000000000000000203C0555 +:1009200000000000810000000020441100000000D1 +:100930000000000E00204811000000000000000030 +:1009400000201010000000000000E007002044110B +:10095000000000000000000F0021022B000000003A +:100960000000000014C00000000000CB00F8FF08E9 +:1009700000204811000000009800000000404811CD +:10098000000000DC000000F000280E220000000043 +:10099000000000A0002F0223000000000000000063 +:1009A0000CC00000000000DA0000001100200E2D35 +:1009B0000000000000000001002F022300000000E2 +:1009C000000000000CE00000000000D50000000264 +:1009D000002F022300000000000000000CE00000D7 +:1009E000000000D400003F0000400C11000000D6C1 +:1009F00000001F0000400C11000000D600000F0096 +:100A000000200C11000000000038000900294A23D2 +:100A1000000000003F00000000280E2B0000000036 +:100A20000000000200220E2300000000000000076A +:100A300000494A23000000DC00380F09002048115B +:100A400000000000680000070020481100000000BE +:100A50000000000800214A270000000000000000FC +:100A60000020481100000000060A020000294A2464 +:100A700000000000000000000020481100000000FD +:100A80000000000000204811000000000000A20249 +:100A9000002044110000000000FF000000280E228A +:100AA000000000000000008000294A230000000030 +:100AB0000000002700200E2D00000000000000268E +:100AC0000020122D0000000000000000002F008315 +:100AD00000000000000000000CE00000000000EA40 +:100AE000000000000060000000000662000000003E +:100AF00000400000000000EB00000000006000006B +:100B000000000665000000070020222D0000000004 +:100B10000000000500220E2200000000001000006E +:100B200000280E23000000000000000000292068BB +:100B30000000000000000000003A0C02000000006D +:100B4000000000EF00280E2300000000000000005D +:100B500000292068000000000000001700200E2D72 +:100B6000000000000000000300210223000000003C +:100B70000000000014E00000000000F80000000B7E +:100B800000210228000000000000000014C0000046 +:100B9000000000F8000004000029222800000000E6 +:100BA0000000001400203628000000000000001C97 +:100BB00000210E22000000000000000014C0000010 +:100BC000000000FD0000A30C002044110000000004 +:100BD0000000000000204811000000000000001E7E +:100BE00000210E22000000000000000014C00000E0 +:100BF0000000010B0000A30F0020441100000000C2 +:100C00000000001100200E2D000000000000000177 +:100C1000002F022300000000000000000CC00000B4 +:100C200000000104FFFFFFFF004048110000010B1E +:100C300000000002002F022300000000000000005E +:100C40000CC00000000001070000FFFF0040481139 +:100C50000000010B00000004002F02230000000030 +:100C6000000000000CC000000000010A000000FFAE +:100C7000004048110000010B000000010020481155 +:100C8000000000000002C400002044110000000029 +:100C90000000001F00210E220000000000000000E4 +:100CA00014C00000000001120000001040210E20BE +:100CB00000000000000000130020362300000000A8 +:100CC0000000001840224A20000000000000001030 +:100CD000C0424A20000001140000000000200C1156 +:100CE0000000000000000013002036230000000078 +:100CF000000000000020481100000000000000007B +:100D000000204811000000000000000A002010111F +:100D10000000000000000000002F0224000000007E +:100D2000000000000CE000000000011B00000000BB +:100D300000204811000000000000000100531224B0 +:100D400000000117FFBFFFFF00283A2E000000003F +:100D50000000001B00210222000000000000000033 +:100D600014C000000000012E81000000002044118A +:100D7000000000000000000D0020481100000000ED +:100D80000000001800220E3000000000FC000000EF +:100D900000280E2300000000810000000020441104 +:100DA000000000000000000E0020481100000000BC +:100DB0000000000000201010000000000000E00E05 +:100DC000002044110000000007F8FF08002048112F +:100DD000000000000000000000294A23000000007D +:100DE0000000001C00201E2D000000000000000874 +:100DF00000214A27000000000000000000204811E8 +:100E000000000000060A020000294A240000000039 +:100E10000000000000204811000000000000000059 +:100E200000204811000000000000000000800000C9 +:100E300000000000810000000020441100000000BC +:100E40000000000100204811000000000000217C8B +:100E50000020441100000000008000000020481124 +:100E60000000000000000000002048060000000014 +:100E70000000000800214A270000000000000000D8 +:100E800017000000000000000004217F00604411F2 +:100E90000000068D0000001F00210230000000004D +:100EA0000000000014C000000000068C00000004D8 +:100EB00000404C1100000135810000000020441169 +:100EC00000000000000000010020481100000000A8 +:100ED000000021F800204411000000000000001C68 +:100EE0000020481100000000000421F900604411B6 +:100EF0000000068D000000110021023000000000FB +:100F00000000000014E000000000013C00000000B0 +:100F100000800000000000000000000000600000F1 +:100F20000000000B00000000006004110000031529 +:100F3000000000000020041100000000000000007C +:100F400000600811000001B2000000000060000015 +:100F5000000001600000FFFF40280E20000000009C +:100F600000000010C0211220000000000000FFFF60 +:100F7000402806200000000000000010C0210A20C8 +:100F800000000000000000000034146100000000B8 +:100F90000000000000741882000002BB0001A1FDE7 +:100FA00000604411000002E000003FFF002F022F0C +:100FB00000000000000000000CC00000000001471D +:100FC00000000000C040040000000001000000001C +:100FD000006000000000000B000000000060041131 +:100FE00000000315000000000020041100000000B4 +:100FF0000000000000600811000001B200003FFF87 +:10100000002F022F00000000000000000CE0000094 +:10101000000000000000000000600000000001600F +:101020000000001040210E20000000000000FFFF23 +:10103000C0281220000000000000001040211620EF +:10104000000000000000FFFFC0681A20000002BB83 +:101050000001A1FD00604411000002E000003FFF1C +:10106000002F022F00000000000000000CC0000054 +:101070000000015800000000C04004000000000112 +:101080000000225C0020441100000000000000016C +:1010900000300A2F000000000000000100210A2299 +:1010A000000000000000000300384A220000000099 +:1010B0000000225600204411000000000000001A29 +:1010C00000204811000000000000A1FC0020441195 +:1010D0000000000000000001008048110000000036 +:1010E00000000000006000000000000B0000000095 +:1010F000006000000000018F0000000000600000A0 +:10110000000001A000003FFF002F022F00000000A0 +:10111000000000000CE000000000000000000000E3 +:1011200000202C0800000000000000000020241116 +:101130000000000000000000002028110000000056 +:10114000000022560020441100000000000000169C +:1011500000204811000000000000225C0020441123 +:101160000000000000000003002048110000000003 +:1011700093800000002044110000000000000002E5 +:1011800000221E290000000000000000007048EB53 +:101190000000019C0000000000600000000002BB95 +:1011A00000000001403306200000000000000000A5 +:1011B000C03024090000000000003FFF002F022F74 +:1011C00000000000000000000CE000000000000033 +:1011D0000000000000600000000002A3000000000A +:1011E000002F022100000000000000000AE00000C3 +:1011F0000000018100000000006000000000013AD2 +:101200000000000000400000000001869500000082 +:10121000002044110000000000000000002F022107 +:1012200000000000000000000CE00000000001864B +:1012300000000000C0204800000000000000000185 +:10124000005306210000018292000000002044119A +:101250000000000000000000C0604800000001978E +:101260000001A1FD00204411000000000000001159 +:101270000020062D00000000000000000078042A75 +:10128000000002FB00000000002028090000000010 +:1012900000003FFF002F022F0000000000000000B0 +:1012A0000CC000000000017400000000C0400400F9 +:1012B000000000010000021000600411000003158E +:1012C00000003FFF002F022F000000000000000080 +:1012D0000CE000000000019400000015C020362042 +:1012E0000000000000000016C020362000000000B2 +:1012F0003F800000002004110000000046000000B4 +:1013000000600811000001B2000000000080000031 +:10131000000000000000A1FC0020441100000000BB +:1013200000003FFF002F022F00000000000000001F +:101330000CC000000000019B00000001008048116B +:1013400000000000000000210080481100000000A3 +:101350000000FFFF40280E200000000000000010E9 +:10136000C0211220000000000000FFFF40281620CE +:101370000000000000000010C0811A2000000000E2 +:101380008100000000204411000000000000000661 +:1013900000204811000000000000000800221E305C +:1013A000000000000000002900201A2D00000000AD +:1013B0000000E0000020441100000000FFFBFF09D6 +:1013C00000204811000000000000000F0020222D26 +:1013D0000000000000001FFF00294A280000000054 +:1013E000000000060020222D000000000000000088 +:1013F000002920E80000000000000000002048084C +:101400000000000000000000002048110000000063 +:10141000060A020000294A26000000000000000021 +:1014200000204811000000000000000000204811CA +:101430000000000000000100002018110000000062 +:101440000000000800621E280000012F00000008B4 +:1014500000822228000000000002C0000020441189 +:10146000000000000000001500600E2D000001BD0E +:101470000000001600600E2D000001BD0000C00835 +:1014800000204411000000000000001700200E2D75 +:10149000000000000000000014C00000000001B9BE +:1014A0000000000000200411000000000000000007 +:1014B0000020480100000000390000000020481111 +:1014C00000000000000000000020481100000000A3 +:1014D000000000000080480200000000000000182A +:1014E00000202E2D0000000000000000003B0D63D6 +:1014F000000000000000000800224A230000000055 +:101500000000001000224A23000000000000001824 +:1015100000224A2300000000000000000080480371 +:101520000000000000000000006000000000000B50 +:10153000000010000060041100000315000000000E +:1015400000200411000000000000000000600811ED +:10155000000001B2000000070021062F000000007B +:101560000000001300200A2D000000000000000110 +:1015700000202C11000000000000FFFF4028222066 +:10158000000000000000000F0026222800000000DC +:101590000000001040212620000000000000000F85 +:1015A000002626290000000000000000002028027C +:1015B000000000000000225600204411000000003E +:1015C0000000001B00204811000000000000000087 +:1015D000002F022100000000000000000CE00000CD +:1015E000000001E00000225C002044110000000027 +:1015F0000000008100204811000000000000A1FC54 +:1016000000204411000000000000000100204811EB +:10161000000000000000008000201C1100000000FD +:1016200000000000002F0227000000000000000062 +:101630000CE00000000001DC000000000060000081 +:10164000000001E90000000100531E27000001D83E +:101650000000000100202C11000000000000001F0D +:1016600000280A22000000000000001F00282A2A8B +:10167000000000000000000100530621000001D11D +:101680000000225C00204411000000000000000265 +:1016900000304A2F000000000000A1FC002044118F +:1016A00000000000000000010020481100000000C0 +:1016B0000000000100301E2F0000000000000000AC +:1016C000002F022700000000000000000CE00000D6 +:1016D000000000000000000000600000000001E9C0 +:1016E0000000000100531E27000001E50000FFFF7D +:1016F00040280E20000000000000000F00260E23EE +:101700000000000000000010C021122000000000B6 +:101710000000000F0026122400000000000000005E +:1017200000201411000000000000000000601811EB +:10173000000002BB0001A1FD0020441100000000D8 +:1017400000000000002F022B00000000000000003D +:101750000CE00000000001F8000000100022162834 +:1017600000000000FFFF0000002816250000000018 +:101770000000FFFF00281A29000000000000000000 +:10178000002948C500000000000000000020480AB1 +:10179000000000000000000000202C1100000000EC +:1017A000000000100022162300000000FFFF0000D0 +:1017B00000281625000000000000FFFF00281A2462 +:1017C0000000000000000000002948C500000000E3 +:1017D0000000000000731503000002050000000077 +:1017E0000020180500000000000000000073152410 +:1017F0000000020500000000002D14C500000000DC +:1018000000000000003008A20000000000000000FE +:101810000020480200000000000000000020280214 +:101820000000000000000000002020030000000075 +:101830000000000000802404000000000000000FF1 +:1018400000210225000000000000000014C000007C +:101850000000068C00000000002B140500000000B2 +:1018600000000001009016250000000000000000AC +:10187000006000000000000B000000000060041188 +:10188000000003150000000000200411000000000B +:101890000000000000600811000001B200002256A4 +:1018A00000204411000000000000001A00294A2214 +:1018B0000000000000000000C02000000000000048 +:1018C00000003FFF002F022F00000000000000007A +:1018D0000CE000000000000000000000C020040038 +:1018E000000000000000225C002044110000000005 +:1018F0000000000300384A21000000000000A1FCA5 +:1019000000204411000000000000000100204811E8 +:10191000000000000000FFFF40281220000000002F +:1019200000000010C0211A20000000000000FFFF8E +:1019300040280E200000000000000010C0211620EA +:10194000000000000000000000741465000002BBED +:101950000001A1FD00604411000002E00000000150 +:10196000003306210000000000000000002F0221CB +:1019700000000000000000000CC000000000021980 +:1019800000003FFF002F022F0000000000000000B9 +:101990000CC000000000021200000000C040040063 +:1019A000000000010000000000600000000006458B +:1019B000000000000040040F0000021300000000BF +:1019C0000060000000000631000000000060000020 +:1019D000000006450000021000600411000003151D +:1019E0000000000000600000000001A000000000F6 +:1019F000006000000000019C00000000006000008A +:101A0000000002BB0000000000600000000002A314 +:101A1000938000000020441100000000000000003E +:101A2000002048080000000000000000002F022FE6 +:101A300000000000000000000AE000000000023288 +:101A400000000000006000000000013A00000000FB +:101A50000040000000000236950000000020441104 +:101A60000000000000000000002F022F0000000016 +:101A7000000000000CE00000000002360000000042 +:101A8000C0404800000002339200000000204411D2 +:101A90000000000000000000C0204800000000001E +:101AA0000000225600204411000000000000001633 +:101AB00000204811000000000000225C00204411BA +:101AC000000000000000000300204811000000009A +:101AD0000000A1FC002044110000000000000001F3 +:101AE00000204811000000000001A1FD0020441169 +:101AF000000000000000000000600411000002FB74 +:101B000000000000C04004000000000100000000D0 +:101B100000600000000006310000A00C002044110D +:101B20000000000000000000C0204800000000008D +:101B300000000000C040480000000000000000005D +:101B4000006000000000000B0000001840210A2087 +:101B50000000000000000003002F0222000000002F +:101B6000000000000AE000000000024C0000001429 +:101B70000020222D00000000000801010029222879 +:101B800000000000000000140020362800000000C3 +:101B90000000A30C00204411000000000000000021 +:101BA000C02048000000000000000000C0204800E5 +:101BB0000000000000000000C0404800000002518A +:101BC00000000000006000000000000B000000109A +:101BD00000600411000003153F8000000020041184 +:101BE000000000000000000000600811000001B2C9 +:101BF0000000225C002044110000000000000003EF +:101C000000204811000000000000000000600000FB +:101C10000000027C0000001700201E2D00000000C4 +:101C20000000000100211E2700000000000000004D +:101C300014E000000000026A0000001200201E2DC7 +:101C4000000000000000FFFF00281E270000000029 +:101C50000000000000341C2700000000000000000D +:101C600012C000000000025F0000000000201C11F4 +:101C70000000000000000000002F00E50000000050 +:101C80000000000008C00000000002620000000028 +:101C900000201407000000000000001200201E2D8C +:101CA000000000000000001000211E2700000000BE +:101CB0000000000000341C4700000000000000008D +:101CC00012C00000000002670000000000201C118C +:101CD0000000000000000000002F00E600000000EF +:101CE0000000000008C000000000026A00000000C0 +:101CF0000020180700000000000000000060000045 +:101D0000000002C100002256002044110000000023 +:101D1000000000000034202300000000000000004C +:101D200012C00000000002720000000000342044D5 +:101D3000000000000000000012C00000000002715E +:101D40000000001600404811000002760000001854 +:101D500000404811000002760000000000342044DA +:101D6000000000000000000012C00000000002752A +:101D70000000001700404811000002760000001922 +:101D800000204811000000000000A1FC00204411C8 +:101D900000000000000000010020481100000000C9 +:101DA0000001A1FD00604411000002E900003FFFB6 +:101DB000002F022F00000000000000000CC00000F7 +:101DC0000000025600000000C040040000000001B6 +:101DD0000000001040210620000000000000FFFF6E +:101DE000C0280A20000000000000001040210E2042 +:101DF000000000000000FFFFC028122000000000CB +:101E00000000001040211620000000000000FFFF2D +:101E1000C0881A200000000081000000002044114A +:101E20000000000000000001002048110000000038 +:101E300000042004006044110000068D0000000032 +:101E4000006000000000063100000000C0600000DB +:101E5000000002A30000000500200A2D0000000081 +:101E60000000000800220A22000000000000002BF1 +:101E700000201A2D000000000000001C00201E2D74 +:101E8000000000000000700000281E270000000075 +:101E90000000000000311CE6000000000000002AE5 +:101EA00000201A2D000000000000000C00221A265D +:101EB0000000000000000000002F00E6000000000D +:101EC0000000000006E00000000002920000000098 +:101ED00000201C11000000000000000000200C1178 +:101EE000000000000000002B00203623000000004E +:101EF0000000001000201811000000000000000089 +:101F000000691CE20000012F9380000000204411B2 +:101F10000000000000000000002048070000000052 +:101F200095000000002044110000000000000000A7 +:101F3000002F022F00000000000000000CE0000055 +:101F40000000029D0000000100333E2F0000000051 +:101F500000000000D90048000000000092000000CE +:101F6000002044110000000000000000C0204800D4 +:101F7000000000000000001C0040362700000000A8 +:101F80000000000CC0220A20000000000000002910 +:101F9000002036220000000000000028C04036204B +:101FA000000000000000A2A4002044110000000076 +:101FB000000000090020481100000000A1000000FE +:101FC00000204411000000000000000100804811C2 +:101FD000000000000000002100201E2D0000000075 +:101FE00000000000002C1CE30000000000000021A5 +:101FF00000203627000000000000002200201E2DD7 +:102000000000000000000000002C1CE400000000A4 +:1020100000000022002036270000000000000023FE +:1020200000201E2D0000000000000000003120A351 +:102030000000000000000000002D1D07000000004F +:1020400000000023002036270000000000000024CC +:1020500000201E2D0000000000000000003120C400 +:102060000000000000000000002D1D07000000001F +:10207000000000240080362700000000000000213E +:10208000002036230000000000000022002036243B +:10209000000000000000000000311CA30000000050 +:1020A0000000002300203627000000000000000090 +:1020B00000311CC40000000000000024008036270E +:1020C000000000000000001A002036270000000079 +:1020D0000000001B00203628000000000000001750 +:1020E00000201E2D00000000000000020021022739 +:1020F000000000000000000014C00000000002DC2E +:102100000000000000400000000002D90000001A9A +:1021100000203627000000000000001B00203628A9 +:10212000000000000000001700201E2D000000002D +:102130000000000200210227000000000000000053 +:1021400014E00000000002D9000000030021022773 +:10215000000000000000000014E00000000002DCAD +:102160000000002300201E2D0000000000000000E1 +:10217000002E00E1000000000000000002C000008E +:10218000000002DC0000002100201E2D00000000E5 +:1021900000000000003120A100000000000000004D +:1021A000002E00E8000000000000000006C0000053 +:1021B000000002DC0000002400201E2D00000000B2 +:1021C00000000000002E00E20000000000000000FF +:1021D00002C00000000002DC0000002200201E2DD2 +:1021E0000000000000000000003120C200000000DC +:1021F00000000000002E00E80000000000000000C9 +:1022000006C00000000002DC0000000000600000CA +:10221000000006680000000000600000000002B539 +:102220000000000000400000000002DE000000008E +:1022300000600000000002B5000000000060000027 +:102240000000065F0000000000400000000002DE09 +:102250000000000000600000000002A70000000075 +:1022600000400000000002DE0000001A00201E2DC9 +:10227000000000000000001B0080222D0000000074 +:102280000000001000221E230000000000000000DB +:1022900000294887000000000000000000311CA356 +:1022A000000000000000001000221E2700000000B7 +:1022B0000000000000294887000000000000001016 +:1022C00000221E230000000000000000003120C496 +:1022D000000000000000FFFF00282228000000008E +:1022E0000000000000894907000000000000001005 +:1022F00000221E2300000000000000000029488783 +:10230000000000000000001000221E21000000005C +:102310000000000000294847000000000000000005 +:1023200000311CA3000000000000001000221E2746 +:1023300000000000000000000029488700000000A5 +:102340000000000000311CA100000000000000108F +:1023500000221E270000000000000000002948475E +:10236000000000000000001000221E2300000000FA +:1023700000000000003120C4000000000000FFFF4A +:102380000028222800000000000000000029490762 +:10239000000000000000001000221E2100000000CC +:1023A00000000000003120C2000000000000FFFF1C +:1023B00000282228000000000000000000894907D2 +:1023C000000000000000001000221E23000000009A +:1023D0000000000000294887000000000000000104 +:1023E00000220A210000000000000000003308A2C3 +:1023F000000000000000001000221E22000000006B +:102400000000001000212222000000000000000057 +:1024100000294907000000000000000000311CA353 +:10242000000000000000001000221E270000000035 +:1024300000000000002948870000000000000001A3 +:1024400000220A210000000000000000003008A265 +:10245000000000000000001000221E22000000000A +:1024600000000010002122220000000000000000F7 +:1024700000294907000000000000001000221E2370 +:102480000000000000000000003120C40000000037 +:102490000000FFFF002822280000000000000000CC +:1024A000002949070000000000000000003808C5AE +:1024B00000000000000000000030084100000000A3 +:1024C0000000000100220A220000000000000000BD +:1024D000003308A2000000000000001000221E22AD +:1024E0000000000000000010002122220000000077 +:1024F00000000000008949070000000000000017EC +:102500000020222D000000000000000014C0000088 +:1025100000000318FFFFFFEF002806210000000065 +:10252000000000140020222D000000000000F8E050 +:1025300000204411000000000000000000294901B3 +:1025400000000000000000000089490100000000B8 +:102550000000000000204811000000000000000002 +:102560000020481100000000060A02000080481107 +:102570000000000000000000C0200000000000007B +:1025800097000000C020441100000000000000007F +:10259000C0204811000000008A0000000020441103 +:1025A00000000000000000000020481100000000B2 +:1025B0000000225C00204411000000000000000028 +:1025C000C0204800000000000000A1FC00204411D1 +:1025D0000000000000000000C020480000000000D3 +:1025E00000000000C0200400000000000000000007 +:1025F00000A0000A00000000970000000020441125 +:102600000000000000000000002048110000000051 +:102610008A000000002044110000000000000000BB +:1026200000204811000000000000225C002044113E +:102630000000000000000000C02048000000000072 +:102640000000A1FC00204411000000000000000078 +:10265000C02048000000000000000000C02004006E +:10266000000000000000000000A0000A00000000C0 +:10267000970000000020441100000000000000004E +:1026800000204811000000008A00000000204411D2 +:1026900000000000000000000020481100000000C1 +:1026A0000000225C00204411000000000000000037 +:1026B000C0204800000000000000A1FC00204411E0 +:1026C0000000000000000000C020480000000000E2 +:1026D0000001A1FD002044110000000000000000E6 +:1026E000D90048000000000000000000C0200400E5 +:1026F000000000000000000000A0000A0000000030 +:1027000000002257002044110000000000000003D8 +:10271000C0484A20000000000000225D0020441153 +:102720000000000000000000C04048000000000061 +:1027300000000000006000000000064500000000EE +:10274000C0200800000000000000225C00204411AE +:10275000000000000000000300384A2200000000D2 +:102760000000A1FC00204411000000000000000057 +:10277000C0204800000000000001A1FD002044111D +:102780000000000000000000002F022200000000F6 +:10279000000000000CE0000000000000000000004D +:1027A00040204800000000000000000140304A20A6 +:1027B0000000000000000002C0304A2000000000BD +:1027C0000000000100530A220000034B0000003FFC +:1027D000C0280A20000000008100000000204411F1 +:1027E000000000000000000100204811000000006F +:1027F000000021F800204411000000000000001833 +:102800000020481100000000000421F9006044117C +:102810000000068D000000110021023000000000C1 +:102820000000000014E00000000003540000001449 +:10283000002F022200000000000000000CC0000079 +:10284000000003640000201000204411000000007C +:102850000000800000204811000000000001A2A438 +:102860000020441100000000000000000060480249 +:102870000000036E00002100002044110000000051 +:1028800000000000C0204800000000000000000020 +:10289000C02048000000000000000000C0204800E8 +:1028A0000000000000000000C040480000000000E0 +:1028B00000000004002F02220000000000000000C1 +:1028C0000CC000000000036A00002010002044112A +:1028D00000000000000080000020481100000000FF +:1028E0000001A2A40020441100000000000000002C +:1028F000004048020000035F00000028002F022271 +:1029000000000000000000000CC00000000005C036 +:102910000001A2A4002044110000000000000000FB +:10292000004048020000035F0000002C0020362613 +:102930000000000000000049002018110000000005 +:102940000000003F002048110000000000000001CE +:1029500000331A260000000000000000002F0226AD +:1029600000000000000000000CC000000000037028 +:102970000000002C00801A2D000000000000003F25 +:10298000C0280A200000000000000015002F0222CD +:1029900000000000000000000CE0000000000386C2 +:1029A00000000006002F02220000000000000000CE +:1029B0000CE00000000003B100000016002F02220E +:1029C00000000000000000000CE00000000003B563 +:1029D00000000020002F0222000000000000000084 +:1029E0000CE000000000039C0000000F002F0222FA +:1029F00000000000000000000CE00000000003A840 +:102A000000000010002F0222000000000000000063 +:102A10000CE00000000003A80000001E002F0222AE +:102A200000000000000000000CE000000000039027 +:102A30000000A2A4002044110000000000000000DB +:102A400000404802000000000800000000290A229F +:102A5000000000000000000340210E2000000000E4 +:102A60000000000CC021122000000000000800003F +:102A7000002812240000000000000014C0221620CC +:102A80000000000000000000002914A40000000065 +:102A90000000A2A40020441100000000000000007B +:102AA000002948A2000000000000A1FE00204411FF +:102AB000000000000000000000404803000000008B +:102AC000810000000020441100000000000000010F +:102AD0000020481100000000000021F800204411EF +:102AE0000000000000000016002048110000000057 +:102AF000000421F9006044110000068D000000155B +:102B000000210230000000000000000014E000007E +:102B1000000003920000210E00204411000000007C +:102B200000000000C020480000000000000000007D +:102B3000C0204800000000000000A2A400204411B2 +:102B400000000000000000000040480200000000FB +:102B5000810000000020441100000000000000017E +:102B60000020481100000000000021F8002044115E +:102B700000000000000000170020481100000000C5 +:102B8000000421F9006044110000068D00000003DC +:102B900000210230000000000000000014E00000EE +:102BA0000000039E000021080020441100000000E6 +:102BB00000000000C02048000000000000000000ED +:102BC000C0204800000000000000A2A40020441122 +:102BD000000000000000000000404802000000006B +:102BE0000000A2A40020441100000000000000002A +:102BF0000020480200000000800000000020441176 +:102C0000000000000000000000204811000000004B +:102C100081000000002044110000000000000010AE +:102C200000204811000000000000000000200010FB +:102C3000000000000000000014C00000000003AE0F +:102C40000000000000400000000000000000201014 +:102C50000020441100000000000080000020481106 +:102C6000000000000001A2A40020441100000000A8 +:102C70000000000600404811000000000000201085 +:102C800000204411000000000000800000204811D6 +:102C9000000000000001A2A4002044110000000078 +:102CA00000000016006048110000036E00000000E4 +:102CB000004000000000000000000000C0200800EC +:102CC0000000000000000000C0200C000000000018 +:102CD0000000001D00210223000000000000000091 +:102CE00014E00000000003CE810000000020441129 +:102CF000000000000000000100204811000000005A +:102D0000000021F80020441100000000000000181D +:102D10000020481100000000000421F90060441167 +:102D20000000068D000000110021023000000000AC +:102D30000000000014E00000000003C000002100BB +:102D400000204411000000000000000000204802A4 +:102D50000000000000000000002048030000000008 +:102D6000BABECAFE0020481100000000CAFEBABE6A +:102D70000020481100000000000020100020441135 +:102D8000000000000000800000204811000000004A +:102D90000000A2A400204411000000000000000474 +:102DA0000040481100000000000021700020441184 +:102DB00000000000000000000020480200000000A9 +:102DC0000000000000204803000000008100000017 +:102DD00000204411000000000000000A00204811FB +:102DE00000000000000000000020001000000000B3 +:102DF0000000000014C00000000003D38C0000009D +:102E00000020441100000000CAFEBABE0040481174 +:102E100000000000810000000020441100000000BC +:102E200000000001002048110000000000003FFFEA +:102E300040280A20000000008000000040280E20EA +:102E40000000000040000000C02812200000000028 +:102E500000040000006946220000068D000000000A +:102E6000002014100000000000000000002F0223CA +:102E700000000000000000000CC00000000003E1A2 +:102E800000000000C0401800000003E400003FFF05 +:102E9000C0281A2000000000000400000069462637 +:102EA0000000068D00000000002018100000000047 +:102EB00000000000002F02240000000000000000BD +:102EC0000CC00000000003E700000000C0401C0030 +:102ED000000003EA00003FFFC0281E2000000000A1 +:102EE00000040000006946270000068D0000000075 +:102EF00000201C1000000000000000000020440220 +:102F00000000000000000000002820C500000000B4 +:102F100000000000004948E800000000A580000013 +:102F200000200811000000000000200000200C110B +:102F30000000000083000000006044110000041243 +:102F4000000000000020440200000000000000001B +:102F5000C0204800000000000000000040204800A1 +:102F6000000000000000001FC0210220000000003F +:102F70000000000014C00000000003F70000201053 +:102F800000204411000000000000800000204811D3 +:102F9000000000000000FFFFC0481220000003FFF7 +:102FA000A780000000200811000000000000A00021 +:102FB00000200C110000000083000000006044119C +:102FC0000000041200000000002044020000000085 +:102FD00000000000C02048000000000000000000C9 +:102FE000C0204800000000000000FFFFC0281220A1 +:102FF00000000000830000000020441100000000D9 +:103000000000000000304883000000008400000041 +:10301000002044110000000000000000C020480013 +:1030200000000000000000001D0000000000000083 +:103030008300000000604411000004120000000042 +:10304000C040040000000001A98000000020081119 +:10305000000000000000C00000400C11000003FA56 +:10306000AB80000000200811000000000000F8E024 +:1030700000400C11000003FAAD8000000020081190 +:10308000000000000000F88000400C11000003FA6E +:10309000B380000000200811000000000000F3FCD5 +:1030A00000400C11000003FAAF800000002008115E +:1030B000000000000000E00000400C11000003FAD6 +:1030C000B180000000200811000000000000F000A6 +:1030D00000400C11000003FA83000000002044119E +:1030E00000000000000021480020481100000000FE +:1030F00084000000002044110000000000000000D7 +:10310000C020480000000000000000001D0000007A +:10311000000000000000000000800000000000002F +:1031200001182000C0304620000000000000000010 +:10313000D90048000000000000000000C02004008A +:10314000000000000000000000A0000A00000000D5 +:103150000218A000C030462000000000000000005F +:10316000D90048000000000000000000C02004005A +:10317000000000000000000000A0000A00000000A5 +:103180000318C000C030462000000000000000000E +:10319000D90048000000000000000000C02004002A +:1031A000000000000000000000A0000A0000000075 +:1031B0000418F8E0C03046200000000000000000C5 +:1031C000D90048000000000000000000C0200400FA +:1031D000000000000000000000A0000A0000000045 +:1031E0000518F880C03046200000000000000000F4 +:1031F000D90048000000000000000000C0200400CA +:10320000000000000000000000A0000A0000000014 +:103210000618E000C030462000000000000000005A +:10322000D90048000000000000000000C020040099 +:10323000000000000000000000A0000A00000000E4 +:103240000718F000C0304620000000000000000019 +:10325000D90048000000000000000000C020040069 +:10326000000000000000000000A0000A00000000B4 +:103270000818F3FCC03046200000000000000000E9 +:10328000D90048000000000000000000C020040039 +:10329000000000000000000000A0000A0000000084 +:1032A0000000003000200A2D000000000000000097 +:1032B000C0290C4000000000000000300020362330 +:1032C0000000000000000000C0200400000000001A +:1032D0000000000000A0000A0000000086000000BE +:1032E00000204411000000000000000000404801E0 +:1032F0000000000085000000C02044110000000014 +:103300000000000000404801000000000000217C97 +:10331000002044110000000000000018402102209D +:10332000000000000000000014C000000000044580 +:1033300000800000C0494A20000004460000000050 +:10334000C02048000000000000000000C02048002D +:103350000000000000000000C02048000000000045 +:103360008100000000204411000000000000000166 +:10337000002048110000000000000000C0200800EC +:103380000000000000000000170000000000000026 +:103390000004217F006044110000068D0000001F22 +:1033A00000210230000000000000000014C00000F6 +:1033B000000000000000000000404C020000044B30 +:1033C00000000000C0200C00000000000000000011 +:1033D000C02010000000000000000000C020140009 +:1033E0000000000000000000C020180000000000E5 +:1033F00000000000C0201C000000000000007F0052 +:1034000000280A210000000000004500002F0222D1 +:1034100000000000000000000CE000000000045963 +:1034200000000000C020200000000000000000009C +:1034300017000000000000000000001000280A2310 +:103440000000000000000010002F02220000000019 +:10345000000000000CE0000000000461810000009A +:10346000002044110000000000000001002048116D +:103470000000000000040000006946240000068DE2 +:103480000000000000400000000004668100000011 +:10349000002044110000000000000000002048113E +:1034A000000000000000216D002044110000000019 +:1034B00000000000002048040000000000000000A0 +:1034C000006048050000069200000000002824F07B +:1034D000000000000000000700280A230000000090 +:1034E00000000001002F0222000000000000000088 +:1034F0000AE000000000046D00000000002F00C979 +:10350000000000000000000004E00000000004864D +:1035100000000000004000000000049300000002D2 +:10352000002F022200000000000000000AE000005E +:103530000000047200000000002F00C9000000001D +:103540000000000002E0000000000486000000000F +:10355000004000000000049300000003002F02223E +:1035600000000000000000000AE0000000000477F6 +:1035700000000000002F00C9000000000000000053 +:103580000CE0000000000486000000000040000085 +:103590000000049300000004002F0222000000003D +:1035A000000000000AE000000000047C00000000B1 +:1035B000002F00C900000000000000000AE0000029 +:1035C000000004860000000000400000000004939A +:1035D00000000005002F0222000000000000000093 +:1035E0000AE000000000048100000000002F00C974 +:1035F000000000000000000006E00000000004865B +:1036000000000000004000000000049300000006DD +:10361000002F022200000000000000000AE000006D +:103620000000048600000000002F00C90000000018 +:103630000000000008E00000000004860000000018 +:10364000004000000000049300007F0000280A21D1 +:103650000000000000004500002F022200000000D2 +:10366000000000000AE00000000000000000000868 +:1036700000210A23000000000000000014C0000028 +:1036800000000490000021690020441100000000A7 +:1036900000000000C0204800000000000000000002 +:1036A000C02048000000000000000000C0204800CA +:1036B00000000000CAFEBABE004048110000000031 +:1036C00000000000C02044000000000000000000D6 +:1036D000C02000000000000000000000C0404800C2 +:1036E0000000000000007F0000280A210000000008 +:1036F00000004500002F0222000000000000000032 +:103700000AE000000000049900000000C020000052 +:103710000000000000000000C020000000000000C9 +:1037200000000000C0400000000000000000000099 +:1037300000404C080000045900000000C0200800B0 +:10374000000000000000001040210E2000000000DA +:1037500000000011402112200000000000000012B3 +:1037600040211620000000000000216900204411C3 +:1037700000000000000000000020480200000000DF +:1037800000000000002102250000000000000000F1 +:1037900014E00000000004A300040000C0494A2017 +:1037A000000004A4FFFBFFFFC0284A200000000027 +:1037B00000000000002102230000000000000000C3 +:1037C00014E00000000004B000000000C020480029 +:1037D0000000000000000000C020480000000000C1 +:1037E0000000000000210224000000000000000092 +:1037F00014C00000000000008100000000204411FF +:10380000000000000000000C002048110000000033 +:103810000000000000200010000000000000000078 +:1038200014C00000000004ACA000000000204411FF +:1038300000000000CAFEBABE0040481100000000AF +:10384000810000000020441100000000000000047E +:1038500000204811000000000000216B00204411EE +:103860000000000000000000C02048100000000020 +:10387000810000000020441100000000000000054D +:1038800000204811000000000000216C00204411BD +:103890000000000000000000C020481000000000F0 +:1038A00000000000002F02240000000000000000C3 +:1038B0000CE00000000000000000000000400000DC +:1038C000000004AA00000000C0210A20000000003F +:1038D0000000000014C00000000004C381000000CC +:1038E00000204411000000000000000000204811EA +:1038F000000000000000216D0020441100000000C5 +:1039000000000000C020480000000000000000008F +:10391000C060480000000692000000000040000067 +:10392000000004C7810000000020441100000000D6 +:103930000000000100204811000000000004000009 +:10394000C02946200000000000000000C060000008 +:103950000000068D0000000100210222000000008E +:103960000000000014C00000000004CE0000216927 +:10397000002044110000000000000000C0204800AA +:103980000000000000000000C0204800000000000F +:10399000000000000020481000000000CAFEBABE6F +:1039A000004048110000000000000000C02044005A +:1039B0000000000000000000C040481000000000AF +:1039C0008100000000204411000000000000000100 +:1039D0000020481100000000000021F800204411E0 +:1039E000000000000000000E002048110000000050 +:1039F000000421F9006044110000068D0000000061 +:103A000000210230000000000000000014C000008F +:103A1000000004D0000021800020441100000000BC +:103A200000000000C020480000000000000000006E +:103A3000C02000000000000000000000C02048007E +:103A40000000000000000000C02000000000000096 +:103A500000000000C040480000000000000000031B +:103A600000333E2F00000000000000010021022171 +:103A7000000000000000000014E00000000005004D +:103A80000000002C00200A2D0000000000040000AF +:103A900018E00C11000004EF0000000100333E2F7D +:103AA0000000000000002169002044110000000017 +:103AB000000000000020480200000000000000009C +:103AC00000204803000000000000000800300A2227 +:103AD0000000000000000000C020480000000000BE +:103AE00000000000C0204800000000000000216924 +:103AF00000204411000000000000000000204802E7 +:103B0000000000000000000000204803000000004A +:103B10000000000800300A22000000000000000041 +:103B2000C02048000000000000000000D8C048008D +:103B3000000004E30000216900204411000000009F +:103B4000000000000020480200000000000000000B +:103B500000204803000000000000000800300A2296 +:103B60000000000000000000C0204800000000002D +:103B700000000000C0204800000000000000002DF0 +:103B80000020122D000000000000000000290C831E +:103B90000000000000002169002044110000000026 +:103BA00000000000002048020000000000000000AB +:103BB00000204803000000000000000800300A2236 +:103BC0000000000000000000C020480000000000CD +:103BD00000000000C02048000000000000000011AC +:103BE00000210224000000000000000014C00000BA +:103BF000000000000000000000400000000004AAD7 +:103C00000000002CC0203620000000000000002D25 +:103C1000C0403620000000000000000F00210221FB +:103C2000000000000000000014C0000000000505B6 +:103C300000000000006000000000000B0000000019 +:103C4000D90000000000000000000000C040040097 +:103C500000000001B5000000002044110000000039 +:103C6000000020000020481100000000B600000005 +:103C700000204411000000000000A00000204811B6 +:103C800000000000B7000000002044110000000008 +:103C90000000C0000020481100000000B800000033 +:103CA00000204411000000000000F8E0002048114E +:103CB00000000000B90000000020441100000000D6 +:103CC0000000F8800020481100000000BA00000049 +:103CD00000204411000000000000E0000020481116 +:103CE00000000000BB0000000020441100000000A4 +:103CF0000000F0000020481100000000BC0000009F +:103D000000204411000000000000F3FC00204811D6 +:103D100000000000810000000020441100000000AD +:103D2000000000020020481100000000000000FF19 +:103D300000280E300000000000000000002F0223C9 +:103D400000000000000000000CC000000000051989 +:103D500000000000C020080000000000000000007B +:103D600014C000000000052E0000000000200C110F +:103D7000000000000000001C0020362300000000AE +:103D80000000002B00203623000000000000002966 +:103D90000020362300000000000000280020362309 +:103DA0000000000000000017002036230000000083 +:103DB000000000250020362300000000000000263F +:103DC00000203623000000000000001500203623EC +:103DD0000000000000000016002036230000000054 +:103DE000FFFFE00000200C11000000000000002197 +:103DF00000203623000000000000002200203623AF +:103E00000000000000001FFF00200C110000000057 +:103E100000000023002036230000000000000024E2 +:103E20000020362300000000F1FFFFFF00283A2E9B +:103E3000000000000000001AC0220E200000000058 +:103E4000000000000029386E000000008100000022 +:103E5000002044110000000000000006002048116E +:103E6000000000000000002A402036200000000072 +:103E70008700000000204411000000000000000046 +:103E8000C0204800000000000000A1F40020441100 +:103E900000000000000000000020481000000000AA +:103EA0000000000000200C110000000000000030A5 +:103EB00000203623000000009D0000000020441177 +:103EC000000000000000001F40214A200000000008 +:103ED00096000000002044110000000000000000D7 +:103EE000C02048000000000000000000C0200C00BE +:103EF0000000000000000000C020100000000000D2 +:103F00000000001F00211624000000000000000037 +:103F100014C00000000000000000001D0020362337 +:103F2000000000000000000300281E230000000025 +:103F3000000000080022222300000000FFFFF00024 +:103F4000002822280000000000000000002920E8CE +:103F5000000000000000001F0020362800000000C4 +:103F60000000001800211E230000000000000020B7 +:103F70000020362700000000000000020022162466 +:103F80000000000000000000003014A80000000045 +:103F90000000001E00203625000000000000000385 +:103FA00000211A24000000001000000000281A263A +:103FB00000000000EFFFFFFF00283A2E0000000085 +:103FC00000000000004938CE0000067B0000000120 +:103FD00040280A20000000000000000640280E20B3 +:103FE0000000000000000300C028122000000000B4 +:103FF0000000000800211224000000000000000062 +:10400000C02016200000000000000000C0201A2080 +:10401000000000000000000000210222000000005B +:104020000000000014C000000000056681000000D0 +:104030000020441100000000000000010020481191 +:10404000000000000000225800300A240000000098 +:1040500000040000006946220000068D000021696E +:10406000002044110000000000000000002048056E +:10407000000000000002000000294A2600000000A5 +:10408000000000000020481000000000CAFEBABE78 +:10409000002048110000000000000002002F022351 +:1040A00000000000000000000CC000000000056ED1 +:1040B00000000000C0201C100000000000000000F4 +:1040C000C04000000000057C00000002002F022319 +:1040D00000000000000000000CC000000000056EA1 +:1040E00081000000002044110000000000000001D9 +:1040F00000204811000000000000225800300A246F +:104100000000000000040000006946220000068D47 +:1041100000000000C0201C10000000000000000093 +:10412000C04000000000057C00000000002F0223BA +:1041300000000000000000000CC00000000005723C +:1041400000000000C0201C00000000000000000073 +:10415000C04000000000057C00000004002F022386 +:1041600000000000000000000CC000000000057A04 +:104170008100000000204411000000000000000049 +:1041800000204811000000000000216D00204411B3 +:104190000000000000000000C020480000000000F7 +:1041A00000000000C060480000000692000000000F +:1041B00000401C100000057C00000000C020000032 +:1041C0000000000000000000C040000000000000EF +:1041D000000000000EE000000000057E000000006E +:1041E00000600000000005C900000000002F02244C +:1041F00000000000000000000CC000000000058F5F +:104200000000A2B7002044110000000000000000E0 +:104210000020480700000000810000000020441139 +:104220000000000000000001002048110000000014 +:104230000004A2B6006044110000068D0000001AC0 +:10424000002122300000000000000006002226307D +:104250000000000000042004006044110000068DEE +:104260000000A2C400204411000000000000000073 +:10427000003048E9000000000000000000E00000FD +:104280000000058D0000A2D10020441100000000B4 +:104290000000000000404808000000000000A2D11B +:1042A00000204411000000000000000100504A28D6 +:1042B0000000000000000001002F022400000000A8 +:1042C000000000000CC00000000005A00000A2BB20 +:1042D00000204411000000000000000000204807FA +:1042E00000000000810000000020441100000000D8 +:1042F0000000000100204811000000000004A2BAE4 +:10430000006044110000068D0000001A00212230D8 +:10431000000000000000000600222630000000001F +:1043200000042004006044110000068D0000A2C5B6 +:10433000002044110000000000000000003048E9A7 +:10434000000000000000000000E000000000059EEA +:104350000000A2D200204411000000000000000074 +:1043600000404808000000000000A2D200204411D4 +:10437000000000000000000100504A28000000007A +:1043800000000002002F02240000000000000000D6 +:104390000CC00000000005B10000A2BF00204411C5 +:1043A000000000000000000000204807000000009E +:1043B0008100000000204411000000000000000106 +:1043C00000204811000000000004A2BE006044115B +:1043D0000000068D0000001A0021223000000000BD +:1043E0000000000600222630000000000004200427 +:1043F000006044110000068D0000A2C60020441198 +:104400000000000000000000003048E9000000004B +:104410000000000000E00000000005AF0000A2D393 +:104420000020441100000000000000000040480887 +:10443000000000000000A2D3002044110000000092 +:104440000000000100504A28000000000000A2C344 +:104450000020441100000000000000000020480778 +:104460000000000081000000002044110000000056 +:104470000000000100204811000000000004A2C25A +:10448000006044110000068D0000001A0021223057 +:10449000000000000000000600222630000000009E +:1044A00000042004006044110000068D0000A2C733 +:1044B000002044110000000000000000003048E926 +:1044C000000000000000000000E00000000005BE49 +:1044D0000000A2D4002044110000000000000000F1 +:1044E00000404808000000000000A2D40020441151 +:1044F000000000000000000100504A2800000000F9 +:1045000085000000002044110000000000000000B1 +:1045100000204801000000000000304A0020441143 +:104520000000000001000000002048110000000011 +:104530000000000000400000000005C4A4000000CE +:10454000C02044110000000000000000C0404800EE +:104550000000000000000000C0600000000005C96D +:1045600000000000C0400400000000010000002C1A +:1045700000203621000000008100000000204411CE +:1045800000000000000000060020481100000000AC +:1045900000000000002F02300000000000000000BA +:1045A0000CC00000000005D0000000000020041135 +:1045B000000000000000003000403621000005E34C +:1045C000000000300020062D0000000000007E00EA +:1045D000002806210000000000000000002F02213A +:1045E00000000000000000000CE00000000005E3F7 +:1045F00081000000002044110000000000000001C4 +:1046000000204811000000000004A0920060441146 +:104610000000068D00000031002036300000000050 +:104620000004A093006044110000068D00000032D9 +:1046300000203630000000000004A2B600604411E3 +:104640000000068D0000003300203630000000001E +:104650000004A2BA006044110000068D000000347E +:1046600000203630000000000004A2BE00604411AB +:104670000000068D000000350020363000000000EC +:104680000004A2C2006044110000068D0000003644 +:1046900000203630000000000004200400604411B7 +:1046A0000000068D0001A2A40020441100000000BB +:1046B0000000003F00204811000000000000003F03 +:1046C00000204811000000000000003F00204811B9 +:1046D000000000000000003F002048110000000022 +:1046E0000000000500204811000000000000A1F4B7 +:1046F00000204411000000000000000000204811CC +:1047000000000000880000000020441100000000AC +:10471000000000010020481100000000810000009E +:104720000020441100000000000000060020481195 +:104730000000000000000001002F02300000000017 +:10474000000000000CE000000000062C000000301B +:104750000020062D0000000000000000002F0221B4 +:1047600000000000000000000CE000000000062C2B +:104770008100000000204411000000000000000142 +:10478000002048110000000000007E0000280621E3 +:104790000000000000000000002F022100000000C7 +:1047A000000000000CE00000000006050000A092E0 +:1047B00000204411000000000000003100204A2DBC +:1047C000000000000000A093002044110000000041 +:1047D0000000003200204A2D000000000000A2B6B8 +:1047E00000204411000000000000003300204A2D8A +:1047F000000000000000A2BA0020441100000000E8 +:104800000000003400204A2D000000000000A2BE7D +:1048100000204411000000000000003500204A2D57 +:10482000000000000000A2C20020441100000000AF +:104830000000003600204A2D00000000000000307B +:104840000020062D00000000000001FF00280621C6 +:104850000000000000000000002F02210000000006 +:10486000000000000CE000000000062B000000002B +:1048700000210221000000000000000014C0000020 +:104880000000060E0004A003006044110000068D25 +:104890000000A00300204411000000000000000000 +:1048A0000020481000000000000000010021062147 +:1048B000000000000000000014C00000000006130B +:1048C0000004A010006044110000068D0000A0103C +:1048D00000204411000000000000000000204810EB +:1048E000000000000000000100210621000000007F +:1048F00000000000002F0221000000000000000066 +:104900000CE000000000062B0004A0110060441120 +:104910000000068D0000A0110020441100000000DE +:104920000000000000204810000000000004A01259 +:10493000006044110000068D0000A0120020441108 +:1049400000000000000000000020481000000000EF +:104950000004A013006044110000068D0000A013A5 +:10496000002044110000000000000000002048105A +:10497000000000000004A014006044110000068D37 +:104980000000A014002044110000000000000000FE +:1049900000204810000000000004A0150060441131 +:1049A0000000068D0000A01500204411000000004A +:1049B0000000000000204810000000000004A016C5 +:1049C000006044110000068D0000A0160020441174 +:1049D000000000000000000000204810000000005F +:1049E0000004A017006044110000068D0000A0170D +:1049F00000204411000000000000000000204810CA +:104A00000000000000042004006044110000068D36 +:104A10000000002C0080062D00000000FF000000B8 +:104A20000020441100000000000000000020481198 +:104A300000000000000000010020481100000000FC +:104A4000000000020080481100000000000000008B +:104A50000EE000000000063D000000300020062DA2 +:104A600000000000000000020028062100000000F5 +:104A700000000000002F02210000000000000000E4 +:104A80000CE000000000063B810000000020441103 +:104A9000000000000000000100204811000000009C +:104AA00000042004006044110000068D0000100086 +:104AB00000200811000000000000002B002036221A +:104AC000000000000000000000600000000006413F +:104AD0000000000000600000000005C99800000010 +:104AE0000020441100000000000000000080481178 +:104AF0000000000000000000C0600000000006414F +:104B000000000000C0400400000000010000A2A45A +:104B10000020441100000000000000220020481185 +:104B20000000000089000000002044110000000087 +:104B300000000001004048110000062D9700000011 +:104B40000020441100000000000000000020481177 +:104B5000000000008A000000002044110000000056 +:104B600000000000004048110000062D0000000079 +:104B7000006000000000065C0000201000204411CE +:104B8000000000000000800000204811000000002C +:104B90000001A2A4C0204411000000000000001683 +:104BA000006048110000036E000020100020441136 +:104BB000000000000001000000204811000000007B +:104BC00081000000002044110000000000000001EE +:104BD00000204811000000000000217C002044114A +:104BE00000000000098000000020481100000000C3 +:104BF000FFFFFFFF00204811000000000000000040 +:104C00000020481100000000000000001700000014 +:104C1000000000000004217F006044110000068DA8 +:104C20000000001F00210230000000000000000012 +:104C300014C00000000000000000000400404C11FF +:104C400000000656000000000040000000000000C8 +:104C50000000001700201E2D0000000000000004CE +:104C600000291E27000000000000001700803627E2 +:104C7000000000000000001700201E2D00000000B2 +:104C8000FFFFFFFB00281E270000000000000017A8 +:104C900000803627000000000000001700201E2DB5 +:104CA000000000000000000800291E27000000008E +:104CB00000000017008036270000000000000017E9 +:104CC00000201E2D00000000FFFFFFF700281E2718 +:104CD00000000000000000170080362700000000E0 +:104CE000000020100020441100000000000080009F +:104CF00000204811000000000001A2A4002044117F +:104D00000000000000000016006048110000036E63 +:104D100000002010002044110000000000010000ED +:104D200000204811000000000000217C00204411F8 +:104D30000000000001800000002048110000000079 +:104D4000FFFFFFFF002048110000000000000000EE +:104D500000204811000000000000000017000000C3 +:104D6000000000008100000000204411000000004D +:104D70000000000100204811000000000004217F15 +:104D8000006044110000068D0000001F0021023069 +:104D9000000000000000000014C000000000068CAD +:104DA0000000001000404C110000067200000000DE +:104DB000C0200400000000000000000038C0000017 +:104DC000000000000000001D00200A2D000000006F +:104DD0000000001E00200E2D000000000000001F3B +:104DE0000020122D00000000000000200020162DE1 +:104DF00000000000000021690020441100000000B4 +:104E00000000000000204804000000000000000036 +:104E100000204805000000000000000000204801BC +:104E200000000000CAFEBABE0020481100000000C9 +:104E30000000000400301224000000000000000008 +:104E4000002F006400000000000000000CC0000003 +:104E50000000068B0000000300281A22000000005A +:104E6000000000080022122200000000FFFFF000F6 +:104E7000002812240000000000000000002910C4D7 +:104E8000000000000000001F004036240000000069 +:104E90000000000000800000000000000000000092 +:104EA0001AC000000000068D9F0000000020441181 +:104EB00000000000CAFEBABE002048110000000039 +:104EC000000000001AE00000000006900000000052 +:104ED0000080000000000000000000001AC0000078 +:104EE000000006929E000000002044110000000017 +:104EF000CAFEBABE002048110000000000000000F9 +:104F00001AE000000000069500000000008000008C +:104F10000000000000000000006000000000000B26 +:104F200000001000006004110000031500000000E4 +:104F300000200411000000000000000000600811C3 +:104F4000000001B20000225C0020441100000000BB +:104F5000000000030020481100000000000022565D +:104F600000204411000000000000001B0020481138 +:104F7000000000000000A1FC00204411000000001F +:104F80000000000100204811000000000001A1FD08 +:104F9000C0204411000000000000002100201E2D50 +:104FA000000000000000001000221E27000000008A +:104FB000000000240020222D000000000000FFFF60 +:104FC00000282228000000000000000000294907F6 +:104FD0000000000000000000002048110000000058 +:104FE000000000220020222D000000000000FFFF32 +:104FF00000282228000000000000000000294907C6 +:105000000000000000000000002048110000000027 +:105010000000002300201E2D0000000000000010F2 +:1050200000221E27000000000000000000294907A0 +:1050300000000000000000000040481100000000D7 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B0000142050205C002500000000001C3016860 +:1052C000043F05C000000000022502090250015100 +:1052D000000000000223024502A00241000000007D +:1052E00003D705C005C005C0000000000649064AF6 +:1052F000031F05C00000000005C005C503200340D2 +:1053000000000000032A0282034203340000000070 +:1053100005C005C005C005C00000000005C005515E +:1053200005C005C00000000003BA05C004BB03446B +:1053300000000000049A0450043D05C00000000075 +:1053400004D005C0044104DD00000000045005073E +:10535000035103750000000005C005C005C005C06D +:105360000000000005C005C005C005C00000000029 +:1053700005C005C0063F05C70000000005C005C008 +:10538000000705C00000000005C005C005C005C03D +:105390000000000005C005C005C005C000000000F9 +:1053A00003F803ED0408040600000000040E040ADC +:1053B000040C041000000000041C04180424042041 +:1053C00000000000042C0428043404300000000015 +:1053D00005C005C0043805C00000000005C005C0B8 +:1053E00005C005C00000000005C005C005C005C01F +:1053F0000000000000020679069700060000000089 +:00000001FF diff --git a/firmware/radeon/RV620_pfp.bin.ihex b/firmware/radeon/RV620_pfp.bin.ihex new file mode 100644 index 000000000000..f55292c97b79 --- /dev/null +++ b/firmware/radeon/RV620_pfp.bin.ihex @@ -0,0 +1,145 @@ +:1000000000CA040000A00000007E828B007C038BED +:10001000008001B8007C038B00D4401E00EE001E5F +:1000200000CA040000A00000007E828B00C41838C3 +:1000300000CA240000CA2800009581A800C41C3A08 +:1000400000C3C00000CA080000CA0C00007C744B4A +:1000500000C200050099C00000C41C3A007C744C2A +:1000600000C0FFF000042C0400309002007D250049 +:1000700000351402007D350B00255403007CD5802B +:1000800000259C030095C00400D5001B007EDDC147 +:10009000007D9D8000D6801B00D5801B00D4401EB3 +:1000A00000D5401E00D6401E00D6801E00D4801E03 +:1000B00000D4C01E009783D300D5C01E00CA08001C +:1000C0000080001A00CA0C0000E4011E00D4001ECB +:1000D0000080000C00C4183800E4013E00D4001E6B +:1000E0000080000C00C4183800D4401E00EE001E32 +:1000F00000CA040000A00000007E828B00E4011E04 +:1001000000D4001E00D4401E00EE001E00CA0400F1 +:1001100000A00000007E828B00E4013E00D4001E9F +:1001200000D4401E00EE001E00CA040000A0000023 +:10013000007E828B00CA180000D4401E00D5801EAD +:100140000080005300D4007500D4401E00CA08008F +:1001500000CA0C0000CA100000D4801900D4C018D6 +:1001600000D5001700D4801E00D4C01E00D5001E8C +:1001700000E2001E00CA040000A00000007E828B86 +:1001800000CA080000D4806000D4401E0080000037 +:1001900000D4801E00CA080000D4806100D4401E34 +:1001A0000080000000D4801E00CA080000CA0C00B5 +:1001B00000D4401E00D4801600D4C01600D4801E87 +:1001C000008001B800D4C01E00C6084300CA0C005D +:1001D00000CA10000094800400CA140000E420F358 +:1001E00000D4201300D5606500D4E01C00D5201C8D +:1001F00000D5601C008000000006200100C60843F6 +:1002000000CA0C0000CA1000009483F700CA140052 +:1002100000E420F30080007900D4201300C60843D6 +:1002200000CA0C0000CA1000009883EF00CA140036 +:1002300000D400640080008D0000000000C414326F +:1002400000C6184300C4082F0095400500C40C30B8 +:1002500000D4401E0080000000EE001E009583F5D3 +:1002600000C4103100D4403300D5206500D4A01C58 +:1002700000D4E01C00D5201C00E4015E00D4001E68 +:10028000008000000006200100CA1800000A2001BA +:1002900000D6007600C408360098800700C61045D6 +:1002A0000095011000D4001F00D46062008000009F +:1002B00000D4206200CC383500CC1433008401BB5C +:1002C00000D4007200D5401E0080000000EE001E29 +:1002D00000E2001A008401BB00E2001A00CC104BBF +:1002E00000CC0447002C9401007D098B0098400548 +:1002F000007D15CB00D4001A008001B800D4006D39 +:100300000034440100CC0C480098403A00CC2C4A00 +:100310000095800400CC0449008001B800D4001A84 +:1003200000D4C01A00282801008400F000CC10037B +:100330000098801B0004380C008400F000CC1003EF +:100340000098801700043808008400F000CC1003E7 +:100350000098801300043804008400F000CC1003DF +:100360000098801400CC104C009A800900CC144DE9 +:10037000009840DC00D4006D00CC184800D5001A6D +:1003800000D5401A008000C900D5801A0096C0D55B +:1003900000D4006D008001B800D4006E009AC00344 +:1003A00000D4006D00D4006E0080000000EC007FDF +:1003B000009AC0CC00D4006D008001B800D4006E5B +:1003C00000CC140300CC180300CC1C03007D910367 +:1003D000007DD583007D190C0035CC1F0035701FC2 +:1003E000007CF0CB007CD08B00880000007E8E8BE0 +:1003F0000095C00400D4006E008001B800D4001A3B +:1004000000D4C01A00CC080300CC0C0300CC1003AD +:1004100000CC140300CC180300CC1C0300CC240334 +:1004200000CC28030035C41F0036B01F007C704B81 +:100430000034F01F007C704B0035701F007C704B47 +:10044000007D8881007DCCC1007E5101007E9541F8 +:10045000007C9082007CD4C2007C848B009AC00314 +:10046000007C8C8B002C88010098809E00D4006D4D +:100470000098409C00D4006E00CC084C00CC0C4D81 +:1004800000CC104800D4801A00D4C01A00800101AA +:1004900000D5001A00CC083200D40032009482D972 +:1004A00000CA0C0000D4401E0080000000D4001ED2 +:1004B00000E4011E00D4001E00CA080000CA0C009F +:1004C00000CA100000D4401E00CA140000D4801ED0 +:1004D00000D4C01E00D5001E00D5401E00D54034FB +:1004E0000080000000EE001E0028040400E2001A54 +:1004F00000E2001A00D4401A00CA380000CC0803F9 +:1005000000CC0C0300CC0C0300CC0C03009882BD83 +:1005100000000000008401BB00D7A06F0080000035 +:1005200000EE001F00CA040000C2FF0000CC083427 +:1005300000C13FFF007C74CB007CC90B007D010F24 +:10054000009902B0007C738B008401BB00D7A06FC0 +:100550000080000000EE001F00CA080000281900FB +:10056000007D898B009580140028140400CA0C00BB +:1005700000CA100000CA1C0000CA240000E2001FCC +:1005800000D4C01A00D5001A00D5401A00CC1803B8 +:1005900000CC2C0300CC2C0300CC2C03007DA58BBD +:1005A000007D9C4700984297000000000080016198 +:1005B00000D4C01A00D4401E00D4801E0080000069 +:1005C00000EE001E00E4011E00D4001E00D4401EF8 +:1005D00000EE001E00CA040000A00000007E828B16 +:1005E00000E4013E00D4001E00D4401E00EE001EB8 +:1005F00000CA040000A00000007E828B00CA080030 +:1006000000248C06000CCC060098C00600CC104ECE +:100610000099000400D4007300E4011E00D4001E01 +:1006200000D4401E00D4801E0080000000EE001E9A +:1006300000CA080000CA0C000034D01800251001C0 +:100640000095002100C17FFF00CA100000CA1400FD +:1006500000CA180000D4801D00D4C01D007DB18BDD +:1006600000C1420200C2C00100D5801D0034DC0E72 +:10067000007D5D4C007F734C00D7401E00D5001EEE +:1006800000D5401E00C1420000C2C00000099C010C +:100690000031DC10007F5F4C007F734C00042802A7 +:1006A000007D838000D5A86F00D5806600D7401EEE +:1006B00000EC005E00C8240200C82402008001B8DB +:1006C00000D6007600D4401E00D4801E00D4C01E88 +:1006D0000080000000EE001E0080000000EE001F01 +:1006E00000D4001F0080000000D4001F00D4001FB1 +:1006F0000088000000D4001F00000000000000007F +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000010171000201780003008F0004007FE5 +:10081000000500030006003F000700320008012C1D +:1008200000090046000A0036001001B6001700A2B9 +:100830000022013A00230149002000B400240125D0 +:100840000027004D0028006A002A0060002B00529B +:10085000002F0065003200870034017F003C015604 +:10086000003F00720041018C0044012E00550173CD +:100870000056017A0060000B00610034006200380D +:1008800000630038006400380065003800660038F6 +:10089000006700380068003A00690041006A0048BB +:1008A000006B0048006C0048006D0048006E004876 +:1008B000006F00480000000600000006000000066F +:1008C0000000000600000006000000060000000610 +:1008D0000000000600000006000000060000000600 +:1008E00000000006000000060000000600000006F0 +:1008F00000000006000000060000000600000006E0 +:00000001FF diff --git a/firmware/radeon/RV630_me.bin.ihex b/firmware/radeon/RV630_me.bin.ihex new file mode 100644 index 000000000000..ba3a7e632d97 --- /dev/null +++ b/firmware/radeon/RV630_me.bin.ihex @@ -0,0 +1,1345 @@ +:1000000000000000C020040000000000000000000C +:1000100000A0000A000000000000FFFF00284621A9 +:100020000000000000000000D900480000000000AF +:1000300000000000C02004000000000000000000DC +:1000400000A0000A000000000000000000E0000026 +:100050000000000000010000C02946200000000050 +:1000600000000000D900480000000000000000006F +:10007000C0200400000000000000000000A0000AF2 +:10008000000000008100000000204411000000007A +:1000900000000001002048110000000000042004BE +:1000A000006044110000068A0000000000600000AB +:1000B0000000062E00000000006000000000064264 +:1000C00000000000C02008000000000000000F0039 +:1000D000002816220000000000000008002116255C +:1000E000000000000000001800203625000000007D +:1000F0008D000000002044110000000000000004FA +:10010000002F022500000000000000000CE00000AD +:1001100000000018004120000040481100000019B4 +:100120000042200000204811000000008E00000066 +:1001300000204411000000000000002800204A2D8B +:1001400000000000900000000020441100000000AA +:100150000000000000204805000000000000000C26 +:1001600000211622000000000000000300281625D0 +:10017000000000000000001900211A220000000009 +:100180000000000400281A26000000000000000003 +:10019000002914C5000000000000001900203625C9 +:1001A0000000000000000000003A140200000000FF +:1001B00000000016002116250000000000000003CA +:1001C00000281625000000000000001700200E2D5A +:1001D00000000000FFFFFFFC00280E2300000000CD +:1001E00000000000002914A3000000000000001718 +:1001F00000203625000000000000800000280E22AC +:10020000000000000000000700220E230000000094 +:10021000000000000029386E0000000020000000EF +:1002200000280E22000000000000000600210E231E +:1002300000000000000000000029386E00000000EF +:100240000000000000220222000000000000000068 +:1002500014E0000000000038000000002EE0000064 +:1002600000000035000000002CE000000000003716 +:100270000000000000400E2D0000003900000008C2 +:1002800000200E2D00000000000000090040122D8B +:10029000000000460000000100400E2D0000003963 +:1002A00000000000C0200C0000000000003FFFFC28 +:1002B0000028122300000000000000020022122487 +:1002C000000000000000001F00211E2300000000AD +:1002D0000000000014E000000000003E00000008E4 +:1002E00000401C11000000410000000D00201E2DE8 +:1002F000000000000000000F00281E270000000082 +:100300000000000300221E27000000007FC0000044 +:1003100000281A23000000000000001400211A2603 +:10032000000000000000000100331A260000000059 +:100330000000000800221A26000000000000000053 +:1003400000290CC700000000000000270020362410 +:100350000000000000007F000028122100000000C3 +:1003600000001400002F0224000000000000000024 +:100370000CE000000000004B0000000100290E23EB +:10038000000000000000000E0020362300000000E6 +:100390000000E0000020441100000000FFF8000011 +:1003A00000294A230000000000000000003A2C024F +:1003B000000000000000000200220E2B00000000E0 +:1003C000FC00000000280E23000000000000000FC9 +:1003D000002036230000000000001FFF00294A23F0 +:1003E000000000000000002700204A2D000000004F +:1003F000000000000020481100000000000000295B +:1004000000200E2D00000000060A020000294A23E9 +:100410000000000000000000002048110000000063 +:100420000000000000204811000000000000000152 +:1004300000210222000000000000000014E0000083 +:1004400000000061000000002EE000000000005FDE +:10045000000000002CE000000000005E0000000032 +:1004600000400E2D000000620000000100400E2D33 +:10047000000000620000000A00200E2D00000000B5 +:100480000000000B0040122D0000006A0000000078 +:10049000C0200C0000000000003FFFFC00281223D9 +:1004A00000000000000000020022122400000000F2 +:1004B0007FC0000000281623000000000000001488 +:1004C0000021162500000000000000010033162561 +:1004D000000000008000000000280E230000000043 +:1004E0000000000000290CA3000000003FFFFC00FA +:1004F00000290E23000000000000001F00211E2321 +:10050000000000000000000014E000000000006D8A +:100510000000010000401C11000000700000000DF0 +:1005200000201E2D00000000000000F000281E2703 +:10053000000000000000000400221E270000000050 +:100540008100000000204411000000000000000DA8 +:100550000020481100000000FFFFF0FF00281A30C3 +:10056000000000000000A02800204411000000004E +:1005700000000000002948E6000000000000A0186C +:1005800000204411000000003FFFFFFF00284A2325 +:10059000000000000000A010002044110000000036 +:1005A00000000000002048040000000000000030AF +:1005B0000020162D00000000000000020029162572 +:1005C0000000000000000030002036250000000080 +:1005D000000000250020162D000000000000000093 +:1005E000002F00A300000000000000000CC000006D +:1005F00000000083000000260020162D00000000EF +:1006000000000000002F00A4000000000000000017 +:100610000CC000000000008400000000004000004A +:100620000000008A000000250020362300000000A2 +:100630000000002600203624000000000000001703 +:1006400000201E2D000000000000000200210227F3 +:10065000000000000000000014E000000000008A1C +:1006600000000000006000000000066500000000BF +:1006700000600000000006590000000200210E2268 +:10068000000000000000000014C000000000008D09 +:1006900000000012C040362000000093000000005F +:1006A0002EE0000000000091000000002CE000009F +:1006B000000000900000000200400E2D000000929B +:1006C0000000000300400E2D000000920000000C0E +:1006D00000200E2D00000000000000120020362334 +:1006E000000000000000000300210E2200000000B6 +:1006F0000000000014C00000000000980000A00CE2 +:10070000002044110000000000000000C02048004C +:100710000000000000000000C0404800000000A0F1 +:100720000000A00C002044110000000000000000A8 +:100730000020481100000000000000002EE0000032 +:100740000000009E000000002CE000000000009D62 +:100750000000000200400E2D0000009F000000037A +:1007600000400E2D0000009F0000000C00200E2D08 +:10077000000000000000000000204803000000000E +:1007800000000000003A0C0200000000003F0000E2 +:1007900000280E23000000000000001000210E239E +:1007A00000000000000000110020362300000000BF +:1007B0000000001E0021022B0000000000000000CD +:1007C00014C00000000000A700000016C020362062 +:1007D000000000000000001F0021022B00000000AC +:1007E0000000000014C00000000000AA0000001576 +:1007F000C0203620000000000000000800210E2B61 +:10080000000000000000007F00280E230000000010 +:1008100000000000002F0223000000000000000084 +:100820000CE00000000000E10000000027000000D4 +:10083000000000000000000000600000000002A3B3 +:1008400000000001002F0223000000000000000053 +:100850000AE00000000000B300000000006000009B +:100860000000013A81000000002044110000000057 +:100870000000000600204811000000000000000CED +:1008800000221E300000000099800000002044116A +:1008900000000000000000040020122D00000000F5 +:1008A00000000008002212240000000000000010D8 +:1008B00000201811000000000000000000291CE4C6 +:1008C0000000000000000000006048070000012F49 +:1008D0009B00000000204411000000000000000008 +:1008E00000204802000000009C000000002044118D +:1008F00000000000000000000033146F0000000042 +:100900000000000100333E23000000000000000052 +:10091000D9004800000000000000000000203C0555 +:1009200000000000810000000020441100000000D1 +:100930000000000E00204811000000000000000030 +:1009400000201010000000000000E007002044110B +:10095000000000000000000F0021022B000000003A +:100960000000000014C00000000000CB00F8FF08E9 +:1009700000204811000000009800000000404811CD +:10098000000000DC000000F000280E220000000043 +:10099000000000A0002F0223000000000000000063 +:1009A0000CC00000000000DA0000001100200E2D35 +:1009B0000000000000000001002F022300000000E2 +:1009C000000000000CE00000000000D50000000264 +:1009D000002F022300000000000000000CE00000D7 +:1009E000000000D400003F0000400C11000000D6C1 +:1009F00000001F0000400C11000000D600000F0096 +:100A000000200C11000000000038000900294A23D2 +:100A1000000000003F00000000280E2B0000000036 +:100A20000000000200220E2300000000000000076A +:100A300000494A23000000DC00380F09002048115B +:100A400000000000680000070020481100000000BE +:100A50000000000800214A270000000000000000FC +:100A60000020481100000000060A020000294A2464 +:100A700000000000000000000020481100000000FD +:100A80000000000000204811000000000000A20249 +:100A9000002044110000000000FF000000280E228A +:100AA000000000000000008000294A230000000030 +:100AB0000000002700200E2D00000000000000268E +:100AC0000020122D0000000000000000002F008315 +:100AD00000000000000000000CE00000000000EA40 +:100AE00000000000006000000000065F0000000041 +:100AF00000400000000000EB00000000006000006B +:100B000000000662000000070020222D0000000007 +:100B10000000000500220E2200000000001000006E +:100B200000280E23000000000000000000292068BB +:100B30000000000000000000003A0C02000000006D +:100B4000000000EF00280E2300000000000000005D +:100B500000292068000000000000001700200E2D72 +:100B6000000000000000000300210223000000003C +:100B70000000000014E00000000000F80000000B7E +:100B800000210228000000000000000014C0000046 +:100B9000000000F8000004000029222800000000E6 +:100BA0000000001400203628000000000000001C97 +:100BB00000210E22000000000000000014C0000010 +:100BC000000000FD0000A30C002044110000000004 +:100BD0000000000000204811000000000000001E7E +:100BE00000210E22000000000000000014C00000E0 +:100BF0000000010B0000A30F0020441100000000C2 +:100C00000000001100200E2D000000000000000177 +:100C1000002F022300000000000000000CC00000B4 +:100C200000000104FFFFFFFF004048110000010B1E +:100C300000000002002F022300000000000000005E +:100C40000CC00000000001070000FFFF0040481139 +:100C50000000010B00000004002F02230000000030 +:100C6000000000000CC000000000010A000000FFAE +:100C7000004048110000010B000000010020481155 +:100C8000000000000002C400002044110000000029 +:100C90000000001F00210E220000000000000000E4 +:100CA00014C00000000001120000001040210E20BE +:100CB00000000000000000130020362300000000A8 +:100CC0000000001840224A20000000000000001030 +:100CD000C0424A20000001140000000000200C1156 +:100CE0000000000000000013002036230000000078 +:100CF000000000000020481100000000000000007B +:100D000000204811000000000000000A002010111F +:100D10000000000000000000002F0224000000007E +:100D2000000000000CE000000000011B00000000BB +:100D300000204811000000000000000100531224B0 +:100D400000000117FFBFFFFF00283A2E000000003F +:100D50000000001B00210222000000000000000033 +:100D600014C000000000012E81000000002044118A +:100D7000000000000000000D0020481100000000ED +:100D80000000001800220E3000000000FC000000EF +:100D900000280E2300000000810000000020441104 +:100DA000000000000000000E0020481100000000BC +:100DB0000000000000201010000000000000E00E05 +:100DC000002044110000000007F8FF08002048112F +:100DD000000000000000000000294A23000000007D +:100DE0000000001C00201E2D000000000000000874 +:100DF00000214A27000000000000000000204811E8 +:100E000000000000060A020000294A240000000039 +:100E10000000000000204811000000000000000059 +:100E200000204811000000000000000000800000C9 +:100E300000000000810000000020441100000000BC +:100E40000000000100204811000000000000217C8B +:100E50000020441100000000008000000020481124 +:100E60000000000000000000002048060000000014 +:100E70000000000800214A270000000000000000D8 +:100E800017000000000000000004217F00604411F2 +:100E90000000068A0000001F002102300000000050 +:100EA0000000000014C000000000068900000004DB +:100EB00000404C1100000135810000000020441169 +:100EC00000000000000000010020481100000000A8 +:100ED000000021F800204411000000000000001C68 +:100EE0000020481100000000000421F900604411B6 +:100EF0000000068A000000110021023000000000FE +:100F00000000000014E000000000013C00000000B0 +:100F100000800000000000000000000000600000F1 +:100F20000000000B00000000006004110000031529 +:100F3000000000000020041100000000000000007C +:100F400000600811000001B2000000000060000015 +:100F5000000001600000FFFF40280E20000000009C +:100F600000000010C0211220000000000000FFFF60 +:100F7000402806200000000000000010C0210A20C8 +:100F800000000000000000000034146100000000B8 +:100F90000000000000741882000002BB0001A1FDE7 +:100FA00000604411000002E000003FFF002F022F0C +:100FB00000000000000000000CC00000000001471D +:100FC00000000000C040040000000001000000001C +:100FD000006000000000000B000000000060041131 +:100FE00000000315000000000020041100000000B4 +:100FF0000000000000600811000001B200003FFF87 +:10100000002F022F00000000000000000CE0000094 +:10101000000000000000000000600000000001600F +:101020000000001040210E20000000000000FFFF23 +:10103000C0281220000000000000001040211620EF +:10104000000000000000FFFFC0681A20000002BB83 +:101050000001A1FD00604411000002E000003FFF1C +:10106000002F022F00000000000000000CC0000054 +:101070000000015800000000C04004000000000112 +:101080000000225C0020441100000000000000016C +:1010900000300A2F000000000000000100210A2299 +:1010A000000000000000000300384A220000000099 +:1010B0000000225600204411000000000000001A29 +:1010C00000204811000000000000A1FC0020441195 +:1010D0000000000000000001008048110000000036 +:1010E00000000000006000000000000B0000000095 +:1010F000006000000000018F0000000000600000A0 +:10110000000001A000003FFF002F022F00000000A0 +:10111000000000000CE000000000000000000000E3 +:1011200000202C0800000000000000000020241116 +:101130000000000000000000002028110000000056 +:10114000000022560020441100000000000000169C +:1011500000204811000000000000225C0020441123 +:101160000000000000000003002048110000000003 +:1011700093800000002044110000000000000002E5 +:1011800000221E290000000000000000007048EB53 +:101190000000019C0000000000600000000002BB95 +:1011A00000000001403306200000000000000000A5 +:1011B000C03024090000000000003FFF002F022F74 +:1011C00000000000000000000CE000000000000033 +:1011D0000000000000600000000002A3000000000A +:1011E000002F022100000000000000000AE00000C3 +:1011F0000000018100000000006000000000013AD2 +:101200000000000000400000000001869500000082 +:10121000002044110000000000000000002F022107 +:1012200000000000000000000CE00000000001864B +:1012300000000000C0204800000000000000000185 +:10124000005306210000018292000000002044119A +:101250000000000000000000C0604800000001978E +:101260000001A1FD00204411000000000000001159 +:101270000020062D00000000000000000078042A75 +:10128000000002FB00000000002028090000000010 +:1012900000003FFF002F022F0000000000000000B0 +:1012A0000CC000000000017400000000C0400400F9 +:1012B000000000010000021000600411000003158E +:1012C00000003FFF002F022F000000000000000080 +:1012D0000CE000000000019400000015C020362042 +:1012E0000000000000000016C020362000000000B2 +:1012F0003F800000002004110000000046000000B4 +:1013000000600811000001B2000000000080000031 +:10131000000000000000A1FC0020441100000000BB +:1013200000003FFF002F022F00000000000000001F +:101330000CC000000000019B00000001008048116B +:1013400000000000000000210080481100000000A3 +:101350000000FFFF40280E200000000000000010E9 +:10136000C0211220000000000000FFFF40281620CE +:101370000000000000000010C0811A2000000000E2 +:101380008100000000204411000000000000000661 +:1013900000204811000000000000000800221E305C +:1013A000000000000000002900201A2D00000000AD +:1013B0000000E0000020441100000000FFFBFF09D6 +:1013C00000204811000000000000000F0020222D26 +:1013D0000000000000001FFF00294A280000000054 +:1013E000000000060020222D000000000000000088 +:1013F000002920E80000000000000000002048084C +:101400000000000000000000002048110000000063 +:10141000060A020000294A26000000000000000021 +:1014200000204811000000000000000000204811CA +:101430000000000000000100002018110000000062 +:101440000000000800621E280000012F00000008B4 +:1014500000822228000000000002C0000020441189 +:10146000000000000000001500600E2D000001BD0E +:101470000000001600600E2D000001BD0000C00835 +:1014800000204411000000000000001700200E2D75 +:10149000000000000000000014C00000000001B9BE +:1014A0000000000000200411000000000000000007 +:1014B0000020480100000000390000000020481111 +:1014C00000000000000000000020481100000000A3 +:1014D000000000000080480200000000000000182A +:1014E00000202E2D0000000000000000003B0D63D6 +:1014F000000000000000000800224A230000000055 +:101500000000001000224A23000000000000001824 +:1015100000224A2300000000000000000080480371 +:101520000000000000000000006000000000000B50 +:10153000000010000060041100000315000000000E +:1015400000200411000000000000000000600811ED +:10155000000001B2000000070021062F000000007B +:101560000000001300200A2D000000000000000110 +:1015700000202C11000000000000FFFF4028222066 +:10158000000000000000000F0026222800000000DC +:101590000000001040212620000000000000000F85 +:1015A000002626290000000000000000002028027C +:1015B000000000000000225600204411000000003E +:1015C0000000001B00204811000000000000000087 +:1015D000002F022100000000000000000CE00000CD +:1015E000000001E00000225C002044110000000027 +:1015F0000000008100204811000000000000A1FC54 +:1016000000204411000000000000000100204811EB +:10161000000000000000008000201C1100000000FD +:1016200000000000002F0227000000000000000062 +:101630000CE00000000001DC000000000060000081 +:10164000000001E90000000100531E27000001D83E +:101650000000000100202C11000000000000001F0D +:1016600000280A22000000000000001F00282A2A8B +:10167000000000000000000100530621000001D11D +:101680000000225C00204411000000000000000265 +:1016900000304A2F000000000000A1FC002044118F +:1016A00000000000000000010020481100000000C0 +:1016B0000000000100301E2F0000000000000000AC +:1016C000002F022700000000000000000CE00000D6 +:1016D000000000000000000000600000000001E9C0 +:1016E0000000000100531E27000001E50000FFFF7D +:1016F00040280E20000000000000000F00260E23EE +:101700000000000000000010C021122000000000B6 +:101710000000000F0026122400000000000000005E +:1017200000201411000000000000000000601811EB +:10173000000002BB0001A1FD0020441100000000D8 +:1017400000000000002F022B00000000000000003D +:101750000CE00000000001F8000000100022162834 +:1017600000000000FFFF0000002816250000000018 +:101770000000FFFF00281A29000000000000000000 +:10178000002948C500000000000000000020480AB1 +:10179000000000000000000000202C1100000000EC +:1017A000000000100022162300000000FFFF0000D0 +:1017B00000281625000000000000FFFF00281A2462 +:1017C0000000000000000000002948C500000000E3 +:1017D0000000000000731503000002050000000077 +:1017E0000020180500000000000000000073152410 +:1017F0000000020500000000002D14C500000000DC +:1018000000000000003008A20000000000000000FE +:101810000020480200000000000000000020280214 +:101820000000000000000000002020030000000075 +:101830000000000000802404000000000000000FF1 +:1018400000210225000000000000000014C000007C +:101850000000068900000000002B140500000000B5 +:1018600000000001009016250000000000000000AC +:10187000006000000000000B000000000060041188 +:10188000000003150000000000200411000000000B +:101890000000000000600811000001B200002256A4 +:1018A00000204411000000000000001A00294A2214 +:1018B0000000000000000000C02000000000000048 +:1018C00000003FFF002F022F00000000000000007A +:1018D0000CE000000000000000000000C020040038 +:1018E000000000000000225C002044110000000005 +:1018F0000000000300384A21000000000000A1FCA5 +:1019000000204411000000000000000100204811E8 +:10191000000000000000FFFF40281220000000002F +:1019200000000010C0211A20000000000000FFFF8E +:1019300040280E200000000000000010C0211620EA +:10194000000000000000000000741465000002BBED +:101950000001A1FD00604411000002E00000000150 +:10196000003306210000000000000000002F0221CB +:1019700000000000000000000CC000000000021980 +:1019800000003FFF002F022F0000000000000000B9 +:101990000CC000000000021200000000C040040063 +:1019A000000000010000000000600000000006428E +:1019B000000000000040040F0000021300000000BF +:1019C000006000000000062E000000000060000023 +:1019D0000000064200000210006004110000031520 +:1019E0000000000000600000000001A000000000F6 +:1019F000006000000000019C00000000006000008A +:101A0000000002BB0000000000600000000002A314 +:101A1000938000000020441100000000000000003E +:101A2000002048080000000000000000002F022FE6 +:101A300000000000000000000AE000000000023288 +:101A400000000000006000000000013A00000000FB +:101A50000040000000000236950000000020441104 +:101A60000000000000000000002F022F0000000016 +:101A7000000000000CE00000000002360000000042 +:101A8000C0404800000002339200000000204411D2 +:101A90000000000000000000C0204800000000001E +:101AA0000000225600204411000000000000001633 +:101AB00000204811000000000000225C00204411BA +:101AC000000000000000000300204811000000009A +:101AD0000000A1FC002044110000000000000001F3 +:101AE00000204811000000000001A1FD0020441169 +:101AF000000000000000000000600411000002FB74 +:101B000000000000C04004000000000100000000D0 +:101B1000006000000000062E0000A00C0020441110 +:101B20000000000000000000C0204800000000008D +:101B300000000000C040480000000000000000005D +:101B4000006000000000000B0000001840210A2087 +:101B50000000000000000003002F0222000000002F +:101B6000000000000AE000000000024C0000001429 +:101B70000020222D00000000000801010029222879 +:101B800000000000000000140020362800000000C3 +:101B90000000A30C00204411000000000000000021 +:101BA000C02048000000000000000000C0204800E5 +:101BB0000000000000000000C0404800000002518A +:101BC00000000000006000000000000B000000109A +:101BD00000600411000003153F8000000020041184 +:101BE000000000000000000000600811000001B2C9 +:101BF0000000225C002044110000000000000003EF +:101C000000204811000000000000000000600000FB +:101C10000000027C0000001700201E2D00000000C4 +:101C20000000000100211E2700000000000000004D +:101C300014E000000000026A0000001200201E2DC7 +:101C4000000000000000FFFF00281E270000000029 +:101C50000000000000341C2700000000000000000D +:101C600012C000000000025F0000000000201C11F4 +:101C70000000000000000000002F00E50000000050 +:101C80000000000008C00000000002620000000028 +:101C900000201407000000000000001200201E2D8C +:101CA000000000000000001000211E2700000000BE +:101CB0000000000000341C4700000000000000008D +:101CC00012C00000000002670000000000201C118C +:101CD0000000000000000000002F00E600000000EF +:101CE0000000000008C000000000026A00000000C0 +:101CF0000020180700000000000000000060000045 +:101D0000000002C100002256002044110000000023 +:101D1000000000000034202300000000000000004C +:101D200012C00000000002720000000000342044D5 +:101D3000000000000000000012C00000000002715E +:101D40000000001600404811000002760000001854 +:101D500000404811000002760000000000342044DA +:101D6000000000000000000012C00000000002752A +:101D70000000001700404811000002760000001922 +:101D800000204811000000000000A1FC00204411C8 +:101D900000000000000000010020481100000000C9 +:101DA0000001A1FD00604411000002E900003FFFB6 +:101DB000002F022F00000000000000000CC00000F7 +:101DC0000000025600000000C040040000000001B6 +:101DD0000000001040210620000000000000FFFF6E +:101DE000C0280A20000000000000001040210E2042 +:101DF000000000000000FFFFC028122000000000CB +:101E00000000001040211620000000000000FFFF2D +:101E1000C0881A200000000081000000002044114A +:101E20000000000000000001002048110000000038 +:101E300000042004006044110000068A0000000035 +:101E4000006000000000062E00000000C0600000DE +:101E5000000002A30000000500200A2D0000000081 +:101E60000000000800220A22000000000000002BF1 +:101E700000201A2D000000000000001C00201E2D74 +:101E8000000000000000700000281E270000000075 +:101E90000000000000311CE6000000000000002AE5 +:101EA00000201A2D000000000000000C00221A265D +:101EB0000000000000000000002F00E6000000000D +:101EC0000000000006E00000000002920000000098 +:101ED00000201C11000000000000000000200C1178 +:101EE000000000000000002B00203623000000004E +:101EF0000000001000201811000000000000000089 +:101F000000691CE20000012F9380000000204411B2 +:101F10000000000000000000002048070000000052 +:101F200095000000002044110000000000000000A7 +:101F3000002F022F00000000000000000CE0000055 +:101F40000000029D0000000100333E2F0000000051 +:101F500000000000D90048000000000092000000CE +:101F6000002044110000000000000000C0204800D4 +:101F7000000000000000001C0040362700000000A8 +:101F80000000000CC0220A20000000000000002910 +:101F9000002036220000000000000028C04036204B +:101FA000000000000000A2A4002044110000000076 +:101FB000000000090020481100000000A1000000FE +:101FC00000204411000000000000000100804811C2 +:101FD000000000000000002100201E2D0000000075 +:101FE00000000000002C1CE30000000000000021A5 +:101FF00000203627000000000000002200201E2DD7 +:102000000000000000000000002C1CE400000000A4 +:1020100000000022002036270000000000000023FE +:1020200000201E2D0000000000000000003120A351 +:102030000000000000000000002D1D07000000004F +:1020400000000023002036270000000000000024CC +:1020500000201E2D0000000000000000003120C400 +:102060000000000000000000002D1D07000000001F +:10207000000000240080362700000000000000213E +:10208000002036230000000000000022002036243B +:10209000000000000000000000311CA30000000050 +:1020A0000000002300203627000000000000000090 +:1020B00000311CC40000000000000024008036270E +:1020C000000000000000001A002036270000000079 +:1020D0000000001B00203628000000000000001750 +:1020E00000201E2D00000000000000020021022739 +:1020F000000000000000000014C00000000002DC2E +:102100000000000000400000000002D90000001A9A +:1021100000203627000000000000001B00203628A9 +:10212000000000000000001700201E2D000000002D +:102130000000000200210227000000000000000053 +:1021400014E00000000002D9000000030021022773 +:10215000000000000000000014E00000000002DCAD +:102160000000002300201E2D0000000000000000E1 +:10217000002E00E1000000000000000002C000008E +:10218000000002DC0000002100201E2D00000000E5 +:1021900000000000003120A100000000000000004D +:1021A000002E00E8000000000000000006C0000053 +:1021B000000002DC0000002400201E2D00000000B2 +:1021C00000000000002E00E20000000000000000FF +:1021D00002C00000000002DC0000002200201E2DD2 +:1021E0000000000000000000003120C200000000DC +:1021F00000000000002E00E80000000000000000C9 +:1022000006C00000000002DC0000000000600000CA +:10221000000006650000000000600000000002B53C +:102220000000000000400000000002DE000000008E +:1022300000600000000002B5000000000060000027 +:102240000000065C0000000000400000000002DE0C +:102250000000000000600000000002A70000000075 +:1022600000400000000002DE0000001A00201E2DC9 +:10227000000000000000001B0080222D0000000074 +:102280000000001000221E230000000000000000DB +:1022900000294887000000000000000000311CA356 +:1022A000000000000000001000221E2700000000B7 +:1022B0000000000000294887000000000000001016 +:1022C00000221E230000000000000000003120C496 +:1022D000000000000000FFFF00282228000000008E +:1022E0000000000000894907000000000000001005 +:1022F00000221E2300000000000000000029488783 +:10230000000000000000001000221E21000000005C +:102310000000000000294847000000000000000005 +:1023200000311CA3000000000000001000221E2746 +:1023300000000000000000000029488700000000A5 +:102340000000000000311CA100000000000000108F +:1023500000221E270000000000000000002948475E +:10236000000000000000001000221E2300000000FA +:1023700000000000003120C4000000000000FFFF4A +:102380000028222800000000000000000029490762 +:10239000000000000000001000221E2100000000CC +:1023A00000000000003120C2000000000000FFFF1C +:1023B00000282228000000000000000000894907D2 +:1023C000000000000000001000221E23000000009A +:1023D0000000000000294887000000000000000104 +:1023E00000220A210000000000000000003308A2C3 +:1023F000000000000000001000221E22000000006B +:102400000000001000212222000000000000000057 +:1024100000294907000000000000000000311CA353 +:10242000000000000000001000221E270000000035 +:1024300000000000002948870000000000000001A3 +:1024400000220A210000000000000000003008A265 +:10245000000000000000001000221E22000000000A +:1024600000000010002122220000000000000000F7 +:1024700000294907000000000000001000221E2370 +:102480000000000000000000003120C40000000037 +:102490000000FFFF002822280000000000000000CC +:1024A000002949070000000000000000003808C5AE +:1024B00000000000000000000030084100000000A3 +:1024C0000000000100220A220000000000000000BD +:1024D000003308A2000000000000001000221E22AD +:1024E0000000000000000010002122220000000077 +:1024F00000000000008949070000000000000017EC +:102500000020222D000000000000000014C0000088 +:1025100000000318FFFFFFEF002806210000000065 +:10252000000000140020222D000000000000F8E050 +:1025300000204411000000000000000000294901B3 +:1025400000000000000000000089490100000000B8 +:102550000000000000204811000000000000000002 +:102560000020481100000000060A02000080481107 +:102570000000000000000000C0200000000000007B +:1025800097000000C020441100000000000000007F +:10259000C0204811000000008A0000000020441103 +:1025A00000000000000000000020481100000000B2 +:1025B0000000225C00204411000000000000000028 +:1025C000C0204800000000000000A1FC00204411D1 +:1025D0000000000000000000C020480000000000D3 +:1025E00000000000C0200400000000000000000007 +:1025F00000A0000A00000000970000000020441125 +:102600000000000000000000002048110000000051 +:102610008A000000002044110000000000000000BB +:1026200000204811000000000000225C002044113E +:102630000000000000000000C02048000000000072 +:102640000000A1FC00204411000000000000000078 +:10265000C02048000000000000000000C02004006E +:10266000000000000000000000A0000A00000000C0 +:10267000970000000020441100000000000000004E +:1026800000204811000000008A00000000204411D2 +:1026900000000000000000000020481100000000C1 +:1026A0000000225C00204411000000000000000037 +:1026B000C0204800000000000000A1FC00204411E0 +:1026C0000000000000000000C020480000000000E2 +:1026D0000001A1FD002044110000000000000000E6 +:1026E000D90048000000000000000000C0200400E5 +:1026F000000000000000000000A0000A0000000030 +:1027000000002257002044110000000000000003D8 +:10271000C0484A20000000000000225D0020441153 +:102720000000000000000000C04048000000000061 +:1027300000000000006000000000064200000000F1 +:10274000C0200800000000000000225C00204411AE +:10275000000000000000000300384A2200000000D2 +:102760000000A1FC00204411000000000000000057 +:10277000C0204800000000000001A1FD002044111D +:102780000000000000000000002F022200000000F6 +:10279000000000000CE0000000000000000000004D +:1027A00040204800000000000000000140304A20A6 +:1027B0000000000000000002C0304A2000000000BD +:1027C0000000000100530A220000034B0000003FFC +:1027D000C0280A20000000008100000000204411F1 +:1027E000000000000000000100204811000000006F +:1027F000000021F800204411000000000000001833 +:102800000020481100000000000421F9006044117C +:102810000000068A000000110021023000000000C4 +:102820000000000014E00000000003540000001449 +:10283000002F022200000000000000000CC0000079 +:10284000000003640000201000204411000000007C +:102850000000800000204811000000000001A2A438 +:102860000020441100000000000000000060480249 +:102870000000036E00002100002044110000000051 +:1028800000000000C0204800000000000000000020 +:10289000C02048000000000000000000C0204800E8 +:1028A0000000000000000000C040480000000000E0 +:1028B00000000004002F02220000000000000000C1 +:1028C0000CC000000000036A00002010002044112A +:1028D00000000000000080000020481100000000FF +:1028E0000001A2A40020441100000000000000002C +:1028F000004048020000035F00000028002F022271 +:1029000000000000000000000CC00000000005BD39 +:102910000001A2A4002044110000000000000000FB +:10292000004048020000035F0000002C0020362613 +:102930000000000000000049002018110000000005 +:102940000000003F002048110000000000000001CE +:1029500000331A260000000000000000002F0226AD +:1029600000000000000000000CC000000000037028 +:102970000000002C00801A2D000000000000003F25 +:10298000C0280A200000000000000015002F0222CD +:1029900000000000000000000CE0000000000386C2 +:1029A00000000006002F02220000000000000000CE +:1029B0000CE00000000003B100000016002F02220E +:1029C00000000000000000000CE00000000003B563 +:1029D00000000020002F0222000000000000000084 +:1029E0000CE000000000039C0000000F002F0222FA +:1029F00000000000000000000CE00000000003A840 +:102A000000000010002F0222000000000000000063 +:102A10000CE00000000003A80000001E002F0222AE +:102A200000000000000000000CE000000000039027 +:102A30000000A2A4002044110000000000000000DB +:102A400000404802000000000800000000290A229F +:102A5000000000000000000340210E2000000000E4 +:102A60000000000CC021122000000000000800003F +:102A7000002812240000000000000014C0221620CC +:102A80000000000000000000002914A40000000065 +:102A90000000A2A40020441100000000000000007B +:102AA000002948A2000000000000A1FE00204411FF +:102AB000000000000000000000404803000000008B +:102AC000810000000020441100000000000000010F +:102AD0000020481100000000000021F800204411EF +:102AE0000000000000000016002048110000000057 +:102AF000000421F9006044110000068A000000155E +:102B000000210230000000000000000014E000007E +:102B1000000003920000210E00204411000000007C +:102B200000000000C020480000000000000000007D +:102B3000C0204800000000000000A2A400204411B2 +:102B400000000000000000000040480200000000FB +:102B5000810000000020441100000000000000017E +:102B60000020481100000000000021F8002044115E +:102B700000000000000000170020481100000000C5 +:102B8000000421F9006044110000068A00000003DF +:102B900000210230000000000000000014E00000EE +:102BA0000000039E000021080020441100000000E6 +:102BB00000000000C02048000000000000000000ED +:102BC000C0204800000000000000A2A40020441122 +:102BD000000000000000000000404802000000006B +:102BE0000000A2A40020441100000000000000002A +:102BF0000020480200000000800000000020441176 +:102C0000000000000000000000204811000000004B +:102C100081000000002044110000000000000010AE +:102C200000204811000000000000000000200010FB +:102C3000000000000000000014C00000000003AE0F +:102C40000000000000400000000000000000201014 +:102C50000020441100000000000080000020481106 +:102C6000000000000001A2A40020441100000000A8 +:102C70000000000600404811000000000000201085 +:102C800000204411000000000000800000204811D6 +:102C9000000000000001A2A4002044110000000078 +:102CA00000000016006048110000036E00000000E4 +:102CB000004000000000000000000000C0200800EC +:102CC0000000000000000000C0200C000000000018 +:102CD0000000001D00210223000000000000000091 +:102CE00014E00000000003CE810000000020441129 +:102CF000000000000000000100204811000000005A +:102D0000000021F80020441100000000000000181D +:102D10000020481100000000000421F90060441167 +:102D20000000068A000000110021023000000000AF +:102D30000000000014E00000000003C000002100BB +:102D400000204411000000000000000000204802A4 +:102D50000000000000000000002048030000000008 +:102D6000BABECAFE0020481100000000CAFEBABE6A +:102D70000020481100000000000020100020441135 +:102D8000000000000000800000204811000000004A +:102D90000000A2A400204411000000000000000474 +:102DA0000040481100000000000021700020441184 +:102DB00000000000000000000020480200000000A9 +:102DC0000000000000204803000000008100000017 +:102DD00000204411000000000000000A00204811FB +:102DE00000000000000000000020001000000000B3 +:102DF0000000000014C00000000003D38C0000009D +:102E00000020441100000000CAFEBABE0040481174 +:102E100000000000810000000020441100000000BC +:102E200000000001002048110000000000003FFFEA +:102E300040280A20000000008000000040280E20EA +:102E40000000000040000000C02812200000000028 +:102E500000040000006946220000068A000000000D +:102E6000002014100000000000000000002F0223CA +:102E700000000000000000000CC00000000003E1A2 +:102E800000000000C0401800000003E400003FFF05 +:102E9000C0281A2000000000000400000069462637 +:102EA0000000068A0000000000201810000000004A +:102EB00000000000002F02240000000000000000BD +:102EC0000CC00000000003E700000000C0401C0030 +:102ED000000003EA00003FFFC0281E2000000000A1 +:102EE00000040000006946270000068A0000000078 +:102EF00000201C1000000000000000000020440220 +:102F00000000000000000000002820C500000000B4 +:102F100000000000004948E800000000A580000013 +:102F200000200811000000000000200000200C110B +:102F30000000000083000000006044110000041243 +:102F4000000000000020440200000000000000001B +:102F5000C0204800000000000000000040204800A1 +:102F6000000000000000001FC0210220000000003F +:102F70000000000014C00000000003F70000201053 +:102F800000204411000000000000800000204811D3 +:102F9000000000000000FFFFC0481220000003FFF7 +:102FA000A780000000200811000000000000A00021 +:102FB00000200C110000000083000000006044119C +:102FC0000000041200000000002044020000000085 +:102FD00000000000C02048000000000000000000C9 +:102FE000C0204800000000000000FFFFC0281220A1 +:102FF00000000000830000000020441100000000D9 +:103000000000000000304883000000008400000041 +:10301000002044110000000000000000C020480013 +:1030200000000000000000001D0000000000000083 +:103030008300000000604411000004120000000042 +:10304000C040040000000001A98000000020081119 +:10305000000000000000C00000400C11000003FA56 +:10306000AB80000000200811000000000000F8E024 +:1030700000400C11000003FAAD8000000020081190 +:10308000000000000000F88000400C11000003FA6E +:10309000B380000000200811000000000000F3FCD5 +:1030A00000400C11000003FAAF800000002008115E +:1030B000000000000000E00000400C11000003FAD6 +:1030C000B180000000200811000000000000F000A6 +:1030D00000400C11000003FA83000000002044119E +:1030E00000000000000021480020481100000000FE +:1030F00084000000002044110000000000000000D7 +:10310000C020480000000000000000001D0000007A +:10311000000000000000000000800000000000002F +:1031200001182000C0304620000000000000000010 +:10313000D90048000000000000000000C02004008A +:10314000000000000000000000A0000A00000000D5 +:103150000218A000C030462000000000000000005F +:10316000D90048000000000000000000C02004005A +:10317000000000000000000000A0000A00000000A5 +:103180000318C000C030462000000000000000000E +:10319000D90048000000000000000000C02004002A +:1031A000000000000000000000A0000A0000000075 +:1031B0000418F8E0C03046200000000000000000C5 +:1031C000D90048000000000000000000C0200400FA +:1031D000000000000000000000A0000A0000000045 +:1031E0000518F880C03046200000000000000000F4 +:1031F000D90048000000000000000000C0200400CA +:10320000000000000000000000A0000A0000000014 +:103210000618E000C030462000000000000000005A +:10322000D90048000000000000000000C020040099 +:10323000000000000000000000A0000A00000000E4 +:103240000718F000C0304620000000000000000019 +:10325000D90048000000000000000000C020040069 +:10326000000000000000000000A0000A00000000B4 +:103270000818F3FCC03046200000000000000000E9 +:10328000D90048000000000000000000C020040039 +:10329000000000000000000000A0000A0000000084 +:1032A0000000003000200A2D000000000000000097 +:1032B000C0290C4000000000000000300020362330 +:1032C0000000000000000000C0200400000000001A +:1032D0000000000000A0000A0000000086000000BE +:1032E00000204411000000000000000000404801E0 +:1032F0000000000085000000C02044110000000014 +:103300000000000000404801000000000000217C97 +:10331000002044110000000000000000C020480010 +:103320000000000000000000C02048000000000075 +:1033300000000000C02048000000000081000000E4 +:10334000002044110000000000000001002048118E +:103350000000000000000000C02008000000000085 +:103360000000000017000000000000000004217FA2 +:10337000006044110000068A0000001F0021023096 +:10338000000000000000000014C000000000000069 +:103390000000000000404C02000004480000000053 +:1033A000C0200C000000000000000000C020100041 +:1033B0000000000000000000C02014000000000019 +:1033C00000000000C0201800000000000000000005 +:1033D000C0201C000000000000007F0000280A211F +:1033E0000000000000004500002F02220000000045 +:1033F000000000000CE00000000004560000000087 +:10340000C0202000000000000000000017000000A5 +:10341000000000000000001000280A230000000047 +:1034200000000010002F0222000000000000000039 +:103430000CE000000000045E810000000020441148 +:103440000000000000000001002048110000000002 +:1034500000040000006946240000068A0000000005 +:1034600000400000000004638100000000204411BF +:1034700000000000000000000020481100000000D3 +:103480000000216D00204411000000000000000039 +:103490000020480400000000000000000060480513 +:1034A0000000068F00000000002824F0000000004B +:1034B0000000000700280A230000000000000001AF +:1034C000002F022200000000000000000AE00000BF +:1034D0000000046A00000000002F00C90000000086 +:1034E0000000000004E00000000004830000000071 +:1034F000004000000000049000000002002F0222A3 +:1035000000000000000000000AE000000000046F5E +:1035100000000000002F00C90000000000000000B3 +:1035200002E00000000004830000000000400000F2 +:103530000000049000000003002F022200000000A1 +:10354000000000000AE00000000004740000000019 +:10355000002F00C900000000000000000CE0000087 +:103560000000048300000000004000000000049000 +:1035700000000004002F02220000000000000000F4 +:103580000AE000000000047900000000002F00C9DC +:1035900000000000000000000AE0000000000483BA +:1035A0000000000000400000000004900000000542 +:1035B000002F022200000000000000000AE00000CE +:1035C0000000047E00000000002F00C90000000081 +:1035D0000000000006E0000000000483000000007E +:1035E000004000000000049000000006002F0222AE +:1035F00000000000000000000AE00000000004835A +:1036000000000000002F00C90000000000000000C2 +:1036100008E00000000004830000000000400000FB +:103620000000049000007F0000280A210000000034 +:1036300000004500002F02220000000000000000F2 +:103640000AE00000000000000000000800210A233A +:10365000000000000000000014C000000000048D05 +:10366000000021690020441100000000000000005B +:10367000C02048000000000000000000C0204800FA +:103680000000000000000000C02048000000000012 +:10369000CAFEBABE00404811000000000000000051 +:1036A000C02044000000000000000000C020000016 +:1036B0000000000000000000C040480000000000C2 +:1036C00000007F0000280A210000000000004500E3 +:1036D000002F022200000000000000000AE00000AD +:1036E0000000049600000000C02000000000000060 +:1036F00000000000C02000000000000000000000EA +:10370000C0400000000000000000000000404C0825 +:103710000000045600000000C02008000000000067 +:103720000000001040210E200000000000000011E9 +:10373000402112200000000000000012402116204D +:10374000000000000000216900204411000000007A +:1037500000000000002048020000000000000000FF +:1037600000210225000000000000000014E000001D +:10377000000004A000040000C0494A20000004A189 +:10378000FFFBFFFFC0284A200000000000000000EF +:1037900000210223000000000000000014E00000EF +:1037A000000004AD00000000C02048000000000040 +:1037B00000000000C02048000000000000000000E1 +:1037C00000210224000000000000000014C00000DE +:1037D00000000000810000000020441100000000F3 +:1037E0000000000C00204811000000000000000054 +:1037F00000200010000000000000000014C00000C5 +:10380000000004A9A00000000020441100000000F6 +:10381000CAFEBABE0040481100000000810000004E +:1038200000204411000000000000000400204811A6 +:10383000000000000000216B002044110000000087 +:1038400000000000C02048100000000081000000BF +:103850000020441100000000000000050020481175 +:10386000000000000000216C002044110000000056 +:1038700000000000C0204810000000000000000010 +:10388000002F022400000000000000000CE00000F7 +:10389000000000000000000000400000000004A73D +:1038A00000000000C0210A2000000000000000000D +:1038B00014C00000000004C081000000002044117A +:1038C000000000000000000000204811000000007F +:1038D0000000216D002044110000000000000000E5 +:1038E000C02048000000000000000000C060480048 +:1038F0000000068F0000000000400000000004C42B +:1039000081000000002044110000000000000001C0 +:10391000002048110000000000040000C0294620DB +:103920000000000000000000C06000000000068AE7 +:103930000000000100210222000000000000000041 +:1039400014C00000000004CB0000216900204411D5 +:103950000000000000000000C0204800000000003F +:1039600000000000C020480000000000000000002F +:103970000020481000000000CAFEBABE00404811F6 +:103980000000000000000000C02044000000000013 +:1039900000000000C040481000000000810000004E +:1039A0000020441100000000000000010020481128 +:1039B00000000000000021F8002044110000000079 +:1039C0000000000E0020481100000000000421F952 +:1039D000006044110000068A00000000002102304F +:1039E000000000000000000014C00000000004CD32 +:1039F00000002180002044110000000000000000B1 +:103A0000C02048000000000000000000C0200000AE +:103A10000000000000000000C0204800000000007E +:103A200000000000C02000000000000000000000B6 +:103A3000C0404800000000000000000300333E2F9B +:103A40000000000000000001002102210000000031 +:103A50000000000014E00000000004FD0000002C45 +:103A600000200A2D000000000004000018E00C11E6 +:103A7000000004EC0000000100333E2F00000000B5 +:103A80000000216900204411000000000000000037 +:103A90000020480200000000000000000020480351 +:103AA000000000000000000800300A2200000000B2 +:103AB00000000000C02048000000000000000000DE +:103AC000C0204800000000000000216900204411CF +:103AD000000000000000000000204802000000007C +:103AE0000000000000204803000000000000000863 +:103AF00000300A220000000000000000C020480042 +:103B00000000000000000000D8C04800000004E0F1 +:103B100000002169002044110000000000000000A6 +:103B200000204802000000000000000000204803C0 +:103B3000000000000000000800300A220000000021 +:103B400000000000C020480000000000000000004D +:103B5000C0204800000000000000002D0020122DB1 +:103B6000000000000000000000290C83000000009D +:103B70000000216900204411000000000000000046 +:103B80000020480200000000000000000020480360 +:103B9000000000000000000800300A2200000000C1 +:103BA00000000000C02048000000000000000000ED +:103BB000C020480000000000000000110021022485 +:103BC000000000000000000014C000000000000021 +:103BD0000000000000400000000004A70000002CCE +:103BE000C0203620000000000000002DC04036201C +:103BF000000000000000000F002102210000000072 +:103C00000000000014C000000000050200000000D9 +:103C1000006000000000000B00000000D900000060 +:103C20000000000000000000C0400400000000018F +:103C3000B50000000020441100000000000020003A +:103C40000020481100000000B600000000204411D0 +:103C5000000000000000A00000204811000000004B +:103C6000B700000000204411000000000000C00068 +:103C70000020481100000000B8000000002044119E +:103C8000000000000000F8E00020481100000000E3 +:103C9000B900000000204411000000000000F8807E +:103CA0000020481100000000BA000000002044116C +:103CB000000000000000E0000020481100000000AB +:103CC000BB00000000204411000000000000F000D4 +:103CD0000020481100000000BC000000002044113A +:103CE000000000000000F3FC00204811000000006C +:103CF00081000000002044110000000000000002CC +:103D00000020481100000000000000FF00280E30D5 +:103D10000000000000000000002F0223000000004F +:103D2000000000000CC000000000051600000000AC +:103D3000C0200800000000000000000014C00000C7 +:103D40000000052B0000000000200C110000000006 +:103D50000000001C00203623000000000000002BA3 +:103D60000020362300000000000000290020362338 +:103D700000000000000000280020362300000000A2 +:103D8000000000170020362300000000000000257E +:103D9000002036230000000000000026002036230B +:103DA0000000000000000015002036230000000085 +:103DB000000000160020362300000000FFFFE00096 +:103DC00000200C110000000000000021002036231C +:103DD0000000000000000022002036230000000048 +:103DE00000001FFF00200C11000000000000002355 +:103DF00000203623000000000000002400203623AD +:103E000000000000F1FFFFFF00283A2E0000000034 +:103E10000000001AC0220E20000000000000000078 +:103E20000029386E000000008100000000204411CD +:103E30000000000000000006002048110000000003 +:103E40000000002A4020362000000000870000000B +:103E5000002044110000000000000000C0204800C5 +:103E6000000000000000A1F4002044110000000048 +:103E700000000000002048100000000000000000CA +:103E800000200C110000000000000030002036234C +:103E9000000000009D000000002044110000000010 +:103EA0000000001F40214A20000000009600000092 +:103EB000002044110000000000000000C020480065 +:103EC0000000000000000000C0200C000000000006 +:103ED00000000000C0201000000000000000001FD3 +:103EE00000211624000000000000000014C00000A3 +:103EF000000000000000001D00203623000000002C +:103F00000000000300281E2300000000000000083D +:103F10000022222300000000FFFFF00000282228DA +:103F20000000000000000000002920E80000000060 +:103F30000000001F002036280000000000000018CC +:103F400000211E2300000000000000200020362772 +:103F50000000000000000002002216240000000003 +:103F600000000000003014A8000000000000001E47 +:103F700000203625000000000000000300211A2464 +:103F8000000000001000000000281A2600000000B9 +:103F9000EFFFFFFF00283A2E0000000000000000A5 +:103FA000004938CE000006780000000140280A20B1 +:103FB000000000000000000640280E200000000065 +:103FC00000000300C02812200000000000000008CC +:103FD000002112240000000000000000C020162074 +:103FE0000000000000000000C0201A2000000000B7 +:103FF000000000000021022200000000000000007C +:1040000014C000000000056381000000002044117E +:104010000000000000000001002048110000000026 +:104020000000225800300A240000000000040000B4 +:10403000006946220000068A000021690020441120 +:104040000000000000000000002048050000000003 +:104050000002000000294A260000000000000000C5 +:104060000020481000000000CAFEBABE002048111F +:104070000000000000000002002F022300000000EA +:10408000000000000CC000000000056B00000000F4 +:10409000C0201C100000000000000000C040000014 +:1040A0000000057900000002002F0223000000003C +:1040B000000000000CC000000000056B8100000043 +:1040C0000020441100000000000000010020481101 +:1040D000000000000000225800300A240000000008 +:1040E00000040000006946220000068A000000006B +:1040F000C0201C100000000000000000C0400000B4 +:104100000000057900000000002F022300000000DD +:10411000000000000CC000000000056F000000005F +:10412000C0201C000000000000000000C040000093 +:104130000000057900000004002F022300000000A9 +:10414000000000000CC000000000057781000000A6 +:104150000020441100000000000000000020481171 +:10416000000000000000216D00204411000000004C +:1041700000000000C0204800000000000000000017 +:10418000C06048000000068F0000000000401C10C6 +:104190000000057900000000C020000000000000C1 +:1041A00000000000C040000000000000000000000F +:1041B0000EE000000000057B000000000060000031 +:1041C000000005C600000000002F022400000000CF +:1041D000000000000CC000000000058C0000A2B729 +:1041E00000204411000000000000000000204807EB +:1041F00000000000810000000020441100000000C9 +:104200000000000100204811000000000004A2B6D8 +:10421000006044110000068A0000001A00212230CC +:104220000000000000000006002226300000000010 +:1042300000042004006044110000068A0000A2C4AB +:10424000002044110000000000000000003048E998 +:10425000000000000000000000E000000000058AEF +:104260000000A2D100204411000000000000000066 +:1042700000404808000000000000A2D100204411C6 +:10428000000000000000000100504A28000000006B +:1042900000000001002F02240000000000000000C8 +:1042A0000CC000000000059D0000A2BB00204411CE +:1042B000000000000000000000204807000000008F +:1042C00081000000002044110000000000000001F7 +:1042D00000204811000000000004A2BA0060441150 +:1042E0000000068A0000001A0021223000000000B1 +:1042F0000000000600222630000000000004200418 +:10430000006044110000068A0000A2C5002044118C +:104310000000000000000000003048E9000000003C +:104320000000000000E000000000059B0000A2D299 +:104330000020441100000000000000000040480878 +:10434000000000000000A2D2002044110000000084 +:104350000000000100504A28000000000000000298 +:10436000002F022400000000000000000CC000002C +:10437000000005AE0000A2BF0020441100000000B4 +:10438000000000000020480700000000810000003D +:10439000002044110000000000000001002048112E +:1043A000000000000004A2BE006044110000068A64 +:1043B0000000001A0021223000000000000000066A +:1043C0000022263000000000000420040060441198 +:1043D0000000068A0000A2C6002044110000000070 +:1043E00000000000003048E900000000000000006C +:1043F00000E00000000005AC0000A2D30020441142 +:10440000000000000000000000404808000000001C +:104410000000A2D3002044110000000000000001B1 +:1044200000504A28000000000000A2C300204411F0 +:10443000000000000000000000204807000000000D +:104440008100000000204411000000000000000175 +:1044500000204811000000000004A2C200604411C6 +:104460000000068A0000001A00212230000000002F +:104470000000000600222630000000000004200496 +:10448000006044110000068A0000A2C70020441109 +:104490000000000000000000003048E900000000BB +:1044A0000000000000E00000000005BB0000A2D4F6 +:1044B00000204411000000000000000000404808F7 +:1044C000000000000000A2D4002044110000000001 +:1044D0000000000100504A28000000008500000094 +:1044E00000204411000000000000000000204801EE +:1044F000000000000000304A0020441100000000CD +:104500000100000000204811000000000000000031 +:1045100000400000000005C1A4000000C0204411BC +:104520000000000000000000C04048000000000043 +:1045300000000000C0600000000005C60000000090 +:10454000C0400400000000010000002C00203621C3 +:104550000000000081000000002044110000000065 +:1045600000000006002048110000000000000000CC +:10457000002F023000000000000000000CC000000E +:10458000000005CD00000000002004110000000024 +:104590000000003000403621000005E0000000303F +:1045A0000020062D0000000000007E0000280621EB +:1045B0000000000000000000002F022100000000A9 +:1045C000000000000CE00000000005E08100000099 +:1045D00000204411000000000000000100204811EC +:1045E000000000000004A092006044110000068A50 +:1045F0000000003100203630000000000004A093CD +:10460000006044110000068A0000003200203630AD +:10461000000000000004A2B6006044110000068AF9 +:104620000000003300203630000000000004A2BA71 +:10463000006044110000068A00000034002036307B +:10464000000000000004A2BE006044110000068AC1 +:104650000000003500203630000000000004A2C237 +:10466000006044110000068A000000360020363049 +:104670000000000000042004006044110000068ACD +:104680000001A2A400204411000000000000003F2F +:1046900000204811000000000000003F00204811E9 +:1046A000000000000000003F002048110000000052 +:1046B0000000003F0020481100000000000000053D +:1046C00000204811000000000000A1F40020441167 +:1046D0000000000000000000002048110000000061 +:1046E00088000000002044110000000000000001CC +:1046F000002048110000000081000000002044114B +:10470000000000000000000600204811000000002A +:1047100000000001002F0230000000000000000037 +:104720000CE0000000000629000000300020062DEB +:104730000000000000000000002F02210000000027 +:10474000000000000CE000000000062981000000CD +:10475000002044110000000000000001002048116A +:104760000000000000007E0000280621000000007C +:1047700000000000002F02210000000000000000E7 +:104780000CE00000000006020000A092002044118E +:10479000000000000000003100204A2D0000000051 +:1047A0000000A0930020441100000000000000322F +:1047B00000204A2D000000000000A2B60020441195 +:1047C000000000000000003300204A2D000000001F +:1047D0000000A2BA002044110000000000000034D4 +:1047E00000204A2D000000000000A2BE002044115D +:1047F000000000000000003500204A2D00000000ED +:104800000000A2C200204411000000000000003699 +:1048100000204A2D00000000000000300020062D7E +:1048200000000000000001FF002806210000000039 +:1048300000000000002F0221000000000000000026 +:104840000CE000000000062800000000002102210A +:10485000000000000000000014C000000000060B73 +:104860000004A003006044110000068A0000A003B9 +:10487000002044110000000000000000002048104B +:1048800000000000000000010021062100000000DF +:104890000000000014C00000000006100004A0107A +:1048A000006044110000068A0000A010002044119E +:1048B0000000000000000000002048100000000080 +:1048C000000000010021062100000000000000009F +:1048D000002F022100000000000000000CE000009A +:1048E000000006280004A011006044110000068AA0 +:1048F0000000A01100204411000000000000000092 +:1049000000204810000000000004A01200604411C4 +:104910000000068A0000A0120020441100000000E0 +:104920000000000000204810000000000004A01358 +:10493000006044110000068A0000A013002044110A +:1049400000000000000000000020481000000000EF +:104950000004A014006044110000068A0000A014A6 +:10496000002044110000000000000000002048105A +:10497000000000000004A015006044110000068A39 +:104980000000A015002044110000000000000000FD +:1049900000204810000000000004A0160060441130 +:1049A0000000068A0000A01600204411000000004C +:1049B0000000000000204810000000000004A017C4 +:1049C000006044110000068A0000A0170020441176 +:1049D000000000000000000000204810000000005F +:1049E00000042004006044110000068A0000002C2E +:1049F0000080062D00000000FF0000000020441190 +:104A0000000000000000000000204811000000002D +:104A1000000000010020481100000000000000021A +:104A20000080481100000000000000000EE00000BF +:104A30000000063A000000300020062D00000000B3 +:104A40000000000200280621000000000000000015 +:104A5000002F022100000000000000000CE0000018 +:104A60000000063881000000002044110000000012 +:104A70000000000100204811000000000004200494 +:104A8000006044110000068A000010000020081198 +:104A9000000000000000002B002036220000000073 +:104AA00000000000006000000000063E0000000062 +:104AB00000600000000005C69800000000204411BE +:104AC000000000000000000000804811000000000D +:104AD00000000000C06000000000063E0000000072 +:104AE000C0400400000000010000A2A40020441106 +:104AF000000000000000002200204811000000001B +:104B000089000000002044110000000000000001A6 +:104B1000004048110000062A9700000000204411C0 +:104B2000000000000000000000204811000000000C +:104B30008A00000000204411000000000000000076 +:104B4000004048110000062A00000000006000003C +:104B50000000065900002010002044110000000051 +:104B60000000800000204811000000000001A2A405 +:104B7000C020441100000000000000160060481131 +:104B80000000036E0000201000204411000000000F +:104B9000000100000020481100000000810000001A +:104BA0000020441100000000000000010020481116 +:104BB000000000000000217C0020441100000000E3 +:104BC000098000000020481100000000FFFFFFFFE7 +:104BD00000204811000000000000000000204811E3 +:104BE00000000000000000001700000000000000AE +:104BF0000004217F006044110000068A0000001FAD +:104C000000210230000000000000000014C000007D +:104C1000000000000000000400404C11000006539A +:104C2000000000000040000000000000000000172D +:104C300000201E2D000000000000000400291E2797 +:104C40000000000000000017008036270000000070 +:104C50000000001700201E2D00000000FFFFFFFBDA +:104C600000281E27000000000000001700803627E3 +:104C7000000000000000001700201E2D00000000B2 +:104C80000000000800291E27000000000000001797 +:104C900000803627000000000000001700201E2DB5 +:104CA00000000000FFFFFFF700281E2700000000A3 +:104CB00000000017008036270000000000002010D0 +:104CC0000020441100000000000080000020481176 +:104CD000000000000001A2A4002044110000000018 +:104CE00000000016006048110000036E0000201054 +:104CF00000204411000000000001000000204811C5 +:104D0000000000000000217C002044110000000091 +:104D1000018000000020481100000000FFFFFFFF9D +:104D20000020481100000000000000000020481191 +:104D3000000000000000000017000000000000005C +:104D4000810000000020441100000000000000016C +:104D500000204811000000000004217F0060441181 +:104D60000000068A0000001F002102300000000041 +:104D70000000000014C000000000068900000010C0 +:104D800000404C110000066F00000000C02004002D +:104D9000000000000000000038C00000000000001B +:104DA0000000001D00200A2D000000000000001E71 +:104DB00000200E2D000000000000001F0020122D1A +:104DC00000000000000000200020162D0000000060 +:104DD00000002169002044110000000000000000D4 +:104DE00000204804000000000000000000204805EA +:104DF000000000000000000000204801000000004A +:104E0000CAFEBABE002048110000000000000004E5 +:104E1000003012240000000000000000002F006499 +:104E200000000000000000000CC000000000068828 +:104E30000000000300281A22000000000000000803 +:104E40000022122200000000FFFFF00000281224C0 +:104E50000000000000000000002910C40000000055 +:104E60000000001F00403624000000000000000089 +:104E70000080000000000000000000001AC00000D8 +:104E80000000068A9F00000000204411000000007E +:104E9000CAFEBABE00204811000000000000000059 +:104EA0001AE000000000068D0000000000800000F5 +:104EB00000000000000000001AC000000000068F83 +:104EC0009E0000000020441100000000CAFEBABE8F +:104ED0000020481100000000000000001AE000005F +:104EE00000000692000000000080000000000000AA +:104EF00000000000006000000000000B0000100037 +:104F000000600411000003150000000000200411DF +:104F1000000000000000000000600811000001B265 +:104F20000000225C0020441100000000000000038B +:104F3000002048110000000000002256002044110B +:104F4000000000000000001B0020481100000000CD +:104F50000000A1FC0020441100000000000000013E +:104F600000204811000000000001A1FDC0204411F4 +:104F7000000000000000002100201E2D00000000A5 +:104F80000000001000221E27000000000000002486 +:104F90000020222D000000000000FFFF0028222832 +:104FA0000000000000000000002949070000000088 +:104FB0000000000000204811000000000000002256 +:104FC0000020222D000000000000FFFF0028222802 +:104FD0000000000000000000002949070000000058 +:104FE0000000000000204811000000000000002325 +:104FF00000201E2D000000000000001000221E27CF +:105000000000000000000000002949070000000027 +:1050100000000000004048110000000000000000F7 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B000014204FF05BD02500000000001C3016867 +:1052C000043F05BD00000000022502090250015103 +:1052D000000000000223024502A00241000000007D +:1052E00003D705BD05BD05BD000000000646064705 +:1052F000031F05BD0000000005BD05C203200340DB +:1053000000000000032A0282034203340000000070 +:1053100005BD05BD05BD05BD0000000005BD054E70 +:1053200005BD05BD0000000003BA05BD04B8034477 +:10533000000000000497044D043D05BD000000007E +:1053400004CD05BD044104DA00000000044D05044D +:10535000035103750000000005BD05BD05BD05BD79 +:105360000000000005BD05BD05BD05BD0000000035 +:1053700005BD05BD063C05C40000000005BD05BD1A +:10538000000705BD0000000005BD05BD05BD05BD4C +:105390000000000005BD05BD05BD05BD0000000005 +:1053A00003F803ED0408040600000000040E040ADC +:1053B000040C041000000000041C04180424042041 +:1053C00000000000042C0428043404300000000015 +:1053D00005BD05BD043805BD0000000005BD05BDC7 +:1053E00005BD05BD0000000005BD05BD05BD05BD31 +:1053F000000000000002067606940006000000008F +:00000001FF diff --git a/firmware/radeon/RV630_pfp.bin.ihex b/firmware/radeon/RV630_pfp.bin.ihex new file mode 100644 index 000000000000..f55292c97b79 --- /dev/null +++ b/firmware/radeon/RV630_pfp.bin.ihex @@ -0,0 +1,145 @@ +:1000000000CA040000A00000007E828B007C038BED +:10001000008001B8007C038B00D4401E00EE001E5F +:1000200000CA040000A00000007E828B00C41838C3 +:1000300000CA240000CA2800009581A800C41C3A08 +:1000400000C3C00000CA080000CA0C00007C744B4A +:1000500000C200050099C00000C41C3A007C744C2A +:1000600000C0FFF000042C0400309002007D250049 +:1000700000351402007D350B00255403007CD5802B +:1000800000259C030095C00400D5001B007EDDC147 +:10009000007D9D8000D6801B00D5801B00D4401EB3 +:1000A00000D5401E00D6401E00D6801E00D4801E03 +:1000B00000D4C01E009783D300D5C01E00CA08001C +:1000C0000080001A00CA0C0000E4011E00D4001ECB +:1000D0000080000C00C4183800E4013E00D4001E6B +:1000E0000080000C00C4183800D4401E00EE001E32 +:1000F00000CA040000A00000007E828B00E4011E04 +:1001000000D4001E00D4401E00EE001E00CA0400F1 +:1001100000A00000007E828B00E4013E00D4001E9F +:1001200000D4401E00EE001E00CA040000A0000023 +:10013000007E828B00CA180000D4401E00D5801EAD +:100140000080005300D4007500D4401E00CA08008F +:1001500000CA0C0000CA100000D4801900D4C018D6 +:1001600000D5001700D4801E00D4C01E00D5001E8C +:1001700000E2001E00CA040000A00000007E828B86 +:1001800000CA080000D4806000D4401E0080000037 +:1001900000D4801E00CA080000D4806100D4401E34 +:1001A0000080000000D4801E00CA080000CA0C00B5 +:1001B00000D4401E00D4801600D4C01600D4801E87 +:1001C000008001B800D4C01E00C6084300CA0C005D +:1001D00000CA10000094800400CA140000E420F358 +:1001E00000D4201300D5606500D4E01C00D5201C8D +:1001F00000D5601C008000000006200100C60843F6 +:1002000000CA0C0000CA1000009483F700CA140052 +:1002100000E420F30080007900D4201300C60843D6 +:1002200000CA0C0000CA1000009883EF00CA140036 +:1002300000D400640080008D0000000000C414326F +:1002400000C6184300C4082F0095400500C40C30B8 +:1002500000D4401E0080000000EE001E009583F5D3 +:1002600000C4103100D4403300D5206500D4A01C58 +:1002700000D4E01C00D5201C00E4015E00D4001E68 +:10028000008000000006200100CA1800000A2001BA +:1002900000D6007600C408360098800700C61045D6 +:1002A0000095011000D4001F00D46062008000009F +:1002B00000D4206200CC383500CC1433008401BB5C +:1002C00000D4007200D5401E0080000000EE001E29 +:1002D00000E2001A008401BB00E2001A00CC104BBF +:1002E00000CC0447002C9401007D098B0098400548 +:1002F000007D15CB00D4001A008001B800D4006D39 +:100300000034440100CC0C480098403A00CC2C4A00 +:100310000095800400CC0449008001B800D4001A84 +:1003200000D4C01A00282801008400F000CC10037B +:100330000098801B0004380C008400F000CC1003EF +:100340000098801700043808008400F000CC1003E7 +:100350000098801300043804008400F000CC1003DF +:100360000098801400CC104C009A800900CC144DE9 +:10037000009840DC00D4006D00CC184800D5001A6D +:1003800000D5401A008000C900D5801A0096C0D55B +:1003900000D4006D008001B800D4006E009AC00344 +:1003A00000D4006D00D4006E0080000000EC007FDF +:1003B000009AC0CC00D4006D008001B800D4006E5B +:1003C00000CC140300CC180300CC1C03007D910367 +:1003D000007DD583007D190C0035CC1F0035701FC2 +:1003E000007CF0CB007CD08B00880000007E8E8BE0 +:1003F0000095C00400D4006E008001B800D4001A3B +:1004000000D4C01A00CC080300CC0C0300CC1003AD +:1004100000CC140300CC180300CC1C0300CC240334 +:1004200000CC28030035C41F0036B01F007C704B81 +:100430000034F01F007C704B0035701F007C704B47 +:10044000007D8881007DCCC1007E5101007E9541F8 +:10045000007C9082007CD4C2007C848B009AC00314 +:10046000007C8C8B002C88010098809E00D4006D4D +:100470000098409C00D4006E00CC084C00CC0C4D81 +:1004800000CC104800D4801A00D4C01A00800101AA +:1004900000D5001A00CC083200D40032009482D972 +:1004A00000CA0C0000D4401E0080000000D4001ED2 +:1004B00000E4011E00D4001E00CA080000CA0C009F +:1004C00000CA100000D4401E00CA140000D4801ED0 +:1004D00000D4C01E00D5001E00D5401E00D54034FB +:1004E0000080000000EE001E0028040400E2001A54 +:1004F00000E2001A00D4401A00CA380000CC0803F9 +:1005000000CC0C0300CC0C0300CC0C03009882BD83 +:1005100000000000008401BB00D7A06F0080000035 +:1005200000EE001F00CA040000C2FF0000CC083427 +:1005300000C13FFF007C74CB007CC90B007D010F24 +:10054000009902B0007C738B008401BB00D7A06FC0 +:100550000080000000EE001F00CA080000281900FB +:10056000007D898B009580140028140400CA0C00BB +:1005700000CA100000CA1C0000CA240000E2001FCC +:1005800000D4C01A00D5001A00D5401A00CC1803B8 +:1005900000CC2C0300CC2C0300CC2C03007DA58BBD +:1005A000007D9C4700984297000000000080016198 +:1005B00000D4C01A00D4401E00D4801E0080000069 +:1005C00000EE001E00E4011E00D4001E00D4401EF8 +:1005D00000EE001E00CA040000A00000007E828B16 +:1005E00000E4013E00D4001E00D4401E00EE001EB8 +:1005F00000CA040000A00000007E828B00CA080030 +:1006000000248C06000CCC060098C00600CC104ECE +:100610000099000400D4007300E4011E00D4001E01 +:1006200000D4401E00D4801E0080000000EE001E9A +:1006300000CA080000CA0C000034D01800251001C0 +:100640000095002100C17FFF00CA100000CA1400FD +:1006500000CA180000D4801D00D4C01D007DB18BDD +:1006600000C1420200C2C00100D5801D0034DC0E72 +:10067000007D5D4C007F734C00D7401E00D5001EEE +:1006800000D5401E00C1420000C2C00000099C010C +:100690000031DC10007F5F4C007F734C00042802A7 +:1006A000007D838000D5A86F00D5806600D7401EEE +:1006B00000EC005E00C8240200C82402008001B8DB +:1006C00000D6007600D4401E00D4801E00D4C01E88 +:1006D0000080000000EE001E0080000000EE001F01 +:1006E00000D4001F0080000000D4001F00D4001FB1 +:1006F0000088000000D4001F00000000000000007F +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000010171000201780003008F0004007FE5 +:10081000000500030006003F000700320008012C1D +:1008200000090046000A0036001001B6001700A2B9 +:100830000022013A00230149002000B400240125D0 +:100840000027004D0028006A002A0060002B00529B +:10085000002F0065003200870034017F003C015604 +:10086000003F00720041018C0044012E00550173CD +:100870000056017A0060000B00610034006200380D +:1008800000630038006400380065003800660038F6 +:10089000006700380068003A00690041006A0048BB +:1008A000006B0048006C0048006D0048006E004876 +:1008B000006F00480000000600000006000000066F +:1008C0000000000600000006000000060000000610 +:1008D0000000000600000006000000060000000600 +:1008E00000000006000000060000000600000006F0 +:1008F00000000006000000060000000600000006E0 +:00000001FF diff --git a/firmware/radeon/RV635_me.bin.ihex b/firmware/radeon/RV635_me.bin.ihex new file mode 100644 index 000000000000..ba3a7e632d97 --- /dev/null +++ b/firmware/radeon/RV635_me.bin.ihex @@ -0,0 +1,1345 @@ +:1000000000000000C020040000000000000000000C +:1000100000A0000A000000000000FFFF00284621A9 +:100020000000000000000000D900480000000000AF +:1000300000000000C02004000000000000000000DC +:1000400000A0000A000000000000000000E0000026 +:100050000000000000010000C02946200000000050 +:1000600000000000D900480000000000000000006F +:10007000C0200400000000000000000000A0000AF2 +:10008000000000008100000000204411000000007A +:1000900000000001002048110000000000042004BE +:1000A000006044110000068A0000000000600000AB +:1000B0000000062E00000000006000000000064264 +:1000C00000000000C02008000000000000000F0039 +:1000D000002816220000000000000008002116255C +:1000E000000000000000001800203625000000007D +:1000F0008D000000002044110000000000000004FA +:10010000002F022500000000000000000CE00000AD +:1001100000000018004120000040481100000019B4 +:100120000042200000204811000000008E00000066 +:1001300000204411000000000000002800204A2D8B +:1001400000000000900000000020441100000000AA +:100150000000000000204805000000000000000C26 +:1001600000211622000000000000000300281625D0 +:10017000000000000000001900211A220000000009 +:100180000000000400281A26000000000000000003 +:10019000002914C5000000000000001900203625C9 +:1001A0000000000000000000003A140200000000FF +:1001B00000000016002116250000000000000003CA +:1001C00000281625000000000000001700200E2D5A +:1001D00000000000FFFFFFFC00280E2300000000CD +:1001E00000000000002914A3000000000000001718 +:1001F00000203625000000000000800000280E22AC +:10020000000000000000000700220E230000000094 +:10021000000000000029386E0000000020000000EF +:1002200000280E22000000000000000600210E231E +:1002300000000000000000000029386E00000000EF +:100240000000000000220222000000000000000068 +:1002500014E0000000000038000000002EE0000064 +:1002600000000035000000002CE000000000003716 +:100270000000000000400E2D0000003900000008C2 +:1002800000200E2D00000000000000090040122D8B +:10029000000000460000000100400E2D0000003963 +:1002A00000000000C0200C0000000000003FFFFC28 +:1002B0000028122300000000000000020022122487 +:1002C000000000000000001F00211E2300000000AD +:1002D0000000000014E000000000003E00000008E4 +:1002E00000401C11000000410000000D00201E2DE8 +:1002F000000000000000000F00281E270000000082 +:100300000000000300221E27000000007FC0000044 +:1003100000281A23000000000000001400211A2603 +:10032000000000000000000100331A260000000059 +:100330000000000800221A26000000000000000053 +:1003400000290CC700000000000000270020362410 +:100350000000000000007F000028122100000000C3 +:1003600000001400002F0224000000000000000024 +:100370000CE000000000004B0000000100290E23EB +:10038000000000000000000E0020362300000000E6 +:100390000000E0000020441100000000FFF8000011 +:1003A00000294A230000000000000000003A2C024F +:1003B000000000000000000200220E2B00000000E0 +:1003C000FC00000000280E23000000000000000FC9 +:1003D000002036230000000000001FFF00294A23F0 +:1003E000000000000000002700204A2D000000004F +:1003F000000000000020481100000000000000295B +:1004000000200E2D00000000060A020000294A23E9 +:100410000000000000000000002048110000000063 +:100420000000000000204811000000000000000152 +:1004300000210222000000000000000014E0000083 +:1004400000000061000000002EE000000000005FDE +:10045000000000002CE000000000005E0000000032 +:1004600000400E2D000000620000000100400E2D33 +:10047000000000620000000A00200E2D00000000B5 +:100480000000000B0040122D0000006A0000000078 +:10049000C0200C0000000000003FFFFC00281223D9 +:1004A00000000000000000020022122400000000F2 +:1004B0007FC0000000281623000000000000001488 +:1004C0000021162500000000000000010033162561 +:1004D000000000008000000000280E230000000043 +:1004E0000000000000290CA3000000003FFFFC00FA +:1004F00000290E23000000000000001F00211E2321 +:10050000000000000000000014E000000000006D8A +:100510000000010000401C11000000700000000DF0 +:1005200000201E2D00000000000000F000281E2703 +:10053000000000000000000400221E270000000050 +:100540008100000000204411000000000000000DA8 +:100550000020481100000000FFFFF0FF00281A30C3 +:10056000000000000000A02800204411000000004E +:1005700000000000002948E6000000000000A0186C +:1005800000204411000000003FFFFFFF00284A2325 +:10059000000000000000A010002044110000000036 +:1005A00000000000002048040000000000000030AF +:1005B0000020162D00000000000000020029162572 +:1005C0000000000000000030002036250000000080 +:1005D000000000250020162D000000000000000093 +:1005E000002F00A300000000000000000CC000006D +:1005F00000000083000000260020162D00000000EF +:1006000000000000002F00A4000000000000000017 +:100610000CC000000000008400000000004000004A +:100620000000008A000000250020362300000000A2 +:100630000000002600203624000000000000001703 +:1006400000201E2D000000000000000200210227F3 +:10065000000000000000000014E000000000008A1C +:1006600000000000006000000000066500000000BF +:1006700000600000000006590000000200210E2268 +:10068000000000000000000014C000000000008D09 +:1006900000000012C040362000000093000000005F +:1006A0002EE0000000000091000000002CE000009F +:1006B000000000900000000200400E2D000000929B +:1006C0000000000300400E2D000000920000000C0E +:1006D00000200E2D00000000000000120020362334 +:1006E000000000000000000300210E2200000000B6 +:1006F0000000000014C00000000000980000A00CE2 +:10070000002044110000000000000000C02048004C +:100710000000000000000000C0404800000000A0F1 +:100720000000A00C002044110000000000000000A8 +:100730000020481100000000000000002EE0000032 +:100740000000009E000000002CE000000000009D62 +:100750000000000200400E2D0000009F000000037A +:1007600000400E2D0000009F0000000C00200E2D08 +:10077000000000000000000000204803000000000E +:1007800000000000003A0C0200000000003F0000E2 +:1007900000280E23000000000000001000210E239E +:1007A00000000000000000110020362300000000BF +:1007B0000000001E0021022B0000000000000000CD +:1007C00014C00000000000A700000016C020362062 +:1007D000000000000000001F0021022B00000000AC +:1007E0000000000014C00000000000AA0000001576 +:1007F000C0203620000000000000000800210E2B61 +:10080000000000000000007F00280E230000000010 +:1008100000000000002F0223000000000000000084 +:100820000CE00000000000E10000000027000000D4 +:10083000000000000000000000600000000002A3B3 +:1008400000000001002F0223000000000000000053 +:100850000AE00000000000B300000000006000009B +:100860000000013A81000000002044110000000057 +:100870000000000600204811000000000000000CED +:1008800000221E300000000099800000002044116A +:1008900000000000000000040020122D00000000F5 +:1008A00000000008002212240000000000000010D8 +:1008B00000201811000000000000000000291CE4C6 +:1008C0000000000000000000006048070000012F49 +:1008D0009B00000000204411000000000000000008 +:1008E00000204802000000009C000000002044118D +:1008F00000000000000000000033146F0000000042 +:100900000000000100333E23000000000000000052 +:10091000D9004800000000000000000000203C0555 +:1009200000000000810000000020441100000000D1 +:100930000000000E00204811000000000000000030 +:1009400000201010000000000000E007002044110B +:10095000000000000000000F0021022B000000003A +:100960000000000014C00000000000CB00F8FF08E9 +:1009700000204811000000009800000000404811CD +:10098000000000DC000000F000280E220000000043 +:10099000000000A0002F0223000000000000000063 +:1009A0000CC00000000000DA0000001100200E2D35 +:1009B0000000000000000001002F022300000000E2 +:1009C000000000000CE00000000000D50000000264 +:1009D000002F022300000000000000000CE00000D7 +:1009E000000000D400003F0000400C11000000D6C1 +:1009F00000001F0000400C11000000D600000F0096 +:100A000000200C11000000000038000900294A23D2 +:100A1000000000003F00000000280E2B0000000036 +:100A20000000000200220E2300000000000000076A +:100A300000494A23000000DC00380F09002048115B +:100A400000000000680000070020481100000000BE +:100A50000000000800214A270000000000000000FC +:100A60000020481100000000060A020000294A2464 +:100A700000000000000000000020481100000000FD +:100A80000000000000204811000000000000A20249 +:100A9000002044110000000000FF000000280E228A +:100AA000000000000000008000294A230000000030 +:100AB0000000002700200E2D00000000000000268E +:100AC0000020122D0000000000000000002F008315 +:100AD00000000000000000000CE00000000000EA40 +:100AE00000000000006000000000065F0000000041 +:100AF00000400000000000EB00000000006000006B +:100B000000000662000000070020222D0000000007 +:100B10000000000500220E2200000000001000006E +:100B200000280E23000000000000000000292068BB +:100B30000000000000000000003A0C02000000006D +:100B4000000000EF00280E2300000000000000005D +:100B500000292068000000000000001700200E2D72 +:100B6000000000000000000300210223000000003C +:100B70000000000014E00000000000F80000000B7E +:100B800000210228000000000000000014C0000046 +:100B9000000000F8000004000029222800000000E6 +:100BA0000000001400203628000000000000001C97 +:100BB00000210E22000000000000000014C0000010 +:100BC000000000FD0000A30C002044110000000004 +:100BD0000000000000204811000000000000001E7E +:100BE00000210E22000000000000000014C00000E0 +:100BF0000000010B0000A30F0020441100000000C2 +:100C00000000001100200E2D000000000000000177 +:100C1000002F022300000000000000000CC00000B4 +:100C200000000104FFFFFFFF004048110000010B1E +:100C300000000002002F022300000000000000005E +:100C40000CC00000000001070000FFFF0040481139 +:100C50000000010B00000004002F02230000000030 +:100C6000000000000CC000000000010A000000FFAE +:100C7000004048110000010B000000010020481155 +:100C8000000000000002C400002044110000000029 +:100C90000000001F00210E220000000000000000E4 +:100CA00014C00000000001120000001040210E20BE +:100CB00000000000000000130020362300000000A8 +:100CC0000000001840224A20000000000000001030 +:100CD000C0424A20000001140000000000200C1156 +:100CE0000000000000000013002036230000000078 +:100CF000000000000020481100000000000000007B +:100D000000204811000000000000000A002010111F +:100D10000000000000000000002F0224000000007E +:100D2000000000000CE000000000011B00000000BB +:100D300000204811000000000000000100531224B0 +:100D400000000117FFBFFFFF00283A2E000000003F +:100D50000000001B00210222000000000000000033 +:100D600014C000000000012E81000000002044118A +:100D7000000000000000000D0020481100000000ED +:100D80000000001800220E3000000000FC000000EF +:100D900000280E2300000000810000000020441104 +:100DA000000000000000000E0020481100000000BC +:100DB0000000000000201010000000000000E00E05 +:100DC000002044110000000007F8FF08002048112F +:100DD000000000000000000000294A23000000007D +:100DE0000000001C00201E2D000000000000000874 +:100DF00000214A27000000000000000000204811E8 +:100E000000000000060A020000294A240000000039 +:100E10000000000000204811000000000000000059 +:100E200000204811000000000000000000800000C9 +:100E300000000000810000000020441100000000BC +:100E40000000000100204811000000000000217C8B +:100E50000020441100000000008000000020481124 +:100E60000000000000000000002048060000000014 +:100E70000000000800214A270000000000000000D8 +:100E800017000000000000000004217F00604411F2 +:100E90000000068A0000001F002102300000000050 +:100EA0000000000014C000000000068900000004DB +:100EB00000404C1100000135810000000020441169 +:100EC00000000000000000010020481100000000A8 +:100ED000000021F800204411000000000000001C68 +:100EE0000020481100000000000421F900604411B6 +:100EF0000000068A000000110021023000000000FE +:100F00000000000014E000000000013C00000000B0 +:100F100000800000000000000000000000600000F1 +:100F20000000000B00000000006004110000031529 +:100F3000000000000020041100000000000000007C +:100F400000600811000001B2000000000060000015 +:100F5000000001600000FFFF40280E20000000009C +:100F600000000010C0211220000000000000FFFF60 +:100F7000402806200000000000000010C0210A20C8 +:100F800000000000000000000034146100000000B8 +:100F90000000000000741882000002BB0001A1FDE7 +:100FA00000604411000002E000003FFF002F022F0C +:100FB00000000000000000000CC00000000001471D +:100FC00000000000C040040000000001000000001C +:100FD000006000000000000B000000000060041131 +:100FE00000000315000000000020041100000000B4 +:100FF0000000000000600811000001B200003FFF87 +:10100000002F022F00000000000000000CE0000094 +:10101000000000000000000000600000000001600F +:101020000000001040210E20000000000000FFFF23 +:10103000C0281220000000000000001040211620EF +:10104000000000000000FFFFC0681A20000002BB83 +:101050000001A1FD00604411000002E000003FFF1C +:10106000002F022F00000000000000000CC0000054 +:101070000000015800000000C04004000000000112 +:101080000000225C0020441100000000000000016C +:1010900000300A2F000000000000000100210A2299 +:1010A000000000000000000300384A220000000099 +:1010B0000000225600204411000000000000001A29 +:1010C00000204811000000000000A1FC0020441195 +:1010D0000000000000000001008048110000000036 +:1010E00000000000006000000000000B0000000095 +:1010F000006000000000018F0000000000600000A0 +:10110000000001A000003FFF002F022F00000000A0 +:10111000000000000CE000000000000000000000E3 +:1011200000202C0800000000000000000020241116 +:101130000000000000000000002028110000000056 +:10114000000022560020441100000000000000169C +:1011500000204811000000000000225C0020441123 +:101160000000000000000003002048110000000003 +:1011700093800000002044110000000000000002E5 +:1011800000221E290000000000000000007048EB53 +:101190000000019C0000000000600000000002BB95 +:1011A00000000001403306200000000000000000A5 +:1011B000C03024090000000000003FFF002F022F74 +:1011C00000000000000000000CE000000000000033 +:1011D0000000000000600000000002A3000000000A +:1011E000002F022100000000000000000AE00000C3 +:1011F0000000018100000000006000000000013AD2 +:101200000000000000400000000001869500000082 +:10121000002044110000000000000000002F022107 +:1012200000000000000000000CE00000000001864B +:1012300000000000C0204800000000000000000185 +:10124000005306210000018292000000002044119A +:101250000000000000000000C0604800000001978E +:101260000001A1FD00204411000000000000001159 +:101270000020062D00000000000000000078042A75 +:10128000000002FB00000000002028090000000010 +:1012900000003FFF002F022F0000000000000000B0 +:1012A0000CC000000000017400000000C0400400F9 +:1012B000000000010000021000600411000003158E +:1012C00000003FFF002F022F000000000000000080 +:1012D0000CE000000000019400000015C020362042 +:1012E0000000000000000016C020362000000000B2 +:1012F0003F800000002004110000000046000000B4 +:1013000000600811000001B2000000000080000031 +:10131000000000000000A1FC0020441100000000BB +:1013200000003FFF002F022F00000000000000001F +:101330000CC000000000019B00000001008048116B +:1013400000000000000000210080481100000000A3 +:101350000000FFFF40280E200000000000000010E9 +:10136000C0211220000000000000FFFF40281620CE +:101370000000000000000010C0811A2000000000E2 +:101380008100000000204411000000000000000661 +:1013900000204811000000000000000800221E305C +:1013A000000000000000002900201A2D00000000AD +:1013B0000000E0000020441100000000FFFBFF09D6 +:1013C00000204811000000000000000F0020222D26 +:1013D0000000000000001FFF00294A280000000054 +:1013E000000000060020222D000000000000000088 +:1013F000002920E80000000000000000002048084C +:101400000000000000000000002048110000000063 +:10141000060A020000294A26000000000000000021 +:1014200000204811000000000000000000204811CA +:101430000000000000000100002018110000000062 +:101440000000000800621E280000012F00000008B4 +:1014500000822228000000000002C0000020441189 +:10146000000000000000001500600E2D000001BD0E +:101470000000001600600E2D000001BD0000C00835 +:1014800000204411000000000000001700200E2D75 +:10149000000000000000000014C00000000001B9BE +:1014A0000000000000200411000000000000000007 +:1014B0000020480100000000390000000020481111 +:1014C00000000000000000000020481100000000A3 +:1014D000000000000080480200000000000000182A +:1014E00000202E2D0000000000000000003B0D63D6 +:1014F000000000000000000800224A230000000055 +:101500000000001000224A23000000000000001824 +:1015100000224A2300000000000000000080480371 +:101520000000000000000000006000000000000B50 +:10153000000010000060041100000315000000000E +:1015400000200411000000000000000000600811ED +:10155000000001B2000000070021062F000000007B +:101560000000001300200A2D000000000000000110 +:1015700000202C11000000000000FFFF4028222066 +:10158000000000000000000F0026222800000000DC +:101590000000001040212620000000000000000F85 +:1015A000002626290000000000000000002028027C +:1015B000000000000000225600204411000000003E +:1015C0000000001B00204811000000000000000087 +:1015D000002F022100000000000000000CE00000CD +:1015E000000001E00000225C002044110000000027 +:1015F0000000008100204811000000000000A1FC54 +:1016000000204411000000000000000100204811EB +:10161000000000000000008000201C1100000000FD +:1016200000000000002F0227000000000000000062 +:101630000CE00000000001DC000000000060000081 +:10164000000001E90000000100531E27000001D83E +:101650000000000100202C11000000000000001F0D +:1016600000280A22000000000000001F00282A2A8B +:10167000000000000000000100530621000001D11D +:101680000000225C00204411000000000000000265 +:1016900000304A2F000000000000A1FC002044118F +:1016A00000000000000000010020481100000000C0 +:1016B0000000000100301E2F0000000000000000AC +:1016C000002F022700000000000000000CE00000D6 +:1016D000000000000000000000600000000001E9C0 +:1016E0000000000100531E27000001E50000FFFF7D +:1016F00040280E20000000000000000F00260E23EE +:101700000000000000000010C021122000000000B6 +:101710000000000F0026122400000000000000005E +:1017200000201411000000000000000000601811EB +:10173000000002BB0001A1FD0020441100000000D8 +:1017400000000000002F022B00000000000000003D +:101750000CE00000000001F8000000100022162834 +:1017600000000000FFFF0000002816250000000018 +:101770000000FFFF00281A29000000000000000000 +:10178000002948C500000000000000000020480AB1 +:10179000000000000000000000202C1100000000EC +:1017A000000000100022162300000000FFFF0000D0 +:1017B00000281625000000000000FFFF00281A2462 +:1017C0000000000000000000002948C500000000E3 +:1017D0000000000000731503000002050000000077 +:1017E0000020180500000000000000000073152410 +:1017F0000000020500000000002D14C500000000DC +:1018000000000000003008A20000000000000000FE +:101810000020480200000000000000000020280214 +:101820000000000000000000002020030000000075 +:101830000000000000802404000000000000000FF1 +:1018400000210225000000000000000014C000007C +:101850000000068900000000002B140500000000B5 +:1018600000000001009016250000000000000000AC +:10187000006000000000000B000000000060041188 +:10188000000003150000000000200411000000000B +:101890000000000000600811000001B200002256A4 +:1018A00000204411000000000000001A00294A2214 +:1018B0000000000000000000C02000000000000048 +:1018C00000003FFF002F022F00000000000000007A +:1018D0000CE000000000000000000000C020040038 +:1018E000000000000000225C002044110000000005 +:1018F0000000000300384A21000000000000A1FCA5 +:1019000000204411000000000000000100204811E8 +:10191000000000000000FFFF40281220000000002F +:1019200000000010C0211A20000000000000FFFF8E +:1019300040280E200000000000000010C0211620EA +:10194000000000000000000000741465000002BBED +:101950000001A1FD00604411000002E00000000150 +:10196000003306210000000000000000002F0221CB +:1019700000000000000000000CC000000000021980 +:1019800000003FFF002F022F0000000000000000B9 +:101990000CC000000000021200000000C040040063 +:1019A000000000010000000000600000000006428E +:1019B000000000000040040F0000021300000000BF +:1019C000006000000000062E000000000060000023 +:1019D0000000064200000210006004110000031520 +:1019E0000000000000600000000001A000000000F6 +:1019F000006000000000019C00000000006000008A +:101A0000000002BB0000000000600000000002A314 +:101A1000938000000020441100000000000000003E +:101A2000002048080000000000000000002F022FE6 +:101A300000000000000000000AE000000000023288 +:101A400000000000006000000000013A00000000FB +:101A50000040000000000236950000000020441104 +:101A60000000000000000000002F022F0000000016 +:101A7000000000000CE00000000002360000000042 +:101A8000C0404800000002339200000000204411D2 +:101A90000000000000000000C0204800000000001E +:101AA0000000225600204411000000000000001633 +:101AB00000204811000000000000225C00204411BA +:101AC000000000000000000300204811000000009A +:101AD0000000A1FC002044110000000000000001F3 +:101AE00000204811000000000001A1FD0020441169 +:101AF000000000000000000000600411000002FB74 +:101B000000000000C04004000000000100000000D0 +:101B1000006000000000062E0000A00C0020441110 +:101B20000000000000000000C0204800000000008D +:101B300000000000C040480000000000000000005D +:101B4000006000000000000B0000001840210A2087 +:101B50000000000000000003002F0222000000002F +:101B6000000000000AE000000000024C0000001429 +:101B70000020222D00000000000801010029222879 +:101B800000000000000000140020362800000000C3 +:101B90000000A30C00204411000000000000000021 +:101BA000C02048000000000000000000C0204800E5 +:101BB0000000000000000000C0404800000002518A +:101BC00000000000006000000000000B000000109A +:101BD00000600411000003153F8000000020041184 +:101BE000000000000000000000600811000001B2C9 +:101BF0000000225C002044110000000000000003EF +:101C000000204811000000000000000000600000FB +:101C10000000027C0000001700201E2D00000000C4 +:101C20000000000100211E2700000000000000004D +:101C300014E000000000026A0000001200201E2DC7 +:101C4000000000000000FFFF00281E270000000029 +:101C50000000000000341C2700000000000000000D +:101C600012C000000000025F0000000000201C11F4 +:101C70000000000000000000002F00E50000000050 +:101C80000000000008C00000000002620000000028 +:101C900000201407000000000000001200201E2D8C +:101CA000000000000000001000211E2700000000BE +:101CB0000000000000341C4700000000000000008D +:101CC00012C00000000002670000000000201C118C +:101CD0000000000000000000002F00E600000000EF +:101CE0000000000008C000000000026A00000000C0 +:101CF0000020180700000000000000000060000045 +:101D0000000002C100002256002044110000000023 +:101D1000000000000034202300000000000000004C +:101D200012C00000000002720000000000342044D5 +:101D3000000000000000000012C00000000002715E +:101D40000000001600404811000002760000001854 +:101D500000404811000002760000000000342044DA +:101D6000000000000000000012C00000000002752A +:101D70000000001700404811000002760000001922 +:101D800000204811000000000000A1FC00204411C8 +:101D900000000000000000010020481100000000C9 +:101DA0000001A1FD00604411000002E900003FFFB6 +:101DB000002F022F00000000000000000CC00000F7 +:101DC0000000025600000000C040040000000001B6 +:101DD0000000001040210620000000000000FFFF6E +:101DE000C0280A20000000000000001040210E2042 +:101DF000000000000000FFFFC028122000000000CB +:101E00000000001040211620000000000000FFFF2D +:101E1000C0881A200000000081000000002044114A +:101E20000000000000000001002048110000000038 +:101E300000042004006044110000068A0000000035 +:101E4000006000000000062E00000000C0600000DE +:101E5000000002A30000000500200A2D0000000081 +:101E60000000000800220A22000000000000002BF1 +:101E700000201A2D000000000000001C00201E2D74 +:101E8000000000000000700000281E270000000075 +:101E90000000000000311CE6000000000000002AE5 +:101EA00000201A2D000000000000000C00221A265D +:101EB0000000000000000000002F00E6000000000D +:101EC0000000000006E00000000002920000000098 +:101ED00000201C11000000000000000000200C1178 +:101EE000000000000000002B00203623000000004E +:101EF0000000001000201811000000000000000089 +:101F000000691CE20000012F9380000000204411B2 +:101F10000000000000000000002048070000000052 +:101F200095000000002044110000000000000000A7 +:101F3000002F022F00000000000000000CE0000055 +:101F40000000029D0000000100333E2F0000000051 +:101F500000000000D90048000000000092000000CE +:101F6000002044110000000000000000C0204800D4 +:101F7000000000000000001C0040362700000000A8 +:101F80000000000CC0220A20000000000000002910 +:101F9000002036220000000000000028C04036204B +:101FA000000000000000A2A4002044110000000076 +:101FB000000000090020481100000000A1000000FE +:101FC00000204411000000000000000100804811C2 +:101FD000000000000000002100201E2D0000000075 +:101FE00000000000002C1CE30000000000000021A5 +:101FF00000203627000000000000002200201E2DD7 +:102000000000000000000000002C1CE400000000A4 +:1020100000000022002036270000000000000023FE +:1020200000201E2D0000000000000000003120A351 +:102030000000000000000000002D1D07000000004F +:1020400000000023002036270000000000000024CC +:1020500000201E2D0000000000000000003120C400 +:102060000000000000000000002D1D07000000001F +:10207000000000240080362700000000000000213E +:10208000002036230000000000000022002036243B +:10209000000000000000000000311CA30000000050 +:1020A0000000002300203627000000000000000090 +:1020B00000311CC40000000000000024008036270E +:1020C000000000000000001A002036270000000079 +:1020D0000000001B00203628000000000000001750 +:1020E00000201E2D00000000000000020021022739 +:1020F000000000000000000014C00000000002DC2E +:102100000000000000400000000002D90000001A9A +:1021100000203627000000000000001B00203628A9 +:10212000000000000000001700201E2D000000002D +:102130000000000200210227000000000000000053 +:1021400014E00000000002D9000000030021022773 +:10215000000000000000000014E00000000002DCAD +:102160000000002300201E2D0000000000000000E1 +:10217000002E00E1000000000000000002C000008E +:10218000000002DC0000002100201E2D00000000E5 +:1021900000000000003120A100000000000000004D +:1021A000002E00E8000000000000000006C0000053 +:1021B000000002DC0000002400201E2D00000000B2 +:1021C00000000000002E00E20000000000000000FF +:1021D00002C00000000002DC0000002200201E2DD2 +:1021E0000000000000000000003120C200000000DC +:1021F00000000000002E00E80000000000000000C9 +:1022000006C00000000002DC0000000000600000CA +:10221000000006650000000000600000000002B53C +:102220000000000000400000000002DE000000008E +:1022300000600000000002B5000000000060000027 +:102240000000065C0000000000400000000002DE0C +:102250000000000000600000000002A70000000075 +:1022600000400000000002DE0000001A00201E2DC9 +:10227000000000000000001B0080222D0000000074 +:102280000000001000221E230000000000000000DB +:1022900000294887000000000000000000311CA356 +:1022A000000000000000001000221E2700000000B7 +:1022B0000000000000294887000000000000001016 +:1022C00000221E230000000000000000003120C496 +:1022D000000000000000FFFF00282228000000008E +:1022E0000000000000894907000000000000001005 +:1022F00000221E2300000000000000000029488783 +:10230000000000000000001000221E21000000005C +:102310000000000000294847000000000000000005 +:1023200000311CA3000000000000001000221E2746 +:1023300000000000000000000029488700000000A5 +:102340000000000000311CA100000000000000108F +:1023500000221E270000000000000000002948475E +:10236000000000000000001000221E2300000000FA +:1023700000000000003120C4000000000000FFFF4A +:102380000028222800000000000000000029490762 +:10239000000000000000001000221E2100000000CC +:1023A00000000000003120C2000000000000FFFF1C +:1023B00000282228000000000000000000894907D2 +:1023C000000000000000001000221E23000000009A +:1023D0000000000000294887000000000000000104 +:1023E00000220A210000000000000000003308A2C3 +:1023F000000000000000001000221E22000000006B +:102400000000001000212222000000000000000057 +:1024100000294907000000000000000000311CA353 +:10242000000000000000001000221E270000000035 +:1024300000000000002948870000000000000001A3 +:1024400000220A210000000000000000003008A265 +:10245000000000000000001000221E22000000000A +:1024600000000010002122220000000000000000F7 +:1024700000294907000000000000001000221E2370 +:102480000000000000000000003120C40000000037 +:102490000000FFFF002822280000000000000000CC +:1024A000002949070000000000000000003808C5AE +:1024B00000000000000000000030084100000000A3 +:1024C0000000000100220A220000000000000000BD +:1024D000003308A2000000000000001000221E22AD +:1024E0000000000000000010002122220000000077 +:1024F00000000000008949070000000000000017EC +:102500000020222D000000000000000014C0000088 +:1025100000000318FFFFFFEF002806210000000065 +:10252000000000140020222D000000000000F8E050 +:1025300000204411000000000000000000294901B3 +:1025400000000000000000000089490100000000B8 +:102550000000000000204811000000000000000002 +:102560000020481100000000060A02000080481107 +:102570000000000000000000C0200000000000007B +:1025800097000000C020441100000000000000007F +:10259000C0204811000000008A0000000020441103 +:1025A00000000000000000000020481100000000B2 +:1025B0000000225C00204411000000000000000028 +:1025C000C0204800000000000000A1FC00204411D1 +:1025D0000000000000000000C020480000000000D3 +:1025E00000000000C0200400000000000000000007 +:1025F00000A0000A00000000970000000020441125 +:102600000000000000000000002048110000000051 +:102610008A000000002044110000000000000000BB +:1026200000204811000000000000225C002044113E +:102630000000000000000000C02048000000000072 +:102640000000A1FC00204411000000000000000078 +:10265000C02048000000000000000000C02004006E +:10266000000000000000000000A0000A00000000C0 +:10267000970000000020441100000000000000004E +:1026800000204811000000008A00000000204411D2 +:1026900000000000000000000020481100000000C1 +:1026A0000000225C00204411000000000000000037 +:1026B000C0204800000000000000A1FC00204411E0 +:1026C0000000000000000000C020480000000000E2 +:1026D0000001A1FD002044110000000000000000E6 +:1026E000D90048000000000000000000C0200400E5 +:1026F000000000000000000000A0000A0000000030 +:1027000000002257002044110000000000000003D8 +:10271000C0484A20000000000000225D0020441153 +:102720000000000000000000C04048000000000061 +:1027300000000000006000000000064200000000F1 +:10274000C0200800000000000000225C00204411AE +:10275000000000000000000300384A2200000000D2 +:102760000000A1FC00204411000000000000000057 +:10277000C0204800000000000001A1FD002044111D +:102780000000000000000000002F022200000000F6 +:10279000000000000CE0000000000000000000004D +:1027A00040204800000000000000000140304A20A6 +:1027B0000000000000000002C0304A2000000000BD +:1027C0000000000100530A220000034B0000003FFC +:1027D000C0280A20000000008100000000204411F1 +:1027E000000000000000000100204811000000006F +:1027F000000021F800204411000000000000001833 +:102800000020481100000000000421F9006044117C +:102810000000068A000000110021023000000000C4 +:102820000000000014E00000000003540000001449 +:10283000002F022200000000000000000CC0000079 +:10284000000003640000201000204411000000007C +:102850000000800000204811000000000001A2A438 +:102860000020441100000000000000000060480249 +:102870000000036E00002100002044110000000051 +:1028800000000000C0204800000000000000000020 +:10289000C02048000000000000000000C0204800E8 +:1028A0000000000000000000C040480000000000E0 +:1028B00000000004002F02220000000000000000C1 +:1028C0000CC000000000036A00002010002044112A +:1028D00000000000000080000020481100000000FF +:1028E0000001A2A40020441100000000000000002C +:1028F000004048020000035F00000028002F022271 +:1029000000000000000000000CC00000000005BD39 +:102910000001A2A4002044110000000000000000FB +:10292000004048020000035F0000002C0020362613 +:102930000000000000000049002018110000000005 +:102940000000003F002048110000000000000001CE +:1029500000331A260000000000000000002F0226AD +:1029600000000000000000000CC000000000037028 +:102970000000002C00801A2D000000000000003F25 +:10298000C0280A200000000000000015002F0222CD +:1029900000000000000000000CE0000000000386C2 +:1029A00000000006002F02220000000000000000CE +:1029B0000CE00000000003B100000016002F02220E +:1029C00000000000000000000CE00000000003B563 +:1029D00000000020002F0222000000000000000084 +:1029E0000CE000000000039C0000000F002F0222FA +:1029F00000000000000000000CE00000000003A840 +:102A000000000010002F0222000000000000000063 +:102A10000CE00000000003A80000001E002F0222AE +:102A200000000000000000000CE000000000039027 +:102A30000000A2A4002044110000000000000000DB +:102A400000404802000000000800000000290A229F +:102A5000000000000000000340210E2000000000E4 +:102A60000000000CC021122000000000000800003F +:102A7000002812240000000000000014C0221620CC +:102A80000000000000000000002914A40000000065 +:102A90000000A2A40020441100000000000000007B +:102AA000002948A2000000000000A1FE00204411FF +:102AB000000000000000000000404803000000008B +:102AC000810000000020441100000000000000010F +:102AD0000020481100000000000021F800204411EF +:102AE0000000000000000016002048110000000057 +:102AF000000421F9006044110000068A000000155E +:102B000000210230000000000000000014E000007E +:102B1000000003920000210E00204411000000007C +:102B200000000000C020480000000000000000007D +:102B3000C0204800000000000000A2A400204411B2 +:102B400000000000000000000040480200000000FB +:102B5000810000000020441100000000000000017E +:102B60000020481100000000000021F8002044115E +:102B700000000000000000170020481100000000C5 +:102B8000000421F9006044110000068A00000003DF +:102B900000210230000000000000000014E00000EE +:102BA0000000039E000021080020441100000000E6 +:102BB00000000000C02048000000000000000000ED +:102BC000C0204800000000000000A2A40020441122 +:102BD000000000000000000000404802000000006B +:102BE0000000A2A40020441100000000000000002A +:102BF0000020480200000000800000000020441176 +:102C0000000000000000000000204811000000004B +:102C100081000000002044110000000000000010AE +:102C200000204811000000000000000000200010FB +:102C3000000000000000000014C00000000003AE0F +:102C40000000000000400000000000000000201014 +:102C50000020441100000000000080000020481106 +:102C6000000000000001A2A40020441100000000A8 +:102C70000000000600404811000000000000201085 +:102C800000204411000000000000800000204811D6 +:102C9000000000000001A2A4002044110000000078 +:102CA00000000016006048110000036E00000000E4 +:102CB000004000000000000000000000C0200800EC +:102CC0000000000000000000C0200C000000000018 +:102CD0000000001D00210223000000000000000091 +:102CE00014E00000000003CE810000000020441129 +:102CF000000000000000000100204811000000005A +:102D0000000021F80020441100000000000000181D +:102D10000020481100000000000421F90060441167 +:102D20000000068A000000110021023000000000AF +:102D30000000000014E00000000003C000002100BB +:102D400000204411000000000000000000204802A4 +:102D50000000000000000000002048030000000008 +:102D6000BABECAFE0020481100000000CAFEBABE6A +:102D70000020481100000000000020100020441135 +:102D8000000000000000800000204811000000004A +:102D90000000A2A400204411000000000000000474 +:102DA0000040481100000000000021700020441184 +:102DB00000000000000000000020480200000000A9 +:102DC0000000000000204803000000008100000017 +:102DD00000204411000000000000000A00204811FB +:102DE00000000000000000000020001000000000B3 +:102DF0000000000014C00000000003D38C0000009D +:102E00000020441100000000CAFEBABE0040481174 +:102E100000000000810000000020441100000000BC +:102E200000000001002048110000000000003FFFEA +:102E300040280A20000000008000000040280E20EA +:102E40000000000040000000C02812200000000028 +:102E500000040000006946220000068A000000000D +:102E6000002014100000000000000000002F0223CA +:102E700000000000000000000CC00000000003E1A2 +:102E800000000000C0401800000003E400003FFF05 +:102E9000C0281A2000000000000400000069462637 +:102EA0000000068A0000000000201810000000004A +:102EB00000000000002F02240000000000000000BD +:102EC0000CC00000000003E700000000C0401C0030 +:102ED000000003EA00003FFFC0281E2000000000A1 +:102EE00000040000006946270000068A0000000078 +:102EF00000201C1000000000000000000020440220 +:102F00000000000000000000002820C500000000B4 +:102F100000000000004948E800000000A580000013 +:102F200000200811000000000000200000200C110B +:102F30000000000083000000006044110000041243 +:102F4000000000000020440200000000000000001B +:102F5000C0204800000000000000000040204800A1 +:102F6000000000000000001FC0210220000000003F +:102F70000000000014C00000000003F70000201053 +:102F800000204411000000000000800000204811D3 +:102F9000000000000000FFFFC0481220000003FFF7 +:102FA000A780000000200811000000000000A00021 +:102FB00000200C110000000083000000006044119C +:102FC0000000041200000000002044020000000085 +:102FD00000000000C02048000000000000000000C9 +:102FE000C0204800000000000000FFFFC0281220A1 +:102FF00000000000830000000020441100000000D9 +:103000000000000000304883000000008400000041 +:10301000002044110000000000000000C020480013 +:1030200000000000000000001D0000000000000083 +:103030008300000000604411000004120000000042 +:10304000C040040000000001A98000000020081119 +:10305000000000000000C00000400C11000003FA56 +:10306000AB80000000200811000000000000F8E024 +:1030700000400C11000003FAAD8000000020081190 +:10308000000000000000F88000400C11000003FA6E +:10309000B380000000200811000000000000F3FCD5 +:1030A00000400C11000003FAAF800000002008115E +:1030B000000000000000E00000400C11000003FAD6 +:1030C000B180000000200811000000000000F000A6 +:1030D00000400C11000003FA83000000002044119E +:1030E00000000000000021480020481100000000FE +:1030F00084000000002044110000000000000000D7 +:10310000C020480000000000000000001D0000007A +:10311000000000000000000000800000000000002F +:1031200001182000C0304620000000000000000010 +:10313000D90048000000000000000000C02004008A +:10314000000000000000000000A0000A00000000D5 +:103150000218A000C030462000000000000000005F +:10316000D90048000000000000000000C02004005A +:10317000000000000000000000A0000A00000000A5 +:103180000318C000C030462000000000000000000E +:10319000D90048000000000000000000C02004002A +:1031A000000000000000000000A0000A0000000075 +:1031B0000418F8E0C03046200000000000000000C5 +:1031C000D90048000000000000000000C0200400FA +:1031D000000000000000000000A0000A0000000045 +:1031E0000518F880C03046200000000000000000F4 +:1031F000D90048000000000000000000C0200400CA +:10320000000000000000000000A0000A0000000014 +:103210000618E000C030462000000000000000005A +:10322000D90048000000000000000000C020040099 +:10323000000000000000000000A0000A00000000E4 +:103240000718F000C0304620000000000000000019 +:10325000D90048000000000000000000C020040069 +:10326000000000000000000000A0000A00000000B4 +:103270000818F3FCC03046200000000000000000E9 +:10328000D90048000000000000000000C020040039 +:10329000000000000000000000A0000A0000000084 +:1032A0000000003000200A2D000000000000000097 +:1032B000C0290C4000000000000000300020362330 +:1032C0000000000000000000C0200400000000001A +:1032D0000000000000A0000A0000000086000000BE +:1032E00000204411000000000000000000404801E0 +:1032F0000000000085000000C02044110000000014 +:103300000000000000404801000000000000217C97 +:10331000002044110000000000000000C020480010 +:103320000000000000000000C02048000000000075 +:1033300000000000C02048000000000081000000E4 +:10334000002044110000000000000001002048118E +:103350000000000000000000C02008000000000085 +:103360000000000017000000000000000004217FA2 +:10337000006044110000068A0000001F0021023096 +:10338000000000000000000014C000000000000069 +:103390000000000000404C02000004480000000053 +:1033A000C0200C000000000000000000C020100041 +:1033B0000000000000000000C02014000000000019 +:1033C00000000000C0201800000000000000000005 +:1033D000C0201C000000000000007F0000280A211F +:1033E0000000000000004500002F02220000000045 +:1033F000000000000CE00000000004560000000087 +:10340000C0202000000000000000000017000000A5 +:10341000000000000000001000280A230000000047 +:1034200000000010002F0222000000000000000039 +:103430000CE000000000045E810000000020441148 +:103440000000000000000001002048110000000002 +:1034500000040000006946240000068A0000000005 +:1034600000400000000004638100000000204411BF +:1034700000000000000000000020481100000000D3 +:103480000000216D00204411000000000000000039 +:103490000020480400000000000000000060480513 +:1034A0000000068F00000000002824F0000000004B +:1034B0000000000700280A230000000000000001AF +:1034C000002F022200000000000000000AE00000BF +:1034D0000000046A00000000002F00C90000000086 +:1034E0000000000004E00000000004830000000071 +:1034F000004000000000049000000002002F0222A3 +:1035000000000000000000000AE000000000046F5E +:1035100000000000002F00C90000000000000000B3 +:1035200002E00000000004830000000000400000F2 +:103530000000049000000003002F022200000000A1 +:10354000000000000AE00000000004740000000019 +:10355000002F00C900000000000000000CE0000087 +:103560000000048300000000004000000000049000 +:1035700000000004002F02220000000000000000F4 +:103580000AE000000000047900000000002F00C9DC +:1035900000000000000000000AE0000000000483BA +:1035A0000000000000400000000004900000000542 +:1035B000002F022200000000000000000AE00000CE +:1035C0000000047E00000000002F00C90000000081 +:1035D0000000000006E0000000000483000000007E +:1035E000004000000000049000000006002F0222AE +:1035F00000000000000000000AE00000000004835A +:1036000000000000002F00C90000000000000000C2 +:1036100008E00000000004830000000000400000FB +:103620000000049000007F0000280A210000000034 +:1036300000004500002F02220000000000000000F2 +:103640000AE00000000000000000000800210A233A +:10365000000000000000000014C000000000048D05 +:10366000000021690020441100000000000000005B +:10367000C02048000000000000000000C0204800FA +:103680000000000000000000C02048000000000012 +:10369000CAFEBABE00404811000000000000000051 +:1036A000C02044000000000000000000C020000016 +:1036B0000000000000000000C040480000000000C2 +:1036C00000007F0000280A210000000000004500E3 +:1036D000002F022200000000000000000AE00000AD +:1036E0000000049600000000C02000000000000060 +:1036F00000000000C02000000000000000000000EA +:10370000C0400000000000000000000000404C0825 +:103710000000045600000000C02008000000000067 +:103720000000001040210E200000000000000011E9 +:10373000402112200000000000000012402116204D +:10374000000000000000216900204411000000007A +:1037500000000000002048020000000000000000FF +:1037600000210225000000000000000014E000001D +:10377000000004A000040000C0494A20000004A189 +:10378000FFFBFFFFC0284A200000000000000000EF +:1037900000210223000000000000000014E00000EF +:1037A000000004AD00000000C02048000000000040 +:1037B00000000000C02048000000000000000000E1 +:1037C00000210224000000000000000014C00000DE +:1037D00000000000810000000020441100000000F3 +:1037E0000000000C00204811000000000000000054 +:1037F00000200010000000000000000014C00000C5 +:10380000000004A9A00000000020441100000000F6 +:10381000CAFEBABE0040481100000000810000004E +:1038200000204411000000000000000400204811A6 +:10383000000000000000216B002044110000000087 +:1038400000000000C02048100000000081000000BF +:103850000020441100000000000000050020481175 +:10386000000000000000216C002044110000000056 +:1038700000000000C0204810000000000000000010 +:10388000002F022400000000000000000CE00000F7 +:10389000000000000000000000400000000004A73D +:1038A00000000000C0210A2000000000000000000D +:1038B00014C00000000004C081000000002044117A +:1038C000000000000000000000204811000000007F +:1038D0000000216D002044110000000000000000E5 +:1038E000C02048000000000000000000C060480048 +:1038F0000000068F0000000000400000000004C42B +:1039000081000000002044110000000000000001C0 +:10391000002048110000000000040000C0294620DB +:103920000000000000000000C06000000000068AE7 +:103930000000000100210222000000000000000041 +:1039400014C00000000004CB0000216900204411D5 +:103950000000000000000000C0204800000000003F +:1039600000000000C020480000000000000000002F +:103970000020481000000000CAFEBABE00404811F6 +:103980000000000000000000C02044000000000013 +:1039900000000000C040481000000000810000004E +:1039A0000020441100000000000000010020481128 +:1039B00000000000000021F8002044110000000079 +:1039C0000000000E0020481100000000000421F952 +:1039D000006044110000068A00000000002102304F +:1039E000000000000000000014C00000000004CD32 +:1039F00000002180002044110000000000000000B1 +:103A0000C02048000000000000000000C0200000AE +:103A10000000000000000000C0204800000000007E +:103A200000000000C02000000000000000000000B6 +:103A3000C0404800000000000000000300333E2F9B +:103A40000000000000000001002102210000000031 +:103A50000000000014E00000000004FD0000002C45 +:103A600000200A2D000000000004000018E00C11E6 +:103A7000000004EC0000000100333E2F00000000B5 +:103A80000000216900204411000000000000000037 +:103A90000020480200000000000000000020480351 +:103AA000000000000000000800300A2200000000B2 +:103AB00000000000C02048000000000000000000DE +:103AC000C0204800000000000000216900204411CF +:103AD000000000000000000000204802000000007C +:103AE0000000000000204803000000000000000863 +:103AF00000300A220000000000000000C020480042 +:103B00000000000000000000D8C04800000004E0F1 +:103B100000002169002044110000000000000000A6 +:103B200000204802000000000000000000204803C0 +:103B3000000000000000000800300A220000000021 +:103B400000000000C020480000000000000000004D +:103B5000C0204800000000000000002D0020122DB1 +:103B6000000000000000000000290C83000000009D +:103B70000000216900204411000000000000000046 +:103B80000020480200000000000000000020480360 +:103B9000000000000000000800300A2200000000C1 +:103BA00000000000C02048000000000000000000ED +:103BB000C020480000000000000000110021022485 +:103BC000000000000000000014C000000000000021 +:103BD0000000000000400000000004A70000002CCE +:103BE000C0203620000000000000002DC04036201C +:103BF000000000000000000F002102210000000072 +:103C00000000000014C000000000050200000000D9 +:103C1000006000000000000B00000000D900000060 +:103C20000000000000000000C0400400000000018F +:103C3000B50000000020441100000000000020003A +:103C40000020481100000000B600000000204411D0 +:103C5000000000000000A00000204811000000004B +:103C6000B700000000204411000000000000C00068 +:103C70000020481100000000B8000000002044119E +:103C8000000000000000F8E00020481100000000E3 +:103C9000B900000000204411000000000000F8807E +:103CA0000020481100000000BA000000002044116C +:103CB000000000000000E0000020481100000000AB +:103CC000BB00000000204411000000000000F000D4 +:103CD0000020481100000000BC000000002044113A +:103CE000000000000000F3FC00204811000000006C +:103CF00081000000002044110000000000000002CC +:103D00000020481100000000000000FF00280E30D5 +:103D10000000000000000000002F0223000000004F +:103D2000000000000CC000000000051600000000AC +:103D3000C0200800000000000000000014C00000C7 +:103D40000000052B0000000000200C110000000006 +:103D50000000001C00203623000000000000002BA3 +:103D60000020362300000000000000290020362338 +:103D700000000000000000280020362300000000A2 +:103D8000000000170020362300000000000000257E +:103D9000002036230000000000000026002036230B +:103DA0000000000000000015002036230000000085 +:103DB000000000160020362300000000FFFFE00096 +:103DC00000200C110000000000000021002036231C +:103DD0000000000000000022002036230000000048 +:103DE00000001FFF00200C11000000000000002355 +:103DF00000203623000000000000002400203623AD +:103E000000000000F1FFFFFF00283A2E0000000034 +:103E10000000001AC0220E20000000000000000078 +:103E20000029386E000000008100000000204411CD +:103E30000000000000000006002048110000000003 +:103E40000000002A4020362000000000870000000B +:103E5000002044110000000000000000C0204800C5 +:103E6000000000000000A1F4002044110000000048 +:103E700000000000002048100000000000000000CA +:103E800000200C110000000000000030002036234C +:103E9000000000009D000000002044110000000010 +:103EA0000000001F40214A20000000009600000092 +:103EB000002044110000000000000000C020480065 +:103EC0000000000000000000C0200C000000000006 +:103ED00000000000C0201000000000000000001FD3 +:103EE00000211624000000000000000014C00000A3 +:103EF000000000000000001D00203623000000002C +:103F00000000000300281E2300000000000000083D +:103F10000022222300000000FFFFF00000282228DA +:103F20000000000000000000002920E80000000060 +:103F30000000001F002036280000000000000018CC +:103F400000211E2300000000000000200020362772 +:103F50000000000000000002002216240000000003 +:103F600000000000003014A8000000000000001E47 +:103F700000203625000000000000000300211A2464 +:103F8000000000001000000000281A2600000000B9 +:103F9000EFFFFFFF00283A2E0000000000000000A5 +:103FA000004938CE000006780000000140280A20B1 +:103FB000000000000000000640280E200000000065 +:103FC00000000300C02812200000000000000008CC +:103FD000002112240000000000000000C020162074 +:103FE0000000000000000000C0201A2000000000B7 +:103FF000000000000021022200000000000000007C +:1040000014C000000000056381000000002044117E +:104010000000000000000001002048110000000026 +:104020000000225800300A240000000000040000B4 +:10403000006946220000068A000021690020441120 +:104040000000000000000000002048050000000003 +:104050000002000000294A260000000000000000C5 +:104060000020481000000000CAFEBABE002048111F +:104070000000000000000002002F022300000000EA +:10408000000000000CC000000000056B00000000F4 +:10409000C0201C100000000000000000C040000014 +:1040A0000000057900000002002F0223000000003C +:1040B000000000000CC000000000056B8100000043 +:1040C0000020441100000000000000010020481101 +:1040D000000000000000225800300A240000000008 +:1040E00000040000006946220000068A000000006B +:1040F000C0201C100000000000000000C0400000B4 +:104100000000057900000000002F022300000000DD +:10411000000000000CC000000000056F000000005F +:10412000C0201C000000000000000000C040000093 +:104130000000057900000004002F022300000000A9 +:10414000000000000CC000000000057781000000A6 +:104150000020441100000000000000000020481171 +:10416000000000000000216D00204411000000004C +:1041700000000000C0204800000000000000000017 +:10418000C06048000000068F0000000000401C10C6 +:104190000000057900000000C020000000000000C1 +:1041A00000000000C040000000000000000000000F +:1041B0000EE000000000057B000000000060000031 +:1041C000000005C600000000002F022400000000CF +:1041D000000000000CC000000000058C0000A2B729 +:1041E00000204411000000000000000000204807EB +:1041F00000000000810000000020441100000000C9 +:104200000000000100204811000000000004A2B6D8 +:10421000006044110000068A0000001A00212230CC +:104220000000000000000006002226300000000010 +:1042300000042004006044110000068A0000A2C4AB +:10424000002044110000000000000000003048E998 +:10425000000000000000000000E000000000058AEF +:104260000000A2D100204411000000000000000066 +:1042700000404808000000000000A2D100204411C6 +:10428000000000000000000100504A28000000006B +:1042900000000001002F02240000000000000000C8 +:1042A0000CC000000000059D0000A2BB00204411CE +:1042B000000000000000000000204807000000008F +:1042C00081000000002044110000000000000001F7 +:1042D00000204811000000000004A2BA0060441150 +:1042E0000000068A0000001A0021223000000000B1 +:1042F0000000000600222630000000000004200418 +:10430000006044110000068A0000A2C5002044118C +:104310000000000000000000003048E9000000003C +:104320000000000000E000000000059B0000A2D299 +:104330000020441100000000000000000040480878 +:10434000000000000000A2D2002044110000000084 +:104350000000000100504A28000000000000000298 +:10436000002F022400000000000000000CC000002C +:10437000000005AE0000A2BF0020441100000000B4 +:10438000000000000020480700000000810000003D +:10439000002044110000000000000001002048112E +:1043A000000000000004A2BE006044110000068A64 +:1043B0000000001A0021223000000000000000066A +:1043C0000022263000000000000420040060441198 +:1043D0000000068A0000A2C6002044110000000070 +:1043E00000000000003048E900000000000000006C +:1043F00000E00000000005AC0000A2D30020441142 +:10440000000000000000000000404808000000001C +:104410000000A2D3002044110000000000000001B1 +:1044200000504A28000000000000A2C300204411F0 +:10443000000000000000000000204807000000000D +:104440008100000000204411000000000000000175 +:1044500000204811000000000004A2C200604411C6 +:104460000000068A0000001A00212230000000002F +:104470000000000600222630000000000004200496 +:10448000006044110000068A0000A2C70020441109 +:104490000000000000000000003048E900000000BB +:1044A0000000000000E00000000005BB0000A2D4F6 +:1044B00000204411000000000000000000404808F7 +:1044C000000000000000A2D4002044110000000001 +:1044D0000000000100504A28000000008500000094 +:1044E00000204411000000000000000000204801EE +:1044F000000000000000304A0020441100000000CD +:104500000100000000204811000000000000000031 +:1045100000400000000005C1A4000000C0204411BC +:104520000000000000000000C04048000000000043 +:1045300000000000C0600000000005C60000000090 +:10454000C0400400000000010000002C00203621C3 +:104550000000000081000000002044110000000065 +:1045600000000006002048110000000000000000CC +:10457000002F023000000000000000000CC000000E +:10458000000005CD00000000002004110000000024 +:104590000000003000403621000005E0000000303F +:1045A0000020062D0000000000007E0000280621EB +:1045B0000000000000000000002F022100000000A9 +:1045C000000000000CE00000000005E08100000099 +:1045D00000204411000000000000000100204811EC +:1045E000000000000004A092006044110000068A50 +:1045F0000000003100203630000000000004A093CD +:10460000006044110000068A0000003200203630AD +:10461000000000000004A2B6006044110000068AF9 +:104620000000003300203630000000000004A2BA71 +:10463000006044110000068A00000034002036307B +:10464000000000000004A2BE006044110000068AC1 +:104650000000003500203630000000000004A2C237 +:10466000006044110000068A000000360020363049 +:104670000000000000042004006044110000068ACD +:104680000001A2A400204411000000000000003F2F +:1046900000204811000000000000003F00204811E9 +:1046A000000000000000003F002048110000000052 +:1046B0000000003F0020481100000000000000053D +:1046C00000204811000000000000A1F40020441167 +:1046D0000000000000000000002048110000000061 +:1046E00088000000002044110000000000000001CC +:1046F000002048110000000081000000002044114B +:10470000000000000000000600204811000000002A +:1047100000000001002F0230000000000000000037 +:104720000CE0000000000629000000300020062DEB +:104730000000000000000000002F02210000000027 +:10474000000000000CE000000000062981000000CD +:10475000002044110000000000000001002048116A +:104760000000000000007E0000280621000000007C +:1047700000000000002F02210000000000000000E7 +:104780000CE00000000006020000A092002044118E +:10479000000000000000003100204A2D0000000051 +:1047A0000000A0930020441100000000000000322F +:1047B00000204A2D000000000000A2B60020441195 +:1047C000000000000000003300204A2D000000001F +:1047D0000000A2BA002044110000000000000034D4 +:1047E00000204A2D000000000000A2BE002044115D +:1047F000000000000000003500204A2D00000000ED +:104800000000A2C200204411000000000000003699 +:1048100000204A2D00000000000000300020062D7E +:1048200000000000000001FF002806210000000039 +:1048300000000000002F0221000000000000000026 +:104840000CE000000000062800000000002102210A +:10485000000000000000000014C000000000060B73 +:104860000004A003006044110000068A0000A003B9 +:10487000002044110000000000000000002048104B +:1048800000000000000000010021062100000000DF +:104890000000000014C00000000006100004A0107A +:1048A000006044110000068A0000A010002044119E +:1048B0000000000000000000002048100000000080 +:1048C000000000010021062100000000000000009F +:1048D000002F022100000000000000000CE000009A +:1048E000000006280004A011006044110000068AA0 +:1048F0000000A01100204411000000000000000092 +:1049000000204810000000000004A01200604411C4 +:104910000000068A0000A0120020441100000000E0 +:104920000000000000204810000000000004A01358 +:10493000006044110000068A0000A013002044110A +:1049400000000000000000000020481000000000EF +:104950000004A014006044110000068A0000A014A6 +:10496000002044110000000000000000002048105A +:10497000000000000004A015006044110000068A39 +:104980000000A015002044110000000000000000FD +:1049900000204810000000000004A0160060441130 +:1049A0000000068A0000A01600204411000000004C +:1049B0000000000000204810000000000004A017C4 +:1049C000006044110000068A0000A0170020441176 +:1049D000000000000000000000204810000000005F +:1049E00000042004006044110000068A0000002C2E +:1049F0000080062D00000000FF0000000020441190 +:104A0000000000000000000000204811000000002D +:104A1000000000010020481100000000000000021A +:104A20000080481100000000000000000EE00000BF +:104A30000000063A000000300020062D00000000B3 +:104A40000000000200280621000000000000000015 +:104A5000002F022100000000000000000CE0000018 +:104A60000000063881000000002044110000000012 +:104A70000000000100204811000000000004200494 +:104A8000006044110000068A000010000020081198 +:104A9000000000000000002B002036220000000073 +:104AA00000000000006000000000063E0000000062 +:104AB00000600000000005C69800000000204411BE +:104AC000000000000000000000804811000000000D +:104AD00000000000C06000000000063E0000000072 +:104AE000C0400400000000010000A2A40020441106 +:104AF000000000000000002200204811000000001B +:104B000089000000002044110000000000000001A6 +:104B1000004048110000062A9700000000204411C0 +:104B2000000000000000000000204811000000000C +:104B30008A00000000204411000000000000000076 +:104B4000004048110000062A00000000006000003C +:104B50000000065900002010002044110000000051 +:104B60000000800000204811000000000001A2A405 +:104B7000C020441100000000000000160060481131 +:104B80000000036E0000201000204411000000000F +:104B9000000100000020481100000000810000001A +:104BA0000020441100000000000000010020481116 +:104BB000000000000000217C0020441100000000E3 +:104BC000098000000020481100000000FFFFFFFFE7 +:104BD00000204811000000000000000000204811E3 +:104BE00000000000000000001700000000000000AE +:104BF0000004217F006044110000068A0000001FAD +:104C000000210230000000000000000014C000007D +:104C1000000000000000000400404C11000006539A +:104C2000000000000040000000000000000000172D +:104C300000201E2D000000000000000400291E2797 +:104C40000000000000000017008036270000000070 +:104C50000000001700201E2D00000000FFFFFFFBDA +:104C600000281E27000000000000001700803627E3 +:104C7000000000000000001700201E2D00000000B2 +:104C80000000000800291E27000000000000001797 +:104C900000803627000000000000001700201E2DB5 +:104CA00000000000FFFFFFF700281E2700000000A3 +:104CB00000000017008036270000000000002010D0 +:104CC0000020441100000000000080000020481176 +:104CD000000000000001A2A4002044110000000018 +:104CE00000000016006048110000036E0000201054 +:104CF00000204411000000000001000000204811C5 +:104D0000000000000000217C002044110000000091 +:104D1000018000000020481100000000FFFFFFFF9D +:104D20000020481100000000000000000020481191 +:104D3000000000000000000017000000000000005C +:104D4000810000000020441100000000000000016C +:104D500000204811000000000004217F0060441181 +:104D60000000068A0000001F002102300000000041 +:104D70000000000014C000000000068900000010C0 +:104D800000404C110000066F00000000C02004002D +:104D9000000000000000000038C00000000000001B +:104DA0000000001D00200A2D000000000000001E71 +:104DB00000200E2D000000000000001F0020122D1A +:104DC00000000000000000200020162D0000000060 +:104DD00000002169002044110000000000000000D4 +:104DE00000204804000000000000000000204805EA +:104DF000000000000000000000204801000000004A +:104E0000CAFEBABE002048110000000000000004E5 +:104E1000003012240000000000000000002F006499 +:104E200000000000000000000CC000000000068828 +:104E30000000000300281A22000000000000000803 +:104E40000022122200000000FFFFF00000281224C0 +:104E50000000000000000000002910C40000000055 +:104E60000000001F00403624000000000000000089 +:104E70000080000000000000000000001AC00000D8 +:104E80000000068A9F00000000204411000000007E +:104E9000CAFEBABE00204811000000000000000059 +:104EA0001AE000000000068D0000000000800000F5 +:104EB00000000000000000001AC000000000068F83 +:104EC0009E0000000020441100000000CAFEBABE8F +:104ED0000020481100000000000000001AE000005F +:104EE00000000692000000000080000000000000AA +:104EF00000000000006000000000000B0000100037 +:104F000000600411000003150000000000200411DF +:104F1000000000000000000000600811000001B265 +:104F20000000225C0020441100000000000000038B +:104F3000002048110000000000002256002044110B +:104F4000000000000000001B0020481100000000CD +:104F50000000A1FC0020441100000000000000013E +:104F600000204811000000000001A1FDC0204411F4 +:104F7000000000000000002100201E2D00000000A5 +:104F80000000001000221E27000000000000002486 +:104F90000020222D000000000000FFFF0028222832 +:104FA0000000000000000000002949070000000088 +:104FB0000000000000204811000000000000002256 +:104FC0000020222D000000000000FFFF0028222802 +:104FD0000000000000000000002949070000000058 +:104FE0000000000000204811000000000000002325 +:104FF00000201E2D000000000000001000221E27CF +:105000000000000000000000002949070000000027 +:1050100000000000004048110000000000000000F7 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B000014204FF05BD02500000000001C3016867 +:1052C000043F05BD00000000022502090250015103 +:1052D000000000000223024502A00241000000007D +:1052E00003D705BD05BD05BD000000000646064705 +:1052F000031F05BD0000000005BD05C203200340DB +:1053000000000000032A0282034203340000000070 +:1053100005BD05BD05BD05BD0000000005BD054E70 +:1053200005BD05BD0000000003BA05BD04B8034477 +:10533000000000000497044D043D05BD000000007E +:1053400004CD05BD044104DA00000000044D05044D +:10535000035103750000000005BD05BD05BD05BD79 +:105360000000000005BD05BD05BD05BD0000000035 +:1053700005BD05BD063C05C40000000005BD05BD1A +:10538000000705BD0000000005BD05BD05BD05BD4C +:105390000000000005BD05BD05BD05BD0000000005 +:1053A00003F803ED0408040600000000040E040ADC +:1053B000040C041000000000041C04180424042041 +:1053C00000000000042C0428043404300000000015 +:1053D00005BD05BD043805BD0000000005BD05BDC7 +:1053E00005BD05BD0000000005BD05BD05BD05BD31 +:1053F000000000000002067606940006000000008F +:00000001FF diff --git a/firmware/radeon/RV635_pfp.bin.ihex b/firmware/radeon/RV635_pfp.bin.ihex new file mode 100644 index 000000000000..f55292c97b79 --- /dev/null +++ b/firmware/radeon/RV635_pfp.bin.ihex @@ -0,0 +1,145 @@ +:1000000000CA040000A00000007E828B007C038BED +:10001000008001B8007C038B00D4401E00EE001E5F +:1000200000CA040000A00000007E828B00C41838C3 +:1000300000CA240000CA2800009581A800C41C3A08 +:1000400000C3C00000CA080000CA0C00007C744B4A +:1000500000C200050099C00000C41C3A007C744C2A +:1000600000C0FFF000042C0400309002007D250049 +:1000700000351402007D350B00255403007CD5802B +:1000800000259C030095C00400D5001B007EDDC147 +:10009000007D9D8000D6801B00D5801B00D4401EB3 +:1000A00000D5401E00D6401E00D6801E00D4801E03 +:1000B00000D4C01E009783D300D5C01E00CA08001C +:1000C0000080001A00CA0C0000E4011E00D4001ECB +:1000D0000080000C00C4183800E4013E00D4001E6B +:1000E0000080000C00C4183800D4401E00EE001E32 +:1000F00000CA040000A00000007E828B00E4011E04 +:1001000000D4001E00D4401E00EE001E00CA0400F1 +:1001100000A00000007E828B00E4013E00D4001E9F +:1001200000D4401E00EE001E00CA040000A0000023 +:10013000007E828B00CA180000D4401E00D5801EAD +:100140000080005300D4007500D4401E00CA08008F +:1001500000CA0C0000CA100000D4801900D4C018D6 +:1001600000D5001700D4801E00D4C01E00D5001E8C +:1001700000E2001E00CA040000A00000007E828B86 +:1001800000CA080000D4806000D4401E0080000037 +:1001900000D4801E00CA080000D4806100D4401E34 +:1001A0000080000000D4801E00CA080000CA0C00B5 +:1001B00000D4401E00D4801600D4C01600D4801E87 +:1001C000008001B800D4C01E00C6084300CA0C005D +:1001D00000CA10000094800400CA140000E420F358 +:1001E00000D4201300D5606500D4E01C00D5201C8D +:1001F00000D5601C008000000006200100C60843F6 +:1002000000CA0C0000CA1000009483F700CA140052 +:1002100000E420F30080007900D4201300C60843D6 +:1002200000CA0C0000CA1000009883EF00CA140036 +:1002300000D400640080008D0000000000C414326F +:1002400000C6184300C4082F0095400500C40C30B8 +:1002500000D4401E0080000000EE001E009583F5D3 +:1002600000C4103100D4403300D5206500D4A01C58 +:1002700000D4E01C00D5201C00E4015E00D4001E68 +:10028000008000000006200100CA1800000A2001BA +:1002900000D6007600C408360098800700C61045D6 +:1002A0000095011000D4001F00D46062008000009F +:1002B00000D4206200CC383500CC1433008401BB5C +:1002C00000D4007200D5401E0080000000EE001E29 +:1002D00000E2001A008401BB00E2001A00CC104BBF +:1002E00000CC0447002C9401007D098B0098400548 +:1002F000007D15CB00D4001A008001B800D4006D39 +:100300000034440100CC0C480098403A00CC2C4A00 +:100310000095800400CC0449008001B800D4001A84 +:1003200000D4C01A00282801008400F000CC10037B +:100330000098801B0004380C008400F000CC1003EF +:100340000098801700043808008400F000CC1003E7 +:100350000098801300043804008400F000CC1003DF +:100360000098801400CC104C009A800900CC144DE9 +:10037000009840DC00D4006D00CC184800D5001A6D +:1003800000D5401A008000C900D5801A0096C0D55B +:1003900000D4006D008001B800D4006E009AC00344 +:1003A00000D4006D00D4006E0080000000EC007FDF +:1003B000009AC0CC00D4006D008001B800D4006E5B +:1003C00000CC140300CC180300CC1C03007D910367 +:1003D000007DD583007D190C0035CC1F0035701FC2 +:1003E000007CF0CB007CD08B00880000007E8E8BE0 +:1003F0000095C00400D4006E008001B800D4001A3B +:1004000000D4C01A00CC080300CC0C0300CC1003AD +:1004100000CC140300CC180300CC1C0300CC240334 +:1004200000CC28030035C41F0036B01F007C704B81 +:100430000034F01F007C704B0035701F007C704B47 +:10044000007D8881007DCCC1007E5101007E9541F8 +:10045000007C9082007CD4C2007C848B009AC00314 +:10046000007C8C8B002C88010098809E00D4006D4D +:100470000098409C00D4006E00CC084C00CC0C4D81 +:1004800000CC104800D4801A00D4C01A00800101AA +:1004900000D5001A00CC083200D40032009482D972 +:1004A00000CA0C0000D4401E0080000000D4001ED2 +:1004B00000E4011E00D4001E00CA080000CA0C009F +:1004C00000CA100000D4401E00CA140000D4801ED0 +:1004D00000D4C01E00D5001E00D5401E00D54034FB +:1004E0000080000000EE001E0028040400E2001A54 +:1004F00000E2001A00D4401A00CA380000CC0803F9 +:1005000000CC0C0300CC0C0300CC0C03009882BD83 +:1005100000000000008401BB00D7A06F0080000035 +:1005200000EE001F00CA040000C2FF0000CC083427 +:1005300000C13FFF007C74CB007CC90B007D010F24 +:10054000009902B0007C738B008401BB00D7A06FC0 +:100550000080000000EE001F00CA080000281900FB +:10056000007D898B009580140028140400CA0C00BB +:1005700000CA100000CA1C0000CA240000E2001FCC +:1005800000D4C01A00D5001A00D5401A00CC1803B8 +:1005900000CC2C0300CC2C0300CC2C03007DA58BBD +:1005A000007D9C4700984297000000000080016198 +:1005B00000D4C01A00D4401E00D4801E0080000069 +:1005C00000EE001E00E4011E00D4001E00D4401EF8 +:1005D00000EE001E00CA040000A00000007E828B16 +:1005E00000E4013E00D4001E00D4401E00EE001EB8 +:1005F00000CA040000A00000007E828B00CA080030 +:1006000000248C06000CCC060098C00600CC104ECE +:100610000099000400D4007300E4011E00D4001E01 +:1006200000D4401E00D4801E0080000000EE001E9A +:1006300000CA080000CA0C000034D01800251001C0 +:100640000095002100C17FFF00CA100000CA1400FD +:1006500000CA180000D4801D00D4C01D007DB18BDD +:1006600000C1420200C2C00100D5801D0034DC0E72 +:10067000007D5D4C007F734C00D7401E00D5001EEE +:1006800000D5401E00C1420000C2C00000099C010C +:100690000031DC10007F5F4C007F734C00042802A7 +:1006A000007D838000D5A86F00D5806600D7401EEE +:1006B00000EC005E00C8240200C82402008001B8DB +:1006C00000D6007600D4401E00D4801E00D4C01E88 +:1006D0000080000000EE001E0080000000EE001F01 +:1006E00000D4001F0080000000D4001F00D4001FB1 +:1006F0000088000000D4001F00000000000000007F +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000010171000201780003008F0004007FE5 +:10081000000500030006003F000700320008012C1D +:1008200000090046000A0036001001B6001700A2B9 +:100830000022013A00230149002000B400240125D0 +:100840000027004D0028006A002A0060002B00529B +:10085000002F0065003200870034017F003C015604 +:10086000003F00720041018C0044012E00550173CD +:100870000056017A0060000B00610034006200380D +:1008800000630038006400380065003800660038F6 +:10089000006700380068003A00690041006A0048BB +:1008A000006B0048006C0048006D0048006E004876 +:1008B000006F00480000000600000006000000066F +:1008C0000000000600000006000000060000000610 +:1008D0000000000600000006000000060000000600 +:1008E00000000006000000060000000600000006F0 +:1008F00000000006000000060000000600000006E0 +:00000001FF diff --git a/firmware/radeon/RV670_me.bin.ihex b/firmware/radeon/RV670_me.bin.ihex new file mode 100644 index 000000000000..9fbfc0e4438c --- /dev/null +++ b/firmware/radeon/RV670_me.bin.ihex @@ -0,0 +1,1345 @@ +:1000000000000000C020040000000000000000000C +:1000100000A0000A000000000000FFFF00284621A9 +:100020000000000000000000D900480000000000AF +:1000300000000000C02004000000000000000000DC +:1000400000A0000A000000000000000000E0000026 +:100050000000000000010000C02946200000000050 +:1000600000000000D900480000000000000000006F +:10007000C0200400000000000000000000A0000AF2 +:10008000000000008100000000204411000000007A +:1000900000000001002048110000000000042004BE +:1000A000006044110000067C0000000000600000B9 +:1000B0000000062400000000006000000000063878 +:1000C00000000000C02008000000000000000F0039 +:1000D000002816220000000000000008002116255C +:1000E000000000000000001800203625000000007D +:1000F0008D000000002044110000000000000004FA +:10010000002F022500000000000000000CE00000AD +:1001100000000018004120000040481100000019B4 +:100120000042200000204811000000008E00000066 +:1001300000204411000000000000002800204A2D8B +:1001400000000000900000000020441100000000AA +:100150000000000000204805000000000000000C26 +:1001600000211622000000000000000300281625D0 +:10017000000000000000001900211A220000000009 +:100180000000000400281A26000000000000000003 +:10019000002914C5000000000000001900203625C9 +:1001A0000000000000000000003A140200000000FF +:1001B00000000016002116250000000000000003CA +:1001C00000281625000000000000001700200E2D5A +:1001D00000000000FFFFFFFC00280E2300000000CD +:1001E00000000000002914A3000000000000001718 +:1001F00000203625000000000000800000280E22AC +:10020000000000000000000700220E230000000094 +:10021000000000000029386E0000000020000000EF +:1002200000280E22000000000000000600210E231E +:1002300000000000000000000029386E00000000EF +:100240000000000000220222000000000000000068 +:1002500014E0000000000038000000002EE0000064 +:1002600000000035000000002CE000000000003716 +:100270000000000000400E2D0000003900000008C2 +:1002800000200E2D00000000000000090040122D8B +:10029000000000460000000100400E2D0000003963 +:1002A00000000000C0200C0000000000003FFFFC28 +:1002B0000028122300000000000000020022122487 +:1002C000000000000000001F00211E2300000000AD +:1002D0000000000014E000000000003E00000008E4 +:1002E00000401C11000000410000000D00201E2DE8 +:1002F000000000000000000F00281E270000000082 +:100300000000000300221E27000000007FC0000044 +:1003100000281A23000000000000001400211A2603 +:10032000000000000000000100331A260000000059 +:100330000000000800221A26000000000000000053 +:1003400000290CC700000000000000270020362410 +:100350000000000000007F000028122100000000C3 +:1003600000001400002F0224000000000000000024 +:100370000CE000000000004B0000000100290E23EB +:10038000000000000000000E0020362300000000E6 +:100390000000E0000020441100000000FFF8000011 +:1003A00000294A230000000000000000003A2C024F +:1003B000000000000000000200220E2B00000000E0 +:1003C000FC00000000280E23000000000000000FC9 +:1003D000002036230000000000001FFF00294A23F0 +:1003E000000000000000002700204A2D000000004F +:1003F000000000000020481100000000000000295B +:1004000000200E2D00000000060A020000294A23E9 +:100410000000000000000000002048110000000063 +:100420000000000000204811000000000000000152 +:1004300000210222000000000000000014E0000083 +:1004400000000061000000002EE000000000005FDE +:10045000000000002CE000000000005E0000000032 +:1004600000400E2D000000620000000100400E2D33 +:10047000000000620000000A00200E2D00000000B5 +:100480000000000B0040122D0000006A0000000078 +:10049000C0200C0000000000003FFFFC00281223D9 +:1004A00000000000000000020022122400000000F2 +:1004B0007FC0000000281623000000000000001488 +:1004C0000021162500000000000000010033162561 +:1004D000000000008000000000280E230000000043 +:1004E0000000000000290CA3000000003FFFFC00FA +:1004F00000290E23000000000000001F00211E2321 +:10050000000000000000000014E000000000006D8A +:100510000000010000401C11000000700000000DF0 +:1005200000201E2D00000000000000F000281E2703 +:10053000000000000000000400221E270000000050 +:100540008100000000204411000000000000000DA8 +:100550000020481100000000FFFFF0FF00281A30C3 +:10056000000000000000A02800204411000000004E +:1005700000000000002948E6000000000000A0186C +:1005800000204411000000003FFFFFFF00284A2325 +:10059000000000000000A010002044110000000036 +:1005A00000000000002048040000000000000030AF +:1005B0000020162D00000000000000020029162572 +:1005C0000000000000000030002036250000000080 +:1005D000000000250020162D000000000000000093 +:1005E000002F00A300000000000000000CC000006D +:1005F00000000083000000260020162D00000000EF +:1006000000000000002F00A4000000000000000017 +:100610000CC000000000008400000000004000004A +:100620000000008A000000250020362300000000A2 +:100630000000002600203624000000000000001703 +:1006400000201E2D000000000000000200210227F3 +:10065000000000000000000014E000000000008A1C +:1006600000000000006000000000065900000000CB +:10067000006000000000064D0000000200210E2274 +:10068000000000000000000014C000000000008D09 +:1006900000000012C040362000000093000000005F +:1006A0002EE0000000000091000000002CE000009F +:1006B000000000900000000200400E2D000000929B +:1006C0000000000300400E2D000000920000000C0E +:1006D00000200E2D00000000000000120020362334 +:1006E000000000000000000300210E2200000000B6 +:1006F0000000000014C00000000000980000A00CE2 +:10070000002044110000000000000000C02048004C +:100710000000000000000000C0404800000000A0F1 +:100720000000A00C002044110000000000000000A8 +:100730000020481100000000000000002EE0000032 +:100740000000009E000000002CE000000000009D62 +:100750000000000200400E2D0000009F000000037A +:1007600000400E2D0000009F0000000C00200E2D08 +:10077000000000000000000000204803000000000E +:1007800000000000003A0C0200000000003F0000E2 +:1007900000280E23000000000000001000210E239E +:1007A00000000000000000110020362300000000BF +:1007B0000000001E0021022B0000000000000000CD +:1007C00014C00000000000A700000016C020362062 +:1007D000000000000000001F0021022B00000000AC +:1007E0000000000014C00000000000AA0000001576 +:1007F000C0203620000000000000000800210E2B61 +:10080000000000000000007F00280E230000000010 +:1008100000000000002F0223000000000000000084 +:100820000CE00000000000E10000000027000000D4 +:10083000000000000000000000600000000002A3B3 +:1008400000000001002F0223000000000000000053 +:100850000AE00000000000B300000000006000009B +:100860000000013A81000000002044110000000057 +:100870000000000600204811000000000000000CED +:1008800000221E300000000099800000002044116A +:1008900000000000000000040020122D00000000F5 +:1008A00000000008002212240000000000000010D8 +:1008B00000201811000000000000000000291CE4C6 +:1008C0000000000000000000006048070000012F49 +:1008D0009B00000000204411000000000000000008 +:1008E00000204802000000009C000000002044118D +:1008F00000000000000000000033146F0000000042 +:100900000000000100333E23000000000000000052 +:10091000D9004800000000000000000000203C0555 +:1009200000000000810000000020441100000000D1 +:100930000000000E00204811000000000000000030 +:1009400000201010000000000000E007002044110B +:10095000000000000000000F0021022B000000003A +:100960000000000014C00000000000CB00F8FF08E9 +:1009700000204811000000009800000000404811CD +:10098000000000DC000000F000280E220000000043 +:10099000000000A0002F0223000000000000000063 +:1009A0000CC00000000000DA0000001100200E2D35 +:1009B0000000000000000001002F022300000000E2 +:1009C000000000000CE00000000000D50000000264 +:1009D000002F022300000000000000000CE00000D7 +:1009E000000000D400003F0000400C11000000D6C1 +:1009F00000001F0000400C11000000D600000F0096 +:100A000000200C11000000000038000900294A23D2 +:100A1000000000003F00000000280E2B0000000036 +:100A20000000000200220E2300000000000000076A +:100A300000494A23000000DC00380F09002048115B +:100A400000000000680000070020481100000000BE +:100A50000000000800214A270000000000000000FC +:100A60000020481100000000060A020000294A2464 +:100A700000000000000000000020481100000000FD +:100A80000000000000204811000000000000A20249 +:100A9000002044110000000000FF000000280E228A +:100AA000000000000000008000294A230000000030 +:100AB0000000002700200E2D00000000000000268E +:100AC0000020122D0000000000000000002F008315 +:100AD00000000000000000000CE00000000000EA40 +:100AE000000000000060000000000653000000004D +:100AF00000400000000000EB00000000006000006B +:100B000000000656000000070020222D0000000013 +:100B10000000000500220E2200000000001000006E +:100B200000280E23000000000000000000292068BB +:100B30000000000000000000003A0C02000000006D +:100B4000000000EF00280E2300000000000000005D +:100B500000292068000000000000001700200E2D72 +:100B6000000000000000000300210223000000003C +:100B70000000000014E00000000000F80000000B7E +:100B800000210228000000000000000014C0000046 +:100B9000000000F8000004000029222800000000E6 +:100BA0000000001400203628000000000000001C97 +:100BB00000210E22000000000000000014C0000010 +:100BC000000000FD0000A30C002044110000000004 +:100BD0000000000000204811000000000000001E7E +:100BE00000210E22000000000000000014C00000E0 +:100BF0000000010B0000A30F0020441100000000C2 +:100C00000000001100200E2D000000000000000177 +:100C1000002F022300000000000000000CC00000B4 +:100C200000000104FFFFFFFF004048110000010B1E +:100C300000000002002F022300000000000000005E +:100C40000CC00000000001070000FFFF0040481139 +:100C50000000010B00000004002F02230000000030 +:100C6000000000000CC000000000010A000000FFAE +:100C7000004048110000010B000000010020481155 +:100C8000000000000002C400002044110000000029 +:100C90000000001F00210E220000000000000000E4 +:100CA00014C00000000001120000001040210E20BE +:100CB00000000000000000130020362300000000A8 +:100CC0000000001840224A20000000000000001030 +:100CD000C0424A20000001140000000000200C1156 +:100CE0000000000000000013002036230000000078 +:100CF000000000000020481100000000000000007B +:100D000000204811000000000000000A002010111F +:100D10000000000000000000002F0224000000007E +:100D2000000000000CE000000000011B00000000BB +:100D300000204811000000000000000100531224B0 +:100D400000000117FFBFFFFF00283A2E000000003F +:100D50000000001B00210222000000000000000033 +:100D600014C000000000012E81000000002044118A +:100D7000000000000000000D0020481100000000ED +:100D80000000001800220E3000000000FC000000EF +:100D900000280E2300000000810000000020441104 +:100DA000000000000000000E0020481100000000BC +:100DB0000000000000201010000000000000E00E05 +:100DC000002044110000000007F8FF08002048112F +:100DD000000000000000000000294A23000000007D +:100DE0000000001C00201E2D000000000000000874 +:100DF00000214A27000000000000000000204811E8 +:100E000000000000060A020000294A240000000039 +:100E10000000000000204811000000000000000059 +:100E200000204811000000000000000000800000C9 +:100E300000000000810000000020441100000000BC +:100E40000000000100204811000000000000217C8B +:100E50000020441100000000008000000020481124 +:100E60000000000000000000002048060000000014 +:100E70000000000800214A270000000000000000D8 +:100E800017000000000000000004217F00604411F2 +:100E90000000067C0000001F00210230000000005E +:100EA0000000000014C000000000067B00000004E9 +:100EB00000404C1100000135810000000020441169 +:100EC00000000000000000010020481100000000A8 +:100ED000000021F800204411000000000000001C68 +:100EE0000020481100000000000421F900604411B6 +:100EF0000000067C0000001100210230000000000C +:100F00000000000014E000000000013C00000000B0 +:100F100000800000000000000000000000600000F1 +:100F20000000000B00000000006004110000031529 +:100F3000000000000020041100000000000000007C +:100F400000600811000001B2000000000060000015 +:100F5000000001600000FFFF40280E20000000009C +:100F600000000010C0211220000000000000FFFF60 +:100F7000402806200000000000000010C0210A20C8 +:100F800000000000000000000034146100000000B8 +:100F90000000000000741882000002BB0001A1FDE7 +:100FA00000604411000002E000003FFF002F022F0C +:100FB00000000000000000000CC00000000001471D +:100FC00000000000C040040000000001000000001C +:100FD000006000000000000B000000000060041131 +:100FE00000000315000000000020041100000000B4 +:100FF0000000000000600811000001B200003FFF87 +:10100000002F022F00000000000000000CE0000094 +:10101000000000000000000000600000000001600F +:101020000000001040210E20000000000000FFFF23 +:10103000C0281220000000000000001040211620EF +:10104000000000000000FFFFC0681A20000002BB83 +:101050000001A1FD00604411000002E000003FFF1C +:10106000002F022F00000000000000000CC0000054 +:101070000000015800000000C04004000000000112 +:101080000000225C0020441100000000000000016C +:1010900000300A2F000000000000000100210A2299 +:1010A000000000000000000300384A220000000099 +:1010B0000000225600204411000000000000001A29 +:1010C00000204811000000000000A1FC0020441195 +:1010D0000000000000000001008048110000000036 +:1010E00000000000006000000000000B0000000095 +:1010F000006000000000018F0000000000600000A0 +:10110000000001A000003FFF002F022F00000000A0 +:10111000000000000CE000000000000000000000E3 +:1011200000202C0800000000000000000020241116 +:101130000000000000000000002028110000000056 +:10114000000022560020441100000000000000169C +:1011500000204811000000000000225C0020441123 +:101160000000000000000003002048110000000003 +:1011700093800000002044110000000000000002E5 +:1011800000221E290000000000000000007048EB53 +:101190000000019C0000000000600000000002BB95 +:1011A00000000001403306200000000000000000A5 +:1011B000C03024090000000000003FFF002F022F74 +:1011C00000000000000000000CE000000000000033 +:1011D0000000000000600000000002A3000000000A +:1011E000002F022100000000000000000AE00000C3 +:1011F0000000018100000000006000000000013AD2 +:101200000000000000400000000001869500000082 +:10121000002044110000000000000000002F022107 +:1012200000000000000000000CE00000000001864B +:1012300000000000C0204800000000000000000185 +:10124000005306210000018292000000002044119A +:101250000000000000000000C0604800000001978E +:101260000001A1FD00204411000000000000001159 +:101270000020062D00000000000000000078042A75 +:10128000000002FB00000000002028090000000010 +:1012900000003FFF002F022F0000000000000000B0 +:1012A0000CC000000000017400000000C0400400F9 +:1012B000000000010000021000600411000003158E +:1012C00000003FFF002F022F000000000000000080 +:1012D0000CE000000000019400000015C020362042 +:1012E0000000000000000016C020362000000000B2 +:1012F0003F800000002004110000000046000000B4 +:1013000000600811000001B2000000000080000031 +:10131000000000000000A1FC0020441100000000BB +:1013200000003FFF002F022F00000000000000001F +:101330000CC000000000019B00000001008048116B +:1013400000000000000000210080481100000000A3 +:101350000000FFFF40280E200000000000000010E9 +:10136000C0211220000000000000FFFF40281620CE +:101370000000000000000010C0811A2000000000E2 +:101380008100000000204411000000000000000661 +:1013900000204811000000000000000800221E305C +:1013A000000000000000002900201A2D00000000AD +:1013B0000000E0000020441100000000FFFBFF09D6 +:1013C00000204811000000000000000F0020222D26 +:1013D0000000000000001FFF00294A280000000054 +:1013E000000000060020222D000000000000000088 +:1013F000002920E80000000000000000002048084C +:101400000000000000000000002048110000000063 +:10141000060A020000294A26000000000000000021 +:1014200000204811000000000000000000204811CA +:101430000000000000000100002018110000000062 +:101440000000000800621E280000012F00000008B4 +:1014500000822228000000000002C0000020441189 +:10146000000000000000001500600E2D000001BD0E +:101470000000001600600E2D000001BD0000C00835 +:1014800000204411000000000000001700200E2D75 +:10149000000000000000000014C00000000001B9BE +:1014A0000000000000200411000000000000000007 +:1014B0000020480100000000390000000020481111 +:1014C00000000000000000000020481100000000A3 +:1014D000000000000080480200000000000000182A +:1014E00000202E2D0000000000000000003B0D63D6 +:1014F000000000000000000800224A230000000055 +:101500000000001000224A23000000000000001824 +:1015100000224A2300000000000000000080480371 +:101520000000000000000000006000000000000B50 +:10153000000010000060041100000315000000000E +:1015400000200411000000000000000000600811ED +:10155000000001B2000000070021062F000000007B +:101560000000001300200A2D000000000000000110 +:1015700000202C11000000000000FFFF4028222066 +:10158000000000000000000F0026222800000000DC +:101590000000001040212620000000000000000F85 +:1015A000002626290000000000000000002028027C +:1015B000000000000000225600204411000000003E +:1015C0000000001B00204811000000000000000087 +:1015D000002F022100000000000000000CE00000CD +:1015E000000001E00000225C002044110000000027 +:1015F0000000008100204811000000000000A1FC54 +:1016000000204411000000000000000100204811EB +:10161000000000000000008000201C1100000000FD +:1016200000000000002F0227000000000000000062 +:101630000CE00000000001DC000000000060000081 +:10164000000001E90000000100531E27000001D83E +:101650000000000100202C11000000000000001F0D +:1016600000280A22000000000000001F00282A2A8B +:10167000000000000000000100530621000001D11D +:101680000000225C00204411000000000000000265 +:1016900000304A2F000000000000A1FC002044118F +:1016A00000000000000000010020481100000000C0 +:1016B0000000000100301E2F0000000000000000AC +:1016C000002F022700000000000000000CE00000D6 +:1016D000000000000000000000600000000001E9C0 +:1016E0000000000100531E27000001E50000FFFF7D +:1016F00040280E20000000000000000F00260E23EE +:101700000000000000000010C021122000000000B6 +:101710000000000F0026122400000000000000005E +:1017200000201411000000000000000000601811EB +:10173000000002BB0001A1FD0020441100000000D8 +:1017400000000000002F022B00000000000000003D +:101750000CE00000000001F8000000100022162834 +:1017600000000000FFFF0000002816250000000018 +:101770000000FFFF00281A29000000000000000000 +:10178000002948C500000000000000000020480AB1 +:10179000000000000000000000202C1100000000EC +:1017A000000000100022162300000000FFFF0000D0 +:1017B00000281625000000000000FFFF00281A2462 +:1017C0000000000000000000002948C500000000E3 +:1017D0000000000000731503000002050000000077 +:1017E0000020180500000000000000000073152410 +:1017F0000000020500000000002D14C500000000DC +:1018000000000000003008A20000000000000000FE +:101810000020480200000000000000000020280214 +:101820000000000000000000002020030000000075 +:101830000000000000802404000000000000000FF1 +:1018400000210225000000000000000014C000007C +:101850000000067B00000000002B140500000000C3 +:1018600000000001009016250000000000000000AC +:10187000006000000000000B000000000060041188 +:10188000000003150000000000200411000000000B +:101890000000000000600811000001B200002256A4 +:1018A00000204411000000000000001A00294A2214 +:1018B0000000000000000000C02000000000000048 +:1018C00000003FFF002F022F00000000000000007A +:1018D0000CE000000000000000000000C020040038 +:1018E000000000000000225C002044110000000005 +:1018F0000000000300384A21000000000000A1FCA5 +:1019000000204411000000000000000100204811E8 +:10191000000000000000FFFF40281220000000002F +:1019200000000010C0211A20000000000000FFFF8E +:1019300040280E200000000000000010C0211620EA +:10194000000000000000000000741465000002BBED +:101950000001A1FD00604411000002E00000000150 +:10196000003306210000000000000000002F0221CB +:1019700000000000000000000CC000000000021980 +:1019800000003FFF002F022F0000000000000000B9 +:101990000CC000000000021200000000C040040063 +:1019A0000000000100000000006000000000063898 +:1019B000000000000040040F0000021300000000BF +:1019C000006000000000062400000000006000002D +:1019D000000006380000021000600411000003152A +:1019E0000000000000600000000001A000000000F6 +:1019F000006000000000019C00000000006000008A +:101A0000000002BB0000000000600000000002A314 +:101A1000938000000020441100000000000000003E +:101A2000002048080000000000000000002F022FE6 +:101A300000000000000000000AE000000000023288 +:101A400000000000006000000000013A00000000FB +:101A50000040000000000236950000000020441104 +:101A60000000000000000000002F022F0000000016 +:101A7000000000000CE00000000002360000000042 +:101A8000C0404800000002339200000000204411D2 +:101A90000000000000000000C0204800000000001E +:101AA0000000225600204411000000000000001633 +:101AB00000204811000000000000225C00204411BA +:101AC000000000000000000300204811000000009A +:101AD0000000A1FC002044110000000000000001F3 +:101AE00000204811000000000001A1FD0020441169 +:101AF000000000000000000000600411000002FB74 +:101B000000000000C04004000000000100000000D0 +:101B100000600000000006240000A00C002044111A +:101B20000000000000000000C0204800000000008D +:101B300000000000C040480000000000000000005D +:101B4000006000000000000B0000001840210A2087 +:101B50000000000000000003002F0222000000002F +:101B6000000000000AE000000000024C0000001429 +:101B70000020222D00000000000801010029222879 +:101B800000000000000000140020362800000000C3 +:101B90000000A30C00204411000000000000000021 +:101BA000C02048000000000000000000C0204800E5 +:101BB0000000000000000000C0404800000002518A +:101BC00000000000006000000000000B000000109A +:101BD00000600411000003153F8000000020041184 +:101BE000000000000000000000600811000001B2C9 +:101BF0000000225C002044110000000000000003EF +:101C000000204811000000000000000000600000FB +:101C10000000027C0000001700201E2D00000000C4 +:101C20000000000100211E2700000000000000004D +:101C300014E000000000026A0000001200201E2DC7 +:101C4000000000000000FFFF00281E270000000029 +:101C50000000000000341C2700000000000000000D +:101C600012C000000000025F0000000000201C11F4 +:101C70000000000000000000002F00E50000000050 +:101C80000000000008C00000000002620000000028 +:101C900000201407000000000000001200201E2D8C +:101CA000000000000000001000211E2700000000BE +:101CB0000000000000341C4700000000000000008D +:101CC00012C00000000002670000000000201C118C +:101CD0000000000000000000002F00E600000000EF +:101CE0000000000008C000000000026A00000000C0 +:101CF0000020180700000000000000000060000045 +:101D0000000002C100002256002044110000000023 +:101D1000000000000034202300000000000000004C +:101D200012C00000000002720000000000342044D5 +:101D3000000000000000000012C00000000002715E +:101D40000000001600404811000002760000001854 +:101D500000404811000002760000000000342044DA +:101D6000000000000000000012C00000000002752A +:101D70000000001700404811000002760000001922 +:101D800000204811000000000000A1FC00204411C8 +:101D900000000000000000010020481100000000C9 +:101DA0000001A1FD00604411000002E900003FFFB6 +:101DB000002F022F00000000000000000CC00000F7 +:101DC0000000025600000000C040040000000001B6 +:101DD0000000001040210620000000000000FFFF6E +:101DE000C0280A20000000000000001040210E2042 +:101DF000000000000000FFFFC028122000000000CB +:101E00000000001040211620000000000000FFFF2D +:101E1000C0881A200000000081000000002044114A +:101E20000000000000000001002048110000000038 +:101E300000042004006044110000067C0000000043 +:101E4000006000000000062400000000C0600000E8 +:101E5000000002A30000000500200A2D0000000081 +:101E60000000000800220A22000000000000002BF1 +:101E700000201A2D000000000000001C00201E2D74 +:101E8000000000000000700000281E270000000075 +:101E90000000000000311CE6000000000000002AE5 +:101EA00000201A2D000000000000000C00221A265D +:101EB0000000000000000000002F00E6000000000D +:101EC0000000000006E00000000002920000000098 +:101ED00000201C11000000000000000000200C1178 +:101EE000000000000000002B00203623000000004E +:101EF0000000001000201811000000000000000089 +:101F000000691CE20000012F9380000000204411B2 +:101F10000000000000000000002048070000000052 +:101F200095000000002044110000000000000000A7 +:101F3000002F022F00000000000000000CE0000055 +:101F40000000029D0000000100333E2F0000000051 +:101F500000000000D90048000000000092000000CE +:101F6000002044110000000000000000C0204800D4 +:101F7000000000000000001C0040362700000000A8 +:101F80000000000CC0220A20000000000000002910 +:101F9000002036220000000000000028C04036204B +:101FA000000000000000A2A4002044110000000076 +:101FB000000000090020481100000000A1000000FE +:101FC00000204411000000000000000100804811C2 +:101FD000000000000000002100201E2D0000000075 +:101FE00000000000002C1CE30000000000000021A5 +:101FF00000203627000000000000002200201E2DD7 +:102000000000000000000000002C1CE400000000A4 +:1020100000000022002036270000000000000023FE +:1020200000201E2D0000000000000000003120A351 +:102030000000000000000000002D1D07000000004F +:1020400000000023002036270000000000000024CC +:1020500000201E2D0000000000000000003120C400 +:102060000000000000000000002D1D07000000001F +:10207000000000240080362700000000000000213E +:10208000002036230000000000000022002036243B +:10209000000000000000000000311CA30000000050 +:1020A0000000002300203627000000000000000090 +:1020B00000311CC40000000000000024008036270E +:1020C000000000000000001A002036270000000079 +:1020D0000000001B00203628000000000000001750 +:1020E00000201E2D00000000000000020021022739 +:1020F000000000000000000014C00000000002DC2E +:102100000000000000400000000002D90000001A9A +:1021100000203627000000000000001B00203628A9 +:10212000000000000000001700201E2D000000002D +:102130000000000200210227000000000000000053 +:1021400014E00000000002D9000000030021022773 +:10215000000000000000000014E00000000002DCAD +:102160000000002300201E2D0000000000000000E1 +:10217000002E00E1000000000000000002C000008E +:10218000000002DC0000002100201E2D00000000E5 +:1021900000000000003120A100000000000000004D +:1021A000002E00E8000000000000000006C0000053 +:1021B000000002DC0000002400201E2D00000000B2 +:1021C00000000000002E00E20000000000000000FF +:1021D00002C00000000002DC0000002200201E2DD2 +:1021E0000000000000000000003120C200000000DC +:1021F00000000000002E00E80000000000000000C9 +:1022000006C00000000002DC0000000000600000CA +:10221000000006590000000000600000000002B548 +:102220000000000000400000000002DE000000008E +:1022300000600000000002B5000000000060000027 +:10224000000006500000000000400000000002DE18 +:102250000000000000600000000002A70000000075 +:1022600000400000000002DE0000001A00201E2DC9 +:10227000000000000000001B0080222D0000000074 +:102280000000001000221E230000000000000000DB +:1022900000294887000000000000000000311CA356 +:1022A000000000000000001000221E2700000000B7 +:1022B0000000000000294887000000000000001016 +:1022C00000221E230000000000000000003120C496 +:1022D000000000000000FFFF00282228000000008E +:1022E0000000000000894907000000000000001005 +:1022F00000221E2300000000000000000029488783 +:10230000000000000000001000221E21000000005C +:102310000000000000294847000000000000000005 +:1023200000311CA3000000000000001000221E2746 +:1023300000000000000000000029488700000000A5 +:102340000000000000311CA100000000000000108F +:1023500000221E270000000000000000002948475E +:10236000000000000000001000221E2300000000FA +:1023700000000000003120C4000000000000FFFF4A +:102380000028222800000000000000000029490762 +:10239000000000000000001000221E2100000000CC +:1023A00000000000003120C2000000000000FFFF1C +:1023B00000282228000000000000000000894907D2 +:1023C000000000000000001000221E23000000009A +:1023D0000000000000294887000000000000000104 +:1023E00000220A210000000000000000003308A2C3 +:1023F000000000000000001000221E22000000006B +:102400000000001000212222000000000000000057 +:1024100000294907000000000000000000311CA353 +:10242000000000000000001000221E270000000035 +:1024300000000000002948870000000000000001A3 +:1024400000220A210000000000000000003008A265 +:10245000000000000000001000221E22000000000A +:1024600000000010002122220000000000000000F7 +:1024700000294907000000000000001000221E2370 +:102480000000000000000000003120C40000000037 +:102490000000FFFF002822280000000000000000CC +:1024A000002949070000000000000000003808C5AE +:1024B00000000000000000000030084100000000A3 +:1024C0000000000100220A220000000000000000BD +:1024D000003308A2000000000000001000221E22AD +:1024E0000000000000000010002122220000000077 +:1024F00000000000008949070000000000000017EC +:102500000020222D000000000000000014C0000088 +:1025100000000318FFFFFFEF002806210000000065 +:10252000000000140020222D000000000000F8E050 +:1025300000204411000000000000000000294901B3 +:1025400000000000000000000089490100000000B8 +:102550000000000000204811000000000000000002 +:102560000020481100000000060A02000080481107 +:102570000000000000000000C0200000000000007B +:1025800097000000C020441100000000000000007F +:10259000C0204811000000008A0000000020441103 +:1025A00000000000000000000020481100000000B2 +:1025B0000000225C00204411000000000000000028 +:1025C000C0204800000000000000A1FC00204411D1 +:1025D0000000000000000000C020480000000000D3 +:1025E00000000000C0200400000000000000000007 +:1025F00000A0000A00000000970000000020441125 +:102600000000000000000000002048110000000051 +:102610008A000000002044110000000000000000BB +:1026200000204811000000000000225C002044113E +:102630000000000000000000C02048000000000072 +:102640000000A1FC00204411000000000000000078 +:10265000C02048000000000000000000C02004006E +:10266000000000000000000000A0000A00000000C0 +:10267000970000000020441100000000000000004E +:1026800000204811000000008A00000000204411D2 +:1026900000000000000000000020481100000000C1 +:1026A0000000225C00204411000000000000000037 +:1026B000C0204800000000000000A1FC00204411E0 +:1026C0000000000000000000C020480000000000E2 +:1026D0000001A1FD002044110000000000000000E6 +:1026E000D90048000000000000000000C0200400E5 +:1026F000000000000000000000A0000A0000000030 +:1027000000002257002044110000000000000003D8 +:10271000C0484A20000000000000225D0020441153 +:102720000000000000000000C04048000000000061 +:1027300000000000006000000000063800000000FB +:10274000C0200800000000000000225C00204411AE +:10275000000000000000000300384A2200000000D2 +:102760000000A1FC00204411000000000000000057 +:10277000C0204800000000000001A1FD002044111D +:102780000000000000000000002F022200000000F6 +:10279000000000000CE0000000000000000000004D +:1027A00040204800000000000000000140304A20A6 +:1027B0000000000000000002C0304A2000000000BD +:1027C0000000000100530A220000034B0000003FFC +:1027D000C0280A20000000008100000000204411F1 +:1027E000000000000000000100204811000000006F +:1027F000000021F800204411000000000000001833 +:102800000020481100000000000421F9006044117C +:102810000000067C000000110021023000000000D2 +:102820000000000014E00000000003540000001449 +:10283000002F022200000000000000000CC0000079 +:10284000000003620001A2A4002044110000000067 +:1028500000000000006048020000036A0000210040 +:10286000002044110000000000000000C0204800CB +:102870000000000000000000C02048000000000030 +:1028800000000000C0204800000000000000000020 +:10289000C04048000000000000000004002F022299 +:1028A00000000000000000000CC0000000000366F3 +:1028B0000001A2A40020441100000000000000005C +:1028C000004048020000035D00000028002F0222A3 +:1028D00000000000000000000CC00000000005B374 +:1028E0000001A2A40020441100000000000000002C +:1028F000004048020000035D0000002C0020362646 +:102900000000000000000049002018110000000035 +:102910000000003F002048110000000000000001FE +:1029200000331A260000000000000000002F0226DD +:1029300000000000000000000CC000000000036C5C +:102940000000002C00801A2D000000000000003F55 +:10295000C0280A200000000000000015002F0222FD +:1029600000000000000000000CE0000000000382F6 +:1029700000000006002F02220000000000000000FE +:102980000CE00000000003AD00000016002F022242 +:1029900000000000000000000CE00000000003AF99 +:1029A00000000020002F02220000000000000000B4 +:1029B0000CE00000000003980000000F002F02222E +:1029C00000000000000000000CE00000000003A474 +:1029D00000000010002F0222000000000000000094 +:1029E0000CE00000000003A40000001E002F0222E3 +:1029F00000000000000000000CE000000000038C5C +:102A00000000A2A40020441100000000000000000B +:102A100000404802000000000800000000290A22CF +:102A2000000000000000000340210E200000000014 +:102A30000000000CC021122000000000000800006F +:102A4000002812240000000000000014C0221620FC +:102A50000000000000000000002914A40000000095 +:102A60000000A2A4002044110000000000000000AB +:102A7000002948A2000000000000A1FE002044112F +:102A800000000000000000000040480300000000BB +:102A9000810000000020441100000000000000013F +:102AA0000020481100000000000021F8002044111F +:102AB0000000000000000016002048110000000087 +:102AC000000421F9006044110000067C000000159C +:102AD00000210230000000000000000014E00000AF +:102AE0000000038E0000210E0020441100000000B1 +:102AF00000000000C02048000000000000000000AE +:102B0000C0204800000000000000A2A400204411E2 +:102B1000000000000000000000404802000000002B +:102B200081000000002044110000000000000001AE +:102B30000020481100000000000021F8002044118E +:102B400000000000000000170020481100000000F5 +:102B5000000421F9006044110000067C000000031D +:102B600000210230000000000000000014E000001E +:102B70000000039A0000210800204411000000001A +:102B800000000000C020480000000000000000001D +:102B9000C0204800000000000000A2A40020441152 +:102BA000000000000000000000404802000000009B +:102BB0000000A2A40020441100000000000000005A +:102BC00000204802000000008000000000204411A6 +:102BD000000000000000000000204811000000007C +:102BE00081000000002044110000000000000010DF +:102BF000002048110000000000000000002000102C +:102C0000000000000000000014C00000000003AA43 +:102C10000000000000400000000000000001A2A42D +:102C20000020441100000000000000060040481190 +:102C3000000000000001A2A40020441100000000D8 +:102C400000000016006048110000036A0000000048 +:102C5000004000000000000000000000C02008004C +:102C60000000000000000000C0200C000000000078 +:102C70000000001D002102230000000000000000F1 +:102C800014E00000000003C4810000000020441193 +:102C900000000000000000010020481100000000BA +:102CA000000021F80020441100000000000000187E +:102CB0000020481100000000000421F900604411C8 +:102CC0000000067C0000001100210230000000001E +:102CD0000000000014E00000000003B80000210024 +:102CE0000020441100000000000000000020480205 +:102CF0000000000000000000002048030000000069 +:102D0000BABECAFE0020481100000000CAFEBABECA +:102D100000204811000000000000A2A4002044117F +:102D20000000000000000004004048110000000006 +:102D3000000021700020441100000000000000008D +:102D400000204802000000000000000000204803AE +:102D5000000000008100000000204411000000007D +:102D60000000000A002048110000000000000000E0 +:102D700000200010000000000000000014C000004F +:102D8000000003C98C000000002044110000000076 +:102D9000CAFEBABE004048110000000081000000D9 +:102DA0000020441100000000000000010020481134 +:102DB0000000000000003FFF40280A200000000043 +:102DC0008000000040280E200000000040000000AD +:102DD000C028122000000000000400000069462204 +:102DE0000000067C0000000000201410000000001D +:102DF00000000000002F022300000000000000007F +:102E00000CC00000000003D700000000C040180004 +:102E1000000003DA00003FFFC0281A200000000075 +:102E200000040000006946260000067C0000000047 +:102E3000002018100000000000000000002F0224F5 +:102E400000000000000000000CC00000000003DDD6 +:102E500000000000C0401C00000003E000003FFF35 +:102E6000C0281E2000000000000400000069462762 +:102E70000000067C0000000000201C100000000084 +:102E800000000000002044020000000000000000DC +:102E9000002820C50000000000000000004948E8AC +:102EA00000000000A58000000020081100000000C4 +:102EB0000000200000200C11000000008300000032 +:102EC00000604411000004080000000000204402DB +:102ED0000000000000000000C020480000000000CA +:102EE0000000000040204800000000000000001F1B +:102EF000C0210220000000000000000014C00000FB +:102F0000000003ED0000201000204411000000002C +:102F10000000800000204811000000000000FFFFBA +:102F2000C0481220000003F5A7800000002008110F +:102F3000000000000000A00000200C1100000000B4 +:102F4000830000000060441100000408000000003D +:102F5000002044020000000000000000C0204800E3 +:102F60000000000000000000C02048000000000039 +:102F70000000FFFFC02812200000000083000000B6 +:102F800000204411000000000000000000304883D1 +:102F90000000000084000000002044110000000038 +:102FA00000000000C02048000000000000000000F9 +:102FB0001D000000000000008300000000604411BC +:102FC0000000040800000000C040040000000001F0 +:102FD000A980000000200811000000000000C000CF +:102FE00000400C11000003F0AB800000002008112D +:102FF000000000000000F8E000400C11000003F0A9 +:10300000AD80000000200811000000000000F880E2 +:1030100000400C11000003F0B380000000200811F4 +:10302000000000000000F3FC00400C11000003F061 +:10303000AF80000000200811000000000000E00048 +:1030400000400C11000003F0B180000000200811C6 +:10305000000000000000F00000400C11000003F030 +:1030600083000000002044110000000000002148FF +:1030700000204811000000008400000000204411DE +:103080000000000000000000C02048000000000018 +:10309000000000001D000000000000000000000013 +:1030A000008000000000000001182000C030462011 +:1030B0000000000000000000D900480000000000EF +:1030C00000000000C020040000000000000000001C +:1030D00000A0000A000000000218A000C030462036 +:1030E0000000000000000000D900480000000000BF +:1030F00000000000C02004000000000000000000EC +:1031000000A0000A000000000318C000C0304620E4 +:103110000000000000000000D9004800000000008E +:1031200000000000C02004000000000000000000BB +:1031300000A0000A000000000418F8E0C03046209B +:103140000000000000000000D9004800000000005E +:1031500000000000C020040000000000000000008B +:1031600000A0000A000000000518F880C0304620CA +:103170000000000000000000D9004800000000002E +:1031800000000000C020040000000000000000005B +:1031900000A0000A000000000618E000C030462031 +:1031A0000000000000000000D900480000000000FE +:1031B00000000000C020040000000000000000002B +:1031C00000A0000A000000000718F000C0304620F0 +:1031D0000000000000000000D900480000000000CE +:1031E00000000000C02004000000000000000000FB +:1031F00000A0000A000000000818F3FCC0304620C0 +:103200000000000000000000D9004800000000009D +:1032100000000000C02004000000000000000000CA +:1032200000A0000A000000000000003000200A2D6D +:103230000000000000000000C0290C400000000059 +:1032400000000030002036230000000000000000D5 +:10325000C0200400000000000000000000A0000AE0 +:103260000000000086000000002044110000000063 +:103270000000000000404801000000008500000040 +:10328000C020441100000000000000000040480180 +:10329000000000000000217C00204411000000001C +:1032A00000000000C02048000000000000000000F6 +:1032B000C02048000000000000000000C0204800BE +:1032C0000000000081000000002044110000000008 +:1032D0000000000100204811000000000000000074 +:1032E000C0200800000000000000000017000000DF +:1032F000000000000004217F006044110000067CF3 +:103300000000001F0021023000000000000000004B +:1033100014C00000000000000000000000404C024B +:103320000000043E00000000C0200C00000000006F +:1033300000000000C020100000000000000000009D +:10334000C02014000000000000000000C020180091 +:103350000000000000000000C0201C000000000071 +:1033600000007F0000280A21000000000000450046 +:10337000002F022200000000000000000CE000000E +:103380000000044C00000000C020200000000000ED +:103390000000000017000000000000000000001006 +:1033A00000280A230000000000000010002F022265 +:1033B00000000000000000000CE0000000000454C9 +:1033C0008100000000204411000000000000000106 +:1033D000002048110000000000040000006946249D +:1033E0000000067C000000000040000000000459BE +:1033F00081000000002044110000000000000000D7 +:1034000000204811000000000000216D0020441140 +:103410000000000000000000002048040000000040 +:103420000000000000604805000006810000000068 +:10343000002824F0000000000000000700280A23F4 +:103440000000000000000001002F02220000000028 +:10345000000000000AE0000000000460000000001E +:10346000002F00C9000000000000000004E0000080 +:103470000000047900000000004000000000048605 +:1034800000000002002F02220000000000000000E7 +:103490000AE000000000046500000000002F00C9E1 +:1034A000000000000000000002E0000000000479BD +:1034B000000000000040000000000486000000033F +:1034C000002F022200000000000000000AE00000BF +:1034D0000000046A00000000002F00C90000000086 +:1034E000000000000CE00000000004790000000073 +:1034F000004000000000048600000004002F0222AB +:1035000000000000000000000AE000000000046F5E +:1035100000000000002F00C90000000000000000B3 +:103520000AE00000000004790000000000400000F4 +:103530000000048600000005002F022200000000A9 +:10354000000000000AE00000000004740000000019 +:10355000002F00C9000000000000000006E000008D +:103560000000047900000000004000000000048614 +:1035700000000006002F02220000000000000000F2 +:103580000AE000000000047900000000002F00C9DC +:10359000000000000000000008E0000000000479C6 +:1035A00000000000004000000000048600007F00D2 +:1035B00000280A210000000000004500002F022220 +:1035C00000000000000000000AE000000000000011 +:1035D0000000000800210A23000000000000000095 +:1035E00014C0000000000483000021690020441181 +:1035F0000000000000000000C020480000000000A3 +:1036000000000000C0204800000000000000000092 +:10361000C020480000000000CAFEBABE00404811A9 +:103620000000000000000000C02044000000000076 +:1036300000000000C02000000000000000000000AA +:10364000C04048000000000000007F0000280A2160 +:103650000000000000004500002F022200000000D2 +:10366000000000000AE000000000048C00000000E0 +:10367000C02000000000000000000000C02000008A +:103680000000000000000000C0400000000000003A +:103690000000000000404C080000044C0000000046 +:1036A000C0200800000000000000001040210E2093 +:1036B0000000000000000011402112200000000066 +:1036C00000000012402116200000000000002169C7 +:1036D000002044110000000000000000002048020B +:1036E0000000000000000000002102250000000092 +:1036F0000000000014E00000000004960004000038 +:10370000C0494A2000000497FFFBFFFFC0284A2061 +:103710000000000000000000002102230000000063 +:103720000000000014E00000000004A300000000FE +:10373000C02048000000000000000000C020480039 +:103740000000000000000000002102240000000032 +:103750000000000014C00000000000008100000014 +:1037600000204411000000000000000C002048115F +:103770000000000000000000002000100000000019 +:103780000000000014C000000000049FA000000022 +:103790000020441100000000CAFEBABE00404811DB +:1037A0000000000081000000002044110000000023 +:1037B0000000000400204811000000000000216B00 +:1037C000002044110000000000000000C02048104C +:1037D00000000000810000000020441100000000F3 +:1037E0000000000500204811000000000000216CCE +:1037F000002044110000000000000000C02048101C +:103800000000000000000000002F02240000000063 +:10381000000000000CE000000000000000000000BC +:10382000004000000000049D00000000C0210A20AC +:10383000000000000000000014C00000000004B6FA +:103840008100000000204411000000000000000082 +:1038500000204811000000000000216D00204411EC +:103860000000000000000000C02048000000000030 +:1038700000000000C0604800000006810000000059 +:1038800000400000000004BA810000000020441144 +:1038900000000000000000010020481100000000AE +:1038A00000040000C02946200000000000000000C5 +:1038B000C06000000000067C000000010021022220 +:1038C000000000000000000014C00000000004C15F +:1038D00000002169002044110000000000000000E9 +:1038E000C02048000000000000000000C020480088 +:1038F0000000000000000000002048100000000050 +:10390000CAFEBABE004048110000000000000000DE +:10391000C02044000000000000000000C04048102B +:1039200000000000810000000020441100000000A1 +:10393000000000010020481100000000000021F8F4 +:1039400000204411000000000000000E002048117B +:1039500000000000000421F9006044110000067C12 +:103960000000000000210230000000000000000004 +:1039700014C00000000004C3000021800020441196 +:103980000000000000000000C0204800000000000F +:1039900000000000C0200000000000000000000047 +:1039A000C02048000000000000000000C02000000F +:1039B0000000000000000000C040480000000000BF +:1039C0000000000300333E2F000000000000000153 +:1039D00000210221000000000000000014E00000AF +:1039E000000004F30000002C00200A2D000000005D +:1039F0000004000018E00C11000004E200000001C7 +:103A000000333E2F00000000000021690020441117 +:103A1000000000000000000000204802000000003C +:103A20000000000000204803000000000000000823 +:103A300000300A220000000000000000C020480002 +:103A40000000000000000000C0204800000000004E +:103A50000000216900204411000000000000000067 +:103A60000020480200000000000000000020480381 +:103A7000000000000000000800300A2200000000E2 +:103A800000000000C020480000000000000000000E +:103A9000D8C04800000004D600002169002044116D +:103AA00000000000000000000020480200000000AC +:103AB0000000000000204803000000000000000893 +:103AC00000300A220000000000000000C020480072 +:103AD0000000000000000000C020480000000000BE +:103AE0000000002D0020122D00000000000000004A +:103AF00000290C830000000000002169002044110F +:103B0000000000000000000000204802000000004B +:103B10000000000000204803000000000000000832 +:103B200000300A220000000000000000C020480011 +:103B30000000000000000000C0204800000000005D +:103B4000000000110021022400000000000000001D +:103B500014C0000000000000000000000040000051 +:103B60000000049D0000002CC02036200000000052 +:103B70000000002DC0403620000000000000000FB3 +:103B800000210221000000000000000014C000001D +:103B9000000004F800000000006000000000000BBE +:103BA00000000000D900000000000000000000003C +:103BB000C040040000000001B500000000204411D6 +:103BC000000000000000200000204811000000005C +:103BD000B600000000204411000000000000A0001A +:103BE0000020481100000000B70000000020441130 +:103BF000000000000000C00000204811000000008C +:103C0000B800000000204411000000000000F8E0AF +:103C10000020481100000000B900000000204411FD +:103C2000000000000000F8800020481100000000A3 +:103C3000BA00000000204411000000000000E00075 +:103C40000020481100000000BB00000000204411CB +:103C5000000000000000F0000020481100000000FB +:103C6000BC00000000204411000000000000F3FC34 +:103C700000204811000000008100000000204411D5 +:103C800000000000000000020020481100000000B9 +:103C9000000000FF00280E300000000000000000BF +:103CA000002F022300000000000000000CC00000F4 +:103CB0000000050C00000000C0200800000000000B +:103CC0000000000014C000000000052100000000FA +:103CD00000200C11000000000000001C0020362312 +:103CE000000000000000002B002036230000000030 +:103CF00000000029002036230000000000000028FA +:103D000000203623000000000000001700203623AA +:103D10000000000000000025002036230000000005 +:103D200000000026002036230000000000000015DF +:103D3000002036230000000000000016002036237B +:103D400000000000FFFFE00000200C110000000058 +:103D500000000021002036230000000000000022A7 +:103D6000002036230000000000001FFF00200C117F +:103D700000000000000000230020362300000000A7 +:103D8000000000240020362300000000F1FFFFFFA8 +:103D900000283A2E000000000000001AC0220E2069 +:103DA00000000000000000000029386E0000000044 +:103DB0008100000000204411000000000000000607 +:103DC00000204811000000000000002A402036209A +:103DD00000000000870000000020441100000000E7 +:103DE00000000000C0204800000000000000A1F416 +:103DF00000204411000000000000000000204810D6 +:103E0000000000000000000000200C110000000075 +:103E10000000003000203623000000009D0000005C +:103E200000204411000000000000001F40214A2033 +:103E30000000000096000000002044110000000077 +:103E400000000000C020480000000000000000004A +:103E5000C0200C000000000000000000C020100086 +:103E6000000000000000001F0021162400000000D8 +:103E70000000000014C00000000000000000001D51 +:103E800000203623000000000000000300281E234D +:103E900000000000000000080022222300000000B3 +:103EA000FFFFF000002822280000000000000000B2 +:103EB000002920E8000000000000001F0020362834 +:103EC000000000000000001800211E230000000078 +:103ED0000000002000203627000000000000000243 +:103EE000002216240000000000000000003014A88A +:103EF000000000000000001E002036250000000029 +:103F00000000000300211A2400000000100000003F +:103F100000281A2600000000EFFFFFFF00283A2EBD +:103F20000000000000000000004938CE0000066AD2 +:103F30000000000140280A200000000000000006E8 +:103F400040280E200000000000000300C0281220BE +:103F50000000000000000008002112240000000002 +:103F600000000000C020162000000000000000003B +:103F7000C0201A20000000000000000000210222E2 +:103F8000000000000000000014C0000000000559FF +:103F9000810000000020441100000000000000012A +:103FA00000204811000000000000225800300A24C0 +:103FB0000000000000040000006946220000067CAA +:103FC00000002169002044110000000000000000F2 +:103FD00000204805000000000002000000294A26D9 +:103FE0000000000000000000002048100000000059 +:103FF000CAFEBABE00204811000000000000000206 +:10400000002F022300000000000000000CC0000090 +:104010000000056100000000C0201C10000000002E +:1040200000000000C04000000000056F000000021A +:10403000002F022300000000000000000CC0000060 +:104040000000056181000000002044110000000014 +:10405000000000010020481100000000000022586C +:1040600000300A240000000000040000006946221D +:104070000000067C00000000C0201C1000000000B2 +:1040800000000000C04000000000056F00000000BC +:10409000002F022300000000000000000CC0000000 +:1040A0000000056500000000C0201C0000000000AA +:1040B00000000000C04000000000056F0000000488 +:1040C000002F022300000000000000000CC00000D0 +:1040D0000000056D81000000002044110000000078 +:1040E0000000000000204811000000000000216DC9 +:1040F000002044110000000000000000C020480023 +:104100000000000000000000C060480000000681C0 +:104110000000000000401C100000056F00000000BF +:10412000C02000000000000000000000C0400000AF +:1041300000000000000000000EE00000000005711B +:104140000000000000600000000005BC000000004E +:10415000002F022400000000000000000CC000003E +:10416000000005820000A2B70020441100000000FA +:10417000000000000020480700000000810000004F +:104180000020441100000000000000010020481140 +:10419000000000000004A2B6006044110000067C8C +:1041A0000000001A0021223000000000000000067C +:1041B00000222630000000000004200400604411AA +:1041C0000000067C0000A2C4002044110000000092 +:1041D00000000000003048E900000000000000007E +:1041E00000E00000000005800000A2D10020441182 +:1041F000000000000000000000404808000000002F +:104200000000A2D1002044110000000000000001C5 +:1042100000504A280000000000000001002F022486 +:1042200000000000000000000CC00000000005932A +:104230000000A2BB002044110000000000000000AC +:104240000020480700000000810000000020441109 +:1042500000000000000000010020481100000000E4 +:104260000004A2BA006044110000067C0000001A9D +:10427000002122300000000000000006002226304D +:104280000000000000042004006044110000067CCF +:104290000000A2C500204411000000000000000042 +:1042A000003048E9000000000000000000E00000CD +:1042B000000005910000A2D200204411000000007F +:1042C0000000000000404808000000000000A2D2EA +:1042D00000204411000000000000000100504A28A6 +:1042E0000000000000000002002F02240000000077 +:1042F000000000000CC00000000005A40000A2BFE8 +:1043000000204411000000000000000000204807C9 +:1043100000000000810000000020441100000000A7 +:104320000000000100204811000000000004A2BEAF +:10433000006044110000067C0000001A00212230B9 +:1043400000000000000000060022263000000000EF +:1043500000042004006044110000067C0000A2C696 +:10436000002044110000000000000000003048E977 +:10437000000000000000000000E00000000005A2B6 +:104380000000A2D300204411000000000000000043 +:1043900000404808000000000000A2D300204411A3 +:1043A000000000000000000100504A28000000004A +:1043B0000000A2C300204411000000000000000023 +:1043C0000020480700000000810000000020441188 +:1043D0000000000000000001002048110000000063 +:1043E0000004A2C2006044110000067C0000001A14 +:1043F00000212230000000000000000600222630CC +:104400000000000000042004006044110000067C4D +:104410000000A2C7002044110000000000000000BE +:10442000003048E9000000000000000000E000004B +:10443000000005B10000A2D40020441100000000DB +:104440000000000000404808000000000000A2D466 +:1044500000204411000000000000000100504A2824 +:104460000000000085000000002044110000000052 +:104470000000000000204801000000000000304A59 +:10448000002044110000000001000000002048113D +:10449000000000000000000000400000000005B720 +:1044A000A4000000C0204411000000000000000033 +:1044B000C04048000000000000000000C060000094 +:1044C000000005BC00000000C04004000000000126 +:1044D0000000002C002036210000000081000000B8 +:1044E00000204411000000000000000600204811D8 +:1044F0000000000000000000002F0230000000005B +:10450000000000000CC00000000005C30000000017 +:10451000002004110000000000000030004036219F +:10452000000005D6000000300020062D000000002D +:1045300000007E00002806210000000000000000AE +:10454000002F022100000000000000000CE000002D +:10455000000005D68100000000204411000000008A +:104560000000000100204811000000000004A0929B +:10457000006044110000067C00000031002036304D +:10458000000000000004A093006044110000067CBD +:104590000000003200203630000000000004A2B607 +:1045A000006044110000067C00000033002036301B +:1045B000000000000004A2BA006044110000067C64 +:1045C0000000003400203630000000000004A2BECD +:1045D000006044110000067C0000003500203630E9 +:1045E000000000000004A2C2006044110000067C2C +:1045F00000000036002036300000000000042004D7 +:10460000006044110000067C0001A2A400204411B7 +:10461000000000000000003F0020481100000000E2 +:104620000000003F00204811000000000000003F93 +:1046300000204811000000000000003F0020481149 +:1046400000000000000000050020481100000000EC +:104650000000A1F400204411000000000000000050 +:1046600000204811000000008800000000204411D4 +:1046700000000000000000010020481100000000C0 +:10468000810000000020441100000000000000062E +:10469000002048110000000000000001002F02303F +:1046A00000000000000000000CE000000000061FF9 +:1046B000000000300020062D000000000000000077 +:1046C000002F022100000000000000000CE00000AC +:1046D0000000061F810000000020441100000000BF +:1046E00000000001002048110000000000007E00D2 +:1046F000002806210000000000000000002F022119 +:1047000000000000000000000CE00000000005F8C0 +:104710000000A092002044110000000000000031C1 +:1047200000204A2D000000000000A093002044114A +:10473000000000000000003200204A2D00000000B0 +:104740000000A2B600204411000000000000003369 +:1047500000204A2D000000000000A2BA00204411F1 +:10476000000000000000003400204A2D000000007E +:104770000000A2BE0020441100000000000000352F +:1047800000204A2D000000000000A2C200204411B9 +:10479000000000000000003600204A2D000000004C +:1047A000000000300020062D00000000000001FF86 +:1047B000002806210000000000000000002F022158 +:1047C00000000000000000000CE000000000061ED9 +:1047D0000000000000210221000000000000000095 +:1047E00014C00000000006010004A0030060441192 +:1047F0000000067C0000A00300204411000000001F +:10480000000000000020481000000000000000012F +:1048100000210621000000000000000014C000007C +:10482000000006060004A010006044110000067C91 +:104830000000A01000204411000000000000000053 +:1048400000204810000000000000000100210621A7 +:104850000000000000000000002F02210000000006 +:10486000000000000CE000000000061E0004A01183 +:10487000006044110000067C0000A01100204411DB +:1048800000000000000000000020481000000000B0 +:104890000004A012006044110000067C0000A01279 +:1048A000002044110000000000000000002048101B +:1048B000000000000004A013006044110000067C0A +:1048C0000000A013002044110000000000000000C0 +:1048D00000204810000000000004A01400604411F3 +:1048E0000000067C0000A01400204411000000001D +:1048F0000000000000204810000000000004A01587 +:10490000006044110000067C0000A0150020441146 +:10491000000000000000000000204810000000001F +:104920000004A016006044110000067C0000A016E0 +:10493000002044110000000000000000002048108A +:10494000000000000004A017006044110000067C75 +:104950000000A0170020441100000000000000002B +:1049600000204810000000000004200400604411F2 +:104970000000067C0000002C0080062D00000000D6 +:10498000FF000000002044110000000000000000B3 +:104990000020481100000000000000010020481124 +:1049A000000000000000000200804811000000002C +:1049B000000000000EE000000000063000000030A3 +:1049C0000020062D00000000000000020028062143 +:1049D0000000000000000000002F02210000000085 +:1049E000000000000CE000000000062E8100000026 +:1049F00000204411000000000000000100204811C8 +:104A00000000000000042004006044110000067C47 +:104A10000000100000200811000000000000002B22 +:104A200000203622000000000000000000600000AE +:104A3000000006340000000000600000000005BC1B +:104A40009800000000204411000000000000000059 +:104A5000008048110000000000000000C06000005D +:104A60000000063400000000C04004000000000107 +:104A70000000A2A400204411000000000000002259 +:104A800000204811000000008900000000204411AF +:104A90000000000000000001004048110000062056 +:104AA00097000000002044110000000000000000FA +:104AB00000204811000000008A000000002044117E +:104AC0000000000000000000004048110000062027 +:104AD00000000000006000000000064D0001A2A4DC +:104AE000C0204411000000000000001600604811C2 +:104AF0000000036A000020100020441100000000A4 +:104B000000010000002048110000000081000000AA +:104B100000204411000000000000000100204811A6 +:104B2000000000000000217C002044110000000073 +:104B3000098000000020481100000000FFFFFFFF77 +:104B40000020481100000000000000000020481173 +:104B5000000000000000000017000000000000003E +:104B60000004217F006044110000067C0000001F4B +:104B700000210230000000000000000014C000000E +:104B8000000000000000000400404C110000064737 +:104B900000000000004000000000000000000017BE +:104BA00000201E2D000000000000000400291E2728 +:104BB0000000000000000017008036270000000001 +:104BC0000000001700201E2D00000000FFFFFFFB6B +:104BD00000281E2700000000000000170080362774 +:104BE000000000000000001700201E2D0000000043 +:104BF0000000000800291E27000000000000001728 +:104C000000803627000000000000001700201E2D45 +:104C100000000000FFFFFFF700281E270000000033 +:104C20000000001700803627000000000001A2A449 +:104C30000020441100000000000000160060481130 +:104C40000000036A00002010002044110000000052 +:104C50000001000000204811000000000000217C3D +:104C600000204411000000000180000000204811D5 +:104C700000000000FFFFFFFF0020481100000000BF +:104C800000000000002048110000000000000000AB +:104C90001700000000000000810000000020441107 +:104CA000000000000000000100204811000000008A +:104CB0000004217F006044110000067C0000001FFA +:104CC00000210230000000000000000014C00000BD +:104CD0000000067B0000001000404C11000006613F +:104CE00000000000C02004000000000000000000E0 +:104CF00038C00000000000000000001D00200A2D48 +:104D0000000000000000001E00200E2D000000002A +:104D10000000001F0020122D0000000000000020F5 +:104D20000020162D00000000000021690020441121 +:104D30000000000000000000002048040000000007 +:104D400000000000002048050000000000000000F6 +:104D50000020480100000000CAFEBABE0020481131 +:104D600000000000000000040030122400000000D9 +:104D700000000000002F00640000000000000000A0 +:104D80000CC000000000067A0000000300281A2270 +:104D900000000000000000080022122200000000B5 +:104DA000FFFFF000002812240000000000000000B7 +:104DB000002910C4000000000000001F004036243D +:104DC0000000000000000000008000000000000063 +:104DD000000000001AC000000000067C9F000000D8 +:104DE0000020441100000000CAFEBABE0020481195 +:104DF00000000000000000001AE000000000067F34 +:104E00000000000000800000000000000000000022 +:104E10001AC00000000006819E000000002044111E +:104E200000000000CAFEBABE0020481100000000C9 +:104E3000000000001AE000000000068400000000EE +:104E40000080000000000000000000000060000082 +:104E50000000000B000010000060041100000315AA +:104E6000000000000020041100000000000000000D +:104E700000600811000001B20000225C0020441113 +:104E800000000000000000030020481100000000A6 +:104E90000000225600204411000000000000001B0A +:104EA00000204811000000000000A1FC0020441177 +:104EB0000000000000000001002048110000000078 +:104EC0000001A1FDC02044110000000000000021ED +:104ED00000201E2D000000000000001000221E27F0 +:104EE00000000000000000240020222D000000002F +:104EF0000000FFFF00282228000000000000000042 +:104F000000294907000000000000000000204811AF +:104F100000000000000000220020222D0000000000 +:104F20000000FFFF00282228000000000000000011 +:104F3000002949070000000000000000002048117F +:104F4000000000000000002300201E2D00000000D3 +:104F50000000001000221E270000000000000000DA +:104F6000002949070000000000000000004048112F +:104F70000000000000000000000000000000000031 +:104F80000000000000000000000000000000000021 +:104F90000000000000000000000000000000000011 +:104FA0000000000000000000000000000000000001 +:104FB00000000000000000000000000000000000F1 +:104FC00000000000000000000000000000000000E1 +:104FD00000000000000000000000000000000000D1 +:104FE00000000000000000000000000000000000C1 +:104FF00000000000000000000000000000000000B1 +:1050000000000000000000000000000000000000A0 +:105010000000000000000000000000000000000090 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B000014204F505B302500000000001C301687B +:1052C000043505B300000000022502090250015117 +:1052D000000000000223024502A00241000000007D +:1052E00003CD05B305B305B300000000063C063D41 +:1052F000031F05B30000000005B305B803200340F9 +:1053000000000000032A0282034203340000000070 +:1053100005B305B305B305B30000000005B30544AC +:1053200005B305B30000000003B205B304AE0344A7 +:1053300000000000048D0443043305B300000000A6 +:1053400004C305B3043704D000000000044304FA8A +:10535000035103710000000005B305B305B305B3A5 +:105360000000000005B305B305B305B3000000005D +:1053700005B305B3063205BA0000000005B305B356 +:10538000000705B30000000005B305B305B305B37E +:105390000000000005B305B305B305B3000000002D +:1053A00003EE03E303FE03FC00000000040404001A +:1053B00004020406000000000412040E041A04167D +:1053C000000000000422041E042A0426000000003D +:1053D00005B305B3042E05B30000000005B305B303 +:1053E00005B305B30000000005B305B305B305B36D +:1053F00000000000000206680686000600000000AB +:00000001FF diff --git a/firmware/radeon/RV670_pfp.bin.ihex b/firmware/radeon/RV670_pfp.bin.ihex new file mode 100644 index 000000000000..f55292c97b79 --- /dev/null +++ b/firmware/radeon/RV670_pfp.bin.ihex @@ -0,0 +1,145 @@ +:1000000000CA040000A00000007E828B007C038BED +:10001000008001B8007C038B00D4401E00EE001E5F +:1000200000CA040000A00000007E828B00C41838C3 +:1000300000CA240000CA2800009581A800C41C3A08 +:1000400000C3C00000CA080000CA0C00007C744B4A +:1000500000C200050099C00000C41C3A007C744C2A +:1000600000C0FFF000042C0400309002007D250049 +:1000700000351402007D350B00255403007CD5802B +:1000800000259C030095C00400D5001B007EDDC147 +:10009000007D9D8000D6801B00D5801B00D4401EB3 +:1000A00000D5401E00D6401E00D6801E00D4801E03 +:1000B00000D4C01E009783D300D5C01E00CA08001C +:1000C0000080001A00CA0C0000E4011E00D4001ECB +:1000D0000080000C00C4183800E4013E00D4001E6B +:1000E0000080000C00C4183800D4401E00EE001E32 +:1000F00000CA040000A00000007E828B00E4011E04 +:1001000000D4001E00D4401E00EE001E00CA0400F1 +:1001100000A00000007E828B00E4013E00D4001E9F +:1001200000D4401E00EE001E00CA040000A0000023 +:10013000007E828B00CA180000D4401E00D5801EAD +:100140000080005300D4007500D4401E00CA08008F +:1001500000CA0C0000CA100000D4801900D4C018D6 +:1001600000D5001700D4801E00D4C01E00D5001E8C +:1001700000E2001E00CA040000A00000007E828B86 +:1001800000CA080000D4806000D4401E0080000037 +:1001900000D4801E00CA080000D4806100D4401E34 +:1001A0000080000000D4801E00CA080000CA0C00B5 +:1001B00000D4401E00D4801600D4C01600D4801E87 +:1001C000008001B800D4C01E00C6084300CA0C005D +:1001D00000CA10000094800400CA140000E420F358 +:1001E00000D4201300D5606500D4E01C00D5201C8D +:1001F00000D5601C008000000006200100C60843F6 +:1002000000CA0C0000CA1000009483F700CA140052 +:1002100000E420F30080007900D4201300C60843D6 +:1002200000CA0C0000CA1000009883EF00CA140036 +:1002300000D400640080008D0000000000C414326F +:1002400000C6184300C4082F0095400500C40C30B8 +:1002500000D4401E0080000000EE001E009583F5D3 +:1002600000C4103100D4403300D5206500D4A01C58 +:1002700000D4E01C00D5201C00E4015E00D4001E68 +:10028000008000000006200100CA1800000A2001BA +:1002900000D6007600C408360098800700C61045D6 +:1002A0000095011000D4001F00D46062008000009F +:1002B00000D4206200CC383500CC1433008401BB5C +:1002C00000D4007200D5401E0080000000EE001E29 +:1002D00000E2001A008401BB00E2001A00CC104BBF +:1002E00000CC0447002C9401007D098B0098400548 +:1002F000007D15CB00D4001A008001B800D4006D39 +:100300000034440100CC0C480098403A00CC2C4A00 +:100310000095800400CC0449008001B800D4001A84 +:1003200000D4C01A00282801008400F000CC10037B +:100330000098801B0004380C008400F000CC1003EF +:100340000098801700043808008400F000CC1003E7 +:100350000098801300043804008400F000CC1003DF +:100360000098801400CC104C009A800900CC144DE9 +:10037000009840DC00D4006D00CC184800D5001A6D +:1003800000D5401A008000C900D5801A0096C0D55B +:1003900000D4006D008001B800D4006E009AC00344 +:1003A00000D4006D00D4006E0080000000EC007FDF +:1003B000009AC0CC00D4006D008001B800D4006E5B +:1003C00000CC140300CC180300CC1C03007D910367 +:1003D000007DD583007D190C0035CC1F0035701FC2 +:1003E000007CF0CB007CD08B00880000007E8E8BE0 +:1003F0000095C00400D4006E008001B800D4001A3B +:1004000000D4C01A00CC080300CC0C0300CC1003AD +:1004100000CC140300CC180300CC1C0300CC240334 +:1004200000CC28030035C41F0036B01F007C704B81 +:100430000034F01F007C704B0035701F007C704B47 +:10044000007D8881007DCCC1007E5101007E9541F8 +:10045000007C9082007CD4C2007C848B009AC00314 +:10046000007C8C8B002C88010098809E00D4006D4D +:100470000098409C00D4006E00CC084C00CC0C4D81 +:1004800000CC104800D4801A00D4C01A00800101AA +:1004900000D5001A00CC083200D40032009482D972 +:1004A00000CA0C0000D4401E0080000000D4001ED2 +:1004B00000E4011E00D4001E00CA080000CA0C009F +:1004C00000CA100000D4401E00CA140000D4801ED0 +:1004D00000D4C01E00D5001E00D5401E00D54034FB +:1004E0000080000000EE001E0028040400E2001A54 +:1004F00000E2001A00D4401A00CA380000CC0803F9 +:1005000000CC0C0300CC0C0300CC0C03009882BD83 +:1005100000000000008401BB00D7A06F0080000035 +:1005200000EE001F00CA040000C2FF0000CC083427 +:1005300000C13FFF007C74CB007CC90B007D010F24 +:10054000009902B0007C738B008401BB00D7A06FC0 +:100550000080000000EE001F00CA080000281900FB +:10056000007D898B009580140028140400CA0C00BB +:1005700000CA100000CA1C0000CA240000E2001FCC +:1005800000D4C01A00D5001A00D5401A00CC1803B8 +:1005900000CC2C0300CC2C0300CC2C03007DA58BBD +:1005A000007D9C4700984297000000000080016198 +:1005B00000D4C01A00D4401E00D4801E0080000069 +:1005C00000EE001E00E4011E00D4001E00D4401EF8 +:1005D00000EE001E00CA040000A00000007E828B16 +:1005E00000E4013E00D4001E00D4401E00EE001EB8 +:1005F00000CA040000A00000007E828B00CA080030 +:1006000000248C06000CCC060098C00600CC104ECE +:100610000099000400D4007300E4011E00D4001E01 +:1006200000D4401E00D4801E0080000000EE001E9A +:1006300000CA080000CA0C000034D01800251001C0 +:100640000095002100C17FFF00CA100000CA1400FD +:1006500000CA180000D4801D00D4C01D007DB18BDD +:1006600000C1420200C2C00100D5801D0034DC0E72 +:10067000007D5D4C007F734C00D7401E00D5001EEE +:1006800000D5401E00C1420000C2C00000099C010C +:100690000031DC10007F5F4C007F734C00042802A7 +:1006A000007D838000D5A86F00D5806600D7401EEE +:1006B00000EC005E00C8240200C82402008001B8DB +:1006C00000D6007600D4401E00D4801E00D4C01E88 +:1006D0000080000000EE001E0080000000EE001F01 +:1006E00000D4001F0080000000D4001F00D4001FB1 +:1006F0000088000000D4001F00000000000000007F +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000010171000201780003008F0004007FE5 +:10081000000500030006003F000700320008012C1D +:1008200000090046000A0036001001B6001700A2B9 +:100830000022013A00230149002000B400240125D0 +:100840000027004D0028006A002A0060002B00529B +:10085000002F0065003200870034017F003C015604 +:10086000003F00720041018C0044012E00550173CD +:100870000056017A0060000B00610034006200380D +:1008800000630038006400380065003800660038F6 +:10089000006700380068003A00690041006A0048BB +:1008A000006B0048006C0048006D0048006E004876 +:1008B000006F00480000000600000006000000066F +:1008C0000000000600000006000000060000000610 +:1008D0000000000600000006000000060000000600 +:1008E00000000006000000060000000600000006F0 +:1008F00000000006000000060000000600000006E0 +:00000001FF diff --git a/firmware/radeon/RV710_me.bin.ihex b/firmware/radeon/RV710_me.bin.ihex new file mode 100644 index 000000000000..5cdfe306eea5 --- /dev/null +++ b/firmware/radeon/RV710_me.bin.ihex @@ -0,0 +1,341 @@ +:10000000CC0003EA04080003CC8000437C4080005D +:10001000A0000000CC80006280000003D040007F80 +:1000200080000003CC4000417C40C000C0160004AA +:1000300030D03FFF7D15000CCC11000028D8001EE9 +:100040003198000128DC001FC820000495C000067C +:100050007C424000CC0000627E56800CCC2900001F +:10006000C82400047E26000B958000067C42C00058 +:10007000CC0000627ED7000CCC310000C82C0004FC +:100080007E2E000CCC00006231103FFF8000000388 +:10009000CE1100007C40C00080000003CC40004036 +:1000A00080000003CC4122577C418000CC400045B9 +:1000B000CC400048CC41225CCC41A1FC7C4080007B +:1000C000A0000000CC800062CC400045CC4000483D +:1000D0007C40C000CC41225CCC41A1FC7C40800033 +:1000E000A0000000CC800062CC000045CC0000489D +:1000F000CC41225CCC41A1FC7C408000A0000000EF +:10010000CC800062040CA1FDC0120001CC000045AF +:10011000CC0000487CD0C00CCC41225CCC41A1FC7E +:10012000D04D00007C408000A0000000CC80006228 +:1001300080000003CC41225D7C4080007C40C000F8 +:10014000C02A00027C4100007D29000C309400018F +:1001500030980006309C030029DC00087C42000037 +:100160007C4240009540000FC02E000405F022584C +:100170007F2F000CCC310000C8280004CCC12169BD +:10018000CD01216ACE81216B0DB40002CC01216C1E +:100190009740000E0DB400008000007DC834000AB6 +:1001A0000DB40002974000090DB40000C02E0004F9 +:1001B00005F022587F2F000CCC310000C828000425 +:1001C0008000007DC834000A974000047E02800051 +:1001D0008000007DC834000A0DB400049740FF8CF5 +:1001E00000000000CE01216DCE41216EC828000321 +:1001F000C834000A9B400004043C00058400026DE2 +:10020000CC0000620DF400009740000BC82C03E600 +:10021000CE81A2B7C03000067EF34028C030002057 +:100220007F6B80207FB3C029CF81A2C480000003F0 +:10023000CFC1A2D10DF400019740000BC82C03E7F9 +:10024000CE81A2BBC03000067EF34028C030002023 +:100250007F6B80207FB3C029CF81A2C580000003BF +:10026000CFC1A2D20DF400029740000BC82C03E8C6 +:10027000CE81A2BFC03000067EF34028C0300020EF +:100280007F6B80207FB3C029CF81A2C6800000038E +:10029000CFC1A2D3C82C03E9CE81A2C3C0300006CF +:1002A0007EF34028C03000207F6B80207FB3C029C0 +:1002B000CF81A2C780000003CFC1A2D48000000379 +:1002C000CC4000427C40C0007C4100002914001D4D +:1002D000315400019940000C31181000C81C001165 +:1002E00095C00000C81C0011CCC12100CD01210126 +:1002F000CCC12102CD012103041800048000037E3B +:10030000CD81A2A4C02A00049580000836A821A3AC +:10031000CC290000C8280004C81C00110DE40040CE +:100320009640FFFFC81C0011CCC12170CD01217186 +:10033000C820001296000000C82000128000037E32 +:10034000CC0000647C40C0007C410000CC00004533 +:10035000CC00004840D40003CD41225CCD01A1FC7B +:10036000C01A0001041CA1FD7DD9C00C7C42000014 +:1003700008CC00010624000106280002CE1D000062 +:10038000CE5D000098C0FFFACE9D00007C4080004A +:10039000A0000000CC8000627C40C00030D0000192 +:1003A00028CC00017C414000950000067C41800083 +:1003B000CD41216DCD81216E800000F4C81C000369 +:1003C000C02200047E16000CCC210000C81C0004D2 +:1003D0007C42400098C000047C4280008000000302 +:1003E000CDE50000CE412169CE81216ACDC1216BCE +:1003F00080000003CC01216C7C40C0007C410000E7 +:100400007C4140007C4180007C41C00028A4000861 +:10041000326400FF0E68003C9680000A7C020000F7 +:100420007C4200001E300003CC00006A9B000003E9 +:100430004220000504200040800001117C024000A1 +:100440007E0240009A4000000A64000130EC001077 +:100450009AC0000ACC000062C02A0004C82C002107 +:100460007E92800CCC000041CC290000CEC000213F +:1004700080000121C8300004CD01216DCD41216EE5 +:10048000C83000037F1F000B30F4000727780001FD +:100490009740002A07B801269F8000000000000056 +:1004A000800001367F1B80048000013A7F1B80059D +:1004B0008000013E7F1B8002800001427F1B800381 +:1004C000800001467F1B80078000014A7F1B800659 +:1004D0008000014F28A400089B80001928A4000870 +:1004E0008000015F326400FF9B80001528A4000893 +:1004F0008000015F326400FF9B80001128A4000887 +:100500008000015F326400FF9B80000D28A400087A +:100510008000015F326400FF9B80000928A400086E +:100520008000015F326400FF9B80000528A4000862 +:100530008000015F326400FF28A40008326400FFDD +:100540000E68003C9A80FEB228EC00087C43400014 +:100550007C4380007C43C00096C00007CC00006252 +:10056000CF412169CF81216ACFC1216B8000000377 +:10057000CC01216C80000003CFF50000CC00006BA3 +:10058000840003810E68003C9A800004C82800158E +:1005900080000003D040007F9680FFAB7E024000C9 +:1005A0008400023BC00E0002CC00004180000239F2 +:1005B000CCC1304A7C40C0007C410000C01E00011C +:1005C00029240012C022000296400005C026000423 +:1005D000C027FFFB7D25000BC02600007DD2800BCD +:1005E0007E12C00B7D25000C7C4140007C418000C8 +:1005F000CCC121699A80000ACD01216ACD41216BCD +:1006000096C0FE83CD81216CC83000189700000091 +:10061000C830001880000003CC000018840003815B +:10062000CC00007FC8140013C8180014CD41216B02 +:1006300096C0FE77CD81216C80000183C830001800 +:10064000C80C000898C00000C80C00087C410000DD +:1006500095000002000000007C414000C820000915 +:10066000CC400043CE01A1F4CC400044C00E800039 +:100670007C4240007C4280002AAC001F96C0FE6491 +:10068000C035F000CE4003E232780003267C00083B +:100690007FF7C00B7FFBC00C2A780018CFC003E3A4 +:1006A000CF8003E426B000027F3F0000CF0003E5C7 +:1006B0008000031F7C80C0007C40C00028D0000860 +:1006C0003110000F9500000F2528000106A801B485 +:1006D0009E80000000000000800001D5C0120800CC +:1006E000800001E3C814000F800001EAC814001064 +:1006F000800001F1CCC1A2A4800001FAC81400114D +:1007000030D0003F0D2800159A8000120D28001EE1 +:100710009A80001E0D2800209A8000230D24000FCF +:100720000D2800107E6A800C9A8000260D2000049F +:100730000D2400140D2800287E62400C7EA6800C3B +:100740009A80002AC814001180000003CCC1A2A422 +:10075000C01208007C4140007D0CC00CC012000893 +:1007600029580003295C000C7C4200007DD1C00B9D +:10077000262000147E1E400C7E4E800CCE81A2A44A +:1007800080000003CD81A1FEC814000F0410210ECB +:1007900095400000C814000FD051000080000003F5 +:1007A000CCC1A2A4C8140010041021089540000078 +:1007B000C8140010D051000080000003CCC1A2A4D6 +:1007C000CCC1A2A404100001CD0000198400038153 +:1007D000CC00007FC810001999000000C810001953 +:1007E000800000047C40800004102100954000003F +:1007F000C8140011D05100008000037ECCC1A2A417 +:100800007C40C000CC40000D94C0FE01CC40000EE6 +:100810007C4100009500000508CC0001C8140005CB +:10082000994000140000000098C0FFFB7C410000CC +:10083000800000047D008000C81400057C40C000DA +:100840009940000CC818000C7C4100009580FDF018 +:10085000C820000EC81C000D662000207E1E002C43 +:10086000252400027E62402080000003CCE60000C8 +:100870007C410000CC00006CCC00006DC818001F4B +:10088000C81C001E659800207DD9C02C7CD4C00CEB +:10089000CCDE000045DC0004C82800179680000F5D +:1008A000C00E0001286800082AAC001632A800FF1C +:1008B0000EB000497F2F000B9700000600000000DB +:1008C000C81400057C40C000800002237C41000069 +:1008D00080000226D040007F8400023BCC00004113 +:1008E000CCC1304A94000000C83C001A043C00050A +:1008F000CFC1A2A4C0361F90C0387FFF7C03C010B8 +:100900007F7B400CCF41217CCFC1217DCC01217E5A +:10091000C03A00040434217F7F7B400CCC350000BA +:10092000C83C00042BFC001F0438002097C00005C1 +:10093000CC0000629B8000000BB8000180000247E1 +:10094000CC000071CC01A1F404380016C0360002BE +:10095000CF81A2A488000000CF4120107C40C000BD +:1009600028D0001C9500000504D40001CD4000658E +:1009700080000003CD40006809540002800000039D +:10098000CD4000668400026CC81803EA7C40C000B9 +:100990009980FD9FC814001608D000019940002BD3 +:1009A000CD0000687C408000A0000000CC80006288 +:1009B000043C0005CFC1A2A4CC01A1F484000381B2 +:1009C000CC00004688000000CC00007F8400027E3E +:1009D000C81803EA7C40C0009980FD8DC814001639 +:1009E00008D0000199400019CD0000687C408000CB +:1009F000A0000000CC800062043C0022CFC1A2A471 +:100A000084000381CC00004788000000CC00007FF8 +:100A1000C81000169900000DCC400067800000044B +:100A20007C408000C81803EA9980FD797C40C000B2 +:100A300094C00003C810001699000004CCC00068E0 +:100A4000800000047C4080008400023BC0148000D1 +:100A5000CC000041CD41304AC01480009900000014 +:100A6000C8100016800000047C408000C012000105 +:100A70007C51400C80000003D05500007C40C00039 +:100A80007C4100007C4140007C418000291C001F0B +:100A9000CCC0004ACD00004B95C00003C01C8000B4 +:100AA000CDC12010DD830000055C2000CC00006279 +:100AB00080000003D81F41007C40C0007C41000042 +:100AC0007C4140007C418000CCC0004CCD00004DFA +:100AD000DD830000055CA00080000003D81F4100FA +:100AE0007C40C0007C4100007C4140007C41800093 +:100AF000CCC0004ECD00004FDD830000055CC0007F +:100B000080000003D81F41007C40C0007C410000F1 +:100B10007C4140007C418000CCC00050CD000051A1 +:100B2000DD830000055CF8E080000003D81F410071 +:100B30007C40C0007C4100007C4140007C41800042 +:100B4000CCC00052CD000053DD830000055CF8806E +:100B500080000003D81F41007C40C0007C410000A1 +:100B60007C4140007C418000CCC00054CD00005549 +:100B7000DD830000055CE00080000003D81F410019 +:100B80007C40C0007C4100007C4140007C418000F2 +:100B9000CCC00056CD000057DD830000055CF0009E +:100BA00080000003D81F41007C40C0007C41000051 +:100BB0007C4140007C418000CCC00058CD000059F1 +:100BC000DD830000055CF3FC80000003D81F4100BA +:100BD000D04320007C408000A0000000CC80006258 +:100BE000D043A0007C408000A0000000CC800062C8 +:100BF000D043C0007C408000A0000000CC80006298 +:100C0000D043F8E07C408000A0000000CC8000626F +:100C1000D043F8807C408000A0000000CC800062BF +:100C2000D043E0007C408000A0000000CC80006247 +:100C3000D043F0007C408000A0000000CC80006227 +:100C4000D043F3FC7C408000A0000000CC80006218 +:100C5000C81403E0CC430000CC430000CC430000A8 +:100C60007D45C000CDC30000D04300007C40800023 +:100C7000A0000000CC8000627C40C000C81003E2ED +:100C8000C81403E5C81803E3C81C03E4CD81216937 +:100C9000CDC1216ACCC1216BCC01216C04200004A0 +:100CA0007DA180007D9640029640FCD9CD8003E373 +:100CB00031280003C02DF000251800087DAD800B01 +:100CC0007DA9800C80000003CD8003E3308CFFFF02 +:100CD000D04D00007C408000A0000000CC8000626D +:100CE000C8140020155800029580FFFFC81400208A +:100CF000CC00006ECC4121807C40C000CCC1218D55 +:100D0000CC41218128D0001F34588000CD81218C16 +:100D10009500FCBFCC412182C81400209940FFFF00 +:100D2000C8140020800000047C4080007C40C0008B +:100D300028D0001831100001C01600809500000373 +:100D4000C02A00047CD4C00CCCC1217CCC41217DC4 +:100D5000CC41217E7C4180001DB0000336A0217F64 +:100D60009B000003419C0005041C004099C000004A +:100D700009DC0001CC210000C82400042A6C001FFB +:100D8000419C00059AC0FFFACC80006280000004FC +:100D90007C4080007C40C00004D403E68000000357 +:100DA000CC5400008000037ECC4003EAC01C8000CD +:100DB000044CA000CDC120107C410000C8140009E3 +:100DC00004180000041C0008CD80007109DC00013B +:100DD00005980001CD0D000099C0FFFCCC80006299 +:100DE0008000037ECD400071C00E0100CC000041A8 +:100DF000CCC1304AC83C007FCC00007F800000039B +:100E0000CC00007FCC00007F88000000CC00007F79 +:100E100000000000000000000000000000000000D2 +:100E200000000000000000000000000000000000C2 +:100E300000000000000000000000000000000000B2 +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000000000082 +:100E70000000000000000000000000000000000072 +:100E80000000000000000000000000000000000062 +:100E90000000000000000000000000000000000052 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000000000000000000000022 +:100ED0000000000000000000000000000000000012 +:100EE0000000000000000000000000000000000002 +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000000E1 +:100F100000000000000000000000000000000000D1 +:100F200000000000000000000000000000000000C1 +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000000000000000000000021 +:100FD0000000000000000000000000000000000011 +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200000000000000000000000000000000000C0 +:1010300000000000000000000000000000000000B0 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C0000000000000000000000000000000000020 +:1010D0000000000000000000000000000000000010 +:1010E0000000000000000000000000000000000000 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000000000000000000000CF +:1011200000000000000000000000000000000000BF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000000000000000F +:1011E00000000000000000000000000000000000FF +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:1012100000000000000000000000000000000000CE +:1012200000000000000000000000000000000000BE +:1012300000000000000000000000000000000000AE +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C000000000000000000000000000000000001E +:1012D000000000000000000000000000000000000E +:1012E00000000000000000000000000000000000FE +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200000000000000000000000000000000000BD +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000000002D +:1013C000000000000000000000000000000000001D +:1013D000000000000000000000000000000000000D +:1013E00000000000000000000000000000000000FD +:1013F00000000000000000000000000000000000ED +:101400000001033300100006001700080021000A45 +:101410000027002A002800250029002B002A002888 +:10142000002B002B002D003A002E0041002F004C15 +:101430000034004E00360032003900B1003A00D1CD +:10144000003B00E6003C00FE003D016D003F00AFA8 +:10145000004103380043034B00440190004500FE67 +:10146000004601AE004701AE004802000049020EEE +:10147000004A0257004B028400520261005302737B +:10148000005402890057029B0060029F006102AE77 +:10149000006202B8006302C2006402CC006502D69A +:1014A000006602E0006702EA006802F4006902F8E0 +:1014B000006A02FC006B0300006C0304006D03086B +:1014C000006E030C006F03100070031400720365BC +:1014D0000074036B00790369007C031E000F037A1C +:1014E000000F037A000F037A000F037A000F037ACC +:1014F000000F037A000F037A000F037A000F037ABC +:10150000000F037A000F037A000F037A000F037AAB +:10151000000F037A000F037A000F037A000F037A9B +:10152000000F037A000F037A000F037A000F037A8B +:10153000000F037A000F037A000F037A000F037A7B +:00000001FF diff --git a/firmware/radeon/RV710_pfp.bin.ihex b/firmware/radeon/RV710_pfp.bin.ihex new file mode 100644 index 000000000000..3d811ff0a1a8 --- /dev/null +++ b/firmware/radeon/RV710_pfp.bin.ihex @@ -0,0 +1,213 @@ +:100000007C408000A00000007E82800B8000000009 +:10001000DC030000CC800040D04000407C408000E9 +:10002000A00000007E82800BC818000E31980001ED +:100030007C4240009580023A7C428000C81C001C33 +:10004000C037C0007C40C0007C4100007CB4800B05 +:10005000C036000399C00000C81C001C7CB4800C92 +:1000600024D400027D654000CD400043CE80004393 +:10007000CD000043CC800040CE400040CE80004008 +:10008000CCC00040DC3A00009780FFDECD0000408D +:100090007C40C000800000187C410000D400034078 +:1000A000D4000FC0D4000FA2C818000E8000000CAE +:1000B00031980002D40003C0D4000FC0D4000FA2B6 +:1000C000C818000E288C000830CC000F3410000136 +:1000D0007D0D00088000000C7D91800BCC800040DD +:1000E000D04000407C408000A00000007E82800B59 +:1000F000D4000340D4000FC0D4000FA2CC80004035 +:10010000D04000407C408000A00000007E82800B38 +:10011000D40003C0D4000FC0D4000FA2CC80004094 +:10012000D04000407C408000A00000007E82800B18 +:10013000CC4003F980000249CC4003F8C037FFFFF0 +:100140007C414000CF41A29EC82003F8C81C03F99F +:1001500066200020C81803FB7DE1C02C7D58C00834 +:100160007CDCC02069100020C0360003CC000054A5 +:100170007CB4800C80000069CC8000407C41800011 +:10018000CD81A29ECC80004080000067CD800040E1 +:10019000C019FFFFCC800040CD81A29E7C40C000F2 +:1001A0007C4100007C414000CCC1A1FACD01A1F905 +:1001B000CD41A29DCCC00040CD000040CD400040CC +:1001C000CC4000407C408000A00000007E82800B7C +:1001D000CC000054CC8000407C40C0007C4100003A +:1001E0007C414000CCC1A1FACD01A1F9CD41A29D35 +:1001F000CCC00040CD000040CD400040D040004089 +:100200007C408000A00000007E82800B7C40C0000B +:1002100030D00001CCC1A29F95000003041400015E +:1002200004140002CD4003FBCC800040800000009D +:10023000CCC000407C40C000CC800040CCC1A2A219 +:1002400080000000CCC000407C40C00028D4001FCB +:10025000CC800040954000037C410000CCC000579A +:100260002918001FCCC0004095800003CD0000403D +:10027000CD00005880000249CC00007FC820001744 +:10028000C83000229A0000060E280001C824001E73 +:100290000A640001D4001240CE400040C036C000C5 +:1002A0009680000737747900041C0001CF4000409D +:1002B000CDC00040CF0003FA7C030000CA0C001040 +:1002C0007C41000094C000047C414000D42002C462 +:1002D000CDE000449B00000B7C418000CC00004B33 +:1002E000CDA00049CD200041CD600041CDA000410E +:1002F00006200001CE00005680000249CC00007F9D +:10030000C8280020C82C0021CC0000637EEA4001F0 +:10031000657400207F53402C269C00027DF5C02090 +:1003200069F80020CE80004BCE600049CDE000414E +:10033000CFA00041CE600041271C00027DF5C02007 +:1003400069F800207DB24001CF00004BCE6000492B +:10035000CDE00041CFA00041800000BCCE60004154 +:10036000C8200017C83000229A0000060E2800019D +:10037000C824001E0A640001D4001240CE40004090 +:10038000CA0C00107C41000094C0000BC036C000B5 +:100390009680000737747900041C0001CF400040AC +:1003A000CDC00040CF0003FA7C030000800000B500 +:1003B0007C414000CC000048800000EE00000000BE +:1003C000C8200017C81C00230E24000299C0001585 +:1003D0007C4180000A200001CE000056D400044079 +:1003E000CC000040C036C000CA140013964000077D +:1003F00037747900CF400040CC000040C83003FA89 +:1004000080000103CF000022CC000022954001466D +:10041000CC00007FCCA0004680000000CC2000462D +:1004200080000249CC000064C8200017C810001FDB +:100430009600000509100001D4000440CD000040E2 +:10044000CD000022CC800040D0400040C80C0025E8 +:1004500094C0FEECC8100008CD000040D4000FC0CE +:1004600080000000D4000FA27C40C0007C4100004E +:10047000CCC003FDCD0003FCCCC00042CD00004247 +:100480002914001F29180010319800073B5C000157 +:100490007D76000B998000057D5E400BCC0000420C +:1004A00080000249CC00004D29980001292C000849 +:1004B0009980003D32EC0001960000042930000CC8 +:1004C00080000249CC00004204140010CD400042DC +:1004D00033300001342800018400015DC81400039A +:1004E0009B40001B0438000C8400015DC81400030D +:1004F0009B400017043800088400015DC814000305 +:100500009B400013043800048400015DC8140003FC +:100510009B400015C80C03FD9A800009C81003FC1D +:100520009B000101CC00004D04140010CCC000421F +:10053000CD00004280000135CD40004296C000FA57 +:10054000CC00004D80000249CC00004E9AC0000350 +:10055000CC00004DCC00004EDF8300008000000086 +:10056000D80301FF9AC000F0CC00004D8000024982 +:10057000CC00004EC8180003C81C0003C8200003AC +:100580007D5D40037DA1C0037D5D400C2A10001FEE +:10059000299C001F7D1D000B7D17400B880000006B +:1005A0007E92800B96400004CC00004E80000249F1 +:1005B000CC00004204380008CF800042C808000385 +:1005C000C80C0003C8100003C8140003C8180003B7 +:1005D000C81C0003C8240003C828000329FC001F0E +:1005E0002AB0001F7FF3C00B28F0001F7FF3C00B61 +:1005F0002970001F7FF3C00B7D8880017DCCC00176 +:100600007E5100017E9540017C9080027CD4C00226 +:100610007CBC800B9AC000037C8F400B38B4000177 +:100620009B4000C1CC00004D9BC000BFCC00004EE1 +:10063000C80C03FDC81003FCCCC000428000016E52 +:10064000CD000042D4000340D4000FC0D4000FA25C +:10065000CC800040CC400040CC400040CC4000402A +:100660007C40C000CCC00040CCC0000D8000000029 +:10067000D04000407C40C0007C4100006514002058 +:100680007D4D402C245800027D5980207C41C000C3 +:10069000CD80004269980020CD800042CDC000424C +:1006A000C023C00005E400027CA0800B266400107B +:1006B0007CA4800CCC800040CDC00040CCC0004069 +:1006C00095C0000ECD00004009DC0001C8280003E1 +:1006D00096800008CE800040C834001D974000007E +:1006E000C834001D26A800088400024CCC2B000052 +:1006F00099C0FFF709DC0001DC3A00009780000494 +:100700007C418000800001A225980002A00000002A +:100710007D808000C818001D7C40C00064D00008A7 +:1007200095800000C818001DCC130000CC8000404C +:10073000CCC0004080000000CC400040C810001F2A +:100740007C40C000CC8000407CD1400CCD400040BB +:100750000518000180000000CD8000227C40C00010 +:10076000645000208400024CCC0000617CD0C02C7E +:10077000C8200017C8D60000994000087C438000BC +:10078000DF830000CFA0004F8400024CCC00006249 +:1007900080000000D040007F80000249CC00006251 +:1007A0008400024CCC000061C82000177C40C000CF +:1007B000C036FF00C810000DC0303FFF7CF5400B75 +:1007C0007D51800B7D81800F998000087CF3800B28 +:1007D000DF830000CFA0004F8400024CCC000062F9 +:1007E00080000000D040007F80000249CC00006201 +:1007F0008400024C7C40C00028DC000895C0001931 +:1008000030DC00107C41000099C0000464540020DA +:1008100080000208C91D00007D15002CC91E0000C3 +:100820007C4200007C4240007C4180007DE5C00BA2 +:100830007DE280079A80000E41AC00059AC000005E +:100840000AEC000130DC001099C000040000000038 +:100850008000020BC91D00008000020BC91E0000B1 +:10086000CC800040CCC00040D0400040C80C0025E7 +:1008700094C0FDE4C8100008CD000040D4000FC0B3 +:1008800080000000D4000FA2D4000340D4000FC0A9 +:10089000D4000FA2CC800040D04000407C408000BB +:1008A000A00000007E82800BD40003C0D4000FC0E3 +:1008B000D4000FA2CC800040D04000407C4080009B +:1008C000A00000007E82800B7C40C00030D000067B +:1008D0000D10000699000007C81400159940000586 +:1008E000CC000052D4000340D4000FC0D4000FA2AB +:1008F000CC800040CCC0004080000000D0400040D0 +:100900007C40C000CC4D0000DC3A00009780FDBD6B +:1009100004CC000180000242CC4D000080000000A9 +:10092000D040007FCC00007F80000000CC00007F22 +:10093000CC00007F88000000CC00007F0000000099 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000000000000000000000B6 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE0000000000000000000000000000000000006 +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000000000000000000000D5 +:100B200000000000000000000000000000000000C5 +:100B300000000000000000000000000000000000B5 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000000000000000000000005 +:100BF00000000000000000000000000000000000F5 +:100C0000000302220004022A0005009F00020003E4 +:100C10000006003C0007002700080191000900447D +:100C2000000A002D00100247001700F0002201D733 +:100C3000002301E80026004C0027005F0020011A75 +:100C4000002800920029004F002A0083002B006436 +:100C5000002F008D003200D80034023200360074BC +:100C60000039010A003C01FC003F009F00410005E3 +:100C7000004401940048019D004901C5004A01CF8C +:100C8000005502250056022D0060000A0061002A6E +:100C90000062003000630030006400300065003006 +:100CA0000066003000670030006800370069003FD0 +:100CB000006A0047006B0047006C0047006D00476A +:100CC000006E0047006F0047007000470073024746 +:100CD000007B024000000005000000050000000548 +:100CE00000000005000000050000000500000005F0 +:100CF00000000005000000050000000500000005E0 +:100D000000000005000000050000000500000005CF +:100D100000000005000000050000000500000005BF +:100D200000000005000000050000000500000005AF +:100D3000000000050000000500000005000000059F +:00000001FF diff --git a/firmware/radeon/RV730_me.bin.ihex b/firmware/radeon/RV730_me.bin.ihex new file mode 100644 index 000000000000..390c18e7cef3 --- /dev/null +++ b/firmware/radeon/RV730_me.bin.ihex @@ -0,0 +1,341 @@ +:10000000CC0003EA7C408000A0000000CC800062AD +:1000100080000001D040007F80000001CC40004102 +:100020007C40C000C016000430D03FFF7D15000C9E +:10003000CC11000028D8001E3198000128DC001FD8 +:10004000C820000495C000067C424000CC0000623D +:100050007E56800CCC290000C82400047E26000BAC +:10006000958000067C42C000CC0000627ED7000C68 +:10007000CC310000C82C00047E2E000CCC000062A5 +:1000800031103FFF80000001CE1100007C40C00015 +:1000900080000001CC40004080000001CC4122578C +:1000A0007C418000CC400045CC400048CC41225CE3 +:1000B000CC41A1FC7C408000A0000000CC8000620C +:1000C000CC400045CC4000487C40C000CC41225C84 +:1000D000CC41A1FC7C408000A0000000CC800062EC +:1000E000CC000045CC000048CC41225CCC41A1FCB6 +:1000F0007C408000A0000000CC800062040CA1FDC8 +:10010000C0120001CC000045CC0000487CD0C00CDF +:10011000CC41225CCC41A1FCD04D00007C40800051 +:10012000A0000000CC80006280000001CC41225D74 +:100130007C4080007C40C000C02A00027C4100005E +:100140007D29000C3094000130980006309C03009B +:1001500029DC00087C4200007C4240009540000FF2 +:10016000C02E000405F022587F2F000CCC31000077 +:10017000C8280004CCC12169CD01216ACE81216B40 +:100180000DB40002CC01216C9740000E0DB40000AC +:100190008000007BC834000A0DB4000297400009BB +:1001A0000DB40000C02E000405F022587F2F000C73 +:1001B000CC310000C82800048000007BC834000A4D +:1001C000974000047E0280008000007BC834000A53 +:1001D0000DB400049740FF8C00000000CE01216D9B +:1001E000CE41216EC8280003C834000A9B40000499 +:1001F000043C00058400026BCC0000620DF400009A +:100200009740000BC82C03E6CE81A2B7C030000691 +:100210007EF34028C03000207F6B80207FB3C02950 +:10022000CF81A2C480000001CFC1A2D10DF4000192 +:100230009740000BC82C03E7CE81A2BBC03000065C +:100240007EF34028C03000207F6B80207FB3C02920 +:10025000CF81A2C580000001CFC1A2D20DF400025F +:100260009740000BC82C03E8CE81A2BFC030000627 +:100270007EF34028C03000207F6B80207FB3C029F0 +:10028000CF81A2C680000001CFC1A2D3C82C03E950 +:10029000CE81A2C3C03000067EF34028C0300020CB +:1002A0007F6B80207FB3C029CF81A2C7800000016F +:1002B000CFC1A2D480000001CC4000427C40C000ED +:1002C0007C4100002914001D315400019940000CAC +:1002D00031181000C81C001195C00000C81C001186 +:1002E000CCC12100CD012101CCC12102CD012103CE +:1002F000041800048000037CCD81A2A4C02A00045D +:100300009580000836A821A3CC290000C828000445 +:10031000C81C00110DE400409640FFFFC81C0011EE +:10032000CCC12170CD012171C820001296000000BF +:10033000C82000128000037CCC0000647C40C00018 +:100340007C410000CC000045CC00004840D40003B4 +:10035000CD41225CCD01A1FCC01A0001041CA1FD0D +:100360007DD9C00C7C42000008CC000106240001AD +:1003700006280002CE1D0000CE5D000098C0FFFAE6 +:10038000CE9D00007C408000A0000000CC80006278 +:100390007C40C00030D0000128CC00017C414000EE +:1003A000950000067C418000CD41216DCD81216EFC +:1003B000800000F2C81C0003C02200047E16000C5E +:1003C000CC210000C81C00047C42400098C00004FE +:1003D0007C42800080000001CDE50000CE41216913 +:1003E000CE81216ACDC1216B80000001CC01216C3E +:1003F0007C40C0007C4100007C4140007C4180008A +:100400007C41C00028A40008326400FF0E68003C54 +:100410009680000A7C0200007C4200001E3000032F +:10042000CC00006A9B00000342200005042000402D +:100430008000010F7C0240007E0240009A400000D4 +:100440000A64000130EC00109AC0000ACC0000627F +:10045000C02A0004C82C00217E92800CCC000041F0 +:10046000CC290000CEC000218000011FC83000044C +:10047000CD01216DCD41216EC83000037F1F000BDF +:1004800030F40007277800019740002A07B80124BC +:100490009F80000000000000800001347F1B80046A +:1004A000800001387F1B80058000013C7F1B80029B +:1004B000800001407F1B8003800001447F1B800778 +:1004C000800001487F1B80068000014D28A40008A1 +:1004D0009B80001928A400088000015D326400FFA1 +:1004E0009B80001528A400088000015D326400FF95 +:1004F0009B80001128A400088000015D326400FF89 +:100500009B80000D28A400088000015D326400FF7C +:100510009B80000928A400088000015D326400FF70 +:100520009B80000528A400088000015D326400FF64 +:1005300028A40008326400FF0E68003C9A80FEB2D6 +:1005400028EC00087C4340007C4380007C43C000D2 +:1005500096C00007CC000062CF412169CF81216A9B +:10056000CFC1216B80000001CC01216C8000000113 +:10057000CFF50000CC00006B8400037F0E68003CC8 +:100580009A800004C828001580000001D040007F38 +:100590009680FFAB7E02400084000239C00E00024C +:1005A000CC00004180000237CCC1304A7C40C00002 +:1005B0007C410000C01E000129240012C02200025C +:1005C00096400005C0260004C027FFFB7D25000BD8 +:1005D000C02600007DD2800B7E12C00B7D25000C52 +:1005E0007C4140007C418000CCC121699A80000A96 +:1005F000CD01216ACD41216B96C0FE83CD81216C56 +:10060000C830001897000000C830001880000001B2 +:10061000CC0000188400037FCC00007FC8140013B6 +:10062000C8180014CD41216B96C0FE77CD81216C96 +:1006300080000181C8300018C80C000898C0000074 +:10064000C80C00087C41000095000002000000007A +:100650007C414000C8200009CC400043CE01A1F4F9 +:10066000CC400044C00E80007C4240007C428000B0 +:100670002AAC001F96C0FE64C035F000CE4003E2F5 +:1006800032780003267C00087FF7C00B7FFBC00C8C +:100690002A780018CFC003E3CF8003E426B000021D +:1006A0007F3F0000CF0003E58000031D7C80C00079 +:1006B0007C40C00028D000083110000F9500000FCA +:1006C0002528000106A801B29E800000000000005D +:1006D000800001D3C0120800800001E1C814000F9F +:1006E000800001E8C8140010800001EFCCC1A2A472 +:1006F000800001F8C814001130D0003F0D2800150B +:100700009A8000120D28001E9A80001E0D280020DD +:100710009A8000230D24000F0D2800107E6A800CA3 +:100720009A8000260D2000040D2400140D280028B6 +:100730007E62400C7EA6800C9A80002AC8140011AC +:1007400080000001CCC1A2A4C01208007C4140007E +:100750007D0CC00CC012000829580003295C000C55 +:100760007C4200007DD1C00B262000147E1E400C70 +:100770007E4E800CCE81A2A480000001CD81A1FE1E +:10078000C814000F0410210E95400000C814000F7B +:10079000D051000080000001CCC1A2A4C8140010F8 +:1007A0000410210895400000C8140010D05100002A +:1007B00080000001CCC1A2A4CCC1A2A404100001FD +:1007C000CD0000198400037FCC00007FC810001901 +:1007D00099000000C8100019800000027C408000D1 +:1007E0000410210095400000C8140011D0510000F1 +:1007F0008000037CCCC1A2A47C40C000CC40000D92 +:1008000094C0FE01CC40000E7C4100009500000524 +:1008100008CC0001C8140005994000140000000035 +:1008200098C0FFFB7C410000800000027D0080003A +:10083000C81400057C40C0009940000CC818000C8A +:100840007C4100009580FDF0C820000EC81C000D02 +:10085000662000207E1E002C252400027E6240209F +:1008600080000001CCE600007C410000CC00006C60 +:10087000CC00006DC818001FC81C001E6598002021 +:100880007DD9C02C7CD4C00CCCDE000045DC00043B +:10089000C82800179680000FC00E000128680008C5 +:1008A0002AAC001632A800FF0EB000497F2F000BC3 +:1008B0009700000600000000C81400057C40C0003E +:1008C000800002217C41000080000224D040007F93 +:1008D00084000239CC000041CCC1304A94000000B1 +:1008E000C83C001A043C0005CFC1A2A4C0361F902A +:1008F000C0387FFF7C03C0107F7B400CCF41217C40 +:10090000CFC1217DCC01217EC03A00040434217F77 +:100910007F7B400CCC350000C83C00042BFC001F42 +:100920000438002097C00005CC0000629B800000C6 +:100930000BB8000180000245CC000071CC01A1F48D +:1009400004380016C0360002CF81A2A4880000003F +:10095000CF4120107C40C00028D0001C950000052D +:1009600004D40001CD40006580000001CD40006846 +:100970000954000280000001CD4000668400026A34 +:10098000C81803EA7C40C0009980FD9FC814001677 +:1009900008D000019940002BCD0000687C40800009 +:1009A000A0000000CC800062043C0005CFC1A2A4DE +:1009B000CC01A1F48400037FCC0000468800000035 +:1009C000CC00007F8400027CC81803EA7C40C00091 +:1009D0009980FD8DC814001608D0000199400019B7 +:1009E000CD0000687C408000A0000000CC80006248 +:1009F000043C0022CFC1A2A48400037FCC000047A6 +:100A000088000000CC00007FC81000169900000D7F +:100A1000CC400067800000027C408000C81803EAD8 +:100A20009980FD797C40C00094C00003C810001676 +:100A300099000004CCC00068800000027C40800067 +:100A400084000239C0148000CC000041CD41304AFE +:100A5000C014800099000000C81000168000000239 +:100A60007C408000C01200017C51400C80000001DD +:100A7000D05500007C40C0007C4100007C4140001B +:100A80007C418000291C001FCCC0004ACD00004BD7 +:100A900095C00003C01C8000CDC12010DD83000084 +:100AA000055C2000CC00006280000001D81F4100DE +:100AB0007C40C0007C4100007C4140007C418000C3 +:100AC000CCC0004CCD00004DDD830000055CA000D3 +:100AD00080000001D81F41007C40C0007C41000024 +:100AE0007C4140007C418000CCC0004ECD00004FD6 +:100AF000DD830000055CC00080000001D81F4100BC +:100B00007C40C0007C4100007C4140007C41800072 +:100B1000CCC00050CD000051DD830000055CF8E042 +:100B200080000001D81F41007C40C0007C410000D3 +:100B30007C4140007C418000CCC00052CD0000537D +:100B4000DD830000055CF88080000001D81F4100B3 +:100B50007C40C0007C4100007C4140007C41800022 +:100B6000CCC00054CD000055DD830000055CE000E2 +:100B700080000001D81F41007C40C0007C41000083 +:100B80007C4140007C418000CCC00056CD00005725 +:100B9000DD830000055CF00080000001D81F4100EB +:100BA0007C40C0007C4100007C4140007C418000D2 +:100BB000CCC00058CD000059DD830000055CF3FC7B +:100BC00080000001D81F4100D04320007C408000FD +:100BD000A0000000CC800062D043A0007C408000D8 +:100BE000A0000000CC800062D043C0007C408000A8 +:100BF000A0000000CC800062D043F8E07C40800080 +:100C0000A0000000CC800062D043F8807C408000CF +:100C1000A0000000CC800062D043E0007C40800057 +:100C2000A0000000CC800062D043F0007C40800037 +:100C3000A0000000CC800062D043F3FC7C40800028 +:100C4000A0000000CC800062C81403E0CC43000088 +:100C5000CC430000CC4300007D45C000CDC3000064 +:100C6000D04300007C408000A0000000CC800062E7 +:100C70007C40C000C81003E2C81403E5C81803E3B1 +:100C8000C81C03E4CD812169CDC1216ACCC1216B8F +:100C9000CC01216C042000047DA180007D964002DF +:100CA0009640FCD9CD8003E331280003C02DF0002D +:100CB000251800087DAD800B7DA9800C8000000107 +:100CC000CD8003E3308CFFFFD04D00007C408000DE +:100CD000A0000000CC800062C8140020155800025B +:100CE0009580FFFFC8140020CC00006ECC4121800D +:100CF0007C40C000CCC1218DCC41218128D0001F77 +:100D000034588000CD81218C9500FCBFCC412182DC +:100D1000C81400209940FFFFC81400208000000282 +:100D20007C4080007C40C00028D0001831100001B9 +:100D3000C016008095000003C02A00047CD4C00CBB +:100D4000CCC1217CCC41217DCC41217E7C418000E5 +:100D50001DB0000336A0217F9B000003419C0005CD +:100D6000041C004099C0000009DC0001CC210000F7 +:100D7000C82400042A6C001F419C00059AC0FFFA99 +:100D8000CC800062800000027C4080007C40C0007B +:100D900004D403E680000001CC5400008000037CF2 +:100DA000CC4003EAC01C8000044CA000CDC1201040 +:100DB0007C410000C814000904180000041C00084D +:100DC000CD80007109DC000105980001CD0D000007 +:100DD00099C0FFFCCC8000628000037CCD40007194 +:100DE000C00E0100CC000041CCC1304AC83C007F9D +:100DF000CC00007F80000001CC00007FCC00007F91 +:100E000088000000CC00007F00000000000000000F +:100E100000000000000000000000000000000000D2 +:100E200000000000000000000000000000000000C2 +:100E300000000000000000000000000000000000B2 +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000000000082 +:100E70000000000000000000000000000000000072 +:100E80000000000000000000000000000000000062 +:100E90000000000000000000000000000000000052 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000000000000000000000022 +:100ED0000000000000000000000000000000000012 +:100EE0000000000000000000000000000000000002 +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000000E1 +:100F100000000000000000000000000000000000D1 +:100F200000000000000000000000000000000000C1 +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000000000000000000000021 +:100FD0000000000000000000000000000000000011 +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200000000000000000000000000000000000C0 +:1010300000000000000000000000000000000000B0 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C0000000000000000000000000000000000020 +:1010D0000000000000000000000000000000000010 +:1010E0000000000000000000000000000000000000 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000000000000000000000CF +:1011200000000000000000000000000000000000BF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000000000000000F +:1011E00000000000000000000000000000000000FF +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:1012100000000000000000000000000000000000CE +:1012200000000000000000000000000000000000BE +:1012300000000000000000000000000000000000AE +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C000000000000000000000000000000000001E +:1012D000000000000000000000000000000000000E +:1012E00000000000000000000000000000000000FE +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200000000000000000000000000000000000BD +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000000002D +:1013C000000000000000000000000000000000001D +:1013D000000000000000000000000000000000000D +:1013E00000000000000000000000000000000000FD +:1013F00000000000000000000000000000000000ED +:10140000000103310010000400170006002100084D +:10141000002700280028002300290029002A002690 +:10142000002B0029002D0038002E003F002F004A1D +:101430000034004C00360030003900AF003A00CFD5 +:10144000003B00E4003C00FC003D016B003F00ADB0 +:1014500000410336004303490044018E004500FC6F +:10146000004601AC004701AC004801FE0049020CF7 +:10147000004A0255004B02820052025F0053027183 +:1014800000540287005702990060029D006102AC7F +:10149000006202B6006302C0006402CA006502D4A2 +:1014A000006602DE006702E8006802F2006902F6E8 +:1014B000006A02FA006B02FE006C0302006D030674 +:1014C000006E030A006F030E0070031200720363C4 +:1014D0000074036900790367007C031C000F037824 +:1014E000000F0378000F0378000F0378000F0378D4 +:1014F000000F0378000F0378000F0378000F0378C4 +:10150000000F0378000F0378000F0378000F0378B3 +:10151000000F0378000F0378000F0378000F0378A3 +:10152000000F0378000F0378000F0378000F037893 +:10153000000F0378000F0378000F0378000F037883 +:00000001FF diff --git a/firmware/radeon/RV730_pfp.bin.ihex b/firmware/radeon/RV730_pfp.bin.ihex new file mode 100644 index 000000000000..3d811ff0a1a8 --- /dev/null +++ b/firmware/radeon/RV730_pfp.bin.ihex @@ -0,0 +1,213 @@ +:100000007C408000A00000007E82800B8000000009 +:10001000DC030000CC800040D04000407C408000E9 +:10002000A00000007E82800BC818000E31980001ED +:100030007C4240009580023A7C428000C81C001C33 +:10004000C037C0007C40C0007C4100007CB4800B05 +:10005000C036000399C00000C81C001C7CB4800C92 +:1000600024D400027D654000CD400043CE80004393 +:10007000CD000043CC800040CE400040CE80004008 +:10008000CCC00040DC3A00009780FFDECD0000408D +:100090007C40C000800000187C410000D400034078 +:1000A000D4000FC0D4000FA2C818000E8000000CAE +:1000B00031980002D40003C0D4000FC0D4000FA2B6 +:1000C000C818000E288C000830CC000F3410000136 +:1000D0007D0D00088000000C7D91800BCC800040DD +:1000E000D04000407C408000A00000007E82800B59 +:1000F000D4000340D4000FC0D4000FA2CC80004035 +:10010000D04000407C408000A00000007E82800B38 +:10011000D40003C0D4000FC0D4000FA2CC80004094 +:10012000D04000407C408000A00000007E82800B18 +:10013000CC4003F980000249CC4003F8C037FFFFF0 +:100140007C414000CF41A29EC82003F8C81C03F99F +:1001500066200020C81803FB7DE1C02C7D58C00834 +:100160007CDCC02069100020C0360003CC000054A5 +:100170007CB4800C80000069CC8000407C41800011 +:10018000CD81A29ECC80004080000067CD800040E1 +:10019000C019FFFFCC800040CD81A29E7C40C000F2 +:1001A0007C4100007C414000CCC1A1FACD01A1F905 +:1001B000CD41A29DCCC00040CD000040CD400040CC +:1001C000CC4000407C408000A00000007E82800B7C +:1001D000CC000054CC8000407C40C0007C4100003A +:1001E0007C414000CCC1A1FACD01A1F9CD41A29D35 +:1001F000CCC00040CD000040CD400040D040004089 +:100200007C408000A00000007E82800B7C40C0000B +:1002100030D00001CCC1A29F95000003041400015E +:1002200004140002CD4003FBCC800040800000009D +:10023000CCC000407C40C000CC800040CCC1A2A219 +:1002400080000000CCC000407C40C00028D4001FCB +:10025000CC800040954000037C410000CCC000579A +:100260002918001FCCC0004095800003CD0000403D +:10027000CD00005880000249CC00007FC820001744 +:10028000C83000229A0000060E280001C824001E73 +:100290000A640001D4001240CE400040C036C000C5 +:1002A0009680000737747900041C0001CF4000409D +:1002B000CDC00040CF0003FA7C030000CA0C001040 +:1002C0007C41000094C000047C414000D42002C462 +:1002D000CDE000449B00000B7C418000CC00004B33 +:1002E000CDA00049CD200041CD600041CDA000410E +:1002F00006200001CE00005680000249CC00007F9D +:10030000C8280020C82C0021CC0000637EEA4001F0 +:10031000657400207F53402C269C00027DF5C02090 +:1003200069F80020CE80004BCE600049CDE000414E +:10033000CFA00041CE600041271C00027DF5C02007 +:1003400069F800207DB24001CF00004BCE6000492B +:10035000CDE00041CFA00041800000BCCE60004154 +:10036000C8200017C83000229A0000060E2800019D +:10037000C824001E0A640001D4001240CE40004090 +:10038000CA0C00107C41000094C0000BC036C000B5 +:100390009680000737747900041C0001CF400040AC +:1003A000CDC00040CF0003FA7C030000800000B500 +:1003B0007C414000CC000048800000EE00000000BE +:1003C000C8200017C81C00230E24000299C0001585 +:1003D0007C4180000A200001CE000056D400044079 +:1003E000CC000040C036C000CA140013964000077D +:1003F00037747900CF400040CC000040C83003FA89 +:1004000080000103CF000022CC000022954001466D +:10041000CC00007FCCA0004680000000CC2000462D +:1004200080000249CC000064C8200017C810001FDB +:100430009600000509100001D4000440CD000040E2 +:10044000CD000022CC800040D0400040C80C0025E8 +:1004500094C0FEECC8100008CD000040D4000FC0CE +:1004600080000000D4000FA27C40C0007C4100004E +:10047000CCC003FDCD0003FCCCC00042CD00004247 +:100480002914001F29180010319800073B5C000157 +:100490007D76000B998000057D5E400BCC0000420C +:1004A00080000249CC00004D29980001292C000849 +:1004B0009980003D32EC0001960000042930000CC8 +:1004C00080000249CC00004204140010CD400042DC +:1004D00033300001342800018400015DC81400039A +:1004E0009B40001B0438000C8400015DC81400030D +:1004F0009B400017043800088400015DC814000305 +:100500009B400013043800048400015DC8140003FC +:100510009B400015C80C03FD9A800009C81003FC1D +:100520009B000101CC00004D04140010CCC000421F +:10053000CD00004280000135CD40004296C000FA57 +:10054000CC00004D80000249CC00004E9AC0000350 +:10055000CC00004DCC00004EDF8300008000000086 +:10056000D80301FF9AC000F0CC00004D8000024982 +:10057000CC00004EC8180003C81C0003C8200003AC +:100580007D5D40037DA1C0037D5D400C2A10001FEE +:10059000299C001F7D1D000B7D17400B880000006B +:1005A0007E92800B96400004CC00004E80000249F1 +:1005B000CC00004204380008CF800042C808000385 +:1005C000C80C0003C8100003C8140003C8180003B7 +:1005D000C81C0003C8240003C828000329FC001F0E +:1005E0002AB0001F7FF3C00B28F0001F7FF3C00B61 +:1005F0002970001F7FF3C00B7D8880017DCCC00176 +:100600007E5100017E9540017C9080027CD4C00226 +:100610007CBC800B9AC000037C8F400B38B4000177 +:100620009B4000C1CC00004D9BC000BFCC00004EE1 +:10063000C80C03FDC81003FCCCC000428000016E52 +:10064000CD000042D4000340D4000FC0D4000FA25C +:10065000CC800040CC400040CC400040CC4000402A +:100660007C40C000CCC00040CCC0000D8000000029 +:10067000D04000407C40C0007C4100006514002058 +:100680007D4D402C245800027D5980207C41C000C3 +:10069000CD80004269980020CD800042CDC000424C +:1006A000C023C00005E400027CA0800B266400107B +:1006B0007CA4800CCC800040CDC00040CCC0004069 +:1006C00095C0000ECD00004009DC0001C8280003E1 +:1006D00096800008CE800040C834001D974000007E +:1006E000C834001D26A800088400024CCC2B000052 +:1006F00099C0FFF709DC0001DC3A00009780000494 +:100700007C418000800001A225980002A00000002A +:100710007D808000C818001D7C40C00064D00008A7 +:1007200095800000C818001DCC130000CC8000404C +:10073000CCC0004080000000CC400040C810001F2A +:100740007C40C000CC8000407CD1400CCD400040BB +:100750000518000180000000CD8000227C40C00010 +:10076000645000208400024CCC0000617CD0C02C7E +:10077000C8200017C8D60000994000087C438000BC +:10078000DF830000CFA0004F8400024CCC00006249 +:1007900080000000D040007F80000249CC00006251 +:1007A0008400024CCC000061C82000177C40C000CF +:1007B000C036FF00C810000DC0303FFF7CF5400B75 +:1007C0007D51800B7D81800F998000087CF3800B28 +:1007D000DF830000CFA0004F8400024CCC000062F9 +:1007E00080000000D040007F80000249CC00006201 +:1007F0008400024C7C40C00028DC000895C0001931 +:1008000030DC00107C41000099C0000464540020DA +:1008100080000208C91D00007D15002CC91E0000C3 +:100820007C4200007C4240007C4180007DE5C00BA2 +:100830007DE280079A80000E41AC00059AC000005E +:100840000AEC000130DC001099C000040000000038 +:100850008000020BC91D00008000020BC91E0000B1 +:10086000CC800040CCC00040D0400040C80C0025E7 +:1008700094C0FDE4C8100008CD000040D4000FC0B3 +:1008800080000000D4000FA2D4000340D4000FC0A9 +:10089000D4000FA2CC800040D04000407C408000BB +:1008A000A00000007E82800BD40003C0D4000FC0E3 +:1008B000D4000FA2CC800040D04000407C4080009B +:1008C000A00000007E82800B7C40C00030D000067B +:1008D0000D10000699000007C81400159940000586 +:1008E000CC000052D4000340D4000FC0D4000FA2AB +:1008F000CC800040CCC0004080000000D0400040D0 +:100900007C40C000CC4D0000DC3A00009780FDBD6B +:1009100004CC000180000242CC4D000080000000A9 +:10092000D040007FCC00007F80000000CC00007F22 +:10093000CC00007F88000000CC00007F0000000099 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000000000000000000000B6 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE0000000000000000000000000000000000006 +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000000000000000000000D5 +:100B200000000000000000000000000000000000C5 +:100B300000000000000000000000000000000000B5 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000000000000000000000005 +:100BF00000000000000000000000000000000000F5 +:100C0000000302220004022A0005009F00020003E4 +:100C10000006003C0007002700080191000900447D +:100C2000000A002D00100247001700F0002201D733 +:100C3000002301E80026004C0027005F0020011A75 +:100C4000002800920029004F002A0083002B006436 +:100C5000002F008D003200D80034023200360074BC +:100C60000039010A003C01FC003F009F00410005E3 +:100C7000004401940048019D004901C5004A01CF8C +:100C8000005502250056022D0060000A0061002A6E +:100C90000062003000630030006400300065003006 +:100CA0000066003000670030006800370069003FD0 +:100CB000006A0047006B0047006C0047006D00476A +:100CC000006E0047006F0047007000470073024746 +:100CD000007B024000000005000000050000000548 +:100CE00000000005000000050000000500000005F0 +:100CF00000000005000000050000000500000005E0 +:100D000000000005000000050000000500000005CF +:100D100000000005000000050000000500000005BF +:100D200000000005000000050000000500000005AF +:100D3000000000050000000500000005000000059F +:00000001FF diff --git a/firmware/radeon/RV770_me.bin.ihex b/firmware/radeon/RV770_me.bin.ihex new file mode 100644 index 000000000000..a0e16990a20a --- /dev/null +++ b/firmware/radeon/RV770_me.bin.ihex @@ -0,0 +1,341 @@ +:10000000CC0003EA7C408000A0000000CC800062AD +:1000100080000001D040007F80000001CC40004102 +:100020007C40C000C016000430D03FFF7D15000C9E +:10003000CC11000028D8001E3198000128DC001FD8 +:10004000C820000495C000067C424000CC0000623D +:100050007E56800CCC290000C82400047E26000BAC +:10006000958000067C42C000CC0000627ED7000C68 +:10007000CC310000C82C00047E2E000CCC000062A5 +:1000800031103FFF80000001CE1100007C40C00015 +:1000900080000001CC40004080000001CC4122578C +:1000A0007C418000CC400045CC400048CC41225CE3 +:1000B000CC41A1FC7C408000A0000000CC8000620C +:1000C000CC400045CC4000487C40C000CC41225C84 +:1000D000CC41A1FC7C408000A0000000CC800062EC +:1000E000CC000045CC000048CC41225CCC41A1FCB6 +:1000F0007C408000A0000000CC800062040CA1FDC8 +:10010000C0120001CC000045CC0000487CD0C00CDF +:10011000CC41225CCC41A1FCD04D00007C40800051 +:10012000A0000000CC80006280000001CC41225D74 +:100130007C4080007C40C000C02A00027C4100005E +:100140007D29000C3094000130980006309C03009B +:1001500029DC00087C4200007C4240009540000FF2 +:10016000C02E000405F022587F2F000CCC31000077 +:10017000C8280004CCC12169CD01216ACE81216B40 +:100180000DB40002CC01216C9740000E0DB40000AC +:100190008000007BC834000A0DB4000297400009BB +:1001A0000DB40000C02E000405F022587F2F000C73 +:1001B000CC310000C82800048000007BC834000A4D +:1001C000974000047E0280008000007BC834000A53 +:1001D0000DB400049740FF8C00000000CE01216D9B +:1001E000CE41216EC8280003C834000A9B40000499 +:1001F000043C00058400026DCC0000620DF4000098 +:100200009740000BC82C03E6CE81A2B7C030000691 +:100210007EF34028C03000207F6B80207FB3C02950 +:10022000CF81A2C480000001CFC1A2D10DF4000192 +:100230009740000BC82C03E7CE81A2BBC03000065C +:100240007EF34028C03000207F6B80207FB3C02920 +:10025000CF81A2C580000001CFC1A2D20DF400025F +:100260009740000BC82C03E8CE81A2BFC030000627 +:100270007EF34028C03000207F6B80207FB3C029F0 +:10028000CF81A2C680000001CFC1A2D3C82C03E950 +:10029000CE81A2C3C03000067EF34028C0300020CB +:1002A0007F6B80207FB3C029CF81A2C7800000016F +:1002B000CFC1A2D480000001CC4000427C40C000ED +:1002C0007C4100002914001D315400019940000DAB +:1002D00031181000C81C001109DC000195C0FFFF97 +:1002E000C81C0011CCC12100CD012101CCC12102CB +:1002F000CD012103041800048000039FCD81A2A436 +:10030000C02A00049580000836A821A3CC2900004B +:10031000C8280004C81C00110DE400409640FFFFEF +:10032000C81C0011CCC12170CD012171C820001260 +:1003300096000000C82000128000039FCC000064DB +:100340007C40C0007C410000CC000045CC0000484F +:1003500040D40003CD41225CCD01A1FCC01A0001B4 +:10036000041CA1FD7DD9C00C7C42000008CC00011A +:100370000624000106280002CE1D0000CE5D00000C +:1003800098C0FFFACE9D00007C408000A0000000D5 +:10039000CC8000627C40C00030D0000128CC00013D +:1003A0007C414000950000067C418000CD41216DDC +:1003B000CD81216E800000F3C81C0003C022000420 +:1003C0007E16000CCC210000C81C00047C424000BA +:1003D00098C000047C42800080000001CDE5000050 +:1003E000CE412169CE81216ACDC1216B80000001FF +:1003F000CC01216C7C40C0007C4100007C4140006D +:100400007C4180007C41C00028A40008326400FFC9 +:100410000E68003C9680000A7C0200007C420000CE +:100420001E300003CC00006A9B0000034220000540 +:1004300004200040800001107C0240007E02400049 +:100440009A4000000A64000130EC00109AC0000AD3 +:10045000CC000062C02A0004C82C00217E92800CCF +:10046000CC000041CC290000CEC00021800001203A +:10047000C8300004CD01216DCD41216EC83000038C +:100480007F1F000B30F40007277800019740002AF7 +:1004900007B801259F8000000000000080000135A2 +:1004A0007F1B8004800001397F1B80058000013D97 +:1004B0007F1B8002800001417F1B8003800001457B +:1004C0007F1B8007800001497F1B80068000014E52 +:1004D00028A400089B80001928A400088000015E61 +:1004E000326400FF9B80001528A400088000015E94 +:1004F000326400FF9B80001128A400088000015E88 +:10050000326400FF9B80000D28A400088000015E7B +:10051000326400FF9B80000928A400088000015E6F +:10052000326400FF9B80000528A400088000015E63 +:10053000326400FF28A40008326400FF0E68003C0B +:100540009A80FEB128EC00087C4340007C43800088 +:100550007C43C00096C00007CC000062CF412169F7 +:10056000CF81216ACFC1216B80000001CC01216CB9 +:1005700080000001CFF50000CC00006B840003A2D6 +:100580000E68003C9A800004C82800158000000115 +:10059000D040007F9680FFAB7E0240008400023B8B +:1005A000C00E0002CC00004180000239CCC1304AAC +:1005B0007C40C0007C410000C01E000129240012C4 +:1005C000C022000296400005C0260004C027FFFBA1 +:1005D0007D25000BC02600007DD2800B7E12C00B53 +:1005E0007D25000C7C4140007C418000CCC121690C +:1005F0009A80000ACD01216ACD41216B96C0FE820E +:10060000CD81216CC830001897000000C830001858 +:1006100080000001CC000018840003A2CC00007F01 +:10062000C8140013C8180014CD41216B96C0FE7683 +:10063000CD81216C80000182C8300018C80C0008F0 +:1006400098C00000C80C00087C4100009500000222 +:10065000000000007C414000C8200009CC4000435D +:10066000CE01A1F4CC400044C00E80007C4240008A +:100670007C4280002AAC001F96C0FE63C035F000AB +:10068000CE4003E232780003267C00087FF7C00BDF +:100690007FFBC00C2A780018CFC003E3CF8003E4AF +:1006A00026B000027F3F0000CF0003E58000031F5B +:1006B0007C80C0007C40C00028D000083110000FB2 +:1006C0009500000F2528000106A801B39E800000B8 +:1006D00000000000800001D4C0120800800001E288 +:1006E000C814000F800001E9C8140010800001F058 +:1006F000CCC1A2A4800001F9C814001130D0003F81 +:100700000D2800159A8000120D28001E9A80001EE8 +:100710000D2800209A8000230D24000F0D280010C2 +:100720007E6A800C9A8000260D2000040D2400149F +:100730000D2800287E62400C7EA6800C9A80002A3C +:10074000C814001180000001CCC1A2A4C01208008E +:100750007C4140007D0CC00CC012000829580003E9 +:10076000295C000C7C4200007DD1C00B26200014C7 +:100770007E1E400C7E4E800CCE81A2A48000000123 +:10078000CD81A1FEC814000F0410210E9540000079 +:10079000C814000FD051000080000001CCC1A2A4F9 +:1007A000C81400100410210895400000C81400105F +:1007B000D051000080000001CCC1A2A4CCC1A2A4F1 +:1007C00004100001CD000019840003A2CC00007FBA +:1007D000C810001999000000C8100019800000021C +:1007E0007C40800004102100095400019540FFFF67 +:1007F000C8140011D05100008000039FCCC1A2A4F6 +:100800007C40C000CC40000D94C0FDFFCC40000EE9 +:100810007C4100009500000508CC0001C8140005CB +:10082000994000140000000098C0FFFB7C410000CC +:10083000800000027D008000C81400057C40C000DC +:100840009940000CC818000C7C4100009580FDEE1A +:10085000C820000EC81C000D662000207E1E002C43 +:10086000252400027E62402080000001CCE60000CA +:100870007C410000CC00006CCC00006DC818001F4B +:10088000C81C001E659800207DD9C02C7CD4C00CEB +:10089000CCDE000045DC0004C82800179680000F5D +:1008A000C00E0001286800082AAC001632A800FF1C +:1008B0000EB000497F2F000B9700000600000000DB +:1008C000C81400057C40C000800002237C41000069 +:1008D00080000226D040007F8400023BCC00004113 +:1008E000CCC1304A94000000C83C001A043C00050A +:1008F000CFC1A2A4C0361F90C0387FFF7C03C010B8 +:100900007F7B400CCF41217CCFC1217DCC01217E5A +:10091000C03A00040434217F7F7B400CCC350000BA +:10092000C83C00042BFC001F0438002097C00005C1 +:10093000CC0000629B8000000BB8000180000247E1 +:10094000CC000071CC01A1F404380016C0360002BE +:10095000CF81A2A488000000CF4120107C40C000BD +:1009600028D0001C9500000504D40001CD4000658E +:1009700080000001CD4000680954000280000001A1 +:10098000CD4000668400026CC81803EA7C40C000B9 +:100990009980FD9DC814001608D000019940002BD5 +:1009A000CD0000687C408000A0000000CC80006288 +:1009B000043C0005CFC1A2A4CC01A1F4840003A291 +:1009C000CC00004688000000CC00007F8400027E3E +:1009D000C81803EA7C40C0009980FD8BC81400163B +:1009E00008D0000199400019CD0000687C408000CB +:1009F000A0000000CC800062043C0022CFC1A2A471 +:100A0000840003A2CC00004788000000CC00007FD7 +:100A1000C81000169900000DCC400067800000024D +:100A20007C408000C81803EA9980FD777C40C000B4 +:100A300094C00003C810001699000004CCC00068E0 +:100A4000800000027C4080008400023BC0148000D3 +:100A5000CC000041CD41304AC01480009900000014 +:100A6000C8100016800000027C408000C012000107 +:100A70007C51400C80000001D05500007C40C0003B +:100A80007C4100007C4140007C418000291C001F0B +:100A9000CCC0004ACD00004B95C00003C01C8000B4 +:100AA000CDC12010DD830000055C2000CC00006279 +:100AB00080000001D81F41007C40C0007C41000044 +:100AC0007C4140007C418000CCC0004CCD00004DFA +:100AD000DD830000055CA00080000001D81F4100FC +:100AE0007C40C0007C4100007C4140007C41800093 +:100AF000CCC0004ECD00004FDD830000055CC0007F +:100B000080000001D81F41007C40C0007C410000F3 +:100B10007C4140007C418000CCC00050CD000051A1 +:100B2000DD830000055CF8E080000001D81F410073 +:100B30007C40C0007C4100007C4140007C41800042 +:100B4000CCC00052CD000053DD830000055CF8806E +:100B500080000001D81F41007C40C0007C410000A3 +:100B60007C4140007C418000CCC00054CD00005549 +:100B7000DD830000055CE00080000001D81F41001B +:100B80007C40C0007C4100007C4140007C418000F2 +:100B9000CCC00056CD000057DD830000055CF0009E +:100BA00080000001D81F41007C40C0007C41000053 +:100BB0007C4140007C418000CCC00058CD000059F1 +:100BC000DD830000055CF3FC80000001D81F4100BC +:100BD000D04320007C408000A0000000CC80006258 +:100BE000D043A0007C408000A0000000CC800062C8 +:100BF000D043C0007C408000A0000000CC80006298 +:100C0000D043F8E07C408000A0000000CC8000626F +:100C1000D043F8807C408000A0000000CC800062BF +:100C2000D043E0007C408000A0000000CC80006247 +:100C3000D043F0007C408000A0000000CC80006227 +:100C4000D043F3FC7C408000A0000000CC80006218 +:100C5000C81403E0CC430000CC430000CC430000A8 +:100C60007D45C000CDC30000D04300007C40800023 +:100C7000A0000000CC8000627C40C000C81003E2ED +:100C8000C81403E5C81803E3C81C03E4CD81216937 +:100C9000CDC1216ACCC1216BCC01216C04200004A0 +:100CA0007DA180007D9640029640FCD7CD8003E375 +:100CB00031280003C02DF000251800087DAD800B01 +:100CC0007DA9800C80000001CD8003E3308CFFFF04 +:100CD000D04D00007C408000A0000000CC8000626D +:100CE0007C40C0007C4100002924001832640001CF +:100CF0009A400013C8140020155800029580FFFF89 +:100D0000C8140020CC00006ECCC12180CD01218D03 +:100D1000CC4121812914001F34588000CD81218CC1 +:100D20009540FCB9CC412182C81400209940FFFFB6 +:100D3000C8140020800000027C4080007C414000FC +:100D40007C4180007C41C00065B400207F57402C6E +:100D5000D437810047740004D437810047740004FD +:100D6000D43781004774000409DC0004D4378100C3 +:100D700099C0FFF8477400042924001FC0380019E7 +:100D80009640FCA1C03E0004CF8121F837E021F954 +:100D9000CC210000C82000042A20001832200001C5 +:100DA0009A00FFFBCF8121F8800000027C40800088 +:100DB0007C40C00028D0001831100001C01600800F +:100DC00095000003C02A00047CD4C00CCCC1217C57 +:100DD000CC41217DCC41217E7C4180001DB00003AF +:100DE00036A0217F9B000003419C0005041C0040AD +:100DF00099C0000009DC0001CC210000C8240004D7 +:100E00002A6C001F419C00059AC0FFFACC8000624A +:100E1000800000027C4080007C40C00004D403E6D7 +:100E200080000001CC5400008000039FCC4003EA06 +:100E3000C01C8000044CA000CDC120107C410000EB +:100E4000C814000904180000041C0008CD800071BB +:100E500009DC000105980001CD0D000099C0FFFCE0 +:100E6000CC8000628000039FCD400071C00E010065 +:100E7000CC000041CCC1304AC83C007FCC00007F90 +:100E800080000001CC00007FCC00007F88000000C3 +:100E9000CC00007F00000000000000000000000007 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000000000000000000000022 +:100ED0000000000000000000000000000000000012 +:100EE0000000000000000000000000000000000002 +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000000E1 +:100F100000000000000000000000000000000000D1 +:100F200000000000000000000000000000000000C1 +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000000000000000000000021 +:100FD0000000000000000000000000000000000011 +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200000000000000000000000000000000000C0 +:1010300000000000000000000000000000000000B0 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C0000000000000000000000000000000000020 +:1010D0000000000000000000000000000000000010 +:1010E0000000000000000000000000000000000000 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000000000000000000000CF +:1011200000000000000000000000000000000000BF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000000000000000F +:1011E00000000000000000000000000000000000FF +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:1012100000000000000000000000000000000000CE +:1012200000000000000000000000000000000000BE +:1012300000000000000000000000000000000000AE +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C000000000000000000000000000000000001E +:1012D000000000000000000000000000000000000E +:1012E00000000000000000000000000000000000FE +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200000000000000000000000000000000000BD +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000000002D +:1013C000000000000000000000000000000000001D +:1013D000000000000000000000000000000000000D +:1013E00000000000000000000000000000000000FD +:1013F00000000000000000000000000000000000ED +:10140000000103330010000400170006002100084B +:10141000002700280028002300290029002A002690 +:10142000002B0029002D0038002E003F002F004A1D +:101430000034004C00360030003900AF003A00D0D4 +:10144000003B00E5003C00FD003D016C003F00ADAD +:10145000004103380043036C0044018F004500FD48 +:10146000004601AD004701AD004802000049020EF0 +:10147000004A0257004B028400520261005302737B +:10148000005402890057029B0060029F006102AE77 +:10149000006202B8006302C2006402CC006502D69A +:1014A000006602E0006702EA006802F4006902F8E0 +:1014B000006A02FC006B0300006C0304006D03086B +:1014C000006E030C006F031000700314007203869B +:1014D0000074038C0079038A007C031E000F039BB9 +:1014E000000F039B000F039B000F039B000F039B48 +:1014F000000F039B000F039B000F039B000F039B38 +:10150000000F039B000F039B000F039B000F039B27 +:10151000000F039B000F039B000F039B000F039B17 +:10152000000F039B000F039B000F039B000F039B07 +:10153000000F039B000F039B000F039B000F039BF7 +:00000001FF diff --git a/firmware/radeon/RV770_pfp.bin.ihex b/firmware/radeon/RV770_pfp.bin.ihex new file mode 100644 index 000000000000..a2d1619107de --- /dev/null +++ b/firmware/radeon/RV770_pfp.bin.ihex @@ -0,0 +1,213 @@ +:100000007C408000A00000007E82800B8000000009 +:10001000DC030000CC800040D04000407C408000E9 +:10002000A00000007E82800BC818000E31980001ED +:100030007C424000958002527C428000C81C001C1B +:10004000C037C0007C40C0007C4100007CB4800B05 +:10005000C036000399C00000C81C001C7CB4800C92 +:1000600024D400027D654000CD400043CE80004393 +:10007000CD000043CC800040CE400040CE80004008 +:10008000CCC00040DC3A00009780FFDECD0000408D +:100090007C40C000800000187C410000D400034078 +:1000A000D4000FC0D4000FA2C818000E8000000CAE +:1000B00031980002D40003C0D4000FC0D4000FA2B6 +:1000C000C818000E288C000830CC000F3410000136 +:1000D0007D0D00088000000C7D91800BCC800040DD +:1000E000D04000407C408000A00000007E82800B59 +:1000F000D4000340D4000FC0D4000FA2CC80004035 +:10010000D04000407C408000A00000007E82800B38 +:10011000D40003C0D4000FC0D4000FA2CC80004094 +:10012000D04000407C408000A00000007E82800B18 +:10013000CC4003F980000261CC4003F8C82003F8EA +:10014000C81C03F9C81803FBC037FFFF7C414000FF +:10015000CF41A29E662000207DE1C02C7D58C008C2 +:100160007CDCC02068D00020C0360003CC000054E6 +:100170007CB4800C8000006ACC8000407C41800010 +:10018000CD81A29ECC800040CD80004080000068E0 +:10019000CC000054C019FFFFCC800040CD81A29E4E +:1001A0007C40C0007C4100007C414000CCC1A1FAF1 +:1001B000CD01A1F9CD41A29DCCC00040CD000040B1 +:1001C000CD400040CC4000407C408000A0000000BA +:1001D0007E82800BCC000054CC8000407C40C0006C +:1001E0007C4100007C414000CCC1A1FACD01A1F9C5 +:1001F000CD41A29DCCC00040CD000040CD4000408C +:10020000D04000407C408000A00000007E82800B37 +:100210007C40C00030D00001CCC1A29F95000003FB +:100220000414000104140002CD4003FBCC80004004 +:1002300080000000CCC000407C40C000CC8000406A +:10024000CCC1A2A280000000CCC000407C40C00015 +:1002500028D4001FCC800040954000037C41000062 +:10026000CCC000572918001FCCC000409580000367 +:10027000CD000040CD00005880000261CC00007F1E +:10028000C8200017C83000229A0000060E2800017E +:10029000C824001E0A640001D4001240CE40004071 +:1002A000C036C0009680000737747900041C000136 +:1002B000CF400040CDC00040CF0003FA7C030000D7 +:1002C000CA0C00107C41000094C000047C41400036 +:1002D000D42002C4CDE000449B00000B7C41800090 +:1002E000CC00004BCDA00049CD200041CD600041A5 +:1002F000CDA0004106200001CE0000568000026122 +:10030000CC00007FC8280020C82C0021CC0000634E +:100310007EEA4001657400207F53402C269C000239 +:100320007DF5C02069F80020CE80004BCE600049EA +:10033000CDE00041CFA00041CE600041271C00026B +:100340007DF5C02069F800207DB24001CF00004B50 +:10035000CE600049CDE00041CFA00041800000BD4B +:10036000CE600041C8200017C83000229A00000665 +:100370000E280001C824001E0A640001D4001240A7 +:10038000CE400040CA0C00107C41000094C0000B1D +:10039000C036C0009680000737747900041C000145 +:1003A000CF400040CDC00040CF0003FA7C030000E6 +:1003B000800000B67C414000CC000048800000EF87 +:1003C00000000000C8200017C81C00230E240002F3 +:1003D00099C000157C4180000A200001CE00005623 +:1003E000D4000440CC000040C036C000CA14001342 +:1003F0009640000737747900CF400040CC000040A1 +:10040000C83003FA80000104CF000022CC00002293 +:100410009540015DCC00007FCCA00046800000002C +:10042000CC20004680000261CC000064C820001788 +:10043000C810001F9600000509100001D4000440F8 +:10044000CD000040CD000022CC800040D0400040D4 +:10045000C80C002594C0FEEBC8100008CD00004079 +:10046000D4000FC080000000D4000FA27C40C00068 +:100470007C410000CCC003FDCD0003FCCCC0004299 +:10048000CD0000422914001F2918001031980007E0 +:100490003B5C00017D76000B998000057D5E400B82 +:1004A000CC00004280000261CC00004D2998000180 +:1004B000292C00089980003D32EC000196000004D0 +:1004C0002930000C80000261CC00004204140010AE +:1004D000CD40004233300001342800018400015E29 +:1004E000C81400039B40001B0438000C8400015E0C +:1004F000C81400039B400017043800088400015E04 +:10050000C81400039B400013043800048400015EFB +:10051000C81400039B400015C80C03FD9A80000915 +:10052000C81003FC9B000118CC00004D04140010FF +:10053000CCC00042CD00004280000136CD400042D8 +:1005400096C00111CC00004D80000261CC00004E2D +:100550009AC00003CC00004DCC00004EDF830000A9 +:1005600080000000D80301FF9AC00107CC00004DB5 +:1005700080000261CC00004EC8180003C81C0003B4 +:10058000C82000037D5D40037DA1C0037D5D400C5C +:100590002A10001F299C001F7D1D000B7D17400B9A +:1005A000880000007E92800B96400004CC00004E34 +:1005B00080000261CC00004204380008CF80004275 +:1005C000C8080003C80C0003C8100003C8140003C7 +:1005D000C8180003C81C0003C8240003C82800036F +:1005E00029FC001F2AB0001F7FF3C00B28F0001F5A +:1005F0007FF3C00B2970001F7FF3C00B7D88800143 +:100600007DCCC0017E5100017E9540017C9080022E +:100610007CD4C0027CBC800B9AC000037C8F400B52 +:1006200038B400019B4000D8CC00004D9BC000D6E0 +:10063000CC00004EC80C03FDC81003FCCCC0004227 +:100640008000016FCD000042D4000340D4000FC0F1 +:10065000D4000FA2CC800040CC400040CC400040F1 +:10066000CC4000407C40C000CCC00040CCC0000D5D +:1006700080000000D04000407C40C0007C41000071 +:10068000651400207D4D402C245800027D598020A7 +:100690007C41C000CD80004269980020CD8000429E +:1006A000CDC00042C023C00005E400027CA0800B46 +:1006B000266400107CA4800CCC800040CDC000409B +:1006C000CCC0004095C0000ECD00004009DC000108 +:1006D000C828000396800008CE800040C834001D62 +:1006E00097400000C834001D26A80008840002645A +:1006F000CC2B000099C0FFF709DC0001DC3A0000B8 +:10070000978000047C418000800001A325980002AE +:10071000A00000007D808000C818001D7C40C00043 +:1007200064D0000895800000C818001DCC1300009C +:10073000CC800040CCC0004080000000CC40004095 +:10074000C810001F7C40C000CC8000407CD1400C11 +:10075000CD4000400518000180000000CD8000223F +:100760007C40C0006450002084000264CC00006122 +:100770007CD0C02CC8200017C8D6000099400008C3 +:100780007C438000DF830000CFA0004F8400026420 +:10079000CC00006280000000D040007F8000026139 +:1007A000CC00006284000264CC000061C820001705 +:1007B0007C40C000C036FF00C810000DC0303FFFB5 +:1007C0007CF5400B7D51800B7D81800F9980000866 +:1007D0007CF3800BDF830000CFA0004F8400026415 +:1007E000CC00006280000000D040007F80000261E9 +:1007F000CC000062840002647C40C00028DC000859 +:1008000095C0001930DC00107C41000099C0000444 +:100810006454002080000209C91D00007D15002CD1 +:10082000C91E00007C4200007C4240007C418000E8 +:100830007DE5C00B7DE280079A80000E41AC00058B +:100840009AC000000AEC000130DC001099C00004DE +:10085000000000008000020CC91D00008000020C96 +:10086000C91E0000CC800040CCC00040D0400040F9 +:10087000C80C002594C0FDE3C8100008CD0000405E +:10088000D4000FC080000000D4000FA2D4000340A9 +:10089000D4000FC0D4000FA2CC800040D040004054 +:1008A0007C408000A00000007E82800BD40003C04A +:1008B000D4000FC0D4000FA2CC800040D040004034 +:1008C0007C408000A00000007E82800B7C40C00045 +:1008D00030D000060D10000699000007C81400155E +:1008E00099400005CC000052D4000340D4000FC052 +:1008F000D4000FA2CC800040CCC00040800000009B +:10090000D04000407C40C000CC4D0000DC3A0000EC +:100910009780FDBC04CC000180000243CC4D000058 +:100920007C40C0007C410000292400183264000192 +:100930009640000FCC8000407C4140007C4180000C +:100940007C41C000CCC00043CD00004331DC7FFFC0 +:10095000CDC00043CCC00040CD000040CD400040A1 +:10096000CD80004080000000CDC00040CCC00040E1 +:10097000CD00004080000000D0400040800000001A +:10098000D040007FCC00007F80000000CC00007FC2 +:10099000CC00007F88000000CC00007F0000000039 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000000000000000000000B6 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE0000000000000000000000000000000000006 +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000000000000000000000D5 +:100B200000000000000000000000000000000000C5 +:100B300000000000000000000000000000000000B5 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000000000000000000000005 +:100BF00000000000000000000000000000000000F5 +:100C0000000302230004022B000500A000020003E1 +:100C10000006003C0007002700080192000900447C +:100C2000000A002D0010025F001700F1002201D819 +:100C3000002301E90026004C0027005F0020011B73 +:100C4000002800930029004F002A0084002B006533 +:100C5000002F008E003200D90034023300360075B8 +:100C60000039010B003C01FD003F00A0004102489B +:100C7000004401950048019E004901C6004A01D088 +:100C8000005502260056022E0060000A0061002A6C +:100C90000062003000630030006400300065003006 +:100CA0000066003000670030006800370069003FD0 +:100CB000006A0047006B0047006C0047006D00476A +:100CC000006E0047006F0047007000470073025F2E +:100CD000007B024100000005000000050000000547 +:100CE00000000005000000050000000500000005F0 +:100CF00000000005000000050000000500000005E0 +:100D000000000005000000050000000500000005CF +:100D100000000005000000050000000500000005BF +:100D200000000005000000050000000500000005AF +:100D3000000000050000000500000005000000059F +:00000001FF diff --git a/fs/nfs/client.c b/fs/nfs/client.c index e350bd6a2334..a7ce15d3c248 100644 --- a/fs/nfs/client.c +++ b/fs/nfs/client.c @@ -933,10 +933,6 @@ static int nfs_probe_fsinfo(struct nfs_server *server, struct nfs_fh *mntfh, str goto out_error; nfs_server_set_fsinfo(server, &fsinfo); - error = bdi_init(&server->backing_dev_info); - if (error) - goto out_error; - /* Get some general file system info */ if (server->namelen == 0) { @@ -995,6 +991,12 @@ static struct nfs_server *nfs_alloc_server(void) return NULL; } + if (bdi_init(&server->backing_dev_info)) { + nfs_free_iostats(server->io_stats); + kfree(server); + return NULL; + } + return server; } diff --git a/fs/nfs/super.c b/fs/nfs/super.c index de935692d40d..f1cc0587cfef 100644 --- a/fs/nfs/super.c +++ b/fs/nfs/super.c @@ -2190,8 +2190,8 @@ static void nfs_kill_super(struct super_block *s) { struct nfs_server *server = NFS_SB(s); - bdi_unregister(&server->backing_dev_info); kill_anon_super(s); + bdi_unregister(&server->backing_dev_info); nfs_fscache_release_super_cookie(s); nfs_free_server(server); } diff --git a/fs/ubifs/budget.c b/fs/ubifs/budget.c index ee1ce68fd98b..076ca50e9933 100644 --- a/fs/ubifs/budget.c +++ b/fs/ubifs/budget.c @@ -715,7 +715,7 @@ long long ubifs_get_free_space_nolock(struct ubifs_info *c) * ubifs_get_free_space - return amount of free space. * @c: UBIFS file-system description object * - * This function calculates and retuns amount of free space to report to + * This function calculates and returns amount of free space to report to * user-space. */ long long ubifs_get_free_space(struct ubifs_info *c) diff --git a/fs/ubifs/commit.c b/fs/ubifs/commit.c index f3a7945527fb..4775af401167 100644 --- a/fs/ubifs/commit.c +++ b/fs/ubifs/commit.c @@ -510,7 +510,7 @@ int dbg_check_old_index(struct ubifs_info *c, struct ubifs_zbranch *zroot) int lnum, offs, len, err = 0, uninitialized_var(last_level), child_cnt; int first = 1, iip; struct ubifs_debug_info *d = c->dbg; - union ubifs_key lower_key, upper_key, l_key, u_key; + union ubifs_key uninitialized_var(lower_key), upper_key, l_key, u_key; unsigned long long uninitialized_var(last_sqnum); struct ubifs_idx_node *idx; struct list_head list; diff --git a/fs/ubifs/debug.c b/fs/ubifs/debug.c index ce2cd8343618..dbc093afd946 100644 --- a/fs/ubifs/debug.c +++ b/fs/ubifs/debug.c @@ -210,6 +210,20 @@ const char *dbg_cstate(int cmt_state) } } +const char *dbg_jhead(int jhead) +{ + switch (jhead) { + case GCHD: + return "0 (GC)"; + case BASEHD: + return "1 (base)"; + case DATAHD: + return "2 (data)"; + default: + return "unknown journal head"; + } +} + static void dump_ch(const struct ubifs_ch *ch) { printk(KERN_DEBUG "\tmagic %#x\n", le32_to_cpu(ch->magic)); @@ -623,8 +637,9 @@ void dbg_dump_budg(struct ubifs_info *c) /* If we are in R/O mode, journal heads do not exist */ if (c->jheads) for (i = 0; i < c->jhead_cnt; i++) - printk(KERN_DEBUG "\tjhead %d\t LEB %d\n", - c->jheads[i].wbuf.jhead, c->jheads[i].wbuf.lnum); + printk(KERN_DEBUG "\tjhead %s\t LEB %d\n", + dbg_jhead(c->jheads[i].wbuf.jhead), + c->jheads[i].wbuf.lnum); for (rb = rb_first(&c->buds); rb; rb = rb_next(rb)) { bud = rb_entry(rb, struct ubifs_bud, rb); printk(KERN_DEBUG "\tbud LEB %d\n", bud->lnum); @@ -648,9 +663,90 @@ void dbg_dump_budg(struct ubifs_info *c) void dbg_dump_lprop(const struct ubifs_info *c, const struct ubifs_lprops *lp) { - printk(KERN_DEBUG "LEB %d lprops: free %d, dirty %d (used %d), " - "flags %#x\n", lp->lnum, lp->free, lp->dirty, - c->leb_size - lp->free - lp->dirty, lp->flags); + int i, spc, dark = 0, dead = 0; + struct rb_node *rb; + struct ubifs_bud *bud; + + spc = lp->free + lp->dirty; + if (spc < c->dead_wm) + dead = spc; + else + dark = ubifs_calc_dark(c, spc); + + if (lp->flags & LPROPS_INDEX) + printk(KERN_DEBUG "LEB %-7d free %-8d dirty %-8d used %-8d " + "free + dirty %-8d flags %#x (", lp->lnum, lp->free, + lp->dirty, c->leb_size - spc, spc, lp->flags); + else + printk(KERN_DEBUG "LEB %-7d free %-8d dirty %-8d used %-8d " + "free + dirty %-8d dark %-4d dead %-4d nodes fit %-3d " + "flags %#-4x (", lp->lnum, lp->free, lp->dirty, + c->leb_size - spc, spc, dark, dead, + (int)(spc / UBIFS_MAX_NODE_SZ), lp->flags); + + if (lp->flags & LPROPS_TAKEN) { + if (lp->flags & LPROPS_INDEX) + printk(KERN_CONT "index, taken"); + else + printk(KERN_CONT "taken"); + } else { + const char *s; + + if (lp->flags & LPROPS_INDEX) { + switch (lp->flags & LPROPS_CAT_MASK) { + case LPROPS_DIRTY_IDX: + s = "dirty index"; + break; + case LPROPS_FRDI_IDX: + s = "freeable index"; + break; + default: + s = "index"; + } + } else { + switch (lp->flags & LPROPS_CAT_MASK) { + case LPROPS_UNCAT: + s = "not categorized"; + break; + case LPROPS_DIRTY: + s = "dirty"; + break; + case LPROPS_FREE: + s = "free"; + break; + case LPROPS_EMPTY: + s = "empty"; + break; + case LPROPS_FREEABLE: + s = "freeable"; + break; + default: + s = NULL; + break; + } + } + printk(KERN_CONT "%s", s); + } + + for (rb = rb_first((struct rb_root *)&c->buds); rb; rb = rb_next(rb)) { + bud = rb_entry(rb, struct ubifs_bud, rb); + if (bud->lnum == lp->lnum) { + int head = 0; + for (i = 0; i < c->jhead_cnt; i++) { + if (lp->lnum == c->jheads[i].wbuf.lnum) { + printk(KERN_CONT ", jhead %s", + dbg_jhead(i)); + head = 1; + } + } + if (!head) + printk(KERN_CONT ", bud of jhead %s", + dbg_jhead(bud->jhead)); + } + } + if (lp->lnum == c->gc_lnum) + printk(KERN_CONT ", GC LEB"); + printk(KERN_CONT ")\n"); } void dbg_dump_lprops(struct ubifs_info *c) @@ -724,7 +820,7 @@ void dbg_dump_leb(const struct ubifs_info *c, int lnum) printk(KERN_DEBUG "(pid %d) start dumping LEB %d\n", current->pid, lnum); - sleb = ubifs_scan(c, lnum, 0, c->dbg->buf); + sleb = ubifs_scan(c, lnum, 0, c->dbg->buf, 0); if (IS_ERR(sleb)) { ubifs_err("scan error %d", (int)PTR_ERR(sleb)); return; @@ -909,8 +1005,10 @@ out: ubifs_msg("saved lprops statistics dump"); dbg_dump_lstats(&d->saved_lst); ubifs_get_lp_stats(c, &lst); + ubifs_msg("current lprops statistics dump"); - dbg_dump_lstats(&d->saved_lst); + dbg_dump_lstats(&lst); + spin_lock(&c->space_lock); dbg_dump_budg(c); spin_unlock(&c->space_lock); diff --git a/fs/ubifs/debug.h b/fs/ubifs/debug.h index c1cd73b2e06e..29d960101ea6 100644 --- a/fs/ubifs/debug.h +++ b/fs/ubifs/debug.h @@ -271,6 +271,7 @@ void ubifs_debugging_exit(struct ubifs_info *c); /* Dump functions */ const char *dbg_ntype(int type); const char *dbg_cstate(int cmt_state); +const char *dbg_jhead(int jhead); const char *dbg_get_key_dump(const struct ubifs_info *c, const union ubifs_key *key); void dbg_dump_inode(const struct ubifs_info *c, const struct inode *inode); @@ -321,6 +322,8 @@ void dbg_check_heap(struct ubifs_info *c, struct ubifs_lpt_heap *heap, int cat, int dbg_check_lprops(struct ubifs_info *c); int dbg_check_lpt_nodes(struct ubifs_info *c, struct ubifs_cnode *cnode, int row, int col); +int dbg_check_inode_size(struct ubifs_info *c, const struct inode *inode, + loff_t size); /* Force the use of in-the-gaps method for testing */ @@ -425,6 +428,7 @@ void dbg_debugfs_exit_fs(struct ubifs_info *c); #define dbg_ntype(type) "" #define dbg_cstate(cmt_state) "" +#define dbg_jhead(jhead) "" #define dbg_get_key_dump(c, key) ({}) #define dbg_dump_inode(c, inode) ({}) #define dbg_dump_node(c, node) ({}) @@ -460,6 +464,7 @@ void dbg_debugfs_exit_fs(struct ubifs_info *c); #define dbg_check_heap(c, heap, cat, add_pos) ({}) #define dbg_check_lprops(c) 0 #define dbg_check_lpt_nodes(c, cnode, row, col) 0 +#define dbg_check_inode_size(c, inode, size) 0 #define dbg_force_in_the_gaps_enabled 0 #define dbg_force_in_the_gaps() 0 #define dbg_failure_mode 0 diff --git a/fs/ubifs/file.c b/fs/ubifs/file.c index 6d34dc7e33e1..2e6481a7701c 100644 --- a/fs/ubifs/file.c +++ b/fs/ubifs/file.c @@ -21,34 +21,32 @@ */ /* - * This file implements VFS file and inode operations of regular files, device + * This file implements VFS file and inode operations for regular files, device * nodes and symlinks as well as address space operations. * - * UBIFS uses 2 page flags: PG_private and PG_checked. PG_private is set if the - * page is dirty and is used for budgeting purposes - dirty pages should not be - * budgeted. The PG_checked flag is set if full budgeting is required for the - * page e.g., when it corresponds to a file hole or it is just beyond the file - * size. The budgeting is done in 'ubifs_write_begin()', because it is OK to - * fail in this function, and the budget is released in 'ubifs_write_end()'. So - * the PG_private and PG_checked flags carry the information about how the page - * was budgeted, to make it possible to release the budget properly. + * UBIFS uses 2 page flags: @PG_private and @PG_checked. @PG_private is set if + * the page is dirty and is used for optimization purposes - dirty pages are + * not budgeted so the flag shows that 'ubifs_write_end()' should not release + * the budget for this page. The @PG_checked flag is set if full budgeting is + * required for the page e.g., when it corresponds to a file hole or it is + * beyond the file size. The budgeting is done in 'ubifs_write_begin()', because + * it is OK to fail in this function, and the budget is released in + * 'ubifs_write_end()'. So the @PG_private and @PG_checked flags carry + * information about how the page was budgeted, to make it possible to release + * the budget properly. * - * A thing to keep in mind: inode's 'i_mutex' is locked in most VFS operations - * we implement. However, this is not true for '->writepage()', which might be - * called with 'i_mutex' unlocked. For example, when pdflush is performing - * write-back, it calls 'writepage()' with unlocked 'i_mutex', although the - * inode has 'I_LOCK' flag in this case. At "normal" work-paths 'i_mutex' is - * locked in '->writepage', e.g. in "sys_write -> alloc_pages -> direct reclaim - * path'. So, in '->writepage()' we are only guaranteed that the page is - * locked. + * A thing to keep in mind: inode @i_mutex is locked in most VFS operations we + * implement. However, this is not true for 'ubifs_writepage()', which may be + * called with @i_mutex unlocked. For example, when pdflush is doing background + * write-back, it calls 'ubifs_writepage()' with unlocked @i_mutex. At "normal" + * work-paths the @i_mutex is locked in 'ubifs_writepage()', e.g. in the + * "sys_write -> alloc_pages -> direct reclaim path". So, in 'ubifs_writepage()' + * we are only guaranteed that the page is locked. * - * Similarly, 'i_mutex' does not have to be locked in readpage(), e.g., - * readahead path does not have it locked ("sys_read -> generic_file_aio_read - * -> ondemand_readahead -> readpage"). In case of readahead, 'I_LOCK' flag is - * not set as well. However, UBIFS disables readahead. - * - * This, for example means that there might be 2 concurrent '->writepage()' - * calls for the same inode, but different inode dirty pages. + * Similarly, @i_mutex is not always locked in 'ubifs_readpage()', e.g., the + * read-ahead path does not lock it ("sys_read -> generic_file_aio_read -> + * ondemand_readahead -> readpage"). In case of readahead, @I_LOCK flag is not + * set as well. However, UBIFS disables readahead. */ #include "ubifs.h" @@ -449,9 +447,9 @@ static int ubifs_write_begin(struct file *file, struct address_space *mapping, /* * We change whole page so no need to load it. But we * have to set the @PG_checked flag to make the further - * code the page is new. This might be not true, but it - * is better to budget more that to read the page from - * the media. + * code know that the page is new. This might be not + * true, but it is better to budget more than to read + * the page from the media. */ SetPageChecked(page); skipped_read = 1; @@ -497,8 +495,8 @@ static int ubifs_write_begin(struct file *file, struct address_space *mapping, } /* - * Whee, we aquired budgeting quickly - without involving - * garbage-collection, committing or forceing write-back. We return + * Whee, we acquired budgeting quickly - without involving + * garbage-collection, committing or forcing write-back. We return * with @ui->ui_mutex locked if we are appending pages, and unlocked * otherwise. This is an optimization (slightly hacky though). */ @@ -562,7 +560,7 @@ static int ubifs_write_end(struct file *file, struct address_space *mapping, /* * Return 0 to force VFS to repeat the whole operation, or the - * error code if 'do_readpage()' failes. + * error code if 'do_readpage()' fails. */ copied = do_readpage(page); goto out; @@ -1175,11 +1173,11 @@ static int do_truncation(struct ubifs_info *c, struct inode *inode, ui->ui_size = inode->i_size; /* Truncation changes inode [mc]time */ inode->i_mtime = inode->i_ctime = ubifs_current_time(inode); - /* The other attributes may be changed at the same time as well */ + /* Other attributes may be changed at the same time as well */ do_attr_changes(inode, attr); - err = ubifs_jnl_truncate(c, inode, old_size, new_size); mutex_unlock(&ui->ui_mutex); + out_budg: if (budgeted) ubifs_release_budget(c, &req); diff --git a/fs/ubifs/gc.c b/fs/ubifs/gc.c index f0f5f15d384e..618c2701d3a7 100644 --- a/fs/ubifs/gc.c +++ b/fs/ubifs/gc.c @@ -529,7 +529,7 @@ int ubifs_garbage_collect_leb(struct ubifs_info *c, struct ubifs_lprops *lp) * We scan the entire LEB even though we only really need to scan up to * (c->leb_size - lp->free). */ - sleb = ubifs_scan(c, lnum, 0, c->sbuf); + sleb = ubifs_scan(c, lnum, 0, c->sbuf, 0); if (IS_ERR(sleb)) return PTR_ERR(sleb); diff --git a/fs/ubifs/io.c b/fs/ubifs/io.c index 762a7d6cec73..e589fedaf1ef 100644 --- a/fs/ubifs/io.c +++ b/fs/ubifs/io.c @@ -297,7 +297,7 @@ static enum hrtimer_restart wbuf_timer_callback_nolock(struct hrtimer *timer) { struct ubifs_wbuf *wbuf = container_of(timer, struct ubifs_wbuf, timer); - dbg_io("jhead %d", wbuf->jhead); + dbg_io("jhead %s", dbg_jhead(wbuf->jhead)); wbuf->need_sync = 1; wbuf->c->need_wbuf_sync = 1; ubifs_wake_up_bgt(wbuf->c); @@ -314,7 +314,8 @@ static void new_wbuf_timer_nolock(struct ubifs_wbuf *wbuf) if (wbuf->no_timer) return; - dbg_io("set timer for jhead %d, %llu-%llu millisecs", wbuf->jhead, + dbg_io("set timer for jhead %s, %llu-%llu millisecs", + dbg_jhead(wbuf->jhead), div_u64(ktime_to_ns(wbuf->softlimit), USEC_PER_SEC), div_u64(ktime_to_ns(wbuf->softlimit) + wbuf->delta, USEC_PER_SEC)); @@ -351,8 +352,8 @@ int ubifs_wbuf_sync_nolock(struct ubifs_wbuf *wbuf) /* Write-buffer is empty or not seeked */ return 0; - dbg_io("LEB %d:%d, %d bytes, jhead %d", - wbuf->lnum, wbuf->offs, wbuf->used, wbuf->jhead); + dbg_io("LEB %d:%d, %d bytes, jhead %s", + wbuf->lnum, wbuf->offs, wbuf->used, dbg_jhead(wbuf->jhead)); ubifs_assert(!(c->vfs_sb->s_flags & MS_RDONLY)); ubifs_assert(!(wbuf->avail & 7)); ubifs_assert(wbuf->offs + c->min_io_size <= c->leb_size); @@ -401,7 +402,7 @@ int ubifs_wbuf_seek_nolock(struct ubifs_wbuf *wbuf, int lnum, int offs, { const struct ubifs_info *c = wbuf->c; - dbg_io("LEB %d:%d, jhead %d", lnum, offs, wbuf->jhead); + dbg_io("LEB %d:%d, jhead %s", lnum, offs, dbg_jhead(wbuf->jhead)); ubifs_assert(lnum >= 0 && lnum < c->leb_cnt); ubifs_assert(offs >= 0 && offs <= c->leb_size); ubifs_assert(offs % c->min_io_size == 0 && !(offs & 7)); @@ -508,9 +509,9 @@ int ubifs_wbuf_write_nolock(struct ubifs_wbuf *wbuf, void *buf, int len) struct ubifs_info *c = wbuf->c; int err, written, n, aligned_len = ALIGN(len, 8), offs; - dbg_io("%d bytes (%s) to jhead %d wbuf at LEB %d:%d", len, - dbg_ntype(((struct ubifs_ch *)buf)->node_type), wbuf->jhead, - wbuf->lnum, wbuf->offs + wbuf->used); + dbg_io("%d bytes (%s) to jhead %s wbuf at LEB %d:%d", len, + dbg_ntype(((struct ubifs_ch *)buf)->node_type), + dbg_jhead(wbuf->jhead), wbuf->lnum, wbuf->offs + wbuf->used); ubifs_assert(len > 0 && wbuf->lnum >= 0 && wbuf->lnum < c->leb_cnt); ubifs_assert(wbuf->offs >= 0 && wbuf->offs % c->min_io_size == 0); ubifs_assert(!(wbuf->offs & 7) && wbuf->offs <= c->leb_size); @@ -535,8 +536,8 @@ int ubifs_wbuf_write_nolock(struct ubifs_wbuf *wbuf, void *buf, int len) memcpy(wbuf->buf + wbuf->used, buf, len); if (aligned_len == wbuf->avail) { - dbg_io("flush jhead %d wbuf to LEB %d:%d", - wbuf->jhead, wbuf->lnum, wbuf->offs); + dbg_io("flush jhead %s wbuf to LEB %d:%d", + dbg_jhead(wbuf->jhead), wbuf->lnum, wbuf->offs); err = ubi_leb_write(c->ubi, wbuf->lnum, wbuf->buf, wbuf->offs, c->min_io_size, wbuf->dtype); @@ -564,8 +565,8 @@ int ubifs_wbuf_write_nolock(struct ubifs_wbuf *wbuf, void *buf, int len) * minimal I/O unit. We have to fill and flush write-buffer and switch * to the next min. I/O unit. */ - dbg_io("flush jhead %d wbuf to LEB %d:%d", - wbuf->jhead, wbuf->lnum, wbuf->offs); + dbg_io("flush jhead %s wbuf to LEB %d:%d", + dbg_jhead(wbuf->jhead), wbuf->lnum, wbuf->offs); memcpy(wbuf->buf + wbuf->used, buf, wbuf->avail); err = ubi_leb_write(c->ubi, wbuf->lnum, wbuf->buf, wbuf->offs, c->min_io_size, wbuf->dtype); @@ -698,8 +699,8 @@ int ubifs_read_node_wbuf(struct ubifs_wbuf *wbuf, void *buf, int type, int len, int err, rlen, overlap; struct ubifs_ch *ch = buf; - dbg_io("LEB %d:%d, %s, length %d, jhead %d", lnum, offs, - dbg_ntype(type), len, wbuf->jhead); + dbg_io("LEB %d:%d, %s, length %d, jhead %s", lnum, offs, + dbg_ntype(type), len, dbg_jhead(wbuf->jhead)); ubifs_assert(wbuf && lnum >= 0 && lnum < c->leb_cnt && offs >= 0); ubifs_assert(!(offs & 7) && offs < c->leb_size); ubifs_assert(type >= 0 && type < UBIFS_NODE_TYPES_CNT); diff --git a/fs/ubifs/journal.c b/fs/ubifs/journal.c index 64b5f3a309f5..d321baeca68d 100644 --- a/fs/ubifs/journal.c +++ b/fs/ubifs/journal.c @@ -158,7 +158,7 @@ again: * some. But the write-buffer mutex has to be unlocked because * GC also takes it. */ - dbg_jnl("no free space jhead %d, run GC", jhead); + dbg_jnl("no free space in jhead %s, run GC", dbg_jhead(jhead)); mutex_unlock(&wbuf->io_mutex); lnum = ubifs_garbage_collect(c, 0); @@ -173,7 +173,8 @@ again: * because we dropped @wbuf->io_mutex, so try once * again. */ - dbg_jnl("GC couldn't make a free LEB for jhead %d", jhead); + dbg_jnl("GC couldn't make a free LEB for jhead %s", + dbg_jhead(jhead)); if (retries++ < 2) { dbg_jnl("retry (%d)", retries); goto again; @@ -184,7 +185,7 @@ again: } mutex_lock_nested(&wbuf->io_mutex, wbuf->jhead); - dbg_jnl("got LEB %d for jhead %d", lnum, jhead); + dbg_jnl("got LEB %d for jhead %s", lnum, dbg_jhead(jhead)); avail = c->leb_size - wbuf->offs - wbuf->used; if (wbuf->lnum != -1 && avail >= len) { @@ -255,7 +256,8 @@ static int write_node(struct ubifs_info *c, int jhead, void *node, int len, *lnum = c->jheads[jhead].wbuf.lnum; *offs = c->jheads[jhead].wbuf.offs + c->jheads[jhead].wbuf.used; - dbg_jnl("jhead %d, LEB %d:%d, len %d", jhead, *lnum, *offs, len); + dbg_jnl("jhead %s, LEB %d:%d, len %d", + dbg_jhead(jhead), *lnum, *offs, len); ubifs_prepare_node(c, node, len, 0); return ubifs_wbuf_write_nolock(wbuf, node, len); @@ -285,7 +287,8 @@ static int write_head(struct ubifs_info *c, int jhead, void *buf, int len, *lnum = c->jheads[jhead].wbuf.lnum; *offs = c->jheads[jhead].wbuf.offs + c->jheads[jhead].wbuf.used; - dbg_jnl("jhead %d, LEB %d:%d, len %d", jhead, *lnum, *offs, len); + dbg_jnl("jhead %s, LEB %d:%d, len %d", + dbg_jhead(jhead), *lnum, *offs, len); err = ubifs_wbuf_write_nolock(wbuf, buf, len); if (err) diff --git a/fs/ubifs/key.h b/fs/ubifs/key.h index 5fa27ea031ba..0f530c684f0b 100644 --- a/fs/ubifs/key.h +++ b/fs/ubifs/key.h @@ -228,23 +228,6 @@ static inline void xent_key_init(const struct ubifs_info *c, key->u32[1] = hash | (UBIFS_XENT_KEY << UBIFS_S_KEY_HASH_BITS); } -/** - * xent_key_init_hash - initialize extended attribute entry key without - * re-calculating hash function. - * @c: UBIFS file-system description object - * @key: key to initialize - * @inum: host inode number - * @hash: extended attribute entry name hash - */ -static inline void xent_key_init_hash(const struct ubifs_info *c, - union ubifs_key *key, ino_t inum, - uint32_t hash) -{ - ubifs_assert(!(hash & ~UBIFS_S_KEY_HASH_MASK)); - key->u32[0] = inum; - key->u32[1] = hash | (UBIFS_XENT_KEY << UBIFS_S_KEY_HASH_BITS); -} - /** * xent_key_init_flash - initialize on-flash extended attribute entry key. * @c: UBIFS file-system description object @@ -295,22 +278,15 @@ static inline void data_key_init(const struct ubifs_info *c, } /** - * data_key_init_flash - initialize on-flash data key. + * highest_data_key - get the highest possible data key for an inode. * @c: UBIFS file-system description object - * @k: key to initialize + * @key: key to initialize * @inum: inode number - * @block: block number */ -static inline void data_key_init_flash(const struct ubifs_info *c, void *k, - ino_t inum, unsigned int block) +static inline void highest_data_key(const struct ubifs_info *c, + union ubifs_key *key, ino_t inum) { - union ubifs_key *key = k; - - ubifs_assert(!(block & ~UBIFS_S_KEY_BLOCK_MASK)); - key->j32[0] = cpu_to_le32(inum); - key->j32[1] = cpu_to_le32(block | - (UBIFS_DATA_KEY << UBIFS_S_KEY_BLOCK_BITS)); - memset(k + 8, 0, UBIFS_MAX_KEY_LEN - 8); + data_key_init(c, key, inum, UBIFS_S_KEY_BLOCK_MASK); } /** @@ -554,4 +530,5 @@ static inline unsigned long long key_max_inode_size(const struct ubifs_info *c) return 0; } } + #endif /* !__UBIFS_KEY_H__ */ diff --git a/fs/ubifs/log.c b/fs/ubifs/log.c index 56e33772a1ee..c345e125f42c 100644 --- a/fs/ubifs/log.c +++ b/fs/ubifs/log.c @@ -169,8 +169,8 @@ void ubifs_add_bud(struct ubifs_info *c, struct ubifs_bud *bud) */ c->bud_bytes += c->leb_size - bud->start; - dbg_log("LEB %d:%d, jhead %d, bud_bytes %lld", bud->lnum, - bud->start, bud->jhead, c->bud_bytes); + dbg_log("LEB %d:%d, jhead %s, bud_bytes %lld", bud->lnum, + bud->start, dbg_jhead(bud->jhead), c->bud_bytes); spin_unlock(&c->buds_lock); } @@ -355,16 +355,16 @@ static void remove_buds(struct ubifs_info *c) * heads (non-closed buds). */ c->cmt_bud_bytes += wbuf->offs - bud->start; - dbg_log("preserve %d:%d, jhead %d, bud bytes %d, " + dbg_log("preserve %d:%d, jhead %s, bud bytes %d, " "cmt_bud_bytes %lld", bud->lnum, bud->start, - bud->jhead, wbuf->offs - bud->start, + dbg_jhead(bud->jhead), wbuf->offs - bud->start, c->cmt_bud_bytes); bud->start = wbuf->offs; } else { c->cmt_bud_bytes += c->leb_size - bud->start; - dbg_log("remove %d:%d, jhead %d, bud bytes %d, " + dbg_log("remove %d:%d, jhead %s, bud bytes %d, " "cmt_bud_bytes %lld", bud->lnum, bud->start, - bud->jhead, c->leb_size - bud->start, + dbg_jhead(bud->jhead), c->leb_size - bud->start, c->cmt_bud_bytes); rb_erase(p1, &c->buds); /* @@ -429,7 +429,8 @@ int ubifs_log_start_commit(struct ubifs_info *c, int *ltail_lnum) if (lnum == -1 || offs == c->leb_size) continue; - dbg_log("add ref to LEB %d:%d for jhead %d", lnum, offs, i); + dbg_log("add ref to LEB %d:%d for jhead %s", + lnum, offs, dbg_jhead(i)); ref = buf + len; ref->ch.node_type = UBIFS_REF_NODE; ref->lnum = cpu_to_le32(lnum); @@ -695,7 +696,7 @@ int ubifs_consolidate_log(struct ubifs_info *c) lnum = c->ltail_lnum; write_lnum = lnum; while (1) { - sleb = ubifs_scan(c, lnum, 0, c->sbuf); + sleb = ubifs_scan(c, lnum, 0, c->sbuf, 0); if (IS_ERR(sleb)) { err = PTR_ERR(sleb); goto out_free; diff --git a/fs/ubifs/lprops.c b/fs/ubifs/lprops.c index 4cdd284dea56..4d4ca388889b 100644 --- a/fs/ubifs/lprops.c +++ b/fs/ubifs/lprops.c @@ -281,7 +281,7 @@ void ubifs_add_to_cat(struct ubifs_info *c, struct ubifs_lprops *lprops, case LPROPS_FREE: if (add_to_lpt_heap(c, lprops, cat)) break; - /* No more room on heap so make it uncategorized */ + /* No more room on heap so make it un-categorized */ cat = LPROPS_UNCAT; /* Fall through */ case LPROPS_UNCAT: @@ -375,8 +375,8 @@ void ubifs_replace_cat(struct ubifs_info *c, struct ubifs_lprops *old_lprops, * @lprops: LEB properties * * A LEB may have fallen off of the bottom of a heap, and ended up as - * uncategorized even though it has enough space for us now. If that is the case - * this function will put the LEB back onto a heap. + * un-categorized even though it has enough space for us now. If that is the + * case this function will put the LEB back onto a heap. */ void ubifs_ensure_cat(struct ubifs_info *c, struct ubifs_lprops *lprops) { @@ -436,10 +436,10 @@ int ubifs_categorize_lprops(const struct ubifs_info *c, /** * change_category - change LEB properties category. * @c: UBIFS file-system description object - * @lprops: LEB properties to recategorize + * @lprops: LEB properties to re-categorize * * LEB properties are categorized to enable fast find operations. When the LEB - * properties change they must be recategorized. + * properties change they must be re-categorized. */ static void change_category(struct ubifs_info *c, struct ubifs_lprops *lprops) { @@ -461,21 +461,18 @@ static void change_category(struct ubifs_info *c, struct ubifs_lprops *lprops) } /** - * calc_dark - calculate LEB dark space size. + * ubifs_calc_dark - calculate LEB dark space size. * @c: the UBIFS file-system description object * @spc: amount of free and dirty space in the LEB * - * This function calculates amount of dark space in an LEB which has @spc bytes - * of free and dirty space. Returns the calculations result. + * This function calculates and returns amount of dark space in an LEB which + * has @spc bytes of free and dirty space. * - * Dark space is the space which is not always usable - it depends on which - * nodes are written in which order. E.g., if an LEB has only 512 free bytes, - * it is dark space, because it cannot fit a large data node. So UBIFS cannot - * count on this LEB and treat these 512 bytes as usable because it is not true - * if, for example, only big chunks of uncompressible data will be written to - * the FS. + * UBIFS is trying to account the space which might not be usable, and this + * space is called "dark space". For example, if an LEB has only %512 free + * bytes, it is dark space, because it cannot fit a large data node. */ -static int calc_dark(struct ubifs_info *c, int spc) +int ubifs_calc_dark(const struct ubifs_info *c, int spc) { ubifs_assert(!(spc & 7)); @@ -518,7 +515,7 @@ static int is_lprops_dirty(struct ubifs_info *c, struct ubifs_lprops *lprops) * @free: new free space amount * @dirty: new dirty space amount * @flags: new flags - * @idx_gc_cnt: change to the count of idx_gc list + * @idx_gc_cnt: change to the count of @idx_gc list * * This function changes LEB properties (@free, @dirty or @flag). However, the * property which has the %LPROPS_NC value is not changed. Returns a pointer to @@ -535,7 +532,7 @@ const struct ubifs_lprops *ubifs_change_lp(struct ubifs_info *c, { /* * This is the only function that is allowed to change lprops, so we - * discard the const qualifier. + * discard the "const" qualifier. */ struct ubifs_lprops *lprops = (struct ubifs_lprops *)lp; @@ -575,7 +572,7 @@ const struct ubifs_lprops *ubifs_change_lp(struct ubifs_info *c, if (old_spc < c->dead_wm) c->lst.total_dead -= old_spc; else - c->lst.total_dark -= calc_dark(c, old_spc); + c->lst.total_dark -= ubifs_calc_dark(c, old_spc); c->lst.total_used -= c->leb_size - old_spc; } @@ -616,7 +613,7 @@ const struct ubifs_lprops *ubifs_change_lp(struct ubifs_info *c, if (new_spc < c->dead_wm) c->lst.total_dead += new_spc; else - c->lst.total_dark += calc_dark(c, new_spc); + c->lst.total_dark += ubifs_calc_dark(c, new_spc); c->lst.total_used += c->leb_size - new_spc; } @@ -1096,7 +1093,7 @@ static int scan_check_cb(struct ubifs_info *c, } } - sleb = ubifs_scan(c, lnum, 0, c->dbg->buf); + sleb = ubifs_scan(c, lnum, 0, c->dbg->buf, 0); if (IS_ERR(sleb)) { /* * After an unclean unmount, empty and freeable LEBs @@ -1107,7 +1104,7 @@ static int scan_check_cb(struct ubifs_info *c, "- continuing checking"); lst->empty_lebs += 1; lst->total_free += c->leb_size; - lst->total_dark += calc_dark(c, c->leb_size); + lst->total_dark += ubifs_calc_dark(c, c->leb_size); return LPT_SCAN_CONTINUE; } @@ -1117,7 +1114,7 @@ static int scan_check_cb(struct ubifs_info *c, "- continuing checking"); lst->total_free += lp->free; lst->total_dirty += lp->dirty; - lst->total_dark += calc_dark(c, c->leb_size); + lst->total_dark += ubifs_calc_dark(c, c->leb_size); return LPT_SCAN_CONTINUE; } data->err = PTR_ERR(sleb); @@ -1235,7 +1232,7 @@ static int scan_check_cb(struct ubifs_info *c, if (spc < c->dead_wm) lst->total_dead += spc; else - lst->total_dark += calc_dark(c, spc); + lst->total_dark += ubifs_calc_dark(c, spc); } ubifs_scan_destroy(sleb); diff --git a/fs/ubifs/master.c b/fs/ubifs/master.c index a88f33801b98..28beaeedadc0 100644 --- a/fs/ubifs/master.c +++ b/fs/ubifs/master.c @@ -29,7 +29,8 @@ * @c: UBIFS file-system description object * * This function scans the master node LEBs and search for the latest master - * node. Returns zero in case of success and a negative error code in case of + * node. Returns zero in case of success, %-EUCLEAN if there master area is + * corrupted and requires recovery, and a negative error code in case of * failure. */ static int scan_for_master(struct ubifs_info *c) @@ -40,7 +41,7 @@ static int scan_for_master(struct ubifs_info *c) lnum = UBIFS_MST_LNUM; - sleb = ubifs_scan(c, lnum, 0, c->sbuf); + sleb = ubifs_scan(c, lnum, 0, c->sbuf, 1); if (IS_ERR(sleb)) return PTR_ERR(sleb); nodes_cnt = sleb->nodes_cnt; @@ -48,7 +49,7 @@ static int scan_for_master(struct ubifs_info *c) snod = list_entry(sleb->nodes.prev, struct ubifs_scan_node, list); if (snod->type != UBIFS_MST_NODE) - goto out; + goto out_dump; memcpy(c->mst_node, snod->node, snod->len); offs = snod->offs; } @@ -56,7 +57,7 @@ static int scan_for_master(struct ubifs_info *c) lnum += 1; - sleb = ubifs_scan(c, lnum, 0, c->sbuf); + sleb = ubifs_scan(c, lnum, 0, c->sbuf, 1); if (IS_ERR(sleb)) return PTR_ERR(sleb); if (sleb->nodes_cnt != nodes_cnt) @@ -65,7 +66,7 @@ static int scan_for_master(struct ubifs_info *c) goto out; snod = list_entry(sleb->nodes.prev, struct ubifs_scan_node, list); if (snod->type != UBIFS_MST_NODE) - goto out; + goto out_dump; if (snod->offs != offs) goto out; if (memcmp((void *)c->mst_node + UBIFS_CH_SZ, @@ -78,6 +79,12 @@ static int scan_for_master(struct ubifs_info *c) out: ubifs_scan_destroy(sleb); + return -EUCLEAN; + +out_dump: + ubifs_err("unexpected node type %d master LEB %d:%d", + snod->type, lnum, snod->offs); + ubifs_scan_destroy(sleb); return -EINVAL; } @@ -256,7 +263,8 @@ int ubifs_read_master(struct ubifs_info *c) err = scan_for_master(c); if (err) { - err = ubifs_recover_master_node(c); + if (err == -EUCLEAN) + err = ubifs_recover_master_node(c); if (err) /* * Note, we do not free 'c->mst_node' here because the diff --git a/fs/ubifs/orphan.c b/fs/ubifs/orphan.c index 152a7b34a141..82009c74b6a3 100644 --- a/fs/ubifs/orphan.c +++ b/fs/ubifs/orphan.c @@ -670,9 +670,10 @@ static int kill_orphans(struct ubifs_info *c) struct ubifs_scan_leb *sleb; dbg_rcvry("LEB %d", lnum); - sleb = ubifs_scan(c, lnum, 0, c->sbuf); + sleb = ubifs_scan(c, lnum, 0, c->sbuf, 1); if (IS_ERR(sleb)) { - sleb = ubifs_recover_leb(c, lnum, 0, c->sbuf, 0); + if (PTR_ERR(sleb) == -EUCLEAN) + sleb = ubifs_recover_leb(c, lnum, 0, c->sbuf, 0); if (IS_ERR(sleb)) { err = PTR_ERR(sleb); break; @@ -899,7 +900,7 @@ static int dbg_scan_orphans(struct ubifs_info *c, struct check_info *ci) for (lnum = c->orph_first; lnum <= c->orph_last; lnum++) { struct ubifs_scan_leb *sleb; - sleb = ubifs_scan(c, lnum, 0, c->dbg->buf); + sleb = ubifs_scan(c, lnum, 0, c->dbg->buf, 0); if (IS_ERR(sleb)) { err = PTR_ERR(sleb); break; diff --git a/fs/ubifs/recovery.c b/fs/ubifs/recovery.c index e5f6cf8a1155..f94ddf7efba0 100644 --- a/fs/ubifs/recovery.c +++ b/fs/ubifs/recovery.c @@ -286,7 +286,7 @@ int ubifs_recover_master_node(struct ubifs_info *c) mst = mst2; } - dbg_rcvry("recovered master node from LEB %d", + ubifs_msg("recovered master node from LEB %d", (mst == mst1 ? UBIFS_MST_LNUM : UBIFS_MST_LNUM + 1)); memcpy(c->mst_node, mst, UBIFS_MST_NODE_SZ); @@ -790,7 +790,7 @@ struct ubifs_scan_leb *ubifs_recover_log_leb(struct ubifs_info *c, int lnum, * We can only recover at the end of the log, so check that the * next log LEB is empty or out of date. */ - sleb = ubifs_scan(c, next_lnum, 0, sbuf); + sleb = ubifs_scan(c, next_lnum, 0, sbuf, 0); if (IS_ERR(sleb)) return sleb; if (sleb->nodes_cnt) { diff --git a/fs/ubifs/replay.c b/fs/ubifs/replay.c index 2970500f32df..5c2d6d759a3e 100644 --- a/fs/ubifs/replay.c +++ b/fs/ubifs/replay.c @@ -506,7 +506,7 @@ static int replay_bud(struct ubifs_info *c, int lnum, int offs, int jhead, if (c->need_recovery) sleb = ubifs_recover_leb(c, lnum, offs, c->sbuf, jhead != GCHD); else - sleb = ubifs_scan(c, lnum, offs, c->sbuf); + sleb = ubifs_scan(c, lnum, offs, c->sbuf, 0); if (IS_ERR(sleb)) return PTR_ERR(sleb); @@ -836,8 +836,8 @@ static int replay_log_leb(struct ubifs_info *c, int lnum, int offs, void *sbuf) const struct ubifs_cs_node *node; dbg_mnt("replay log LEB %d:%d", lnum, offs); - sleb = ubifs_scan(c, lnum, offs, sbuf); - if (IS_ERR(sleb) ) { + sleb = ubifs_scan(c, lnum, offs, sbuf, c->need_recovery); + if (IS_ERR(sleb)) { if (PTR_ERR(sleb) != -EUCLEAN || !c->need_recovery) return PTR_ERR(sleb); sleb = ubifs_recover_log_leb(c, lnum, offs, sbuf); diff --git a/fs/ubifs/scan.c b/fs/ubifs/scan.c index 892ebfee4fe5..96c525384191 100644 --- a/fs/ubifs/scan.c +++ b/fs/ubifs/scan.c @@ -108,10 +108,9 @@ int ubifs_scan_a_node(const struct ubifs_info *c, void *buf, int len, int lnum, /* Make the node pads to 8-byte boundary */ if ((node_len + pad_len) & 7) { - if (!quiet) { + if (!quiet) dbg_err("bad padding length %d - %d", offs, offs + node_len + pad_len); - } return SCANNED_A_BAD_PAD_NODE; } @@ -253,15 +252,19 @@ void ubifs_scanned_corruption(const struct ubifs_info *c, int lnum, int offs, * @c: UBIFS file-system description object * @lnum: logical eraseblock number * @offs: offset to start at (usually zero) - * @sbuf: scan buffer (must be c->leb_size) + * @sbuf: scan buffer (must be of @c->leb_size bytes in size) + * @quiet: print no messages * * This function scans LEB number @lnum and returns complete information about * its contents. Returns the scaned information in case of success and, * %-EUCLEAN if the LEB neads recovery, and other negative error codes in case * of failure. + * + * If @quiet is non-zero, this function does not print large and scary + * error messages and flash dumps in case of errors. */ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum, - int offs, void *sbuf) + int offs, void *sbuf, int quiet) { void *buf = sbuf + offs; int err, len = c->leb_size - offs; @@ -280,7 +283,7 @@ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum, cond_resched(); - ret = ubifs_scan_a_node(c, buf, len, lnum, offs, 0); + ret = ubifs_scan_a_node(c, buf, len, lnum, offs, quiet); if (ret > 0) { /* Padding bytes or a valid padding node */ offs += ret; @@ -320,7 +323,9 @@ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum, } if (offs % c->min_io_size) { - ubifs_err("empty space starts at non-aligned offset %d", offs); + if (!quiet) + ubifs_err("empty space starts at non-aligned offset %d", + offs); goto corrupted;; } @@ -331,18 +336,25 @@ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum, break; for (; len; offs++, buf++, len--) if (*(uint8_t *)buf != 0xff) { - ubifs_err("corrupt empty space at LEB %d:%d", - lnum, offs); + if (!quiet) + ubifs_err("corrupt empty space at LEB %d:%d", + lnum, offs); goto corrupted; } return sleb; corrupted: - ubifs_scanned_corruption(c, lnum, offs, buf); + if (!quiet) { + ubifs_scanned_corruption(c, lnum, offs, buf); + ubifs_err("LEB %d scanning failed", lnum); + } err = -EUCLEAN; + ubifs_scan_destroy(sleb); + return ERR_PTR(err); + error: - ubifs_err("LEB %d scanning failed", lnum); + ubifs_err("LEB %d scanning failed, error %d", lnum, err); ubifs_scan_destroy(sleb); return ERR_PTR(err); } diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index c4af069df1ad..333e181ee987 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -36,7 +36,6 @@ #include #include #include -#include #include "ubifs.h" /* @@ -318,6 +317,8 @@ static int ubifs_write_inode(struct inode *inode, int wait) if (err) ubifs_err("can't write inode %lu, error %d", inode->i_ino, err); + else + err = dbg_check_inode_size(c, inode, ui->ui_size); } ui->dirty = 0; @@ -447,17 +448,6 @@ static int ubifs_sync_fs(struct super_block *sb, int wait) if (!wait) return 0; - /* - * VFS calls '->sync_fs()' before synchronizing all dirty inodes and - * pages, so synchronize them first, then commit the journal. Strictly - * speaking, it is not necessary to commit the journal here, - * synchronizing write-buffers would be enough. But committing makes - * UBIFS free space predictions much more accurate, so we want to let - * the user be able to get more accurate results of 'statfs()' after - * they synchronize the file system. - */ - sync_inodes_sb(sb); - /* * Synchronize write buffers, because 'ubifs_run_commit()' does not * do this if it waits for an already running commit. @@ -468,6 +458,13 @@ static int ubifs_sync_fs(struct super_block *sb, int wait) return err; } + /* + * Strictly speaking, it is not necessary to commit the journal here, + * synchronizing write-buffers would be enough. But committing makes + * UBIFS free space predictions much more accurate, so we want to let + * the user be able to get more accurate results of 'statfs()' after + * they synchronize the file system. + */ err = ubifs_run_commit(c); if (err) return err; @@ -1720,8 +1717,6 @@ static void ubifs_put_super(struct super_block *sb) ubifs_msg("un-mount UBI device %d, volume %d", c->vi.ubi_num, c->vi.vol_id); - lock_kernel(); - /* * The following asserts are only valid if there has not been a failure * of the media. For example, there will be dirty inodes if we failed @@ -1786,8 +1781,6 @@ static void ubifs_put_super(struct super_block *sb) ubi_close_volume(c->ubi); mutex_unlock(&c->umount_mutex); kfree(c); - - unlock_kernel(); } static int ubifs_remount_fs(struct super_block *sb, int *flags, char *data) @@ -1803,22 +1796,17 @@ static int ubifs_remount_fs(struct super_block *sb, int *flags, char *data) return err; } - lock_kernel(); if ((sb->s_flags & MS_RDONLY) && !(*flags & MS_RDONLY)) { if (c->ro_media) { ubifs_msg("cannot re-mount due to prior errors"); - unlock_kernel(); return -EROFS; } err = ubifs_remount_rw(c); - if (err) { - unlock_kernel(); + if (err) return err; - } } else if (!(sb->s_flags & MS_RDONLY) && (*flags & MS_RDONLY)) { if (c->ro_media) { ubifs_msg("cannot re-mount due to prior errors"); - unlock_kernel(); return -EROFS; } ubifs_remount_ro(c); @@ -1833,7 +1821,6 @@ static int ubifs_remount_fs(struct super_block *sb, int *flags, char *data) } ubifs_assert(c->lst.taken_empty_lebs > 0); - unlock_kernel(); return 0; } diff --git a/fs/ubifs/tnc.c b/fs/ubifs/tnc.c index f249f7b0d656..e5b1a7d00fa0 100644 --- a/fs/ubifs/tnc.c +++ b/fs/ubifs/tnc.c @@ -1159,8 +1159,8 @@ static struct ubifs_znode *dirty_cow_bottom_up(struct ubifs_info *c, * o exact match, i.e. the found zero-level znode contains key @key, then %1 * is returned and slot number of the matched branch is stored in @n; * o not exact match, which means that zero-level znode does not contain - * @key, then %0 is returned and slot number of the closed branch is stored - * in @n; + * @key, then %0 is returned and slot number of the closest branch is stored + * in @n; * o @key is so small that it is even less than the lowest key of the * leftmost zero-level node, then %0 is returned and %0 is stored in @n. * @@ -1433,7 +1433,7 @@ static int maybe_leb_gced(struct ubifs_info *c, int lnum, int gc_seq1) * @lnum: LEB number is returned here * @offs: offset is returned here * - * This function look up and reads node with key @key. The caller has to make + * This function looks up and reads node with key @key. The caller has to make * sure the @node buffer is large enough to fit the node. Returns zero in case * of success, %-ENOENT if the node was not found, and a negative error code in * case of failure. The node location can be returned in @lnum and @offs. @@ -3268,3 +3268,73 @@ out_unlock: mutex_unlock(&c->tnc_mutex); return err; } + +#ifdef CONFIG_UBIFS_FS_DEBUG + +/** + * dbg_check_inode_size - check if inode size is correct. + * @c: UBIFS file-system description object + * @inum: inode number + * @size: inode size + * + * This function makes sure that the inode size (@size) is correct and it does + * not have any pages beyond @size. Returns zero if the inode is OK, %-EINVAL + * if it has a data page beyond @size, and other negative error code in case of + * other errors. + */ +int dbg_check_inode_size(struct ubifs_info *c, const struct inode *inode, + loff_t size) +{ + int err, n; + union ubifs_key from_key, to_key, *key; + struct ubifs_znode *znode; + unsigned int block; + + if (!S_ISREG(inode->i_mode)) + return 0; + if (!(ubifs_chk_flags & UBIFS_CHK_GEN)) + return 0; + + block = (size + UBIFS_BLOCK_SIZE - 1) >> UBIFS_BLOCK_SHIFT; + data_key_init(c, &from_key, inode->i_ino, block); + highest_data_key(c, &to_key, inode->i_ino); + + mutex_lock(&c->tnc_mutex); + err = ubifs_lookup_level0(c, &from_key, &znode, &n); + if (err < 0) + goto out_unlock; + + if (err) { + err = -EINVAL; + key = &from_key; + goto out_dump; + } + + err = tnc_next(c, &znode, &n); + if (err == -ENOENT) { + err = 0; + goto out_unlock; + } + if (err < 0) + goto out_unlock; + + ubifs_assert(err == 0); + key = &znode->zbranch[n].key; + if (!key_in_range(c, key, &from_key, &to_key)) + goto out_unlock; + +out_dump: + block = key_block(c, key); + ubifs_err("inode %lu has size %lld, but there are data at offset %lld " + "(data key %s)", (unsigned long)inode->i_ino, size, + ((loff_t)block) << UBIFS_BLOCK_SHIFT, DBGKEY(key)); + dbg_dump_inode(c, inode); + dbg_dump_stack(); + err = -EINVAL; + +out_unlock: + mutex_unlock(&c->tnc_mutex); + return err; +} + +#endif /* CONFIG_UBIFS_FS_DEBUG */ diff --git a/fs/ubifs/tnc_commit.c b/fs/ubifs/tnc_commit.c index fde8d127c768..53288e5d604e 100644 --- a/fs/ubifs/tnc_commit.c +++ b/fs/ubifs/tnc_commit.c @@ -245,7 +245,7 @@ static int layout_leb_in_gaps(struct ubifs_info *c, int *p) * it is more comprehensive and less efficient than is needed for this * purpose. */ - sleb = ubifs_scan(c, lnum, 0, c->ileb_buf); + sleb = ubifs_scan(c, lnum, 0, c->ileb_buf, 0); c->ileb_len = 0; if (IS_ERR(sleb)) return PTR_ERR(sleb); diff --git a/fs/ubifs/ubifs-media.h b/fs/ubifs/ubifs-media.h index 3eee07e0c495..191ca7863fe7 100644 --- a/fs/ubifs/ubifs-media.h +++ b/fs/ubifs/ubifs-media.h @@ -135,6 +135,13 @@ /* The key is always at the same position in all keyed nodes */ #define UBIFS_KEY_OFFSET offsetof(struct ubifs_ino_node, key) +/* Garbage collector journal head number */ +#define UBIFS_GC_HEAD 0 +/* Base journal head number */ +#define UBIFS_BASE_HEAD 1 +/* Data journal head number */ +#define UBIFS_DATA_HEAD 2 + /* * LEB Properties Tree node types. * diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h index a29349094422..b2d976366a46 100644 --- a/fs/ubifs/ubifs.h +++ b/fs/ubifs/ubifs.h @@ -105,12 +105,10 @@ /* Number of non-data journal heads */ #define NONDATA_JHEADS_CNT 2 -/* Garbage collector head */ -#define GCHD 0 -/* Base journal head number */ -#define BASEHD 1 -/* First "general purpose" journal head */ -#define DATAHD 2 +/* Shorter names for journal head numbers for internal usage */ +#define GCHD UBIFS_GC_HEAD +#define BASEHD UBIFS_BASE_HEAD +#define DATAHD UBIFS_DATA_HEAD /* 'No change' value for 'ubifs_change_lp()' */ #define LPROPS_NC 0x80000001 @@ -1451,7 +1449,7 @@ int ubifs_sync_wbufs_by_inode(struct ubifs_info *c, struct inode *inode); /* scan.c */ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum, - int offs, void *sbuf); + int offs, void *sbuf, int quiet); void ubifs_scan_destroy(struct ubifs_scan_leb *sleb); int ubifs_scan_a_node(const struct ubifs_info *c, void *buf, int len, int lnum, int offs, int quiet); @@ -1676,6 +1674,7 @@ const struct ubifs_lprops *ubifs_fast_find_free(struct ubifs_info *c); const struct ubifs_lprops *ubifs_fast_find_empty(struct ubifs_info *c); const struct ubifs_lprops *ubifs_fast_find_freeable(struct ubifs_info *c); const struct ubifs_lprops *ubifs_fast_find_frdi_idx(struct ubifs_info *c); +int ubifs_calc_dark(const struct ubifs_info *c, int spc); /* file.c */ int ubifs_fsync(struct file *file, struct dentry *dentry, int datasync); diff --git a/fs/ubifs/xattr.c b/fs/ubifs/xattr.c index adafcf556531..7998cc378250 100644 --- a/fs/ubifs/xattr.c +++ b/fs/ubifs/xattr.c @@ -78,9 +78,9 @@ enum { SECURITY_XATTR, }; -static struct inode_operations none_inode_operations; +static const struct inode_operations none_inode_operations; static struct address_space_operations none_address_operations; -static struct file_operations none_file_operations; +static const struct file_operations none_file_operations; /** * create_xattr - create an extended attribute. diff --git a/include/drm/drmP.h b/include/drm/drmP.h index 45b67d9c39c1..c8e64bbadbcf 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -88,7 +88,37 @@ struct drm_device; #define DRM_UT_CORE 0x01 #define DRM_UT_DRIVER 0x02 #define DRM_UT_KMS 0x04 -#define DRM_UT_MODE 0x08 +/* + * Three debug levels are defined. + * drm_core, drm_driver, drm_kms + * drm_core level can be used in the generic drm code. For example: + * drm_ioctl, drm_mm, drm_memory + * The macro definiton of DRM_DEBUG is used. + * DRM_DEBUG(fmt, args...) + * The debug info by using the DRM_DEBUG can be obtained by adding + * the boot option of "drm.debug=1". + * + * drm_driver level can be used in the specific drm driver. It is used + * to add the debug info related with the drm driver. For example: + * i915_drv, i915_dma, i915_gem, radeon_drv, + * The macro definition of DRM_DEBUG_DRIVER can be used. + * DRM_DEBUG_DRIVER(fmt, args...) + * The debug info by using the DRM_DEBUG_DRIVER can be obtained by + * adding the boot option of "drm.debug=0x02" + * + * drm_kms level can be used in the KMS code related with specific drm driver. + * It is used to add the debug info related with KMS mode. For example: + * the connector/crtc , + * The macro definition of DRM_DEBUG_KMS can be used. + * DRM_DEBUG_KMS(fmt, args...) + * The debug info by using the DRM_DEBUG_KMS can be obtained by + * adding the boot option of "drm.debug=0x04" + * + * If we add the boot option of "drm.debug=0x06", we can get the debug info by + * using the DRM_DEBUG_KMS and DRM_DEBUG_DRIVER. + * If we add the boot option of "drm.debug=0x05", we can get the debug info by + * using the DRM_DEBUG_KMS and DRM_DEBUG. + */ extern void drm_ut_debug_printk(unsigned int request_level, const char *prefix, @@ -174,19 +204,14 @@ extern void drm_ut_debug_printk(unsigned int request_level, __func__, fmt, ##args); \ } while (0) -#define DRM_DEBUG_DRIVER(prefix, fmt, args...) \ +#define DRM_DEBUG_DRIVER(fmt, args...) \ do { \ - drm_ut_debug_printk(DRM_UT_DRIVER, prefix, \ + drm_ut_debug_printk(DRM_UT_DRIVER, DRM_NAME, \ __func__, fmt, ##args); \ } while (0) -#define DRM_DEBUG_KMS(prefix, fmt, args...) \ +#define DRM_DEBUG_KMS(fmt, args...) \ do { \ - drm_ut_debug_printk(DRM_UT_KMS, prefix, \ - __func__, fmt, ##args); \ - } while (0) -#define DRM_DEBUG_MODE(prefix, fmt, args...) \ - do { \ - drm_ut_debug_printk(DRM_UT_MODE, prefix, \ + drm_ut_debug_printk(DRM_UT_KMS, DRM_NAME, \ __func__, fmt, ##args); \ } while (0) #define DRM_LOG(fmt, args...) \ @@ -210,9 +235,8 @@ extern void drm_ut_debug_printk(unsigned int request_level, NULL, fmt, ##args); \ } while (0) #else -#define DRM_DEBUG_DRIVER(prefix, fmt, args...) do { } while (0) -#define DRM_DEBUG_KMS(prefix, fmt, args...) do { } while (0) -#define DRM_DEBUG_MODE(prefix, fmt, args...) do { } while (0) +#define DRM_DEBUG_DRIVER(fmt, args...) do { } while (0) +#define DRM_DEBUG_KMS(fmt, args...) do { } while (0) #define DRM_DEBUG(fmt, arg...) do { } while (0) #define DRM_LOG(fmt, arg...) do { } while (0) #define DRM_LOG_KMS(fmt, args...) do { } while (0) @@ -786,6 +810,9 @@ struct drm_driver { int (*gem_init_object) (struct drm_gem_object *obj); void (*gem_free_object) (struct drm_gem_object *obj); + /* vga arb irq handler */ + void (*vgaarb_irq)(struct drm_device *dev, bool state); + /* Driver private ops for this object */ struct vm_operations_struct *gem_vm_ops; @@ -1417,7 +1444,7 @@ drm_gem_object_unreference(struct drm_gem_object *obj) int drm_gem_handle_create(struct drm_file *file_priv, struct drm_gem_object *obj, - int *handlep); + u32 *handlep); static inline void drm_gem_object_handle_reference(struct drm_gem_object *obj) @@ -1443,7 +1470,7 @@ drm_gem_object_handle_unreference(struct drm_gem_object *obj) struct drm_gem_object *drm_gem_object_lookup(struct drm_device *dev, struct drm_file *filp, - int handle); + u32 handle); int drm_gem_close_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); int drm_gem_flink_ioctl(struct drm_device *dev, void *data, diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h new file mode 100644 index 000000000000..7bfb063029d8 --- /dev/null +++ b/include/drm/drm_cache.h @@ -0,0 +1,38 @@ +/************************************************************************** + * + * Copyright 2009 Red Hat Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * + **************************************************************************/ +/* + * Authors: + * Dave Airlie + */ + +#ifndef _DRM_CACHE_H_ +#define _DRM_CACHE_H_ + +void drm_clflush_pages(struct page *pages[], unsigned long num_pages); + +#endif diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 7300fb866767..ae1e9e166959 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -259,6 +259,8 @@ struct drm_framebuffer { void *fbdev; u32 pseudo_palette[17]; struct list_head filp_head; + /* if you are using the helper */ + void *helper_private; }; struct drm_property_blob { @@ -572,6 +574,12 @@ struct drm_mode_config { struct drm_property *tv_right_margin_property; struct drm_property *tv_top_margin_property; struct drm_property *tv_bottom_margin_property; + struct drm_property *tv_brightness_property; + struct drm_property *tv_contrast_property; + struct drm_property *tv_flicker_reduction_property; + struct drm_property *tv_overscan_property; + struct drm_property *tv_saturation_property; + struct drm_property *tv_hue_property; /* Optional properties */ struct drm_property *scaling_mode_property; @@ -736,4 +744,12 @@ extern int drm_mode_gamma_get_ioctl(struct drm_device *dev, extern int drm_mode_gamma_set_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); extern bool drm_detect_hdmi_monitor(struct edid *edid); +extern struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, + int hdisplay, int vdisplay, int vrefresh, + bool reduced, bool interlaced); +extern struct drm_display_mode *drm_gtf_mode(struct drm_device *dev, + int hdisplay, int vdisplay, int vrefresh, + bool interlaced, int margins); +extern int drm_add_modes_noedid(struct drm_connector *connector, + int hdisplay, int vdisplay); #endif /* __DRM_CRTC_H__ */ diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h index 6769ff6c1bc0..4c8dacaf4f58 100644 --- a/include/drm/drm_crtc_helper.h +++ b/include/drm/drm_crtc_helper.h @@ -79,6 +79,8 @@ struct drm_encoder_helper_funcs { /* detect for DAC style encoders */ enum drm_connector_status (*detect)(struct drm_encoder *encoder, struct drm_connector *connector); + /* disable encoder when not in use - more explicit than dpms off */ + void (*disable)(struct drm_encoder *encoder); }; struct drm_connector_helper_funcs { @@ -98,6 +100,7 @@ extern bool drm_crtc_helper_set_mode(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb); extern bool drm_helper_crtc_in_use(struct drm_crtc *crtc); +extern bool drm_helper_encoder_in_use(struct drm_encoder *encoder); extern void drm_helper_connector_dpms(struct drm_connector *connector, int mode); diff --git a/include/drm/drm_encoder_slave.h b/include/drm/drm_encoder_slave.h new file mode 100644 index 000000000000..2f65633d28a7 --- /dev/null +++ b/include/drm/drm_encoder_slave.h @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2009 Francisco Jerez. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __DRM_ENCODER_SLAVE_H__ +#define __DRM_ENCODER_SLAVE_H__ + +#include "drmP.h" +#include "drm_crtc.h" + +/** + * struct drm_encoder_slave_funcs - Entry points exposed by a slave encoder driver + * @set_config: Initialize any encoder-specific modesetting parameters. + * The meaning of the @params parameter is implementation + * dependent. It will usually be a structure with DVO port + * data format settings or timings. It's not required for + * the new parameters to take effect until the next mode + * is set. + * + * Most of its members are analogous to the function pointers in + * &drm_encoder_helper_funcs and they can optionally be used to + * initialize the latter. Connector-like methods (e.g. @get_modes and + * @set_property) will typically be wrapped around and only be called + * if the encoder is the currently selected one for the connector. + */ +struct drm_encoder_slave_funcs { + void (*set_config)(struct drm_encoder *encoder, + void *params); + + void (*destroy)(struct drm_encoder *encoder); + void (*dpms)(struct drm_encoder *encoder, int mode); + void (*save)(struct drm_encoder *encoder); + void (*restore)(struct drm_encoder *encoder); + bool (*mode_fixup)(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode); + int (*mode_valid)(struct drm_encoder *encoder, + struct drm_display_mode *mode); + void (*mode_set)(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode); + + enum drm_connector_status (*detect)(struct drm_encoder *encoder, + struct drm_connector *connector); + int (*get_modes)(struct drm_encoder *encoder, + struct drm_connector *connector); + int (*create_resources)(struct drm_encoder *encoder, + struct drm_connector *connector); + int (*set_property)(struct drm_encoder *encoder, + struct drm_connector *connector, + struct drm_property *property, + uint64_t val); + +}; + +/** + * struct drm_encoder_slave - Slave encoder struct + * @base: DRM encoder object. + * @slave_funcs: Slave encoder callbacks. + * @slave_priv: Slave encoder private data. + * @bus_priv: Bus specific data. + * + * A &drm_encoder_slave has two sets of callbacks, @slave_funcs and the + * ones in @base. The former are never actually called by the common + * CRTC code, it's just a convenience for splitting the encoder + * functions in an upper, GPU-specific layer and a (hopefully) + * GPU-agnostic lower layer: It's the GPU driver responsibility to + * call the slave methods when appropriate. + * + * drm_i2c_encoder_init() provides a way to get an implementation of + * this. + */ +struct drm_encoder_slave { + struct drm_encoder base; + + struct drm_encoder_slave_funcs *slave_funcs; + void *slave_priv; + void *bus_priv; +}; +#define to_encoder_slave(x) container_of((x), struct drm_encoder_slave, base) + +int drm_i2c_encoder_init(struct drm_device *dev, + struct drm_encoder_slave *encoder, + struct i2c_adapter *adap, + const struct i2c_board_info *info); + + +/** + * struct drm_i2c_encoder_driver + * + * Describes a device driver for an encoder connected to the GPU + * through an I2C bus. In addition to the entry points in @i2c_driver + * an @encoder_init function should be provided. It will be called to + * give the driver an opportunity to allocate any per-encoder data + * structures and to initialize the @slave_funcs and (optionally) + * @slave_priv members of @encoder. + */ +struct drm_i2c_encoder_driver { + struct i2c_driver i2c_driver; + + int (*encoder_init)(struct i2c_client *client, + struct drm_device *dev, + struct drm_encoder_slave *encoder); + +}; +#define to_drm_i2c_encoder_driver(x) container_of((x), \ + struct drm_i2c_encoder_driver, \ + i2c_driver) + +/** + * drm_i2c_encoder_get_client - Get the I2C client corresponding to an encoder + */ +static inline struct i2c_client *drm_i2c_encoder_get_client(struct drm_encoder *encoder) +{ + return (struct i2c_client *)to_encoder_slave(encoder)->bus_priv; +} + +/** + * drm_i2c_encoder_register - Register an I2C encoder driver + * @owner: Module containing the driver. + * @driver: Driver to be registered. + */ +static inline int drm_i2c_encoder_register(struct module *owner, + struct drm_i2c_encoder_driver *driver) +{ + return i2c_register_driver(owner, &driver->i2c_driver); +} + +/** + * drm_i2c_encoder_unregister - Unregister an I2C encoder driver + * @driver: Driver to be unregistered. + */ +static inline void drm_i2c_encoder_unregister(struct drm_i2c_encoder_driver *driver) +{ + i2c_del_driver(&driver->i2c_driver); +} + +void drm_i2c_encoder_destroy(struct drm_encoder *encoder); + +#endif diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h new file mode 100644 index 000000000000..88fffbdfa26f --- /dev/null +++ b/include/drm/drm_fb_helper.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2006-2009 Red Hat Inc. + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * + * DRM framebuffer helper functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Dave Airlie + * Jesse Barnes + */ +#ifndef DRM_FB_HELPER_H +#define DRM_FB_HELPER_H + +struct drm_fb_helper_crtc { + uint32_t crtc_id; + struct drm_mode_set mode_set; +}; + +struct drm_fb_helper_funcs { + void (*gamma_set)(struct drm_crtc *crtc, u16 red, u16 green, + u16 blue, int regno); +}; + +struct drm_fb_helper { + struct drm_framebuffer *fb; + struct drm_device *dev; + struct drm_display_mode *mode; + int crtc_count; + struct drm_fb_helper_crtc *crtc_info; + struct drm_fb_helper_funcs *funcs; + int conn_limit; + struct list_head kernel_fb_list; +}; + +int drm_fb_helper_single_fb_probe(struct drm_device *dev, + int (*fb_create)(struct drm_device *dev, + uint32_t fb_width, + uint32_t fb_height, + uint32_t surface_width, + uint32_t surface_height, + struct drm_framebuffer **fb_ptr)); +int drm_fb_helper_init_crtc_count(struct drm_fb_helper *helper, int crtc_count, + int max_conn); +void drm_fb_helper_free(struct drm_fb_helper *helper); +int drm_fb_helper_blank(int blank, struct fb_info *info); +int drm_fb_helper_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info); +int drm_fb_helper_set_par(struct fb_info *info); +int drm_fb_helper_check_var(struct fb_var_screeninfo *var, + struct fb_info *info); +int drm_fb_helper_setcolreg(unsigned regno, + unsigned red, + unsigned green, + unsigned blue, + unsigned transp, + struct fb_info *info); + +void drm_fb_helper_restore(void); +void drm_fb_helper_fill_var(struct fb_info *info, struct drm_framebuffer *fb, + uint32_t fb_width, uint32_t fb_height); +void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch); + +#endif diff --git a/include/drm/drm_mm.h b/include/drm/drm_mm.h index f8332073d277..62329f9a42cb 100644 --- a/include/drm/drm_mm.h +++ b/include/drm/drm_mm.h @@ -37,6 +37,9 @@ * Generic range manager structs */ #include +#ifdef CONFIG_DEBUG_FS +#include +#endif struct drm_mm_node { struct list_head fl_entry; @@ -96,4 +99,8 @@ static inline struct drm_mm *drm_get_mm(struct drm_mm_node *block) return block->mm; } +#ifdef CONFIG_DEBUG_FS +int drm_mm_dump_table(struct seq_file *m, struct drm_mm *mm); +#endif + #endif diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h index ae304cc73c90..1f908416aedb 100644 --- a/include/drm/drm_mode.h +++ b/include/drm/drm_mode.h @@ -68,10 +68,11 @@ #define DRM_MODE_DPMS_OFF 3 /* Scaling mode options */ -#define DRM_MODE_SCALE_NON_GPU 0 -#define DRM_MODE_SCALE_FULLSCREEN 1 -#define DRM_MODE_SCALE_NO_SCALE 2 -#define DRM_MODE_SCALE_ASPECT 3 +#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or + software can still scale) */ +#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */ +#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ +#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ /* Dithering mode options */ #define DRM_MODE_DITHERING_OFF 0 @@ -141,6 +142,7 @@ struct drm_mode_get_encoder { #define DRM_MODE_SUBCONNECTOR_Composite 5 #define DRM_MODE_SUBCONNECTOR_SVIDEO 6 #define DRM_MODE_SUBCONNECTOR_Component 8 +#define DRM_MODE_SUBCONNECTOR_SCART 9 #define DRM_MODE_CONNECTOR_Unknown 0 #define DRM_MODE_CONNECTOR_VGA 1 @@ -155,6 +157,7 @@ struct drm_mode_get_encoder { #define DRM_MODE_CONNECTOR_DisplayPort 10 #define DRM_MODE_CONNECTOR_HDMIA 11 #define DRM_MODE_CONNECTOR_HDMIB 12 +#define DRM_MODE_CONNECTOR_TV 13 struct drm_mode_get_connector { diff --git a/include/drm/drm_sysfs.h b/include/drm/drm_sysfs.h new file mode 100644 index 000000000000..1d8e033fde67 --- /dev/null +++ b/include/drm/drm_sysfs.h @@ -0,0 +1,12 @@ +#ifndef _DRM_SYSFS_H_ +#define _DRM_SYSFS_H_ + +/** + * This minimalistic include file is intended for users (read TTM) that + * don't want to include the full drmP.h file. + */ + +extern int drm_class_device_register(struct device *dev); +extern void drm_class_device_unregister(struct device *dev); + +#endif diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h index 2ba61e18fc8b..3b9932ab1756 100644 --- a/include/drm/radeon_drm.h +++ b/include/drm/radeon_drm.h @@ -802,11 +802,12 @@ struct drm_radeon_gem_create { uint32_t flags; }; -#define RADEON_TILING_MACRO 0x1 -#define RADEON_TILING_MICRO 0x2 -#define RADEON_TILING_SWAP 0x4 -#define RADEON_TILING_SURFACE 0x8 /* this object requires a surface - * when mapped - i.e. front buffer */ +#define RADEON_TILING_MACRO 0x1 +#define RADEON_TILING_MICRO 0x2 +#define RADEON_TILING_SWAP_16BIT 0x4 +#define RADEON_TILING_SWAP_32BIT 0x8 +#define RADEON_TILING_SURFACE 0x10 /* this object requires a surface + * when mapped - i.e. front buffer */ struct drm_radeon_gem_set_tiling { uint32_t handle; @@ -899,6 +900,7 @@ struct drm_radeon_cs { #define RADEON_INFO_DEVICE_ID 0x00 #define RADEON_INFO_NUM_GB_PIPES 0x01 #define RADEON_INFO_NUM_Z_PIPES 0x02 +#define RADEON_INFO_ACCEL_WORKING 0x03 struct drm_radeon_info { uint32_t request; diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h index cd22ab4b495c..491146170522 100644 --- a/include/drm/ttm/ttm_bo_api.h +++ b/include/drm/ttm/ttm_bo_api.h @@ -155,6 +155,7 @@ struct ttm_buffer_object { * Members constant at init. */ + struct ttm_bo_global *glob; struct ttm_bo_device *bdev; unsigned long buffer_start; enum ttm_bo_type type; @@ -245,14 +246,15 @@ struct ttm_buffer_object { * premapped region. */ +#define TTM_BO_MAP_IOMEM_MASK 0x80 struct ttm_bo_kmap_obj { void *virtual; struct page *page; enum { - ttm_bo_map_iomap, - ttm_bo_map_vmap, - ttm_bo_map_kmap, - ttm_bo_map_premapped, + ttm_bo_map_iomap = 1 | TTM_BO_MAP_IOMEM_MASK, + ttm_bo_map_vmap = 2, + ttm_bo_map_kmap = 3, + ttm_bo_map_premapped = 4 | TTM_BO_MAP_IOMEM_MASK, } bo_kmap_type; }; @@ -522,8 +524,7 @@ extern int ttm_bo_evict_mm(struct ttm_bo_device *bdev, unsigned mem_type); static inline void *ttm_kmap_obj_virtual(struct ttm_bo_kmap_obj *map, bool *is_iomem) { - *is_iomem = (map->bo_kmap_type == ttm_bo_map_iomap || - map->bo_kmap_type == ttm_bo_map_premapped); + *is_iomem = !!(map->bo_kmap_type & TTM_BO_MAP_IOMEM_MASK); return map->virtual; } diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h index a68829db381a..e8cd6d20aed2 100644 --- a/include/drm/ttm/ttm_bo_driver.h +++ b/include/drm/ttm/ttm_bo_driver.h @@ -32,6 +32,7 @@ #include "ttm/ttm_bo_api.h" #include "ttm/ttm_memory.h" +#include "ttm/ttm_module.h" #include "drm_mm.h" #include "linux/workqueue.h" #include "linux/fs.h" @@ -161,7 +162,7 @@ struct ttm_tt { long last_lomem_page; uint32_t page_flags; unsigned long num_pages; - struct ttm_bo_device *bdev; + struct ttm_bo_global *glob; struct ttm_backend *be; struct task_struct *tsk; unsigned long start; @@ -364,24 +365,73 @@ struct ttm_bo_driver { void (*fault_reserve_notify)(struct ttm_buffer_object *bo); }; -#define TTM_NUM_MEM_TYPES 8 +/** + * struct ttm_bo_global_ref - Argument to initialize a struct ttm_bo_global. + */ + +struct ttm_bo_global_ref { + struct ttm_global_reference ref; + struct ttm_mem_global *mem_glob; +}; -#define TTM_BO_PRIV_FLAG_MOVING 0 /* Buffer object is moving and needs - idling before CPU mapping */ -#define TTM_BO_PRIV_FLAG_MAX 1 /** - * struct ttm_bo_device - Buffer object driver device-specific data. + * struct ttm_bo_global - Buffer object driver global data. * * @mem_glob: Pointer to a struct ttm_mem_global object for accounting. - * @driver: Pointer to a struct ttm_bo_driver struct setup by the driver. - * @count: Current number of buffer object. - * @pages: Current number of pinned pages. * @dummy_read_page: Pointer to a dummy page used for mapping requests * of unpopulated pages. - * @shrink: A shrink callback object used for buffre object swap. + * @shrink: A shrink callback object used for buffer object swap. * @ttm_bo_extra_size: Extra size (sizeof(struct ttm_buffer_object) excluded) * used by a buffer object. This is excluding page arrays and backing pages. * @ttm_bo_size: This is @ttm_bo_extra_size + sizeof(struct ttm_buffer_object). + * @device_list_mutex: Mutex protecting the device list. + * This mutex is held while traversing the device list for pm options. + * @lru_lock: Spinlock protecting the bo subsystem lru lists. + * @device_list: List of buffer object devices. + * @swap_lru: Lru list of buffer objects used for swapping. + */ + +struct ttm_bo_global { + + /** + * Constant after init. + */ + + struct kobject kobj; + struct ttm_mem_global *mem_glob; + struct page *dummy_read_page; + struct ttm_mem_shrink shrink; + size_t ttm_bo_extra_size; + size_t ttm_bo_size; + struct mutex device_list_mutex; + spinlock_t lru_lock; + + /** + * Protected by device_list_mutex. + */ + struct list_head device_list; + + /** + * Protected by the lru_lock. + */ + struct list_head swap_lru; + + /** + * Internal protection. + */ + atomic_t bo_count; +}; + + +#define TTM_NUM_MEM_TYPES 8 + +#define TTM_BO_PRIV_FLAG_MOVING 0 /* Buffer object is moving and needs + idling before CPU mapping */ +#define TTM_BO_PRIV_FLAG_MAX 1 +/** + * struct ttm_bo_device - Buffer object driver device-specific data. + * + * @driver: Pointer to a struct ttm_bo_driver struct setup by the driver. * @man: An array of mem_type_managers. * @addr_space_mm: Range manager for the device address space. * lru_lock: Spinlock that protects the buffer+device lru lists and @@ -399,32 +449,21 @@ struct ttm_bo_device { /* * Constant after bo device init / atomic. */ - - struct ttm_mem_global *mem_glob; + struct list_head device_list; + struct ttm_bo_global *glob; struct ttm_bo_driver *driver; - struct page *dummy_read_page; - struct ttm_mem_shrink shrink; - - size_t ttm_bo_extra_size; - size_t ttm_bo_size; - rwlock_t vm_lock; + struct ttm_mem_type_manager man[TTM_NUM_MEM_TYPES]; /* * Protected by the vm lock. */ - struct ttm_mem_type_manager man[TTM_NUM_MEM_TYPES]; struct rb_root addr_space_rb; struct drm_mm addr_space_mm; /* - * Might want to change this to one lock per manager. - */ - spinlock_t lru_lock; - /* - * Protected by the lru lock. + * Protected by the global:lru lock. */ struct list_head ddestroy; - struct list_head swap_lru; /* * Protected by load / firstopen / lastclose /unload sync. @@ -640,6 +679,9 @@ extern int ttm_bo_pci_offset(struct ttm_bo_device *bdev, unsigned long *bus_offset, unsigned long *bus_size); +extern void ttm_bo_global_release(struct ttm_global_reference *ref); +extern int ttm_bo_global_init(struct ttm_global_reference *ref); + extern int ttm_bo_device_release(struct ttm_bo_device *bdev); /** @@ -657,7 +699,7 @@ extern int ttm_bo_device_release(struct ttm_bo_device *bdev); * !0: Failure. */ extern int ttm_bo_device_init(struct ttm_bo_device *bdev, - struct ttm_mem_global *mem_glob, + struct ttm_bo_global *glob, struct ttm_bo_driver *driver, uint64_t file_page_offset, bool need_dma32); diff --git a/include/drm/ttm/ttm_memory.h b/include/drm/ttm/ttm_memory.h index d8b8f042c4f1..6983a7cf4da4 100644 --- a/include/drm/ttm/ttm_memory.h +++ b/include/drm/ttm/ttm_memory.h @@ -32,6 +32,7 @@ #include #include #include +#include /** * struct ttm_mem_shrink - callback to shrink TTM memory usage. @@ -60,34 +61,33 @@ struct ttm_mem_shrink { * @queue: Wait queue for processes suspended waiting for memory. * @lock: Lock to protect the @shrink - and the memory accounting members, * that is, essentially the whole structure with some exceptions. - * @emer_memory: Lowmem memory limit available for root. - * @max_memory: Lowmem memory limit available for non-root. - * @swap_limit: Lowmem memory limit where the shrink workqueue kicks in. - * @used_memory: Currently used lowmem memory. - * @used_total_memory: Currently used total (lowmem + highmem) memory. - * @total_memory_swap_limit: Total memory limit where the shrink workqueue - * kicks in. - * @max_total_memory: Total memory available to non-root processes. - * @emer_total_memory: Total memory available to root processes. + * @zones: Array of pointers to accounting zones. + * @num_zones: Number of populated entries in the @zones array. + * @zone_kernel: Pointer to the kernel zone. + * @zone_highmem: Pointer to the highmem zone if there is one. + * @zone_dma32: Pointer to the dma32 zone if there is one. * * Note that this structure is not per device. It should be global for all * graphics devices. */ +#define TTM_MEM_MAX_ZONES 2 +struct ttm_mem_zone; struct ttm_mem_global { + struct kobject kobj; struct ttm_mem_shrink *shrink; struct workqueue_struct *swap_queue; struct work_struct work; wait_queue_head_t queue; spinlock_t lock; - uint64_t emer_memory; - uint64_t max_memory; - uint64_t swap_limit; - uint64_t used_memory; - uint64_t used_total_memory; - uint64_t total_memory_swap_limit; - uint64_t max_total_memory; - uint64_t emer_total_memory; + struct ttm_mem_zone *zones[TTM_MEM_MAX_ZONES]; + unsigned int num_zones; + struct ttm_mem_zone *zone_kernel; +#ifdef CONFIG_HIGHMEM + struct ttm_mem_zone *zone_highmem; +#else + struct ttm_mem_zone *zone_dma32; +#endif }; /** @@ -146,8 +146,13 @@ static inline void ttm_mem_unregister_shrink(struct ttm_mem_global *glob, extern int ttm_mem_global_init(struct ttm_mem_global *glob); extern void ttm_mem_global_release(struct ttm_mem_global *glob); extern int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory, - bool no_wait, bool interruptible, bool himem); + bool no_wait, bool interruptible); extern void ttm_mem_global_free(struct ttm_mem_global *glob, - uint64_t amount, bool himem); + uint64_t amount); +extern int ttm_mem_global_alloc_page(struct ttm_mem_global *glob, + struct page *page, + bool no_wait, bool interruptible); +extern void ttm_mem_global_free_page(struct ttm_mem_global *glob, + struct page *page); extern size_t ttm_round_pot(size_t size); #endif diff --git a/include/drm/ttm/ttm_module.h b/include/drm/ttm/ttm_module.h index d1d433834e4f..cf416aee19af 100644 --- a/include/drm/ttm/ttm_module.h +++ b/include/drm/ttm/ttm_module.h @@ -32,6 +32,7 @@ #define _TTM_MODULE_H_ #include +struct kobject; #define TTM_PFX "[TTM] " @@ -54,5 +55,6 @@ extern void ttm_global_init(void); extern void ttm_global_release(void); extern int ttm_global_item_ref(struct ttm_global_reference *ref); extern void ttm_global_item_unref(struct ttm_global_reference *ref); +extern struct kobject *ttm_get_kobj(void); #endif /* _TTM_MODULE_H_ */ diff --git a/include/linux/dvb/frontend.h b/include/linux/dvb/frontend.h index 51c8d2d49e42..b6cb5425cde3 100644 --- a/include/linux/dvb/frontend.h +++ b/include/linux/dvb/frontend.h @@ -173,7 +173,8 @@ typedef enum fe_modulation { typedef enum fe_transmit_mode { TRANSMISSION_MODE_2K, TRANSMISSION_MODE_8K, - TRANSMISSION_MODE_AUTO + TRANSMISSION_MODE_AUTO, + TRANSMISSION_MODE_4K } fe_transmit_mode_t; typedef enum fe_bandwidth { @@ -268,15 +269,42 @@ struct dvb_frontend_event { #define DTV_FE_CAPABILITY 16 #define DTV_DELIVERY_SYSTEM 17 -#define DTV_API_VERSION 35 -#define DTV_API_VERSION 35 -#define DTV_CODE_RATE_HP 36 -#define DTV_CODE_RATE_LP 37 -#define DTV_GUARD_INTERVAL 38 -#define DTV_TRANSMISSION_MODE 39 -#define DTV_HIERARCHY 40 +/* ISDB-T and ISDB-Tsb */ +#define DTV_ISDBT_PARTIAL_RECEPTION 18 +#define DTV_ISDBT_SOUND_BROADCASTING 19 -#define DTV_MAX_COMMAND DTV_HIERARCHY +#define DTV_ISDBT_SB_SUBCHANNEL_ID 20 +#define DTV_ISDBT_SB_SEGMENT_IDX 21 +#define DTV_ISDBT_SB_SEGMENT_COUNT 22 + +#define DTV_ISDBT_LAYERA_FEC 23 +#define DTV_ISDBT_LAYERA_MODULATION 24 +#define DTV_ISDBT_LAYERA_SEGMENT_COUNT 25 +#define DTV_ISDBT_LAYERA_TIME_INTERLEAVING 26 + +#define DTV_ISDBT_LAYERB_FEC 27 +#define DTV_ISDBT_LAYERB_MODULATION 28 +#define DTV_ISDBT_LAYERB_SEGMENT_COUNT 29 +#define DTV_ISDBT_LAYERB_TIME_INTERLEAVING 30 + +#define DTV_ISDBT_LAYERC_FEC 31 +#define DTV_ISDBT_LAYERC_MODULATION 32 +#define DTV_ISDBT_LAYERC_SEGMENT_COUNT 33 +#define DTV_ISDBT_LAYERC_TIME_INTERLEAVING 34 + +#define DTV_API_VERSION 35 + +#define DTV_CODE_RATE_HP 36 +#define DTV_CODE_RATE_LP 37 +#define DTV_GUARD_INTERVAL 38 +#define DTV_TRANSMISSION_MODE 39 +#define DTV_HIERARCHY 40 + +#define DTV_ISDBT_LAYER_ENABLED 41 + +#define DTV_ISDBS_TS_ID 42 + +#define DTV_MAX_COMMAND DTV_ISDBS_TS_ID typedef enum fe_pilot { PILOT_ON, diff --git a/include/linux/dvb/version.h b/include/linux/dvb/version.h index 25b823b81734..540b0583d9fb 100644 --- a/include/linux/dvb/version.h +++ b/include/linux/dvb/version.h @@ -24,6 +24,6 @@ #define _DVBVERSION_H_ #define DVB_API_VERSION 5 -#define DVB_API_VERSION_MINOR 0 +#define DVB_API_VERSION_MINOR 1 #endif /*_DVBVERSION_H_*/ diff --git a/include/linux/ftrace_event.h b/include/linux/ftrace_event.h index bd099ba82ccc..4ec5e67e18cf 100644 --- a/include/linux/ftrace_event.h +++ b/include/linux/ftrace_event.h @@ -4,6 +4,7 @@ #include #include #include +#include struct trace_array; struct tracer; @@ -130,10 +131,15 @@ struct ftrace_event_call { void *data; atomic_t profile_count; - int (*profile_enable)(struct ftrace_event_call *); - void (*profile_disable)(struct ftrace_event_call *); + int (*profile_enable)(void); + void (*profile_disable)(void); }; +#define FTRACE_MAX_PROFILE_SIZE 2048 + +extern char *trace_profile_buf; +extern char *trace_profile_buf_nmi; + #define MAX_FILTER_PRED 32 #define MAX_FILTER_STR_VAL 256 /* Should handle KSYM_SYMBOL_LEN */ diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 4af56036a6bf..b7bbb5ddd7ae 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -15,7 +15,6 @@ #include #include #include -#include #include #include diff --git a/include/linux/marker.h b/include/linux/marker.h deleted file mode 100644 index b85e74ca782f..000000000000 --- a/include/linux/marker.h +++ /dev/null @@ -1,221 +0,0 @@ -#ifndef _LINUX_MARKER_H -#define _LINUX_MARKER_H - -/* - * Code markup for dynamic and static tracing. - * - * See Documentation/marker.txt. - * - * (C) Copyright 2006 Mathieu Desnoyers - * - * This file is released under the GPLv2. - * See the file COPYING for more details. - */ - -#include -#include - -struct module; -struct marker; - -/** - * marker_probe_func - Type of a marker probe function - * @probe_private: probe private data - * @call_private: call site private data - * @fmt: format string - * @args: variable argument list pointer. Use a pointer to overcome C's - * inability to pass this around as a pointer in a portable manner in - * the callee otherwise. - * - * Type of marker probe functions. They receive the mdata and need to parse the - * format string to recover the variable argument list. - */ -typedef void marker_probe_func(void *probe_private, void *call_private, - const char *fmt, va_list *args); - -struct marker_probe_closure { - marker_probe_func *func; /* Callback */ - void *probe_private; /* Private probe data */ -}; - -struct marker { - const char *name; /* Marker name */ - const char *format; /* Marker format string, describing the - * variable argument list. - */ - char state; /* Marker state. */ - char ptype; /* probe type : 0 : single, 1 : multi */ - /* Probe wrapper */ - void (*call)(const struct marker *mdata, void *call_private, ...); - struct marker_probe_closure single; - struct marker_probe_closure *multi; - const char *tp_name; /* Optional tracepoint name */ - void *tp_cb; /* Optional tracepoint callback */ -} __attribute__((aligned(8))); - -#ifdef CONFIG_MARKERS - -#define _DEFINE_MARKER(name, tp_name_str, tp_cb, format) \ - static const char __mstrtab_##name[] \ - __attribute__((section("__markers_strings"))) \ - = #name "\0" format; \ - static struct marker __mark_##name \ - __attribute__((section("__markers"), aligned(8))) = \ - { __mstrtab_##name, &__mstrtab_##name[sizeof(#name)], \ - 0, 0, marker_probe_cb, { __mark_empty_function, NULL},\ - NULL, tp_name_str, tp_cb } - -#define DEFINE_MARKER(name, format) \ - _DEFINE_MARKER(name, NULL, NULL, format) - -#define DEFINE_MARKER_TP(name, tp_name, tp_cb, format) \ - _DEFINE_MARKER(name, #tp_name, tp_cb, format) - -/* - * Note : the empty asm volatile with read constraint is used here instead of a - * "used" attribute to fix a gcc 4.1.x bug. - * Make sure the alignment of the structure in the __markers section will - * not add unwanted padding between the beginning of the section and the - * structure. Force alignment to the same alignment as the section start. - * - * The "generic" argument controls which marker enabling mechanism must be used. - * If generic is true, a variable read is used. - * If generic is false, immediate values are used. - */ -#define __trace_mark(generic, name, call_private, format, args...) \ - do { \ - DEFINE_MARKER(name, format); \ - __mark_check_format(format, ## args); \ - if (unlikely(__mark_##name.state)) { \ - (*__mark_##name.call) \ - (&__mark_##name, call_private, ## args);\ - } \ - } while (0) - -#define __trace_mark_tp(name, call_private, tp_name, tp_cb, format, args...) \ - do { \ - void __check_tp_type(void) \ - { \ - register_trace_##tp_name(tp_cb); \ - } \ - DEFINE_MARKER_TP(name, tp_name, tp_cb, format); \ - __mark_check_format(format, ## args); \ - (*__mark_##name.call)(&__mark_##name, call_private, \ - ## args); \ - } while (0) - -extern void marker_update_probe_range(struct marker *begin, - struct marker *end); - -#define GET_MARKER(name) (__mark_##name) - -#else /* !CONFIG_MARKERS */ -#define DEFINE_MARKER(name, tp_name, tp_cb, format) -#define __trace_mark(generic, name, call_private, format, args...) \ - __mark_check_format(format, ## args) -#define __trace_mark_tp(name, call_private, tp_name, tp_cb, format, args...) \ - do { \ - void __check_tp_type(void) \ - { \ - register_trace_##tp_name(tp_cb); \ - } \ - __mark_check_format(format, ## args); \ - } while (0) -static inline void marker_update_probe_range(struct marker *begin, - struct marker *end) -{ } -#define GET_MARKER(name) -#endif /* CONFIG_MARKERS */ - -/** - * trace_mark - Marker using code patching - * @name: marker name, not quoted. - * @format: format string - * @args...: variable argument list - * - * Places a marker using optimized code patching technique (imv_read()) - * to be enabled when immediate values are present. - */ -#define trace_mark(name, format, args...) \ - __trace_mark(0, name, NULL, format, ## args) - -/** - * _trace_mark - Marker using variable read - * @name: marker name, not quoted. - * @format: format string - * @args...: variable argument list - * - * Places a marker using a standard memory read (_imv_read()) to be - * enabled. Should be used for markers in code paths where instruction - * modification based enabling is not welcome. (__init and __exit functions, - * lockdep, some traps, printk). - */ -#define _trace_mark(name, format, args...) \ - __trace_mark(1, name, NULL, format, ## args) - -/** - * trace_mark_tp - Marker in a tracepoint callback - * @name: marker name, not quoted. - * @tp_name: tracepoint name, not quoted. - * @tp_cb: tracepoint callback. Should have an associated global symbol so it - * is not optimized away by the compiler (should not be static). - * @format: format string - * @args...: variable argument list - * - * Places a marker in a tracepoint callback. - */ -#define trace_mark_tp(name, tp_name, tp_cb, format, args...) \ - __trace_mark_tp(name, NULL, tp_name, tp_cb, format, ## args) - -/** - * MARK_NOARGS - Format string for a marker with no argument. - */ -#define MARK_NOARGS " " - -/* To be used for string format validity checking with gcc */ -static inline void __printf(1, 2) ___mark_check_format(const char *fmt, ...) -{ -} - -#define __mark_check_format(format, args...) \ - do { \ - if (0) \ - ___mark_check_format(format, ## args); \ - } while (0) - -extern marker_probe_func __mark_empty_function; - -extern void marker_probe_cb(const struct marker *mdata, - void *call_private, ...); - -/* - * Connect a probe to a marker. - * private data pointer must be a valid allocated memory address, or NULL. - */ -extern int marker_probe_register(const char *name, const char *format, - marker_probe_func *probe, void *probe_private); - -/* - * Returns the private data given to marker_probe_register. - */ -extern int marker_probe_unregister(const char *name, - marker_probe_func *probe, void *probe_private); -/* - * Unregister a marker by providing the registered private data. - */ -extern int marker_probe_unregister_private_data(marker_probe_func *probe, - void *probe_private); - -extern void *marker_get_private_data(const char *name, marker_probe_func *probe, - int num); - -/* - * marker_synchronize_unregister must be called between the last marker probe - * unregistration and the first one of - * - the end of module exit function - * - the free of any resource used by the probes - * to ensure the code and data are valid for any possibly running probes. - */ -#define marker_synchronize_unregister() synchronize_sched() - -#endif diff --git a/include/linux/module.h b/include/linux/module.h index f8f92d015efe..1c755b2f937d 100644 --- a/include/linux/module.h +++ b/include/linux/module.h @@ -15,7 +15,6 @@ #include #include #include -#include #include #include @@ -327,10 +326,6 @@ struct module /* The command line arguments (may be mangled). People like keeping pointers to this stuff */ char *args; -#ifdef CONFIG_MARKERS - struct marker *markers; - unsigned int num_markers; -#endif #ifdef CONFIG_TRACEPOINTS struct tracepoint *tracepoints; unsigned int num_tracepoints; @@ -535,8 +530,6 @@ int unregister_module_notifier(struct notifier_block * nb); extern void print_modules(void); -extern void module_update_markers(void); - extern void module_update_tracepoints(void); extern int module_get_iter_tracepoints(struct tracepoint_iter *iter); @@ -651,10 +644,6 @@ static inline void print_modules(void) { } -static inline void module_update_markers(void) -{ -} - static inline void module_update_tracepoints(void) { } diff --git a/include/linux/rculist_nulls.h b/include/linux/rculist_nulls.h index f9ddd03961a8..589a40919f01 100644 --- a/include/linux/rculist_nulls.h +++ b/include/linux/rculist_nulls.h @@ -102,7 +102,7 @@ static inline void hlist_nulls_add_head_rcu(struct hlist_nulls_node *n, */ #define hlist_nulls_for_each_entry_rcu(tpos, pos, head, member) \ for (pos = rcu_dereference((head)->first); \ - (!is_a_nulls(pos)) && \ + (!is_a_nulls(pos)) && \ ({ tpos = hlist_nulls_entry(pos, typeof(*tpos), member); 1; }); \ pos = rcu_dereference(pos->next)) diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h index 95e0615f4d75..6fe0363724e9 100644 --- a/include/linux/rcupdate.h +++ b/include/linux/rcupdate.h @@ -1,5 +1,5 @@ /* - * Read-Copy Update mechanism for mutual exclusion + * Read-Copy Update mechanism for mutual exclusion * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * Copyright IBM Corporation, 2001 * * Author: Dipankar Sarma - * + * * Based on the original work by Paul McKenney * and inputs from Rusty Russell, Andrea Arcangeli and Andi Kleen. * Papers: @@ -26,7 +26,7 @@ * http://lse.sourceforge.net/locking/rclock_OLS.2001.05.01c.sc.pdf (OLS2001) * * For detailed explanation of Read-Copy Update mechanism see - - * http://lse.sourceforge.net/locking/rcupdate.html + * http://lse.sourceforge.net/locking/rcupdate.html * */ @@ -52,8 +52,13 @@ struct rcu_head { }; /* Exported common interfaces */ +#ifdef CONFIG_TREE_PREEMPT_RCU extern void synchronize_rcu(void); +#else /* #ifdef CONFIG_TREE_PREEMPT_RCU */ +#define synchronize_rcu synchronize_sched +#endif /* #else #ifdef CONFIG_TREE_PREEMPT_RCU */ extern void synchronize_rcu_bh(void); +extern void synchronize_sched(void); extern void rcu_barrier(void); extern void rcu_barrier_bh(void); extern void rcu_barrier_sched(void); @@ -261,24 +266,6 @@ struct rcu_synchronize { extern void wakeme_after_rcu(struct rcu_head *head); -/** - * synchronize_sched - block until all CPUs have exited any non-preemptive - * kernel code sequences. - * - * This means that all preempt_disable code sequences, including NMI and - * hardware-interrupt handlers, in progress on entry will have completed - * before this primitive returns. However, this does not guarantee that - * softirq handlers will have completed, since in some kernels, these - * handlers can run in process context, and can block. - * - * This primitive provides the guarantees made by the (now removed) - * synchronize_kernel() API. In contrast, synchronize_rcu() only - * guarantees that rcu_read_lock() sections will have completed. - * In "classic RCU", these two guarantees happen to be one and - * the same, but can differ in realtime RCU implementations. - */ -#define synchronize_sched() __synchronize_sched() - /** * call_rcu - Queue an RCU callback for invocation after a grace period. * @head: structure to be used for queueing the RCU updates. diff --git a/include/linux/rcutree.h b/include/linux/rcutree.h index a89307717825..37682770e9d2 100644 --- a/include/linux/rcutree.h +++ b/include/linux/rcutree.h @@ -24,7 +24,7 @@ * and inputs from Rusty Russell, Andrea Arcangeli and Andi Kleen. * * For detailed explanation of Read-Copy Update mechanism see - - * Documentation/RCU + * Documentation/RCU */ #ifndef __LINUX_RCUTREE_H @@ -53,6 +53,8 @@ static inline void __rcu_read_unlock(void) preempt_enable(); } +#define __synchronize_sched() synchronize_rcu() + static inline void exit_rcu(void) { } @@ -68,8 +70,6 @@ static inline void __rcu_read_unlock_bh(void) local_bh_enable(); } -#define __synchronize_sched() synchronize_rcu() - extern void call_rcu_sched(struct rcu_head *head, void (*func)(struct rcu_head *rcu)); diff --git a/include/linux/sched.h b/include/linux/sched.h index 8b265a8986d0..8fe351c3914a 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -257,7 +257,7 @@ extern asmlinkage void schedule_tail(struct task_struct *prev); extern void init_idle(struct task_struct *idle, int cpu); extern void init_idle_bootup_task(struct task_struct *idle); -extern int runqueue_is_locked(void); +extern int runqueue_is_locked(int cpu); extern void task_rq_unlock_wait(struct task_struct *p); extern cpumask_var_t nohz_cpu_mask; @@ -1075,6 +1075,8 @@ struct sched_class { void (*prio_changed) (struct rq *this_rq, struct task_struct *task, int oldprio, int running); + unsigned int (*get_rr_interval) (struct task_struct *task); + #ifdef CONFIG_FAIR_GROUP_SCHED void (*moved_group) (struct task_struct *p); #endif @@ -1753,7 +1755,6 @@ extern cputime_t task_gtime(struct task_struct *p); #define RCU_READ_UNLOCK_BLOCKED (1 << 0) /* blocked while in RCU read-side. */ #define RCU_READ_UNLOCK_NEED_QS (1 << 1) /* RCU core needs CPU response. */ -#define RCU_READ_UNLOCK_GOT_QS (1 << 2) /* CPU has responded to RCU core. */ static inline void rcu_copy_process(struct task_struct *p) { diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h index 02f19f9a76c6..8d8285a10db9 100644 --- a/include/linux/syscalls.h +++ b/include/linux/syscalls.h @@ -100,33 +100,25 @@ struct perf_event_attr; #ifdef CONFIG_EVENT_PROFILE #define TRACE_SYS_ENTER_PROFILE(sname) \ -static int prof_sysenter_enable_##sname(struct ftrace_event_call *event_call) \ +static int prof_sysenter_enable_##sname(void) \ { \ - int ret = 0; \ - if (!atomic_inc_return(&event_enter_##sname.profile_count)) \ - ret = reg_prof_syscall_enter("sys"#sname); \ - return ret; \ + return reg_prof_syscall_enter("sys"#sname); \ } \ \ -static void prof_sysenter_disable_##sname(struct ftrace_event_call *event_call)\ +static void prof_sysenter_disable_##sname(void) \ { \ - if (atomic_add_negative(-1, &event_enter_##sname.profile_count)) \ - unreg_prof_syscall_enter("sys"#sname); \ + unreg_prof_syscall_enter("sys"#sname); \ } #define TRACE_SYS_EXIT_PROFILE(sname) \ -static int prof_sysexit_enable_##sname(struct ftrace_event_call *event_call) \ +static int prof_sysexit_enable_##sname(void) \ { \ - int ret = 0; \ - if (!atomic_inc_return(&event_exit_##sname.profile_count)) \ - ret = reg_prof_syscall_exit("sys"#sname); \ - return ret; \ + return reg_prof_syscall_exit("sys"#sname); \ } \ \ -static void prof_sysexit_disable_##sname(struct ftrace_event_call *event_call) \ +static void prof_sysexit_disable_##sname(void) \ { \ - if (atomic_add_negative(-1, &event_exit_##sname.profile_count)) \ - unreg_prof_syscall_exit("sys"#sname); \ + unreg_prof_syscall_exit("sys"#sname); \ } #define TRACE_SYS_ENTER_PROFILE_INIT(sname) \ diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h index 3689d7d81fe9..b59e78c57161 100644 --- a/include/linux/videodev2.h +++ b/include/linux/videodev2.h @@ -910,9 +910,10 @@ enum v4l2_colorfx { V4L2_COLORFX_SEPIA = 2, }; #define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE+32) +#define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE+33) /* last CID + 1 */ -#define V4L2_CID_LASTP1 (V4L2_CID_BASE+33) +#define V4L2_CID_LASTP1 (V4L2_CID_BASE+34) /* MPEG-class control IDs defined by V4L2 */ #define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900) diff --git a/include/media/davinci/ccdc_types.h b/include/media/davinci/ccdc_types.h new file mode 100644 index 000000000000..5773874bf266 --- /dev/null +++ b/include/media/davinci/ccdc_types.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2008-2009 Texas Instruments Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + **************************************************************************/ +#ifndef _CCDC_TYPES_H +#define _CCDC_TYPES_H +enum ccdc_pixfmt { + CCDC_PIXFMT_RAW, + CCDC_PIXFMT_YCBCR_16BIT, + CCDC_PIXFMT_YCBCR_8BIT +}; + +enum ccdc_frmfmt { + CCDC_FRMFMT_PROGRESSIVE, + CCDC_FRMFMT_INTERLACED +}; + +/* PIXEL ORDER IN MEMORY from LSB to MSB */ +/* only applicable for 8-bit input mode */ +enum ccdc_pixorder { + CCDC_PIXORDER_YCBYCR, + CCDC_PIXORDER_CBYCRY, +}; + +enum ccdc_buftype { + CCDC_BUFTYPE_FLD_INTERLEAVED, + CCDC_BUFTYPE_FLD_SEPARATED +}; +#endif diff --git a/include/media/davinci/dm355_ccdc.h b/include/media/davinci/dm355_ccdc.h new file mode 100644 index 000000000000..df8a7b107477 --- /dev/null +++ b/include/media/davinci/dm355_ccdc.h @@ -0,0 +1,321 @@ +/* + * Copyright (C) 2005-2009 Texas Instruments Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _DM355_CCDC_H +#define _DM355_CCDC_H +#include +#include + +/* enum for No of pixel per line to be avg. in Black Clamping */ +enum ccdc_sample_length { + CCDC_SAMPLE_1PIXELS, + CCDC_SAMPLE_2PIXELS, + CCDC_SAMPLE_4PIXELS, + CCDC_SAMPLE_8PIXELS, + CCDC_SAMPLE_16PIXELS +}; + +/* enum for No of lines in Black Clamping */ +enum ccdc_sample_line { + CCDC_SAMPLE_1LINES, + CCDC_SAMPLE_2LINES, + CCDC_SAMPLE_4LINES, + CCDC_SAMPLE_8LINES, + CCDC_SAMPLE_16LINES +}; + +/* enum for Alaw gama width */ +enum ccdc_gamma_width { + CCDC_GAMMA_BITS_13_4, + CCDC_GAMMA_BITS_12_3, + CCDC_GAMMA_BITS_11_2, + CCDC_GAMMA_BITS_10_1, + CCDC_GAMMA_BITS_09_0 +}; + +enum ccdc_colpats { + CCDC_RED, + CCDC_GREEN_RED, + CCDC_GREEN_BLUE, + CCDC_BLUE +}; + +struct ccdc_col_pat { + enum ccdc_colpats olop; + enum ccdc_colpats olep; + enum ccdc_colpats elop; + enum ccdc_colpats elep; +}; + +enum ccdc_datasft { + CCDC_DATA_NO_SHIFT, + CCDC_DATA_SHIFT_1BIT, + CCDC_DATA_SHIFT_2BIT, + CCDC_DATA_SHIFT_3BIT, + CCDC_DATA_SHIFT_4BIT, + CCDC_DATA_SHIFT_5BIT, + CCDC_DATA_SHIFT_6BIT +}; + +enum ccdc_data_size { + CCDC_DATA_16BITS, + CCDC_DATA_15BITS, + CCDC_DATA_14BITS, + CCDC_DATA_13BITS, + CCDC_DATA_12BITS, + CCDC_DATA_11BITS, + CCDC_DATA_10BITS, + CCDC_DATA_8BITS +}; +enum ccdc_mfilt1 { + CCDC_NO_MEDIAN_FILTER1, + CCDC_AVERAGE_FILTER1, + CCDC_MEDIAN_FILTER1 +}; + +enum ccdc_mfilt2 { + CCDC_NO_MEDIAN_FILTER2, + CCDC_AVERAGE_FILTER2, + CCDC_MEDIAN_FILTER2 +}; + +/* structure for ALaw */ +struct ccdc_a_law { + /* Enable/disable A-Law */ + unsigned char enable; + /* Gama Width Input */ + enum ccdc_gamma_width gama_wd; +}; + +/* structure for Black Clamping */ +struct ccdc_black_clamp { + /* only if bClampEnable is TRUE */ + unsigned char b_clamp_enable; + /* only if bClampEnable is TRUE */ + enum ccdc_sample_length sample_pixel; + /* only if bClampEnable is TRUE */ + enum ccdc_sample_line sample_ln; + /* only if bClampEnable is TRUE */ + unsigned short start_pixel; + /* only if bClampEnable is FALSE */ + unsigned short sgain; + unsigned short dc_sub; +}; + +/* structure for Black Level Compensation */ +struct ccdc_black_compensation { + /* Constant value to subtract from Red component */ + unsigned char r; + /* Constant value to subtract from Gr component */ + unsigned char gr; + /* Constant value to subtract from Blue component */ + unsigned char b; + /* Constant value to subtract from Gb component */ + unsigned char gb; +}; + +struct ccdc_float { + int integer; + unsigned int decimal; +}; + +#define CCDC_CSC_COEFF_TABLE_SIZE 16 +/* structure for color space converter */ +struct ccdc_csc { + unsigned char enable; + /* + * S8Q5. Use 2 decimal precision, user values range from -3.00 to 3.99. + * example - to use 1.03, set integer part as 1, and decimal part as 3 + * to use -1.03, set integer part as -1 and decimal part as 3 + */ + struct ccdc_float coeff[CCDC_CSC_COEFF_TABLE_SIZE]; +}; + +/* Structures for Vertical Defect Correction*/ +enum ccdc_vdf_csl { + CCDC_VDF_NORMAL, + CCDC_VDF_HORZ_INTERPOL_SAT, + CCDC_VDF_HORZ_INTERPOL +}; + +enum ccdc_vdf_cuda { + CCDC_VDF_WHOLE_LINE_CORRECT, + CCDC_VDF_UPPER_DISABLE +}; + +enum ccdc_dfc_mwr { + CCDC_DFC_MWR_WRITE_COMPLETE, + CCDC_DFC_WRITE_REG +}; + +enum ccdc_dfc_mrd { + CCDC_DFC_READ_COMPLETE, + CCDC_DFC_READ_REG +}; + +enum ccdc_dfc_ma_rst { + CCDC_DFC_INCR_ADDR, + CCDC_DFC_CLR_ADDR +}; + +enum ccdc_dfc_mclr { + CCDC_DFC_CLEAR_COMPLETE, + CCDC_DFC_CLEAR +}; + +struct ccdc_dft_corr_ctl { + enum ccdc_vdf_csl vdfcsl; + enum ccdc_vdf_cuda vdfcuda; + unsigned int vdflsft; +}; + +struct ccdc_dft_corr_mem_ctl { + enum ccdc_dfc_mwr dfcmwr; + enum ccdc_dfc_mrd dfcmrd; + enum ccdc_dfc_ma_rst dfcmarst; + enum ccdc_dfc_mclr dfcmclr; +}; + +#define CCDC_DFT_TABLE_SIZE 16 +/* + * Main Structure for vertical defect correction. Vertical defect + * correction can correct upto 16 defects if defects less than 16 + * then pad the rest with 0 + */ +struct ccdc_vertical_dft { + unsigned char ver_dft_en; + unsigned char gen_dft_en; + unsigned int saturation_ctl; + struct ccdc_dft_corr_ctl dft_corr_ctl; + struct ccdc_dft_corr_mem_ctl dft_corr_mem_ctl; + int table_size; + unsigned int dft_corr_horz[CCDC_DFT_TABLE_SIZE]; + unsigned int dft_corr_vert[CCDC_DFT_TABLE_SIZE]; + unsigned int dft_corr_sub1[CCDC_DFT_TABLE_SIZE]; + unsigned int dft_corr_sub2[CCDC_DFT_TABLE_SIZE]; + unsigned int dft_corr_sub3[CCDC_DFT_TABLE_SIZE]; +}; + +struct ccdc_data_offset { + unsigned char horz_offset; + unsigned char vert_offset; +}; + +/* + * Structure for CCDC configuration parameters for raw capture mode passed + * by application + */ +struct ccdc_config_params_raw { + /* data shift to be applied before storing */ + enum ccdc_datasft datasft; + /* data size value from 8 to 16 bits */ + enum ccdc_data_size data_sz; + /* median filter for sdram */ + enum ccdc_mfilt1 mfilt1; + enum ccdc_mfilt2 mfilt2; + /* low pass filter enable/disable */ + unsigned char lpf_enable; + /* Threshold of median filter */ + int med_filt_thres; + /* + * horz and vertical data offset. Appliable for defect correction + * and lsc + */ + struct ccdc_data_offset data_offset; + /* Structure for Optional A-Law */ + struct ccdc_a_law alaw; + /* Structure for Optical Black Clamp */ + struct ccdc_black_clamp blk_clamp; + /* Structure for Black Compensation */ + struct ccdc_black_compensation blk_comp; + /* struture for vertical Defect Correction Module Configuration */ + struct ccdc_vertical_dft vertical_dft; + /* structure for color space converter Module Configuration */ + struct ccdc_csc csc; + /* color patters for bayer capture */ + struct ccdc_col_pat col_pat_field0; + struct ccdc_col_pat col_pat_field1; +}; + +#ifdef __KERNEL__ +#include + +#define CCDC_WIN_PAL {0, 0, 720, 576} +#define CCDC_WIN_VGA {0, 0, 640, 480} + +struct ccdc_params_ycbcr { + /* pixel format */ + enum ccdc_pixfmt pix_fmt; + /* progressive or interlaced frame */ + enum ccdc_frmfmt frm_fmt; + /* video window */ + struct v4l2_rect win; + /* field id polarity */ + enum vpfe_pin_pol fid_pol; + /* vertical sync polarity */ + enum vpfe_pin_pol vd_pol; + /* horizontal sync polarity */ + enum vpfe_pin_pol hd_pol; + /* enable BT.656 embedded sync mode */ + int bt656_enable; + /* cb:y:cr:y or y:cb:y:cr in memory */ + enum ccdc_pixorder pix_order; + /* interleaved or separated fields */ + enum ccdc_buftype buf_type; +}; + +/* Gain applied to Raw Bayer data */ +struct ccdc_gain { + unsigned short r_ye; + unsigned short gr_cy; + unsigned short gb_g; + unsigned short b_mg; +}; + +/* Structure for CCDC configuration parameters for raw capture mode */ +struct ccdc_params_raw { + /* pixel format */ + enum ccdc_pixfmt pix_fmt; + /* progressive or interlaced frame */ + enum ccdc_frmfmt frm_fmt; + /* video window */ + struct v4l2_rect win; + /* field id polarity */ + enum vpfe_pin_pol fid_pol; + /* vertical sync polarity */ + enum vpfe_pin_pol vd_pol; + /* horizontal sync polarity */ + enum vpfe_pin_pol hd_pol; + /* interleaved or separated fields */ + enum ccdc_buftype buf_type; + /* Gain values */ + struct ccdc_gain gain; + /* offset */ + unsigned int ccdc_offset; + /* horizontal flip enable */ + unsigned char horz_flip_enable; + /* + * enable to store the image in inverse order in memory + * (bottom to top) + */ + unsigned char image_invert_enable; + /* Configurable part of raw data */ + struct ccdc_config_params_raw config_params; +}; + +#endif +#endif /* DM355_CCDC_H */ diff --git a/include/media/davinci/dm644x_ccdc.h b/include/media/davinci/dm644x_ccdc.h new file mode 100644 index 000000000000..3e178eb52fb3 --- /dev/null +++ b/include/media/davinci/dm644x_ccdc.h @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2006-2009 Texas Instruments Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _DM644X_CCDC_H +#define _DM644X_CCDC_H +#include +#include + +/* enum for No of pixel per line to be avg. in Black Clamping*/ +enum ccdc_sample_length { + CCDC_SAMPLE_1PIXELS, + CCDC_SAMPLE_2PIXELS, + CCDC_SAMPLE_4PIXELS, + CCDC_SAMPLE_8PIXELS, + CCDC_SAMPLE_16PIXELS +}; + +/* enum for No of lines in Black Clamping */ +enum ccdc_sample_line { + CCDC_SAMPLE_1LINES, + CCDC_SAMPLE_2LINES, + CCDC_SAMPLE_4LINES, + CCDC_SAMPLE_8LINES, + CCDC_SAMPLE_16LINES +}; + +/* enum for Alaw gama width */ +enum ccdc_gama_width { + CCDC_GAMMA_BITS_15_6, + CCDC_GAMMA_BITS_14_5, + CCDC_GAMMA_BITS_13_4, + CCDC_GAMMA_BITS_12_3, + CCDC_GAMMA_BITS_11_2, + CCDC_GAMMA_BITS_10_1, + CCDC_GAMMA_BITS_09_0 +}; + +enum ccdc_data_size { + CCDC_DATA_16BITS, + CCDC_DATA_15BITS, + CCDC_DATA_14BITS, + CCDC_DATA_13BITS, + CCDC_DATA_12BITS, + CCDC_DATA_11BITS, + CCDC_DATA_10BITS, + CCDC_DATA_8BITS +}; + +/* structure for ALaw */ +struct ccdc_a_law { + /* Enable/disable A-Law */ + unsigned char enable; + /* Gama Width Input */ + enum ccdc_gama_width gama_wd; +}; + +/* structure for Black Clamping */ +struct ccdc_black_clamp { + unsigned char enable; + /* only if bClampEnable is TRUE */ + enum ccdc_sample_length sample_pixel; + /* only if bClampEnable is TRUE */ + enum ccdc_sample_line sample_ln; + /* only if bClampEnable is TRUE */ + unsigned short start_pixel; + /* only if bClampEnable is TRUE */ + unsigned short sgain; + /* only if bClampEnable is FALSE */ + unsigned short dc_sub; +}; + +/* structure for Black Level Compensation */ +struct ccdc_black_compensation { + /* Constant value to subtract from Red component */ + char r; + /* Constant value to subtract from Gr component */ + char gr; + /* Constant value to subtract from Blue component */ + char b; + /* Constant value to subtract from Gb component */ + char gb; +}; + +/* structure for fault pixel correction */ +struct ccdc_fault_pixel { + /* Enable or Disable fault pixel correction */ + unsigned char enable; + /* Number of fault pixel */ + unsigned short fp_num; + /* Address of fault pixel table */ + unsigned int fpc_table_addr; +}; + +/* Structure for CCDC configuration parameters for raw capture mode passed + * by application + */ +struct ccdc_config_params_raw { + /* data size value from 8 to 16 bits */ + enum ccdc_data_size data_sz; + /* Structure for Optional A-Law */ + struct ccdc_a_law alaw; + /* Structure for Optical Black Clamp */ + struct ccdc_black_clamp blk_clamp; + /* Structure for Black Compensation */ + struct ccdc_black_compensation blk_comp; + /* Structure for Fault Pixel Module Configuration */ + struct ccdc_fault_pixel fault_pxl; +}; + + +#ifdef __KERNEL__ +#include +/* Define to enable/disable video port */ +#define FP_NUM_BYTES 4 +/* Define for extra pixel/line and extra lines/frame */ +#define NUM_EXTRAPIXELS 8 +#define NUM_EXTRALINES 8 + +/* settings for commonly used video formats */ +#define CCDC_WIN_PAL {0, 0, 720, 576} +/* ntsc square pixel */ +#define CCDC_WIN_VGA {0, 0, (640 + NUM_EXTRAPIXELS), (480 + NUM_EXTRALINES)} + +/* Structure for CCDC configuration parameters for raw capture mode */ +struct ccdc_params_raw { + /* pixel format */ + enum ccdc_pixfmt pix_fmt; + /* progressive or interlaced frame */ + enum ccdc_frmfmt frm_fmt; + /* video window */ + struct v4l2_rect win; + /* field id polarity */ + enum vpfe_pin_pol fid_pol; + /* vertical sync polarity */ + enum vpfe_pin_pol vd_pol; + /* horizontal sync polarity */ + enum vpfe_pin_pol hd_pol; + /* interleaved or separated fields */ + enum ccdc_buftype buf_type; + /* + * enable to store the image in inverse + * order in memory(bottom to top) + */ + unsigned char image_invert_enable; + /* configurable paramaters */ + struct ccdc_config_params_raw config_params; +}; + +struct ccdc_params_ycbcr { + /* pixel format */ + enum ccdc_pixfmt pix_fmt; + /* progressive or interlaced frame */ + enum ccdc_frmfmt frm_fmt; + /* video window */ + struct v4l2_rect win; + /* field id polarity */ + enum vpfe_pin_pol fid_pol; + /* vertical sync polarity */ + enum vpfe_pin_pol vd_pol; + /* horizontal sync polarity */ + enum vpfe_pin_pol hd_pol; + /* enable BT.656 embedded sync mode */ + int bt656_enable; + /* cb:y:cr:y or y:cb:y:cr in memory */ + enum ccdc_pixorder pix_order; + /* interleaved or separated fields */ + enum ccdc_buftype buf_type; +}; +#endif +#endif /* _DM644X_CCDC_H */ diff --git a/include/media/davinci/vpfe_capture.h b/include/media/davinci/vpfe_capture.h new file mode 100644 index 000000000000..71d8982e13ff --- /dev/null +++ b/include/media/davinci/vpfe_capture.h @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2008-2009 Texas Instruments Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _VPFE_CAPTURE_H +#define _VPFE_CAPTURE_H + +#ifdef __KERNEL__ + +/* Header files */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define VPFE_CAPTURE_NUM_DECODERS 5 + +/* Macros */ +#define VPFE_MAJOR_RELEASE 0 +#define VPFE_MINOR_RELEASE 0 +#define VPFE_BUILD 1 +#define VPFE_CAPTURE_VERSION_CODE ((VPFE_MAJOR_RELEASE << 16) | \ + (VPFE_MINOR_RELEASE << 8) | \ + VPFE_BUILD) + +#define CAPTURE_DRV_NAME "vpfe-capture" + +struct vpfe_pixel_format { + struct v4l2_fmtdesc fmtdesc; + /* bytes per pixel */ + int bpp; +}; + +struct vpfe_std_info { + int active_pixels; + int active_lines; + /* current frame format */ + int frame_format; +}; + +struct vpfe_route { + u32 input; + u32 output; +}; + +struct vpfe_subdev_info { + /* Sub device name */ + char name[32]; + /* Sub device group id */ + int grp_id; + /* Number of inputs supported */ + int num_inputs; + /* inputs available at the sub device */ + struct v4l2_input *inputs; + /* Sub dev routing information for each input */ + struct vpfe_route *routes; + /* check if sub dev supports routing */ + int can_route; + /* ccdc bus/interface configuration */ + struct vpfe_hw_if_param ccdc_if_params; + /* i2c subdevice board info */ + struct i2c_board_info board_info; +}; + +struct vpfe_config { + /* Number of sub devices connected to vpfe */ + int num_subdevs; + /* information about each subdev */ + struct vpfe_subdev_info *sub_devs; + /* evm card info */ + char *card_name; + /* ccdc name */ + char *ccdc; + /* vpfe clock */ + struct clk *vpssclk; + struct clk *slaveclk; +}; + +struct vpfe_device { + /* V4l2 specific parameters */ + /* Identifies video device for this channel */ + struct video_device *video_dev; + /* sub devices */ + struct v4l2_subdev **sd; + /* vpfe cfg */ + struct vpfe_config *cfg; + /* V4l2 device */ + struct v4l2_device v4l2_dev; + /* parent device */ + struct device *pdev; + /* Used to keep track of state of the priority */ + struct v4l2_prio_state prio; + /* number of open instances of the channel */ + u32 usrs; + /* Indicates id of the field which is being displayed */ + u32 field_id; + /* flag to indicate whether decoder is initialized */ + u8 initialized; + /* current interface type */ + struct vpfe_hw_if_param vpfe_if_params; + /* ptr to currently selected sub device */ + struct vpfe_subdev_info *current_subdev; + /* current input at the sub device */ + int current_input; + /* Keeps track of the information about the standard */ + struct vpfe_std_info std_info; + /* std index into std table */ + int std_index; + /* CCDC IRQs used when CCDC/ISIF output to SDRAM */ + unsigned int ccdc_irq0; + unsigned int ccdc_irq1; + /* number of buffers in fbuffers */ + u32 numbuffers; + /* List of buffer pointers for storing frames */ + u8 *fbuffers[VIDEO_MAX_FRAME]; + /* Pointer pointing to current v4l2_buffer */ + struct videobuf_buffer *cur_frm; + /* Pointer pointing to next v4l2_buffer */ + struct videobuf_buffer *next_frm; + /* + * This field keeps track of type of buffer exchange mechanism + * user has selected + */ + enum v4l2_memory memory; + /* Used to store pixel format */ + struct v4l2_format fmt; + /* + * used when IMP is chained to store the crop window which + * is different from the image window + */ + struct v4l2_rect crop; + /* Buffer queue used in video-buf */ + struct videobuf_queue buffer_queue; + /* Queue of filled frames */ + struct list_head dma_queue; + /* Used in video-buf */ + spinlock_t irqlock; + /* IRQ lock for DMA queue */ + spinlock_t dma_queue_lock; + /* lock used to access this structure */ + struct mutex lock; + /* number of users performing IO */ + u32 io_usrs; + /* Indicates whether streaming started */ + u8 started; + /* + * offset where second field starts from the starting of the + * buffer for field seperated YCbCr formats + */ + u32 field_off; +}; + +/* File handle structure */ +struct vpfe_fh { + struct vpfe_device *vpfe_dev; + /* Indicates whether this file handle is doing IO */ + u8 io_allowed; + /* Used to keep track priority of this instance */ + enum v4l2_priority prio; +}; + +struct vpfe_config_params { + u8 min_numbuffers; + u8 numbuffers; + u32 min_bufsize; + u32 device_bufsize; +}; + +#endif /* End of __KERNEL__ */ +/** + * VPFE_CMD_S_CCDC_RAW_PARAMS - EXPERIMENTAL IOCTL to set raw capture params + * This can be used to configure modules such as defect pixel correction, + * color space conversion, culling etc. This is an experimental ioctl that + * will change in future kernels. So use this ioctl with care ! + * TODO: This is to be split into multiple ioctls and also explore the + * possibility of extending the v4l2 api to include this + **/ +#define VPFE_CMD_S_CCDC_RAW_PARAMS _IOW('V', BASE_VIDIOC_PRIVATE + 1, \ + void *) +#endif /* _DAVINCI_VPFE_H */ diff --git a/include/media/davinci/vpfe_types.h b/include/media/davinci/vpfe_types.h new file mode 100644 index 000000000000..76fb74bad08c --- /dev/null +++ b/include/media/davinci/vpfe_types.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2008-2009 Texas Instruments Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option)any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _VPFE_TYPES_H +#define _VPFE_TYPES_H + +#ifdef __KERNEL__ + +enum vpfe_pin_pol { + VPFE_PINPOL_POSITIVE, + VPFE_PINPOL_NEGATIVE +}; + +enum vpfe_hw_if_type { + /* BT656 - 8 bit */ + VPFE_BT656, + /* BT1120 - 16 bit */ + VPFE_BT1120, + /* Raw Bayer */ + VPFE_RAW_BAYER, + /* YCbCr - 8 bit with external sync */ + VPFE_YCBCR_SYNC_8, + /* YCbCr - 16 bit with external sync */ + VPFE_YCBCR_SYNC_16, + /* BT656 - 10 bit */ + VPFE_BT656_10BIT +}; + +/* interface description */ +struct vpfe_hw_if_param { + enum vpfe_hw_if_type if_type; + enum vpfe_pin_pol hdpol; + enum vpfe_pin_pol vdpol; +}; + +#endif +#endif diff --git a/include/media/davinci/vpss.h b/include/media/davinci/vpss.h new file mode 100644 index 000000000000..fcdff745fae2 --- /dev/null +++ b/include/media/davinci/vpss.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2009 Texas Instruments Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * vpss - video processing subsystem module header file. + * + * Include this header file if a driver needs to configure vpss system + * module. It exports a set of library functions for video drivers to + * configure vpss system module functions such as clock enable/disable, + * vpss interrupt mux to arm, and other common vpss system module + * functions. + */ +#ifndef _VPSS_H +#define _VPSS_H + +/* selector for ccdc input selection on DM355 */ +enum vpss_ccdc_source_sel { + VPSS_CCDCIN, + VPSS_HSSIIN +}; + +/* Used for enable/diable VPSS Clock */ +enum vpss_clock_sel { + /* DM355/DM365 */ + VPSS_CCDC_CLOCK, + VPSS_IPIPE_CLOCK, + VPSS_H3A_CLOCK, + VPSS_CFALD_CLOCK, + /* + * When using VPSS_VENC_CLOCK_SEL in vpss_enable_clock() api + * following applies:- + * en = 0 selects ENC_CLK + * en = 1 selects ENC_CLK/2 + */ + VPSS_VENC_CLOCK_SEL, + VPSS_VPBE_CLOCK, +}; + +/* select input to ccdc on dm355 */ +int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel); +/* enable/disable a vpss clock, 0 - success, -1 - failure */ +int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en); + +/* wbl reset for dm644x */ +enum vpss_wbl_sel { + VPSS_PCR_AEW_WBL_0 = 16, + VPSS_PCR_AF_WBL_0, + VPSS_PCR_RSZ4_WBL_0, + VPSS_PCR_RSZ3_WBL_0, + VPSS_PCR_RSZ2_WBL_0, + VPSS_PCR_RSZ1_WBL_0, + VPSS_PCR_PREV_WBL_0, + VPSS_PCR_CCDC_WBL_O, +}; +int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel); +#endif diff --git a/include/media/soc_camera.h b/include/media/soc_camera.h index 23ecead35e7a..3d74e60032dd 100644 --- a/include/media/soc_camera.h +++ b/include/media/soc_camera.h @@ -16,24 +16,17 @@ #include #include #include +#include struct soc_camera_device { struct list_head list; struct device dev; - struct device *control; - unsigned short width; /* Current window */ - unsigned short height; /* sizes */ - unsigned short x_min; /* Camera capabilities */ - unsigned short y_min; - unsigned short x_current; /* Current window location */ - unsigned short y_current; + struct device *pdev; /* Platform device */ + s32 user_width; + s32 user_height; unsigned short width_min; - unsigned short width_max; unsigned short height_min; - unsigned short height_max; unsigned short y_skip_top; /* Lines to skip at the top */ - unsigned short gain; - unsigned short exposure; unsigned char iface; /* Host number */ unsigned char devnum; /* Device number per host */ unsigned char buswidth; /* See comment in .c */ @@ -46,7 +39,6 @@ struct soc_camera_device { struct soc_camera_format_xlate *user_formats; int num_user_formats; enum v4l2_field field; /* Preserve field over close() */ - struct module *owner; void *host_priv; /* Per-device host private data */ /* soc_camera.c private count. Only accessed with .video_lock held */ int use_count; @@ -59,8 +51,8 @@ struct soc_camera_file { }; struct soc_camera_host { + struct v4l2_device v4l2_dev; struct list_head list; - struct device *dev; unsigned char nr; /* Host number */ void *priv; const char *drv_name; @@ -73,9 +65,18 @@ struct soc_camera_host_ops { void (*remove)(struct soc_camera_device *); int (*suspend)(struct soc_camera_device *, pm_message_t); int (*resume)(struct soc_camera_device *); + /* + * .get_formats() is called for each client device format, but + * .put_formats() is only called once. Further, if any of the calls to + * .get_formats() fail, .put_formats() will not be called at all, the + * failing .get_formats() must then clean up internally. + */ int (*get_formats)(struct soc_camera_device *, int, struct soc_camera_format_xlate *); - int (*set_crop)(struct soc_camera_device *, struct v4l2_rect *); + void (*put_formats)(struct soc_camera_device *); + int (*cropcap)(struct soc_camera_device *, struct v4l2_cropcap *); + int (*get_crop)(struct soc_camera_device *, struct v4l2_crop *); + int (*set_crop)(struct soc_camera_device *, struct v4l2_crop *); int (*set_fmt)(struct soc_camera_device *, struct v4l2_format *); int (*try_fmt)(struct soc_camera_device *, struct v4l2_format *); void (*init_videobuf)(struct videobuf_queue *, @@ -83,7 +84,11 @@ struct soc_camera_host_ops { int (*reqbufs)(struct soc_camera_file *, struct v4l2_requestbuffers *); int (*querycap)(struct soc_camera_host *, struct v4l2_capability *); int (*set_bus_param)(struct soc_camera_device *, __u32); + int (*get_ctrl)(struct soc_camera_device *, struct v4l2_control *); + int (*set_ctrl)(struct soc_camera_device *, struct v4l2_control *); unsigned int (*poll)(struct file *, poll_table *); + const struct v4l2_queryctrl *controls; + int num_controls; }; #define SOCAM_SENSOR_INVERT_PCLK (1 << 0) @@ -102,6 +107,12 @@ struct soc_camera_link { int i2c_adapter_id; struct i2c_board_info *board_info; const char *module_name; + /* + * For non-I2C devices platform platform has to provide methods to + * add a device to the system and to remove + */ + int (*add_device)(struct soc_camera_link *, struct device *); + void (*del_device)(struct soc_camera_link *); /* Optional callbacks to power on or off and reset the sensor */ int (*power)(struct device *, int); int (*reset)(struct device *); @@ -115,27 +126,45 @@ struct soc_camera_link { void (*free_bus)(struct soc_camera_link *); }; -static inline struct soc_camera_device *to_soc_camera_dev(struct device *dev) +static inline struct soc_camera_device *to_soc_camera_dev( + const struct device *dev) { return container_of(dev, struct soc_camera_device, dev); } -static inline struct soc_camera_host *to_soc_camera_host(struct device *dev) +static inline struct soc_camera_host *to_soc_camera_host( + const struct device *dev) { - return dev_get_drvdata(dev); + struct v4l2_device *v4l2_dev = dev_get_drvdata(dev); + + return container_of(v4l2_dev, struct soc_camera_host, v4l2_dev); } -extern int soc_camera_host_register(struct soc_camera_host *ici); -extern void soc_camera_host_unregister(struct soc_camera_host *ici); -extern int soc_camera_device_register(struct soc_camera_device *icd); -extern void soc_camera_device_unregister(struct soc_camera_device *icd); +static inline struct soc_camera_link *to_soc_camera_link( + const struct soc_camera_device *icd) +{ + return icd->dev.platform_data; +} -extern int soc_camera_video_start(struct soc_camera_device *icd); -extern void soc_camera_video_stop(struct soc_camera_device *icd); +static inline struct device *to_soc_camera_control( + const struct soc_camera_device *icd) +{ + return dev_get_drvdata(&icd->dev); +} -extern const struct soc_camera_data_format *soc_camera_format_by_fourcc( +static inline struct v4l2_subdev *soc_camera_to_subdev( + const struct soc_camera_device *icd) +{ + struct device *control = to_soc_camera_control(icd); + return dev_get_drvdata(control); +} + +int soc_camera_host_register(struct soc_camera_host *ici); +void soc_camera_host_unregister(struct soc_camera_host *ici); + +const struct soc_camera_data_format *soc_camera_format_by_fourcc( struct soc_camera_device *icd, unsigned int fourcc); -extern const struct soc_camera_format_xlate *soc_camera_xlate_by_fourcc( +const struct soc_camera_format_xlate *soc_camera_xlate_by_fourcc( struct soc_camera_device *icd, unsigned int fourcc); struct soc_camera_data_format { @@ -163,30 +192,11 @@ struct soc_camera_format_xlate { }; struct soc_camera_ops { - struct module *owner; - int (*probe)(struct soc_camera_device *); - void (*remove)(struct soc_camera_device *); int (*suspend)(struct soc_camera_device *, pm_message_t state); int (*resume)(struct soc_camera_device *); - int (*init)(struct soc_camera_device *); - int (*release)(struct soc_camera_device *); - int (*start_capture)(struct soc_camera_device *); - int (*stop_capture)(struct soc_camera_device *); - int (*set_crop)(struct soc_camera_device *, struct v4l2_rect *); - int (*set_fmt)(struct soc_camera_device *, struct v4l2_format *); - int (*try_fmt)(struct soc_camera_device *, struct v4l2_format *); unsigned long (*query_bus_param)(struct soc_camera_device *); int (*set_bus_param)(struct soc_camera_device *, unsigned long); - int (*get_chip_id)(struct soc_camera_device *, - struct v4l2_dbg_chip_ident *); - int (*set_std)(struct soc_camera_device *, v4l2_std_id *); int (*enum_input)(struct soc_camera_device *, struct v4l2_input *); -#ifdef CONFIG_VIDEO_ADV_DEBUG - int (*get_register)(struct soc_camera_device *, struct v4l2_dbg_register *); - int (*set_register)(struct soc_camera_device *, struct v4l2_dbg_register *); -#endif - int (*get_control)(struct soc_camera_device *, struct v4l2_control *); - int (*set_control)(struct soc_camera_device *, struct v4l2_control *); const struct v4l2_queryctrl *controls; int num_controls; }; @@ -268,6 +278,21 @@ static inline unsigned long soc_camera_bus_param_compatible( common_flags; } +static inline void soc_camera_limit_side(unsigned int *start, + unsigned int *length, unsigned int start_min, + unsigned int length_min, unsigned int length_max) +{ + if (*length < length_min) + *length = length_min; + else if (*length > length_max) + *length = length_max; + + if (*start < start_min) + *start = start_min; + else if (*start > start_min + length_max - *length) + *start = start_min + length_max - *length; +} + extern unsigned long soc_camera_apply_sensor_flags(struct soc_camera_link *icl, unsigned long flags); diff --git a/include/media/soc_camera_platform.h b/include/media/soc_camera_platform.h index 1d092b4678aa..bb70401b8141 100644 --- a/include/media/soc_camera_platform.h +++ b/include/media/soc_camera_platform.h @@ -12,15 +12,18 @@ #define __SOC_CAMERA_H__ #include +#include + +struct device; struct soc_camera_platform_info { - int iface; - char *format_name; + const char *format_name; unsigned long format_depth; struct v4l2_pix_format format; unsigned long bus_param; - void (*power)(int); + struct device *dev; int (*set_capture)(struct soc_camera_platform_info *info, int enable); + struct soc_camera_link link; }; #endif /* __SOC_CAMERA_H__ */ diff --git a/include/media/tuner.h b/include/media/tuner.h index c146f2f530b0..4d5b53ff17db 100644 --- a/include/media/tuner.h +++ b/include/media/tuner.h @@ -127,6 +127,8 @@ #define TUNER_PHILIPS_FM1216MK5 79 #define TUNER_PHILIPS_FQ1216LME_MK3 80 /* Active loopthrough, no FM */ #define TUNER_PARTSNIC_PTI_5NF05 81 +#define TUNER_PHILIPS_CU1216L 82 +#define TUNER_NXP_TDA18271 83 /* tv card specific */ #define TDA9887_PRESENT (1<<0) diff --git a/include/media/tvp514x.h b/include/media/tvp514x.h index 5e7ee968c6dc..74387e83f5b9 100644 --- a/include/media/tvp514x.h +++ b/include/media/tvp514x.h @@ -104,10 +104,6 @@ enum tvp514x_output { * @ vs_polarity: VSYNC Polarity configuration for current interface. */ struct tvp514x_platform_data { - char *master; - int (*power_set) (enum v4l2_power on); - int (*ifparm) (struct v4l2_ifparm *p); - int (*priv_data_set) (void *); /* Interface control params */ bool clk_polarity; bool hs_polarity; diff --git a/include/media/v4l2-chip-ident.h b/include/media/v4l2-chip-ident.h index 94e908c0d7a0..cf16689adba7 100644 --- a/include/media/v4l2-chip-ident.h +++ b/include/media/v4l2-chip-ident.h @@ -135,6 +135,9 @@ enum { /* module adv7175: just ident 7175 */ V4L2_IDENT_ADV7175 = 7175, + /* module adv7180: just ident 7180 */ + V4L2_IDENT_ADV7180 = 7180, + /* module saa7185: just ident 7185 */ V4L2_IDENT_SAA7185 = 7185, diff --git a/include/media/v4l2-common.h b/include/media/v4l2-common.h index 33a18426ab9b..1c25b10da34b 100644 --- a/include/media/v4l2-common.h +++ b/include/media/v4l2-common.h @@ -139,29 +139,23 @@ struct v4l2_subdev_ops; /* Load an i2c module and return an initialized v4l2_subdev struct. Only call request_module if module_name != NULL. The client_type argument is the name of the chip that's on the adapter. */ -struct v4l2_subdev *v4l2_i2c_new_subdev(struct v4l2_device *v4l2_dev, - struct i2c_adapter *adapter, - const char *module_name, const char *client_type, u8 addr); -/* Probe and load an i2c module and return an initialized v4l2_subdev struct. - Only call request_module if module_name != NULL. - The client_type argument is the name of the chip that's on the adapter. */ -struct v4l2_subdev *v4l2_i2c_new_probed_subdev(struct v4l2_device *v4l2_dev, +struct v4l2_subdev *v4l2_i2c_new_subdev_cfg(struct v4l2_device *v4l2_dev, struct i2c_adapter *adapter, const char *module_name, const char *client_type, - const unsigned short *addrs); -/* Like v4l2_i2c_new_probed_subdev, except probe for a single address. */ -struct v4l2_subdev *v4l2_i2c_new_probed_subdev_addr(struct v4l2_device *v4l2_dev, - struct i2c_adapter *adapter, - const char *module_name, const char *client_type, u8 addr); + int irq, void *platform_data, + u8 addr, const unsigned short *probe_addrs); /* Load an i2c module and return an initialized v4l2_subdev struct. Only call request_module if module_name != NULL. The client_type argument is the name of the chip that's on the adapter. */ -struct v4l2_subdev *v4l2_i2c_new_subdev_cfg(struct v4l2_device *v4l2_dev, +static inline struct v4l2_subdev *v4l2_i2c_new_subdev(struct v4l2_device *v4l2_dev, struct i2c_adapter *adapter, const char *module_name, const char *client_type, - int irq, void *platform_data, - u8 addr, const unsigned short *probe_addrs); + u8 addr, const unsigned short *probe_addrs) +{ + return v4l2_i2c_new_subdev_cfg(v4l2_dev, adapter, module_name, + client_type, 0, NULL, addr, probe_addrs); +} struct i2c_board_info; diff --git a/include/media/v4l2-dev.h b/include/media/v4l2-dev.h index 2058dd45e915..73c9867d744c 100644 --- a/include/media/v4l2-dev.h +++ b/include/media/v4l2-dev.h @@ -100,8 +100,10 @@ struct video_device Also note that vdev->minor is set to -1 if the registration failed. */ int __must_check video_register_device(struct video_device *vdev, int type, int nr); -int __must_check video_register_device_index(struct video_device *vdev, - int type, int nr, int index); + +/* Same as video_register_device, but no warning is issued if the desired + device node number was already in use. */ +int __must_check video_register_device_no_warn(struct video_device *vdev, int type, int nr); /* Unregister video devices. Will do nothing if vdev == NULL or vdev->minor < 0. */ diff --git a/include/trace/ftrace.h b/include/trace/ftrace.h index ec91e78244f0..cc0d9667e182 100644 --- a/include/trace/ftrace.h +++ b/include/trace/ftrace.h @@ -382,20 +382,14 @@ static inline int ftrace_get_offsets_##call( \ * * NOTE: The insertion profile callback (ftrace_profile_) is defined later * - * static int ftrace_profile_enable_(struct ftrace_event_call *event_call) + * static int ftrace_profile_enable_(void) * { - * int ret = 0; - * - * if (!atomic_inc_return(&event_call->profile_count)) - * ret = register_trace_(ftrace_profile_); - * - * return ret; + * return register_trace_(ftrace_profile_); * } * - * static void ftrace_profile_disable_(struct ftrace_event_call *event_call) + * static void ftrace_profile_disable_(void) * { - * if (atomic_add_negative(-1, &event->call->profile_count)) - * unregister_trace_(ftrace_profile_); + * unregister_trace_(ftrace_profile_); * } * */ @@ -405,20 +399,14 @@ static inline int ftrace_get_offsets_##call( \ \ static void ftrace_profile_##call(proto); \ \ -static int ftrace_profile_enable_##call(struct ftrace_event_call *event_call) \ +static int ftrace_profile_enable_##call(void) \ { \ - int ret = 0; \ - \ - if (!atomic_inc_return(&event_call->profile_count)) \ - ret = register_trace_##call(ftrace_profile_##call); \ - \ - return ret; \ + return register_trace_##call(ftrace_profile_##call); \ } \ \ -static void ftrace_profile_disable_##call(struct ftrace_event_call *event_call)\ +static void ftrace_profile_disable_##call(void) \ { \ - if (atomic_add_negative(-1, &event_call->profile_count)) \ - unregister_trace_##call(ftrace_profile_##call); \ + unregister_trace_##call(ftrace_profile_##call); \ } #include TRACE_INCLUDE(TRACE_INCLUDE_FILE) @@ -660,11 +648,12 @@ __attribute__((section("_ftrace_events"))) event_##call = { \ * struct ftrace_raw_##call *entry; * u64 __addr = 0, __count = 1; * unsigned long irq_flags; + * struct trace_entry *ent; * int __entry_size; * int __data_size; + * int __cpu * int pc; * - * local_save_flags(irq_flags); * pc = preempt_count(); * * __data_size = ftrace_get_offsets_(&__data_offsets, args); @@ -675,25 +664,34 @@ __attribute__((section("_ftrace_events"))) event_##call = { \ * sizeof(u64)); * __entry_size -= sizeof(u32); * - * do { - * char raw_data[__entry_size]; <- allocate our sample in the stack - * struct trace_entry *ent; + * // Protect the non nmi buffer + * // This also protects the rcu read side + * local_irq_save(irq_flags); + * __cpu = smp_processor_id(); + * + * if (in_nmi()) + * raw_data = rcu_dereference(trace_profile_buf_nmi); + * else + * raw_data = rcu_dereference(trace_profile_buf); + * + * if (!raw_data) + * goto end; * - * zero dead bytes from alignment to avoid stack leak to userspace: + * raw_data = per_cpu_ptr(raw_data, __cpu); * - * *(u64 *)(&raw_data[__entry_size - sizeof(u64)]) = 0ULL; - * entry = (struct ftrace_raw_ *)raw_data; - * ent = &entry->ent; - * tracing_generic_entry_update(ent, irq_flags, pc); - * ent->type = event_call->id; + * //zero dead bytes from alignment to avoid stack leak to userspace: + * *(u64 *)(&raw_data[__entry_size - sizeof(u64)]) = 0ULL; + * entry = (struct ftrace_raw_ *)raw_data; + * ent = &entry->ent; + * tracing_generic_entry_update(ent, irq_flags, pc); + * ent->type = event_call->id; * - * <- do some jobs with dynamic arrays + * <- do some jobs with dynamic arrays * - * <- affect our values + * <- affect our values * - * perf_tp_event(event_call->id, __addr, __count, entry, - * __entry_size); <- submit them to perf counter - * } while (0); + * perf_tp_event(event_call->id, __addr, __count, entry, + * __entry_size); <- submit them to perf counter * * } */ @@ -716,11 +714,13 @@ static void ftrace_profile_##call(proto) \ struct ftrace_raw_##call *entry; \ u64 __addr = 0, __count = 1; \ unsigned long irq_flags; \ + struct trace_entry *ent; \ int __entry_size; \ int __data_size; \ + char *raw_data; \ + int __cpu; \ int pc; \ \ - local_save_flags(irq_flags); \ pc = preempt_count(); \ \ __data_size = ftrace_get_offsets_##call(&__data_offsets, args); \ @@ -728,23 +728,38 @@ static void ftrace_profile_##call(proto) \ sizeof(u64)); \ __entry_size -= sizeof(u32); \ \ - do { \ - char raw_data[__entry_size]; \ - struct trace_entry *ent; \ + if (WARN_ONCE(__entry_size > FTRACE_MAX_PROFILE_SIZE, \ + "profile buffer not large enough")) \ + return; \ + \ + local_irq_save(irq_flags); \ + __cpu = smp_processor_id(); \ \ - *(u64 *)(&raw_data[__entry_size - sizeof(u64)]) = 0ULL; \ - entry = (struct ftrace_raw_##call *)raw_data; \ - ent = &entry->ent; \ - tracing_generic_entry_update(ent, irq_flags, pc); \ - ent->type = event_call->id; \ + if (in_nmi()) \ + raw_data = rcu_dereference(trace_profile_buf_nmi); \ + else \ + raw_data = rcu_dereference(trace_profile_buf); \ \ - tstruct \ + if (!raw_data) \ + goto end; \ \ - { assign; } \ + raw_data = per_cpu_ptr(raw_data, __cpu); \ \ - perf_tp_event(event_call->id, __addr, __count, entry,\ + *(u64 *)(&raw_data[__entry_size - sizeof(u64)]) = 0ULL; \ + entry = (struct ftrace_raw_##call *)raw_data; \ + ent = &entry->ent; \ + tracing_generic_entry_update(ent, irq_flags, pc); \ + ent->type = event_call->id; \ + \ + tstruct \ + \ + { assign; } \ + \ + perf_tp_event(event_call->id, __addr, __count, entry, \ __entry_size); \ - } while (0); \ + \ +end: \ + local_irq_restore(irq_flags); \ \ } diff --git a/init/Kconfig b/init/Kconfig index 706728be312f..0aa6579504cc 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -331,7 +331,8 @@ config TREE_PREEMPT_RCU This option selects the RCU implementation that is designed for very large SMP systems with hundreds or thousands of CPUs, but for which real-time response - is also required. + is also required. It also scales down nicely to + smaller systems. endchoice @@ -1071,13 +1072,6 @@ config PROFILING config TRACEPOINTS bool -config MARKERS - bool "Activate markers" - select TRACEPOINTS - help - Place an empty function call at each marker site. Can be - dynamically changed for a probe function. - source "arch/Kconfig" config SLOW_WORK diff --git a/kernel/Makefile b/kernel/Makefile index e26a546eac44..187c89b4783d 100644 --- a/kernel/Makefile +++ b/kernel/Makefile @@ -87,7 +87,6 @@ obj-$(CONFIG_RELAY) += relay.o obj-$(CONFIG_SYSCTL) += utsname_sysctl.o obj-$(CONFIG_TASK_DELAY_ACCT) += delayacct.o obj-$(CONFIG_TASKSTATS) += taskstats.o tsacct.o -obj-$(CONFIG_MARKERS) += marker.o obj-$(CONFIG_TRACEPOINTS) += tracepoint.o obj-$(CONFIG_LATENCYTOP) += latencytop.o obj-$(CONFIG_FUNCTION_TRACER) += trace/ diff --git a/kernel/marker.c b/kernel/marker.c deleted file mode 100644 index ea54f2647868..000000000000 --- a/kernel/marker.c +++ /dev/null @@ -1,930 +0,0 @@ -/* - * Copyright (C) 2007 Mathieu Desnoyers - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern struct marker __start___markers[]; -extern struct marker __stop___markers[]; - -/* Set to 1 to enable marker debug output */ -static const int marker_debug; - -/* - * markers_mutex nests inside module_mutex. Markers mutex protects the builtin - * and module markers and the hash table. - */ -static DEFINE_MUTEX(markers_mutex); - -/* - * Marker hash table, containing the active markers. - * Protected by module_mutex. - */ -#define MARKER_HASH_BITS 6 -#define MARKER_TABLE_SIZE (1 << MARKER_HASH_BITS) -static struct hlist_head marker_table[MARKER_TABLE_SIZE]; - -/* - * Note about RCU : - * It is used to make sure every handler has finished using its private data - * between two consecutive operation (add or remove) on a given marker. It is - * also used to delay the free of multiple probes array until a quiescent state - * is reached. - * marker entries modifications are protected by the markers_mutex. - */ -struct marker_entry { - struct hlist_node hlist; - char *format; - /* Probe wrapper */ - void (*call)(const struct marker *mdata, void *call_private, ...); - struct marker_probe_closure single; - struct marker_probe_closure *multi; - int refcount; /* Number of times armed. 0 if disarmed. */ - struct rcu_head rcu; - void *oldptr; - int rcu_pending; - unsigned char ptype:1; - unsigned char format_allocated:1; - char name[0]; /* Contains name'\0'format'\0' */ -}; - -/** - * __mark_empty_function - Empty probe callback - * @probe_private: probe private data - * @call_private: call site private data - * @fmt: format string - * @...: variable argument list - * - * Empty callback provided as a probe to the markers. By providing this to a - * disabled marker, we make sure the execution flow is always valid even - * though the function pointer change and the marker enabling are two distinct - * operations that modifies the execution flow of preemptible code. - */ -notrace void __mark_empty_function(void *probe_private, void *call_private, - const char *fmt, va_list *args) -{ -} -EXPORT_SYMBOL_GPL(__mark_empty_function); - -/* - * marker_probe_cb Callback that prepares the variable argument list for probes. - * @mdata: pointer of type struct marker - * @call_private: caller site private data - * @...: Variable argument list. - * - * Since we do not use "typical" pointer based RCU in the 1 argument case, we - * need to put a full smp_rmb() in this branch. This is why we do not use - * rcu_dereference() for the pointer read. - */ -notrace void marker_probe_cb(const struct marker *mdata, - void *call_private, ...) -{ - va_list args; - char ptype; - - /* - * rcu_read_lock_sched does two things : disabling preemption to make - * sure the teardown of the callbacks can be done correctly when they - * are in modules and they insure RCU read coherency. - */ - rcu_read_lock_sched_notrace(); - ptype = mdata->ptype; - if (likely(!ptype)) { - marker_probe_func *func; - /* Must read the ptype before ptr. They are not data dependant, - * so we put an explicit smp_rmb() here. */ - smp_rmb(); - func = mdata->single.func; - /* Must read the ptr before private data. They are not data - * dependant, so we put an explicit smp_rmb() here. */ - smp_rmb(); - va_start(args, call_private); - func(mdata->single.probe_private, call_private, mdata->format, - &args); - va_end(args); - } else { - struct marker_probe_closure *multi; - int i; - /* - * Read mdata->ptype before mdata->multi. - */ - smp_rmb(); - multi = mdata->multi; - /* - * multi points to an array, therefore accessing the array - * depends on reading multi. However, even in this case, - * we must insure that the pointer is read _before_ the array - * data. Same as rcu_dereference, but we need a full smp_rmb() - * in the fast path, so put the explicit barrier here. - */ - smp_read_barrier_depends(); - for (i = 0; multi[i].func; i++) { - va_start(args, call_private); - multi[i].func(multi[i].probe_private, call_private, - mdata->format, &args); - va_end(args); - } - } - rcu_read_unlock_sched_notrace(); -} -EXPORT_SYMBOL_GPL(marker_probe_cb); - -/* - * marker_probe_cb Callback that does not prepare the variable argument list. - * @mdata: pointer of type struct marker - * @call_private: caller site private data - * @...: Variable argument list. - * - * Should be connected to markers "MARK_NOARGS". - */ -static notrace void marker_probe_cb_noarg(const struct marker *mdata, - void *call_private, ...) -{ - va_list args; /* not initialized */ - char ptype; - - rcu_read_lock_sched_notrace(); - ptype = mdata->ptype; - if (likely(!ptype)) { - marker_probe_func *func; - /* Must read the ptype before ptr. They are not data dependant, - * so we put an explicit smp_rmb() here. */ - smp_rmb(); - func = mdata->single.func; - /* Must read the ptr before private data. They are not data - * dependant, so we put an explicit smp_rmb() here. */ - smp_rmb(); - func(mdata->single.probe_private, call_private, mdata->format, - &args); - } else { - struct marker_probe_closure *multi; - int i; - /* - * Read mdata->ptype before mdata->multi. - */ - smp_rmb(); - multi = mdata->multi; - /* - * multi points to an array, therefore accessing the array - * depends on reading multi. However, even in this case, - * we must insure that the pointer is read _before_ the array - * data. Same as rcu_dereference, but we need a full smp_rmb() - * in the fast path, so put the explicit barrier here. - */ - smp_read_barrier_depends(); - for (i = 0; multi[i].func; i++) - multi[i].func(multi[i].probe_private, call_private, - mdata->format, &args); - } - rcu_read_unlock_sched_notrace(); -} - -static void free_old_closure(struct rcu_head *head) -{ - struct marker_entry *entry = container_of(head, - struct marker_entry, rcu); - kfree(entry->oldptr); - /* Make sure we free the data before setting the pending flag to 0 */ - smp_wmb(); - entry->rcu_pending = 0; -} - -static void debug_print_probes(struct marker_entry *entry) -{ - int i; - - if (!marker_debug) - return; - - if (!entry->ptype) { - printk(KERN_DEBUG "Single probe : %p %p\n", - entry->single.func, - entry->single.probe_private); - } else { - for (i = 0; entry->multi[i].func; i++) - printk(KERN_DEBUG "Multi probe %d : %p %p\n", i, - entry->multi[i].func, - entry->multi[i].probe_private); - } -} - -static struct marker_probe_closure * -marker_entry_add_probe(struct marker_entry *entry, - marker_probe_func *probe, void *probe_private) -{ - int nr_probes = 0; - struct marker_probe_closure *old, *new; - - WARN_ON(!probe); - - debug_print_probes(entry); - old = entry->multi; - if (!entry->ptype) { - if (entry->single.func == probe && - entry->single.probe_private == probe_private) - return ERR_PTR(-EBUSY); - if (entry->single.func == __mark_empty_function) { - /* 0 -> 1 probes */ - entry->single.func = probe; - entry->single.probe_private = probe_private; - entry->refcount = 1; - entry->ptype = 0; - debug_print_probes(entry); - return NULL; - } else { - /* 1 -> 2 probes */ - nr_probes = 1; - old = NULL; - } - } else { - /* (N -> N+1), (N != 0, 1) probes */ - for (nr_probes = 0; old[nr_probes].func; nr_probes++) - if (old[nr_probes].func == probe - && old[nr_probes].probe_private - == probe_private) - return ERR_PTR(-EBUSY); - } - /* + 2 : one for new probe, one for NULL func */ - new = kzalloc((nr_probes + 2) * sizeof(struct marker_probe_closure), - GFP_KERNEL); - if (new == NULL) - return ERR_PTR(-ENOMEM); - if (!old) - new[0] = entry->single; - else - memcpy(new, old, - nr_probes * sizeof(struct marker_probe_closure)); - new[nr_probes].func = probe; - new[nr_probes].probe_private = probe_private; - entry->refcount = nr_probes + 1; - entry->multi = new; - entry->ptype = 1; - debug_print_probes(entry); - return old; -} - -static struct marker_probe_closure * -marker_entry_remove_probe(struct marker_entry *entry, - marker_probe_func *probe, void *probe_private) -{ - int nr_probes = 0, nr_del = 0, i; - struct marker_probe_closure *old, *new; - - old = entry->multi; - - debug_print_probes(entry); - if (!entry->ptype) { - /* 0 -> N is an error */ - WARN_ON(entry->single.func == __mark_empty_function); - /* 1 -> 0 probes */ - WARN_ON(probe && entry->single.func != probe); - WARN_ON(entry->single.probe_private != probe_private); - entry->single.func = __mark_empty_function; - entry->refcount = 0; - entry->ptype = 0; - debug_print_probes(entry); - return NULL; - } else { - /* (N -> M), (N > 1, M >= 0) probes */ - for (nr_probes = 0; old[nr_probes].func; nr_probes++) { - if ((!probe || old[nr_probes].func == probe) - && old[nr_probes].probe_private - == probe_private) - nr_del++; - } - } - - if (nr_probes - nr_del == 0) { - /* N -> 0, (N > 1) */ - entry->single.func = __mark_empty_function; - entry->refcount = 0; - entry->ptype = 0; - } else if (nr_probes - nr_del == 1) { - /* N -> 1, (N > 1) */ - for (i = 0; old[i].func; i++) - if ((probe && old[i].func != probe) || - old[i].probe_private != probe_private) - entry->single = old[i]; - entry->refcount = 1; - entry->ptype = 0; - } else { - int j = 0; - /* N -> M, (N > 1, M > 1) */ - /* + 1 for NULL */ - new = kzalloc((nr_probes - nr_del + 1) - * sizeof(struct marker_probe_closure), GFP_KERNEL); - if (new == NULL) - return ERR_PTR(-ENOMEM); - for (i = 0; old[i].func; i++) - if ((probe && old[i].func != probe) || - old[i].probe_private != probe_private) - new[j++] = old[i]; - entry->refcount = nr_probes - nr_del; - entry->ptype = 1; - entry->multi = new; - } - debug_print_probes(entry); - return old; -} - -/* - * Get marker if the marker is present in the marker hash table. - * Must be called with markers_mutex held. - * Returns NULL if not present. - */ -static struct marker_entry *get_marker(const char *name) -{ - struct hlist_head *head; - struct hlist_node *node; - struct marker_entry *e; - u32 hash = jhash(name, strlen(name), 0); - - head = &marker_table[hash & ((1 << MARKER_HASH_BITS)-1)]; - hlist_for_each_entry(e, node, head, hlist) { - if (!strcmp(name, e->name)) - return e; - } - return NULL; -} - -/* - * Add the marker to the marker hash table. Must be called with markers_mutex - * held. - */ -static struct marker_entry *add_marker(const char *name, const char *format) -{ - struct hlist_head *head; - struct hlist_node *node; - struct marker_entry *e; - size_t name_len = strlen(name) + 1; - size_t format_len = 0; - u32 hash = jhash(name, name_len-1, 0); - - if (format) - format_len = strlen(format) + 1; - head = &marker_table[hash & ((1 << MARKER_HASH_BITS)-1)]; - hlist_for_each_entry(e, node, head, hlist) { - if (!strcmp(name, e->name)) { - printk(KERN_NOTICE - "Marker %s busy\n", name); - return ERR_PTR(-EBUSY); /* Already there */ - } - } - /* - * Using kmalloc here to allocate a variable length element. Could - * cause some memory fragmentation if overused. - */ - e = kmalloc(sizeof(struct marker_entry) + name_len + format_len, - GFP_KERNEL); - if (!e) - return ERR_PTR(-ENOMEM); - memcpy(&e->name[0], name, name_len); - if (format) { - e->format = &e->name[name_len]; - memcpy(e->format, format, format_len); - if (strcmp(e->format, MARK_NOARGS) == 0) - e->call = marker_probe_cb_noarg; - else - e->call = marker_probe_cb; - trace_mark(core_marker_format, "name %s format %s", - e->name, e->format); - } else { - e->format = NULL; - e->call = marker_probe_cb; - } - e->single.func = __mark_empty_function; - e->single.probe_private = NULL; - e->multi = NULL; - e->ptype = 0; - e->format_allocated = 0; - e->refcount = 0; - e->rcu_pending = 0; - hlist_add_head(&e->hlist, head); - return e; -} - -/* - * Remove the marker from the marker hash table. Must be called with mutex_lock - * held. - */ -static int remove_marker(const char *name) -{ - struct hlist_head *head; - struct hlist_node *node; - struct marker_entry *e; - int found = 0; - size_t len = strlen(name) + 1; - u32 hash = jhash(name, len-1, 0); - - head = &marker_table[hash & ((1 << MARKER_HASH_BITS)-1)]; - hlist_for_each_entry(e, node, head, hlist) { - if (!strcmp(name, e->name)) { - found = 1; - break; - } - } - if (!found) - return -ENOENT; - if (e->single.func != __mark_empty_function) - return -EBUSY; - hlist_del(&e->hlist); - if (e->format_allocated) - kfree(e->format); - /* Make sure the call_rcu has been executed */ - if (e->rcu_pending) - rcu_barrier_sched(); - kfree(e); - return 0; -} - -/* - * Set the mark_entry format to the format found in the element. - */ -static int marker_set_format(struct marker_entry *entry, const char *format) -{ - entry->format = kstrdup(format, GFP_KERNEL); - if (!entry->format) - return -ENOMEM; - entry->format_allocated = 1; - - trace_mark(core_marker_format, "name %s format %s", - entry->name, entry->format); - return 0; -} - -/* - * Sets the probe callback corresponding to one marker. - */ -static int set_marker(struct marker_entry *entry, struct marker *elem, - int active) -{ - int ret = 0; - WARN_ON(strcmp(entry->name, elem->name) != 0); - - if (entry->format) { - if (strcmp(entry->format, elem->format) != 0) { - printk(KERN_NOTICE - "Format mismatch for probe %s " - "(%s), marker (%s)\n", - entry->name, - entry->format, - elem->format); - return -EPERM; - } - } else { - ret = marker_set_format(entry, elem->format); - if (ret) - return ret; - } - - /* - * probe_cb setup (statically known) is done here. It is - * asynchronous with the rest of execution, therefore we only - * pass from a "safe" callback (with argument) to an "unsafe" - * callback (does not set arguments). - */ - elem->call = entry->call; - /* - * Sanity check : - * We only update the single probe private data when the ptr is - * set to a _non_ single probe! (0 -> 1 and N -> 1, N != 1) - */ - WARN_ON(elem->single.func != __mark_empty_function - && elem->single.probe_private != entry->single.probe_private - && !elem->ptype); - elem->single.probe_private = entry->single.probe_private; - /* - * Make sure the private data is valid when we update the - * single probe ptr. - */ - smp_wmb(); - elem->single.func = entry->single.func; - /* - * We also make sure that the new probe callbacks array is consistent - * before setting a pointer to it. - */ - rcu_assign_pointer(elem->multi, entry->multi); - /* - * Update the function or multi probe array pointer before setting the - * ptype. - */ - smp_wmb(); - elem->ptype = entry->ptype; - - if (elem->tp_name && (active ^ elem->state)) { - WARN_ON(!elem->tp_cb); - /* - * It is ok to directly call the probe registration because type - * checking has been done in the __trace_mark_tp() macro. - */ - - if (active) { - /* - * try_module_get should always succeed because we hold - * lock_module() to get the tp_cb address. - */ - ret = try_module_get(__module_text_address( - (unsigned long)elem->tp_cb)); - BUG_ON(!ret); - ret = tracepoint_probe_register_noupdate( - elem->tp_name, - elem->tp_cb); - } else { - ret = tracepoint_probe_unregister_noupdate( - elem->tp_name, - elem->tp_cb); - /* - * tracepoint_probe_update_all() must be called - * before the module containing tp_cb is unloaded. - */ - module_put(__module_text_address( - (unsigned long)elem->tp_cb)); - } - } - elem->state = active; - - return ret; -} - -/* - * Disable a marker and its probe callback. - * Note: only waiting an RCU period after setting elem->call to the empty - * function insures that the original callback is not used anymore. This insured - * by rcu_read_lock_sched around the call site. - */ -static void disable_marker(struct marker *elem) -{ - int ret; - - /* leave "call" as is. It is known statically. */ - if (elem->tp_name && elem->state) { - WARN_ON(!elem->tp_cb); - /* - * It is ok to directly call the probe registration because type - * checking has been done in the __trace_mark_tp() macro. - */ - ret = tracepoint_probe_unregister_noupdate(elem->tp_name, - elem->tp_cb); - WARN_ON(ret); - /* - * tracepoint_probe_update_all() must be called - * before the module containing tp_cb is unloaded. - */ - module_put(__module_text_address((unsigned long)elem->tp_cb)); - } - elem->state = 0; - elem->single.func = __mark_empty_function; - /* Update the function before setting the ptype */ - smp_wmb(); - elem->ptype = 0; /* single probe */ - /* - * Leave the private data and id there, because removal is racy and - * should be done only after an RCU period. These are never used until - * the next initialization anyway. - */ -} - -/** - * marker_update_probe_range - Update a probe range - * @begin: beginning of the range - * @end: end of the range - * - * Updates the probe callback corresponding to a range of markers. - */ -void marker_update_probe_range(struct marker *begin, - struct marker *end) -{ - struct marker *iter; - struct marker_entry *mark_entry; - - mutex_lock(&markers_mutex); - for (iter = begin; iter < end; iter++) { - mark_entry = get_marker(iter->name); - if (mark_entry) { - set_marker(mark_entry, iter, !!mark_entry->refcount); - /* - * ignore error, continue - */ - } else { - disable_marker(iter); - } - } - mutex_unlock(&markers_mutex); -} - -/* - * Update probes, removing the faulty probes. - * - * Internal callback only changed before the first probe is connected to it. - * Single probe private data can only be changed on 0 -> 1 and 2 -> 1 - * transitions. All other transitions will leave the old private data valid. - * This makes the non-atomicity of the callback/private data updates valid. - * - * "special case" updates : - * 0 -> 1 callback - * 1 -> 0 callback - * 1 -> 2 callbacks - * 2 -> 1 callbacks - * Other updates all behave the same, just like the 2 -> 3 or 3 -> 2 updates. - * Site effect : marker_set_format may delete the marker entry (creating a - * replacement). - */ -static void marker_update_probes(void) -{ - /* Core kernel markers */ - marker_update_probe_range(__start___markers, __stop___markers); - /* Markers in modules. */ - module_update_markers(); - tracepoint_probe_update_all(); -} - -/** - * marker_probe_register - Connect a probe to a marker - * @name: marker name - * @format: format string - * @probe: probe handler - * @probe_private: probe private data - * - * private data must be a valid allocated memory address, or NULL. - * Returns 0 if ok, error value on error. - * The probe address must at least be aligned on the architecture pointer size. - */ -int marker_probe_register(const char *name, const char *format, - marker_probe_func *probe, void *probe_private) -{ - struct marker_entry *entry; - int ret = 0; - struct marker_probe_closure *old; - - mutex_lock(&markers_mutex); - entry = get_marker(name); - if (!entry) { - entry = add_marker(name, format); - if (IS_ERR(entry)) - ret = PTR_ERR(entry); - } else if (format) { - if (!entry->format) - ret = marker_set_format(entry, format); - else if (strcmp(entry->format, format)) - ret = -EPERM; - } - if (ret) - goto end; - - /* - * If we detect that a call_rcu is pending for this marker, - * make sure it's executed now. - */ - if (entry->rcu_pending) - rcu_barrier_sched(); - old = marker_entry_add_probe(entry, probe, probe_private); - if (IS_ERR(old)) { - ret = PTR_ERR(old); - goto end; - } - mutex_unlock(&markers_mutex); - marker_update_probes(); - mutex_lock(&markers_mutex); - entry = get_marker(name); - if (!entry) - goto end; - if (entry->rcu_pending) - rcu_barrier_sched(); - entry->oldptr = old; - entry->rcu_pending = 1; - /* write rcu_pending before calling the RCU callback */ - smp_wmb(); - call_rcu_sched(&entry->rcu, free_old_closure); -end: - mutex_unlock(&markers_mutex); - return ret; -} -EXPORT_SYMBOL_GPL(marker_probe_register); - -/** - * marker_probe_unregister - Disconnect a probe from a marker - * @name: marker name - * @probe: probe function pointer - * @probe_private: probe private data - * - * Returns the private data given to marker_probe_register, or an ERR_PTR(). - * We do not need to call a synchronize_sched to make sure the probes have - * finished running before doing a module unload, because the module unload - * itself uses stop_machine(), which insures that every preempt disabled section - * have finished. - */ -int marker_probe_unregister(const char *name, - marker_probe_func *probe, void *probe_private) -{ - struct marker_entry *entry; - struct marker_probe_closure *old; - int ret = -ENOENT; - - mutex_lock(&markers_mutex); - entry = get_marker(name); - if (!entry) - goto end; - if (entry->rcu_pending) - rcu_barrier_sched(); - old = marker_entry_remove_probe(entry, probe, probe_private); - mutex_unlock(&markers_mutex); - marker_update_probes(); - mutex_lock(&markers_mutex); - entry = get_marker(name); - if (!entry) - goto end; - if (entry->rcu_pending) - rcu_barrier_sched(); - entry->oldptr = old; - entry->rcu_pending = 1; - /* write rcu_pending before calling the RCU callback */ - smp_wmb(); - call_rcu_sched(&entry->rcu, free_old_closure); - remove_marker(name); /* Ignore busy error message */ - ret = 0; -end: - mutex_unlock(&markers_mutex); - return ret; -} -EXPORT_SYMBOL_GPL(marker_probe_unregister); - -static struct marker_entry * -get_marker_from_private_data(marker_probe_func *probe, void *probe_private) -{ - struct marker_entry *entry; - unsigned int i; - struct hlist_head *head; - struct hlist_node *node; - - for (i = 0; i < MARKER_TABLE_SIZE; i++) { - head = &marker_table[i]; - hlist_for_each_entry(entry, node, head, hlist) { - if (!entry->ptype) { - if (entry->single.func == probe - && entry->single.probe_private - == probe_private) - return entry; - } else { - struct marker_probe_closure *closure; - closure = entry->multi; - for (i = 0; closure[i].func; i++) { - if (closure[i].func == probe && - closure[i].probe_private - == probe_private) - return entry; - } - } - } - } - return NULL; -} - -/** - * marker_probe_unregister_private_data - Disconnect a probe from a marker - * @probe: probe function - * @probe_private: probe private data - * - * Unregister a probe by providing the registered private data. - * Only removes the first marker found in hash table. - * Return 0 on success or error value. - * We do not need to call a synchronize_sched to make sure the probes have - * finished running before doing a module unload, because the module unload - * itself uses stop_machine(), which insures that every preempt disabled section - * have finished. - */ -int marker_probe_unregister_private_data(marker_probe_func *probe, - void *probe_private) -{ - struct marker_entry *entry; - int ret = 0; - struct marker_probe_closure *old; - - mutex_lock(&markers_mutex); - entry = get_marker_from_private_data(probe, probe_private); - if (!entry) { - ret = -ENOENT; - goto end; - } - if (entry->rcu_pending) - rcu_barrier_sched(); - old = marker_entry_remove_probe(entry, NULL, probe_private); - mutex_unlock(&markers_mutex); - marker_update_probes(); - mutex_lock(&markers_mutex); - entry = get_marker_from_private_data(probe, probe_private); - if (!entry) - goto end; - if (entry->rcu_pending) - rcu_barrier_sched(); - entry->oldptr = old; - entry->rcu_pending = 1; - /* write rcu_pending before calling the RCU callback */ - smp_wmb(); - call_rcu_sched(&entry->rcu, free_old_closure); - remove_marker(entry->name); /* Ignore busy error message */ -end: - mutex_unlock(&markers_mutex); - return ret; -} -EXPORT_SYMBOL_GPL(marker_probe_unregister_private_data); - -/** - * marker_get_private_data - Get a marker's probe private data - * @name: marker name - * @probe: probe to match - * @num: get the nth matching probe's private data - * - * Returns the nth private data pointer (starting from 0) matching, or an - * ERR_PTR. - * Returns the private data pointer, or an ERR_PTR. - * The private data pointer should _only_ be dereferenced if the caller is the - * owner of the data, or its content could vanish. This is mostly used to - * confirm that a caller is the owner of a registered probe. - */ -void *marker_get_private_data(const char *name, marker_probe_func *probe, - int num) -{ - struct hlist_head *head; - struct hlist_node *node; - struct marker_entry *e; - size_t name_len = strlen(name) + 1; - u32 hash = jhash(name, name_len-1, 0); - int i; - - head = &marker_table[hash & ((1 << MARKER_HASH_BITS)-1)]; - hlist_for_each_entry(e, node, head, hlist) { - if (!strcmp(name, e->name)) { - if (!e->ptype) { - if (num == 0 && e->single.func == probe) - return e->single.probe_private; - } else { - struct marker_probe_closure *closure; - int match = 0; - closure = e->multi; - for (i = 0; closure[i].func; i++) { - if (closure[i].func != probe) - continue; - if (match++ == num) - return closure[i].probe_private; - } - } - break; - } - } - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL_GPL(marker_get_private_data); - -#ifdef CONFIG_MODULES - -int marker_module_notify(struct notifier_block *self, - unsigned long val, void *data) -{ - struct module *mod = data; - - switch (val) { - case MODULE_STATE_COMING: - marker_update_probe_range(mod->markers, - mod->markers + mod->num_markers); - break; - case MODULE_STATE_GOING: - marker_update_probe_range(mod->markers, - mod->markers + mod->num_markers); - break; - } - return 0; -} - -struct notifier_block marker_module_nb = { - .notifier_call = marker_module_notify, - .priority = 0, -}; - -static int init_markers(void) -{ - return register_module_notifier(&marker_module_nb); -} -__initcall(init_markers); - -#endif /* CONFIG_MODULES */ diff --git a/kernel/module.c b/kernel/module.c index 05ce49ced8f6..b6ee424245dd 100644 --- a/kernel/module.c +++ b/kernel/module.c @@ -2237,10 +2237,6 @@ static noinline struct module *load_module(void __user *umod, sizeof(*mod->ctors), &mod->num_ctors); #endif -#ifdef CONFIG_MARKERS - mod->markers = section_objs(hdr, sechdrs, secstrings, "__markers", - sizeof(*mod->markers), &mod->num_markers); -#endif #ifdef CONFIG_TRACEPOINTS mod->tracepoints = section_objs(hdr, sechdrs, secstrings, "__tracepoints", @@ -2958,20 +2954,6 @@ void module_layout(struct module *mod, EXPORT_SYMBOL(module_layout); #endif -#ifdef CONFIG_MARKERS -void module_update_markers(void) -{ - struct module *mod; - - mutex_lock(&module_mutex); - list_for_each_entry(mod, &modules, list) - if (!mod->taints) - marker_update_probe_range(mod->markers, - mod->markers + mod->num_markers); - mutex_unlock(&module_mutex); -} -#endif - #ifdef CONFIG_TRACEPOINTS void module_update_tracepoints(void) { diff --git a/kernel/profile.c b/kernel/profile.c index 419250ebec4d..a55d3a367ae8 100644 --- a/kernel/profile.c +++ b/kernel/profile.c @@ -442,48 +442,51 @@ void profile_tick(int type) #ifdef CONFIG_PROC_FS #include +#include #include -static int prof_cpu_mask_read_proc(char *page, char **start, off_t off, - int count, int *eof, void *data) +static int prof_cpu_mask_proc_show(struct seq_file *m, void *v) { - int len = cpumask_scnprintf(page, count, data); - if (count - len < 2) - return -EINVAL; - len += sprintf(page + len, "\n"); - return len; + seq_cpumask(m, prof_cpu_mask); + seq_putc(m, '\n'); + return 0; } -static int prof_cpu_mask_write_proc(struct file *file, - const char __user *buffer, unsigned long count, void *data) +static int prof_cpu_mask_proc_open(struct inode *inode, struct file *file) +{ + return single_open(file, prof_cpu_mask_proc_show, NULL); +} + +static ssize_t prof_cpu_mask_proc_write(struct file *file, + const char __user *buffer, size_t count, loff_t *pos) { - struct cpumask *mask = data; - unsigned long full_count = count, err; cpumask_var_t new_value; + int err; if (!alloc_cpumask_var(&new_value, GFP_KERNEL)) return -ENOMEM; err = cpumask_parse_user(buffer, count, new_value); if (!err) { - cpumask_copy(mask, new_value); - err = full_count; + cpumask_copy(prof_cpu_mask, new_value); + err = count; } free_cpumask_var(new_value); return err; } +static const struct file_operations prof_cpu_mask_proc_fops = { + .open = prof_cpu_mask_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = prof_cpu_mask_proc_write, +}; + void create_prof_cpu_mask(struct proc_dir_entry *root_irq_dir) { - struct proc_dir_entry *entry; - /* create /proc/irq/prof_cpu_mask */ - entry = create_proc_entry("prof_cpu_mask", 0600, root_irq_dir); - if (!entry) - return; - entry->data = prof_cpu_mask; - entry->read_proc = prof_cpu_mask_read_proc; - entry->write_proc = prof_cpu_mask_write_proc; + proc_create("prof_cpu_mask", 0600, root_irq_dir, &prof_cpu_mask_proc_fops); } /* diff --git a/kernel/rcupdate.c b/kernel/rcupdate.c index bd5d5c8e5140..37ac45483082 100644 --- a/kernel/rcupdate.c +++ b/kernel/rcupdate.c @@ -19,7 +19,7 @@ * * Authors: Dipankar Sarma * Manfred Spraul - * + * * Based on the original work by Paul McKenney * and inputs from Rusty Russell, Andrea Arcangeli and Andi Kleen. * Papers: @@ -27,7 +27,7 @@ * http://lse.sourceforge.net/locking/rclock_OLS.2001.05.01c.sc.pdf (OLS2001) * * For detailed explanation of Read-Copy Update mechanism see - - * http://lse.sourceforge.net/locking/rcupdate.html + * http://lse.sourceforge.net/locking/rcupdate.html * */ #include @@ -74,6 +74,8 @@ void wakeme_after_rcu(struct rcu_head *head) complete(&rcu->completion); } +#ifdef CONFIG_TREE_PREEMPT_RCU + /** * synchronize_rcu - wait until a grace period has elapsed. * @@ -87,7 +89,7 @@ void synchronize_rcu(void) { struct rcu_synchronize rcu; - if (rcu_blocking_is_gp()) + if (!rcu_scheduler_active) return; init_completion(&rcu.completion); @@ -98,6 +100,46 @@ void synchronize_rcu(void) } EXPORT_SYMBOL_GPL(synchronize_rcu); +#endif /* #ifdef CONFIG_TREE_PREEMPT_RCU */ + +/** + * synchronize_sched - wait until an rcu-sched grace period has elapsed. + * + * Control will return to the caller some time after a full rcu-sched + * grace period has elapsed, in other words after all currently executing + * rcu-sched read-side critical sections have completed. These read-side + * critical sections are delimited by rcu_read_lock_sched() and + * rcu_read_unlock_sched(), and may be nested. Note that preempt_disable(), + * local_irq_disable(), and so on may be used in place of + * rcu_read_lock_sched(). + * + * This means that all preempt_disable code sequences, including NMI and + * hardware-interrupt handlers, in progress on entry will have completed + * before this primitive returns. However, this does not guarantee that + * softirq handlers will have completed, since in some kernels, these + * handlers can run in process context, and can block. + * + * This primitive provides the guarantees made by the (now removed) + * synchronize_kernel() API. In contrast, synchronize_rcu() only + * guarantees that rcu_read_lock() sections will have completed. + * In "classic RCU", these two guarantees happen to be one and + * the same, but can differ in realtime RCU implementations. + */ +void synchronize_sched(void) +{ + struct rcu_synchronize rcu; + + if (rcu_blocking_is_gp()) + return; + + init_completion(&rcu.completion); + /* Will wake me after RCU finished. */ + call_rcu_sched(&rcu.head, wakeme_after_rcu); + /* Wait for it. */ + wait_for_completion(&rcu.completion); +} +EXPORT_SYMBOL_GPL(synchronize_sched); + /** * synchronize_rcu_bh - wait until an rcu_bh grace period has elapsed. * diff --git a/kernel/rcutorture.c b/kernel/rcutorture.c index b33db539a8ad..233768f21f97 100644 --- a/kernel/rcutorture.c +++ b/kernel/rcutorture.c @@ -18,7 +18,7 @@ * Copyright (C) IBM Corporation, 2005, 2006 * * Authors: Paul E. McKenney - * Josh Triplett + * Josh Triplett * * See also: Documentation/RCU/torture.txt */ @@ -50,7 +50,7 @@ MODULE_LICENSE("GPL"); MODULE_AUTHOR("Paul E. McKenney and " - "Josh Triplett "); + "Josh Triplett "); static int nreaders = -1; /* # reader threads, defaults to 2*ncpus */ static int nfakewriters = 4; /* # fake writer threads */ @@ -110,8 +110,8 @@ struct rcu_torture { }; static LIST_HEAD(rcu_torture_freelist); -static struct rcu_torture *rcu_torture_current = NULL; -static long rcu_torture_current_version = 0; +static struct rcu_torture *rcu_torture_current; +static long rcu_torture_current_version; static struct rcu_torture rcu_tortures[10 * RCU_TORTURE_PIPE_LEN]; static DEFINE_SPINLOCK(rcu_torture_lock); static DEFINE_PER_CPU(long [RCU_TORTURE_PIPE_LEN + 1], rcu_torture_count) = @@ -124,11 +124,11 @@ static atomic_t n_rcu_torture_alloc_fail; static atomic_t n_rcu_torture_free; static atomic_t n_rcu_torture_mberror; static atomic_t n_rcu_torture_error; -static long n_rcu_torture_timers = 0; +static long n_rcu_torture_timers; static struct list_head rcu_torture_removed; static cpumask_var_t shuffle_tmp_mask; -static int stutter_pause_test = 0; +static int stutter_pause_test; #if defined(MODULE) || defined(CONFIG_RCU_TORTURE_TEST_RUNNABLE) #define RCUTORTURE_RUNNABLE_INIT 1 @@ -267,7 +267,8 @@ struct rcu_torture_ops { int irq_capable; char *name; }; -static struct rcu_torture_ops *cur_ops = NULL; + +static struct rcu_torture_ops *cur_ops; /* * Definitions for rcu torture testing. @@ -281,14 +282,17 @@ static int rcu_torture_read_lock(void) __acquires(RCU) static void rcu_read_delay(struct rcu_random_state *rrsp) { - long delay; - const long longdelay = 200; + const unsigned long shortdelay_us = 200; + const unsigned long longdelay_ms = 50; - /* We want there to be long-running readers, but not all the time. */ + /* We want a short delay sometimes to make a reader delay the grace + * period, and we want a long delay occasionally to trigger + * force_quiescent_state. */ - delay = rcu_random(rrsp) % (nrealreaders * 2 * longdelay); - if (!delay) - udelay(longdelay); + if (!(rcu_random(rrsp) % (nrealreaders * 2000 * longdelay_ms))) + mdelay(longdelay_ms); + if (!(rcu_random(rrsp) % (nrealreaders * 2 * shortdelay_us))) + udelay(shortdelay_us); } static void rcu_torture_read_unlock(int idx) __releases(RCU) @@ -339,8 +343,8 @@ static struct rcu_torture_ops rcu_ops = { .sync = synchronize_rcu, .cb_barrier = rcu_barrier, .stats = NULL, - .irq_capable = 1, - .name = "rcu" + .irq_capable = 1, + .name = "rcu" }; static void rcu_sync_torture_deferred_free(struct rcu_torture *p) @@ -638,7 +642,8 @@ rcu_torture_writer(void *arg) do { schedule_timeout_uninterruptible(1); - if ((rp = rcu_torture_alloc()) == NULL) + rp = rcu_torture_alloc(); + if (rp == NULL) continue; rp->rtort_pipe_count = 0; udelay(rcu_random(&rand) & 0x3ff); @@ -1110,7 +1115,7 @@ rcu_torture_init(void) printk(KERN_ALERT "rcutorture: invalid torture type: \"%s\"\n", torture_type); mutex_unlock(&fullstop_mutex); - return (-EINVAL); + return -EINVAL; } if (cur_ops->init) cur_ops->init(); /* no "goto unwind" prior to this point!!! */ @@ -1161,7 +1166,7 @@ rcu_torture_init(void) goto unwind; } fakewriter_tasks = kzalloc(nfakewriters * sizeof(fakewriter_tasks[0]), - GFP_KERNEL); + GFP_KERNEL); if (fakewriter_tasks == NULL) { VERBOSE_PRINTK_ERRSTRING("out of memory"); firsterr = -ENOMEM; @@ -1170,7 +1175,7 @@ rcu_torture_init(void) for (i = 0; i < nfakewriters; i++) { VERBOSE_PRINTK_STRING("Creating rcu_torture_fakewriter task"); fakewriter_tasks[i] = kthread_run(rcu_torture_fakewriter, NULL, - "rcu_torture_fakewriter"); + "rcu_torture_fakewriter"); if (IS_ERR(fakewriter_tasks[i])) { firsterr = PTR_ERR(fakewriter_tasks[i]); VERBOSE_PRINTK_ERRSTRING("Failed to create fakewriter"); diff --git a/kernel/rcutree.c b/kernel/rcutree.c index 6b11b07cfe7f..52b06f6e158c 100644 --- a/kernel/rcutree.c +++ b/kernel/rcutree.c @@ -25,7 +25,7 @@ * and inputs from Rusty Russell, Andrea Arcangeli and Andi Kleen. * * For detailed explanation of Read-Copy Update mechanism see - - * Documentation/RCU + * Documentation/RCU */ #include #include @@ -107,27 +107,23 @@ static void __cpuinit rcu_init_percpu_data(int cpu, struct rcu_state *rsp, */ void rcu_sched_qs(int cpu) { - unsigned long flags; struct rcu_data *rdp; - local_irq_save(flags); rdp = &per_cpu(rcu_sched_data, cpu); - rdp->passed_quiesc = 1; rdp->passed_quiesc_completed = rdp->completed; - rcu_preempt_qs(cpu); - local_irq_restore(flags); + barrier(); + rdp->passed_quiesc = 1; + rcu_preempt_note_context_switch(cpu); } void rcu_bh_qs(int cpu) { - unsigned long flags; struct rcu_data *rdp; - local_irq_save(flags); rdp = &per_cpu(rcu_bh_data, cpu); - rdp->passed_quiesc = 1; rdp->passed_quiesc_completed = rdp->completed; - local_irq_restore(flags); + barrier(); + rdp->passed_quiesc = 1; } #ifdef CONFIG_NO_HZ @@ -605,8 +601,6 @@ rcu_start_gp(struct rcu_state *rsp, unsigned long flags) { struct rcu_data *rdp = rsp->rda[smp_processor_id()]; struct rcu_node *rnp = rcu_get_root(rsp); - struct rcu_node *rnp_cur; - struct rcu_node *rnp_end; if (!cpu_needs_another_gp(rsp, rdp)) { spin_unlock_irqrestore(&rnp->lock, flags); @@ -615,6 +609,7 @@ rcu_start_gp(struct rcu_state *rsp, unsigned long flags) /* Advance to a new grace period and initialize state. */ rsp->gpnum++; + WARN_ON_ONCE(rsp->signaled == RCU_GP_INIT); rsp->signaled = RCU_GP_INIT; /* Hold off force_quiescent_state. */ rsp->jiffies_force_qs = jiffies + RCU_JIFFIES_TILL_FORCE_QS; record_gp_stall_check_time(rsp); @@ -631,7 +626,9 @@ rcu_start_gp(struct rcu_state *rsp, unsigned long flags) /* Special-case the common single-level case. */ if (NUM_RCU_NODES == 1) { + rcu_preempt_check_blocked_tasks(rnp); rnp->qsmask = rnp->qsmaskinit; + rnp->gpnum = rsp->gpnum; rsp->signaled = RCU_SIGNAL_INIT; /* force_quiescent_state OK. */ spin_unlock_irqrestore(&rnp->lock, flags); return; @@ -644,42 +641,28 @@ rcu_start_gp(struct rcu_state *rsp, unsigned long flags) spin_lock(&rsp->onofflock); /* irqs already disabled. */ /* - * Set the quiescent-state-needed bits in all the non-leaf RCU - * nodes for all currently online CPUs. This operation relies - * on the layout of the hierarchy within the rsp->node[] array. - * Note that other CPUs will access only the leaves of the - * hierarchy, which still indicate that no grace period is in - * progress. In addition, we have excluded CPU-hotplug operations. - * - * We therefore do not need to hold any locks. Any required - * memory barriers will be supplied by the locks guarding the - * leaf rcu_nodes in the hierarchy. - */ - - rnp_end = rsp->level[NUM_RCU_LVLS - 1]; - for (rnp_cur = &rsp->node[0]; rnp_cur < rnp_end; rnp_cur++) - rnp_cur->qsmask = rnp_cur->qsmaskinit; - - /* - * Now set up the leaf nodes. Here we must be careful. First, - * we need to hold the lock in order to exclude other CPUs, which - * might be contending for the leaf nodes' locks. Second, as - * soon as we initialize a given leaf node, its CPUs might run - * up the rest of the hierarchy. We must therefore acquire locks - * for each node that we touch during this stage. (But we still - * are excluding CPU-hotplug operations.) + * Set the quiescent-state-needed bits in all the rcu_node + * structures for all currently online CPUs in breadth-first + * order, starting from the root rcu_node structure. This + * operation relies on the layout of the hierarchy within the + * rsp->node[] array. Note that other CPUs will access only + * the leaves of the hierarchy, which still indicate that no + * grace period is in progress, at least until the corresponding + * leaf node has been initialized. In addition, we have excluded + * CPU-hotplug operations. * * Note that the grace period cannot complete until we finish * the initialization process, as there will be at least one * qsmask bit set in the root node until that time, namely the - * one corresponding to this CPU. + * one corresponding to this CPU, due to the fact that we have + * irqs disabled. */ - rnp_end = &rsp->node[NUM_RCU_NODES]; - rnp_cur = rsp->level[NUM_RCU_LVLS - 1]; - for (; rnp_cur < rnp_end; rnp_cur++) { - spin_lock(&rnp_cur->lock); /* irqs already disabled. */ - rnp_cur->qsmask = rnp_cur->qsmaskinit; - spin_unlock(&rnp_cur->lock); /* irqs already disabled. */ + for (rnp = &rsp->node[0]; rnp < &rsp->node[NUM_RCU_NODES]; rnp++) { + spin_lock(&rnp->lock); /* irqs already disabled. */ + rcu_preempt_check_blocked_tasks(rnp); + rnp->qsmask = rnp->qsmaskinit; + rnp->gpnum = rsp->gpnum; + spin_unlock(&rnp->lock); /* irqs already disabled. */ } rsp->signaled = RCU_SIGNAL_INIT; /* force_quiescent_state now OK. */ @@ -722,6 +705,7 @@ rcu_process_gp_end(struct rcu_state *rsp, struct rcu_data *rdp) static void cpu_quiet_msk_finish(struct rcu_state *rsp, unsigned long flags) __releases(rnp->lock) { + WARN_ON_ONCE(rsp->completed == rsp->gpnum); rsp->completed = rsp->gpnum; rcu_process_gp_end(rsp, rsp->rda[smp_processor_id()]); rcu_start_gp(rsp, flags); /* releases root node's rnp->lock. */ @@ -739,6 +723,8 @@ cpu_quiet_msk(unsigned long mask, struct rcu_state *rsp, struct rcu_node *rnp, unsigned long flags) __releases(rnp->lock) { + struct rcu_node *rnp_c; + /* Walk up the rcu_node hierarchy. */ for (;;) { if (!(rnp->qsmask & mask)) { @@ -762,8 +748,10 @@ cpu_quiet_msk(unsigned long mask, struct rcu_state *rsp, struct rcu_node *rnp, break; } spin_unlock_irqrestore(&rnp->lock, flags); + rnp_c = rnp; rnp = rnp->parent; spin_lock_irqsave(&rnp->lock, flags); + WARN_ON_ONCE(rnp_c->qsmask); } /* @@ -776,10 +764,10 @@ cpu_quiet_msk(unsigned long mask, struct rcu_state *rsp, struct rcu_node *rnp, /* * Record a quiescent state for the specified CPU, which must either be - * the current CPU or an offline CPU. The lastcomp argument is used to - * make sure we are still in the grace period of interest. We don't want - * to end the current grace period based on quiescent states detected in - * an earlier grace period! + * the current CPU. The lastcomp argument is used to make sure we are + * still in the grace period of interest. We don't want to end the current + * grace period based on quiescent states detected in an earlier grace + * period! */ static void cpu_quiet(int cpu, struct rcu_state *rsp, struct rcu_data *rdp, long lastcomp) @@ -814,7 +802,6 @@ cpu_quiet(int cpu, struct rcu_state *rsp, struct rcu_data *rdp, long lastcomp) * This GP can't end until cpu checks in, so all of our * callbacks can be processed during the next GP. */ - rdp = rsp->rda[smp_processor_id()]; rdp->nxttail[RCU_NEXT_READY_TAIL] = rdp->nxttail[RCU_NEXT_TAIL]; cpu_quiet_msk(mask, rsp, rnp, flags); /* releases rnp->lock */ @@ -872,7 +859,7 @@ static void __rcu_offline_cpu(int cpu, struct rcu_state *rsp) spin_lock_irqsave(&rsp->onofflock, flags); /* Remove the outgoing CPU from the masks in the rcu_node hierarchy. */ - rnp = rdp->mynode; + rnp = rdp->mynode; /* this is the outgoing CPU's rnp. */ mask = rdp->grpmask; /* rnp->grplo is constant. */ do { spin_lock(&rnp->lock); /* irqs already disabled. */ @@ -881,7 +868,7 @@ static void __rcu_offline_cpu(int cpu, struct rcu_state *rsp) spin_unlock(&rnp->lock); /* irqs remain disabled. */ break; } - rcu_preempt_offline_tasks(rsp, rnp); + rcu_preempt_offline_tasks(rsp, rnp, rdp); mask = rnp->grpmask; spin_unlock(&rnp->lock); /* irqs remain disabled. */ rnp = rnp->parent; @@ -890,9 +877,6 @@ static void __rcu_offline_cpu(int cpu, struct rcu_state *rsp) spin_unlock(&rsp->onofflock); /* irqs remain disabled. */ - /* Being offline is a quiescent state, so go record it. */ - cpu_quiet(cpu, rsp, rdp, lastcomp); - /* * Move callbacks from the outgoing CPU to the running CPU. * Note that the outgoing CPU is now quiscent, so it is now @@ -1457,20 +1441,7 @@ rcu_init_percpu_data(int cpu, struct rcu_state *rsp, int preemptable) rnp = rnp->parent; } while (rnp != NULL && !(rnp->qsmaskinit & mask)); - spin_unlock(&rsp->onofflock); /* irqs remain disabled. */ - - /* - * A new grace period might start here. If so, we will be part of - * it, and its gpnum will be greater than ours, so we will - * participate. It is also possible for the gpnum to have been - * incremented before this function was called, and the bitmasks - * to not be filled out until now, in which case we will also - * participate due to our gpnum being behind. - */ - - /* Since it is coming online, the CPU is in a quiescent state. */ - cpu_quiet(cpu, rsp, rdp, lastcomp); - local_irq_restore(flags); + spin_unlock_irqrestore(&rsp->onofflock, flags); } static void __cpuinit rcu_online_cpu(int cpu) diff --git a/kernel/rcutree.h b/kernel/rcutree.h index bf8a6f9f134d..8e8287a983c2 100644 --- a/kernel/rcutree.h +++ b/kernel/rcutree.h @@ -142,7 +142,7 @@ struct rcu_data { */ struct rcu_head *nxtlist; struct rcu_head **nxttail[RCU_NEXT_SIZE]; - long qlen; /* # of queued callbacks */ + long qlen; /* # of queued callbacks */ long blimit; /* Upper limit on a processed batch */ #ifdef CONFIG_NO_HZ diff --git a/kernel/rcutree_plugin.h b/kernel/rcutree_plugin.h index 47789369ea59..1cee04f627eb 100644 --- a/kernel/rcutree_plugin.h +++ b/kernel/rcutree_plugin.h @@ -64,22 +64,31 @@ EXPORT_SYMBOL_GPL(rcu_batches_completed); * not in a quiescent state. There might be any number of tasks blocked * while in an RCU read-side critical section. */ -static void rcu_preempt_qs_record(int cpu) +static void rcu_preempt_qs(int cpu) { struct rcu_data *rdp = &per_cpu(rcu_preempt_data, cpu); - rdp->passed_quiesc = 1; rdp->passed_quiesc_completed = rdp->completed; + barrier(); + rdp->passed_quiesc = 1; } /* - * We have entered the scheduler or are between softirqs in ksoftirqd. - * If we are in an RCU read-side critical section, we need to reflect - * that in the state of the rcu_node structure corresponding to this CPU. - * Caller must disable hardirqs. + * We have entered the scheduler, and the current task might soon be + * context-switched away from. If this task is in an RCU read-side + * critical section, we will no longer be able to rely on the CPU to + * record that fact, so we enqueue the task on the appropriate entry + * of the blocked_tasks[] array. The task will dequeue itself when + * it exits the outermost enclosing RCU read-side critical section. + * Therefore, the current grace period cannot be permitted to complete + * until the blocked_tasks[] entry indexed by the low-order bit of + * rnp->gpnum empties. + * + * Caller must disable preemption. */ -static void rcu_preempt_qs(int cpu) +static void rcu_preempt_note_context_switch(int cpu) { struct task_struct *t = current; + unsigned long flags; int phase; struct rcu_data *rdp; struct rcu_node *rnp; @@ -90,7 +99,7 @@ static void rcu_preempt_qs(int cpu) /* Possibly blocking in an RCU read-side critical section. */ rdp = rcu_preempt_state.rda[cpu]; rnp = rdp->mynode; - spin_lock(&rnp->lock); + spin_lock_irqsave(&rnp->lock, flags); t->rcu_read_unlock_special |= RCU_READ_UNLOCK_BLOCKED; t->rcu_blocked_node = rnp; @@ -103,11 +112,15 @@ static void rcu_preempt_qs(int cpu) * state for the current grace period), then as long * as that task remains queued, the current grace period * cannot end. + * + * But first, note that the current CPU must still be + * on line! */ - phase = !(rnp->qsmask & rdp->grpmask) ^ (rnp->gpnum & 0x1); + WARN_ON_ONCE((rdp->grpmask & rnp->qsmaskinit) == 0); + WARN_ON_ONCE(!list_empty(&t->rcu_node_entry)); + phase = (rnp->gpnum + !(rnp->qsmask & rdp->grpmask)) & 0x1; list_add(&t->rcu_node_entry, &rnp->blocked_tasks[phase]); - smp_mb(); /* Ensure later ctxt swtch seen after above. */ - spin_unlock(&rnp->lock); + spin_unlock_irqrestore(&rnp->lock, flags); } /* @@ -119,9 +132,10 @@ static void rcu_preempt_qs(int cpu) * grace period, then the fact that the task has been enqueued * means that we continue to block the current grace period. */ - rcu_preempt_qs_record(cpu); - t->rcu_read_unlock_special &= ~(RCU_READ_UNLOCK_NEED_QS | - RCU_READ_UNLOCK_GOT_QS); + rcu_preempt_qs(cpu); + local_irq_save(flags); + t->rcu_read_unlock_special &= ~RCU_READ_UNLOCK_NEED_QS; + local_irq_restore(flags); } /* @@ -157,7 +171,7 @@ static void rcu_read_unlock_special(struct task_struct *t) special = t->rcu_read_unlock_special; if (special & RCU_READ_UNLOCK_NEED_QS) { t->rcu_read_unlock_special &= ~RCU_READ_UNLOCK_NEED_QS; - t->rcu_read_unlock_special |= RCU_READ_UNLOCK_GOT_QS; + rcu_preempt_qs(smp_processor_id()); } /* Hardware IRQ handlers cannot block. */ @@ -177,10 +191,10 @@ static void rcu_read_unlock_special(struct task_struct *t) */ for (;;) { rnp = t->rcu_blocked_node; - spin_lock(&rnp->lock); + spin_lock(&rnp->lock); /* irqs already disabled. */ if (rnp == t->rcu_blocked_node) break; - spin_unlock(&rnp->lock); + spin_unlock(&rnp->lock); /* irqs remain disabled. */ } empty = list_empty(&rnp->blocked_tasks[rnp->gpnum & 0x1]); list_del_init(&t->rcu_node_entry); @@ -194,9 +208,8 @@ static void rcu_read_unlock_special(struct task_struct *t) */ if (!empty && rnp->qsmask == 0 && list_empty(&rnp->blocked_tasks[rnp->gpnum & 0x1])) { - t->rcu_read_unlock_special &= - ~(RCU_READ_UNLOCK_NEED_QS | - RCU_READ_UNLOCK_GOT_QS); + struct rcu_node *rnp_p; + if (rnp->parent == NULL) { /* Only one rcu_node in the tree. */ cpu_quiet_msk_finish(&rcu_preempt_state, flags); @@ -205,9 +218,10 @@ static void rcu_read_unlock_special(struct task_struct *t) /* Report up the rest of the hierarchy. */ mask = rnp->grpmask; spin_unlock_irqrestore(&rnp->lock, flags); - rnp = rnp->parent; - spin_lock_irqsave(&rnp->lock, flags); - cpu_quiet_msk(mask, &rcu_preempt_state, rnp, flags); + rnp_p = rnp->parent; + spin_lock_irqsave(&rnp_p->lock, flags); + WARN_ON_ONCE(rnp->qsmask); + cpu_quiet_msk(mask, &rcu_preempt_state, rnp_p, flags); return; } spin_unlock(&rnp->lock); @@ -258,6 +272,19 @@ static void rcu_print_task_stall(struct rcu_node *rnp) #endif /* #ifdef CONFIG_RCU_CPU_STALL_DETECTOR */ +/* + * Check that the list of blocked tasks for the newly completed grace + * period is in fact empty. It is a serious bug to complete a grace + * period that still has RCU readers blocked! This function must be + * invoked -before- updating this rnp's ->gpnum, and the rnp's ->lock + * must be held by the caller. + */ +static void rcu_preempt_check_blocked_tasks(struct rcu_node *rnp) +{ + WARN_ON_ONCE(!list_empty(&rnp->blocked_tasks[rnp->gpnum & 0x1])); + WARN_ON_ONCE(rnp->qsmask); +} + /* * Check for preempted RCU readers for the specified rcu_node structure. * If the caller needs a reliable answer, it must hold the rcu_node's @@ -280,7 +307,8 @@ static int rcu_preempted_readers(struct rcu_node *rnp) * The caller must hold rnp->lock with irqs disabled. */ static void rcu_preempt_offline_tasks(struct rcu_state *rsp, - struct rcu_node *rnp) + struct rcu_node *rnp, + struct rcu_data *rdp) { int i; struct list_head *lp; @@ -292,6 +320,9 @@ static void rcu_preempt_offline_tasks(struct rcu_state *rsp, WARN_ONCE(1, "Last CPU thought to be offlined?"); return; /* Shouldn't happen: at least one CPU online. */ } + WARN_ON_ONCE(rnp != rdp->mynode && + (!list_empty(&rnp->blocked_tasks[0]) || + !list_empty(&rnp->blocked_tasks[1]))); /* * Move tasks up to root rcu_node. Rely on the fact that the @@ -335,20 +366,12 @@ static void rcu_preempt_check_callbacks(int cpu) struct task_struct *t = current; if (t->rcu_read_lock_nesting == 0) { - t->rcu_read_unlock_special &= - ~(RCU_READ_UNLOCK_NEED_QS | RCU_READ_UNLOCK_GOT_QS); - rcu_preempt_qs_record(cpu); + t->rcu_read_unlock_special &= ~RCU_READ_UNLOCK_NEED_QS; + rcu_preempt_qs(cpu); return; } - if (per_cpu(rcu_preempt_data, cpu).qs_pending) { - if (t->rcu_read_unlock_special & RCU_READ_UNLOCK_GOT_QS) { - rcu_preempt_qs_record(cpu); - t->rcu_read_unlock_special &= ~RCU_READ_UNLOCK_GOT_QS; - } else if (!(t->rcu_read_unlock_special & - RCU_READ_UNLOCK_NEED_QS)) { - t->rcu_read_unlock_special |= RCU_READ_UNLOCK_NEED_QS; - } - } + if (per_cpu(rcu_preempt_data, cpu).qs_pending) + t->rcu_read_unlock_special |= RCU_READ_UNLOCK_NEED_QS; } /* @@ -434,7 +457,7 @@ EXPORT_SYMBOL_GPL(rcu_batches_completed); * Because preemptable RCU does not exist, we never have to check for * CPUs being in quiescent states. */ -static void rcu_preempt_qs(int cpu) +static void rcu_preempt_note_context_switch(int cpu) { } @@ -450,6 +473,16 @@ static void rcu_print_task_stall(struct rcu_node *rnp) #endif /* #ifdef CONFIG_RCU_CPU_STALL_DETECTOR */ +/* + * Because there is no preemptable RCU, there can be no readers blocked, + * so there is no need to check for blocked tasks. So check only for + * bogus qsmask values. + */ +static void rcu_preempt_check_blocked_tasks(struct rcu_node *rnp) +{ + WARN_ON_ONCE(rnp->qsmask); +} + /* * Because preemptable RCU does not exist, there are never any preempted * RCU readers. @@ -466,7 +499,8 @@ static int rcu_preempted_readers(struct rcu_node *rnp) * tasks that were blocked within RCU read-side critical sections. */ static void rcu_preempt_offline_tasks(struct rcu_state *rsp, - struct rcu_node *rnp) + struct rcu_node *rnp, + struct rcu_data *rdp) { } diff --git a/kernel/rcutree_trace.c b/kernel/rcutree_trace.c index 0ea1bff69727..c89f5e9fd173 100644 --- a/kernel/rcutree_trace.c +++ b/kernel/rcutree_trace.c @@ -20,7 +20,7 @@ * Papers: http://www.rdrop.com/users/paulmck/RCU * * For detailed explanation of Read-Copy Update mechanism see - - * Documentation/RCU + * Documentation/RCU * */ #include diff --git a/kernel/sched.c b/kernel/sched.c index 291c8d213d13..91843ba7f237 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -681,15 +681,9 @@ inline void update_rq_clock(struct rq *rq) * This interface allows printk to be called with the runqueue lock * held and know whether or not it is OK to wake up the klogd. */ -int runqueue_is_locked(void) +int runqueue_is_locked(int cpu) { - int cpu = get_cpu(); - struct rq *rq = cpu_rq(cpu); - int ret; - - ret = spin_is_locked(&rq->lock); - put_cpu(); - return ret; + return spin_is_locked(&cpu_rq(cpu)->lock); } /* @@ -6825,23 +6819,8 @@ SYSCALL_DEFINE2(sched_rr_get_interval, pid_t, pid, if (retval) goto out_unlock; - /* - * Time slice is 0 for SCHED_FIFO tasks and for SCHED_OTHER - * tasks that are on an otherwise idle runqueue: - */ - time_slice = 0; - if (p->policy == SCHED_RR) { - time_slice = DEF_TIMESLICE; - } else if (p->policy != SCHED_FIFO) { - struct sched_entity *se = &p->se; - unsigned long flags; - struct rq *rq; + time_slice = p->sched_class->get_rr_interval(p); - rq = task_rq_lock(p, &flags); - if (rq->cfs.load.weight) - time_slice = NS_TO_JIFFIES(sched_slice(&rq->cfs, se)); - task_rq_unlock(rq, &flags); - } read_unlock(&tasklist_lock); jiffies_to_timespec(time_slice, &t); retval = copy_to_user(interval, &t, sizeof(t)) ? -EFAULT : 0; @@ -9171,6 +9150,7 @@ void __init sched_init_smp(void) cpumask_var_t non_isolated_cpus; alloc_cpumask_var(&non_isolated_cpus, GFP_KERNEL); + alloc_cpumask_var(&fallback_doms, GFP_KERNEL); #if defined(CONFIG_NUMA) sched_group_nodes_bycpu = kzalloc(nr_cpu_ids * sizeof(void **), @@ -9202,7 +9182,6 @@ void __init sched_init_smp(void) sched_init_granularity(); free_cpumask_var(non_isolated_cpus); - alloc_cpumask_var(&fallback_doms, GFP_KERNEL); init_sched_rt_class(); } #else diff --git a/kernel/sched_fair.c b/kernel/sched_fair.c index 990b188803ce..ecc637a0d591 100644 --- a/kernel/sched_fair.c +++ b/kernel/sched_fair.c @@ -710,31 +710,28 @@ place_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int initial) if (initial && sched_feat(START_DEBIT)) vruntime += sched_vslice(cfs_rq, se); - if (!initial) { - /* sleeps upto a single latency don't count. */ - if (sched_feat(FAIR_SLEEPERS)) { - unsigned long thresh = sysctl_sched_latency; + /* sleeps up to a single latency don't count. */ + if (!initial && sched_feat(FAIR_SLEEPERS)) { + unsigned long thresh = sysctl_sched_latency; - /* - * Convert the sleeper threshold into virtual time. - * SCHED_IDLE is a special sub-class. We care about - * fairness only relative to other SCHED_IDLE tasks, - * all of which have the same weight. - */ - if (sched_feat(NORMALIZED_SLEEPER) && - (!entity_is_task(se) || - task_of(se)->policy != SCHED_IDLE)) - thresh = calc_delta_fair(thresh, se); + /* + * Convert the sleeper threshold into virtual time. + * SCHED_IDLE is a special sub-class. We care about + * fairness only relative to other SCHED_IDLE tasks, + * all of which have the same weight. + */ + if (sched_feat(NORMALIZED_SLEEPER) && (!entity_is_task(se) || + task_of(se)->policy != SCHED_IDLE)) + thresh = calc_delta_fair(thresh, se); - /* - * Halve their sleep time's effect, to allow - * for a gentler effect of sleepers: - */ - if (sched_feat(GENTLE_FAIR_SLEEPERS)) - thresh >>= 1; + /* + * Halve their sleep time's effect, to allow + * for a gentler effect of sleepers: + */ + if (sched_feat(GENTLE_FAIR_SLEEPERS)) + thresh >>= 1; - vruntime -= thresh; - } + vruntime -= thresh; } /* ensure we never gain time by being placed backwards. */ @@ -1343,7 +1340,8 @@ static int select_task_rq_fair(struct task_struct *p, int sd_flag, int wake_flag int sync = wake_flags & WF_SYNC; if (sd_flag & SD_BALANCE_WAKE) { - if (sched_feat(AFFINE_WAKEUPS)) + if (sched_feat(AFFINE_WAKEUPS) && + cpumask_test_cpu(cpu, &p->cpus_allowed)) want_affine = 1; new_cpu = prev_cpu; } @@ -1941,6 +1939,25 @@ static void moved_group_fair(struct task_struct *p) } #endif +unsigned int get_rr_interval_fair(struct task_struct *task) +{ + struct sched_entity *se = &task->se; + unsigned long flags; + struct rq *rq; + unsigned int rr_interval = 0; + + /* + * Time slice is 0 for SCHED_OTHER tasks that are on an otherwise + * idle runqueue: + */ + rq = task_rq_lock(task, &flags); + if (rq->cfs.load.weight) + rr_interval = NS_TO_JIFFIES(sched_slice(&rq->cfs, se)); + task_rq_unlock(rq, &flags); + + return rr_interval; +} + /* * All the scheduling class methods: */ @@ -1969,6 +1986,8 @@ static const struct sched_class fair_sched_class = { .prio_changed = prio_changed_fair, .switched_to = switched_to_fair, + .get_rr_interval = get_rr_interval_fair, + #ifdef CONFIG_FAIR_GROUP_SCHED .moved_group = moved_group_fair, #endif diff --git a/kernel/sched_idletask.c b/kernel/sched_idletask.c index a8b448af004b..b133a28fcde3 100644 --- a/kernel/sched_idletask.c +++ b/kernel/sched_idletask.c @@ -97,6 +97,11 @@ static void prio_changed_idle(struct rq *rq, struct task_struct *p, check_preempt_curr(rq, p, 0); } +unsigned int get_rr_interval_idle(struct task_struct *task) +{ + return 0; +} + /* * Simple, special scheduling class for the per-CPU idle tasks: */ @@ -122,6 +127,8 @@ static const struct sched_class idle_sched_class = { .set_curr_task = set_curr_task_idle, .task_tick = task_tick_idle, + .get_rr_interval = get_rr_interval_idle, + .prio_changed = prio_changed_idle, .switched_to = switched_to_idle, diff --git a/kernel/sched_rt.c b/kernel/sched_rt.c index 13de7126a6ab..a4d790cddb19 100644 --- a/kernel/sched_rt.c +++ b/kernel/sched_rt.c @@ -1734,6 +1734,17 @@ static void set_curr_task_rt(struct rq *rq) dequeue_pushable_task(rq, p); } +unsigned int get_rr_interval_rt(struct task_struct *task) +{ + /* + * Time slice is 0 for SCHED_FIFO tasks + */ + if (task->policy == SCHED_RR) + return DEF_TIMESLICE; + else + return 0; +} + static const struct sched_class rt_sched_class = { .next = &fair_sched_class, .enqueue_task = enqueue_task_rt, @@ -1762,6 +1773,8 @@ static const struct sched_class rt_sched_class = { .set_curr_task = set_curr_task_rt, .task_tick = task_tick_rt, + .get_rr_interval = get_rr_interval_rt, + .prio_changed = prio_changed_rt, .switched_to = switched_to_rt, }; diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c index cc615f84751b..c71e91bf7372 100644 --- a/kernel/trace/ftrace.c +++ b/kernel/trace/ftrace.c @@ -2414,11 +2414,9 @@ unsigned long ftrace_graph_funcs[FTRACE_GRAPH_MAX_FUNCS] __read_mostly; static void * __g_next(struct seq_file *m, loff_t *pos) { - unsigned long *array = m->private; - if (*pos >= ftrace_graph_count) return NULL; - return &array[*pos]; + return &ftrace_graph_funcs[*pos]; } static void * @@ -2482,16 +2480,10 @@ ftrace_graph_open(struct inode *inode, struct file *file) ftrace_graph_count = 0; memset(ftrace_graph_funcs, 0, sizeof(ftrace_graph_funcs)); } + mutex_unlock(&graph_lock); - if (file->f_mode & FMODE_READ) { + if (file->f_mode & FMODE_READ) ret = seq_open(file, &ftrace_graph_seq_ops); - if (!ret) { - struct seq_file *m = file->private_data; - m->private = ftrace_graph_funcs; - } - } else - file->private_data = ftrace_graph_funcs; - mutex_unlock(&graph_lock); return ret; } @@ -2560,7 +2552,6 @@ ftrace_graph_write(struct file *file, const char __user *ubuf, size_t cnt, loff_t *ppos) { struct trace_parser parser; - unsigned long *array; size_t read = 0; ssize_t ret; @@ -2574,12 +2565,6 @@ ftrace_graph_write(struct file *file, const char __user *ubuf, goto out; } - if (file->f_mode & FMODE_READ) { - struct seq_file *m = file->private_data; - array = m->private; - } else - array = file->private_data; - if (trace_parser_get_init(&parser, FTRACE_BUFF_MAX)) { ret = -ENOMEM; goto out; @@ -2591,7 +2576,7 @@ ftrace_graph_write(struct file *file, const char __user *ubuf, parser.buffer[parser.idx] = 0; /* we allow only one expression at a time */ - ret = ftrace_set_func(array, &ftrace_graph_count, + ret = ftrace_set_func(ftrace_graph_funcs, &ftrace_graph_count, parser.buffer); if (ret) goto out; diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c index fd52a19dd172..a35925d222ba 100644 --- a/kernel/trace/trace.c +++ b/kernel/trace/trace.c @@ -125,13 +125,13 @@ int ftrace_dump_on_oops; static int tracing_set_tracer(const char *buf); -#define BOOTUP_TRACER_SIZE 100 -static char bootup_tracer_buf[BOOTUP_TRACER_SIZE] __initdata; +#define MAX_TRACER_SIZE 100 +static char bootup_tracer_buf[MAX_TRACER_SIZE] __initdata; static char *default_bootup_tracer; static int __init set_ftrace(char *str) { - strncpy(bootup_tracer_buf, str, BOOTUP_TRACER_SIZE); + strncpy(bootup_tracer_buf, str, MAX_TRACER_SIZE); default_bootup_tracer = bootup_tracer_buf; /* We are using ftrace early, expand it */ ring_buffer_expanded = 1; @@ -241,13 +241,6 @@ static struct tracer *trace_types __read_mostly; /* current_trace points to the tracer that is currently active */ static struct tracer *current_trace __read_mostly; -/* - * max_tracer_type_len is used to simplify the allocating of - * buffers to read userspace tracer names. We keep track of - * the longest tracer name registered. - */ -static int max_tracer_type_len; - /* * trace_types_lock is used to protect the trace_types list. * This lock is also used to keep user access serialized. @@ -275,12 +268,18 @@ static DEFINE_SPINLOCK(tracing_start_lock); */ void trace_wake_up(void) { + int cpu; + + if (trace_flags & TRACE_ITER_BLOCK) + return; /* * The runqueue_is_locked() can fail, but this is the best we * have for now: */ - if (!(trace_flags & TRACE_ITER_BLOCK) && !runqueue_is_locked()) + cpu = get_cpu(); + if (!runqueue_is_locked(cpu)) wake_up(&trace_wait); + put_cpu(); } static int __init set_buf_size(char *str) @@ -619,7 +618,6 @@ __releases(kernel_lock) __acquires(kernel_lock) { struct tracer *t; - int len; int ret = 0; if (!type->name) { @@ -627,6 +625,11 @@ __acquires(kernel_lock) return -1; } + if (strlen(type->name) > MAX_TRACER_SIZE) { + pr_info("Tracer has a name longer than %d\n", MAX_TRACER_SIZE); + return -1; + } + /* * When this gets called we hold the BKL which means that * preemption is disabled. Various trace selftests however @@ -641,7 +644,7 @@ __acquires(kernel_lock) for (t = trace_types; t; t = t->next) { if (strcmp(type->name, t->name) == 0) { /* already found */ - pr_info("Trace %s already registered\n", + pr_info("Tracer %s already registered\n", type->name); ret = -1; goto out; @@ -692,9 +695,6 @@ __acquires(kernel_lock) type->next = trace_types; trace_types = type; - len = strlen(type->name); - if (len > max_tracer_type_len) - max_tracer_type_len = len; out: tracing_selftest_running = false; @@ -703,7 +703,7 @@ __acquires(kernel_lock) if (ret || !default_bootup_tracer) goto out_unlock; - if (strncmp(default_bootup_tracer, type->name, BOOTUP_TRACER_SIZE)) + if (strncmp(default_bootup_tracer, type->name, MAX_TRACER_SIZE)) goto out_unlock; printk(KERN_INFO "Starting tracer '%s'\n", type->name); @@ -725,14 +725,13 @@ __acquires(kernel_lock) void unregister_tracer(struct tracer *type) { struct tracer **t; - int len; mutex_lock(&trace_types_lock); for (t = &trace_types; *t; t = &(*t)->next) { if (*t == type) goto found; } - pr_info("Trace %s not registered\n", type->name); + pr_info("Tracer %s not registered\n", type->name); goto out; found: @@ -745,17 +744,7 @@ void unregister_tracer(struct tracer *type) current_trace->stop(&global_trace); current_trace = &nop_trace; } - - if (strlen(type->name) != max_tracer_type_len) - goto out; - - max_tracer_type_len = 0; - for (t = &trace_types; *t; t = &(*t)->next) { - len = strlen((*t)->name); - if (len > max_tracer_type_len) - max_tracer_type_len = len; - } - out: +out: mutex_unlock(&trace_types_lock); } @@ -2604,7 +2593,7 @@ static ssize_t tracing_set_trace_read(struct file *filp, char __user *ubuf, size_t cnt, loff_t *ppos) { - char buf[max_tracer_type_len+2]; + char buf[MAX_TRACER_SIZE+2]; int r; mutex_lock(&trace_types_lock); @@ -2754,15 +2743,15 @@ static ssize_t tracing_set_trace_write(struct file *filp, const char __user *ubuf, size_t cnt, loff_t *ppos) { - char buf[max_tracer_type_len+1]; + char buf[MAX_TRACER_SIZE+1]; int i; size_t ret; int err; ret = cnt; - if (cnt > max_tracer_type_len) - cnt = max_tracer_type_len; + if (cnt > MAX_TRACER_SIZE) + cnt = MAX_TRACER_SIZE; if (copy_from_user(&buf, ubuf, cnt)) return -EFAULT; diff --git a/kernel/trace/trace_event_profile.c b/kernel/trace/trace_event_profile.c index 55a25c933d15..dd44b8768867 100644 --- a/kernel/trace/trace_event_profile.c +++ b/kernel/trace/trace_event_profile.c @@ -8,6 +8,57 @@ #include #include "trace.h" +/* + * We can't use a size but a type in alloc_percpu() + * So let's create a dummy type that matches the desired size + */ +typedef struct {char buf[FTRACE_MAX_PROFILE_SIZE];} profile_buf_t; + +char *trace_profile_buf; +EXPORT_SYMBOL_GPL(trace_profile_buf); + +char *trace_profile_buf_nmi; +EXPORT_SYMBOL_GPL(trace_profile_buf_nmi); + +/* Count the events in use (per event id, not per instance) */ +static int total_profile_count; + +static int ftrace_profile_enable_event(struct ftrace_event_call *event) +{ + char *buf; + int ret = -ENOMEM; + + if (atomic_inc_return(&event->profile_count)) + return 0; + + if (!total_profile_count++) { + buf = (char *)alloc_percpu(profile_buf_t); + if (!buf) + goto fail_buf; + + rcu_assign_pointer(trace_profile_buf, buf); + + buf = (char *)alloc_percpu(profile_buf_t); + if (!buf) + goto fail_buf_nmi; + + rcu_assign_pointer(trace_profile_buf_nmi, buf); + } + + ret = event->profile_enable(); + if (!ret) + return 0; + + kfree(trace_profile_buf_nmi); +fail_buf_nmi: + kfree(trace_profile_buf); +fail_buf: + total_profile_count--; + atomic_dec(&event->profile_count); + + return ret; +} + int ftrace_profile_enable(int event_id) { struct ftrace_event_call *event; @@ -17,7 +68,7 @@ int ftrace_profile_enable(int event_id) list_for_each_entry(event, &ftrace_events, list) { if (event->id == event_id && event->profile_enable && try_module_get(event->mod)) { - ret = event->profile_enable(event); + ret = ftrace_profile_enable_event(event); break; } } @@ -26,6 +77,33 @@ int ftrace_profile_enable(int event_id) return ret; } +static void ftrace_profile_disable_event(struct ftrace_event_call *event) +{ + char *buf, *nmi_buf; + + if (!atomic_add_negative(-1, &event->profile_count)) + return; + + event->profile_disable(); + + if (!--total_profile_count) { + buf = trace_profile_buf; + rcu_assign_pointer(trace_profile_buf, NULL); + + nmi_buf = trace_profile_buf_nmi; + rcu_assign_pointer(trace_profile_buf_nmi, NULL); + + /* + * Ensure every events in profiling have finished before + * releasing the buffers + */ + synchronize_sched(); + + free_percpu(buf); + free_percpu(nmi_buf); + } +} + void ftrace_profile_disable(int event_id) { struct ftrace_event_call *event; @@ -33,7 +111,7 @@ void ftrace_profile_disable(int event_id) mutex_lock(&event_mutex); list_for_each_entry(event, &ftrace_events, list) { if (event->id == event_id) { - event->profile_disable(event); + ftrace_profile_disable_event(event); module_put(event->mod); break; } diff --git a/kernel/trace/trace_events.c b/kernel/trace/trace_events.c index 56c260b83a9c..6f03c8a1105e 100644 --- a/kernel/trace/trace_events.c +++ b/kernel/trace/trace_events.c @@ -271,42 +271,32 @@ ftrace_event_write(struct file *file, const char __user *ubuf, static void * t_next(struct seq_file *m, void *v, loff_t *pos) { - struct list_head *list = m->private; - struct ftrace_event_call *call; + struct ftrace_event_call *call = v; (*pos)++; - for (;;) { - if (list == &ftrace_events) - return NULL; - - call = list_entry(list, struct ftrace_event_call, list); - + list_for_each_entry_continue(call, &ftrace_events, list) { /* * The ftrace subsystem is for showing formats only. * They can not be enabled or disabled via the event files. */ if (call->regfunc) - break; - - list = list->next; + return call; } - m->private = list->next; - - return call; + return NULL; } static void *t_start(struct seq_file *m, loff_t *pos) { - struct ftrace_event_call *call = NULL; + struct ftrace_event_call *call; loff_t l; mutex_lock(&event_mutex); - m->private = ftrace_events.next; + call = list_entry(&ftrace_events, struct ftrace_event_call, list); for (l = 0; l <= *pos; ) { - call = t_next(m, NULL, &l); + call = t_next(m, call, &l); if (!call) break; } @@ -316,37 +306,28 @@ static void *t_start(struct seq_file *m, loff_t *pos) static void * s_next(struct seq_file *m, void *v, loff_t *pos) { - struct list_head *list = m->private; - struct ftrace_event_call *call; + struct ftrace_event_call *call = v; (*pos)++; - retry: - if (list == &ftrace_events) - return NULL; - - call = list_entry(list, struct ftrace_event_call, list); - - if (!call->enabled) { - list = list->next; - goto retry; + list_for_each_entry_continue(call, &ftrace_events, list) { + if (call->enabled) + return call; } - m->private = list->next; - - return call; + return NULL; } static void *s_start(struct seq_file *m, loff_t *pos) { - struct ftrace_event_call *call = NULL; + struct ftrace_event_call *call; loff_t l; mutex_lock(&event_mutex); - m->private = ftrace_events.next; + call = list_entry(&ftrace_events, struct ftrace_event_call, list); for (l = 0; l <= *pos; ) { - call = s_next(m, NULL, &l); + call = s_next(m, call, &l); if (!call) break; } diff --git a/kernel/trace/trace_printk.c b/kernel/trace/trace_printk.c index 687699d365ae..2547d8813cf0 100644 --- a/kernel/trace/trace_printk.c +++ b/kernel/trace/trace_printk.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff --git a/kernel/trace/trace_syscalls.c b/kernel/trace/trace_syscalls.c index 233f3483ac83..9fbce6c9d2e1 100644 --- a/kernel/trace/trace_syscalls.c +++ b/kernel/trace/trace_syscalls.c @@ -384,10 +384,13 @@ static int sys_prof_refcount_exit; static void prof_syscall_enter(struct pt_regs *regs, long id) { - struct syscall_trace_enter *rec; struct syscall_metadata *sys_data; + struct syscall_trace_enter *rec; + unsigned long flags; + char *raw_data; int syscall_nr; int size; + int cpu; syscall_nr = syscall_get_nr(current, regs); if (!test_bit(syscall_nr, enabled_prof_enter_syscalls)) @@ -402,20 +405,38 @@ static void prof_syscall_enter(struct pt_regs *regs, long id) size = ALIGN(size + sizeof(u32), sizeof(u64)); size -= sizeof(u32); - do { - char raw_data[size]; + if (WARN_ONCE(size > FTRACE_MAX_PROFILE_SIZE, + "profile buffer not large enough")) + return; + + /* Protect the per cpu buffer, begin the rcu read side */ + local_irq_save(flags); - /* zero the dead bytes from align to not leak stack to user */ - *(u64 *)(&raw_data[size - sizeof(u64)]) = 0ULL; + cpu = smp_processor_id(); + + if (in_nmi()) + raw_data = rcu_dereference(trace_profile_buf_nmi); + else + raw_data = rcu_dereference(trace_profile_buf); + + if (!raw_data) + goto end; - rec = (struct syscall_trace_enter *) raw_data; - tracing_generic_entry_update(&rec->ent, 0, 0); - rec->ent.type = sys_data->enter_id; - rec->nr = syscall_nr; - syscall_get_arguments(current, regs, 0, sys_data->nb_args, - (unsigned long *)&rec->args); - perf_tp_event(sys_data->enter_id, 0, 1, rec, size); - } while(0); + raw_data = per_cpu_ptr(raw_data, cpu); + + /* zero the dead bytes from align to not leak stack to user */ + *(u64 *)(&raw_data[size - sizeof(u64)]) = 0ULL; + + rec = (struct syscall_trace_enter *) raw_data; + tracing_generic_entry_update(&rec->ent, 0, 0); + rec->ent.type = sys_data->enter_id; + rec->nr = syscall_nr; + syscall_get_arguments(current, regs, 0, sys_data->nb_args, + (unsigned long *)&rec->args); + perf_tp_event(sys_data->enter_id, 0, 1, rec, size); + +end: + local_irq_restore(flags); } int reg_prof_syscall_enter(char *name) @@ -460,8 +481,12 @@ void unreg_prof_syscall_enter(char *name) static void prof_syscall_exit(struct pt_regs *regs, long ret) { struct syscall_metadata *sys_data; - struct syscall_trace_exit rec; + struct syscall_trace_exit *rec; + unsigned long flags; int syscall_nr; + char *raw_data; + int size; + int cpu; syscall_nr = syscall_get_nr(current, regs); if (!test_bit(syscall_nr, enabled_prof_exit_syscalls)) @@ -471,12 +496,46 @@ static void prof_syscall_exit(struct pt_regs *regs, long ret) if (!sys_data) return; - tracing_generic_entry_update(&rec.ent, 0, 0); - rec.ent.type = sys_data->exit_id; - rec.nr = syscall_nr; - rec.ret = syscall_get_return_value(current, regs); + /* We can probably do that at build time */ + size = ALIGN(sizeof(*rec) + sizeof(u32), sizeof(u64)); + size -= sizeof(u32); - perf_tp_event(sys_data->exit_id, 0, 1, &rec, sizeof(rec)); + /* + * Impossible, but be paranoid with the future + * How to put this check outside runtime? + */ + if (WARN_ONCE(size > FTRACE_MAX_PROFILE_SIZE, + "exit event has grown above profile buffer size")) + return; + + /* Protect the per cpu buffer, begin the rcu read side */ + local_irq_save(flags); + cpu = smp_processor_id(); + + if (in_nmi()) + raw_data = rcu_dereference(trace_profile_buf_nmi); + else + raw_data = rcu_dereference(trace_profile_buf); + + if (!raw_data) + goto end; + + raw_data = per_cpu_ptr(raw_data, cpu); + + /* zero the dead bytes from align to not leak stack to user */ + *(u64 *)(&raw_data[size - sizeof(u64)]) = 0ULL; + + rec = (struct syscall_trace_exit *)raw_data; + + tracing_generic_entry_update(&rec->ent, 0, 0); + rec->ent.type = sys_data->exit_id; + rec->nr = syscall_nr; + rec->ret = syscall_get_return_value(current, regs); + + perf_tp_event(sys_data->exit_id, 0, 1, rec, size); + +end: + local_irq_restore(flags); } int reg_prof_syscall_exit(char *name) diff --git a/mm/page-writeback.c b/mm/page-writeback.c index 1eea4fa0d410..d1ba46441053 100644 --- a/mm/page-writeback.c +++ b/mm/page-writeback.c @@ -485,6 +485,7 @@ static void balance_dirty_pages(struct address_space *mapping) unsigned long bdi_thresh; unsigned long pages_written = 0; unsigned long write_chunk = sync_writeback_pages(); + unsigned long pause = 1; struct backing_dev_info *bdi = mapping->backing_dev_info; @@ -561,7 +562,15 @@ static void balance_dirty_pages(struct address_space *mapping) if (pages_written >= write_chunk) break; /* We've done our duty */ - schedule_timeout(1); + schedule_timeout_interruptible(pause); + + /* + * Increase the delay for each loop, up to our previous + * default of taking a 100ms nap. + */ + pause <<= 1; + if (pause > HZ / 10) + pause = HZ / 10; } if (bdi_nr_reclaimable + bdi_nr_writeback < bdi_thresh && diff --git a/samples/Kconfig b/samples/Kconfig index 428b065ba695..b92bde3c6a89 100644 --- a/samples/Kconfig +++ b/samples/Kconfig @@ -7,12 +7,6 @@ menuconfig SAMPLES if SAMPLES -config SAMPLE_MARKERS - tristate "Build markers examples -- loadable modules only" - depends on MARKERS && m - help - This build markers example modules. - config SAMPLE_TRACEPOINTS tristate "Build tracepoints examples -- loadable modules only" depends on TRACEPOINTS && m diff --git a/samples/Makefile b/samples/Makefile index 13e4b470b539..43343a03b1f4 100644 --- a/samples/Makefile +++ b/samples/Makefile @@ -1,3 +1,3 @@ # Makefile for Linux samples code -obj-$(CONFIG_SAMPLES) += markers/ kobject/ kprobes/ tracepoints/ trace_events/ +obj-$(CONFIG_SAMPLES) += kobject/ kprobes/ tracepoints/ trace_events/ diff --git a/samples/markers/Makefile b/samples/markers/Makefile deleted file mode 100644 index 6d7231265f0f..000000000000 --- a/samples/markers/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# builds the kprobes example kernel modules; -# then to use one (as root): insmod - -obj-$(CONFIG_SAMPLE_MARKERS) += probe-example.o marker-example.o diff --git a/samples/markers/marker-example.c b/samples/markers/marker-example.c deleted file mode 100644 index e9cd9c0bc84f..000000000000 --- a/samples/markers/marker-example.c +++ /dev/null @@ -1,53 +0,0 @@ -/* marker-example.c - * - * Executes a marker when /proc/marker-example is opened. - * - * (C) Copyright 2007 Mathieu Desnoyers - * - * This file is released under the GPLv2. - * See the file COPYING for more details. - */ - -#include -#include -#include -#include - -struct proc_dir_entry *pentry_example; - -static int my_open(struct inode *inode, struct file *file) -{ - int i; - - trace_mark(subsystem_event, "integer %d string %s", 123, - "example string"); - for (i = 0; i < 10; i++) - trace_mark(subsystem_eventb, MARK_NOARGS); - return -EPERM; -} - -static struct file_operations mark_ops = { - .open = my_open, -}; - -static int __init example_init(void) -{ - printk(KERN_ALERT "example init\n"); - pentry_example = proc_create("marker-example", 0444, NULL, &mark_ops); - if (!pentry_example) - return -EPERM; - return 0; -} - -static void __exit example_exit(void) -{ - printk(KERN_ALERT "example exit\n"); - remove_proc_entry("marker-example", NULL); -} - -module_init(example_init) -module_exit(example_exit) - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mathieu Desnoyers"); -MODULE_DESCRIPTION("Marker example"); diff --git a/samples/markers/probe-example.c b/samples/markers/probe-example.c deleted file mode 100644 index 2dfb3b32937e..000000000000 --- a/samples/markers/probe-example.c +++ /dev/null @@ -1,92 +0,0 @@ -/* probe-example.c - * - * Connects two functions to marker call sites. - * - * (C) Copyright 2007 Mathieu Desnoyers - * - * This file is released under the GPLv2. - * See the file COPYING for more details. - */ - -#include -#include -#include -#include -#include - -struct probe_data { - const char *name; - const char *format; - marker_probe_func *probe_func; -}; - -void probe_subsystem_event(void *probe_data, void *call_data, - const char *format, va_list *args) -{ - /* Declare args */ - unsigned int value; - const char *mystr; - - /* Assign args */ - value = va_arg(*args, typeof(value)); - mystr = va_arg(*args, typeof(mystr)); - - /* Call printk */ - printk(KERN_INFO "Value %u, string %s\n", value, mystr); - - /* or count, check rights, serialize data in a buffer */ -} - -atomic_t eventb_count = ATOMIC_INIT(0); - -void probe_subsystem_eventb(void *probe_data, void *call_data, - const char *format, va_list *args) -{ - /* Increment counter */ - atomic_inc(&eventb_count); -} - -static struct probe_data probe_array[] = -{ - { .name = "subsystem_event", - .format = "integer %d string %s", - .probe_func = probe_subsystem_event }, - { .name = "subsystem_eventb", - .format = MARK_NOARGS, - .probe_func = probe_subsystem_eventb }, -}; - -static int __init probe_init(void) -{ - int result; - int i; - - for (i = 0; i < ARRAY_SIZE(probe_array); i++) { - result = marker_probe_register(probe_array[i].name, - probe_array[i].format, - probe_array[i].probe_func, &probe_array[i]); - if (result) - printk(KERN_INFO "Unable to register probe %s\n", - probe_array[i].name); - } - return 0; -} - -static void __exit probe_fini(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(probe_array); i++) - marker_probe_unregister(probe_array[i].name, - probe_array[i].probe_func, &probe_array[i]); - printk(KERN_INFO "Number of event b : %u\n", - atomic_read(&eventb_count)); - marker_synchronize_unregister(); -} - -module_init(probe_init); -module_exit(probe_fini); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mathieu Desnoyers"); -MODULE_DESCRIPTION("SUBSYSTEM Probe"); diff --git a/scripts/Makefile.modpost b/scripts/Makefile.modpost index f4053dc7b5d6..8f14c81abbc7 100644 --- a/scripts/Makefile.modpost +++ b/scripts/Makefile.modpost @@ -13,7 +13,6 @@ # 2) modpost is then used to # 3) create one .mod.c file pr. module # 4) create one Module.symvers file with CRC for all exported symbols -# 4a) [CONFIG_MARKERS] create one Module.markers file listing defined markers # 5) compile all .mod.c files # 6) final link of the module to a file @@ -59,10 +58,6 @@ include scripts/Makefile.lib kernelsymfile := $(objtree)/Module.symvers modulesymfile := $(firstword $(KBUILD_EXTMOD))/Module.symvers -kernelmarkersfile := $(objtree)/Module.markers -modulemarkersfile := $(firstword $(KBUILD_EXTMOD))/Module.markers - -markersfile = $(if $(KBUILD_EXTMOD),$(modulemarkersfile),$(kernelmarkersfile)) # Step 1), find all modules listed in $(MODVERDIR)/ __modules := $(sort $(shell grep -h '\.ko' /dev/null $(wildcard $(MODVERDIR)/*.mod))) @@ -85,8 +80,6 @@ modpost = scripts/mod/modpost \ $(if $(KBUILD_EXTRA_SYMBOLS), $(patsubst %, -e %,$(KBUILD_EXTRA_SYMBOLS))) \ $(if $(KBUILD_EXTMOD),-o $(modulesymfile)) \ $(if $(CONFIG_DEBUG_SECTION_MISMATCH),,-S) \ - $(if $(CONFIG_MARKERS),-K $(kernelmarkersfile)) \ - $(if $(CONFIG_MARKERS),-M $(markersfile)) \ $(if $(KBUILD_EXTMOD)$(KBUILD_MODPOST_WARN),-w) \ $(if $(cross_build),-c) @@ -101,17 +94,12 @@ quiet_cmd_kernel-mod = MODPOST $@ cmd_kernel-mod = $(modpost) $@ vmlinux.o: FORCE - @rm -fr $(kernelmarkersfile) $(call cmd,kernel-mod) # Declare generated files as targets for modpost $(symverfile): __modpost ; $(modules:.ko=.mod.c): __modpost ; -ifdef CONFIG_MARKERS -$(markersfile): __modpost ; -endif - # Step 5), compile all *.mod.c files