From: Jon Hunter <jonathanh@nvidia.com>
Date: Tue, 5 May 2015 14:17:52 +0000 (+0100)
Subject: serial: tegra: Correct delay after TX flush
X-Git-Tag: omap-for-v4.2/wakeirq-drivers-v2^2~74
X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=245c0278ab2a2e3d0360296710b4c285291469b5;p=pandora-kernel.git

serial: tegra: Correct delay after TX flush

For all tegra devices (up to t210), there is a hardware issue that
requires software to wait for 32 UART clock periods for the flush
to propagate otherwise TX data could be post. Add a helper function
to wait for N UART clock periods and update delay following FIFO
flush to be 32 UART clock cycles.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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