From: Paul Walmsley <paul@pwsan.com>
Date: Mon, 15 Jun 2009 08:00:43 +0000 (-0600)
Subject: OMAP3 clock: add a short delay when lowering CORE clk rate
X-Git-Tag: v2.6.32-omap1~11^2^2~1^2^2^2^2^2~8^2^2~18^2~2^2^2~2^2^2^2^2~16^2^2~8^2^2~7^2~75^2~6
X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2303320efd1bedf78d4fca7585ca3b0cc3f1997b;p=pandora-kernel.git

OMAP3 clock: add a short delay when lowering CORE clk rate

When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
divider, add a short delay before returning to SDRAM to allow the SDRC
time to stabilize.  Without this delay, the system is prone to random
panics upon re-entering SDRAM.

This time delay varies based on MPU frequency.  At 500MHz MPU frequency at
room temperature, 64 loops seems to work okay; so add another 32 loops for
environmental and process variation.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---

Reading git-diff-tree failed