From: Paul Walmsley <paul@pwsan.com>
Date: Mon, 15 Jun 2009 08:00:44 +0000 (-0600)
Subject: OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change
X-Git-Tag: v2.6.32-omap1~11^2^2~1^2^2^2^2^2~8^2^2~18^2~2^2^2~2^2^2^2^2~16^2^2~8^2^2~7^2~77^2~5
X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1aa1d190b89541b94758420b000dd5f58e867557;p=pandora-kernel.git

OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change

Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency.  Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
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