From: Russell King Date: Sun, 20 Mar 2011 09:32:12 +0000 (+0000) Subject: Merge branches 'fixes', 'pgt-next' and 'versatile' into devel X-Git-Tag: v2.6.39-rc1~100^2~2 X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=196f020fbbb83d246960548e73a40fd08f3e7866;hp=-c;p=pandora-kernel.git Merge branches 'fixes', 'pgt-next' and 'versatile' into devel --- 196f020fbbb83d246960548e73a40fd08f3e7866 diff --combined arch/arm/Kconfig index e34bf0272da4,166efa2a19cd,db524e75c4a2,a6ccef6d9d72..f785b49bf1f5 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@@@@ -2,20 -2,20 -2,18 -2,20 +2,20 @@@@@ config AR bool default y select HAVE_AOUT + select HAVE_DMA_API_DEBUG select HAVE_IDE select HAVE_MEMBLOCK select RTC_LIB select SYS_SUPPORTS_APM_EMULATION --- select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI) +++ select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) select HAVE_OPROFILE if (HAVE_PERF_EVENTS) select HAVE_ARCH_KGDB - select HAVE_KPROBES if (!XIP_KERNEL) + select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL) select HAVE_KRETPROBES if (HAVE_KPROBES) select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) + select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) select HAVE_GENERIC_DMA_COHERENT select HAVE_KERNEL_GZIP select HAVE_KERNEL_LZO @@@@@ -24,10 -24,10 -22,7 -24,10 +24,10 @@@@@ select HAVE_PERF_EVENTS select PERF_USE_VMALLOC select HAVE_REGS_AND_STACK_ACCESS_API --- select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7)) +++ select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) + select HAVE_C_RECORDMCOUNT + select HAVE_GENERIC_HARDIRQS + select HAVE_SPARSE_IRQ help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and @@@@@ -39,15 -39,15 -34,9 -39,15 +39,15 @@@@@ config HAVE_PWM bool + config MIGHT_HAVE_PCI + bool + config SYS_SUPPORTS_APM_EMULATION bool + config HAVE_SCHED_CLOCK + bool + config GENERIC_GPIO bool @@@@@ -63,10 -63,6 -52,6 -63,6 +63,10 @@@@@ config GENERIC_CLOCKEVENTS_BROADCAS depends on GENERIC_CLOCKEVENTS default y if SMP +++config KTIME_SCALAR +++ bool +++ default y +++ config HAVE_TCM bool select GENERIC_ALLOCATOR @@@@@ -103,6 -99,6 -88,10 -99,6 +103,6 @@@@@ config MC (and especially the web page given there) before attempting to build an MCA bus kernel. - config GENERIC_HARDIRQS - bool - default y - config STACKTRACE_SUPPORT bool default y @@@@@ -182,6 -178,11 -171,14 -178,11 +182,6 @@@@@ config FI config ARCH_MTD_XIP bool - config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - ---config ARM_L1_CACHE_SHIFT_6 --- bool --- help --- Setting ARM L1 cache line size to 64 Bytes. --- config VECTORS_BASE hex default 0xffff0000 if MMU || CPU_HIGH_VECTOR @@@@@ -190,22 -191,6 -187,6 -191,6 +190,22 @@@@@ help The base address of exception vectors. +++config ARM_PATCH_PHYS_VIRT +++ bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)" +++ depends on EXPERIMENTAL +++ depends on !XIP_KERNEL && MMU +++ depends on !ARCH_REALVIEW || !SPARSEMEM +++ help +++ Patch phys-to-virt translation functions at runtime according to +++ the position of the kernel in system memory. +++ +++ This can only be used with non-XIP with MMU kernels where +++ the base of physical memory is at a 16MB boundary. +++ +++config ARM_PATCH_PHYS_VIRT_16BIT +++ def_bool y +++ depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM +++ source "init/Kconfig" source "kernel/Kconfig.freezer" @@@@@ -227,26 -212,35 -208,34 -212,36 +227,27 @@@@@ choic prompt "ARM system type" default ARCH_VERSATILE ---config ARCH_AAEC2000 --- bool "Agilent AAEC-2000 based" --- select CPU_ARM920T --- select ARM_AMBA --- select HAVE_CLK --- select ARCH_USES_GETTIMEOFFSET --- help --- This enables support for systems based on the Agilent AAEC-2000 --- config ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" select ARM_AMBA select ARCH_HAS_CPUFREQ - select COMMON_CLKDEV + select CLKDEV_LOOKUP select ICST select GENERIC_CLOCKEVENTS select PLAT_VERSATILE +++ select PLAT_VERSATILE_FPGA_IRQ help Support for ARM's Integrator platform. config ARCH_REALVIEW bool "ARM Ltd. RealView family" select ARM_AMBA - select COMMON_CLKDEV + select CLKDEV_LOOKUP -- select HAVE_SCHED_CLOCK select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB select PLAT_VERSATILE +++ select PLAT_VERSATILE_CLCD select ARM_TIMER_SP804 select GPIO_PL061 if GPIOLIB help @@@@@ -256,12 -250,12 -245,11 -251,13 +257,13 @@@@@ config ARCH_VERSATIL bool "ARM Ltd. Versatile family" select ARM_AMBA select ARM_VIC - select COMMON_CLKDEV + select CLKDEV_LOOKUP -- select HAVE_SCHED_CLOCK select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB select PLAT_VERSATILE +++ select PLAT_VERSATILE_CLCD +++ select PLAT_VERSATILE_FPGA_IRQ select ARM_TIMER_SP804 help This enables support for ARM Ltd Versatile board. @@@@@ -271,12 -265,12 -259,11 -267,13 +273,13 @@@@@ config ARCH_VEXPRES select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_AMBA select ARM_TIMER_SP804 - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select HAVE_CLK -- select HAVE_SCHED_CLOCK +++ select HAVE_PATA_PLATFORM select ICST select PLAT_VERSATILE +++ select PLAT_VERSATILE_CLCD help This enables support for the ARM Ltd Versatile Express boards. @@@@@ -293,7 -287,7 -280,7 -290,7 +296,7 @@@@@ config ARCH_BCMRIN depends on MMU select CPU_V6 select ARM_AMBA - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB help @@@@@ -311,7 -305,7 -298,6 -308,7 +314,7 @@@@@ config ARCH_CNS3XX select CPU_V6 select GENERIC_CLOCKEVENTS select ARM_GIC + select MIGHT_HAVE_PCI select PCI_DOMAINS if PCI help Support for Cavium Networks CNS3XXX platform. @@@@@ -341,7 -335,7 -327,7 -338,7 +344,7 @@@@@ config ARCH_EP93X select CPU_ARM920T select ARM_AMBA select ARM_VIC - select COMMON_CLKDEV + select CLKDEV_LOOKUP select ARCH_REQUIRE_GPIOLIB select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_USES_GETTIMEOFFSET @@@@@ -352,7 -346,7 -338,7 -349,7 +355,7 @@@@@ config ARCH_FOOTBRIDG bool "FootBridge" select CPU_SA110 select FOOTBRIDGE --- select ARCH_USES_GETTIMEOFFSET +++ select GENERIC_CLOCKEVENTS help Support for systems based on the DC21285 companion chip ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. @@@@@ -361,22 -355,22 -347,14 -358,22 +364,22 @@@@@ config ARCH_MX bool "Freescale MXC/iMX-based" select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB - select COMMON_CLKDEV + select CLKDEV_LOOKUP help Support for Freescale MXC/iMX-based family of processors + config ARCH_MXS + bool "Freescale MXS-based" + select GENERIC_CLOCKEVENTS + select ARCH_REQUIRE_GPIOLIB + select CLKDEV_LOOKUP + help + Support for Freescale MXS-based family of processors + config ARCH_STMP3XXX bool "Freescale STMP3xxx" select CPU_ARM926T - select COMMON_CLKDEV + select CLKDEV_LOOKUP select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS select USB_ARCH_HAS_EHCI @@@@@ -455,15 -449,14 -433,12 -452,14 +458,15 @@@@@ config ARCH_IXP4X select CPU_XSCALE select GENERIC_GPIO select GENERIC_CLOCKEVENTS + select HAVE_SCHED_CLOCK + select MIGHT_HAVE_PCI select DMABOUNCE if PCI help Support for Intel's IXP4XX (XScale) family of processors. config ARCH_DOVE bool "Marvell Dove" +++ select CPU_V6K select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS @@@@@ -497,7 -490,7 -472,7 -493,7 +500,7 @@@@@ config ARCH_LPC32X select HAVE_IDE select ARM_AMBA select USB_ARCH_HAS_OHCI - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_TIME select GENERIC_CLOCKEVENTS help @@@@@ -531,9 -524,9 -506,8 -527,9 +534,9 @@@@@ config ARCH_MM bool "Marvell PXA168/910/MMP2" depends on MMU select ARCH_REQUIRE_GPIOLIB - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS + select HAVE_SCHED_CLOCK select TICK_ONESHOT select PLAT_PXA select SPARSE_IRQ @@@@@ -565,7 -558,7 -539,7 -561,7 +568,7 @@@@@ config ARCH_W90X90 bool "Nuvoton W90X900 CPU" select CPU_ARM926T select ARCH_REQUIRE_GPIOLIB - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS help Support for Nuvoton (Winbond logic dept.) ARM9 processor, @@@@@ -579,19 -572,19 -553,18 -575,19 +582,19 @@@@@ config ARCH_NUC93X bool "Nuvoton NUC93X CPU" select CPU_ARM926T - select COMMON_CLKDEV + select CLKDEV_LOOKUP help Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a low-power and high performance MPEG-4/JPEG multimedia controller chip. config ARCH_TEGRA bool "NVIDIA Tegra" + select CLKDEV_LOOKUP select GENERIC_TIME select GENERIC_CLOCKEVENTS select GENERIC_GPIO select HAVE_CLK - select COMMON_CLKDEV + select HAVE_SCHED_CLOCK select ARCH_HAS_BARRIERS if CACHE_L2X0 select ARCH_HAS_CPUFREQ help @@@@@ -601,7 -594,7 -574,7 -597,7 +604,7 @@@@@ config ARCH_PNX4008 bool "Philips Nexperia PNX4008 Mobile" select CPU_ARM926T - select COMMON_CLKDEV + select CLKDEV_LOOKUP select ARCH_USES_GETTIMEOFFSET help This enables support for Philips PNX4008 mobile platform. @@@@@ -611,10 -604,10 -584,9 -607,10 +614,10 @@@@@ config ARCH_PX depends on MMU select ARCH_MTD_XIP select ARCH_HAS_CPUFREQ - select COMMON_CLKDEV + select CLKDEV_LOOKUP select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS + select HAVE_SCHED_CLOCK select TICK_ONESHOT select PLAT_PXA select SPARSE_IRQ @@@@@ -634,15 -627,15 -606,9 -630,15 +637,15 @@@@@ config ARCH_MS (clock and power control, etc). config ARCH_SHMOBILE - bool "Renesas SH-Mobile" + bool "Renesas SH-Mobile / R-Mobile" + select HAVE_CLK + select CLKDEV_LOOKUP + select GENERIC_CLOCKEVENTS + select NO_IOPORT + select SPARSE_IRQ + select MULTI_IRQ_HANDLER help - Support for Renesas's SH-Mobile ARM platforms + Support for Renesas's SH-Mobile and R-Mobile ARM platforms. config ARCH_RPC bool "RiscPC" @@@@@ -669,7 -662,7 -635,6 -665,7 +672,7 @@@@@ config ARCH_SA110 select CPU_FREQ select GENERIC_CLOCKEVENTS select HAVE_CLK + select HAVE_SCHED_CLOCK select TICK_ONESHOT select ARCH_REQUIRE_GPIOLIB help @@@@@ -773,7 -766,7 -738,6 -769,7 +776,7 @@@@@ config ARCH_S5PV31 select ARCH_SPARSEMEM_ENABLE select GENERIC_GPIO select HAVE_CLK + select ARCH_HAS_CPUFREQ select GENERIC_CLOCKEVENTS select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_I2C if I2C @@@@@ -797,21 -790,32 -761,31 -793,32 +800,21 @@@@@ config ARCH_TCC_92 bool "Telechips TCC ARM926-based systems" select CPU_ARM926T select HAVE_CLK - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS help Support for Telechips TCC ARM926-based systems. ---config ARCH_LH7A40X --- bool "Sharp LH7A40X" --- select CPU_ARM922T --- select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM --- select ARCH_USES_GETTIMEOFFSET --- help --- Say Y here for systems based on one of the Sharp LH7A40X --- System on a Chip processors. These CPUs include an ARM922T --- core with a wide array of integrated devices for --- hand-held and low-power applications. --- config ARCH_U300 bool "ST-Ericsson U300 Series" depends on MMU select CPU_ARM926T + select HAVE_SCHED_CLOCK select HAVE_TCM select ARM_AMBA select ARM_VIC select GENERIC_CLOCKEVENTS - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_GPIO help Support for ST-Ericsson U300 series mobile platforms. @@@@@ -821,9 -825,9 -795,8 -828,9 +824,9 @@@@@ config ARCH_U850 select CPU_V7 select ARM_AMBA select GENERIC_CLOCKEVENTS - select COMMON_CLKDEV + select CLKDEV_LOOKUP select ARCH_REQUIRE_GPIOLIB + select ARCH_HAS_CPUFREQ help Support for ST-Ericsson's Ux500 architecture @@@@@ -832,7 -836,7 -805,7 -839,7 +835,7 @@@@@ config ARCH_NOMADI select ARM_AMBA select ARM_VIC select CPU_ARM926T - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB help @@@@@ -844,7 -848,7 -817,7 -851,7 +847,7 @@@@@ config ARCH_DAVINC select ARCH_REQUIRE_GPIOLIB select ZONE_DMA select HAVE_IDE - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_ALLOCATOR select ARCH_HAS_HOLES_MEMORYMODEL help @@@@@ -856,7 -860,7 -829,6 -863,7 +859,7 @@@@@ config ARCH_OMA select ARCH_REQUIRE_GPIOLIB select ARCH_HAS_CPUFREQ select GENERIC_CLOCKEVENTS + select HAVE_SCHED_CLOCK select ARCH_HAS_HOLES_MEMORYMODEL help Support for TI's OMAP platform (OMAP1/2/3/4). @@@@@ -865,22 -869,12 -837,12 -872,12 +868,22 @@@@@ config PLAT_SPEA bool "ST SPEAr" select ARM_AMBA select ARCH_REQUIRE_GPIOLIB - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select HAVE_CLK help Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). +++config ARCH_VT8500 +++ bool "VIA/WonderMedia 85xx" +++ select CPU_ARM926T +++ select GENERIC_GPIO +++ select ARCH_HAS_CPUFREQ +++ select GENERIC_CLOCKEVENTS +++ select ARCH_REQUIRE_GPIOLIB +++ select HAVE_PWM +++ help +++ Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. endchoice # @@@@@ -888,6 -882,8 -850,8 -885,8 +891,6 @@@@@ # Kconfigs may be included either alphabetically (according to the # plat- suffix) or along side the corresponding mach-* source. # ---source "arch/arm/mach-aaec2000/Kconfig" --- source "arch/arm/mach-at91/Kconfig" source "arch/arm/mach-bcmring/Kconfig" @@@@@ -926,6 -922,8 -890,8 -925,8 +929,6 @@@@@ source "arch/arm/mach-kirkwood/Kconfig source "arch/arm/mach-ks8695/Kconfig" ---source "arch/arm/mach-lh7a40x/Kconfig" --- source "arch/arm/mach-loki/Kconfig" source "arch/arm/mach-lpc32xx/Kconfig" @@@@@ -936,8 -934,8 -902,6 -937,8 +939,8 @@@@@ source "arch/arm/mach-mv78xx0/Kconfig source "arch/arm/plat-mxc/Kconfig" + source "arch/arm/mach-mxs/Kconfig" + source "arch/arm/mach-netx/Kconfig" source "arch/arm/mach-nomadik/Kconfig" @@@@@ -1008,9 -1006,7 -972,7 -1009,8 +1011,10 @@@@@ source "arch/arm/mach-ux500/Kconfig source "arch/arm/mach-versatile/Kconfig" source "arch/arm/mach-vexpress/Kconfig" +++ source "arch/arm/plat-versatile/Kconfig" ++ +++source "arch/arm/mach-vt8500/Kconfig" + source "arch/arm/mach-w90x900/Kconfig" # Definitions to make life easier @@@@@ -1020,11 -1016,11 -982,9 -1020,11 +1024,11 @@@@@ config ARCH_ACOR config PLAT_IOP bool select GENERIC_CLOCKEVENTS + select HAVE_SCHED_CLOCK config PLAT_ORION bool + select HAVE_SCHED_CLOCK config PLAT_PXA bool @@@@@ -1039,8 -1035,8 -999,8 -1039,8 +1043,8 @@@@@ source arch/arm/mm/Kconfi config IWMMXT bool "Enable iWMMXt support" - depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK - default y if PXA27x || PXA3xx || ARCH_MMP + depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 + default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP help Enable support for iWMMXt context switching at run time if running on a CPU that supports it. @@@@@ -1052,23 -1048,23 -1012,18 -1052,23 +1056,23 @@@@@ config XSCALE_PM default y config CPU_HAS_PMU --- depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \ +++ depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ (!ARCH_OMAP3 || OMAP3_EMU) default y bool + config MULTI_IRQ_HANDLER + bool + help + Allow each machine to specify it's own IRQ handler at run time. + if !MMU source "arch/arm/Kconfig-nommu" endif config ARM_ERRATA_411920 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" --- depends on CPU_V6 +++ depends on CPU_V6 || CPU_V6K help Invalidation of the Instruction Cache operation can fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. @@@@@ -1144,7 -1140,7 -1099,7 -1144,7 +1148,7 @@@@@ config ARM_ERRATA_74223 config PL310_ERRATA_588369 bool "Clean & Invalidate maintenance operations do not invalidate clean lines" --- depends on CACHE_L2X0 && ARCH_OMAP4 +++ depends on CACHE_L2X0 help The PL310 L2 cache controller implements three types of Clean & Invalidate maintenance operations: by Physical Address @@@@@ -1153,7 -1149,8 -1108,8 -1153,8 +1157,7 @@@@@ clean operation followed immediately by an invalidate operation, both performing to the same memory location. This functionality is not correctly implemented in PL310 as clean lines are not --- invalidated as a result of these operations. Note that this errata --- uses Texas Instrument's secure monitor api. +++ invalidated as a result of these operations. config ARM_ERRATA_720789 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" @@@@@ -1167,17 -1164,6 -1123,6 -1168,6 +1171,17 @@@@@ tables. The workaround changes the TLB flushing routines to invalidate entries regardless of the ASID. +++config PL310_ERRATA_727915 +++ bool "Background Clean & Invalidate by Way operation can cause data corruption" +++ depends on CACHE_L2X0 +++ help +++ PL310 implements the Clean & Invalidate by Way L2 cache maintenance +++ operation (offset 0x7FC). This operation runs in background so that +++ PL310 can handle normal accesses while it is in progress. Under very +++ rare circumstances, due to this erratum, write data can be lost when +++ PL310 treats a cacheable write transaction during a Clean & +++ Invalidate by Way operation. +++ config ARM_ERRATA_743622 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" depends on CPU_V7 @@@@@ -1191,53 -1177,31 -1136,6 -1181,6 +1195,53 @@@@@ visible impact on the overall performance or power consumption of the processor. ++config ARM_ERRATA_751472 ++ bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" ++ depends on CPU_V7 && SMP ++ help ++ This option enables the workaround for the 751472 Cortex-A9 (prior ++ to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the ++ completion of a following broadcasted operation if the second ++ operation is received by a CPU before the ICIALLUIS has completed, ++ potentially leading to corrupted entries in the cache or TLB. ++ ++config ARM_ERRATA_753970 ++ bool "ARM errata: cache sync operation may be faulty" ++ depends on CACHE_PL310 ++ help ++ This option enables the workaround for the 753970 PL310 (r3p0) erratum. ++ ++ Under some condition the effect of cache sync operation on ++ the store buffer still remains when the operation completes. ++ This means that the store buffer is always asked to drain and ++ this prevents it from merging any further writes. The workaround ++ is to replace the normal offset of cache sync operation (0x730) ++ by another offset targeting an unmapped PL310 register 0x740. ++ This has the same effect as the cache sync operation: store buffer ++ drain and waiting for all buffers empty. ++ +++config ARM_ERRATA_754322 +++ bool "ARM errata: possible faulty MMU translations following an ASID switch" +++ depends on CPU_V7 +++ help +++ This option enables the workaround for the 754322 Cortex-A9 (r2p*, +++ r3p*) erratum. A speculative memory access may cause a page table walk +++ which starts prior to an ASID switch but completes afterwards. This +++ can populate the micro-TLB with a stale entry which may be hit with +++ the new ASID. This workaround places two dsb instructions in the mm +++ switching code so that no page table walks can cross the ASID switch. +++ +++config ARM_ERRATA_754327 +++ bool "ARM errata: no automatic Store Buffer drain" +++ depends on CPU_V7 && SMP +++ help +++ This option enables the workaround for the 754327 Cortex-A9 (prior to +++ r2p0) erratum. The Store Buffer does not have any automatic draining +++ mechanism and therefore a livelock may occur if an external agent +++ continuously polls a memory location waiting to observe an update. +++ This workaround defines cpu_relax() as smp_mb(), preventing correctly +++ written polling loops from denying visibility of updates to memory. +++ endmenu source "arch/arm/common/Kconfig" @@@@@ -1266,7 -1230,7 -1164,7 -1209,7 +1270,7 @@@@@ config ISA_DMA_AP bool config PCI - bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX + bool "PCI support" if MIGHT_HAVE_PCI help Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff inside @@@@@ -1277,12 -1241,12 -1175,6 -1220,12 +1281,12 @@@@@ config PCI_DOMAIN bool depends on PCI + config PCI_NANOENGINE + bool "BSE nanoEngine PCI support" + depends on SA1100_NANOENGINE + help + Enable PCI on the BSE nanoEngine board. + config PCI_SYSCALL def_bool PCI @@@@@ -1311,14 -1275,13 -1203,12 -1254,13 +1315,14 @@@@@ source "kernel/time/Kconfig config SMP bool "Symmetric Multi-Processing (EXPERIMENTAL)" depends on EXPERIMENTAL +++ depends on CPU_V6K || CPU_V7 depends on GENERIC_CLOCKEVENTS depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ - MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\ - ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 + MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ + ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ + ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE select USE_GENERIC_SMP_HELPERS - select HAVE_ARM_SCU + select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP help This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If @@@@@ -1339,7 -1302,7 -1229,7 -1281,7 +1343,7 @@@@@ config SMP_ON_UP bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" depends on EXPERIMENTAL - depends on SMP && !XIP && !THUMB2_KERNEL + depends on SMP && !XIP_KERNEL default y help SMP kernels contain instructions which fail on non-SMP processors. @@@@@ -1358,7 -1321,7 -1248,6 -1300,7 +1362,7 @@@@@ config HAVE_ARM_SC config HAVE_ARM_TWD bool depends on SMP + select TICK_ONESHOT help This options enables support for the ARM timer and watchdog unit @@@@@ -1394,7 -1357,7 -1283,6 -1336,7 +1398,7 @@@@@ config NR_CPU config HOTPLUG_CPU bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" depends on SMP && HOTPLUG && EXPERIMENTAL + depends on !ARCH_MSM help Say Y here to experiment with turning CPUs off and on. CPUs can be controlled through /sys/devices/system/cpu. @@@@@ -1403,7 -1366,7 -1291,7 -1345,7 +1407,7 @@@@@ config LOCAL_TIMER bool "Use local timer interrupts" depends on SMP default y - select HAVE_ARM_TWD + select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP help Enable support for local timers on SMP platforms, rather then the legacy IPI broadcast method. Local timers allows the system @@@@@ -1422,8 -1385,8 -1310,8 -1364,8 +1426,8 @@@@@ config H default 100 config THUMB2_KERNEL - bool "Compile the kernel in Thumb-2 mode" - depends on CPU_V7 && EXPERIMENTAL + bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" - - depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL +++ depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL select AEABI select ARM_ASM_UNIFIED help @@@@@ -1433,37 -1396,6 -1321,6 -1375,6 +1437,37 @@@@@ If unsure, say N. +++config THUMB2_AVOID_R_ARM_THM_JUMP11 +++ bool "Work around buggy Thumb-2 short branch relocations in gas" +++ depends on THUMB2_KERNEL && MODULES +++ default y +++ help +++ Various binutils versions can resolve Thumb-2 branches to +++ locally-defined, preemptible global symbols as short-range "b.n" +++ branch instructions. +++ +++ This is a problem, because there's no guarantee the final +++ destination of the symbol, or any candidate locations for a +++ trampoline, are within range of the branch. For this reason, the +++ kernel does not support fixing up the R_ARM_THM_JUMP11 (102) +++ relocation in modules at all, and it makes little sense to add +++ support. +++ +++ The symptom is that the kernel fails with an "unsupported +++ relocation" error when loading some modules. +++ +++ Until fixed tools are available, passing +++ -fno-optimize-sibling-calls to gcc should prevent gcc generating +++ code which hits this problem, at the cost of a bit of extra runtime +++ stack usage in some cases. +++ +++ The problem is described in more detail at: +++ https://bugs.launchpad.net/binutils-linaro/+bug/725126 +++ +++ Only Thumb-2 kernels are affected. +++ +++ Unless you are sure your tools don't have this problem, say Y. +++ config ARM_ASM_UNIFIED bool @@@@@ -1484,7 -1416,7 -1341,7 -1395,7 +1488,7 @@@@@ config AEAB config OABI_COMPAT bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" -- depends on AEABI && EXPERIMENTAL ++ depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL default y help This option preserves the old syscall interface along with the @@@@@ -1541,6 -1473,6 -1398,15 -1452,6 +1545,6 @@@@@ config HW_PERF_EVENT Enable hardware performance counter support for perf events. If disabled, perf events will use software events only. - config SPARSE_IRQ - def_bool n - help - This enables support for sparse irqs. This is useful in general - as most CPUs have a fairly sparse array of IRQ vectors, which - the irq_desc then maps directly on to. Systems with a high - number of off-chip IRQs will want to treat this as - experimental until they have been independently verified. - source "mm/Kconfig" config FORCE_MAX_ZONEORDER @@@@@ -1658,7 -1590,7 -1524,6 -1569,7 +1662,7 @@@@@ config SECCOM config CC_STACKPROTECTOR bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" + depends on EXPERIMENTAL help This option turns on the -fstack-protector GCC feature. This feature puts, at the beginning of functions, a canary value on @@@@@ -1712,18 -1644,6 -1577,6 -1623,6 +1716,18 @@@@@ config ZBOOT_RO Say Y here if you intend to execute your compressed kernel image (zImage) directly from ROM or flash. If unsure, say N. +++config ZBOOT_ROM_MMCIF +++ bool "Include MMCIF loader in zImage (EXPERIMENTAL)" +++ depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL +++ help +++ Say Y here to include experimental MMCIF loading code in the +++ ROM-able zImage. With this enabled it is possible to write the +++ the ROM-able zImage kernel image to an MMC card and boot the +++ kernel straight from the reset vector. At reset the processor +++ Mask ROM will load the first part of the the ROM-able zImage +++ which in turn loads the rest the kernel image to RAM using the +++ MMCIF hardware block. +++ config CMDLINE string "Default kernel command string" default "" @@@@@ -1797,19 -1717,19 -1650,6 -1696,19 +1801,19 @@@@@ config ATAGS_PRO Should the atags used to boot the kernel be exported in an "atags" file in procfs. Useful with kexec. + config CRASH_DUMP + bool "Build kdump crash kernel (EXPERIMENTAL)" + depends on EXPERIMENTAL + help + Generate crash dump after being started by kexec. This should + be normally only set in special crash dump kernels which are + loaded in the main kernel with kexec-tools into a specially + reserved region and then later executed after a crash by + kdump/kexec. The crash dump kernel must be compiled to a + memory address not used by the main kernel + + For more details see Documentation/kdump/kdump.txt + config AUTO_ZRELADDR bool "Auto calculation of the decompressed kernel image address" depends on !ZBOOT_ROM && !ARCH_U300 @@@@@ -1867,7 -1787,7 -1707,7 -1766,7 +1871,7 @@@@@ config CPU_FREQ_S3 Internal configuration node for common cpufreq on Samsung SoC config CPU_FREQ_S3C24XX - bool "CPUfreq driver for Samsung S3C24XX series CPUs" + bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL select CPU_FREQ_S3C help @@@@@ -1879,7 -1799,7 -1719,7 -1778,7 +1883,7 @@@@@ If in doubt, say N. config CPU_FREQ_S3C24XX_PLL - bool "Support CPUfreq changing of PLL frequency" + bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" depends on CPU_FREQ_S3C24XX && EXPERIMENTAL help Compile in support for changing the PLL frequency from the @@@@@ -1919,7 -1839,7 -1759,7 -1818,7 +1923,7 @@@@@ comment "At least one emulation must b config FPE_NWFPE bool "NWFPE math emulation" - depends on !AEABI || OABI_COMPAT + depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL ---help--- Say Y to include the NWFPE floating point emulator in the kernel. This is necessary to run most binaries. Linux does not currently @@@@@ -1957,7 -1877,7 -1797,7 -1856,7 +1961,7 @@@@@ config FPE_FASTFP config VFP bool "VFP-format floating point maths" --- depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON +++ depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON help Say Y to include VFP support code in the kernel. This is needed if your hardware includes a VFP unit. diff --combined arch/arm/include/asm/outercache.h index 348d513afa92,fc1900925275,88ad89209764,fc1900925275..d8387437ec5a --- a/arch/arm/include/asm/outercache.h +++ b/arch/arm/include/asm/outercache.h @@@@@ -21,6 -21,6 -21,8 -21,6 +21,8 @@@@@ #ifndef __ASM_OUTERCACHE_H #define __ASM_OUTERCACHE_H ++ +#include ++ + struct outer_cache_fns { void (*inv_range)(unsigned long, unsigned long); void (*clean_range)(unsigned long, unsigned long); @@@@@ -31,24 -31,23 -33,23 -31,23 +33,24 @@@@@ #ifdef CONFIG_OUTER_CACHE_SYNC void (*sync)(void); #endif +++ void (*set_debug)(unsigned long); }; #ifdef CONFIG_OUTER_CACHE extern struct outer_cache_fns outer_cache; -- -static inline void outer_inv_range(unsigned long start, unsigned long end) ++ +static inline void outer_inv_range(phys_addr_t start, phys_addr_t end) { if (outer_cache.inv_range) outer_cache.inv_range(start, end); } -- -static inline void outer_clean_range(unsigned long start, unsigned long end) ++ +static inline void outer_clean_range(phys_addr_t start, phys_addr_t end) { if (outer_cache.clean_range) outer_cache.clean_range(start, end); } -- -static inline void outer_flush_range(unsigned long start, unsigned long end) ++ +static inline void outer_flush_range(phys_addr_t start, phys_addr_t end) { if (outer_cache.flush_range) outer_cache.flush_range(start, end); @@@@@ -74,11 -73,11 -75,11 -73,11 +76,11 @@@@@ static inline void outer_disable(void #else -- -static inline void outer_inv_range(unsigned long start, unsigned long end) ++ +static inline void outer_inv_range(phys_addr_t start, phys_addr_t end) { } -- -static inline void outer_clean_range(unsigned long start, unsigned long end) ++ +static inline void outer_clean_range(phys_addr_t start, phys_addr_t end) { } -- -static inline void outer_flush_range(unsigned long start, unsigned long end) ++ +static inline void outer_flush_range(phys_addr_t start, phys_addr_t end) { } static inline void outer_flush_all(void) { } static inline void outer_inv_all(void) { } diff --combined arch/arm/include/asm/setup.h index da8b52ec49cf,f1e5a9bca249,50921182b7c3,f1e5a9bca249..95176af3df8c --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@@@@ -192,10 -192,14 -192,14 -192,14 +192,10 @@@@@ static struct tagtable __tagtable_##fn /* * Memory map description */ ---#ifdef CONFIG_ARCH_LH7A40X ---# define NR_BANKS 16 ---#else ---# define NR_BANKS 8 ---#endif +++#define NR_BANKS 8 struct membank { -- - unsigned long start; ++ + phys_addr_t start; unsigned long size; unsigned int highmem; }; diff --combined arch/arm/kernel/setup.c index d1da92174277,5ea4fb718b97,9d4a84402ae9,420b8d6485d6..d149539ccd68 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@@@@ -75,9 -75,9 -75,9 -75,9 +75,9 @@@@@ extern void reboot_setup(char *str) unsigned int processor_id; EXPORT_SYMBOL(processor_id); - unsigned int __machine_arch_type; + unsigned int __machine_arch_type __read_mostly; EXPORT_SYMBOL(__machine_arch_type); - unsigned int cacheid; + unsigned int cacheid __read_mostly; EXPORT_SYMBOL(cacheid); unsigned int __atags_pointer __initdata; @@@@@ -91,24 -91,24 -91,24 -91,24 +91,24 @@@@@ EXPORT_SYMBOL(system_serial_low) unsigned int system_serial_high; EXPORT_SYMBOL(system_serial_high); - unsigned int elf_hwcap; + unsigned int elf_hwcap __read_mostly; EXPORT_SYMBOL(elf_hwcap); #ifdef MULTI_CPU - struct processor processor; + struct processor processor __read_mostly; #endif #ifdef MULTI_TLB - struct cpu_tlb_fns cpu_tlb; + struct cpu_tlb_fns cpu_tlb __read_mostly; #endif #ifdef MULTI_USER - struct cpu_user_fns cpu_user; + struct cpu_user_fns cpu_user __read_mostly; #endif #ifdef MULTI_CACHE - struct cpu_cache_fns cpu_cache; + struct cpu_cache_fns cpu_cache __read_mostly; #endif #ifdef CONFIG_OUTER_CACHE - struct outer_cache_fns outer_cache; + struct outer_cache_fns outer_cache __read_mostly; EXPORT_SYMBOL(outer_cache); #endif @@@@@ -126,7 -126,7 -126,6 -126,7 +126,7 @@@@@ EXPORT_SYMBOL(elf_platform) static const char *cpu_name; static const char *machine_name; static char __initdata cmd_line[COMMAND_LINE_SIZE]; + struct machine_desc *machine_desc __initdata; static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE; static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } }; @@@@@ -226,8 -226,8 -225,8 -226,8 +226,8 @@@@@ int cpu_architecture(void * Register 0 and check for VMSAv7 or PMSAv7 */ asm("mrc p15, 0, %0, c0, c1, 4" : "=r" (mmfr0)); -- if ((mmfr0 & 0x0000000f) == 0x00000003 || -- (mmfr0 & 0x000000f0) == 0x00000030) ++ if ((mmfr0 & 0x0000000f) >= 0x00000003 || ++ (mmfr0 & 0x000000f0) >= 0x00000030) cpu_arch = CPU_ARCH_ARMv7; else if ((mmfr0 & 0x0000000f) == 0x00000002 || (mmfr0 & 0x000000f0) == 0x00000020) @@@@@ -308,22 -308,7 -307,7 -308,7 +308,22 @@@@@ static void __init cacheid_init(void * already provide the required functionality. */ extern struct proc_info_list *lookup_processor_type(unsigned int); ---extern struct machine_desc *lookup_machine_type(unsigned int); +++ +++static void __init early_print(const char *str, ...) +++{ +++ extern void printascii(const char *); +++ char buf[256]; +++ va_list ap; +++ +++ va_start(ap, str); +++ vsnprintf(buf, sizeof(buf), str, ap); +++ va_end(ap); +++ +++#ifdef CONFIG_DEBUG_LL +++ printascii(buf); +++#endif +++ printk("%s", buf); +++} static void __init feat_v6_fixup(void) { @@@@@ -441,38 -426,30 -425,30 -426,30 +441,38 @@@@@ void cpu_init(void static struct machine_desc * __init setup_machine(unsigned int nr) { --- struct machine_desc *list; +++ extern struct machine_desc __arch_info_begin[], __arch_info_end[]; +++ struct machine_desc *p; /* * locate machine in the list of supported machines. */ --- list = lookup_machine_type(nr); --- if (!list) { --- printk("Machine configuration botched (nr %d), unable " --- "to continue.\n", nr); --- while (1); --- } +++ for (p = __arch_info_begin; p < __arch_info_end; p++) +++ if (nr == p->nr) { +++ printk("Machine: %s\n", p->name); +++ return p; +++ } +++ +++ early_print("\n" +++ "Error: unrecognized/unsupported machine ID (r1 = 0x%08x).\n\n" +++ "Available machine support:\n\nID (hex)\tNAME\n", nr); + - - printk("Machine: %s\n", list->name); +++ for (p = __arch_info_begin; p < __arch_info_end; p++) +++ early_print("%08x\t%s\n", p->nr, p->name); - - return list; - printk("Machine: %s\n", list->name); +++ early_print("\nPlease check your kernel config and/or bootloader.\n"); + + - return list; +++ while (true) +++ /* can't use cpu_relax() here as it may require MMU setup */; } -- -static int __init arm_add_memory(unsigned long start, unsigned long size) ++ +static int __init arm_add_memory(phys_addr_t start, unsigned long size) { struct membank *bank = &meminfo.bank[meminfo.nr_banks]; if (meminfo.nr_banks >= NR_BANKS) { printk(KERN_CRIT "NR_BANKS too low, " -- - "ignoring memory at %#lx\n", start); ++ + "ignoring memory at 0x%08llx\n", (long long)start); return -EINVAL; } @@@@@ -502,7 -479,7 -478,8 -479,7 +502,8 @@@@@ static int __init early_mem(char *p) { static int usermem __initdata = 0; -- - unsigned long size, start; ++ + unsigned long size; ++ + phys_addr_t start; char *endp; /* @@@@@ -541,21 -518,21 -518,25 -518,21 +542,21 @@@@@ setup_ramdisk(int doload, int prompt, i #endif } - static void __init - request_standard_resources(struct meminfo *mi, struct machine_desc *mdesc) + static void __init request_standard_resources(struct machine_desc *mdesc) { + struct memblock_region *region; struct resource *res; - int i; kernel_code.start = virt_to_phys(_text); kernel_code.end = virt_to_phys(_etext - 1); kernel_data.start = virt_to_phys(_sdata); kernel_data.end = virt_to_phys(_end - 1); - for (i = 0; i < mi->nr_banks; i++) { - if (mi->bank[i].size == 0) - continue; - + for_each_memblock(memory, region) { res = alloc_bootmem_low(sizeof(*res)); res->name = "System RAM"; - res->start = mi->bank[i].start; - res->end = mi->bank[i].start + mi->bank[i].size - 1; + res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); + res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; request_resource(&iomem_resource, res); @@@@@ -669,17 -646,17 -650,15 -646,17 +670,17 @@@@@ static int __init parse_tag_revision(co __tagtable(ATAG_REVISION, parse_tag_revision); - #ifndef CONFIG_CMDLINE_FORCE static int __init parse_tag_cmdline(const struct tag *tag) { + #ifndef CONFIG_CMDLINE_FORCE strlcpy(default_command_line, tag->u.cmdline.cmdline, COMMAND_LINE_SIZE); + #else + pr_warning("Ignoring tag cmdline (using the default kernel command line)\n"); + #endif /* CONFIG_CMDLINE_FORCE */ return 0; } __tagtable(ATAG_CMDLINE, parse_tag_cmdline); - #endif /* CONFIG_CMDLINE_FORCE */ /* * Scan the tag table for this tag, and call its parse function. @@@@@ -726,15 -703,15 -705,17 -703,15 +727,15 @@@@@ static struct init_tags { tag_size(tag_core), ATAG_CORE }, { 1, PAGE_SIZE, 0xff }, { tag_size(tag_mem32), ATAG_MEM }, --- { MEM_SIZE, PHYS_OFFSET }, +++ { MEM_SIZE }, { 0, ATAG_NONE } }; - static void (*init_machine)(void) __initdata; - static int __init customize_machine(void) { /* customizes platform devices, or adds new ones */ - if (init_machine) - init_machine(); + if (machine_desc->init_machine) + machine_desc->init_machine(); return 0; } arch_initcall(customize_machine); @@@@@ -825,13 -802,11 -806,10 -802,11 +826,13 @@@@@ void __init setup_arch(char **cmdline_p struct machine_desc *mdesc; char *from = default_command_line; +++ init_tags.mem.start = PHYS_OFFSET; +++ unwind_init(); setup_processor(); mdesc = setup_machine(machine_arch_type); + machine_desc = mdesc; machine_name = mdesc->name; if (mdesc->soft_reboot) @@@@@ -839,25 -814,8 -817,8 -814,8 +840,25 @@@@@ if (__atags_pointer) tags = phys_to_virt(__atags_pointer); --- else if (mdesc->boot_params) --- tags = phys_to_virt(mdesc->boot_params); +++ else if (mdesc->boot_params) { +++#ifdef CONFIG_MMU +++ /* +++ * We still are executing with a minimal MMU mapping created +++ * with the presumption that the machine default for this +++ * is located in the first MB of RAM. Anything else will +++ * fault and silently hang the kernel at this point. +++ */ +++ if (mdesc->boot_params < PHYS_OFFSET || +++ mdesc->boot_params >= PHYS_OFFSET + SZ_1M) { +++ printk(KERN_WARNING +++ "Default boot params at physical 0x%08lx out of reach\n", +++ mdesc->boot_params); +++ } else +++#endif +++ { +++ tags = phys_to_virt(mdesc->boot_params); +++ } +++ } #if defined(CONFIG_DEPRECATED_PARAM_STRUCT) /* @@@@@ -897,7 -855,7 -858,7 -855,7 +898,7 @@@@@ arm_memblock_init(&meminfo, mdesc); paging_init(mdesc); - request_standard_resources(&meminfo, mdesc); + request_standard_resources(mdesc); #ifdef CONFIG_SMP if (is_smp()) @@@@@ -908,9 -866,9 -869,13 -866,9 +909,9 @@@@@ cpu_init(); tcm_init(); - /* - * Set up various architecture-specific pointers - */ - arch_nr_irqs = mdesc->nr_irqs; - init_arch_irq = mdesc->init_irq; - system_timer = mdesc->timer; - init_machine = mdesc->init_machine; + #ifdef CONFIG_MULTI_IRQ_HANDLER + handle_arch_irq = mdesc->handle_irq; + #endif #ifdef CONFIG_VT #if defined(CONFIG_VGA_CONSOLE) @@@@@ -920,9 -878,9 -885,6 -878,9 +921,9 @@@@@ #endif #endif early_trap_init(); + + if (mdesc->init_early) + mdesc->init_early(); } diff --combined arch/arm/kernel/traps.c index 21ac43f1c2d0,ee57640ba2bb,10f5b8926ee6,ee57640ba2bb..f0000e188c8c --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@@@@ -23,7 -23,6 -23,6 -23,6 +23,7 @@@@@ #include #include #include +++#include #include #include @@@@@ -33,12 -32,13 -32,11 -32,13 +33,12 @@@@@ #include #include ---#include "ptrace.h" #include "signal.h" static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" }; + void *vectors_page; + #ifdef CONFIG_DEBUG_USER unsigned int user_debug; @@@@@ -256,7 -256,7 -254,7 -256,7 +256,7 @@@@@ static int __die(const char *str, int e return ret; } ---DEFINE_SPINLOCK(die_lock); +++static DEFINE_SPINLOCK(die_lock); /* * This function is protected against re-entrancy. @@@@@ -712,17 -712,17 -710,17 -712,17 +712,17 @@@@@ EXPORT_SYMBOL(__readwrite_bug) void __pte_error(const char *file, int line, pte_t pte) { -- - printk("%s:%d: bad pte %08lx.\n", file, line, pte_val(pte)); ++ + printk("%s:%d: bad pte %08llx.\n", file, line, (long long)pte_val(pte)); } void __pmd_error(const char *file, int line, pmd_t pmd) { -- - printk("%s:%d: bad pmd %08lx.\n", file, line, pmd_val(pmd)); ++ + printk("%s:%d: bad pmd %08llx.\n", file, line, (long long)pmd_val(pmd)); } void __pgd_error(const char *file, int line, pgd_t pgd) { -- - printk("%s:%d: bad pgd %08lx.\n", file, line, pgd_val(pgd)); ++ + printk("%s:%d: bad pgd %08llx.\n", file, line, (long long)pgd_val(pgd)); } asmlinkage void __div0(void) @@@@@ -758,11 -758,11 -756,7 -758,11 +758,11 @@@@@ static void __init kuser_get_tls_init(u void __init early_trap_init(void) { + #if defined(CONFIG_CPU_USE_DOMAINS) unsigned long vectors = CONFIG_VECTORS_BASE; + #else + unsigned long vectors = (unsigned long)vectors_page; + #endif extern char __stubs_start[], __stubs_end[]; extern char __vectors_start[], __vectors_end[]; extern char __kuser_helper_start[], __kuser_helper_end[]; @@@@@ -786,10 -786,10 -780,10 -786,10 +786,10 @@@@@ * Copy signal return handlers into the vector page, and * set sigreturn to be a pointer to these. */ - memcpy((void *)KERN_SIGRETURN_CODE, sigreturn_codes, - sizeof(sigreturn_codes)); - memcpy((void *)KERN_RESTART_CODE, syscall_restart_code, - sizeof(syscall_restart_code)); + memcpy((void *)(vectors + KERN_SIGRETURN_CODE - CONFIG_VECTORS_BASE), + sigreturn_codes, sizeof(sigreturn_codes)); + memcpy((void *)(vectors + KERN_RESTART_CODE - CONFIG_VECTORS_BASE), + syscall_restart_code, sizeof(syscall_restart_code)); flush_icache_range(vectors, vectors + PAGE_SIZE); modify_domain(DOMAIN_USER, DOMAIN_CLIENT); diff --combined arch/arm/mach-omap2/Kconfig index b69fa0a0299e,1a2cf6226a55,ab784bfde908,ec55fd830f62..6819c64594ef --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@@@@ -15,7 -15,7 -15,7 -15,7 +15,7 @@@@@ config ARCH_OMAP2PLUS_TYPICA select SERIAL_OMAP_CONSOLE select I2C select I2C_OMAP - select MFD + select MFD_SUPPORT select MENELAUS if ARCH_OMAP2 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 @@@@@ -35,8 -35,8 -35,6 -35,8 +35,8 @@@@@ config ARCH_OMAP select CPU_V7 select USB_ARCH_HAS_EHCI select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4 + select ARCH_HAS_OPP + select PM_OPP if PM config ARCH_OMAP4 bool "TI OMAP4" @@@@@ -44,12 -44,11 -42,8 -44,12 +44,13 @@@@@ depends on ARCH_OMAP2PLUS select CPU_V7 select ARM_GIC +++ select LOCAL_TIMERS if SMP select PL310_ERRATA_588369 +++ select PL310_ERRATA_727915 select ARM_ERRATA_720789 + select ARCH_HAS_OPP + select PM_OPP if PM + select USB_ARCH_HAS_EHCI comment "OMAP Core Type" depends on ARCH_OMAP2 @@@@@ -91,12 -90,12 -85,6 -91,12 +92,12 @@@@@ config OMAP_PACKAGE_CU config OMAP_PACKAGE_CBP bool + config OMAP_PACKAGE_CBL + bool + + config OMAP_PACKAGE_CBS + bool + comment "OMAP Board Type" depends on ARCH_OMAP2PLUS @@@@@ -140,6 -139,6 -128,7 -140,6 +141,6 @@@@@ config MACH_DEVKIT800 depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CUS - select OMAP_MUX config MACH_OMAP_LDP bool "OMAP3 LDP board" @@@@@ -185,17 -184,17 -174,11 -185,17 +186,17 @@@@@ config MACH_OMAP3517EV default y select OMAP_PACKAGE_CBB + config MACH_CRANEBOARD + bool "AM3517/05 CRANE board" + depends on ARCH_OMAP3 + select OMAP_PACKAGE_CBB + config MACH_OMAP3_PANDORA bool "OMAP3 Pandora" depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CBB + select REGULATOR_FIXED_VOLTAGE config MACH_OMAP3_TOUCHBOOK bool "OMAP3 Touch Book" @@@@@ -227,12 -226,12 -210,6 -227,12 +228,12 @@@@@ config MACH_NOKIA_N8X select MACH_NOKIA_N810 select MACH_NOKIA_N810_WIMAX + config MACH_NOKIA_RM680 + bool "Nokia RM-680 board" + depends on ARCH_OMAP3 + default y + select OMAP_PACKAGE_CBB + config MACH_NOKIA_RX51 bool "Nokia RX-51 board" depends on ARCH_OMAP3 @@@@@ -247,7 -246,7 -224,6 -247,7 +248,7 @@@@@ config MACH_OMAP_ZOOM select SERIAL_8250 select SERIAL_CORE_CONSOLE select SERIAL_8250_CONSOLE + select REGULATOR_FIXED_VOLTAGE config MACH_OMAP_ZOOM3 bool "OMAP3630 Zoom3 board" @@@@@ -257,19 -256,19 -233,20 -257,19 +258,19 @@@@@ select SERIAL_8250 select SERIAL_CORE_CONSOLE select SERIAL_8250_CONSOLE + select REGULATOR_FIXED_VOLTAGE config MACH_CM_T35 bool "CompuLab CM-T35 module" depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CUS - select OMAP_MUX config MACH_CM_T3517 bool "CompuLab CM-T3517 module" depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CBB - select OMAP_MUX config MACH_IGEP0020 bool "IGEP v2 board" @@@@@ -288,6 -287,6 -265,7 -288,6 +289,6 @@@@@ config MACH_SBC353 depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CUS - select OMAP_MUX config MACH_OMAP_3630SDP bool "OMAP3630 SDP board" @@@@@ -299,15 -298,15 -277,11 -299,15 +300,15 @@@@@ config MACH_OMAP_4430SD bool "OMAP 4430 SDP board" default y depends on ARCH_OMAP4 + select OMAP_PACKAGE_CBL + select OMAP_PACKAGE_CBS config MACH_OMAP4_PANDA bool "OMAP4 Panda Board" default y depends on ARCH_OMAP4 + select OMAP_PACKAGE_CBL + select OMAP_PACKAGE_CBS config OMAP3_EMU bool "OMAP3 debugging peripherals" diff --combined arch/arm/mach-realview/realview_eb.c index 8ede983b861c,6ef5c5e528b2,f2697106f809,d0f851b886db..2ecc1d94284e --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@@@@ -144,60 -144,60 -144,60 -144,39 +144,39 @@@@@ static struct pl022_ssp_controller ssp0 * These devices are connected via the core APB bridge */ #define GPIO2_IRQ { IRQ_EB_GPIO2, NO_IRQ } --- #define GPIO2_DMA { 0, 0 } #define GPIO3_IRQ { IRQ_EB_GPIO3, NO_IRQ } --- #define GPIO3_DMA { 0, 0 } #define AACI_IRQ { IRQ_EB_AACI, NO_IRQ } --- #define AACI_DMA { 0x80, 0x81 } #define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B } --- #define MMCI0_DMA { 0x84, 0 } #define KMI0_IRQ { IRQ_EB_KMI0, NO_IRQ } --- #define KMI0_DMA { 0, 0 } #define KMI1_IRQ { IRQ_EB_KMI1, NO_IRQ } --- #define KMI1_DMA { 0, 0 } /* * These devices are connected directly to the multi-layer AHB switch */ #define EB_SMC_IRQ { NO_IRQ, NO_IRQ } --- #define EB_SMC_DMA { 0, 0 } #define MPMC_IRQ { NO_IRQ, NO_IRQ } --- #define MPMC_DMA { 0, 0 } #define EB_CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ } --- #define EB_CLCD_DMA { 0, 0 } #define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ } --- #define DMAC_DMA { 0, 0 } /* * These devices are connected via the core APB bridge */ #define SCTL_IRQ { NO_IRQ, NO_IRQ } --- #define SCTL_DMA { 0, 0 } #define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ } --- #define EB_WATCHDOG_DMA { 0, 0 } #define EB_GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ } --- #define EB_GPIO0_DMA { 0, 0 } #define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ } --- #define GPIO1_DMA { 0, 0 } #define EB_RTC_IRQ { IRQ_EB_RTC, NO_IRQ } --- #define EB_RTC_DMA { 0, 0 } /* * These devices are connected via the DMA APB bridge */ #define SCI_IRQ { IRQ_EB_SCI, NO_IRQ } --- #define SCI_DMA { 7, 6 } #define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ } --- #define EB_UART0_DMA { 15, 14 } #define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ } --- #define EB_UART1_DMA { 13, 12 } #define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ } --- #define EB_UART2_DMA { 11, 10 } #define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ } --- #define EB_UART3_DMA { 0x86, 0x87 } #define EB_SSP_IRQ { IRQ_EB_SSP, NO_IRQ } --- #define EB_SSP_DMA { 9, 8 } /* FPGA Primecells */ AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); @@@@@ -364,19 -364,19 -364,21 -343,19 +343,19 @@@@@ static void __init gic_init_irq(void writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); /* core tile GIC, primary */ - gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE); - gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29); - gic_cpu_init(0, gic_cpu_base_addr); + gic_init(0, 29, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), + __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB /* board GIC, secondary */ - gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64); - gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE)); + gic_init(1, 64, __io_address(REALVIEW_EB_GIC_DIST_BASE), + __io_address(REALVIEW_EB_GIC_CPU_BASE)); gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); #endif } else { /* board GIC, primary */ - gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE); - gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29); - gic_cpu_init(0, gic_cpu_base_addr); + gic_init(0, 29, __io_address(REALVIEW_EB_GIC_DIST_BASE), + __io_address(REALVIEW_EB_GIC_CPU_BASE)); } } @@@@@ -484,9 -484,9 -486,9 -463,10 +463,10 @@@@@ static void __init realview_eb_init(voi MACHINE_START(REALVIEW_EB, "ARM-RealView EB") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ --- .boot_params = PHYS_OFFSET + 0x00000100, +++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_fixup, .map_io = realview_eb_map_io, +++ .init_early = realview_init_early, .init_irq = gic_init_irq, .timer = &realview_eb_timer, .init_machine = realview_eb_init, diff --combined arch/arm/mach-realview/realview_pb1176.c index 9f26369555c7,cbdc97a5685f,a4125619d71b,61f6a9d853fc..eab6070f66d0 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c @@@@@ -134,47 -134,47 -134,47 -134,26 +134,26 @@@@@ static struct pl022_ssp_controller ssp0 * RealView PB1176 AMBA devices */ #define GPIO2_IRQ { IRQ_PB1176_GPIO2, NO_IRQ } --- #define GPIO2_DMA { 0, 0 } #define GPIO3_IRQ { IRQ_PB1176_GPIO3, NO_IRQ } --- #define GPIO3_DMA { 0, 0 } #define AACI_IRQ { IRQ_PB1176_AACI, NO_IRQ } --- #define AACI_DMA { 0x80, 0x81 } #define MMCI0_IRQ { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B } --- #define MMCI0_DMA { 0x84, 0 } #define KMI0_IRQ { IRQ_PB1176_KMI0, NO_IRQ } --- #define KMI0_DMA { 0, 0 } #define KMI1_IRQ { IRQ_PB1176_KMI1, NO_IRQ } --- #define KMI1_DMA { 0, 0 } #define PB1176_SMC_IRQ { NO_IRQ, NO_IRQ } --- #define PB1176_SMC_DMA { 0, 0 } #define MPMC_IRQ { NO_IRQ, NO_IRQ } --- #define MPMC_DMA { 0, 0 } #define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ } --- #define PB1176_CLCD_DMA { 0, 0 } #define SCTL_IRQ { NO_IRQ, NO_IRQ } --- #define SCTL_DMA { 0, 0 } #define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG, NO_IRQ } --- #define PB1176_WATCHDOG_DMA { 0, 0 } #define PB1176_GPIO0_IRQ { IRQ_PB1176_GPIO0, NO_IRQ } --- #define PB1176_GPIO0_DMA { 0, 0 } #define GPIO1_IRQ { IRQ_PB1176_GPIO1, NO_IRQ } --- #define GPIO1_DMA { 0, 0 } #define PB1176_RTC_IRQ { IRQ_DC1176_RTC, NO_IRQ } --- #define PB1176_RTC_DMA { 0, 0 } #define SCI_IRQ { IRQ_PB1176_SCI, NO_IRQ } --- #define SCI_DMA { 7, 6 } #define PB1176_UART0_IRQ { IRQ_DC1176_UART0, NO_IRQ } --- #define PB1176_UART0_DMA { 15, 14 } #define PB1176_UART1_IRQ { IRQ_DC1176_UART1, NO_IRQ } --- #define PB1176_UART1_DMA { 13, 12 } #define PB1176_UART2_IRQ { IRQ_DC1176_UART2, NO_IRQ } --- #define PB1176_UART2_DMA { 11, 10 } #define PB1176_UART3_IRQ { IRQ_DC1176_UART3, NO_IRQ } --- #define PB1176_UART3_DMA { 0x86, 0x87 } #define PB1176_UART4_IRQ { IRQ_PB1176_UART4, NO_IRQ } --- #define PB1176_UART4_DMA { 0, 0 } #define PB1176_SSP_IRQ { IRQ_DC1176_SSP, NO_IRQ } --- #define PB1176_SSP_DMA { 9, 8 } /* FPGA Primecells */ AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); @@@@@ -304,14 -304,14 -304,13 -283,14 +283,14 @@@@@ static struct platform_device char_lcd_ static void __init gic_init_irq(void) { /* ARM1176 DevChip GIC, primary */ - gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE); - gic_dist_init(0, __io_address(REALVIEW_DC1176_GIC_DIST_BASE), IRQ_DC1176_GIC_START); - gic_cpu_init(0, gic_cpu_base_addr); + gic_init(0, IRQ_DC1176_GIC_START, + __io_address(REALVIEW_DC1176_GIC_DIST_BASE), + __io_address(REALVIEW_DC1176_GIC_CPU_BASE)); /* board GIC, secondary */ - gic_dist_init(1, __io_address(REALVIEW_PB1176_GIC_DIST_BASE), IRQ_PB1176_GIC_START); - gic_cpu_init(1, __io_address(REALVIEW_PB1176_GIC_CPU_BASE)); + gic_init(1, IRQ_PB1176_GIC_START, + __io_address(REALVIEW_PB1176_GIC_DIST_BASE), + __io_address(REALVIEW_PB1176_GIC_CPU_BASE)); gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1); } @@@@@ -379,9 -379,9 -378,9 -358,10 +358,10 @@@@@ static void __init realview_pb1176_init MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ --- .boot_params = PHYS_OFFSET + 0x00000100, +++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_pb1176_fixup, .map_io = realview_pb1176_map_io, +++ .init_early = realview_init_early, .init_irq = gic_init_irq, .timer = &realview_pb1176_timer, .init_machine = realview_pb1176_init, diff --combined arch/arm/mach-realview/realview_pb11mp.c index dea06b2da3a2,8e8ab7d29a6a,117b95b2ca15,27bfeca89129..b2985fc7cd4e --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c @@@@@ -136,47 -136,47 -136,47 -136,26 +136,26 @@@@@ static struct pl022_ssp_controller ssp0 */ #define GPIO2_IRQ { IRQ_PB11MP_GPIO2, NO_IRQ } --- #define GPIO2_DMA { 0, 0 } #define GPIO3_IRQ { IRQ_PB11MP_GPIO3, NO_IRQ } --- #define GPIO3_DMA { 0, 0 } #define AACI_IRQ { IRQ_TC11MP_AACI, NO_IRQ } --- #define AACI_DMA { 0x80, 0x81 } #define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B } --- #define MMCI0_DMA { 0x84, 0 } #define KMI0_IRQ { IRQ_TC11MP_KMI0, NO_IRQ } --- #define KMI0_DMA { 0, 0 } #define KMI1_IRQ { IRQ_TC11MP_KMI1, NO_IRQ } --- #define KMI1_DMA { 0, 0 } #define PB11MP_SMC_IRQ { NO_IRQ, NO_IRQ } --- #define PB11MP_SMC_DMA { 0, 0 } #define MPMC_IRQ { NO_IRQ, NO_IRQ } --- #define MPMC_DMA { 0, 0 } #define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD, NO_IRQ } --- #define PB11MP_CLCD_DMA { 0, 0 } #define DMAC_IRQ { IRQ_PB11MP_DMAC, NO_IRQ } --- #define DMAC_DMA { 0, 0 } #define SCTL_IRQ { NO_IRQ, NO_IRQ } --- #define SCTL_DMA { 0, 0 } #define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG, NO_IRQ } --- #define PB11MP_WATCHDOG_DMA { 0, 0 } #define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0, NO_IRQ } --- #define PB11MP_GPIO0_DMA { 0, 0 } #define GPIO1_IRQ { IRQ_PB11MP_GPIO1, NO_IRQ } --- #define GPIO1_DMA { 0, 0 } #define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC, NO_IRQ } --- #define PB11MP_RTC_DMA { 0, 0 } #define SCI_IRQ { IRQ_PB11MP_SCI, NO_IRQ } --- #define SCI_DMA { 7, 6 } #define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0, NO_IRQ } --- #define PB11MP_UART0_DMA { 15, 14 } #define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1, NO_IRQ } --- #define PB11MP_UART1_DMA { 13, 12 } #define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2, NO_IRQ } --- #define PB11MP_UART2_DMA { 11, 10 } #define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3, NO_IRQ } --- #define PB11MP_UART3_DMA { 0x86, 0x87 } #define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP, NO_IRQ } --- #define PB11MP_SSP_DMA { 9, 8 } /* FPGA Primecells */ AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); @@@@@ -309,13 -309,13 -309,13 -288,13 +288,13 @@@@@ static void __init gic_init_irq(void writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); /* ARM11MPCore test chip GIC, primary */ - gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE); - gic_dist_init(0, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), 29); - gic_cpu_init(0, gic_cpu_base_addr); + gic_init(0, 29, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), + __io_address(REALVIEW_TC11MP_GIC_CPU_BASE)); /* board GIC, secondary */ - gic_dist_init(1, __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), IRQ_PB11MP_GIC_START); - gic_cpu_init(1, __io_address(REALVIEW_PB11MP_GIC_CPU_BASE)); + gic_init(1, IRQ_PB11MP_GIC_START, + __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), + __io_address(REALVIEW_PB11MP_GIC_CPU_BASE)); gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1); } @@@@@ -381,9 -381,9 -381,9 -360,10 +360,10 @@@@@ static void __init realview_pb11mp_init MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ --- .boot_params = PHYS_OFFSET + 0x00000100, +++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_fixup, .map_io = realview_pb11mp_map_io, +++ .init_early = realview_init_early, .init_irq = gic_init_irq, .timer = &realview_pb11mp_timer, .init_machine = realview_pb11mp_init, diff --combined arch/arm/mach-realview/realview_pba8.c index 7d0f1734a217,841118e3e118,929b8dc12e81,11972df94313..fb6866558760 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c @@@@@ -126,47 -126,47 -126,47 -126,26 +126,26 @@@@@ static struct pl022_ssp_controller ssp0 */ #define GPIO2_IRQ { IRQ_PBA8_GPIO2, NO_IRQ } --- #define GPIO2_DMA { 0, 0 } #define GPIO3_IRQ { IRQ_PBA8_GPIO3, NO_IRQ } --- #define GPIO3_DMA { 0, 0 } #define AACI_IRQ { IRQ_PBA8_AACI, NO_IRQ } --- #define AACI_DMA { 0x80, 0x81 } #define MMCI0_IRQ { IRQ_PBA8_MMCI0A, IRQ_PBA8_MMCI0B } --- #define MMCI0_DMA { 0x84, 0 } #define KMI0_IRQ { IRQ_PBA8_KMI0, NO_IRQ } --- #define KMI0_DMA { 0, 0 } #define KMI1_IRQ { IRQ_PBA8_KMI1, NO_IRQ } --- #define KMI1_DMA { 0, 0 } #define PBA8_SMC_IRQ { NO_IRQ, NO_IRQ } --- #define PBA8_SMC_DMA { 0, 0 } #define MPMC_IRQ { NO_IRQ, NO_IRQ } --- #define MPMC_DMA { 0, 0 } #define PBA8_CLCD_IRQ { IRQ_PBA8_CLCD, NO_IRQ } --- #define PBA8_CLCD_DMA { 0, 0 } #define DMAC_IRQ { IRQ_PBA8_DMAC, NO_IRQ } --- #define DMAC_DMA { 0, 0 } #define SCTL_IRQ { NO_IRQ, NO_IRQ } --- #define SCTL_DMA { 0, 0 } #define PBA8_WATCHDOG_IRQ { IRQ_PBA8_WATCHDOG, NO_IRQ } --- #define PBA8_WATCHDOG_DMA { 0, 0 } #define PBA8_GPIO0_IRQ { IRQ_PBA8_GPIO0, NO_IRQ } --- #define PBA8_GPIO0_DMA { 0, 0 } #define GPIO1_IRQ { IRQ_PBA8_GPIO1, NO_IRQ } --- #define GPIO1_DMA { 0, 0 } #define PBA8_RTC_IRQ { IRQ_PBA8_RTC, NO_IRQ } --- #define PBA8_RTC_DMA { 0, 0 } #define SCI_IRQ { IRQ_PBA8_SCI, NO_IRQ } --- #define SCI_DMA { 7, 6 } #define PBA8_UART0_IRQ { IRQ_PBA8_UART0, NO_IRQ } --- #define PBA8_UART0_DMA { 15, 14 } #define PBA8_UART1_IRQ { IRQ_PBA8_UART1, NO_IRQ } --- #define PBA8_UART1_DMA { 13, 12 } #define PBA8_UART2_IRQ { IRQ_PBA8_UART2, NO_IRQ } --- #define PBA8_UART2_DMA { 11, 10 } #define PBA8_UART3_IRQ { IRQ_PBA8_UART3, NO_IRQ } --- #define PBA8_UART3_DMA { 0x86, 0x87 } #define PBA8_SSP_IRQ { IRQ_PBA8_SSP, NO_IRQ } --- #define PBA8_SSP_DMA { 9, 8 } /* FPGA Primecells */ AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); @@@@@ -273,9 -273,9 -273,9 -252,9 +252,9 @@@@@ static struct platform_device pmu_devic static void __init gic_init_irq(void) { /* ARM PB-A8 on-board GIC */ - gic_cpu_base_addr = __io_address(REALVIEW_PBA8_GIC_CPU_BASE); - gic_dist_init(0, __io_address(REALVIEW_PBA8_GIC_DIST_BASE), IRQ_PBA8_GIC_START); - gic_cpu_init(0, __io_address(REALVIEW_PBA8_GIC_CPU_BASE)); + gic_init(0, IRQ_PBA8_GIC_START, + __io_address(REALVIEW_PBA8_GIC_DIST_BASE), + __io_address(REALVIEW_PBA8_GIC_CPU_BASE)); } static void __init realview_pba8_timer_init(void) @@@@@ -331,9 -331,9 -331,9 -310,10 +310,10 @@@@@ static void __init realview_pba8_init(v MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ --- .boot_params = PHYS_OFFSET + 0x00000100, +++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_fixup, .map_io = realview_pba8_map_io, +++ .init_early = realview_init_early, .init_irq = gic_init_irq, .timer = &realview_pba8_timer, .init_machine = realview_pba8_init, diff --combined arch/arm/mach-realview/realview_pbx.c index b89e28f8853e,02b755b009db,b9f9e20031a7,73ab3ca9355e..92ace2cf2b2c --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c @@@@@ -148,47 -148,47 -148,47 -148,26 +148,26 @@@@@ static struct pl022_ssp_controller ssp0 */ #define GPIO2_IRQ { IRQ_PBX_GPIO2, NO_IRQ } --- #define GPIO2_DMA { 0, 0 } #define GPIO3_IRQ { IRQ_PBX_GPIO3, NO_IRQ } --- #define GPIO3_DMA { 0, 0 } #define AACI_IRQ { IRQ_PBX_AACI, NO_IRQ } --- #define AACI_DMA { 0x80, 0x81 } #define MMCI0_IRQ { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B } --- #define MMCI0_DMA { 0x84, 0 } #define KMI0_IRQ { IRQ_PBX_KMI0, NO_IRQ } --- #define KMI0_DMA { 0, 0 } #define KMI1_IRQ { IRQ_PBX_KMI1, NO_IRQ } --- #define KMI1_DMA { 0, 0 } #define PBX_SMC_IRQ { NO_IRQ, NO_IRQ } --- #define PBX_SMC_DMA { 0, 0 } #define MPMC_IRQ { NO_IRQ, NO_IRQ } --- #define MPMC_DMA { 0, 0 } #define PBX_CLCD_IRQ { IRQ_PBX_CLCD, NO_IRQ } --- #define PBX_CLCD_DMA { 0, 0 } #define DMAC_IRQ { IRQ_PBX_DMAC, NO_IRQ } --- #define DMAC_DMA { 0, 0 } #define SCTL_IRQ { NO_IRQ, NO_IRQ } --- #define SCTL_DMA { 0, 0 } #define PBX_WATCHDOG_IRQ { IRQ_PBX_WATCHDOG, NO_IRQ } --- #define PBX_WATCHDOG_DMA { 0, 0 } #define PBX_GPIO0_IRQ { IRQ_PBX_GPIO0, NO_IRQ } --- #define PBX_GPIO0_DMA { 0, 0 } #define GPIO1_IRQ { IRQ_PBX_GPIO1, NO_IRQ } --- #define GPIO1_DMA { 0, 0 } #define PBX_RTC_IRQ { IRQ_PBX_RTC, NO_IRQ } --- #define PBX_RTC_DMA { 0, 0 } #define SCI_IRQ { IRQ_PBX_SCI, NO_IRQ } --- #define SCI_DMA { 7, 6 } #define PBX_UART0_IRQ { IRQ_PBX_UART0, NO_IRQ } --- #define PBX_UART0_DMA { 15, 14 } #define PBX_UART1_IRQ { IRQ_PBX_UART1, NO_IRQ } --- #define PBX_UART1_DMA { 13, 12 } #define PBX_UART2_IRQ { IRQ_PBX_UART2, NO_IRQ } --- #define PBX_UART2_DMA { 11, 10 } #define PBX_UART3_IRQ { IRQ_PBX_UART3, NO_IRQ } --- #define PBX_UART3_DMA { 0x86, 0x87 } #define PBX_SSP_IRQ { IRQ_PBX_SSP, NO_IRQ } --- #define PBX_SSP_DMA { 9, 8 } /* FPGA Primecells */ AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); @@@@@ -313,12 -313,12 -313,15 -292,12 +292,12 @@@@@ static void __init gic_init_irq(void { /* ARM PBX on-board GIC */ if (core_tile_pbx11mp() || core_tile_pbxa9mp()) { - gic_cpu_base_addr = __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE); - gic_dist_init(0, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE), - 29); - gic_cpu_init(0, __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE)); + gic_init(0, 29, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE), + __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE)); } else { - gic_cpu_base_addr = __io_address(REALVIEW_PBX_GIC_CPU_BASE); - gic_dist_init(0, __io_address(REALVIEW_PBX_GIC_DIST_BASE), - IRQ_PBX_GIC_START); - gic_cpu_init(0, __io_address(REALVIEW_PBX_GIC_CPU_BASE)); + gic_init(0, IRQ_PBX_GIC_START, + __io_address(REALVIEW_PBX_GIC_DIST_BASE), + __io_address(REALVIEW_PBX_GIC_CPU_BASE)); } } @@@@@ -414,9 -414,9 -417,9 -393,10 +393,10 @@@@@ static void __init realview_pbx_init(vo MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ --- .boot_params = PHYS_OFFSET + 0x00000100, +++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_pbx_fixup, .map_io = realview_pbx_map_io, +++ .init_early = realview_init_early, .init_irq = gic_init_irq, .timer = &realview_pbx_timer, .init_machine = realview_pbx_init, diff --combined arch/arm/mach-vexpress/ct-ca9x4.c index e9bccc5230c9,e628402b754c,fd25ccd7272f,ff48ebc1a40b..30d5a5b0ac21 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c @@@@@ -8,8 -8,8 -8,8 -8,8 +8,8 @@@@@ #include #include #include + #include - #include #include #include #include @@@@@ -18,9 -18,9 -18,10 -18,9 +18,9 @@@@@ #include #include - #include #include - #include + #include #include #include @@@@@ -30,6 -30,6 -31,6 -30,8 +30,8 @@@@@ #include +++ #include +++ #define V2M_PA_CS7 0x10000000 static struct map_desc ct_ca9x4_io_desc[] __initdata = { @@@@@ -59,10 -59,10 -60,13 -61,10 +61,10 @@@@@ static void __init ct_ca9x4_map_io(void v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc)); } - void __iomem *gic_cpu_base_addr; - static void __init ct_ca9x4_init_irq(void) { - gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU); - gic_dist_init(0, MMIO_P2V(A9_MPCORE_GIC_DIST), 29); - gic_cpu_init(0, gic_cpu_base_addr); + gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST), + MMIO_P2V(A9_MPCORE_GIC_CPU)); } #if 0 @@@@@ -80,29 -80,29 -84,29 -82,6 +82,6 @@@@@ static struct sys_timer ct_ca9x4_timer }; #endif --- static struct clcd_panel xvga_panel = { --- .mode = { --- .name = "XVGA", --- .refresh = 60, --- .xres = 1024, --- .yres = 768, --- .pixclock = 15384, --- .left_margin = 168, --- .right_margin = 8, --- .upper_margin = 29, --- .lower_margin = 3, --- .hsync_len = 144, --- .vsync_len = 6, --- .sync = 0, --- .vmode = FB_VMODE_NONINTERLACED, --- }, --- .width = -1, --- .height = -1, --- .tim2 = TIM2_BCD | TIM2_IPC, --- .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), --- .bpp = 16, --- }; --- static void ct_ca9x4_clcd_enable(struct clcd_fb *fb) { v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0); @@@@@ -112,42 -112,42 -116,42 -91,23 +91,23 @@@@@ static int ct_ca9x4_clcd_setup(struct clcd_fb *fb) { unsigned long framesize = 1024 * 768 * 2; --- dma_addr_t dma; -- -- fb->panel = &xvga_panel; -- fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, -- &dma, GFP_KERNEL); -- if (!fb->fb.screen_base) { -- printk(KERN_ERR "CLCD: unable to map frame buffer\n"); -- return -ENOMEM; -- } -- fb->fb.fix.smem_start = dma; -- fb->fb.fix.smem_len = framesize; -- -- return 0; -- } -- -- static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) -- { -- return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base, -- fb->fb.fix.smem_start, fb->fb.fix.smem_len); -- } - fb->panel = &xvga_panel; +++ fb->panel = versatile_clcd_get_panel("XVGA"); +++ if (!fb->panel) +++ return -EINVAL; - fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, - &dma, GFP_KERNEL); - if (!fb->fb.screen_base) { - printk(KERN_ERR "CLCD: unable to map frame buffer\n"); - return -ENOMEM; - } - fb->fb.fix.smem_start = dma; - fb->fb.fix.smem_len = framesize; - - return 0; - } - - static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) - { - return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base, - fb->fb.fix.smem_start, fb->fb.fix.smem_len); - } - --- static void ct_ca9x4_clcd_remove(struct clcd_fb *fb) --- { --- dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, --- fb->fb.screen_base, fb->fb.fix.smem_start); +++ return versatile_clcd_setup_dma(fb, framesize); } static struct clcd_board ct_ca9x4_clcd_data = { .name = "CT-CA9X4", +++ .caps = CLCD_CAP_5551 | CLCD_CAP_565, .check = clcdfb_check, .decode = clcdfb_decode, .enable = ct_ca9x4_clcd_enable, .setup = ct_ca9x4_clcd_setup, --- .mmap = ct_ca9x4_clcd_mmap, --- .remove = ct_ca9x4_clcd_remove, +++ .mmap = versatile_clcd_mmap_dma, +++ .remove = versatile_clcd_remove_dma, }; static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data); @@@@@ -220,6 -220,6 -224,6 -180,13 +180,13 @@@@@ static struct platform_device pmu_devic .resource = pmu_resources, }; +++ static void __init ct_ca9x4_init_early(void) +++ { +++ clkdev_add_table(lookups, ARRAY_SIZE(lookups)); +++ +++ v2m_init_early(); +++ } +++ static void __init ct_ca9x4_init(void) { int i; @@@@@ -234,8 -234,8 -238,8 -201,6 +201,6 @@@@@ l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff); #endif --- clkdev_add_table(lookups, ARRAY_SIZE(lookups)); --- for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++) amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource); @@@@@ -243,9 -243,9 -247,9 -208,10 +208,10 @@@@@ } MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4") --- .boot_params = PHYS_OFFSET + 0x00000100, +++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .map_io = ct_ca9x4_map_io, .init_irq = ct_ca9x4_init_irq, +++ .init_early = ct_ca9x4_init_early, #if 0 .timer = &ct_ca9x4_timer, #else diff --combined arch/arm/mm/dma-mapping.c index 4771dba61448,4771dba61448,a9bdfcda23f4,4771dba61448..82a093cee09a --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@@@@ -17,7 -17,7 -17,6 -17,7 +17,7 @@@@@ #include #include #include + #include #include #include @@@@@ -149,6 -149,6 -148,7 -149,6 +149,7 @@@@@ static int __init consistent_init(void { int ret = 0; pgd_t *pgd; ++ + pud_t *pud; pmd_t *pmd; pte_t *pte; int i = 0; @@@@@ -156,7 -156,7 -156,15 -156,7 +157,15 @@@@@ do { pgd = pgd_offset(&init_mm, base); -- - pmd = pmd_alloc(&init_mm, pgd, base); ++ + ++ + pud = pud_alloc(&init_mm, pgd, base); ++ + if (!pud) { ++ + printk(KERN_ERR "%s: no pud tables\n", __func__); ++ + ret = -ENOMEM; ++ + break; ++ + } ++ + ++ + pmd = pmd_alloc(&init_mm, pud, base); if (!pmd) { printk(KERN_ERR "%s: no pmd tables\n", __func__); ret = -ENOMEM; @@@@@ -312,7 -312,7 -320,7 -312,7 +321,7 @@@@@ __dma_alloc(struct device *dev, size_t addr = page_address(page); if (addr) - *handle = page_to_dma(dev, page); + *handle = pfn_to_dma(dev, page_to_pfn(page)); return addr; } @@@@@ -407,7 -407,7 -415,7 -407,7 +416,7 @@@@@ void dma_free_coherent(struct device *d if (!arch_is_coherent()) __dma_free_remap(cpu_addr, size); - __dma_free_buffer(dma_to_page(dev, handle), size); + __dma_free_buffer(pfn_to_page(dma_to_pfn(dev, handle)), size); } EXPORT_SYMBOL(dma_free_coherent); @@@@@ -481,10 -481,10 -489,10 -481,10 +490,10 @@@@@ static void dma_cache_maint_page(struc op(vaddr, len, dir); kunmap_high(page); } else if (cache_is_vipt()) { - pte_t saved_pte; - vaddr = kmap_high_l1_vipt(page, &saved_pte); + /* unmapped pages might still be cached */ + vaddr = kmap_atomic(page); op(vaddr + offset, len, dir); - kunmap_high_l1_vipt(page, saved_pte); + kunmap_atomic(vaddr); } } else { vaddr = page_address(page) + offset; @@@@@ -555,20 -555,20 -563,17 -555,20 +564,20 @@@@@ int dma_map_sg(struct device *dev, stru struct scatterlist *s; int i, j; + BUG_ON(!valid_dma_direction(dir)); + for_each_sg(sg, s, nents, i) { - s->dma_address = dma_map_page(dev, sg_page(s), s->offset, + s->dma_address = __dma_map_page(dev, sg_page(s), s->offset, s->length, dir); if (dma_mapping_error(dev, s->dma_address)) goto bad_mapping; } + debug_dma_map_sg(dev, sg, nents, nents, dir); return nents; bad_mapping: for_each_sg(sg, s, i, j) - dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); + __dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); return 0; } EXPORT_SYMBOL(dma_map_sg); @@@@@ -577,7 -577,7 -582,7 -577,7 +586,7 @@@@@ * dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices * @sg: list of buffers - * @nents: number of buffers to unmap (returned from dma_map_sg) + * @nents: number of buffers to unmap (same as was passed to dma_map_sg) * @dir: DMA transfer direction (same as was passed to dma_map_sg) * * Unmap a set of streaming mode DMA translations. Again, CPU access @@@@@ -589,10 -589,10 -594,8 -589,10 +598,10 @@@@@ void dma_unmap_sg(struct device *dev, s struct scatterlist *s; int i; + debug_dma_unmap_sg(dev, sg, nents, dir); + for_each_sg(sg, s, nents, i) - dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); + __dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); } EXPORT_SYMBOL(dma_unmap_sg); @@@@@ -617,8 -617,8 -620,6 -617,8 +626,8 @@@@@ void dma_sync_sg_for_cpu(struct device __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); } + + debug_dma_sync_sg_for_cpu(dev, sg, nents, dir); } EXPORT_SYMBOL(dma_sync_sg_for_cpu); @@@@@ -643,16 -643,16 -644,5 -643,16 +652,16 @@@@@ void dma_sync_sg_for_device(struct devi __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); } + + debug_dma_sync_sg_for_device(dev, sg, nents, dir); } EXPORT_SYMBOL(dma_sync_sg_for_device); + + #define PREALLOC_DMA_DEBUG_ENTRIES 4096 + + static int __init dma_debug_do_init(void) + { + dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); + return 0; + } + fs_initcall(dma_debug_do_init); diff --combined arch/arm/mm/init.c index cddd684364da,cddd684364da,14a00a1ef52f,5164069ced42..b3b0f0f5053d --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@@@@ -297,12 -297,12 -297,6 -297,6 +297,12 @@@@@ void __init arm_memblock_init(struct me memblock_reserve(__pa(_stext), _end - _stext); #endif #ifdef CONFIG_BLK_DEV_INITRD ++ if (phys_initrd_size && ++ memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) { ++ pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n", ++ phys_initrd_start, phys_initrd_size); ++ phys_initrd_start = phys_initrd_size = 0; ++ } if (phys_initrd_size) { memblock_reserve(phys_initrd_start, phys_initrd_size); @@@@@ -350,7 -350,7 -344,7 -344,7 +350,7 @@@@@ void __init bootmem_init(void */ arm_bootmem_free(min, max_low, max_high); -- - high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1; ++ + high_memory = __va(((phys_addr_t)max_low << PAGE_SHIFT) - 1) + 1; /* * This doesn't seem to be used by the Linux memory manager any @@@@@ -398,8 -398,8 -392,8 -392,8 +398,8 @@@@@ free_memmap(unsigned long start_pfn, un * Convert to physical addresses, and * round start upwards and end downwards. */ -- - pg = PAGE_ALIGN(__pa(start_pg)); -- - pgend = __pa(end_pg) & PAGE_MASK; ++ + pg = (unsigned long)PAGE_ALIGN(__pa(start_pg)); ++ + pgend = (unsigned long)__pa(end_pg) & PAGE_MASK; /* * If there are free pages between these, diff --combined arch/arm/mm/mmu.c index ff7b43b5885a,3c67e92f7d59,82ef6966ae09,3c67e92f7d59..6cf76b3b68d1 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@@@@ -24,7 -24,7 -24,6 -24,7 +24,7 @@@@@ #include #include #include + #include #include #include @@@@@ -533,7 -533,7 -532,7 -533,7 +533,7 @@@@@ static void __init *early_alloc(unsigne static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) { if (pmd_none(*pmd)) { -- - pte_t *pte = early_alloc(2 * PTRS_PER_PTE * sizeof(pte_t)); ++ + pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); __pmd_populate(pmd, __pa(pte), prot); } BUG_ON(pmd_bad(*pmd)); @@@@@ -551,11 -551,11 -550,11 -551,11 +551,11 @@@@@ static void __init alloc_init_pte(pmd_ } while (pte++, addr += PAGE_SIZE, addr != end); } -- -static void __init alloc_init_section(pgd_t *pgd, unsigned long addr, ++ +static void __init alloc_init_section(pud_t *pud, unsigned long addr, unsigned long end, phys_addr_t phys, const struct mem_type *type) { -- - pmd_t *pmd = pmd_offset(pgd, addr); ++ + pmd_t *pmd = pmd_offset(pud, addr); /* * Try a section mapping - end, addr and phys must all be aligned @@@@@ -584,6 -584,6 -583,19 -584,6 +584,19 @@@@@ } } ++ +static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end, ++ + unsigned long phys, const struct mem_type *type) ++ +{ ++ + pud_t *pud = pud_offset(pgd, addr); ++ + unsigned long next; ++ + ++ + do { ++ + next = pud_addr_end(addr, end); ++ + alloc_init_section(pud, addr, next, phys, type); ++ + phys += next - addr; ++ + } while (pud++, addr = next, addr != end); ++ +} ++ + static void __init create_36bit_mapping(struct map_desc *md, const struct mem_type *type) { @@@@@ -592,13 -592,13 -604,13 -592,13 +605,13 @@@@@ pgd_t *pgd; addr = md->virtual; -- - phys = (unsigned long)__pfn_to_phys(md->pfn); ++ + phys = __pfn_to_phys(md->pfn); length = PAGE_ALIGN(md->length); if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { printk(KERN_ERR "MM: CPU does not support supersection " "mapping for 0x%08llx at 0x%08lx\n", -- - __pfn_to_phys((u64)md->pfn), addr); ++ + (long long)__pfn_to_phys((u64)md->pfn), addr); return; } @@@@@ -611,14 -611,14 -623,14 -611,14 +624,14 @@@@@ if (type->domain) { printk(KERN_ERR "MM: invalid domain in supersection " "mapping for 0x%08llx at 0x%08lx\n", -- - __pfn_to_phys((u64)md->pfn), addr); ++ + (long long)__pfn_to_phys((u64)md->pfn), addr); return; } if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { -- - printk(KERN_ERR "MM: cannot create mapping for " -- - "0x%08llx at 0x%08lx invalid alignment\n", -- - __pfn_to_phys((u64)md->pfn), addr); ++ + printk(KERN_ERR "MM: cannot create mapping for 0x%08llx" ++ + " at 0x%08lx invalid alignment\n", ++ + (long long)__pfn_to_phys((u64)md->pfn), addr); return; } @@@@@ -631,7 -631,7 -643,8 -631,7 +644,8 @@@@@ pgd = pgd_offset_k(addr); end = addr + length; do { -- - pmd_t *pmd = pmd_offset(pgd, addr); ++ + pud_t *pud = pud_offset(pgd, addr); ++ + pmd_t *pmd = pmd_offset(pud, addr); int i; for (i = 0; i < 16; i++) @@@@@ -652,22 -652,22 -665,23 -652,22 +666,23 @@@@@ */ static void __init create_mapping(struct map_desc *md) { -- - unsigned long phys, addr, length, end; ++ + unsigned long addr, length, end; ++ + phys_addr_t phys; const struct mem_type *type; pgd_t *pgd; if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { -- - printk(KERN_WARNING "BUG: not creating mapping for " -- - "0x%08llx at 0x%08lx in user region\n", -- - __pfn_to_phys((u64)md->pfn), md->virtual); ++ + printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx" ++ + " at 0x%08lx in user region\n", ++ + (long long)__pfn_to_phys((u64)md->pfn), md->virtual); return; } if ((md->type == MT_DEVICE || md->type == MT_ROM) && md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) { -- - printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx " -- - "overlaps vmalloc space\n", -- - __pfn_to_phys((u64)md->pfn), md->virtual); ++ + printk(KERN_WARNING "BUG: mapping for 0x%08llx" ++ + " at 0x%08lx overlaps vmalloc space\n", ++ + (long long)__pfn_to_phys((u64)md->pfn), md->virtual); } type = &mem_types[md->type]; @@@@@ -681,13 -681,13 -695,13 -681,13 +696,13 @@@@@ } addr = md->virtual & PAGE_MASK; -- - phys = (unsigned long)__pfn_to_phys(md->pfn); ++ + phys = __pfn_to_phys(md->pfn); length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { -- - printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not " ++ + printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not " "be mapped using pages, ignoring.\n", -- - __pfn_to_phys(md->pfn), addr); ++ + (long long)__pfn_to_phys(md->pfn), addr); return; } @@@@@ -696,7 -696,7 -710,7 -696,7 +711,7 @@@@@ do { unsigned long next = pgd_addr_end(addr, end); -- - alloc_init_section(pgd, addr, next, phys, type); ++ + alloc_init_pud(pgd, addr, next, phys, type); phys += next - addr; addr = next; @@@@@ -794,9 -794,9 -808,10 -794,9 +809,10 @@@@@ static void __init sanity_check_meminfo */ if (__va(bank->start) >= vmalloc_min || __va(bank->start) < (void *)PAGE_OFFSET) { -- - printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx " ++ + printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " "(vmalloc region overlap).\n", -- - bank->start, bank->start + bank->size - 1); ++ + (unsigned long long)bank->start, ++ + (unsigned long long)bank->start + bank->size - 1); continue; } @@@@@ -807,10 -807,10 -822,11 -807,10 +823,11 @@@@@ if (__va(bank->start + bank->size) > vmalloc_min || __va(bank->start + bank->size) < __va(bank->start)) { unsigned long newsize = vmalloc_min - __va(bank->start); -- - printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx " -- - "to -%.8lx (vmalloc region overlap).\n", -- - bank->start, bank->start + bank->size - 1, -- - bank->start + newsize - 1); ++ + printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx " ++ + "to -%.8llx (vmalloc region overlap).\n", ++ + (unsigned long long)bank->start, ++ + (unsigned long long)bank->start + bank->size - 1, ++ + (unsigned long long)bank->start + newsize - 1); bank->size = newsize; } #endif @@@@@ -827,6 -827,16 -843,16 -827,16 +844,6 @@@@@ * rather difficult. */ reason = "with VIPT aliasing cache"; --- } else if (is_smp() && tlb_ops_need_broadcast()) { --- /* --- * kmap_high needs to occasionally flush TLB entries, --- * however, if the TLB entries need to be broadcast --- * we may deadlock: --- * kmap_high(irqs off)->flush_all_zero_pkmaps-> --- * flush_tlb_kernel_range->smp_call_function_many --- * (must not be called with irqs off) --- */ --- reason = "without hardware TLB ops broadcasting"; } if (reason) { printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", @@@@@ -904,11 -914,11 -930,12 -914,11 +921,11 @@@@@ static void __init devicemaps_init(stru { struct map_desc map; unsigned long addr; - void *vectors; /* * Allocate the vector page early. */ - vectors = early_alloc(PAGE_SIZE); + vectors_page = early_alloc(PAGE_SIZE); for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) pmd_clear(pmd_off_k(addr)); @@@@@ -948,7 -958,7 -975,7 -958,7 +965,7 @@@@@ * location (0xffff0000). If we aren't using high-vectors, also * create a mapping at the low-vectors virtual address. */ - map.pfn = __phys_to_pfn(virt_to_phys(vectors)); + map.pfn = __phys_to_pfn(virt_to_phys(vectors_page)); map.virtual = 0xffff0000; map.length = PAGE_SIZE; map.type = MT_HIGH_VECTORS; diff --combined arch/arm/mm/pgd.c index 709244c66fa3,709244c66fa3,f7fafb1741f4,709244c66fa3..b2027c154b2a --- a/arch/arm/mm/pgd.c +++ b/arch/arm/mm/pgd.c @@@@@ -23,6 -23,6 -23,7 -23,6 +23,7 @@@@@ pgd_t *pgd_alloc(struct mm_struct *mm) { pgd_t *new_pgd, *init_pgd; ++ + pud_t *new_pud, *init_pud; pmd_t *new_pmd, *init_pmd; pte_t *new_pte, *init_pte; @@@@@ -46,15 -46,15 -47,20 -46,15 +47,20 @@@@@ * On ARM, first page must always be allocated since it * contains the machine vectors. */ -- - new_pmd = pmd_alloc(mm, new_pgd, 0); ++ + new_pud = pud_alloc(mm, new_pgd, 0); ++ + if (!new_pud) ++ + goto no_pud; ++ + ++ + new_pmd = pmd_alloc(mm, new_pud, 0); if (!new_pmd) goto no_pmd; - new_pte = pte_alloc_map(mm, new_pmd, 0); + new_pte = pte_alloc_map(mm, NULL, new_pmd, 0); if (!new_pte) goto no_pte; -- - init_pmd = pmd_offset(init_pgd, 0); ++ + init_pud = pud_offset(init_pgd, 0); ++ + init_pmd = pmd_offset(init_pud, 0); init_pte = pte_offset_map(init_pmd, 0); set_pte_ext(new_pte, *init_pte, 0); pte_unmap(init_pte); @@@@@ -66,6 -66,6 -72,8 -66,6 +72,8 @@@@@ no_pte: pmd_free(mm, new_pmd); no_pmd: ++ + pud_free(mm, new_pud); ++ +no_pud: free_pages((unsigned long)new_pgd, 2); no_pgd: return NULL; @@@@@ -74,6 -74,6 -82,7 -74,6 +82,7 @@@@@ void pgd_free(struct mm_struct *mm, pgd_t *pgd_base) { pgd_t *pgd; ++ + pud_t *pud; pmd_t *pmd; pgtable_t pte; @@@@@ -84,7 -84,7 -93,11 -84,7 +93,11 @@@@@ if (pgd_none_or_clear_bad(pgd)) goto no_pgd; -- - pmd = pmd_offset(pgd, 0); ++ + pud = pud_offset(pgd, 0); ++ + if (pud_none_or_clear_bad(pud)) ++ + goto no_pud; ++ + ++ + pmd = pmd_offset(pud, 0); if (pmd_none_or_clear_bad(pmd)) goto no_pmd; @@@@@ -92,8 -92,8 -105,11 -92,8 +105,11 @@@@@ pmd_clear(pmd); pte_free(mm, pte); no_pmd: -- - pgd_clear(pgd); ++ + pud_clear(pud); pmd_free(mm, pmd); ++ +no_pud: ++ + pgd_clear(pgd); ++ + pud_free(mm, pud); no_pgd: free_pages((unsigned long) pgd_base, 2); } diff --combined drivers/video/amba-clcd.c index 013c8ce57205,1c2c68356ea7,1c2c68356ea7,8bd370697533..5fc983c5b92c --- a/drivers/video/amba-clcd.c +++ b/drivers/video/amba-clcd.c @@@@@ -120,8 -120,8 -120,8 -120,23 +120,23 @@@@@ static void clcdfb_enable(struct clcd_f static int clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var) { +++ u32 caps; int ret = 0; +++ if (fb->panel->caps && fb->board->caps) +++ caps = fb->panel->caps & fb->board->caps; +++ else { +++ /* Old way of specifying what can be used */ +++ caps = fb->panel->cntl & CNTL_BGR ? +++ CLCD_CAP_BGR : CLCD_CAP_RGB; +++ /* But mask out 444 modes as they weren't supported */ +++ caps &= ~CLCD_CAP_444; +++ } +++ +++ /* Only TFT panels can do RGB888/BGR888 */ +++ if (!(fb->panel->cntl & CNTL_LCDTFT)) +++ caps &= ~CLCD_CAP_888; +++ memset(&var->transp, 0, sizeof(var->transp)); var->red.msb_right = 0; @@@@@ -133,6 -133,6 -133,6 -148,13 +148,13 @@@@@ case 2: case 4: case 8: +++ /* If we can't do 5551, reject */ +++ caps &= CLCD_CAP_5551; +++ if (!caps) { +++ ret = -EINVAL; +++ break; +++ } +++ var->red.length = var->bits_per_pixel; var->red.offset = 0; var->green.length = var->bits_per_pixel; @@@@@ -140,23 -140,23 -140,23 -162,61 +162,61 @@@@@ var->blue.length = var->bits_per_pixel; var->blue.offset = 0; break; +++ case 16: --- var->red.length = 5; --- var->blue.length = 5; +++ /* If we can't do 444, 5551 or 565, reject */ +++ if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) { +++ ret = -EINVAL; +++ break; +++ } +++ /* --- * Green length can be 5 or 6 depending whether --- * we're operating in RGB555 or RGB565 mode. +++ * Green length can be 4, 5 or 6 depending whether +++ * we're operating in 444, 5551 or 565 mode. */ --- if (var->green.length != 5 && var->green.length != 6) --- var->green.length = 6; +++ if (var->green.length == 4 && caps & CLCD_CAP_444) +++ caps &= CLCD_CAP_444; +++ if (var->green.length == 5 && caps & CLCD_CAP_5551) +++ caps &= CLCD_CAP_5551; +++ else if (var->green.length == 6 && caps & CLCD_CAP_565) +++ caps &= CLCD_CAP_565; +++ else { +++ /* +++ * PL110 officially only supports RGB555, +++ * but may be wired up to allow RGB565. +++ */ +++ if (caps & CLCD_CAP_565) { +++ var->green.length = 6; +++ caps &= CLCD_CAP_565; +++ } else if (caps & CLCD_CAP_5551) { +++ var->green.length = 5; +++ caps &= CLCD_CAP_5551; +++ } else { +++ var->green.length = 4; +++ caps &= CLCD_CAP_444; +++ } +++ } +++ +++ if (var->green.length >= 5) { +++ var->red.length = 5; +++ var->blue.length = 5; +++ } else { +++ var->red.length = 4; +++ var->blue.length = 4; +++ } break; case 32: --- if (fb->panel->cntl & CNTL_LCDTFT) { --- var->red.length = 8; --- var->green.length = 8; --- var->blue.length = 8; +++ /* If we can't do 888, reject */ +++ caps &= CLCD_CAP_888; +++ if (!caps) { +++ ret = -EINVAL; break; } +++ +++ var->red.length = 8; +++ var->green.length = 8; +++ var->blue.length = 8; +++ break; default: ret = -EINVAL; break; @@@@@ -168,7 -168,7 -168,7 -228,20 +228,20 @@@@@ * the bitfield length defined above. */ if (ret == 0 && var->bits_per_pixel >= 16) { --- if (fb->panel->cntl & CNTL_BGR) { +++ bool bgr, rgb; +++ +++ bgr = caps & CLCD_CAP_BGR && var->blue.offset == 0; +++ rgb = caps & CLCD_CAP_RGB && var->red.offset == 0; +++ +++ if (!bgr && !rgb) +++ /* +++ * The requested format was not possible, try just +++ * our capabilities. One of BGR or RGB must be +++ * supported. +++ */ +++ bgr = caps & CLCD_CAP_BGR; +++ +++ if (bgr) { var->blue.offset = 0; var->green.offset = var->blue.offset + var->blue.length; var->red.offset = var->green.offset + var->green.length; @@@@@ -443,8 -443,8 -443,8 -516,8 +516,8 @@@@@ static int clcdfb_register(struct clcd_ fb_set_var(&fb->fb, &fb->fb.var); --- printk(KERN_INFO "CLCD: %s hardware, %s display\n", --- fb->board->name, fb->panel->mode.name); +++ dev_info(&fb->dev->dev, "%s hardware, %s display\n", +++ fb->board->name, fb->panel->mode.name); ret = register_framebuffer(&fb->fb); if (ret == 0) @@@@@ -461,7 -461,7 -461,7 -534,7 +534,7 @@@@@ return ret; } ---static int clcdfb_probe(struct amba_device *dev, struct amba_id *id) +++static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id) { struct clcd_board *board = dev->dev.platform_data; struct clcd_fb *fb; @@@@@ -486,6 -486,6 -486,6 -559,10 +559,10 @@@@@ fb->dev = dev; fb->board = board; +++ dev_info(&fb->dev->dev, "PL%03x rev%u at 0x%08llx\n", +++ amba_part(dev), amba_rev(dev), +++ (unsigned long long)dev->res.start); +++ ret = fb->board->setup(fb); if (ret) goto free_fb;