From: Jon Hunter <jonathanh@nvidia.com>
Date: Tue, 5 May 2015 14:17:53 +0000 (+0100)
Subject: serial: tegra: Add delay after enabling FIFO mode
X-Git-Tag: omap-for-v4.2/wakeirq-drivers-v2^2~73
X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=11e71007a5652dce2528a5d2451fe2697c6a370a;p=pandora-kernel.git

serial: tegra: Add delay after enabling FIFO mode

For all tegra devices (up to t210), there is a hardware issue that
requires software to wait for 3 UART clock periods after enabling
the TX fifo, otherwise data could be lost.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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