From: Andi Kleen Date: Thu, 12 Feb 2009 12:49:35 +0000 (+0100) Subject: x86, mce, cmci: define MSR names and fields for new CMCI registers X-Git-Tag: v2.6.30-rc1~2^2~50^2~5^2~8 X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=03195c6b40f2b4db92545921daa7c3a19b4e4c32;p=pandora-kernel.git x86, mce, cmci: define MSR names and fields for new CMCI registers Impact: New register definitions only CMCI means support for raising an interrupt on a corrected machine check event instead of having to poll for it. It's a new feature in Intel Nehalem CPUs available on some machine check banks. For details see the IA32 SDM Vol3a 14.5 Define the registers for it as a preparation for further patches. Signed-off-by: Andi Kleen Signed-off-by: H. Peter Anvin --- Reading git-diff-tree failed