From: Deepak K Date: Mon, 2 Aug 2010 10:18:12 +0000 (+0300) Subject: omap2/3/4: serial: errata i202: fix for MDR1 access X-Git-Tag: v2.6.36-rc1~488^2~22 X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0003450964357ec85eeeeda2e4bb8b06a6f82ad3;p=pandora-kernel.git omap2/3/4: serial: errata i202: fix for MDR1 access Errata i202 (OMAP3430 - 1.12, OMAP3630 - 1.6): UART module MDR1 register access can cause a dummy underrun condition which could result in a freeze in the case of IrDA communication or if used as UART, corrupted data. Workaround is as follows for everytime MDR1 register is changed: * setup all required UART registers * setup MDR1.MODE_SELECT bit field * Wait 5 L4 clk cycles + 5 UART functional clock cycles * Clear the Tx and RX fifo using FCR register Note: The following step is not done as I am assuming it is not needed due to reconfiguration being done and there is no halted operation perse. * Read if required, the RESUME register to resume halted operation Based on an earlier patch at: http://git.omapzoom.org/?p=kernel/omap.git;a=commitdiff;h=42d4a342c009bd9727c100abc8a4bc3063c22f0c Signed-off-by: Deepak K Signed-off-by: Nishanth Menon Signed-off-by: Tony Lindgren --- Reading git-diff-tree failed