Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

+ ae350: modify memory layout and target name
+ ae350: use generic RISC-V timer driver in S-mode
+ Support bootstage report for RISC-V
+ Support C extension exception command for RISC-V
+ Add Starfive timer support

diff --git a/.gitignore b/.gitignore
index 9697f00..aa01604 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -107,5 +107,5 @@ __pycache__
 /pylint.cur
 /pylint.out/
 
-# moveconfig database
-/moveconfig.db
+# qconfig database
+/qconfig.db

diff --git a/MAINTAINERS b/MAINTAINERS
index 4df7925..efa71db 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -622,7 +622,7 @@ F:  drivers/ram/stm32mp1/
 F:     drivers/remoteproc/stm32_copro.c
 F:     drivers/reset/stm32-reset.c
 F:     drivers/rng/optee_rng.c
-F:     drivers/rng/stm32mp1_rng.c
+F:     drivers/rng/stm32_rng.c
 F:     drivers/rtc/stm32_rtc.c
 F:     drivers/serial/serial_stm32.*
 F:     drivers/spi/stm32_qspi.c

diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
index f8c04e8..d6c6baa 100644 (file)
--- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
@@ -14,143 +14,143 @@
        };
 
        memory@80000000 {
-               bootph-pre-ram;
+               bootph-all;
        };
 
        /* Keep the LEDs on by default to indicate life */
        leds {
-               bootph-pre-ram;
+               bootph-all;
                led-0 {
                        default-state = "on";
-                       bootph-pre-ram;
+                       bootph-all;
                };
 
                led-1 {
                        default-state = "on";
-                       bootph-pre-ram;
+                       bootph-all;
                };
 
                led-2 {
                        default-state = "on";
-                       bootph-pre-ram;
+                       bootph-all;
                };
 
                led-3 {
                        default-state = "on";
-                       bootph-pre-ram;
+                       bootph-all;
                };
 
                led-4 {
                        default-state = "on";
-                       bootph-pre-ram;
+                       bootph-all;
                };
        };
 };
 
 &cbass_main {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_timer0 {
        clock-frequency = <25000000>;
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &dmss {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &secure_proxy_main {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &dmsc {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &k3_pds {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &k3_clks {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &k3_reset {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &dmsc {
-       bootph-pre-ram;
+       bootph-all;
        k3_sysreset: sysreset-controller {
                compatible = "ti,sci-sysreset";
-               bootph-pre-ram;
+               bootph-all;
        };
 };
 
 &wkup_conf {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &chipid {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_pmx0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_uart0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &console_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &cbass_mcu {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &cbass_wakeup {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &mcu_pmx0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_i2c0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &local_i2c_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &gpio0_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_gpio0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_gpio1 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &sdhci0 {
        /* EMMC */
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &emmc_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &sd_pins_default {
-       bootph-pre-ram;
+       bootph-all;
        /* Force to use SDCD card detect pin */
        pinctrl-single,pins = <
                AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
@@ -164,11 +164,11 @@
 };
 
 &tps65219 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &sdhci1 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 #ifdef CONFIG_TARGET_AM625_A53_EVM

diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
index c1685bc..b78d34b 100644 (file)
--- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
@@ -17,113 +17,152 @@
        };
 
        memory@80000000 {
-               bootph-pre-ram;
+               bootph-all;
        };
 };
 
+&main_conf {
+       bootph-all;
+};
+
 &cbass_main {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_timer0 {
        clock-frequency = <25000000>;
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &dmss {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &secure_proxy_main {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &dmsc {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &k3_pds {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &k3_clks {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &k3_reset {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &wkup_conf {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &chipid {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_pmx0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_uart0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_uart0_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &cbass_mcu {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &cbass_wakeup {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &mcu_pmx0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &sdhci1 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_mmc1_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &fss {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &ospi0_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &ospi0 {
-       bootph-pre-ram;
+       bootph-all;
 
        flash@0 {
-               bootph-pre-ram;
+               bootph-all;
 
                partitions {
-                       bootph-pre-ram;
+                       bootph-all;
 
                        partition@3fc0000 {
-                               bootph-pre-ram;
+                               bootph-all;
                        };
                };
        };
 };
 
+&inta_main_dmss {
+       bootph-all;
+};
+
+&main_pktdma {
+       bootph-all;
+};
+
+&cpsw3g_mdio {
+       bootph-all;
+};
+
+&cpsw3g_phy0 {
+       bootph-all;
+};
+
+&cpsw3g_phy1 {
+       bootph-all;
+};
+
+&main_rgmii1_pins_default {
+       bootph-all;
+};
+
+&main_rgmii2_pins_default {
+       bootph-all;
+};
+
+&phy_gmii_sel {
+       bootph-all;
+};
+
 &cpsw3g {
-       bootph-pre-ram;
+       bootph-all;
+       ethernet-ports {
+               bootph-all;
+       };
 };
 
 &cpsw_port1 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &cpsw_port2 {

diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
index c85f57d..953bbe9 100644 (file)
--- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
@@ -11,109 +11,149 @@
        };
 
        memory@80000000 {
-               bootph-pre-ram;
+               bootph-all;
        };
 };
 
-&vtt_supply {
-       bootph-pre-ram;
-};
-
 &cbass_main {
-       bootph-pre-ram;
-};
-
-&cbass_mcu {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_timer0 {
-       bootph-pre-ram;
+       bootph-all;
        clock-frequency = <200000000>;
 };
 
 &main_conf {
-       bootph-pre-ram;
+       bootph-all;
        chipid@14 {
-               bootph-pre-ram;
+               bootph-all;
        };
 };
 
 &main_pmx0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_i2c0_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_i2c0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_uart0_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_uart0 {
-       bootph-pre-ram;
+       bootph-all;
+};
+
+&main_usb0_pins_default {
+       bootph-all;
 };
 
 &usb0 {
        dr_mode="peripheral";
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &usbss0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_mmc1_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_usb0_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &dmss {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &secure_proxy_main {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &dmsc {
-       bootph-pre-ram;
+       bootph-all;
        k3_sysreset: sysreset-controller {
                compatible = "ti,sci-sysreset";
-               bootph-pre-ram;
+               bootph-all;
        };
 };
 
 &k3_pds {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &k3_clks {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &k3_reset {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &sdhci0 {
-       bootph-pre-ram;
+       bootph-all;
+};
+
+&main_mmc1_pins_default {
+       bootph-all;
 };
 
 &sdhci1 {
-       bootph-pre-ram;
+       bootph-all;
+};
+
+&inta_main_dmss {
+       bootph-all;
+};
+
+&main_pktdma {
+       bootph-all;
+};
+
+&mdio1_pins_default {
+       bootph-all;
+};
+
+&cpsw3g_mdio {
+       bootph-all;
+};
+
+&cpsw3g_phy0 {
+       bootph-all;
+};
+
+&rgmii1_pins_default {
+       bootph-all;
+};
+
+&rgmii2_pins_default {
+       bootph-all;
 };
 
 &cpsw3g {
-       bootph-pre-ram;
+       bootph-all;
+
+       ethernet-ports {
+               bootph-all;
+       };
+};
+
+&phy_gmii_sel {
+       bootph-all;
+};
+
+&cpsw_port1 {
+       bootph-all;
 };
 
 &cpsw_port2 {

diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts
index 73461f8..64b3c3a 100644 (file)
--- a/arch/arm/dts/k3-am642-r5-evm.dts
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@@ -40,6 +40,10 @@
        };
 };
 
+&vtt_supply {
+       bootph-pre-ram;
+};
+
 &cbass_main {
        sysctrler: sysctrler {
                compatible = "ti,am654-system-controller";
@@ -53,6 +57,10 @@
        bootph-pre-ram;
 };
 
+&cbass_mcu {
+       bootph-pre-ram;
+};
+
 &mcu_esm {
        bootph-pre-ram;
 };
@@ -66,6 +74,14 @@
        ti,secure-host;
 };
 
+&vtt_supply {
+       bootph-pre-ram;
+};
+
+&memorycontroller {
+       vtt-supply = <&vtt_supply>;
+};
+
 &sdhci0 {
        clocks = <&clk_200mhz>;
        clock-names = "clk_xin";

diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts
index def4622..daa483a 100644 (file)
--- a/arch/arm/dts/k3-am642-r5-sk.dts
+++ b/arch/arm/dts/k3-am642-r5-sk.dts
@@ -53,6 +53,10 @@
        bootph-pre-ram;
 };
 
+&cbass_mcu {
+       bootph-pre-ram;
+};
+
 &mcu_esm {
        bootph-pre-ram;
 };

diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
index c277ef8..40a53df 100644 (file)
--- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
@@ -11,129 +11,161 @@
        };
 
        memory@80000000 {
-               bootph-pre-ram;
+               bootph-all;
        };
 };
 
 &cbass_main{
-       bootph-pre-ram;
-};
-
-&cbass_mcu {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_timer0 {
-       bootph-pre-ram;
+       bootph-all;
        clock-frequency = <200000000>;
 };
 
 &main_conf {
-       bootph-pre-ram;
+       bootph-all;
        chipid@14 {
-               bootph-pre-ram;
+               bootph-all;
        };
 };
 
 &main_pmx0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_i2c0_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_i2c0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_uart0_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_uart0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &dmss {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &secure_proxy_main {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &dmsc {
-       bootph-pre-ram;
+       bootph-all;
        k3_sysreset: sysreset-controller {
                compatible = "ti,sci-sysreset";
-               bootph-pre-ram;
+               bootph-all;
        };
 };
 
 &k3_pds {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &k3_clks {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &k3_reset {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &sdhci0 {
        status = "disabled";
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &sdhci1 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_mmc1_pins_default {
-       bootph-pre-ram;
+       bootph-all;
+};
+
+&inta_main_dmss {
+       bootph-all;
+};
+
+&main_pktdma {
+       bootph-all;
+};
+
+&mdio1_pins_default {
+       bootph-all;
+};
+
+&cpsw3g_mdio {
+       bootph-all;
+};
+
+&cpsw3g_phy0 {
+       bootph-all;
+};
+
+&cpsw3g_phy1 {
+       bootph-all;
+};
+
+&rgmii1_pins_default {
+       bootph-all;
+};
+
+&rgmii2_pins_default {
+       bootph-all;
 };
 
 &cpsw3g {
-       bootph-pre-ram;
+       bootph-all;
 
        ethernet-ports {
-               bootph-pre-ram;
+               bootph-all;
        };
 };
 
+&phy_gmii_sel {
+       bootph-all;
+};
+
 &cpsw_port2 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_bcdma {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_pktdma {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &rgmii1_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &rgmii2_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &mdio1_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &cpsw3g_phy1 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &main_usb0_pins_default {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &serdes_ln_ctrl {
@@ -141,25 +173,25 @@
 };
 
 &usbss0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &usb0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &serdes_wiz0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &serdes0_usb_link {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &serdes0 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &serdes_refclk {
-       bootph-pre-ram;
+       bootph-all;
 };

diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 540c847..c638af6 100644 (file)
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -3,83 +3,42 @@
  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  */
 
-#include <dt-bindings/net/ti-dp83867.h>
 #include "k3-j721e-binman.dtsi"
 
-/ {
-       chosen {
-               stdout-path = "serial2:115200n8";
-               tick-timer = &timer1;
-       };
-
-       aliases {
-               ethernet0 = &cpsw_port1;
-               spi0 = &ospi0;
-               spi1 = &ospi1;
-               remoteproc0 = &mcu_r5fss0_core0;
-               remoteproc1 = &mcu_r5fss0_core1;
-               remoteproc2 = &main_r5fss0_core0;
-               remoteproc3 = &main_r5fss0_core1;
-               remoteproc4 = &main_r5fss1_core0;
-               remoteproc5 = &main_r5fss1_core1;
-               remoteproc6 = &c66_0;
-               remoteproc7 = &c66_1;
-               remoteproc8 = &c71_0;
-               i2c0 = &wkup_i2c0;
-               i2c1 = &mcu_i2c0;
-               i2c2 = &mcu_i2c1;
-               i2c3 = &main_i2c0;
-       };
+&cbass_main {
+       bootph-pre-ram;
 };
 
-&cbass_main{
+&main_navss {
        bootph-pre-ram;
-
-       main_navss: bus@30000000 {
-               bootph-pre-ram;
-       };
 };
 
 &cbass_mcu_wakeup {
        bootph-pre-ram;
 
-       timer1: timer@40400000 {
-               compatible = "ti,omap5430-timer";
-               reg = <0x0 0x40400000 0x0 0x80>;
-               ti,timer-alwon;
-               clock-frequency = <250000000>;
+       chipid@43000014 {
                bootph-pre-ram;
        };
+};
 
-       mcu_navss: bus@28380000 {
-               bootph-pre-ram;
+&mcu_navss {
+       bootph-pre-ram;
+};
 
-               ringacc@2b800000 {
-                       reg =   <0x0 0x2b800000 0x0 0x400000>,
-                               <0x0 0x2b000000 0x0 0x400000>,
-                               <0x0 0x28590000 0x0 0x100>,
-                               <0x0 0x2a500000 0x0 0x40000>,
-                               <0x0 0x28440000 0x0 0x40000>;
-                       reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
-                       bootph-pre-ram;
-               };
-
-               dma-controller@285c0000 {
-                       reg =   <0x0 0x285c0000 0x0 0x100>,
-                               <0x0 0x284c0000 0x0 0x4000>,
-                               <0x0 0x2a800000 0x0 0x40000>,
-                               <0x0 0x284a0000 0x0 0x4000>,
-                               <0x0 0x2aa00000 0x0 0x40000>,
-                               <0x0 0x28400000 0x0 0x2000>;
-                       reg-names = "gcfg", "rchan", "rchanrt", "tchan",
-                                           "tchanrt", "rflow";
-                       bootph-pre-ram;
-               };
-       };
+&mcu_ringacc {
+       bootph-pre-ram;
+};
 
-       chipid@43000014 {
-               bootph-pre-ram;
-       };
+&mcu_udmap {
+       reg =   <0x0 0x285c0000 0x0 0x100>,
+               <0x0 0x284c0000 0x0 0x4000>,
+               <0x0 0x2a800000 0x0 0x40000>,
+               <0x0 0x284a0000 0x0 0x4000>,
+               <0x0 0x2aa00000 0x0 0x40000>,
+               <0x0 0x28400000 0x0 0x2000>;
+       reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+                   "tchanrt", "rflow";
+       bootph-pre-ram;
 };
 
 &secure_proxy_main {
@@ -130,9 +89,8 @@
        bootph-pre-ram;
 };
 
-&wiz3_pll1_refclk {
-       assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
-       assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
+&main_uart0_pins_default {
+       bootph-pre-ram;
 };
 
 &main_usbss0_pins_default {
@@ -148,19 +106,6 @@
        bootph-pre-ram;
 };
 
-&mcu_cpsw {
-       reg = <0x0 0x46000000 0x0 0x200000>,
-             <0x0 0x40f00200 0x0 0x2>;
-       reg-names = "cpsw_nuss", "mac_efuse";
-       /delete-property/ ranges;
-
-       cpsw-phy-sel@40f04040 {
-               compatible = "ti,am654-cpsw-phy-sel";
-               reg= <0x0 0x40f04040 0x0 0x4>;
-               reg-names = "gmii-sel";
-       };
-};
-
 &main_mmc1_pins_default {
        bootph-pre-ram;
 };
@@ -169,39 +114,37 @@
        bootph-pre-ram;
 };
 
-&wkup_i2c0 {
+&wkup_uart0 {
        bootph-pre-ram;
+       status = "okay";
 };
 
-&main_i2c0 {
+&wkup_i2c0 {
        bootph-pre-ram;
+       status = "okay";
 };
 
-&main_i2c0_pins_default {
+&main_i2c0 {
        bootph-pre-ram;
 };
 
-&exp2 {
+&main_i2c0_pins_default {
        bootph-pre-ram;
 };
 
-&mcu_fss0_ospi0_pins_default {
+&main_esm {
        bootph-pre-ram;
 };
 
-&fss {
+&exp2 {
        bootph-pre-ram;
 };
 
-&hbmc {
+&mcu_fss0_ospi0_pins_default {
        bootph-pre-ram;
-
-       flash@0,0 {
-               bootph-pre-ram;
-       };
 };
 
-&hbmc_mux {
+&fss {
        bootph-pre-ram;
 };
 
@@ -236,39 +179,3 @@
 &mcu_fss0_ospi1_pins_default {
        bootph-pre-ram;
 };
-
-&main_r5fss0 {
-       ti,cluster-mode = <0>;
-};
-
-&main_r5fss1 {
-       ti,cluster-mode = <0>;
-};
-
-&wiz3_pll1_refclk {
-       assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
-       assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
-};
-
-&serdes_ln_ctrl {
-       u-boot,mux-autoprobe;
-};
-
-&usb_serdes_mux {
-       u-boot,mux-autoprobe;
-};
-
-&serdes0 {
-       /delete-property/ assigned-clocks;
-       /delete-property/ assigned-clock-parents;
-};
-
-&serdes0_pcie_link {
-       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
-       assigned-clock-parents = <&wiz0_pll1_refclk>;
-};
-
-&serdes0_qsgmii_link {
-       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
-       assigned-clock-parents = <&wiz0_pll1_refclk>;
-};

diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts
index 1b60054..fe5207a 100644 (file)
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -1,6 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Product Link: https://www.ti.com/tool/J721EXCPXEVM
  */
 
 /dts-v1/;
@@ -12,24 +14,38 @@
 #include <dt-bindings/phy/phy-cadence.h>
 
 / {
+       compatible = "ti,j721e-evm", "ti,j721e";
+       model = "Texas Instruments J721e EVM";
+
+       aliases {
+               serial0 = &wkup_uart0;
+               serial1 = &mcu_uart0;
+               serial2 = &main_uart0;
+               serial3 = &main_uart1;
+               serial4 = &main_uart2;
+               serial6 = &main_uart4;
+               ethernet0 = &cpsw_port1;
+               mmc0 = &main_sdhci0;
+               mmc1 = &main_sdhci1;
+       };
+
        chosen {
                stdout-path = "serial2:115200n8";
-               bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
        };
 
        gpio_keys: gpio-keys {
                compatible = "gpio-keys";
                autorepeat;
                pinctrl-names = "default";
-               pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
+               pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>;
 
-               sw10: sw10 {
+               sw10: switch-10 {
                        label = "GPIO Key USER1";
                        linux,code = <BTN_0>;
                        gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
                };
 
-               sw11: sw11 {
+               sw11: switch-11 {
                        label = "GPIO Key USER2";
                        linux,code = <BTN_1>;
                        gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
@@ -93,7 +109,7 @@
                         <3300000 0x1>;
        };
 
-       sound0: sound@0 {
+       sound0: sound-0 {
                compatible = "ti,j721e-cpb-audio";
                model = "j721e-cpb";
 
@@ -109,16 +125,104 @@
                              "cpb-codec-scki",
                              "cpb-codec-scki-48000", "cpb-codec-scki-44100";
        };
+
+       transceiver1: can-phy0 {
+               compatible = "ti,tcan1043";
+               #phy-cells = <0>;
+               max-bitrate = <5000000>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
+               standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>;
+               enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
+       };
+
+       transceiver2: can-phy1 {
+               compatible = "ti,tcan1042";
+               #phy-cells = <0>;
+               max-bitrate = <5000000>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
+               standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
+       };
+
+       transceiver3: can-phy2 {
+               compatible = "ti,tcan1043";
+               #phy-cells = <0>;
+               max-bitrate = <5000000>;
+               standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
+               enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
+       };
+
+       transceiver4: can-phy3 {
+               compatible = "ti,tcan1042";
+               #phy-cells = <0>;
+               max-bitrate = <5000000>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&main_mcan2_gpio_pins_default>;
+               standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>;
+       };
+
+       dp_pwr_3v3: regulator-dp-pwr {
+               compatible = "regulator-fixed";
+               regulator-name = "dp-pwr";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */
+               enable-active-high;
+       };
+
+       dp0: connector {
+               compatible = "dp-connector";
+               label = "DP0";
+               type = "full-size";
+               dp-pwr-supply = <&dp_pwr_3v3>;
+
+               port {
+                       dp_connector_in: endpoint {
+                               remote-endpoint = <&dp0_out>;
+                       };
+               };
+       };
 };
 
 &main_pmx0 {
-       sw10_button_pins_default: sw10-button-pins-default {
+       main_uart0_pins_default: main-uart0-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */
+                       J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
+                       J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
+                       J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
+               >;
+       };
+
+       main_uart1_pins_default: main-uart1-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */
+                       J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */
+               >;
+       };
+
+       main_uart2_pins_default: main-uart2-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */
+                       J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */
+               >;
+       };
+
+       main_uart4_pins_default: main-uart4-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */
+                       J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */
+               >;
+       };
+
+       sw10_button_pins_default: sw10-button-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
                >;
        };
 
-       main_mmc1_pins_default: main-mmc1-pins-default {
+       main_mmc1_pins_default: main-mmc1-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
                        J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
@@ -132,60 +236,66 @@
                >;
        };
 
-       vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
+       vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
                >;
        };
 
-       main_usbss0_pins_default: main-usbss0-pins-default {
+       main_usbss0_pins_default: main-usbss0-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
                        J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
                >;
        };
 
-       main_usbss1_pins_default: main-usbss1-pins-default {
+       main_usbss1_pins_default: main-usbss1-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
                >;
        };
 
-       main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
+       dp0_pins_default: dp0-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
+               >;
+       };
+
+       main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
                >;
        };
 
-       main_i2c0_pins_default: main-i2c0-pins-default {
+       main_i2c0_pins_default: main-i2c0-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
                        J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
                >;
        };
 
-       main_i2c1_pins_default: main-i2c1-pins-default {
+       main_i2c1_pins_default: main-i2c1-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
                        J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
                >;
        };
 
-       main_i2c3_pins_default: main-i2c3-pins-default {
+       main_i2c3_pins_default: main-i2c3-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
                        J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
                >;
        };
 
-       main_i2c6_pins_default: main-i2c6-pins-default {
+       main_i2c6_pins_default: main-i2c6-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
                        J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
                >;
        };
 
-       mcasp10_pins_default: mcasp10-pins-default {
+       mcasp10_pins_default: mcasp10-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
                        J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
@@ -199,27 +309,57 @@
                >;
        };
 
-       audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default {
+       audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
                >;
        };
+
+       main_mcan0_pins_default: main-mcan0-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
+                       J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
+               >;
+       };
+
+       main_mcan2_pins_default: main-mcan2-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */
+                       J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */
+               >;
+       };
+
+       main_mcan2_gpio_pins_default: main-mcan2-gpio-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
+               >;
+       };
 };
 
 &wkup_pmx0 {
-       sw11_button_pins_default: sw11-button-pins-default {
+       wkup_uart0_pins_default: wkup-uart0-default-pins {
                pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
+                       J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
+                       J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
                >;
        };
 
-       wkup_gpio_pins_default: wkup-gpio-pins-default {
+       mcu_uart0_pins_default: mcu-uart0-default-pins {
                pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
+                       J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */
+                       J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
+                       J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
+                       J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
+               >;
+       };
+
+       sw11_button_pins_default: sw11-button-default-pins {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
                >;
        };
 
-       mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
+       mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
                        J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
@@ -232,7 +372,7 @@
                >;
        };
 
-       mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+       mcu_cpsw_pins_default: mcu-cpsw-default-pins {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
                        J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
@@ -249,83 +389,103 @@
                >;
        };
 
-       mcu_mdio_pins_default: mcu-mdio1-pins-default {
+       mcu_mdio_pins_default: mcu-mdio1-default-pins {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
                        J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
                >;
        };
-};
 
-&wkup_uart0 {
-       /* Wakeup UART is used by System firmware */
-       status = "reserved";
-};
-
-&main_uart0 {
-       power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
-};
+       mcu_mcan0_pins_default: mcu-mcan0-default-pins {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
+                       J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
+               >;
+       };
 
-&main_uart3 {
-       /* UART not brought out */
-       status = "disabled";
-};
+       mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */
+                       J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */
+               >;
+       };
 
-&main_uart5 {
-       /* UART not brought out */
-       status = "disabled";
-};
+       mcu_mcan1_pins_default: mcu-mcan1-default-pins {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */
+                       J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */
+               >;
+       };
 
-&main_uart6 {
-       /* UART not brought out */
-       status = "disabled";
-};
+       mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
+               >;
+       };
 
-&main_uart7 {
-       /* UART not brought out */
-       status = "disabled";
+       wkup_gpio_pins_default: wkup-gpio-default-pins {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
+               >;
+       };
 };
 
-&main_uart8 {
-       /* UART not brought out */
-       status = "disabled";
+&wkup_uart0 {
+       /* Wakeup UART is used by System firmware */
+       status = "reserved";
+       pinctrl-names = "default";
+       pinctrl-0 = <&wkup_uart0_pins_default>;
 };
 
-&main_uart9 {
-       /* UART not brought out */
-       status = "disabled";
+&mcu_uart0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcu_uart0_pins_default>;
 };
 
-&main_gpio2 {
-       status = "disabled";
+&main_uart0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_uart0_pins_default>;
+       /* Shared with ATF on this platform */
+       power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
 };
 
-&main_gpio3 {
-       status = "disabled";
+&main_uart1 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_uart1_pins_default>;
 };
 
-&main_gpio4 {
-       status = "disabled";
+&main_uart2 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_uart2_pins_default>;
 };
 
-&main_gpio5 {
-       status = "disabled";
+&main_uart4 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_uart4_pins_default>;
 };
 
-&main_gpio6 {
-       status = "disabled";
+&wkup_gpio0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&wkup_gpio_pins_default>;
 };
 
-&main_gpio7 {
-       status = "disabled";
+&main_gpio0 {
+       status = "okay";
 };
 
-&wkup_gpio1 {
-       status = "disabled";
+&main_gpio1 {
+       status = "okay";
 };
 
 &main_sdhci0 {
        /* eMMC */
+       status = "okay";
        non-removable;
        ti,driver-strength-ohm = <50>;
        disable-wp;
@@ -333,6 +493,7 @@
 
 &main_sdhci1 {
        /* SD/MMC */
+       status = "okay";
        vmmc-supply = <&vdd_mmc1>;
        vqmmc-supply = <&vdd_sd_dv_alt>;
        pinctrl-names = "default";
@@ -341,17 +502,12 @@
        disable-wp;
 };
 
-&main_sdhci2 {
-       /* Unused */
-       status = "disabled";
-};
-
 &usb_serdes_mux {
        idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
 };
 
 &serdes_ln_ctrl {
-       idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
+       idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
                      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
                      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
                      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
@@ -387,11 +543,6 @@
        phy-names = "cdns3,usb3-phy";
 };
 
-&wkup_gpio0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&wkup_gpio_pins_default>;
-};
-
 &usbss1 {
        pinctrl-names = "default";
        pinctrl-0 = <&main_usbss1_pins_default>;
@@ -407,7 +558,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
 
-       flash@0{
+       flash@0 {
                compatible = "jedec,spi-nor";
                reg = <0x0>;
                spi-tx-bus-width = <1>;
@@ -418,24 +569,71 @@
                cdns,tchsh-ns = <60>;
                cdns,tslch-ns = <60>;
                cdns,read-delay = <2>;
-               #address-cells = <1>;
-               #size-cells = <1>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "qspi.tiboot3";
+                               reg = <0x0 0x80000>;
+                       };
+
+                       partition@80000 {
+                               label = "qspi.tispl";
+                               reg = <0x80000 0x200000>;
+                       };
+
+                       partition@280000 {
+                               label = "qspi.u-boot";
+                               reg = <0x280000 0x400000>;
+                       };
+
+                       partition@680000 {
+                               label = "qspi.env";
+                               reg = <0x680000 0x20000>;
+                       };
+
+                       partition@6a0000 {
+                               label = "qspi.env.backup";
+                               reg = <0x6a0000 0x20000>;
+                       };
+
+                       partition@6c0000 {
+                               label = "qspi.sysfw";
+                               reg = <0x6c0000 0x100000>;
+                       };
+
+                       partition@800000 {
+                               label = "qspi.rootfs";
+                               reg = <0x800000 0x37c0000>;
+                       };
+
+                       partition@3fe0000 {
+                               label = "qspi.phypattern";
+                               reg = <0x3fe0000 0x20000>;
+                       };
+               };
        };
 };
 
 &tscadc0 {
+       status = "okay";
        adc {
                ti,adc-channels = <0 1 2 3 4 5 6 7>;
        };
 };
 
 &tscadc1 {
+       status = "okay";
        adc {
                ti,adc-channels = <0 1 2 3 4 5 6 7>;
        };
 };
 
 &main_i2c0 {
+       status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&main_i2c0_pins_default>;
        clock-frequency = <400000>;
@@ -472,6 +670,7 @@
 };
 
 &main_i2c1 {
+       status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&main_i2c1_pins_default>;
        clock-frequency = <400000>;
@@ -497,6 +696,7 @@
 };
 
 &main_i2c3 {
+       status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&main_i2c3_pins_default>;
        clock-frequency = <400000>;
@@ -535,6 +735,7 @@
 };
 
 &main_i2c6 {
+       status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&main_i2c6_pins_default>;
        clock-frequency = <400000>;
@@ -549,7 +750,7 @@
 
 &mcu_cpsw {
        pinctrl-names = "default";
-       pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+       pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
 };
 
 &davinci_mdio {
@@ -585,47 +786,35 @@
                                 <&k3_clks 152 18>;     /* PLL23_HSDIV0 */
 };
 
-&mcasp0 {
-       status = "disabled";
-};
-
-&mcasp1 {
-       status = "disabled";
-};
-
-&mcasp2 {
-       status = "disabled";
-};
-
-&mcasp3 {
-       status = "disabled";
-};
-
-&mcasp4 {
-       status = "disabled";
-};
-
-&mcasp5 {
-       status = "disabled";
+&dss_ports {
+       port {
+               dpi0_out: endpoint {
+                       remote-endpoint = <&dp0_in>;
+               };
+       };
 };
 
-&mcasp6 {
-       status = "disabled";
-};
+&dp0_ports {
+       #address-cells = <1>;
+       #size-cells = <0>;
 
-&mcasp7 {
-       status = "disabled";
-};
-
-&mcasp8 {
-       status = "disabled";
-};
+       port@0 {
+               reg = <0>;
+               dp0_in: endpoint {
+                       remote-endpoint = <&dpi0_out>;
+               };
+       };
 
-&mcasp9 {
-       status = "disabled";
+       port@4 {
+               reg = <4>;
+               dp0_out: endpoint {
+                       remote-endpoint = <&dp_connector_in>;
+               };
+       };
 };
 
 &mcasp10 {
+       status = "okay";
        #sound-dai-cells = <0>;
 
        pinctrl-names = "default";
@@ -643,10 +832,6 @@
        rx-num-evt = <0>;
 };
 
-&mcasp11 {
-       status = "disabled";
-};
-
 &cmn_refclk1 {
        clock-frequency = <100000000>;
 };
@@ -682,8 +867,8 @@
 };
 
 &serdes0 {
-       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
-       assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
+       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
+       assigned-clock-parents = <&wiz0_pll1_refclk>;
 
        serdes0_pcie_link: phy@0 {
                reg = <0>;
@@ -692,14 +877,6 @@
                cdns,phy-type = <PHY_TYPE_PCIE>;
                resets = <&serdes_wiz0 1>;
        };
-
-       serdes0_qsgmii_link: phy@1 {
-               reg = <1>;
-               cdns,num-lanes = <1>;
-               #phy-cells = <0>;
-               cdns,phy-type = <PHY_TYPE_QSGMII>;
-               resets = <&serdes_wiz0 2>;
-       };
 };
 
 &serdes1 {
@@ -728,7 +905,26 @@
        };
 };
 
+&serdes4 {
+       torrent_phy_dp: phy@0 {
+               reg = <0>;
+               resets = <&serdes_wiz4 1>;
+               cdns,phy-type = <PHY_TYPE_DP>;
+               cdns,num-lanes = <4>;
+               cdns,max-bit-rate = <5400>;
+               #phy-cells = <0>;
+       };
+};
+
+&mhdp {
+       phys = <&torrent_phy_dp>;
+       phy-names = "dpphy";
+       pinctrl-names = "default";
+       pinctrl-0 = <&dp0_pins_default>;
+};
+
 &pcie0_rc {
+       status = "okay";
        reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
        phys = <&serdes0_pcie_link>;
        phy-names = "pcie-phy";
@@ -736,6 +932,7 @@
 };
 
 &pcie1_rc {
+       status = "okay";
        reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
        phys = <&serdes1_pcie_link>;
        phy-names = "pcie-phy";
@@ -743,49 +940,37 @@
 };
 
 &pcie2_rc {
+       status = "okay";
        reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
        phys = <&serdes2_pcie_link>;
        phy-names = "pcie-phy";
        num-lanes = <2>;
 };
 
-&pcie0_ep {
-       phys = <&serdes0_pcie_link>;
-       phy-names = "pcie-phy";
-       num-lanes = <1>;
-       status = "disabled";
-};
-
-&pcie1_ep {
-       phys = <&serdes1_pcie_link>;
-       phy-names = "pcie-phy";
-       num-lanes = <2>;
-       status = "disabled";
-};
-
-&pcie2_ep {
-       phys = <&serdes2_pcie_link>;
-       phy-names = "pcie-phy";
-       num-lanes = <2>;
-       status = "disabled";
-};
-
-&pcie3_rc {
-       status = "disabled";
-};
-
-&pcie3_ep {
-       status = "disabled";
+&mcu_mcan0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcu_mcan0_pins_default>;
+       phys = <&transceiver1>;
 };
 
-&dss {
-       status = "disabled";
+&mcu_mcan1 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcu_mcan1_pins_default>;
+       phys = <&transceiver2>;
 };
 
-&icssg0_mdio {
-       status = "disabled";
+&main_mcan0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_mcan0_pins_default>;
+       phys = <&transceiver3>;
 };
 
-&icssg1_mdio {
-       status = "disabled";
+&main_mcan2 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_mcan2_pins_default>;
+       phys = <&transceiver4>;
 };

diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index d2edf5d..f6c7e16 100644 (file)
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -5,7 +5,9 @@
  * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
  */
 #include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-ti.h>
 #include <dt-bindings/mux/mux.h>
+
 #include "k3-serdes.h"
 
 / {
@@ -42,7 +44,7 @@
                #size-cells = <1>;
                ranges = <0x0 0x0 0x00100000 0x1c000>;
 
-               serdes_ln_ctrl: mux@4080 {
+               serdes_ln_ctrl: mux-controller@4080 {
                        compatible = "mmio-mux";
                        reg = <0x00004080 0x50>;
                        #mux-control-cells = <1>;
@@ -60,12 +62,85 @@
                                      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
                };
 
+               cpsw0_phy_gmii_sel: phy@4044 {
+                       compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
+                       ti,qsgmii-main-ports = <2>, <2>;
+                       reg = <0x4044 0x20>;
+                       #phy-cells = <1>;
+               };
+
                usb_serdes_mux: mux-controller@4000 {
                        compatible = "mmio-mux";
                        #mux-control-cells = <1>;
                        mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
                                        <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
-           };
+               };
+
+               ehrpwm_tbclk: clock-controller@4140 {
+                       compatible = "ti,am654-ehrpwm-tbclk";
+                       reg = <0x4140 0x18>;
+                       #clock-cells = <1>;
+               };
+       };
+
+       main_ehrpwm0: pwm@3000000 {
+               compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x00 0x3000000 0x00 0x100>;
+               power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
+               clock-names = "tbclk", "fck";
+               status = "disabled";
+       };
+
+       main_ehrpwm1: pwm@3010000 {
+               compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x00 0x3010000 0x00 0x100>;
+               power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
+               clock-names = "tbclk", "fck";
+               status = "disabled";
+       };
+
+       main_ehrpwm2: pwm@3020000 {
+               compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x00 0x3020000 0x00 0x100>;
+               power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
+               clock-names = "tbclk", "fck";
+               status = "disabled";
+       };
+
+       main_ehrpwm3: pwm@3030000 {
+               compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x00 0x3030000 0x00 0x100>;
+               power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
+               clock-names = "tbclk", "fck";
+               status = "disabled";
+       };
+
+       main_ehrpwm4: pwm@3040000 {
+               compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x00 0x3040000 0x00 0x100>;
+               power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
+               clock-names = "tbclk", "fck";
+               status = "disabled";
+       };
+
+       main_ehrpwm5: pwm@3050000 {
+               compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x00 0x3050000 0x00 0x100>;
+               power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
+               clock-names = "tbclk", "fck";
+               status = "disabled";
        };
 
        gic500: interrupt-controller@1800000 {
@@ -76,7 +151,10 @@
                #interrupt-cells = <3>;
                interrupt-controller;
                reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
-                     <0x00 0x01900000 0x00 0x100000>;  /* GICR */
+                     <0x00 0x01900000 0x00 0x100000>,  /* GICR */
+                     <0x00 0x6f000000 0x00 0x2000>,    /* GICC */
+                     <0x00 0x6f010000 0x00 0x1000>,    /* GICH */
+                     <0x00 0x6f020000 0x00 0x2000>;    /* GICV */
 
                /* vcpumntirq: virtual CPU interface maintenance interrupt */
                interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
@@ -172,6 +250,7 @@
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <16>;
                        interrupt-parent = <&main_navss_intr>;
+                       status = "disabled";
                };
 
                mailbox0_cluster1: mailbox@31f81000 {
@@ -181,6 +260,7 @@
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <16>;
                        interrupt-parent = <&main_navss_intr>;
+                       status = "disabled";
                };
 
                mailbox0_cluster2: mailbox@31f82000 {
@@ -190,6 +270,7 @@
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <16>;
                        interrupt-parent = <&main_navss_intr>;
+                       status = "disabled";
                };
 
                mailbox0_cluster3: mailbox@31f83000 {
@@ -199,6 +280,7 @@
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <16>;
                        interrupt-parent = <&main_navss_intr>;
+                       status = "disabled";
                };
 
                mailbox0_cluster4: mailbox@31f84000 {
@@ -208,6 +290,7 @@
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <16>;
                        interrupt-parent = <&main_navss_intr>;
+                       status = "disabled";
                };
 
                mailbox0_cluster5: mailbox@31f85000 {
@@ -217,6 +300,7 @@
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <16>;
                        interrupt-parent = <&main_navss_intr>;
+                       status = "disabled";
                };
 
                mailbox0_cluster6: mailbox@31f86000 {
@@ -226,6 +310,7 @@
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <16>;
                        interrupt-parent = <&main_navss_intr>;
+                       status = "disabled";
                };
 
                mailbox0_cluster7: mailbox@31f87000 {
@@ -235,6 +320,7 @@
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <16>;
                        interrupt-parent = <&main_navss_intr>;
+                       status = "disabled";
                };
 
                mailbox0_cluster8: mailbox@31f88000 {
@@ -244,6 +330,7 @@
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <16>;
                        interrupt-parent = <&main_navss_intr>;
+                       status = "disabled";
                };
 
                mailbox0_cluster9: mailbox@31f89000 {
@@ -253,6 +340,7 @@
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <16>;
                        interrupt-parent = <&main_navss_intr>;
+                       status = "disabled";
                };
 
                mailbox0_cluster10: mailbox@31f8a000 {
@@ -262,6 +350,7 @@
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <16>;
                        interrupt-parent = <&main_navss_intr>;
+                       status = "disabled";
                };
 
                mailbox0_cluster11: mailbox@31f8b000 {
@@ -271,15 +360,17 @@
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <16>;
                        interrupt-parent = <&main_navss_intr>;
+                       status = "disabled";
                };
 
                main_ringacc: ringacc@3c000000 {
                        compatible = "ti,am654-navss-ringacc";
-                       reg =   <0x0 0x3c000000 0x0 0x400000>,
-                               <0x0 0x38000000 0x0 0x400000>,
-                               <0x0 0x31120000 0x0 0x100>,
-                               <0x0 0x33000000 0x0 0x40000>;
-                       reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+                       reg = <0x0 0x3c000000 0x0 0x400000>,
+                             <0x0 0x38000000 0x0 0x400000>,
+                             <0x0 0x31120000 0x0 0x100>,
+                             <0x0 0x33000000 0x0 0x40000>,
+                             <0x0 0x31080000 0x0 0x40000>;
+                       reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
                        ti,num-rings = <1024>;
                        ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
                        ti,sci = <&dmsc>;
@@ -289,9 +380,9 @@
 
                main_udmap: dma-controller@31150000 {
                        compatible = "ti,j721e-navss-main-udmap";
-                       reg =   <0x0 0x31150000 0x0 0x100>,
-                               <0x0 0x34000000 0x0 0x100000>,
-                               <0x0 0x35000000 0x0 0x100000>;
+                       reg = <0x0 0x31150000 0x0 0x100>,
+                             <0x0 0x34000000 0x0 0x100000>,
+                             <0x0 0x35000000 0x0 0x100000>;
                        reg-names = "gcfg", "rchanrt", "tchanrt";
                        msi-parent = <&main_udmass_inta>;
                        #dma-cells = <1>;
@@ -322,6 +413,115 @@
                };
        };
 
+       cpsw0: ethernet@c000000 {
+               compatible = "ti,j721e-cpswxg-nuss";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               reg = <0x0 0xc000000 0x0 0x200000>;
+               reg-names = "cpsw_nuss";
+               ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>;
+               clocks = <&k3_clks 19 89>;
+               clock-names = "fck";
+               power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
+
+               dmas = <&main_udmap 0xca00>,
+                      <&main_udmap 0xca01>,
+                      <&main_udmap 0xca02>,
+                      <&main_udmap 0xca03>,
+                      <&main_udmap 0xca04>,
+                      <&main_udmap 0xca05>,
+                      <&main_udmap 0xca06>,
+                      <&main_udmap 0xca07>,
+                      <&main_udmap 0x4a00>;
+               dma-names = "tx0", "tx1", "tx2", "tx3",
+                           "tx4", "tx5", "tx6", "tx7",
+                           "rx";
+
+               status = "disabled";
+
+               ethernet-ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cpsw0_port1: port@1 {
+                               reg = <1>;
+                               ti,mac-only;
+                               label = "port1";
+                               status = "disabled";
+                       };
+
+                       cpsw0_port2: port@2 {
+                               reg = <2>;
+                               ti,mac-only;
+                               label = "port2";
+                               status = "disabled";
+                       };
+
+                       cpsw0_port3: port@3 {
+                               reg = <3>;
+                               ti,mac-only;
+                               label = "port3";
+                               status = "disabled";
+                       };
+
+                       cpsw0_port4: port@4 {
+                               reg = <4>;
+                               ti,mac-only;
+                               label = "port4";
+                               status = "disabled";
+                       };
+
+                       cpsw0_port5: port@5 {
+                               reg = <5>;
+                               ti,mac-only;
+                               label = "port5";
+                               status = "disabled";
+                       };
+
+                       cpsw0_port6: port@6 {
+                               reg = <6>;
+                               ti,mac-only;
+                               label = "port6";
+                               status = "disabled";
+                       };
+
+                       cpsw0_port7: port@7 {
+                               reg = <7>;
+                               ti,mac-only;
+                               label = "port7";
+                               status = "disabled";
+                       };
+
+                       cpsw0_port8: port@8 {
+                               reg = <8>;
+                               ti,mac-only;
+                               label = "port8";
+                               status = "disabled";
+                       };
+               };
+
+               cpsw9g_mdio: mdio@f00 {
+                       compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+                       reg = <0x0 0xf00 0x0 0x100>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&k3_clks 19 89>;
+                       clock-names = "fck";
+                       bus_freq = <1000000>;
+                       status = "disabled";
+               };
+
+               cpts@3d000 {
+                       compatible = "ti,j721e-cpts";
+                       reg = <0x0 0x3d000 0x0 0x400>;
+                       clocks = <&k3_clks 19 16>;
+                       clock-names = "cpts";
+                       interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "cpts";
+                       ti,cpts-ext-ts-inputs = <4>;
+                       ti,cpts-periodic-outputs = <2>;
+               };
+       };
+
        main_crypto: crypto@4e00000 {
                compatible = "ti,j721e-sa2ul";
                reg = <0x0 0x4e00000 0x0 0x1200>;
@@ -333,13 +533,11 @@
                dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
                                <&main_udmap 0x4001>;
                dma-names = "tx", "rx1", "rx2";
-               dma-coherent;
 
                rng: rng@4e10000 {
                        compatible = "inside-secure,safexcel-eip76";
                        reg = <0x0 0x4e10000 0x0 0x7d>;
                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&k3_clks 264 1>;
                };
        };
 
@@ -352,6 +550,24 @@
                pinctrl-single,function-mask = <0xffffffff>;
        };
 
+       /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+       main_timerio_input: pinctrl@104200 {
+               compatible = "pinctrl-single";
+               reg = <0x00 0x104200 0x00 0x50>;
+               #pinctrl-cells = <1>;
+               pinctrl-single,register-width = <32>;
+               pinctrl-single,function-mask = <0x00000007>;
+       };
+
+       /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+       main_timerio_output: pinctrl@104280 {
+               compatible = "pinctrl-single";
+               reg = <0x00 0x104280 0x00 0x20>;
+               #pinctrl-cells = <1>;
+               pinctrl-single,register-width = <32>;
+               pinctrl-single,function-mask = <0x0000001f>;
+       };
+
        serdes_wiz0: wiz@5000000 {
                compatible = "ti,j721e-wiz-16g";
                #address-cells = <1>;
@@ -446,7 +662,7 @@
                        assigned-clock-parents = <&k3_clks 293 13>;
                };
 
-               wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
+               wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div {
                        clocks = <&wiz1_refclk_dig>;
                        #clock-cells = <0>;
                };
@@ -610,7 +826,7 @@
                clock-names = "fck";
                #address-cells = <3>;
                #size-cells = <2>;
-               bus-range = <0x0 0xf>;
+               bus-range = <0x0 0xff>;
                vendor-id = <0x104c>;
                device-id = <0xb00d>;
                msi-map = <0x0 &gic_its 0x0 0x10000>;
@@ -618,26 +834,7 @@
                ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
                         <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
                dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
-       };
-
-       pcie0_ep: pcie-ep@2900000 {
-               compatible = "ti,j721e-pcie-ep";
-               reg = <0x00 0x02900000 0x00 0x1000>,
-                     <0x00 0x02907000 0x00 0x400>,
-                     <0x00 0x0d000000 0x00 0x00800000>,
-                     <0x00 0x10000000 0x00 0x08000000>;
-               reg-names = "intd_cfg", "user_cfg", "reg", "mem";
-               interrupt-names = "link_state";
-               interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
-               ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
-               max-link-speed = <3>;
-               num-lanes = <2>;
-               power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 239 1>;
-               clock-names = "fck";
-               max-functions = /bits/ 8 <6>;
-               max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
-               dma-coherent;
+               status = "disabled";
        };
 
        pcie1_rc: pcie@2910000 {
@@ -658,7 +855,7 @@
                clock-names = "fck";
                #address-cells = <3>;
                #size-cells = <2>;
-               bus-range = <0x0 0xf>;
+               bus-range = <0x0 0xff>;
                vendor-id = <0x104c>;
                device-id = <0xb00d>;
                msi-map = <0x0 &gic_its 0x10000 0x10000>;
@@ -666,26 +863,7 @@
                ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
                         <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
                dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
-       };
-
-       pcie1_ep: pcie-ep@2910000 {
-               compatible = "ti,j721e-pcie-ep";
-               reg = <0x00 0x02910000 0x00 0x1000>,
-                     <0x00 0x02917000 0x00 0x400>,
-                     <0x00 0x0d800000 0x00 0x00800000>,
-                     <0x00 0x18000000 0x00 0x08000000>;
-               reg-names = "intd_cfg", "user_cfg", "reg", "mem";
-               interrupt-names = "link_state";
-               interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
-               ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
-               max-link-speed = <3>;
-               num-lanes = <2>;
-               power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 240 1>;
-               clock-names = "fck";
-               max-functions = /bits/ 8 <6>;
-               max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
-               dma-coherent;
+               status = "disabled";
        };
 
        pcie2_rc: pcie@2920000 {
@@ -706,7 +884,7 @@
                clock-names = "fck";
                #address-cells = <3>;
                #size-cells = <2>;
-               bus-range = <0x0 0xf>;
+               bus-range = <0x0 0xff>;
                vendor-id = <0x104c>;
                device-id = <0xb00d>;
                msi-map = <0x0 &gic_its 0x20000 0x10000>;
@@ -714,26 +892,7 @@
                ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
                         <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
                dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
-       };
-
-       pcie2_ep: pcie-ep@2920000 {
-               compatible = "ti,j721e-pcie-ep";
-               reg = <0x00 0x02920000 0x00 0x1000>,
-                     <0x00 0x02927000 0x00 0x400>,
-                     <0x00 0x0e000000 0x00 0x00800000>,
-                     <0x44 0x00000000 0x00 0x08000000>;
-               reg-names = "intd_cfg", "user_cfg", "reg", "mem";
-               interrupt-names = "link_state";
-               interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
-               ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
-               max-link-speed = <3>;
-               num-lanes = <2>;
-               power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 241 1>;
-               clock-names = "fck";
-               max-functions = /bits/ 8 <6>;
-               max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
-               dma-coherent;
+               status = "disabled";
        };
 
        pcie3_rc: pcie@2930000 {
@@ -754,7 +913,7 @@
                clock-names = "fck";
                #address-cells = <3>;
                #size-cells = <2>;
-               bus-range = <0x0 0xf>;
+               bus-range = <0x0 0xff>;
                vendor-id = <0x104c>;
                device-id = <0xb00d>;
                msi-map = <0x0 &gic_its 0x30000 0x10000>;
@@ -762,28 +921,288 @@
                ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
                         <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
                dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+               status = "disabled";
        };
 
-       pcie3_ep: pcie-ep@2930000 {
-               compatible = "ti,j721e-pcie-ep";
-               reg = <0x00 0x02930000 0x00 0x1000>,
-                     <0x00 0x02937000 0x00 0x400>,
-                     <0x00 0x0e800000 0x00 0x00800000>,
-                     <0x44 0x10000000 0x00 0x08000000>;
-               reg-names = "intd_cfg", "user_cfg", "reg", "mem";
-               interrupt-names = "link_state";
-               interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
-               ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
-               max-link-speed = <3>;
-               num-lanes = <2>;
-               power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 242 1>;
+       serdes_wiz4: wiz@5050000 {
+               compatible = "ti,am64-wiz-10g";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
+               clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+               assigned-clocks = <&k3_clks 297 9>;
+               assigned-clock-parents = <&k3_clks 297 10>;
+               assigned-clock-rates = <19200000>;
+               num-lanes = <4>;
+               #reset-cells = <1>;
+               #clock-cells = <1>;
+               ranges = <0x05050000 0x00 0x05050000 0x010000>,
+                       <0x0a030a00 0x00 0x0a030a00 0x40>;
+
+               serdes4: serdes@5050000 {
+                       /*
+                        * Note: we also map DPTX PHY registers as the Torrent
+                        * needs to manage those.
+                        */
+                       compatible = "ti,j721e-serdes-10g";
+                       reg = <0x05050000 0x010000>,
+                             <0x0a030a00 0x40>; /* DPTX PHY */
+                       reg-names = "torrent_phy", "dptx_phy";
+
+                       resets = <&serdes_wiz4 0>;
+                       reset-names = "torrent_reset";
+                       clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>;
+                       clock-names = "refclk";
+                       assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+                                         <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
+                                         <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
+                       assigned-clock-parents = <&k3_clks 297 9>,
+                                                <&k3_clks 297 9>,
+                                                <&k3_clks 297 9>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+       };
+
+       main_timer0: timer@2400000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x2400000 0x00 0x400>;
+               interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 49 1>;
                clock-names = "fck";
-               max-functions = /bits/ 8 <6>;
-               max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
-               dma-coherent;
-               #address-cells = <2>;
-               #size-cells = <2>;
+               assigned-clocks = <&k3_clks 49 1>;
+               assigned-clock-parents = <&k3_clks 49 2>;
+               power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer1: timer@2410000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x2410000 0x00 0x400>;
+               interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 50 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
+               assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>;
+               power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer2: timer@2420000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x2420000 0x00 0x400>;
+               interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 51 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 51 1>;
+               assigned-clock-parents = <&k3_clks 51 2>;
+               power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer3: timer@2430000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x2430000 0x00 0x400>;
+               interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 52 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
+               assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>;
+               power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer4: timer@2440000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x2440000 0x00 0x400>;
+               interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 53 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 53 1>;
+               assigned-clock-parents = <&k3_clks 53 2>;
+               power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer5: timer@2450000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x2450000 0x00 0x400>;
+               interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 54 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
+               assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>;
+               power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer6: timer@2460000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x2460000 0x00 0x400>;
+               interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 55 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 55 1>;
+               assigned-clock-parents = <&k3_clks 55 2>;
+               power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer7: timer@2470000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x2470000 0x00 0x400>;
+               interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 57 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
+               assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>;
+               power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer8: timer@2480000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x2480000 0x00 0x400>;
+               interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 58 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 58 1>;
+               assigned-clock-parents = <&k3_clks 58 2>;
+               power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer9: timer@2490000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x2490000 0x00 0x400>;
+               interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 59 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
+               assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>;
+               power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer10: timer@24a0000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x24a0000 0x00 0x400>;
+               interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 60 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 60 1>;
+               assigned-clock-parents = <&k3_clks 60 2>;
+               power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer11: timer@24b0000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x24b0000 0x00 0x400>;
+               interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 62 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
+               assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>;
+               power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer12: timer@24c0000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x24c0000 0x00 0x400>;
+               interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 63 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 63 1>;
+               assigned-clock-parents = <&k3_clks 63 2>;
+               power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer13: timer@24d0000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x24d0000 0x00 0x400>;
+               interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 64 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
+               assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>;
+               power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer14: timer@24e0000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x24e0000 0x00 0x400>;
+               interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 65 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 65 1>;
+               assigned-clock-parents = <&k3_clks 65 2>;
+               power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer15: timer@24f0000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x24f0000 0x00 0x400>;
+               interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 66 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
+               assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>;
+               power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer16: timer@2500000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x2500000 0x00 0x400>;
+               interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 67 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 67 1>;
+               assigned-clock-parents = <&k3_clks 67 2>;
+               power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer17: timer@2510000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x2510000 0x00 0x400>;
+               interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 68 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
+               assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>;
+               power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer18: timer@2520000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x2520000 0x00 0x400>;
+               interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 69 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 69 1>;
+               assigned-clock-parents = <&k3_clks 69 2>;
+               power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+       };
+
+       main_timer19: timer@2530000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x2530000 0x00 0x400>;
+               interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 70 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
+               assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>;
+               power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
        };
 
        main_uart0: serial@2800000 {
@@ -795,6 +1214,7 @@
                power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 146 0>;
                clock-names = "fclk";
+               status = "disabled";
        };
 
        main_uart1: serial@2810000 {
@@ -806,6 +1226,7 @@
                power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 278 0>;
                clock-names = "fclk";
+               status = "disabled";
        };
 
        main_uart2: serial@2820000 {
@@ -817,6 +1238,7 @@
                power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 279 0>;
                clock-names = "fclk";
+               status = "disabled";
        };
 
        main_uart3: serial@2830000 {
@@ -828,6 +1250,7 @@
                power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 280 0>;
                clock-names = "fclk";
+               status = "disabled";
        };
 
        main_uart4: serial@2840000 {
@@ -839,6 +1262,7 @@
                power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 281 0>;
                clock-names = "fclk";
+               status = "disabled";
        };
 
        main_uart5: serial@2850000 {
@@ -850,6 +1274,7 @@
                power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 282 0>;
                clock-names = "fclk";
+               status = "disabled";
        };
 
        main_uart6: serial@2860000 {
@@ -861,6 +1286,7 @@
                power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 283 0>;
                clock-names = "fclk";
+               status = "disabled";
        };
 
        main_uart7: serial@2870000 {
@@ -872,6 +1298,7 @@
                power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 284 0>;
                clock-names = "fclk";
+               status = "disabled";
        };
 
        main_uart8: serial@2880000 {
@@ -883,6 +1310,7 @@
                power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 285 0>;
                clock-names = "fclk";
+               status = "disabled";
        };
 
        main_uart9: serial@2890000 {
@@ -894,6 +1322,7 @@
                power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 286 0>;
                clock-names = "fclk";
+               status = "disabled";
        };
 
        main_gpio0: gpio@600000 {
@@ -911,6 +1340,7 @@
                power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 105 0>;
                clock-names = "gpio";
+               status = "disabled";
        };
 
        main_gpio1: gpio@601000 {
@@ -927,6 +1357,7 @@
                power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 106 0>;
                clock-names = "gpio";
+               status = "disabled";
        };
 
        main_gpio2: gpio@610000 {
@@ -944,6 +1375,7 @@
                power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 107 0>;
                clock-names = "gpio";
+               status = "disabled";
        };
 
        main_gpio3: gpio@611000 {
@@ -960,6 +1392,7 @@
                power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 108 0>;
                clock-names = "gpio";
+               status = "disabled";
        };
 
        main_gpio4: gpio@620000 {
@@ -977,6 +1410,7 @@
                power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 109 0>;
                clock-names = "gpio";
+               status = "disabled";
        };
 
        main_gpio5: gpio@621000 {
@@ -993,6 +1427,7 @@
                power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 110 0>;
                clock-names = "gpio";
+               status = "disabled";
        };
 
        main_gpio6: gpio@630000 {
@@ -1010,6 +1445,7 @@
                power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 111 0>;
                clock-names = "gpio";
+               status = "disabled";
        };
 
        main_gpio7: gpio@631000 {
@@ -1026,6 +1462,7 @@
                power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 112 0>;
                clock-names = "gpio";
+               status = "disabled";
        };
 
        main_sdhci0: mmc@4f80000 {
@@ -1040,8 +1477,8 @@
                bus-width = <8>;
                mmc-hs200-1_8v;
                mmc-ddr-1_8v;
-               ti,otap-del-sel-legacy = <0xf>;
-               ti,otap-del-sel-mmc-hs = <0xf>;
+               ti,otap-del-sel-legacy = <0x0>;
+               ti,otap-del-sel-mmc-hs = <0x0>;
                ti,otap-del-sel-ddr52 = <0x5>;
                ti,otap-del-sel-hs200 = <0x6>;
                ti,otap-del-sel-hs400 = <0x0>;
@@ -1049,8 +1486,8 @@
                ti,itap-del-sel-mmc-hs = <0xa>;
                ti,itap-del-sel-ddr52 = <0x3>;
                ti,trm-icp = <0x8>;
-               ti,strobe-sel = <0x77>;
                dma-coherent;
+               status = "disabled";
        };
 
        main_sdhci1: mmc@4fb0000 {
@@ -1063,11 +1500,12 @@
                assigned-clocks = <&k3_clks 92 0>;
                assigned-clock-parents = <&k3_clks 92 1>;
                ti,otap-del-sel-legacy = <0x0>;
-               ti,otap-del-sel-sd-hs = <0xf>;
+               ti,otap-del-sel-sd-hs = <0x0>;
                ti,otap-del-sel-sdr12 = <0xf>;
                ti,otap-del-sel-sdr25 = <0xf>;
                ti,otap-del-sel-sdr50 = <0xc>;
                ti,otap-del-sel-ddr50 = <0xc>;
+               ti,otap-del-sel-sdr104 = <0x5>;
                ti,itap-del-sel-legacy = <0x0>;
                ti,itap-del-sel-sd-hs = <0x0>;
                ti,itap-del-sel-sdr12 = <0x0>;
@@ -1077,6 +1515,7 @@
                ti,clkbuf-sel = <0x7>;
                dma-coherent;
                sdhci-caps-mask = <0x2 0x0>;
+               status = "disabled";
        };
 
        main_sdhci2: mmc@4f98000 {
@@ -1089,11 +1528,12 @@
                assigned-clocks = <&k3_clks 93 0>;
                assigned-clock-parents = <&k3_clks 93 1>;
                ti,otap-del-sel-legacy = <0x0>;
-               ti,otap-del-sel-sd-hs = <0xf>;
+               ti,otap-del-sel-sd-hs = <0x0>;
                ti,otap-del-sel-sdr12 = <0xf>;
                ti,otap-del-sel-sdr25 = <0xf>;
                ti,otap-del-sel-sdr50 = <0xc>;
                ti,otap-del-sel-ddr50 = <0xc>;
+               ti,otap-del-sel-sdr104 = <0x5>;
                ti,itap-del-sel-legacy = <0x0>;
                ti,itap-del-sel-sd-hs = <0x0>;
                ti,itap-del-sel-sdr12 = <0x0>;
@@ -1103,6 +1543,7 @@
                ti,clkbuf-sel = <0x7>;
                dma-coherent;
                sdhci-caps-mask = <0x2 0x0>;
+               status = "disabled";
        };
 
        usbss0: cdns-usb@4104000 {
@@ -1174,6 +1615,7 @@
                clock-names = "fck";
                clocks = <&k3_clks 187 0>;
                power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
+               status = "disabled";
        };
 
        main_i2c1: i2c@2010000 {
@@ -1185,6 +1627,7 @@
                clock-names = "fck";
                clocks = <&k3_clks 188 0>;
                power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        main_i2c2: i2c@2020000 {
@@ -1196,6 +1639,7 @@
                clock-names = "fck";
                clocks = <&k3_clks 189 0>;
                power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        main_i2c3: i2c@2030000 {
@@ -1207,6 +1651,7 @@
                clock-names = "fck";
                clocks = <&k3_clks 190 0>;
                power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        main_i2c4: i2c@2040000 {
@@ -1218,6 +1663,7 @@
                clock-names = "fck";
                clocks = <&k3_clks 191 0>;
                power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        main_i2c5: i2c@2050000 {
@@ -1229,6 +1675,7 @@
                clock-names = "fck";
                clocks = <&k3_clks 192 0>;
                power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        main_i2c6: i2c@2060000 {
@@ -1240,6 +1687,7 @@
                clock-names = "fck";
                clocks = <&k3_clks 193 0>;
                power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        ufs_wrapper: ufs-wrapper@4e80000 {
@@ -1264,6 +1712,37 @@
                };
        };
 
+       mhdp: dp-bridge@a000000 {
+               compatible = "ti,j721e-mhdp8546";
+               /*
+                * Note: we do not map DPTX PHY area, as that is handled by
+                * the PHY driver.
+                */
+               reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
+                     <0x00 0x04f40000 0x00 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
+               reg-names = "mhdptx", "j721e-intg";
+
+               clocks = <&k3_clks 151 36>;
+
+               interrupt-parent = <&gic500>;
+               interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
+
+               power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
+
+               dp0_ports: ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                           reg = <0>;
+                       };
+
+                       port@4 {
+                           reg = <4>;
+                       };
+               };
+       };
+
        dss: dss@4a00000 {
                compatible = "ti,j721e-dss";
                reg =
@@ -1295,11 +1774,11 @@
                        "vp1", "vp2", "vp3", "vp4",
                        "wb";
 
-               clocks =        <&k3_clks 152 0>,
-                               <&k3_clks 152 1>,
-                               <&k3_clks 152 4>,
-                               <&k3_clks 152 9>,
-                               <&k3_clks 152 13>;
+               clocks = <&k3_clks 152 0>,
+                        <&k3_clks 152 1>,
+                        <&k3_clks 152 4>,
+                        <&k3_clks 152 9>,
+                        <&k3_clks 152 13>;
                clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
 
                power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
@@ -1314,8 +1793,6 @@
                                  "common_s2";
 
                dss_ports: ports {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
                };
        };
 
@@ -1334,6 +1811,7 @@
                clocks = <&k3_clks 174 1>;
                clock-names = "fck";
                power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        mcasp1: mcasp@2b10000 {
@@ -1351,6 +1829,7 @@
                clocks = <&k3_clks 175 1>;
                clock-names = "fck";
                power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        mcasp2: mcasp@2b20000 {
@@ -1368,6 +1847,7 @@
                clocks = <&k3_clks 176 1>;
                clock-names = "fck";
                power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        mcasp3: mcasp@2b30000 {
@@ -1385,6 +1865,7 @@
                clocks = <&k3_clks 177 1>;
                clock-names = "fck";
                power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        mcasp4: mcasp@2b40000 {
@@ -1402,6 +1883,7 @@
                clocks = <&k3_clks 178 1>;
                clock-names = "fck";
                power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        mcasp5: mcasp@2b50000 {
@@ -1419,6 +1901,7 @@
                clocks = <&k3_clks 179 1>;
                clock-names = "fck";
                power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        mcasp6: mcasp@2b60000 {
@@ -1436,6 +1919,7 @@
                clocks = <&k3_clks 180 1>;
                clock-names = "fck";
                power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        mcasp7: mcasp@2b70000 {
@@ -1453,6 +1937,7 @@
                clocks = <&k3_clks 181 1>;
                clock-names = "fck";
                power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        mcasp8: mcasp@2b80000 {
@@ -1470,6 +1955,7 @@
                clocks = <&k3_clks 182 1>;
                clock-names = "fck";
                power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        mcasp9: mcasp@2b90000 {
@@ -1487,6 +1973,7 @@
                clocks = <&k3_clks 183 1>;
                clock-names = "fck";
                power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        mcasp10: mcasp@2ba0000 {
@@ -1504,6 +1991,7 @@
                clocks = <&k3_clks 184 1>;
                clock-names = "fck";
                power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        mcasp11: mcasp@2bb0000 {
@@ -1521,6 +2009,7 @@
                clocks = <&k3_clks 185 1>;
                clock-names = "fck";
                power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        watchdog0: watchdog@2200000 {
@@ -1632,6 +2121,7 @@
                ti,sci-proc-ids = <0x03 0xff>;
                resets = <&k3_reset 142 1>;
                firmware-name = "j7-c66_0-fw";
+               status = "disabled";
        };
 
        c66_1: dsp@4d81800000 {
@@ -1645,6 +2135,7 @@
                ti,sci-proc-ids = <0x04 0xff>;
                resets = <&k3_reset 143 1>;
                firmware-name = "j7-c66_1-fw";
+               status = "disabled";
        };
 
        c71_0: dsp@64800000 {
@@ -1657,6 +2148,7 @@
                ti,sci-proc-ids = <0x30 0xff>;
                resets = <&k3_reset 15 1>;
                firmware-name = "j7-c71_0-fw";
+               status = "disabled";
        };
 
        icssg0: icssg@b000000 {
@@ -1797,6 +2289,7 @@
                        #address-cells = <1>;
                        #size-cells = <0>;
                        bus_freq = <1000000>;
+                       status = "disabled";
                };
        };
 
@@ -1938,6 +2431,311 @@
                        #address-cells = <1>;
                        #size-cells = <0>;
                        bus_freq = <1000000>;
-               };
+                       status = "disabled";
+               };
+       };
+
+       main_mcan0: can@2701000 {
+               compatible = "bosch,m_can";
+               reg = <0x00 0x02701000 0x00 0x200>,
+                     <0x00 0x02708000 0x00 0x8000>;
+               reg-names = "m_can", "message_ram";
+               power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
+               clock-names = "hclk", "cclk";
+               interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+               status = "disabled";
+       };
+
+       main_mcan1: can@2711000 {
+               compatible = "bosch,m_can";
+               reg = <0x00 0x02711000 0x00 0x200>,
+                     <0x00 0x02718000 0x00 0x8000>;
+               reg-names = "m_can", "message_ram";
+               power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
+               clock-names = "hclk", "cclk";
+               interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+               status = "disabled";
+       };
+
+       main_mcan2: can@2721000 {
+               compatible = "bosch,m_can";
+               reg = <0x00 0x02721000 0x00 0x200>,
+                     <0x00 0x02728000 0x00 0x8000>;
+               reg-names = "m_can", "message_ram";
+               power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
+               clock-names = "hclk", "cclk";
+               interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+               status = "disabled";
+       };
+
+       main_mcan3: can@2731000 {
+               compatible = "bosch,m_can";
+               reg = <0x00 0x02731000 0x00 0x200>,
+                     <0x00 0x02738000 0x00 0x8000>;
+               reg-names = "m_can", "message_ram";
+               power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
+               clock-names = "hclk", "cclk";
+               interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+               status = "disabled";
+       };
+
+       main_mcan4: can@2741000 {
+               compatible = "bosch,m_can";
+               reg = <0x00 0x02741000 0x00 0x200>,
+                     <0x00 0x02748000 0x00 0x8000>;
+               reg-names = "m_can", "message_ram";
+               power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
+               clock-names = "hclk", "cclk";
+               interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+               status = "disabled";
+       };
+
+       main_mcan5: can@2751000 {
+               compatible = "bosch,m_can";
+               reg = <0x00 0x02751000 0x00 0x200>,
+                     <0x00 0x02758000 0x00 0x8000>;
+               reg-names = "m_can", "message_ram";
+               power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
+               clock-names = "hclk", "cclk";
+               interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+               status = "disabled";
+       };
+
+       main_mcan6: can@2761000 {
+               compatible = "bosch,m_can";
+               reg = <0x00 0x02761000 0x00 0x200>,
+                     <0x00 0x02768000 0x00 0x8000>;
+               reg-names = "m_can", "message_ram";
+               power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
+               clock-names = "hclk", "cclk";
+               interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+               status = "disabled";
+       };
+
+       main_mcan7: can@2771000 {
+               compatible = "bosch,m_can";
+               reg = <0x00 0x02771000 0x00 0x200>,
+                     <0x00 0x02778000 0x00 0x8000>;
+               reg-names = "m_can", "message_ram";
+               power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
+               clock-names = "hclk", "cclk";
+               interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+               status = "disabled";
+       };
+
+       main_mcan8: can@2781000 {
+               compatible = "bosch,m_can";
+               reg = <0x00 0x02781000 0x00 0x200>,
+                     <0x00 0x02788000 0x00 0x8000>;
+               reg-names = "m_can", "message_ram";
+               power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
+               clock-names = "hclk", "cclk";
+               interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+               status = "disabled";
+       };
+
+       main_mcan9: can@2791000 {
+               compatible = "bosch,m_can";
+               reg = <0x00 0x02791000 0x00 0x200>,
+                     <0x00 0x02798000 0x00 0x8000>;
+               reg-names = "m_can", "message_ram";
+               power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
+               clock-names = "hclk", "cclk";
+               interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+               status = "disabled";
+       };
+
+       main_mcan10: can@27a1000 {
+               compatible = "bosch,m_can";
+               reg = <0x00 0x027a1000 0x00 0x200>,
+                     <0x00 0x027a8000 0x00 0x8000>;
+               reg-names = "m_can", "message_ram";
+               power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
+               clock-names = "hclk", "cclk";
+               interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+               status = "disabled";
+       };
+
+       main_mcan11: can@27b1000 {
+               compatible = "bosch,m_can";
+               reg = <0x00 0x027b1000 0x00 0x200>,
+                     <0x00 0x027b8000 0x00 0x8000>;
+               reg-names = "m_can", "message_ram";
+               power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
+               clock-names = "hclk", "cclk";
+               interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+               status = "disabled";
+       };
+
+       main_mcan12: can@27c1000 {
+               compatible = "bosch,m_can";
+               reg = <0x00 0x027c1000 0x00 0x200>,
+                     <0x00 0x027c8000 0x00 0x8000>;
+               reg-names = "m_can", "message_ram";
+               power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
+               clock-names = "hclk", "cclk";
+               interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+               status = "disabled";
+       };
+
+       main_mcan13: can@27d1000 {
+               compatible = "bosch,m_can";
+               reg = <0x00 0x027d1000 0x00 0x200>,
+                     <0x00 0x027d8000 0x00 0x8000>;
+               reg-names = "m_can", "message_ram";
+               power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
+               clock-names = "hclk", "cclk";
+               interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+               status = "disabled";
+       };
+
+       main_spi0: spi@2100000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x02100000 0x00 0x400>;
+               interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 266 1>;
+               status = "disabled";
+       };
+
+       main_spi1: spi@2110000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x02110000 0x00 0x400>;
+               interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 267 1>;
+               status = "disabled";
+       };
+
+       main_spi2: spi@2120000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x02120000 0x00 0x400>;
+               interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 268 1>;
+               status = "disabled";
+       };
+
+       main_spi3: spi@2130000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x02130000 0x00 0x400>;
+               interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 269 1>;
+               status = "disabled";
+       };
+
+       main_spi4: spi@2140000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x02140000 0x00 0x400>;
+               interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 270 1>;
+               status = "disabled";
+       };
+
+       main_spi5: spi@2150000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x02150000 0x00 0x400>;
+               interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 271 1>;
+               status = "disabled";
+       };
+
+       main_spi6: spi@2160000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x02160000 0x00 0x400>;
+               interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 272 1>;
+               status = "disabled";
+       };
+
+       main_spi7: spi@2170000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x02170000 0x00 0x400>;
+               interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 273 1>;
+               status = "disabled";
+       };
+
+       main_esm: esm@700000 {
+               compatible = "ti,j721e-esm";
+               reg = <0x0 0x700000 0x0 0x1000>;
+               ti,esm-pins = <344>, <345>;
        };
 };

diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
index 22166c7..05d6ef1 100644 (file)
--- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
@@ -12,8 +12,8 @@
 
                mbox-names = "rx", "tx";
 
-               mboxes= <&secure_proxy_main 11>,
-                       <&secure_proxy_main 13>;
+               mboxes = <&secure_proxy_main 11>,
+                        <&secure_proxy_main 13>;
 
                reg-names = "debug_messages";
                reg = <0x00 0x44083000 0x0 0x1000>;
@@ -62,6 +62,28 @@
                pinctrl-single,function-mask = <0xffffffff>;
        };
 
+       /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+       mcu_timerio_input: pinctrl@40f04200 {
+               compatible = "pinctrl-single";
+               reg = <0x00 0x40f04200 0x00 0x28>;
+               #pinctrl-cells = <1>;
+               pinctrl-single,register-width = <32>;
+               pinctrl-single,function-mask = <0x0000000f>;
+               /* Non-MPU Firmware usage */
+               status = "reserved";
+       };
+
+       /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+       mcu_timerio_output: pinctrl@40f04280 {
+               compatible = "pinctrl-single";
+               reg = <0x00 0x40f04280 0x00 0x28>;
+               #pinctrl-cells = <1>;
+               pinctrl-single,register-width = <32>;
+               pinctrl-single,function-mask = <0x0000000f>;
+               /* Non-MPU Firmware usage */
+               status = "reserved";
+       };
+
        mcu_ram: sram@41c00000 {
                compatible = "mmio-sram";
                reg = <0x00 0x41c00000 0x00 0x100000>;
@@ -70,6 +92,145 @@
                #size-cells = <1>;
        };
 
+       mcu_timer0: timer@40400000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x40400000 0x00 0x400>;
+               interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 35 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 35 1>;
+               assigned-clock-parents = <&k3_clks 35 2>;
+               power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+               /* Non-MPU Firmware usage */
+               status = "reserved";
+       };
+
+       mcu_timer1: timer@40410000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x40410000 0x00 0x400>;
+               interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 71 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
+               assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>;
+               power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+               /* Non-MPU Firmware usage */
+               status = "reserved";
+       };
+
+       mcu_timer2: timer@40420000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x40420000 0x00 0x400>;
+               interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 72 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 72 1>;
+               assigned-clock-parents = <&k3_clks 72 2>;
+               power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+               /* Non-MPU Firmware usage */
+               status = "reserved";
+       };
+
+       mcu_timer3: timer@40430000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x40430000 0x00 0x400>;
+               interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 73 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
+               assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>;
+               power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+               /* Non-MPU Firmware usage */
+               status = "reserved";
+       };
+
+       mcu_timer4: timer@40440000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x40440000 0x00 0x400>;
+               interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 74 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 74 1>;
+               assigned-clock-parents = <&k3_clks 74 2>;
+               power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+               /* Non-MPU Firmware usage */
+               status = "reserved";
+       };
+
+       mcu_timer5: timer@40450000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x40450000 0x00 0x400>;
+               interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 75 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>;
+               assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>;
+               power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+               /* Non-MPU Firmware usage */
+               status = "reserved";
+       };
+
+       mcu_timer6: timer@40460000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x40460000 0x00 0x400>;
+               interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 76 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 76 1>;
+               assigned-clock-parents = <&k3_clks 76 2>;
+               power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+               /* Non-MPU Firmware usage */
+               status = "reserved";
+       };
+
+       mcu_timer7: timer@40470000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x40470000 0x00 0x400>;
+               interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 77 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>;
+               assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>;
+               power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+               /* Non-MPU Firmware usage */
+               status = "reserved";
+       };
+
+       mcu_timer8: timer@40480000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x40480000 0x00 0x400>;
+               interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 78 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 78 1>;
+               assigned-clock-parents = <&k3_clks 78 2>;
+               power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+               /* Non-MPU Firmware usage */
+               status = "reserved";
+       };
+
+       mcu_timer9: timer@40490000 {
+               compatible = "ti,am654-timer";
+               reg = <0x00 0x40490000 0x00 0x400>;
+               interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 79 1>;
+               clock-names = "fck";
+               assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>;
+               assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>;
+               power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
+               ti,timer-pwm;
+               /* Non-MPU Firmware usage */
+               status = "reserved";
+       };
        wkup_uart0: serial@42300000 {
                compatible = "ti,j721e-uart", "ti,am654-uart";
                reg = <0x00 0x42300000 0x00 0x100>;
@@ -79,6 +240,7 @@
                power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 287 0>;
                clock-names = "fclk";
+               status = "disabled";
        };
 
        mcu_uart0: serial@40a00000 {
@@ -90,6 +252,7 @@
                power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 149 0>;
                clock-names = "fclk";
+               status = "disabled";
        };
 
        wkup_gpio_intr: interrupt-controller@42200000 {
@@ -118,6 +281,7 @@
                power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 113 0>;
                clock-names = "gpio";
+               status = "disabled";
        };
 
        wkup_gpio1: gpio@42100000 {
@@ -134,6 +298,7 @@
                power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 114 0>;
                clock-names = "gpio";
+               status = "disabled";
        };
 
        mcu_i2c0: i2c@40b00000 {
@@ -145,6 +310,7 @@
                clock-names = "fck";
                clocks = <&k3_clks 194 0>;
                power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        mcu_i2c1: i2c@40b10000 {
@@ -156,6 +322,7 @@
                clock-names = "fck";
                clocks = <&k3_clks 195 0>;
                power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
        };
 
        wkup_i2c0: i2c@42120000 {
@@ -167,31 +334,35 @@
                clock-names = "fck";
                clocks = <&k3_clks 197 0>;
                power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
+               status = "disabled";
        };
 
-       fss: fss@47000000 {
-               compatible = "syscon", "simple-mfd";
+       fss: bus@47000000 {
+               compatible = "simple-bus";
                reg = <0x0 0x47000000 0x0 0x100>;
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;
 
-               hbmc_mux: hbmc-mux {
-                       compatible = "mmio-mux";
+               hbmc_mux: mux-controller@47000004 {
+                       compatible = "reg-mux";
+                       reg = <0x00 0x47000004 0x00 0x2>;
                        #mux-control-cells = <1>;
                        mux-reg-masks = <0x4 0x2>; /* HBMC select */
                };
 
                hbmc: hyperbus@47034000 {
-                       compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
-                       reg = <0x0 0x47034000 0x0 0x100>,
-                               <0x5 0x00000000 0x1 0x0000000>;
+                       compatible = "ti,am654-hbmc";
+                       reg = <0x00 0x47034000 0x00 0x100>,
+                               <0x05 0x00000000 0x01 0x0000000>;
                        power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+                       clocks = <&k3_clks 102 0>;
+                       assigned-clocks = <&k3_clks 102 5>;
+                       assigned-clock-rates = <333333333>;
                        #address-cells = <2>;
                        #size-cells = <1>;
                        mux-controls = <&hbmc_mux 0>;
-                       assigned-clocks = <&k3_clks 102 0>;
-                       assigned-clock-rates = <250000000>;
+                       status = "disabled";
                };
 
                ospi0: spi@47040000 {
@@ -209,6 +380,7 @@
                        power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                       status = "disabled";
                };
 
                ospi1: spi@47050000 {
@@ -223,6 +395,7 @@
                        power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                       status = "disabled";
                };
        };
 
@@ -234,10 +407,11 @@
                clocks = <&k3_clks 0 1>;
                assigned-clocks = <&k3_clks 0 3>;
                assigned-clock-rates = <60000000>;
-               clock-names = "adc_tsc_fck";
+               clock-names = "fck";
                dmas = <&main_udmap 0x7400>,
                        <&main_udmap 0x7401>;
                dma-names = "fifo0", "fifo1";
+               status = "disabled";
 
                adc {
                        #io-channel-cells = <1>;
@@ -253,10 +427,11 @@
                clocks = <&k3_clks 1 1>;
                assigned-clocks = <&k3_clks 1 3>;
                assigned-clock-rates = <60000000>;
-               clock-names = "adc_tsc_fck";
+               clock-names = "fck";
                dmas = <&main_udmap 0x7402>,
                        <&main_udmap 0x7403>;
                dma-names = "fifo0", "fifo1";
+               status = "disabled";
 
                adc {
                        #io-channel-cells = <1>;
@@ -276,11 +451,12 @@
 
                mcu_ringacc: ringacc@2b800000 {
                        compatible = "ti,am654-navss-ringacc";
-                       reg =   <0x0 0x2b800000 0x0 0x400000>,
-                               <0x0 0x2b000000 0x0 0x400000>,
-                               <0x0 0x28590000 0x0 0x100>,
-                               <0x0 0x2a500000 0x0 0x40000>;
-                       reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+                       reg = <0x0 0x2b800000 0x0 0x400000>,
+                             <0x0 0x2b000000 0x0 0x400000>,
+                             <0x0 0x28590000 0x0 0x100>,
+                             <0x0 0x2a500000 0x0 0x40000>,
+                             <0x0 0x28440000 0x0 0x40000>;
+                       reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
                        ti,num-rings = <286>;
                        ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
                        ti,sci = <&dmsc>;
@@ -290,9 +466,9 @@
 
                mcu_udmap: dma-controller@285c0000 {
                        compatible = "ti,j721e-navss-mcu-udmap";
-                       reg =   <0x0 0x285c0000 0x0 0x100>,
-                               <0x0 0x2a800000 0x0 0x40000>,
-                               <0x0 0x2aa00000 0x0 0x40000>;
+                       reg = <0x0 0x285c0000 0x0 0x100>,
+                             <0x0 0x2a800000 0x0 0x40000>,
+                             <0x0 0x2aa00000 0x0 0x40000>;
                        reg-names = "gcfg", "rchanrt", "tchanrt";
                        msi-parent = <&main_udmass_inta>;
                        #dma-cells = <1>;
@@ -309,6 +485,21 @@
                };
        };
 
+       secure_proxy_mcu: mailbox@2a480000 {
+               compatible = "ti,am654-secure-proxy";
+               #mbox-cells = <1>;
+               reg-names = "target_data", "rt", "scfg";
+               reg = <0x0 0x2a480000 0x0 0x80000>,
+                     <0x0 0x2a380000 0x0 0x80000>,
+                     <0x0 0x2a400000 0x0 0x80000>;
+               /*
+                * Marked Disabled:
+                * Node is incomplete as it is meant for bootloaders and
+                * firmware on non-MPU processors
+                */
+               status = "disabled";
+       };
+
        mcu_cpsw: ethernet@46000000 {
                compatible = "ti,j721e-cpsw-nuss";
                #address-cells = <2>;
@@ -408,4 +599,76 @@
                        ti,loczrama = <1>;
                };
        };
+
+       mcu_mcan0: can@40528000 {
+               compatible = "bosch,m_can";
+               reg = <0x00 0x40528000 0x00 0x200>,
+                     <0x00 0x40500000 0x00 0x8000>;
+               reg-names = "m_can", "message_ram";
+               power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 172 0>, <&k3_clks 172 1>;
+               clock-names = "hclk", "cclk";
+               interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+               status = "disabled";
+       };
+
+       mcu_mcan1: can@40568000 {
+               compatible = "bosch,m_can";
+               reg = <0x00 0x40568000 0x00 0x200>,
+                     <0x00 0x40540000 0x00 0x8000>;
+               reg-names = "m_can", "message_ram";
+               power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 173 0>, <&k3_clks 173 1>;
+               clock-names = "hclk", "cclk";
+               interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+               status = "disabled";
+       };
+
+       mcu_spi0: spi@40300000 {
+               compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+               reg = <0x00 0x040300000 0x00 0x400>;
+               interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 274 0>;
+               status = "disabled";
+       };
+
+       mcu_spi1: spi@40310000 {
+               compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+               reg = <0x00 0x040310000 0x00 0x400>;
+               interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 275 0>;
+               status = "disabled";
+       };
+
+       mcu_spi2: spi@40320000 {
+               compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+               reg = <0x00 0x040320000 0x00 0x400>;
+               interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 276 0>;
+               status = "disabled";
+       };
+
+       wkup_vtm0: temperature-sensor@42040000 {
+               compatible = "ti,j721e-vtm";
+               reg = <0x00 0x42040000 0x00 0x350>,
+                     <0x00 0x42050000 0x00 0x350>,
+                     <0x00 0x43000300 0x00 0x10>;
+               power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+               #thermal-sensor-cells = <1>;
+       };
 };

diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
deleted file mode 100644 (file)
index f9746d3..0000000
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include "k3-j721e-common-proc-board-u-boot.dtsi"
-
-/ {
-       chosen {
-               firmware-loader = &fs_loader0;
-       };
-
-       aliases {
-               remoteproc0 = &sysctrler;
-               remoteproc1 = &a72_0;
-       };
-
-       fs_loader0: fs_loader@0 {
-               bootph-all;
-               compatible = "u-boot,fs-loader";
-       };
-};
-
-&tps659413a {
-       esm: esm {
-               compatible = "ti,tps659413-esm";
-               bootph-pre-ram;
-       };
-};

diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 32f71e9..fcd9c71 100644 (file)
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -5,23 +5,21 @@
 
 /dts-v1/;
 
-#include "k3-j721e-som-p0.dtsi"
+#include "k3-j721e-common-proc-board.dts"
 #include "k3-j721e-ddr-evm-lp4-4266.dtsi"
 #include "k3-j721e-ddr.dtsi"
-#include "k3-j721e-binman.dtsi"
-#include <dt-bindings/phy/phy-cadence.h>
+#include "k3-j721e-common-proc-board-u-boot.dtsi"
 
 / {
+       chosen {
+               tick-timer = &mcu_timer0;
+       };
+
        aliases {
                remoteproc0 = &sysctrler;
                remoteproc1 = &a72_0;
        };
 
-       chosen {
-               stdout-path = "serial2:115200n8";
-               tick-timer = &timer1;
-       };
-
        a72_0: a72@0 {
                compatible = "ti,am654-rproc";
                reg = <0x0 0x00a90000 0x0 0x10>;
@@ -38,244 +36,49 @@
                bootph-pre-ram;
        };
 
-       clk_200mhz: dummy_clock_200mhz {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <200000000>;
-               bootph-pre-ram;
-       };
-
-       clk_19_2mhz: dummy_clock_19_2mhz {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <19200000>;
-               bootph-pre-ram;
-       };
-};
-
-&cbass_mcu_wakeup {
-       mcu_secproxy: secproxy@28380000 {
-               bootph-pre-ram;
-               compatible = "ti,am654-secure-proxy";
-               reg = <0x0 0x2a380000 0x0 0x80000>,
-                     <0x0 0x2a400000 0x0 0x80000>,
-                     <0x0 0x2a480000 0x0 0x80000>;
-               reg-names = "rt", "scfg", "target_data";
-               #mbox-cells = <1>;
-       };
-
-       sysctrler: sysctrler {
-               bootph-pre-ram;
-               compatible = "ti,am654-system-controller";
-               mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
-               mbox-names = "tx", "rx";
-       };
-
-       wkup_vtm0: wkup_vtm@42040000 {
-               compatible = "ti,am654-vtm", "ti,j721e-avs";
-               reg = <0x0 0x42040000 0x0 0x330>;
-               power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
-               #thermal-sensor-cells = <1>;
-       };
-
        dm_tifs: dm-tifs {
                compatible = "ti,j721e-dm-sci";
                ti,host-id = <3>;
                ti,secure-host;
                mbox-names = "rx", "tx";
-               mboxes= <&mcu_secproxy 21>,
-                       <&mcu_secproxy 23>;
+               mboxes= <&secure_proxy_mcu 21>,
+                       <&secure_proxy_mcu 23>;
                bootph-pre-ram;
        };
 };
 
-&cbass_main {
-       main_esm: esm@700000 {
-               compatible = "ti,j721e-esm";
-               reg = <0x0 0x700000 0x0 0x1000>;
-               ti,esm-pins = <344>, <345>;
-               bootph-pre-ram;
-       };
+&mcu_timer0 {
+       status = "okay";
+       bootph-pre-ram;
 };
 
 &dmsc {
-       mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+       mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
        mbox-names = "tx", "rx", "notify";
        ti,host-id = <4>;
        ti,secure-host;
 };
 
-&wkup_pmx0 {
-       wkup_uart0_pins_default: wkup_uart0_pins_default {
-               bootph-pre-ram;
-               pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
-                       J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
-               >;
-       };
-
-       mcu_uart0_pins_default: mcu_uart0_pins_default {
-               bootph-pre-ram;
-               pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */
-                       J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
-                       J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
-                       J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
-               >;
-       };
-
-       wkup_i2c0_pins_default: wkup-i2c0-pins-default {
-               pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
-                       J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
-               >;
-       };
-
-       mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
-               pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
-                       J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
-                       J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
-                       J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
-                       J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
-                       J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
-                       J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
-                       J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
-                       J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
-                       J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
-                       J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
-                       J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
-                       J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
-                       J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
-               >;
-       };
-
-       wkup_gpio_pins_default: wkup-gpio-pins-default {
-               pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* WKUP_GPIO0_8 */
-               >;
-       };
-
-       mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
-               pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
-                       J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
-                       J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* MCU_OSPI0_D0 */
-                       J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* MCU_OSPI0_D1 */
-                       J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* MCU_OSPI0_D2 */
-                       J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* MCU_OSPI0_D3 */
-                       J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* MCU_OSPI0_D4 */
-                       J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* MCU_OSPI0_D5 */
-                       J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
-                       J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
-                       J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
-               >;
-       };
-
-       mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
-               bootph-pre-ram;
-               pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
-                       J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
-                       J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
-                       J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
-                       J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
-                       J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
-                       J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
-                       J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
-               >;
-       };
-};
-
-&main_pmx0 {
-       main_uart0_pins_default: main_uart0_pins_default {
-               bootph-pre-ram;
-               pinctrl-single,pins = <
-                       J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */
-                       J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
-                       J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
-                       J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
-               >;
-       };
-
-       main_usbss0_pins_default: main_usbss0_pins_default {
-               pinctrl-single,pins = <
-                       J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
-                       J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
-               >;
-       };
-
-       main_mmc1_pins_default: main_mmc1_pins_default {
-               pinctrl-single,pins = <
-                       J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
-                       J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
-                       J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
-                       J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
-                       J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
-                       J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
-                       J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
-                       J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
-                       J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
-               >;
-       };
-
-       main_i2c0_pins_default: main-i2c0-pins-default {
-               pinctrl-single,pins = <
-                       J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
-                       J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
-               >;
-       };
-};
-
-&wkup_uart0 {
+&secure_proxy_mcu {
        bootph-pre-ram;
-       pinctrl-names = "default";
-       pinctrl-0 = <&wkup_uart0_pins_default>;
        status = "okay";
 };
 
-&wkup_gpio0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&wkup_gpio_pins_default>;
-};
-
-&mcu_uart0 {
-       /delete-property/ power-domains;
-       /delete-property/ clocks;
-       /delete-property/ clock-names;
-       pinctrl-names = "default";
-       pinctrl-0 = <&mcu_uart0_pins_default>;
-       status = "okay";
-       clock-frequency = <48000000>;
-};
-
-&main_uart0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&main_uart0_pins_default>;
-       status = "okay";
-       power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+&cbass_mcu_wakeup {
+       sysctrler: sysctrler {
+               bootph-pre-ram;
+               compatible = "ti,am654-system-controller";
+               mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
+               mbox-names = "tx", "rx";
+       };
 };
 
-&main_sdhci0 {
-       /delete-property/ power-domains;
-       /delete-property/ assigned-clocks;
-       /delete-property/ assigned-clock-parents;
-       clock-names = "clk_xin";
-       clocks = <&clk_200mhz>;
-       ti,driver-strength-ohm = <50>;
-       non-removable;
-       bus-width = <8>;
+&mcu_ringacc {
+       ti,sci = <&dm_tifs>;
 };
 
-&main_sdhci1 {
-       /delete-property/ power-domains;
-       /delete-property/ assigned-clocks;
-       /delete-property/ assigned-clock-parents;
-       pinctrl-names = "default";
-       pinctrl-0 = <&main_mmc1_pins_default>;
-       clock-names = "clk_xin";
-       clocks = <&clk_200mhz>;
-       ti,driver-strength-ohm = <50>;
+&mcu_udmap {
+       ti,sci = <&dm_tifs>;
 };
 
 &wkup_i2c0 {
@@ -300,148 +103,35 @@
                                bootph-pre-ram;
                        };
                };
+
+               esm: esm {
+                       compatible = "ti,tps659413-esm";
+                       bootph-pre-ram;
+               };
        };
 };
 
-&wkup_vtm0 {
-       vdd-supply-2 = <&buck12_reg>;
+&wkup_uart0_pins_default {
        bootph-pre-ram;
 };
 
-&usbss0 {
-       /delete-property/ power-domains;
-       /delete-property/ assigned-clocks;
-       /delete-property/ assigned-clock-parents;
-       clocks = <&clk_19_2mhz>;
-       clock-names = "ref";
-       pinctrl-names = "default";
-       pinctrl-0 = <&main_usbss0_pins_default>;
-       ti,vbus-divider;
-};
-
-&main_i2c0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&main_i2c0_pins_default>;
-       clock-frequency = <400000>;
-
-       exp1: gpio@20 {
-               compatible = "ti,tca6416";
-               reg = <0x20>;
-               gpio-controller;
-               #gpio-cells = <2>;
-       };
-
-       exp2: gpio@22 {
-               compatible = "ti,tca6424";
-               reg = <0x22>;
-               gpio-controller;
-               #gpio-cells = <2>;
-       };
+&mcu_uart0_pins_default {
+       bootph-pre-ram;
 };
 
-&hbmc {
-       status = "okay";
-       pinctrl-names = "default";
-       pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
-       reg = <0x0 0x47040000 0x0 0x100>,
-               <0x0 0x50000000 0x0 0x8000000>;
-       ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
-                <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
-
-       flash@0,0 {
-               compatible = "cypress,hyperflash", "cfi-flash";
-               reg = <0x0 0x0 0x4000000>;
-       };
+&wkup_vtm0 {
+       vdd-supply-2 = <&buck12_reg>;
+       bootph-pre-ram;
 };
 
 &ospi0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-
+       /* Address change for data region (32-bit) */
        reg = <0x0 0x47040000 0x0 0x100>,
              <0x0 0x50000000 0x0 0x8000000>;
-
-       flash@0{
-               compatible = "jedec,spi-nor";
-               reg = <0x0>;
-               spi-tx-bus-width = <1>;
-               spi-rx-bus-width = <8>;
-               spi-max-frequency = <50000000>;
-               cdns,tshsl-ns = <60>;
-               cdns,tsd2d-ns = <60>;
-               cdns,tchsh-ns = <60>;
-               cdns,tslch-ns = <60>;
-               cdns,read-delay = <0>;
-               #address-cells = <1>;
-               #size-cells = <1>;
-       };
 };
 
 &ospi1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
-       bootph-pre-ram;
-
+       /* Address change for data region (32-bit) */
        reg = <0x0 0x47050000 0x0 0x100>,
              <0x0 0x58000000 0x0 0x8000000>;
-
-       flash@0{
-               compatible = "jedec,spi-nor";
-               reg = <0x0>;
-               spi-tx-bus-width = <1>;
-               spi-rx-bus-width = <4>;
-               spi-max-frequency = <40000000>;
-               cdns,tshsl-ns = <60>;
-               cdns,tsd2d-ns = <60>;
-               cdns,tchsh-ns = <60>;
-               cdns,tslch-ns = <60>;
-               cdns,read-delay = <2>;
-               #address-cells = <1>;
-               #size-cells = <1>;
-               bootph-pre-ram;
-       };
-};
-
-&mcu_ringacc {
-       ti,sci = <&dm_tifs>;
-};
-
-&mcu_udmap {
-       ti,sci = <&dm_tifs>;
-};
-
-&wiz0_pll1_refclk {
-       assigned-clocks = <&wiz0_pll1_refclk>;
-       assigned-clock-parents = <&cmn_refclk1>;
-};
-
-&wiz0_refclk_dig {
-       assigned-clocks = <&wiz0_refclk_dig>;
-       assigned-clock-parents = <&cmn_refclk1>;
-};
-
-&serdes0 {
-       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
-       assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
-
-       serdes0_pcie_link: link@0 {
-               reg = <0>;
-               cdns,num-lanes = <1>;
-               #phy-cells = <0>;
-               cdns,phy-type = <PHY_TYPE_PCIE>;
-               resets = <&serdes_wiz0 1>;
-       };
-
-       serdes0_qsgmii_link: phy@1 {
-               reg = <1>;
-               cdns,num-lanes = <1>;
-               #phy-cells = <0>;
-               cdns,phy-type = <PHY_TYPE_QSGMII>;
-               resets = <&serdes_wiz0 2>;
-       };
-};
-
-/* EEPROM might be read before SYSFW is available */
-&wkup_i2c0 {
-       /delete-property/ power-domains;
 };

diff --git a/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi
deleted file mode 100644 (file)
index 733d69c..0000000
--- a/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include "k3-j721e-sk-u-boot.dtsi"
-
-/ {
-       chosen {
-               firmware-loader = &fs_loader0;
-       };
-
-       aliases {
-               remoteproc0 = &sysctrler;
-               remoteproc1 = &a72_0;
-               remoteproc2 = &main_r5fss0_core0;
-               remoteproc3 = &main_r5fss0_core1;
-       };
-
-       fs_loader0: fs_loader@0 {
-               bootph-all;
-               compatible = "u-boot,fs-loader";
-       };
-};
-
-&tps659412 {
-       esm: esm {
-               compatible = "ti,tps659413-esm";
-               bootph-pre-ram;
-       };
-};

diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts
index 6986292..b0c108e 100644 (file)
--- a/arch/arm/dts/k3-j721e-r5-sk.dts
+++ b/arch/arm/dts/k3-j721e-r5-sk.dts
@@ -5,156 +5,21 @@
 
 /dts-v1/;
 
-#include "k3-j721e.dtsi"
+#include "k3-j721e-sk.dts"
 #include "k3-j721e-ddr-sk-lp4-4266.dtsi"
 #include "k3-j721e-ddr.dtsi"
+#include "k3-j721e-sk-u-boot.dtsi"
 
 / {
-       model = "Texas Instruments J721E SK R5";
+       chosen {
+               tick-timer = &mcu_timer0;
+       };
 
        aliases {
                remoteproc0 = &sysctrler;
                remoteproc1 = &a72_0;
        };
 
-       chosen {
-               stdout-path = "serial2:115200n8";
-               tick-timer = &timer1;
-       };
-
-       memory@80000000 {
-               device_type = "memory";
-               /* 4G RAM */
-               reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
-                     <0x00000008 0x80000000 0x00000000 0x80000000>;
-       };
-
-       reserved_memory: reserved-memory {
-               #address-cells = <2>;
-               #size-cells = <2>;
-               ranges;
-
-               secure_ddr: optee@9e800000 {
-                       reg = <0x00 0x9e800000 0x00 0x01800000>;
-                       alignment = <0x1000>;
-                       no-map;
-               };
-
-               mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa0000000 0x00 0x100000>;
-                       no-map;
-               };
-
-               mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa0100000 0x00 0xf00000>;
-                       no-map;
-               };
-
-               mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa1000000 0x00 0x100000>;
-                       no-map;
-               };
-
-               mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa1100000 0x00 0xf00000>;
-                       no-map;
-               };
-
-               main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa2000000 0x00 0x100000>;
-                       no-map;
-               };
-
-               main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa2100000 0x00 0xf00000>;
-                       no-map;
-               };
-
-               main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa3000000 0x00 0x100000>;
-                       no-map;
-               };
-
-               main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa3100000 0x00 0xf00000>;
-                       no-map;
-               };
-
-               main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa4000000 0x00 0x100000>;
-                       no-map;
-               };
-
-               main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa4100000 0x00 0xf00000>;
-                       no-map;
-               };
-
-               main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa5000000 0x00 0x100000>;
-                       no-map;
-               };
-
-               main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa5100000 0x00 0xf00000>;
-                       no-map;
-               };
-
-               c66_1_dma_memory_region: c66-dma-memory@a6000000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa6000000 0x00 0x100000>;
-                       no-map;
-               };
-
-               c66_0_memory_region: c66-memory@a6100000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa6100000 0x00 0xf00000>;
-                       no-map;
-               };
-
-               c66_0_dma_memory_region: c66-dma-memory@a7000000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa7000000 0x00 0x100000>;
-                       no-map;
-               };
-
-               c66_1_memory_region: c66-memory@a7100000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa7100000 0x00 0xf00000>;
-                       no-map;
-               };
-
-               c71_0_dma_memory_region: c71-dma-memory@a8000000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa8000000 0x00 0x100000>;
-                       no-map;
-               };
-
-               c71_0_memory_region: c71-memory@a8100000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa8100000 0x00 0xf00000>;
-                       no-map;
-               };
-
-               rtos_ipc_memory_region: ipc-memories@aa000000 {
-                       reg = <0x00 0xaa000000 0x00 0x01c00000>;
-                       alignment = <0x1000>;
-                       no-map;
-               };
-       };
-
        a72_0: a72@0 {
                compatible = "ti,am654-rproc";
                reg = <0x0 0x00a90000 0x0 0x10>;
@@ -171,233 +36,57 @@
                bootph-pre-ram;
        };
 
-       clk_200mhz: dummy_clock_200mhz {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <200000000>;
-               bootph-pre-ram;
-       };
-
-       clk_19_2mhz: dummy_clock_19_2mhz {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <19200000>;
-               bootph-pre-ram;
-       };
-};
-
-&cbass_mcu_wakeup {
-       mcu_secproxy: secproxy@28380000 {
-               bootph-pre-ram;
-               compatible = "ti,am654-secure-proxy";
-               reg = <0x0 0x2a380000 0x0 0x80000>,
-                     <0x0 0x2a400000 0x0 0x80000>,
-                     <0x0 0x2a480000 0x0 0x80000>;
-               reg-names = "rt", "scfg", "target_data";
-               #mbox-cells = <1>;
-       };
-
-       sysctrler: sysctrler {
-               bootph-pre-ram;
-               compatible = "ti,am654-system-controller";
-               mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
-               mbox-names = "tx", "rx";
-       };
-
-       wkup_vtm0: wkup_vtm@42040000 {
-               compatible = "ti,am654-vtm", "ti,j721e-avs";
-               reg = <0x0 0x42040000 0x0 0x330>;
-               power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
-               #thermal-sensor-cells = <1>;
-       };
-
        dm_tifs: dm-tifs {
                compatible = "ti,j721e-dm-sci";
                ti,host-id = <3>;
                ti,secure-host;
                mbox-names = "rx", "tx";
-               mboxes= <&mcu_secproxy 21>,
-                               <&mcu_secproxy 23>;
+               mboxes= <&secure_proxy_mcu 21>,
+                               <&secure_proxy_mcu 23>;
                bootph-pre-ram;
        };
 };
 
-&cbass_main {
-       main_esm: esm@700000 {
-               compatible = "ti,j721e-esm";
-               reg = <0x0 0x700000 0x0 0x1000>;
-               ti,esm-pins = <344>, <345>;
+&mcu_timer0 {
+       status = "okay";
+       bootph-pre-ram;
+};
+
+&secure_proxy_mcu {
+       bootph-pre-ram;
+       status = "okay";
+};
+
+&cbass_mcu_wakeup {
+       sysctrler: sysctrler {
                bootph-pre-ram;
+               compatible = "ti,am654-system-controller";
+               mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
+               mbox-names = "tx", "rx";
        };
 };
 
 &dmsc {
-       mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+       mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
        mbox-names = "tx", "rx", "notify";
        ti,host-id = <4>;
        ti,secure-host;
 };
 
-&wkup_pmx0 {
-       wkup_uart0_pins_default: wkup_uart0_pins_default {
-               bootph-pre-ram;
-               pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
-                       J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
-               >;
-       };
-
-       mcu_uart0_pins_default: mcu_uart0_pins_default {
-               bootph-pre-ram;
-               pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */
-                       J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
-                       J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
-                       J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
-               >;
-       };
-
-       wkup_i2c0_pins_default: wkup-i2c0-pins-default {
-               pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
-                       J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
-               >;
-       };
-
-       mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
-               pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
-                       J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
-                       J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
-                       J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
-                       J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
-                       J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
-                       J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
-                       J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
-                       J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
-                       J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
-                       J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
-               >;
-       };
-
-       mcu_i2c0_pins_default: mcu_i2c0_pins_default {
-               pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (J26) MCU_I2C0_SCL */
-                       J721E_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H25) MCU_I2C0_SDA */
-               >;
-       };
+&mcu_ringacc {
+       ti,sci = <&dm_tifs>;
 };
 
-&main_pmx0 {
-       main_uart0_pins_default: main_uart0_pins_default {
-               bootph-pre-ram;
-               pinctrl-single,pins = <
-                       J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
-                       J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
-                       J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
-                       J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
-               >;
-       };
-
-       main_usbss0_pins_default: main_usbss0_pins_default {
-               pinctrl-single,pins = <
-                       J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
-                       J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
-               >;
-       };
-
-       main_usbss1_pins_default: main-usbss1-pins-default {
-               pinctrl-single,pins = <
-                       J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
-               >;
-       };
-
-       main_mmc1_pins_default: main_mmc1_pins_default {
-               pinctrl-single,pins = <
-                       J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
-                       J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
-                       J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
-                       J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
-                       J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
-                       J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
-                       J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
-                       J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
-               >;
-       };
-
-       main_i2c0_pins_default: main-i2c0-pins-default {
-               pinctrl-single,pins = <
-                       J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
-                       J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
-               >;
-       };
-
-       main_i2c1_pins_default: main-i2c1-pins-default {
-               pinctrl-single,pins = <
-                       J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
-                       J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
-               >;
-       };
-
-       main_i2c2_pins_default: main-i2c2-pins-default {
-               pinctrl-single,pins = <
-                       J721E_IOPAD(0x158, PIN_INPUT_PULLUP, 2) /* (U23) RGMII5_TX_CTL.I2C2_SCL */
-                       J721E_IOPAD(0x15c, PIN_INPUT_PULLUP, 2) /* (U26) RGMII5_RX_CTL.I2C2_SDA */
-               >;
-       };
-
-       main_i2c3_pins_default: main-i2c3-pins-default {
-               pinctrl-single,pins = <
-                       J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
-                       J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
-               >;
-       };
-
-       main_i2c5_pins_default: main-i2c5-pins-default {
-               pinctrl-single,pins = <
-                       J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
-                       J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
-               >;
-       };
+&mcu_udmap {
+       ti,sci = <&dm_tifs>;
 };
 
-&wkup_uart0 {
+&wkup_uart0_pins_default {
        bootph-pre-ram;
-       pinctrl-names = "default";
-       pinctrl-0 = <&wkup_uart0_pins_default>;
-       status = "okay";
-};
-
-&mcu_uart0 {
-       /delete-property/ power-domains;
-       /delete-property/ clocks;
-       /delete-property/ clock-names;
-       pinctrl-names = "default";
-       pinctrl-0 = <&mcu_uart0_pins_default>;
-       status = "okay";
-       clock-frequency = <48000000>;
 };
 
-&main_uart0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&main_uart0_pins_default>;
-       status = "okay";
-       power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
-};
-
-&main_sdhci0 {
-       status = "disabled";
-};
-
-&main_sdhci1 {
-       /delete-property/ power-domains;
-       /delete-property/ assigned-clocks;
-       /delete-property/ assigned-clock-parents;
-       pinctrl-names = "default";
-       pinctrl-0 = <&main_mmc1_pins_default>;
-       clock-names = "clk_xin";
-       clocks = <&clk_200mhz>;
-       ti,driver-strength-ohm = <50>;
+&mcu_uart0_pins_default {
+       bootph-pre-ram;
 };
 
 &wkup_i2c0 {
@@ -423,6 +112,11 @@
                                bootph-pre-ram;
                        };
                };
+
+               esm: esm {
+                       compatible = "ti,tps659413-esm";
+                       bootph-pre-ram;
+               };
        };
 };
 
@@ -431,217 +125,8 @@
        bootph-pre-ram;
 };
 
-&usbss0 {
-       /delete-property/ power-domains;
-       /delete-property/ assigned-clocks;
-       /delete-property/ assigned-clock-parents;
-       clocks = <&clk_19_2mhz>;
-       clock-names = "usb2_refclk";
-       pinctrl-names = "default";
-       pinctrl-0 = <&main_usbss0_pins_default>;
-       ti,vbus-divider;
-};
-
-&usbss1 {
-       /delete-property/ power-domains;
-       /delete-property/ assigned-clocks;
-       /delete-property/ assigned-clock-parents;
-       clocks = <&clk_19_2mhz>;
-       clock-names = "usb2_refclk";
-       pinctrl-names = "default";
-       pinctrl-0 = <&main_usbss1_pins_default>;
-};
-
-&main_i2c0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&main_i2c0_pins_default>;
-       clock-frequency = <400000>;
-};
-
 &ospi0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-
+       /* Address change for data region (32-bit) */
        reg = <0x0 0x47040000 0x0 0x100>,
              <0x0 0x50000000 0x0 0x8000000>;
-
-       flash@0{
-               compatible = "jedec,spi-nor";
-               reg = <0x0>;
-               spi-tx-bus-width = <8>;
-               spi-rx-bus-width = <8>;
-               spi-max-frequency = <25000000>;
-               cdns,tshsl-ns = <60>;
-               cdns,tsd2d-ns = <60>;
-               cdns,tchsh-ns = <60>;
-               cdns,tslch-ns = <60>;
-               cdns,read-delay = <4>;
-               cdns,phy-mode;
-               #address-cells = <1>;
-               #size-cells = <1>;
-       };
-};
-
-&ospi1 {
-       status = "disabled";
-};
-
-&mcu_ringacc {
-       ti,sci = <&dm_tifs>;
-};
-
-&mcu_udmap {
-       ti,sci = <&dm_tifs>;
-};
-
-&mailbox0_cluster0 {
-       interrupts = <436>;
-
-       mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
-               ti,mbox-rx = <0 0 0>;
-               ti,mbox-tx = <1 0 0>;
-       };
-
-       mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
-               ti,mbox-rx = <2 0 0>;
-               ti,mbox-tx = <3 0 0>;
-       };
-};
-
-&mailbox0_cluster1 {
-       interrupts = <432>;
-
-       mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
-               ti,mbox-rx = <0 0 0>;
-               ti,mbox-tx = <1 0 0>;
-       };
-
-       mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
-               ti,mbox-rx = <2 0 0>;
-               ti,mbox-tx = <3 0 0>;
-       };
-};
-
-&mailbox0_cluster2 {
-       interrupts = <428>;
-
-       mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
-               ti,mbox-rx = <0 0 0>;
-               ti,mbox-tx = <1 0 0>;
-       };
-
-       mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
-               ti,mbox-rx = <2 0 0>;
-               ti,mbox-tx = <3 0 0>;
-       };
-};
-
-&mailbox0_cluster3 {
-       interrupts = <424>;
-
-       mbox_c66_0: mbox-c66-0 {
-               ti,mbox-rx = <0 0 0>;
-               ti,mbox-tx = <1 0 0>;
-       };
-
-       mbox_c66_1: mbox-c66-1 {
-               ti,mbox-rx = <2 0 0>;
-               ti,mbox-tx = <3 0 0>;
-       };
-};
-
-&mailbox0_cluster4 {
-       interrupts = <420>;
-
-       mbox_c71_0: mbox-c71-0 {
-               ti,mbox-rx = <0 0 0>;
-               ti,mbox-tx = <1 0 0>;
-       };
-};
-
-&mailbox0_cluster5 {
-       status = "disabled";
-};
-
-&mailbox0_cluster6 {
-       status = "disabled";
-};
-
-&mailbox0_cluster7 {
-       status = "disabled";
-};
-
-&mailbox0_cluster8 {
-       status = "disabled";
-};
-
-&mailbox0_cluster9 {
-       status = "disabled";
-};
-
-&mailbox0_cluster10 {
-       status = "disabled";
-};
-
-&mailbox0_cluster11 {
-       status = "disabled";
-};
-
-&mcu_r5fss0_core0 {
-       mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
-       memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
-                       <&mcu_r5fss0_core0_memory_region>;
-};
-
-&mcu_r5fss0_core1 {
-       mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
-       memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
-                       <&mcu_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss0_core0 {
-       mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
-       memory-region = <&main_r5fss0_core0_dma_memory_region>,
-                       <&main_r5fss0_core0_memory_region>;
-};
-
-&main_r5fss0_core1 {
-       mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
-       memory-region = <&main_r5fss0_core1_dma_memory_region>,
-                       <&main_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss1_core0 {
-       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
-       memory-region = <&main_r5fss1_core0_dma_memory_region>,
-                       <&main_r5fss1_core0_memory_region>;
-};
-
-&main_r5fss1_core1 {
-       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
-       memory-region = <&main_r5fss1_core1_dma_memory_region>,
-                       <&main_r5fss1_core1_memory_region>;
-};
-
-&c66_0 {
-       mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
-       memory-region = <&c66_0_dma_memory_region>,
-                       <&c66_0_memory_region>;
-};
-
-&c66_1 {
-       mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
-       memory-region = <&c66_1_dma_memory_region>,
-                       <&c66_1_memory_region>;
-};
-
-&c71_0 {
-       mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
-       memory-region = <&c71_0_dma_memory_region>,
-                       <&c71_0_memory_region>;
-};
-
-/* EEPROM might be read before SYSFW is available */
-&wkup_i2c0 {
-       /delete-property/ power-domains;
 };

diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
index 205dacf..57da7c2 100644 (file)
--- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
@@ -3,82 +3,42 @@
  * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
  */
 
-#include <dt-bindings/net/ti-dp83867.h>
 #include "k3-j721e-binman.dtsi"
 
-/ {
-       chosen {
-               stdout-path = "serial2:115200n8";
-               tick-timer = &timer1;
-       };
-
-       aliases {
-               ethernet0 = &cpsw_port1;
-               spi0 = &ospi0;
-               remoteproc0 = &mcu_r5fss0_core0;
-               remoteproc1 = &mcu_r5fss0_core1;
-               remoteproc2 = &main_r5fss0_core0;
-               remoteproc3 = &main_r5fss0_core1;
-               remoteproc4 = &main_r5fss1_core0;
-               remoteproc5 = &main_r5fss1_core1;
-               remoteproc6 = &c66_0;
-               remoteproc7 = &c66_1;
-               remoteproc8 = &c71_0;
-               i2c0 = &wkup_i2c0;
-               i2c1 = &mcu_i2c0;
-               i2c2 = &main_i2c0;
-               mmc1 = &main_sdhci1;  /* SD Card */
-       };
+&cbass_main {
+       bootph-pre-ram;
 };
 
-&cbass_main{
+&main_navss {
        bootph-pre-ram;
-
-       main_navss: bus@30000000 {
-               bootph-pre-ram;
-       };
 };
 
 &cbass_mcu_wakeup {
        bootph-pre-ram;
 
-       timer1: timer@40400000 {
-               compatible = "ti,omap5430-timer";
-               reg = <0x0 0x40400000 0x0 0x80>;
-               ti,timer-alwon;
-               clock-frequency = <25000000>;
+       chipid@43000014 {
                bootph-pre-ram;
        };
+};
 
-       mcu_navss: bus@28380000 {
-               bootph-pre-ram;
-
-               ringacc@2b800000 {
-                       reg =   <0x0 0x2b800000 0x0 0x400000>,
-                               <0x0 0x2b000000 0x0 0x400000>,
-                               <0x0 0x28590000 0x0 0x100>,
-                               <0x0 0x2a500000 0x0 0x40000>,
-                               <0x0 0x28440000 0x0 0x40000>;
-                       reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
-                       bootph-pre-ram;
-               };
+&mcu_navss {
+       bootph-pre-ram;
+};
 
-               dma-controller@285c0000 {
-                       reg =   <0x0 0x285c0000 0x0 0x100>,
-                               <0x0 0x284c0000 0x0 0x4000>,
-                               <0x0 0x2a800000 0x0 0x40000>,
-                               <0x0 0x284a0000 0x0 0x4000>,
-                               <0x0 0x2aa00000 0x0 0x40000>,
-                               <0x0 0x28400000 0x0 0x2000>;
-                       reg-names = "gcfg", "rchan", "rchanrt", "tchan",
-                                           "tchanrt", "rflow";
-                       bootph-pre-ram;
-               };
-       };
+&mcu_ringacc {
+               bootph-pre-ram;
+};
 
-       chipid@43000014 {
+&mcu_udmap {
+       reg =   <0x0 0x285c0000 0x0 0x100>,
+               <0x0 0x284c0000 0x0 0x4000>,
+               <0x0 0x2a800000 0x0 0x40000>,
+               <0x0 0x284a0000 0x0 0x4000>,
+               <0x0 0x2aa00000 0x0 0x40000>,
+               <0x0 0x28400000 0x0 0x2000>;
+               reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+                           "tchanrt", "rflow";
                bootph-pre-ram;
-       };
 };
 
 &secure_proxy_main {
@@ -121,17 +81,12 @@
        bootph-pre-ram;
 };
 
-&main_sdhci0 {
-       status = "disabled";
-};
-
 &main_sdhci1 {
        bootph-pre-ram;
 };
 
-&wiz3_pll1_refclk {
-       assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
-       assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
+&main_uart0_pins_default {
+       bootph-pre-ram;
 };
 
 &main_usbss0_pins_default {
@@ -147,11 +102,6 @@
        bootph-pre-ram;
 };
 
-&wiz2_pll1_refclk {
-       assigned-clocks = <&wiz2_pll1_refclk>, <&wiz2_pll0_refclk>;
-       assigned-clock-parents = <&k3_clks 294 0>, <&k3_clks 294 11>;
-};
-
 &main_usbss1_pins_default {
        bootph-pre-ram;
 };
@@ -165,19 +115,6 @@
        bootph-pre-ram;
 };
 
-&mcu_cpsw {
-       reg = <0x0 0x46000000 0x0 0x200000>,
-             <0x0 0x40f00200 0x0 0x2>;
-       reg-names = "cpsw_nuss", "mac_efuse";
-       /delete-property/ ranges;
-
-       cpsw-phy-sel@40f04040 {
-               compatible = "ti,am654-cpsw-phy-sel";
-               reg= <0x0 0x40f04040 0x0 0x4>;
-               reg-names = "gmii-sel";
-       };
-};
-
 &main_mmc1_pins_default {
        bootph-pre-ram;
 };
@@ -190,44 +127,9 @@
        bootph-pre-ram;
 };
 
-&mcu_i2c0 {
-       bootph-pre-ram;
-};
-
-&mcu_i2c1 {
-       status = "disabled";
-};
-
-&main_i2c0 {
-       status = "disabled";
-};
-
-&main_i2c1 {
-       status = "disabled";
-};
-
-&main_i2c2 {
-       status = "disabled";
-};
-
-&main_i2c3 {
-       status = "disabled";
-};
-
-&main_i2c4 {
-       status = "disabled";
-};
-
-&main_i2c5 {
-       status = "disabled";
-};
-
-&main_i2c6 {
-       status = "disabled";
-};
-
-&mcu_i2c0_pins_default {
+&wkup_uart0 {
        bootph-pre-ram;
+       status = "okay";
 };
 
 &mcu_fss0_ospi0_pins_default {
@@ -238,8 +140,8 @@
        bootph-pre-ram;
 };
 
-&hbmc {
-       status = "disabled";
+&main_esm {
+       bootph-pre-ram;
 };
 
 &ospi0 {
@@ -249,37 +151,7 @@
                bootph-pre-ram;
 
                partition@3fc0000 {
-                       label = "ospi.phypattern";
-                       reg = <0x3fc0000 0x40000>;
                        bootph-pre-ram;
                };
        };
 };
-
-&serdes_ln_ctrl {
-       u-boot,mux-autoprobe;
-};
-
-&usb_serdes_mux {
-       u-boot,mux-autoprobe;
-};
-
-&pcie0_rc {
-       status = "disabled";
-};
-
-&pcie1_rc {
-       status = "disabled";
-};
-
-&pcie0_ep {
-       status = "disabled";
-};
-
-&pcie1_ep {
-       status = "disabled";
-};
-
-&dss {
-       status = "disabled";
-};

diff --git a/arch/arm/dts/k3-j721e-sk.dts b/arch/arm/dts/k3-j721e-sk.dts
index 4443cd0..42fe8ee 100644 (file)
--- a/arch/arm/dts/k3-j721e-sk.dts
+++ b/arch/arm/dts/k3-j721e-sk.dts
@@ -1,6 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM
  */
 
 /dts-v1/;
@@ -12,11 +14,19 @@
 
 / {
        compatible = "ti,j721e-sk", "ti,j721e";
-       model = "Texas Instruments J721E SK A72";
+       model = "Texas Instruments J721E SK";
+
+       aliases {
+               serial0 = &wkup_uart0;
+               serial1 = &mcu_uart0;
+               serial2 = &main_uart0;
+               serial3 = &main_uart1;
+               ethernet0 = &cpsw_port1;
+               mmc1 = &main_sdhci1;
+       };
 
        chosen {
                stdout-path = "serial2:115200n8";
-               bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
        };
 
        memory@80000000 {
@@ -195,14 +205,91 @@
                regulator-max-microvolt = <3300000>;
                regulator-boot-on;
                vin-supply = <&vsys_3v3>;
-               gpios = <&wkup_gpio0 9 GPIO_ACTIVE_LOW>;
-               states = <3300000 0x0>,
-                        <1800000 0x1>;
+               gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>;
+               states = <1800000 0x0>,
+                        <3300000 0x1>;
+       };
+
+       dp_pwr_3v3: fixedregulator-dp-prw {
+               compatible = "regulator-fixed";
+               regulator-name = "dp-pwr";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&dp_pwr_en_pins_default>;
+               gpio = <&main_gpio0 111 0>;     /* DP0_3V3 _EN */
+               enable-active-high;
+       };
+
+       dp0: connector {
+               compatible = "dp-connector";
+               label = "DP0";
+               type = "full-size";
+               dp-pwr-supply = <&dp_pwr_3v3>;
+
+               port {
+                       dp_connector_in: endpoint {
+                               remote-endpoint = <&dp0_out>;
+                       };
+               };
+       };
+
+       hdmi-connector {
+               compatible = "hdmi-connector";
+               label = "hdmi";
+               type = "a";
+
+               pinctrl-names = "default";
+               pinctrl-0 = <&hdmi_hpd_pins_default>;
+
+               ddc-i2c-bus = <&main_i2c1>;
+
+               /* HDMI_HPD */
+               hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>;
+
+               port {
+                       hdmi_connector_in: endpoint {
+                               remote-endpoint = <&tfp410_out>;
+                       };
+               };
+       };
+
+       dvi-bridge {
+               compatible = "ti,tfp410";
+
+               pinctrl-names = "default";
+               pinctrl-0 = <&hdmi_pdn_pins_default>;
+
+               powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>;
+               ti,deskew = <0>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+
+                               tfp410_in: endpoint {
+                                       remote-endpoint = <&dpi1_out>;
+                                       pclk-sample = <1>;
+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+
+                               tfp410_out: endpoint {
+                                       remote-endpoint =
+                                               <&hdmi_connector_in>;
+                               };
+                       };
+               };
        };
 };
 
 &main_pmx0 {
-       main_mmc1_pins_default: main-mmc1-pins-default {
+       main_mmc1_pins_default: main-mmc1-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
                        J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
@@ -215,7 +302,7 @@
                >;
        };
 
-       main_uart0_pins_default: main-uart0-pins-default {
+       main_uart0_pins_default: main-uart0-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
                        J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
@@ -224,50 +311,155 @@
                >;
        };
 
-       main_i2c0_pins_default: main-i2c0-pins-default {
+       main_uart1_pins_default: main-uart1-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */
+                       J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */
+               >;
+       };
+
+       main_i2c0_pins_default: main-i2c0-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
                        J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
                >;
        };
 
-       main_i2c1_pins_default: main-i2c1-pins-default {
+       main_i2c1_pins_default: main-i2c1-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
                        J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
                >;
        };
 
-       main_i2c3_pins_default: main-i2c3-pins-default {
+       main_i2c3_pins_default: main-i2c3-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
                        J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
                >;
        };
 
-       mcu_i2c0_pins_default: mcu-i2c0-pins-default {
+       main_usbss0_pins_default: main-usbss0-default-pins {
                pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (J26) MCU_I2C0_SCL */
-                       J721E_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H25) MCU_I2C0_SDA */
+                       J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+                       J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
                >;
        };
 
-       main_usbss0_pins_default: main-usbss0-pins-default {
+       main_usbss1_pins_default: main-usbss1-default-pins {
                pinctrl-single,pins = <
-                       J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
-                       J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+                       J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
                >;
        };
 
-       main_usbss1_pins_default: main-usbss1-pins-default {
+       dp0_pins_default: dp0-default-pins {
                pinctrl-single,pins = <
-                       J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
+                       J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
+               >;
+       };
+
+       dp_pwr_en_pins_default: dp-pwr-en-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
+               >;
+       };
+
+       dss_vout0_pins_default: dss-vout0-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */
+                       J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */
+                       J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */
+                       J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */
+                       J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */
+                       J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */
+                       J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */
+                       J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */
+                       J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */
+                       J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */
+                       J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */
+                       J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */
+                       J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */
+                       J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */
+                       J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */
+                       J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */
+                       J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */
+                       J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */
+                       J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */
+                       J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */
+                       J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */
+                       J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */
+                       J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */
+                       J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */
+                       J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */
+                       J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */
+                       J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */
+                       J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */
+               >;
+       };
+
+       hdmi_hpd_pins_default: hdmi-hpd-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */
+               >;
+       };
+
+       hdmi_pdn_pins_default: hdmi-pdn-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
+               >;
+       };
+
+       /* Reset for M.2 E Key slot on PCIe0  */
+       ekey_reset_pins_default: ekey-reset-pns-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */
+               >;
+       };
+
+       main_i2c5_pins_default: main-i2c5-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
+                       J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
+               >;
+       };
+
+       rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
+                       J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */
+                       J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
+                       J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
+                       J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
+                       J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
+                       J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
+                       J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */
+                       J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
+                       J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
+                       J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */
+                       J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */
+                       J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */
+                       J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */
+                       J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
+                       J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
+                       J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
+                       J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
+                       J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */
+                       J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */
+                       J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
+                       J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */
+                       J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
+               >;
+       };
+
+       rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */
                >;
        };
 };
 
 &wkup_pmx0 {
-       mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+       mcu_cpsw_pins_default: mcu-cpsw-default-pins {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
                        J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
@@ -284,14 +476,14 @@
                >;
        };
 
-       mcu_mdio_pins_default: mcu-mdio1-pins-default {
+       mcu_mdio_pins_default: mcu-mdio1-default-pins {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
                        J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
                >;
        };
 
-       mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+       mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
                        J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
@@ -307,80 +499,92 @@
                >;
        };
 
-       vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default {
+       vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */
                >;
        };
 
-       vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
+       vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */
                >;
        };
 
-       wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+       wkup_uart0_pins_default: wkup-uart0-default-pins {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
+                       J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
+               >;
+       };
+
+       mcu_uart0_pins_default: mcu-uart0-default-pins {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */
+                       J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
+                       J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
+                       J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
+               >;
+       };
+
+       wkup_i2c0_pins_default: wkup-i2c0-default-pins {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
                        J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
                >;
        };
+
+       /* Reset for M.2 M Key slot on PCIe1  */
+       mkey_reset_pins_default: mkey-reset-pns-default-pins {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */
+               >;
+       };
 };
 
 &wkup_uart0 {
        /* Wakeup UART is used by System firmware */
        status = "reserved";
-};
-
-&main_uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&main_uart0_pins_default>;
-       /* Shared with ATF on this platform */
-       power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
-};
-
-&main_uart2 {
-       /* Brought out on RPi header */
-       status = "disabled";
+       pinctrl-0 = <&wkup_uart0_pins_default>;
 };
 
-&main_uart3 {
-       /* UART not brought out */
-       status = "disabled";
-};
-
-&main_uart5 {
-       /* UART not brought out */
-       status = "disabled";
-};
-
-&main_uart6 {
-       /* UART not brought out */
-       status = "disabled";
-};
+&wkup_i2c0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&wkup_i2c0_pins_default>;
+       clock-frequency = <400000>;
 
-&main_uart7 {
-       /* UART not brought out */
-       status = "disabled";
+       eeprom@51 {
+               /* AT24C512C-MAHM-T */
+               compatible = "atmel,24c512";
+               reg = <0x51>;
+       };
 };
 
-&main_uart8 {
-       /* UART not brought out */
-       status = "disabled";
+&mcu_uart0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcu_uart0_pins_default>;
 };
 
-&main_uart9 {
-       /* Brought out on M.2 E Key */
-       status = "disabled";
+&main_uart0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_uart0_pins_default>;
+       /* Shared with ATF on this platform */
+       power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
 };
 
-&main_sdhci0 {
-       /* Unused */
-       status = "disabled";
+&main_uart1 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_uart1_pins_default>;
 };
 
 &main_sdhci1 {
        /* SD Card */
+       status = "okay";
        vmmc-supply = <&vdd_mmc1>;
        vqmmc-supply = <&vdd_sd_dv_alt>;
        pinctrl-names = "default";
@@ -389,16 +593,12 @@
        disable-wp;
 };
 
-&main_sdhci2 {
-       /* Unused */
-       status = "disabled";
-};
-
 &ospi0 {
+       status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
 
-       flash@0{
+       flash@0 {
                compatible = "jedec,spi-nor";
                reg = <0x0>;
                spi-tx-bus-width = <8>;
@@ -409,55 +609,141 @@
                cdns,tchsh-ns = <60>;
                cdns,tslch-ns = <60>;
                cdns,read-delay = <4>;
-               cdns,phy-mode;
-               cdns,phy-tx-start = <18>;
-               #address-cells = <1>;
-               #size-cells = <1>;
-       };
-};
 
-&ospi1 {
-       /* Unused */
-       status = "disabled";
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "ospi.tiboot3";
+                               reg = <0x0 0x80000>;
+                       };
+
+                       partition@80000 {
+                               label = "ospi.tispl";
+                               reg = <0x80000 0x200000>;
+                       };
+
+                       partition@280000 {
+                               label = "ospi.u-boot";
+                               reg = <0x280000 0x400000>;
+                       };
+
+                       partition@680000 {
+                               label = "ospi.env";
+                               reg = <0x680000 0x40000>;
+                       };
+
+                       partition@6c0000 {
+                               label = "ospi.sysfw";
+                               reg = <0x6c0000 0x100000>;
+                       };
+
+                       partition@7c0000 {
+                               label = "ospi.env.backup";
+                               reg = <0x7c0000 0x40000>;
+                       };
+
+                       partition@800000 {
+                               label = "ospi.rootfs";
+                               reg = <0x800000 0x37c0000>;
+                       };
+
+                       partition@3fc0000 {
+                               label = "ospi.phypattern";
+                               reg = <0x3fc0000 0x40000>;
+                       };
+               };
+       };
 };
 
 &main_i2c0 {
+       status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&main_i2c0_pins_default>;
        clock-frequency = <400000>;
+
+       i2c-mux@71 {
+               compatible = "nxp,pca9543";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0x71>;
+
+               /* PCIe1 M.2 M Key I2C */
+               i2c@0 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0>;
+               };
+
+               /* PCIe0 M.2 E Key I2C */
+               i2c@1 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <1>;
+               };
+       };
 };
 
 &main_i2c1 {
+       status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&main_i2c1_pins_default>;
-       clock-frequency = <400000>;
+       /* i2c1 is used for DVI DDC, so we need to use 100kHz */
+       clock-frequency = <100000>;
 };
 
 &main_i2c3 {
+       status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&main_i2c3_pins_default>;
        clock-frequency = <400000>;
-};
 
-&main_i2c4 {
-       /* Unused */
-       status = "disabled";
+       i2c-mux@70 {
+               compatible = "nxp,pca9543";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0x70>;
+
+               /* CSI0 I2C */
+               i2c@0 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0>;
+               };
+
+               /* CSI1 I2C */
+               i2c@1 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <1>;
+               };
+       };
 };
 
 &main_i2c5 {
        /* Brought out on RPi Header */
-       status = "disabled";
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_i2c5_pins_default>;
+       clock-frequency = <400000>;
 };
 
-&main_i2c6 {
-       /* Unused */
-       status = "disabled";
+&main_gpio0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&rpi_header_gpio0_pins_default>;
 };
 
-&mcu_i2c0 {
+&main_gpio1 {
+       status = "okay";
        pinctrl-names = "default";
-       pinctrl-0 = <&mcu_i2c0_pins_default>;
-       clock-frequency = <400000>;
+       pinctrl-0 = <&rpi_header_gpio1_pins_default>;
+};
+
+&wkup_gpio0 {
+       status = "okay";
 };
 
 &usb_serdes_mux {
@@ -479,7 +765,7 @@
 };
 
 &serdes3 {
-       serdes3_usb_link: link@0 {
+       serdes3_usb_link: phy@0 {
                reg = <0>;
                cdns,num-lanes = <2>;
                #phy-cells = <0>;
@@ -488,6 +774,24 @@
        };
 };
 
+&serdes4 {
+       torrent_phy_dp: phy@0 {
+               reg = <0>;
+               resets = <&serdes_wiz4 1>;
+               cdns,phy-type = <PHY_TYPE_DP>;
+               cdns,num-lanes = <4>;
+               cdns,max-bit-rate = <5400>;
+               #phy-cells = <0>;
+       };
+};
+
+&mhdp {
+       phys = <&torrent_phy_dp>;
+       phy-names = "dpphy";
+       pinctrl-names = "default";
+       pinctrl-0 = <&dp0_pins_default>;
+};
+
 &usbss0 {
        pinctrl-names = "default";
        pinctrl-0 = <&main_usbss0_pins_default>;
@@ -502,7 +806,7 @@
 };
 
 &serdes2 {
-       serdes2_usb_link: link@1 {
+       serdes2_usb_link: phy@1 {
                reg = <1>;
                cdns,num-lanes = <1>;
                #phy-cells = <0>;
@@ -524,19 +828,9 @@
        phy-names = "cdns3,usb3-phy";
 };
 
-&tscadc0 {
-       /* Unused */
-       status = "disabled";
-};
-
-&tscadc1 {
-       /* Unused */
-       status = "disabled";
-};
-
 &mcu_cpsw {
        pinctrl-names = "default";
-       pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+       pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
 };
 
 &davinci_mdio {
@@ -553,6 +847,9 @@
 };
 
 &dss {
+       pinctrl-names = "default";
+       pinctrl-0 = <&dss_vout0_pins_default>;
+
        assigned-clocks = <&k3_clks 152 1>,     /* VP 1 pixel clock */
                          <&k3_clks 152 4>,     /* VP 2 pixel clock */
                          <&k3_clks 152 9>,     /* VP 3 pixel clock */
@@ -563,87 +860,94 @@
                                 <&k3_clks 152 18>;     /* DPI1_EXT_CLKSEL_OUT0 */
 };
 
-&mcasp0 {
-       /* Unused */
-       status = "disabled";
-};
-
-&mcasp1 {
-       /* Unused */
-       status = "disabled";
-};
+&dss_ports {
+       #address-cells = <1>;
+       #size-cells = <0>;
 
-&mcasp2 {
-       /* Unused */
-       status = "disabled";
-};
+       port@0  {
+               reg = <0>;
 
-&mcasp3 {
-       /* Unused */
-       status = "disabled";
-};
+               dpi0_out: endpoint {
+                       remote-endpoint = <&dp0_in>;
+               };
+       };
 
-&mcasp4 {
-       /* Unused */
-       status = "disabled";
-};
+       port@1 {
+               reg = <1>;
 
-&mcasp5 {
-       /* Unused */
-       status = "disabled";
+               dpi1_out: endpoint {
+                       remote-endpoint = <&tfp410_in>;
+               };
+       };
 };
 
-&mcasp6 {
-       /* Brought out on RPi header */
-       status = "disabled";
-};
+&dp0_ports {
+       #address-cells = <1>;
+       #size-cells = <0>;
 
-&mcasp7 {
-       /* Unused */
-       status = "disabled";
-};
+       port@0 {
+               reg = <0>;
+               dp0_in: endpoint {
+                       remote-endpoint = <&dpi0_out>;
+               };
+       };
 
-&mcasp8 {
-       /* Unused */
-       status = "disabled";
+       port@4 {
+               reg = <4>;
+               dp0_out: endpoint {
+                       remote-endpoint = <&dp_connector_in>;
+               };
+       };
 };
 
-&mcasp9 {
-       /* Unused */
-       status = "disabled";
+&serdes0 {
+       serdes0_pcie_link: phy@0 {
+               reg = <0>;
+               cdns,num-lanes = <1>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz0 1>;
+       };
 };
 
-&mcasp10 {
-       /* Unused */
-       status = "disabled";
+&serdes1 {
+       serdes1_pcie_link: phy@0 {
+               reg = <0>;
+               cdns,num-lanes = <2>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+       };
 };
 
-&mcasp11 {
-       /* Brought out on M.2 E Key */
-       status = "disabled";
-};
+&pcie0_rc {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&ekey_reset_pins_default>;
+       reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>;
 
-&pcie2_rc {
-       /* Unused */
-       status = "disabled";
+       phys = <&serdes0_pcie_link>;
+       phy-names = "pcie-phy";
+       num-lanes = <1>;
 };
 
-&pcie2_ep {
-       /* Unused */
-       status = "disabled";
-};
+&pcie1_rc {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&mkey_reset_pins_default>;
+       reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>;
 
-&pcie3_rc {
-       /* Unused */
-       status = "disabled";
+       phys = <&serdes1_pcie_link>;
+       phy-names = "pcie-phy";
+       num-lanes = <2>;
 };
 
-&pcie3_ep {
-       /* Unused */
+&ufs_wrapper {
        status = "disabled";
 };
 
 &mailbox0_cluster0 {
+       status = "okay";
        interrupts = <436>;
 
        mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -658,6 +962,7 @@
 };
 
 &mailbox0_cluster1 {
+       status = "okay";
        interrupts = <432>;
 
        mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
@@ -672,6 +977,7 @@
 };
 
 &mailbox0_cluster2 {
+       status = "okay";
        interrupts = <428>;
 
        mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
@@ -686,6 +992,7 @@
 };
 
 &mailbox0_cluster3 {
+       status = "okay";
        interrupts = <424>;
 
        mbox_c66_0: mbox-c66-0 {
@@ -700,6 +1007,7 @@
 };
 
 &mailbox0_cluster4 {
+       status = "okay";
        interrupts = <420>;
 
        mbox_c71_0: mbox-c71-0 {
@@ -708,84 +1016,59 @@
        };
 };
 
-&mailbox0_cluster5 {
-       status = "disabled";
-};
-
-&mailbox0_cluster6 {
-       status = "disabled";
-};
-
-&mailbox0_cluster7 {
-       status = "disabled";
-};
-
-&mailbox0_cluster8 {
-       status = "disabled";
-};
-
-&mailbox0_cluster9 {
-       status = "disabled";
-};
-
-&mailbox0_cluster10 {
-       status = "disabled";
-};
-
-&mailbox0_cluster11 {
-       status = "disabled";
-};
-
 &mcu_r5fss0_core0 {
-       mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+       mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
        memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
                        <&mcu_r5fss0_core0_memory_region>;
 };
 
 &mcu_r5fss0_core1 {
-       mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+       mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
        memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
                        <&mcu_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss0_core0 {
-       mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+       mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
        memory-region = <&main_r5fss0_core0_dma_memory_region>,
                        <&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
-       mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+       mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
        memory-region = <&main_r5fss0_core1_dma_memory_region>,
                        <&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
-       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+       mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
        memory-region = <&main_r5fss1_core0_dma_memory_region>,
                        <&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
-       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+       mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
        memory-region = <&main_r5fss1_core1_dma_memory_region>,
                        <&main_r5fss1_core1_memory_region>;
 };
 
 &c66_0 {
-       mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+       status = "okay";
+       mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
        memory-region = <&c66_0_dma_memory_region>,
                        <&c66_0_memory_region>;
 };
 
 &c66_1 {
-       mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+       status = "okay";
+       mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
        memory-region = <&c66_1_dma_memory_region>,
                        <&c66_1_memory_region>;
 };
 
 &c71_0 {
-       mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+       status = "okay";
+       mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
        memory-region = <&c71_0_dma_memory_region>,
                        <&c71_0_memory_region>;
 };

diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e-som-p0.dtsi
index a725435..7f0686c 100644 (file)
--- a/arch/arm/dts/k3-j721e-som-p0.dtsi
+++ b/arch/arm/dts/k3-j721e-som-p0.dtsi
@@ -1,6 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Product Link: https://www.ti.com/tool/J721EXSOMXEVM
  */
 
 /dts-v1/;
@@ -143,33 +145,14 @@
 };
 
 &wkup_pmx0 {
-       wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+       wkup_i2c0_pins_default: wkup-i2c0-default-pins {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
                        J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
                >;
        };
 
-       mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
-               pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
-                       J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
-                       J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
-                       J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
-                       J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
-                       J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
-                       J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
-                       J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
-                       J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
-                       J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
-                       J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
-                       J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
-                       J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
-                       J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
-               >;
-       };
-
-       mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+       mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
                        J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
@@ -184,26 +167,46 @@
                        J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
                >;
        };
+
+       mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1)  /* MCU_HYPERBUS0_CK */
+                       J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1)  /* MCU_HYPERBUS0_CKn */
+                       J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */
+                       J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */
+                       J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */
+                       J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1)   /* MCU_HYPERBUS0_RWDS */
+                       J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1)   /* MCU_HYPERBUS0_DQ0 */
+                       J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ1 */
+                       J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ2 */
+                       J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ3 */
+                       J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ4 */
+                       J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ5 */
+                       J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ6 */
+                       J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ7 */
+               >;
+       };
 };
 
-&hbmc {
-       status = "disabled";
+&wkup_i2c0 {
+       status = "okay";
        pinctrl-names = "default";
-       pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
-       ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
-                <0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
+       pinctrl-0 = <&wkup_i2c0_pins_default>;
+       clock-frequency = <400000>;
 
-       flash@0,0 {
-               compatible = "cypress,hyperflash", "cfi-flash";
-               reg = <0x0 0x0 0x4000000>;
+       eeprom@50 {
+               /* CAV24C256WE-GT3 */
+               compatible = "atmel,24c256";
+               reg = <0x50>;
        };
 };
 
 &ospi0 {
+       status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
 
-       flash@0{
+       flash@0 {
                compatible = "jedec,spi-nor";
                reg = <0x0>;
                spi-tx-bus-width = <8>;
@@ -214,12 +217,109 @@
                cdns,tchsh-ns = <60>;
                cdns,tslch-ns = <60>;
                cdns,read-delay = <0>;
-               #address-cells = <1>;
-               #size-cells = <1>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "ospi.tiboot3";
+                               reg = <0x0 0x80000>;
+                       };
+
+                       partition@80000 {
+                               label = "ospi.tispl";
+                               reg = <0x80000 0x200000>;
+                       };
+
+                       partition@280000 {
+                               label = "ospi.u-boot";
+                               reg = <0x280000 0x400000>;
+                       };
+
+                       partition@680000 {
+                               label = "ospi.env";
+                               reg = <0x680000 0x20000>;
+                       };
+
+                       partition@6a0000 {
+                               label = "ospi.env.backup";
+                               reg = <0x6a0000 0x20000>;
+                       };
+
+                       partition@6c0000 {
+                               label = "ospi.sysfw";
+                               reg = <0x6c0000 0x100000>;
+                       };
+
+                       partition@800000 {
+                               label = "ospi.rootfs";
+                               reg = <0x800000 0x37c0000>;
+                       };
+
+                       partition@3fe0000 {
+                               label = "ospi.phypattern";
+                               reg = <0x3fe0000 0x20000>;
+                       };
+               };
+       };
+};
+
+&hbmc {
+       /* OSPI and HBMC are muxed inside FSS, Bootloader will enable
+        * appropriate node based on board detection
+        */
+       status = "disabled";
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
+       ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
+                <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
+
+       flash@0,0 {
+               compatible = "cypress,hyperflash", "cfi-flash";
+               reg = <0x00 0x00 0x4000000>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "hbmc.tiboot3";
+                               reg = <0x0 0x80000>;
+                       };
+
+                       partition@80000 {
+                               label = "hbmc.tispl";
+                               reg = <0x80000 0x200000>;
+                       };
+
+                       partition@280000 {
+                               label = "hbmc.u-boot";
+                               reg = <0x280000 0x400000>;
+                       };
+
+                       partition@680000 {
+                               label = "hbmc.env";
+                               reg = <0x680000 0x40000>;
+                       };
+
+                       partition@6c0000 {
+                               label = "hbmc.sysfw";
+                               reg = <0x6c0000 0x100000>;
+                       };
+
+                       partition@800000 {
+                               label = "hbmc.rootfs";
+                               reg = <0x800000 0x3800000>;
+                       };
+               };
        };
 };
 
 &mailbox0_cluster0 {
+       status = "okay";
        interrupts = <436>;
 
        mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -234,6 +334,7 @@
 };
 
 &mailbox0_cluster1 {
+       status = "okay";
        interrupts = <432>;
 
        mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
@@ -248,6 +349,7 @@
 };
 
 &mailbox0_cluster2 {
+       status = "okay";
        interrupts = <428>;
 
        mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
@@ -262,6 +364,7 @@
 };
 
 &mailbox0_cluster3 {
+       status = "okay";
        interrupts = <424>;
 
        mbox_c66_0: mbox-c66-0 {
@@ -276,6 +379,7 @@
 };
 
 &mailbox0_cluster4 {
+       status = "okay";
        interrupts = <420>;
 
        mbox_c71_0: mbox-c71-0 {
@@ -284,84 +388,59 @@
        };
 };
 
-&mailbox0_cluster5 {
-       status = "disabled";
-};
-
-&mailbox0_cluster6 {
-       status = "disabled";
-};
-
-&mailbox0_cluster7 {
-       status = "disabled";
-};
-
-&mailbox0_cluster8 {
-       status = "disabled";
-};
-
-&mailbox0_cluster9 {
-       status = "disabled";
-};
-
-&mailbox0_cluster10 {
-       status = "disabled";
-};
-
-&mailbox0_cluster11 {
-       status = "disabled";
-};
-
 &mcu_r5fss0_core0 {
-       mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+       mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
        memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
                        <&mcu_r5fss0_core0_memory_region>;
 };
 
 &mcu_r5fss0_core1 {
-       mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+       mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
        memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
                        <&mcu_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss0_core0 {
-       mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+       mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
        memory-region = <&main_r5fss0_core0_dma_memory_region>,
                        <&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
-       mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+       mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
        memory-region = <&main_r5fss0_core1_dma_memory_region>,
                        <&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
-       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+       mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
        memory-region = <&main_r5fss1_core0_dma_memory_region>,
                        <&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
-       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+       mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
        memory-region = <&main_r5fss1_core1_dma_memory_region>,
                        <&main_r5fss1_core1_memory_region>;
 };
 
 &c66_0 {
-       mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+       status = "okay";
+       mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
        memory-region = <&c66_0_dma_memory_region>,
                        <&c66_0_memory_region>;
 };
 
 &c66_1 {
-       mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+       status = "okay";
+       mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
        memory-region = <&c66_1_dma_memory_region>,
                        <&c66_1_memory_region>;
 };
 
 &c71_0 {
-       mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+       status = "okay";
+       mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
        memory-region = <&c71_0_dma_memory_region>,
                        <&c71_0_memory_region>;
 };

diff --git a/arch/arm/dts/k3-j721e-thermal.dtsi b/arch/arm/dts/k3-j721e-thermal.dtsi
new file mode 100644 (file)
index 0000000..c252327
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-thermal.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+       wkup_thermal: wkup-thermal {
+               polling-delay-passive = <250>; /* milliseconds */
+               polling-delay = <500>; /* milliseconds */
+               thermal-sensors = <&wkup_vtm0 0>;
+
+               trips {
+                       wkup_crit: wkup-crit {
+                               temperature = <125000>; /* milliCelsius */
+                               hysteresis = <2000>; /* milliCelsius */
+                               type = "critical";
+                       };
+               };
+       };
+
+       mpu_thermal: mpu-thermal {
+               polling-delay-passive = <250>; /* milliseconds */
+               polling-delay = <500>; /* milliseconds */
+               thermal-sensors = <&wkup_vtm0 1>;
+
+               trips {
+                       mpu_crit: mpu-crit {
+                               temperature = <125000>; /* milliCelsius */
+                               hysteresis = <2000>; /* milliCelsius */
+                               type = "critical";
+                       };
+               };
+       };
+
+       c7x_thermal: c7x-thermal {
+               polling-delay-passive = <250>; /* milliseconds */
+               polling-delay = <500>; /* milliseconds */
+               thermal-sensors = <&wkup_vtm0 2>;
+
+               trips {
+                       c7x_crit: c7x-crit {
+                               temperature = <125000>; /* milliCelsius */
+                               hysteresis = <2000>; /* milliCelsius */
+                               type = "critical";
+                       };
+               };
+       };
+
+       gpu_thermal: gpu-thermal {
+               polling-delay-passive = <250>; /* milliseconds */
+               polling-delay = <500>; /* milliseconds */
+               thermal-sensors = <&wkup_vtm0 3>;
+
+               trips {
+                       gpu_crit: gpu-crit {
+                               temperature = <125000>; /* milliCelsius */
+                               hysteresis = <2000>; /* milliCelsius */
+                               type = "critical";
+                       };
+               };
+       };
+
+       r5f_thermal: r5f-thermal {
+               polling-delay-passive = <250>; /* milliseconds */
+               polling-delay = <500>; /* milliseconds */
+               thermal-sensors = <&wkup_vtm0 4>;
+
+               trips {
+                       r5f_crit: r5f-crit {
+                               temperature = <125000>; /* milliCelsius */
+                               hysteresis = <2000>; /* milliCelsius */
+                               type = "critical";
+                       };
+               };
+       };
+};

diff --git a/arch/arm/dts/k3-j721e.dtsi b/arch/arm/dts/k3-j721e.dtsi
index f0587fd..a200810 100644 (file)
--- a/arch/arm/dts/k3-j721e.dtsi
+++ b/arch/arm/dts/k3-j721e.dtsi
@@ -7,9 +7,10 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/k3.h>
 #include <dt-bindings/soc/ti,sci_pm_domain.h>
 
+#include "k3-pinctrl.h"
+
 / {
        model = "Texas Instruments K3 J721E SoC";
        compatible = "ti,j721e";
@@ -17,22 +18,6 @@
        #address-cells = <2>;
        #size-cells = <2>;
 
-       aliases {
-               serial0 = &wkup_uart0;
-               serial1 = &mcu_uart0;
-               serial2 = &main_uart0;
-               serial3 = &main_uart1;
-               serial4 = &main_uart2;
-               serial5 = &main_uart3;
-               serial6 = &main_uart4;
-               serial7 = &main_uart5;
-               serial8 = &main_uart6;
-               serial9 = &main_uart7;
-               serial10 = &main_uart8;
-               serial11 = &main_uart9;
-               ethernet0 = &cpsw_port1;
-       };
-
        chosen { };
 
        cpus {
@@ -61,7 +46,7 @@
                        i-cache-sets = <256>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
-                       d-cache-sets = <128>;
+                       d-cache-sets = <256>;
                        next-level-cache = <&L2_0>;
                };
 
@@ -75,7 +60,7 @@
                        i-cache-sets = <256>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
-                       d-cache-sets = <128>;
+                       d-cache-sets = <256>;
                        next-level-cache = <&L2_0>;
                };
        };
@@ -83,15 +68,17 @@
        L2_0: l2-cache0 {
                compatible = "cache";
                cache-level = <2>;
+               cache-unified;
                cache-size = <0x100000>;
                cache-line-size = <64>;
-               cache-sets = <2048>;
+               cache-sets = <1024>;
                next-level-cache = <&msmc_l3>;
        };
 
        msmc_l3: l3-cache0 {
                compatible = "cache";
                cache-level = <3>;
+               cache-unified;
        };
 
        firmware {
@@ -126,16 +113,19 @@
                #size-cells = <2>;
                ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
                         <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
+                        <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
                         <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
                         <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
                         <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
                         <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
                         <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
+                        <0x00 0x0c000000 0x00 0x0c000000 0x00 0x0d000000>, /* CPSW9G */
                         <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
                         <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/
                         <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/
                         <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
                         <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
+                        <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
                         <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
                         <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
                         <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
@@ -177,6 +167,8 @@
                                 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
                };
        };
+
+       #include "k3-j721e-thermal.dtsi"
 };
 
 /* Now include the peripherals for each bus segments */

diff --git a/arch/arm/dts/stm32f4-pinctrl.dtsi b/arch/arm/dts/stm32f4-pinctrl.dtsi
index 46815c9..0adc41b 100644 (file)
--- a/arch/arm/dts/stm32f4-pinctrl.dtsi
+++ b/arch/arm/dts/stm32f4-pinctrl.dtsi
@@ -412,6 +412,36 @@
                                        slew-rate = <2>;
                                };
                        };
+
+                       can1_pins_a: can1-0 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
+                                       bias-pull-up;
+                               };
+                       };
+
+                       can2_pins_a: can2-0 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
+                                       bias-pull-up;
+                               };
+                       };
+
+                       can2_pins_b: can2-1 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
+                                       bias-pull-up;
+                               };
+                       };
                };
        };
 };

diff --git a/arch/arm/dts/stm32f429.dtsi b/arch/arm/dts/stm32f429.dtsi
index e5b13ac..8133ea1 100644 (file)
--- a/arch/arm/dts/stm32f429.dtsi
+++ b/arch/arm/dts/stm32f429.dtsi
@@ -321,6 +321,36 @@
                        status = "disabled";
                };
 
+               can1: can@40006400 {
+                       compatible = "st,stm32f4-bxcan";
+                       reg = <0x40006400 0x200>;
+                       interrupts = <19>, <20>, <21>, <22>;
+                       interrupt-names = "tx", "rx0", "rx1", "sce";
+                       resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
+                       clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
+                       st,can-primary;
+                       st,gcan = <&gcan>;
+                       status = "disabled";
+               };
+
+               gcan: gcan@40006600 {
+                       compatible = "st,stm32f4-gcan", "syscon";
+                       reg = <0x40006600 0x200>;
+                       clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
+               };
+
+               can2: can@40006800 {
+                       compatible = "st,stm32f4-bxcan";
+                       reg = <0x40006800 0x200>;
+                       interrupts = <63>, <64>, <65>, <66>;
+                       interrupt-names = "tx", "rx0", "rx1", "sce";
+                       resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
+                       clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
+                       st,can-secondary;
+                       st,gcan = <&gcan>;
+                       status = "disabled";
+               };
+
                dac: dac@40007400 {
                        compatible = "st,stm32f4-dac-core";
                        reg = <0x40007400 0x400>;

diff --git a/arch/arm/dts/stm32f7-pinctrl.dtsi b/arch/arm/dts/stm32f7-pinctrl.dtsi
index 8f37aef..d3706ee 100644 (file)
--- a/arch/arm/dts/stm32f7-pinctrl.dtsi
+++ b/arch/arm/dts/stm32f7-pinctrl.dtsi
@@ -172,6 +172,16 @@
                                };
                        };
 
+                       i2c3_pins_a: i2c3-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('H', 8, AF4)>, /* I2C3_SDA */
+                                                <STM32_PINMUX('H', 7, AF4)>; /* I2C3_SCL */
+                                       bias-disable;
+                                       drive-open-drain;
+                                       slew-rate = <0>;
+                               };
+                       };
+
                        usbotg_hs_pins_a: usbotg-hs-0 {
                                pins {
                                        pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
@@ -284,6 +294,122 @@
                                        slew-rate = <2>;
                                };
                        };
+
+                       can1_pins_a: can1-0 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
+                                       bias-pull-up;
+                               };
+                       };
+
+                       can1_pins_b: can1-1 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
+                                       bias-pull-up;
+                               };
+                       };
+
+                       can1_pins_c: can1-2 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
+                                       bias-pull-up;
+
+                               };
+                       };
+
+                       can1_pins_d: can1-3 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
+                                       bias-pull-up;
+
+                               };
+                       };
+
+                       can2_pins_a: can2-0 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN2_TX */
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
+                                       bias-pull-up;
+                               };
+                       };
+
+                       can2_pins_b: can2-1 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
+                                       bias-pull-up;
+                               };
+                       };
+
+                       can3_pins_a: can3-0 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('A', 15, AF11)>; /* CAN3_TX */
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('A', 8, AF11)>; /* CAN3_RX */
+                                       bias-pull-up;
+                               };
+                       };
+
+                       can3_pins_b: can3-1 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('B', 4, AF11)>;  /* CAN3_TX */
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('B', 3, AF11)>; /* CAN3_RX */
+                                       bias-pull-up;
+                               };
+                       };
+
+                       ltdc_pins_a: ltdc-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('E', 4, AF14)>, /* LCD_B0 */
+                                                <STM32_PINMUX('G',12, AF9)>,  /* LCD_B4 */
+                                                <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
+                                                <STM32_PINMUX('I',10, AF14)>, /* LCD_HSYNC */
+                                                <STM32_PINMUX('I',14, AF14)>, /* LCD_CLK */
+                                                <STM32_PINMUX('I',15, AF14)>, /* LCD_R0 */
+                                                <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
+                                                <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
+                                                <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
+                                                <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
+                                                <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
+                                                <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
+                                                <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
+                                                <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
+                                                <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
+                                                <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
+                                                <STM32_PINMUX('J',10, AF14)>, /* LCD_G3 */
+                                                <STM32_PINMUX('J',11, AF14)>, /* LCD_G4 */
+                                                <STM32_PINMUX('J',13, AF14)>, /* LCD_B1 */
+                                                <STM32_PINMUX('J',14, AF14)>, /* LCD_B2 */
+                                                <STM32_PINMUX('J',15, AF14)>, /* LCD_B3 */
+                                                <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
+                                                <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
+                                                <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
+                                                <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
+                                                <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
+                                                <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
+                                                <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
+                                       slew-rate = <2>;
+                               };
+                       };
                };
        };
 };

diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
index 522cffb..1b42d6c 100644 (file)
--- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
@@ -23,12 +23,6 @@
                spi0 = &qspi;
        };
 
-       backlight: backlight {
-               compatible = "gpio-backlight";
-               gpios = <&gpiok 3 0>;
-               status = "okay";
-       };
-
        button1 {
                compatible = "st,button1";
                button-gpio = <&gpioi 11 0>;
@@ -38,44 +32,11 @@
                compatible = "st,led1";
                led-gpio = <&gpioi 1 0>;
        };
+};
 
-       panel-rgb@0 {
-               compatible = "simple-panel";
-               backlight = <&backlight>;
-               enable-gpios = <&gpioi 12 0>;
-               status = "okay";
-
-               display-timings {
-                       timing@0 {
-                               clock-frequency = <9000000>;
-                               hactive = <480>;
-                               vactive = <272>;
-                               hfront-porch = <2>;
-                               hback-porch = <2>;
-                               hsync-len = <41>;
-                               vfront-porch = <2>;
-                               vback-porch = <2>;
-                               vsync-len = <10>;
-                               hsync-active = <0>;
-                               vsync-active = <0>;
-                               de-active = <1>;
-                               pixelclk-active = <1>;
-                       };
-               };
-       };
-
-       soc {
-               ltdc: display-controller@40016800 {
-                       compatible = "st,stm32-ltdc";
-                       reg = <0x40016800 0x200>;
-                       resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
-                       clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
-                       pinctrl-0 = <&ltdc_pins>;
-
-                       status = "okay";
-                       bootph-all;
-               };
-       };
+&ltdc {
+       clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+       bootph-all;
 };
 
 &fmc {
@@ -102,6 +63,28 @@
        };
 };
 
+&panel_rgb {
+       compatible = "simple-panel";
+
+       display-timings {
+               timing@0 {
+                       clock-frequency = <9000000>;
+                       hactive = <480>;
+                       vactive = <272>;
+                       hfront-porch = <2>;
+                       hback-porch = <2>;
+                       hsync-len = <41>;
+                       vfront-porch = <2>;
+                       vback-porch = <2>;
+                       vsync-len = <10>;
+                       hsync-active = <0>;
+                       vsync-active = <0>;
+                       de-active = <1>;
+                       pixelclk-active = <1>;
+               };
+       };
+};
+
 &pinctrl {
        ethernet_mii: mii@0 {
                pins {
@@ -166,40 +149,6 @@
                };
        };
 
-       ltdc_pins: ltdc@0 {
-               pins {
-                       pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */
-                                <STM32_PINMUX('G',12, AF9)>,  /* B4 */
-                                <STM32_PINMUX('I', 9, AF14)>, /* VSYNC */
-                                <STM32_PINMUX('I',10, AF14)>, /* HSYNC */
-                                <STM32_PINMUX('I',14, AF14)>, /* CLK */
-                                <STM32_PINMUX('I',15, AF14)>, /* R0 */
-                                <STM32_PINMUX('J', 0, AF14)>, /* R1 */
-                                <STM32_PINMUX('J', 1, AF14)>, /* R2 */
-                                <STM32_PINMUX('J', 2, AF14)>, /* R3 */
-                                <STM32_PINMUX('J', 3, AF14)>, /* R4 */
-                                <STM32_PINMUX('J', 4, AF14)>, /* R5 */
-                                <STM32_PINMUX('J', 5, AF14)>, /* R6 */
-                                <STM32_PINMUX('J', 6, AF14)>, /* R7 */
-                                <STM32_PINMUX('J', 7, AF14)>, /* G0 */
-                                <STM32_PINMUX('J', 8, AF14)>, /* G1 */
-                                <STM32_PINMUX('J', 9, AF14)>, /* G2 */
-                                <STM32_PINMUX('J',10, AF14)>, /* G3 */
-                                <STM32_PINMUX('J',11, AF14)>, /* G4 */
-                                <STM32_PINMUX('J',13, AF14)>, /* B1 */
-                                <STM32_PINMUX('J',14, AF14)>, /* B2 */
-                                <STM32_PINMUX('J',15, AF14)>, /* B3 */
-                                <STM32_PINMUX('K', 0, AF14)>, /* G5 */
-                                <STM32_PINMUX('K', 1, AF14)>, /* G6 */
-                                <STM32_PINMUX('K', 2, AF14)>, /* G7 */
-                                <STM32_PINMUX('K', 4, AF14)>, /* B5 */
-                                <STM32_PINMUX('K', 5, AF14)>, /* B6 */
-                                <STM32_PINMUX('K', 6, AF14)>, /* B7 */
-                                <STM32_PINMUX('K', 7, AF14)>; /* DE */
-                       slew-rate = <2>;
-               };
-       };
-
        qspi_pins: qspi@0 {
                pins {
                        pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */

diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
index 1ed58f2..4312751 100644 (file)
--- a/arch/arm/dts/stm32f746-disco.dts
+++ b/arch/arm/dts/stm32f746-disco.dts
@@ -7,8 +7,9 @@
 /dts-v1/;
 #include "stm32f746.dtsi"
 #include "stm32f746-pinctrl.dtsi"
-#include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
        model = "STMicroelectronics STM32F746-DISCO board";
@@ -24,6 +25,19 @@
                reg = <0xC0000000 0x800000>;
        };
 
+       reserved-memory {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               linux,cma {
+                       compatible = "shared-dma-pool";
+                       no-map;
+                       size = <0x80000>;
+                       linux,dma-default;
+               };
+       };
+
        aliases {
                serial0 = &usart1;
        };
@@ -43,12 +57,31 @@
                regulator-always-on;
        };
 
-       mmc_vcard: mmc_vcard {
+       vcc_3v3: vcc-3v3 {
                compatible = "regulator-fixed";
-               regulator-name = "mmc_vcard";
+               regulator-name = "vcc_3v3";
                regulator-min-microvolt = <3300000>;
                regulator-max-microvolt = <3300000>;
        };
+
+       backlight: backlight {
+               compatible = "gpio-backlight";
+               gpios = <&gpiok 3 GPIO_ACTIVE_HIGH>;
+               status = "okay";
+       };
+
+       panel_rgb: panel-rgb {
+               compatible = "rocktech,rk043fn48h";
+               power-supply = <&vcc_3v3>;
+               backlight = <&backlight>;
+               enable-gpios = <&gpioi 12 GPIO_ACTIVE_HIGH>;
+               status = "okay";
+               port {
+                       panel_in_rgb: endpoint {
+                               remote-endpoint = <&ltdc_out_rgb>;
+                       };
+               };
+       };
 };
 
 &clk_hse {
@@ -63,9 +96,37 @@
        status = "okay";
 };
 
+&i2c3 {
+       pinctrl-0 = <&i2c3_pins_a>;
+       pinctrl-names = "default";
+       clock-frequency = <400000>;
+       status = "okay";
+
+       touchscreen@38 {
+               compatible = "edt,edt-ft5306";
+               reg = <0x38>;
+               interrupt-parent = <&gpioi>;
+               interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+               touchscreen-size-x = <480>;
+               touchscreen-size-y = <272>;
+       };
+};
+
+&ltdc {
+       pinctrl-0 = <&ltdc_pins_a>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       port {
+               ltdc_out_rgb: endpoint {
+                       remote-endpoint = <&panel_in_rgb>;
+               };
+       };
+};
+
 &sdio1 {
        status = "okay";
-       vmmc-supply = <&mmc_vcard>;
+       vmmc-supply = <&vcc_3v3>;
        cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
        pinctrl-names = "default", "opendrain";
        pinctrl-0 = <&sdio_pins_a>;

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index c97b3d0..79dad31 100644 (file)
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -221,6 +221,23 @@
                        status = "disabled";
                };
 
+               can3: can@40003400 {
+                       compatible = "st,stm32f4-bxcan";
+                       reg = <0x40003400 0x200>;
+                       interrupts = <104>, <105>, <106>, <107>;
+                       interrupt-names = "tx", "rx0", "rx1", "sce";
+                       resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
+                       clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
+                       st,gcan = <&gcan3>;
+                       status = "disabled";
+               };
+
+               gcan3: gcan@40003600 {
+                       compatible = "st,stm32f4-gcan", "syscon";
+                       reg = <0x40003600 0x200>;
+                       clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
+               };
+
                usart2: serial@40004400 {
                        compatible = "st,stm32f7-uart";
                        reg = <0x40004400 0x400>;
@@ -301,6 +318,36 @@
                        status = "disabled";
                };
 
+               can1: can@40006400 {
+                       compatible = "st,stm32f4-bxcan";
+                       reg = <0x40006400 0x200>;
+                       interrupts = <19>, <20>, <21>, <22>;
+                       interrupt-names = "tx", "rx0", "rx1", "sce";
+                       resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
+                       clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
+                       st,can-primary;
+                       st,gcan = <&gcan1>;
+                       status = "disabled";
+               };
+
+               gcan1: gcan@40006600 {
+                       compatible = "st,stm32f4-gcan", "syscon";
+                       reg = <0x40006600 0x200>;
+                       clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
+               };
+
+               can2: can@40006800 {
+                       compatible = "st,stm32f4-bxcan";
+                       reg = <0x40006800 0x200>;
+                       interrupts = <63>, <64>, <65>, <66>;
+                       interrupt-names = "tx", "rx0", "rx1", "sce";
+                       resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
+                       clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
+                       st,can-secondary;
+                       st,gcan = <&gcan1>;
+                       status = "disabled";
+               };
+
                cec: cec@40006c00 {
                        compatible = "st,stm32-cec";
                        reg = <0x40006C00 0x400>;
@@ -471,6 +518,16 @@
                        };
                };
 
+               ltdc: display-controller@40016800 {
+                       compatible = "st,stm32-ltdc";
+                       reg = <0x40016800 0x200>;
+                       interrupts = <88>, <89>;
+                       resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
+                       clocks = <&rcc 1 CLK_LCD>;
+                       clock-names = "lcd";
+                       status = "disabled";
+               };
+
                pwrcfg: power-config@40007000 {
                        compatible = "st,stm32-power-config", "syscon";
                        reg = <0x40007000 0x400>;
@@ -479,7 +536,7 @@
                crc: crc@40023000 {
                        compatible = "st,stm32f7-crc";
                        reg = <0x40023000 0x400>;
-                       clocks = <&rcc 0 12>;
+                       clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
                        status = "disabled";
                };
 

diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
index d23bbc3..215ad92 100644 (file)
--- a/arch/arm/dts/stm32mp131.dtsi
+++ b/arch/arm/dts/stm32mp131.dtsi
@@ -33,6 +33,8 @@
                optee {
                        method = "smc";
                        compatible = "linaro,optee-tz";
+                       interrupt-parent = <&intc>;
+                       interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
                };
 
                scmi: scmi {
@@ -50,6 +52,28 @@
                                reg = <0x16>;
                                #reset-cells = <1>;
                        };
+
+                       scmi_voltd: protocol@17 {
+                               reg = <0x17>;
+
+                               scmi_regu: regulators {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       scmi_reg11: regulator@0 {
+                                               reg = <VOLTD_SCMI_REG11>;
+                                               regulator-name = "reg11";
+                                       };
+                                       scmi_reg18: regulator@1 {
+                                               reg = <VOLTD_SCMI_REG18>;
+                                               regulator-name = "reg18";
+                                       };
+                                       scmi_usb33: regulator@2 {
+                                               reg = <VOLTD_SCMI_USB33>;
+                                               regulator-name = "usb33";
+                                       };
+                               };
+                       };
                };
        };
 
@@ -76,28 +100,6 @@
                always-on;
        };
 
-       /* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */
-       reg11: reg11 {
-               compatible = "regulator-fixed";
-               regulator-name = "reg11";
-               regulator-min-microvolt = <1100000>;
-               regulator-max-microvolt = <1100000>;
-       };
-
-       reg18: reg18 {
-               compatible = "regulator-fixed";
-               regulator-name = "reg18";
-               regulator-min-microvolt = <1800000>;
-               regulator-max-microvolt = <1800000>;
-       };
-
-       usb33: usb33 {
-               compatible = "regulator-fixed";
-               regulator-name = "usb33";
-               regulator-min-microvolt = <3300000>;
-               regulator-max-microvolt = <3300000>;
-       };
-
        soc {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -799,7 +801,7 @@
                        g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
                        dr_mode = "otg";
                        otg-rev = <0x200>;
-                       usb33d-supply = <&usb33>;
+                       usb33d-supply = <&scmi_usb33>;
                        status = "disabled";
                };
 
@@ -1208,6 +1210,14 @@
                        };
                };
 
+               rng: rng@54004000 {
+                       compatible = "st,stm32mp13-rng";
+                       reg = <0x54004000 0x400>;
+                       clocks = <&rcc RNG1_K>;
+                       resets = <&rcc RNG1_R>;
+                       status = "disabled";
+               };
+
                mdma: dma-controller@58000000 {
                        compatible = "st,stm32h7-mdma";
                        reg = <0x58000000 0x1000>;
@@ -1329,8 +1339,8 @@
                        reg = <0x5a006000 0x1000>;
                        clocks = <&rcc USBPHY_K>;
                        resets = <&rcc USBPHY_R>;
-                       vdda1v1-supply = <&reg11>;
-                       vdda1v8-supply = <&reg18>;
+                       vdda1v1-supply = <&scmi_reg11>;
+                       vdda1v8-supply = <&scmi_reg18>;
                        status = "disabled";
 
                        usbphyc_port0: usb-phy@0 {

diff --git a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
index 48605ff..ba0c024 100644 (file)
--- a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
@@ -38,3 +38,7 @@
                bootph-all;
        };
 };
+
+&usbotg_hs {
+       u-boot,force-b-session-valid;
+};

diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts
index f0900ca..eea740d 100644 (file)
--- a/arch/arm/dts/stm32mp135f-dk.dts
+++ b/arch/arm/dts/stm32mp135f-dk.dts
@@ -9,6 +9,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
 #include "stm32mp135.dtsi"
 #include "stm32mp13xf.dtsi"
 #include "stm32mp13-pinctrl.dtsi"
@@ -65,45 +66,13 @@
                        default-state = "off";
                };
        };
-
-       v3v3_sw: v3v3-sw {
-               compatible = "regulator-fixed";
-               regulator-name = "v3v3_sw";
-               regulator-min-microvolt = <3300000>;
-               regulator-max-microvolt = <3300000>;
-               regulator-always-on;
-       };
-
-       vdd_adc: vdd-adc {
-               compatible = "regulator-fixed";
-               regulator-name = "vdd_adc";
-               regulator-min-microvolt = <3300000>;
-               regulator-max-microvolt = <3300000>;
-               regulator-always-on;
-       };
-
-       vdd_sd: vdd-sd {
-               compatible = "regulator-fixed";
-               regulator-name = "vdd_sd";
-               regulator-min-microvolt = <2900000>;
-               regulator-max-microvolt = <2900000>;
-               regulator-always-on;
-       };
-
-       vdd_usb: vdd-usb {
-               compatible = "regulator-fixed";
-               regulator-name = "vdd_usb";
-               regulator-min-microvolt = <3300000>;
-               regulator-max-microvolt = <3300000>;
-               regulator-always-on;
-       };
 };
 
 &adc_1 {
        pinctrl-names = "default";
        pinctrl-0 = <&adc1_usb_cc_pins_a>;
-       vdda-supply = <&vdd_adc>;
-       vref-supply = <&vdd_adc>;
+       vdda-supply = <&scmi_vdd_adc>;
+       vref-supply = <&scmi_vdd_adc>;
        status = "okay";
        adc1: adc@0 {
                status = "okay";
@@ -195,6 +164,29 @@
        status = "okay";
 };
 
+&scmi_regu {
+       scmi_vdd_adc: regulator@10 {
+               reg = <VOLTD_SCMI_STPMIC1_LDO1>;
+               regulator-name = "vdd_adc";
+       };
+       scmi_vdd_usb: regulator@13 {
+               reg = <VOLTD_SCMI_STPMIC1_LDO4>;
+               regulator-name = "vdd_usb";
+       };
+       scmi_vdd_sd: regulator@14 {
+               reg = <VOLTD_SCMI_STPMIC1_LDO5>;
+               regulator-name = "vdd_sd";
+       };
+       scmi_v1v8_periph: regulator@15 {
+               reg = <VOLTD_SCMI_STPMIC1_LDO6>;
+               regulator-name = "v1v8_periph";
+       };
+       scmi_v3v3_sw: regulator@19 {
+               reg = <VOLTD_SCMI_STPMIC1_PWR_SW2>;
+               regulator-name = "v3v3_sw";
+       };
+};
+
 &sdmmc1 {
        pinctrl-names = "default", "opendrain", "sleep";
        pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
@@ -204,7 +196,7 @@
        disable-wp;
        st,neg-edge;
        bus-width = <4>;
-       vmmc-supply = <&vdd_sd>;
+       vmmc-supply = <&scmi_vdd_sd>;
        status = "okay";
 };
 
@@ -321,7 +313,7 @@
        hub@1 {
                compatible = "usb424,2514";
                reg = <1>;
-               vdd-supply = <&v3v3_sw>;
+               vdd-supply = <&scmi_v3v3_sw>;
        };
 };
 
@@ -342,7 +334,7 @@
 };
 
 &usbphyc_port0 {
-       phy-supply = <&vdd_usb>;
+       phy-supply = <&scmi_vdd_usb>;
        st,current-boost-microamp = <1000>;
        st,decrease-hs-slew-rate;
        st,tune-hs-dc-level = <2>;
@@ -356,7 +348,7 @@
 };
 
 &usbphyc_port1 {
-       phy-supply = <&vdd_usb>;
+       phy-supply = <&scmi_vdd_usb>;
        st,current-boost-microamp = <1000>;
        st,decrease-hs-slew-rate;
        st,tune-hs-dc-level = <2>;

diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index e86d989..098153e 100644 (file)
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
@@ -6,6 +6,17 @@
 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
 
 &pinctrl {
+       adc1_ain_pins_a: adc1-ain-0 {
+               pins {
+                       pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1_INP2 */
+                                <STM32_PINMUX('B', 1, ANALOG)>, /* ADC1_INP5 */
+                                <STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */
+                                <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */
+                                <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1_INP13 */
+                                <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1_INP15 */
+               };
+       };
+
        adc1_in6_pins_a: adc1-in6-0 {
                pins {
                        pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
@@ -341,6 +352,96 @@
                };
        };
 
+       ethernet0_rgmii_pins_d: rgmii-3 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
+                                <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
+                                <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+                                <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+                                <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
+                                <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
+                                <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
+                       bias-disable;
+                       drive-push-pull;
+                       slew-rate = <2>;
+               };
+               pins2 {
+                       pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
+                       bias-disable;
+                       drive-push-pull;
+                       slew-rate = <0>;
+               };
+               pins3 {
+                       pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
+                                <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
+                                <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
+                                <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
+                                <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
+                                <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
+                       bias-disable;
+               };
+       };
+
+       ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
+                                <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+                                <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
+                                <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
+                                <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
+                                <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
+                                <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
+                                <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+                                <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
+                                <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+                                <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
+                                <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
+                                <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
+                                <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
+                                <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
+               };
+       };
+
+       ethernet0_rgmii_pins_e: rgmii-4 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
+                                <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
+                                <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+                                <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+                                <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
+                                <STM32_PINMUX('B', 11, AF11)>; /* ETH_RGMII_TX_CTL */
+                       bias-disable;
+                       drive-push-pull;
+                       slew-rate = <2>;
+               };
+               pins2 {
+                       pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
+                                <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
+                                <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
+                                <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
+                                <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
+                                <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
+                       bias-disable;
+               };
+       };
+
+       ethernet0_rgmii_sleep_pins_e: rgmii-sleep-4 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+                                <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
+                                <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
+                                <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
+                                <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
+                                <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
+                                <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+                                <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
+                                <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
+                                <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */
+                                <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
+                                <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
+               };
+       };
+
        ethernet0_rmii_pins_a: rmii-0 {
                pins1 {
                        pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
@@ -1104,6 +1205,20 @@
                };
        };
 
+       pwm1_pins_c: pwm1-2 {
+               pins {
+                       pinmux = <STM32_PINMUX('E', 11, AF1)>; /* TIM1_CH2 */
+                       drive-push-pull;
+                       slew-rate = <0>;
+               };
+       };
+
+       pwm1_sleep_pins_c: pwm1-sleep-2 {
+               pins {
+                       pinmux = <STM32_PINMUX('E', 11, ANALOG)>; /* TIM1_CH2 */
+               };
+       };
+
        pwm2_pins_a: pwm2-0 {
                pins {
                        pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
@@ -1230,6 +1345,26 @@
                };
        };
 
+       pwm8_pins_b: pwm8-1 {
+               pins {
+                       pinmux = <STM32_PINMUX('I', 5, AF3)>, /* TIM8_CH1 */
+                                <STM32_PINMUX('I', 6, AF3)>, /* TIM8_CH2 */
+                                <STM32_PINMUX('I', 7, AF3)>, /* TIM8_CH3 */
+                                <STM32_PINMUX('C', 9, AF3)>; /* TIM8_CH4 */
+                       drive-push-pull;
+                       slew-rate = <0>;
+               };
+       };
+
+       pwm8_sleep_pins_b: pwm8-sleep-1 {
+               pins {
+                       pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* TIM8_CH1 */
+                                <STM32_PINMUX('I', 6, ANALOG)>, /* TIM8_CH2 */
+                                <STM32_PINMUX('I', 7, ANALOG)>, /* TIM8_CH3 */
+                                <STM32_PINMUX('C', 9, ANALOG)>; /* TIM8_CH4 */
+               };
+       };
+
        pwm12_pins_a: pwm12-0 {
                pins {
                        pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
@@ -1441,6 +1576,30 @@
                };
        };
 
+       sai2b_pins_d: sai2b-3 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('H', 2, AF10)>, /* SAI2_SCK_B */
+                                <STM32_PINMUX('C', 0, AF8)>, /* SAI2_FS_B */
+                                <STM32_PINMUX('H', 3, AF10)>; /* SAI2_MCLK_B */
+                       slew-rate = <0>;
+                       drive-push-pull;
+                       bias-disable;
+               };
+               pins2 {
+                       pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
+                       bias-disable;
+               };
+       };
+
+       sai2b_sleep_pins_d: sai2b-sleep-3 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* SAI2_SCK_B */
+                                <STM32_PINMUX('C', 0, ANALOG)>, /* SAI2_FS_B */
+                                <STM32_PINMUX('H', 3, ANALOG)>, /* SAI2_MCLK_B */
+                                <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
+               };
+       };
+
        sai4a_pins_a: sai4a-0 {
                pins {
                        pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
@@ -1522,6 +1681,60 @@
                };
        };
 
+       sdmmc1_b4_pins_b: sdmmc1-b4-1 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+                                <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+                                <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
+                                <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+                                <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+                       slew-rate = <1>;
+                       drive-push-pull;
+                       bias-disable;
+               };
+               pins2 {
+                       pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+                       slew-rate = <2>;
+                       drive-push-pull;
+                       bias-disable;
+               };
+       };
+
+       sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+                                <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+                                <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
+                                <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
+                       slew-rate = <1>;
+                       drive-push-pull;
+                       bias-disable;
+               };
+               pins2 {
+                       pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+                       slew-rate = <2>;
+                       drive-push-pull;
+                       bias-disable;
+               };
+               pins3 {
+                       pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+                       slew-rate = <1>;
+                       drive-open-drain;
+                       bias-disable;
+               };
+       };
+
+       sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 {
+               pins {
+                       pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+                                <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+                                <STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC1_D2 */
+                                <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+                                <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+                                <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+               };
+       };
+
        sdmmc1_dir_pins_a: sdmmc1-dir-0 {
                pins1 {
                        pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
@@ -1531,7 +1744,7 @@
                        drive-push-pull;
                        bias-pull-up;
                };
-               pins2{
+               pins2 {
                        pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
                        bias-pull-up;
                };
@@ -1566,7 +1779,7 @@
                        drive-push-pull;
                        bias-pull-up;
                };
-               pins2{
+               pins2 {
                        pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
                        bias-pull-up;
                };
@@ -1759,6 +1972,27 @@
                };
        };
 
+       sdmmc2_d47_pins_e: sdmmc2-d47-4 {
+               pins {
+                       pinmux = <STM32_PINMUX('A', 8, AF9)>,   /* SDMMC2_D4 */
+                                <STM32_PINMUX('A', 9, AF10)>,  /* SDMMC2_D5 */
+                                <STM32_PINMUX('C', 6, AF10)>,  /* SDMMC2_D6 */
+                                <STM32_PINMUX('D', 3, AF9)>;   /* SDMMC2_D7 */
+                       slew-rate = <1>;
+                       drive-push-pull;
+                       bias-pull-up;
+               };
+       };
+
+       sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 {
+               pins {
+                       pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
+                                <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
+                                <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
+                                <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
+               };
+       };
+
        sdmmc3_b4_pins_a: sdmmc3-b4-0 {
                pins1 {
                        pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
@@ -1925,6 +2159,20 @@
                };
        };
 
+       spi2_pins_c: spi2-2 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */
+                                <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
+                       bias-disable;
+                       drive-push-pull;
+               };
+
+               pins2 {
+                       pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
+                       bias-pull-down;
+               };
+       };
+
        spi4_pins_a: spi4-0 {
                pins {
                        pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
@@ -1939,6 +2187,21 @@
                };
        };
 
+       spi5_pins_a: spi5-0 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('F', 7, AF5)>, /* SPI5_SCK */
+                                <STM32_PINMUX('F', 9, AF5)>; /* SPI5_MOSI */
+                       bias-disable;
+                       drive-push-pull;
+                       slew-rate = <1>;
+               };
+
+               pins2 {
+                       pinmux = <STM32_PINMUX('F', 8, AF5)>; /* SPI5_MISO */
+                       bias-disable;
+               };
+       };
+
        stusb1600_pins_a: stusb1600-0 {
                pins {
                        pinmux = <STM32_PINMUX('I', 11, GPIO)>;
@@ -2124,6 +2387,33 @@
                };
        };
 
+       usart1_pins_a: usart1-0 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('A', 12, AF7)>; /* USART1_RTS */
+                       bias-disable;
+                       drive-push-pull;
+                       slew-rate = <0>;
+               };
+               pins2 {
+                       pinmux = <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
+                       bias-disable;
+               };
+       };
+
+       usart1_idle_pins_a: usart1-idle-0 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
+                                <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
+               };
+       };
+
+       usart1_sleep_pins_a: usart1-sleep-0 {
+               pins {
+                       pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
+                                <STM32_PINMUX('A', 11, ANALOG)>; /* USART1_CTS_NSS */
+               };
+       };
+
        usart2_pins_a: usart2-0 {
                pins1 {
                        pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
@@ -2226,6 +2516,23 @@
                };
        };
 
+       usart3_idle_pins_a: usart3-idle-0 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('B', 10, ANALOG)>; /* USART3_TX */
+               };
+               pins2 {
+                       pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
+                       bias-disable;
+               };
+       };
+
+       usart3_sleep_pins_a: usart3-sleep-0 {
+               pins {
+                       pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+                                <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
+               };
+       };
+
        usart3_pins_b: usart3-1 {
                pins1 {
                        pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
@@ -2385,6 +2692,21 @@
                };
        };
 
+       usart3_pins_f: usart3-5 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
+                                <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS */
+                       bias-disable;
+                       drive-push-pull;
+                       slew-rate = <0>;
+               };
+               pins2 {
+                       pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
+                                <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
+                       bias-disable;
+               };
+       };
+
        usbotg_hs_pins_a: usbotg-hs-0 {
                pins {
                        pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
@@ -2463,4 +2785,42 @@
                        bias-disable;
                };
        };
+
+       spi1_sleep_pins_a: spi1-sleep-0 {
+               pins {
+                       pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */
+                                <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
+                                <STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */
+               };
+       };
+
+       usart1_pins_b: usart1-1 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('Z', 7, AF7)>; /* USART1_TX */
+                       bias-disable;
+                       drive-push-pull;
+                       slew-rate = <0>;
+               };
+               pins2 {
+                       pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
+                       bias-disable;
+               };
+       };
+
+       usart1_idle_pins_b: usart1-idle-1 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('Z', 7, ANALOG)>; /* USART1_TX */
+               };
+               pins2 {
+                       pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
+                       bias-disable;
+               };
+       };
+
+       usart1_sleep_pins_b: usart1-sleep-1 {
+               pins {
+                       pinmux = <STM32_PINMUX('Z', 7, ANALOG)>, /* USART1_TX */
+                                <STM32_PINMUX('Z', 6, ANALOG)>; /* USART1_RX */
+               };
+       };
 };

diff --git a/arch/arm/dts/stm32mp15-scmi.dtsi b/arch/arm/dts/stm32mp15-scmi.dtsi
index ad25842..dc3b09f 100644 (file)
--- a/arch/arm/dts/stm32mp15-scmi.dtsi
+++ b/arch/arm/dts/stm32mp15-scmi.dtsi
@@ -34,22 +34,21 @@
                                        #address-cells = <1>;
                                        #size-cells = <0>;
 
-                                       scmi_reg11: reg11@0 {
+                                       scmi_reg11: regulator@0 {
                                                reg = <0>;
                                                regulator-name = "reg11";
                                                regulator-min-microvolt = <1100000>;
                                                regulator-max-microvolt = <1100000>;
                                        };
 
-                                       scmi_reg18: reg18@1 {
-                                               voltd-name = "reg18";
+                                       scmi_reg18: regulator@1 {
                                                reg = <1>;
                                                regulator-name = "reg18";
                                                regulator-min-microvolt = <1800000>;
                                                regulator-max-microvolt = <1800000>;
                                        };
 
-                                       scmi_usb33: usb33@2 {
+                                       scmi_usb33: regulator@2 {
                                                reg = <2>;
                                                regulator-name = "usb33";
                                                regulator-min-microvolt = <3300000>;

diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index 21d11be..e277140 100644 (file)
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -1111,6 +1111,8 @@
                        adc1: adc@0 {
                                compatible = "st,stm32mp1-adc";
                                #io-channel-cells = <1>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
                                reg = <0x0>;
                                interrupt-parent = <&adc>;
                                interrupts = <0>;
@@ -1122,12 +1124,24 @@
                        adc2: adc@100 {
                                compatible = "st,stm32mp1-adc";
                                #io-channel-cells = <1>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
                                reg = <0x100>;
                                interrupt-parent = <&adc>;
                                interrupts = <1>;
                                dmas = <&dmamux1 10 0x400 0x01>;
                                dma-names = "rx";
+                               nvmem-cells = <&vrefint>;
+                               nvmem-cell-names = "vrefint";
                                status = "disabled";
+                               channel@13 {
+                                       reg = <13>;
+                                       label = "vrefint";
+                               };
+                               channel@14 {
+                                       reg = <14>;
+                                       label = "vddcore";
+                               };
                        };
                };
 
@@ -1162,14 +1176,6 @@
                        status = "disabled";
                };
 
-               hwspinlock: hwspinlock@4c000000 {
-                       compatible = "st,stm32-hwspinlock";
-                       #hwlock-cells = <1>;
-                       reg = <0x4c000000 0x400>;
-                       clocks = <&rcc HSEM>;
-                       clock-names = "hwspinlock";
-               };
-
                ipcc: mailbox@4c001000 {
                        compatible = "st,stm32mp1-ipcc";
                        #mbox-cells = <1>;
@@ -1559,11 +1565,6 @@
                        clock-names = "lcd";
                        resets = <&rcc LTDC_R>;
                        status = "disabled";
-
-                       port {
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-                       };
                };
 
                iwdg2: watchdog@5a002000 {
@@ -1650,9 +1651,12 @@
                        reg = <0x5c005000 0x400>;
                        #address-cells = <1>;
                        #size-cells = <1>;
-                       part_number_otp: part_number_otp@4 {
+                       part_number_otp: part-number-otp@4 {
                                reg = <0x4 0x1>;
                        };
+                       vrefint: vrefin-cal@52 {
+                               reg = <0x52 0x2>;
+                       };
                        ts_cal1: calib@5c {
                                reg = <0x5c 0x2>;
                        };
@@ -1853,8 +1857,8 @@
                              <0x30000000 0x40000>,
                              <0x38000000 0x10000>;
                        resets = <&rcc MCU_R>;
+                       reset-names = "mcu_rst";
                        st,syscfg-holdboot = <&rcc 0x10C 0x1>;
-                       st,syscfg-tz = <&rcc 0x000 0x1>;
                        st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
                        st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
                        st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;

diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi
index 54e73cc..6197d87 100644 (file)
--- a/arch/arm/dts/stm32mp157.dtsi
+++ b/arch/arm/dts/stm32mp157.dtsi
@@ -22,15 +22,26 @@
                        reg = <0x5a000000 0x800>;
                        clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
                        clock-names = "pclk", "ref", "px_clk";
+                       phy-dsi-supply = <&reg18>;
                        resets = <&rcc DSI_R>;
                        reset-names = "apb";
-                       #address-cells = <1>;
-                       #size-cells = <0>;
                        status = "disabled";
 
                        ports {
                                #address-cells = <1>;
                                #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       dsi_in: endpoint {
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                                       dsi_out: endpoint {
+                                       };
+                               };
                        };
                };
        };

diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/dts/stm32mp157a-dk1-scmi.dts
index e539cc8..afcd628 100644 (file)
--- a/arch/arm/dts/stm32mp157a-dk1-scmi.dts
+++ b/arch/arm/dts/stm32mp157a-dk1-scmi.dts
@@ -55,8 +55,11 @@
        resets = <&scmi_reset RST_SCMI_MDMA>;
 };
 
-&mlahb {
-       resets = <&scmi_reset RST_SCMI_MCU>;
+&m4_rproc {
+       /delete-property/ st,syscfg-holdboot;
+       resets = <&scmi_reset RST_SCMI_MCU>,
+                <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
+       reset-names =  "mcu_rst", "hold_boot";
 };
 
 &rcc {

diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
index fae656e..f4a4942 100644 (file)
--- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
+++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
@@ -81,6 +81,9 @@
        status = "okay";
 
        port {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
                ltdc_ep0_out: endpoint@0 {
                        reg = <0>;
                        remote-endpoint = <&panel_in>;

diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/dts/stm32mp157c-dk2-scmi.dts
index 97e4f94..39358d9 100644 (file)
--- a/arch/arm/dts/stm32mp157c-dk2-scmi.dts
+++ b/arch/arm/dts/stm32mp157c-dk2-scmi.dts
@@ -61,8 +61,11 @@
        resets = <&scmi_reset RST_SCMI_MDMA>;
 };
 
-&mlahb {
-       resets = <&scmi_reset RST_SCMI_MCU>;
+&m4_rproc {
+       /delete-property/ st,syscfg-holdboot;
+       resets = <&scmi_reset RST_SCMI_MCU>,
+                <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
+       reset-names =  "mcu_rst", "hold_boot";
 };
 
 &rcc {

diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
index ab13e34..510cca5 100644 (file)
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/dts/stm32mp157c-dk2.dts
@@ -31,24 +31,9 @@
 };
 
 &dsi {
+       #address-cells = <1>;
+       #size-cells = <0>;
        status = "okay";
-       phy-dsi-supply = <&reg18>;
-
-       ports {
-               port@0 {
-                       reg = <0>;
-                       dsi_in: endpoint {
-                               remote-endpoint = <&ltdc_ep1_out>;
-                       };
-               };
-
-               port@1 {
-                       reg = <1>;
-                       dsi_out: endpoint {
-                               remote-endpoint = <&panel_in>;
-                       };
-               };
-       };
 
        panel@0 {
                compatible = "orisetech,otm8009a";
@@ -65,6 +50,14 @@
        };
 };
 
+&dsi_in {
+       remote-endpoint = <&ltdc_ep1_out>;
+};
+
+&dsi_out {
+       remote-endpoint = <&panel_in>;
+};
+
 &i2c1 {
        touchscreen@38 {
                compatible = "focaltech,ft6236";
@@ -82,6 +75,9 @@
        status = "okay";
 
        port {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
                ltdc_ep1_out: endpoint@1 {
                        reg = <1>;
                        remote-endpoint = <&dsi_in>;

diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/dts/stm32mp157c-ed1-scmi.dts
index 9cf0a44..07ea765 100644 (file)
--- a/arch/arm/dts/stm32mp157c-ed1-scmi.dts
+++ b/arch/arm/dts/stm32mp157c-ed1-scmi.dts
@@ -60,8 +60,11 @@
        resets = <&scmi_reset RST_SCMI_MDMA>;
 };
 
-&mlahb {
-       resets = <&scmi_reset RST_SCMI_MCU>;
+&m4_rproc {
+       /delete-property/ st,syscfg-holdboot;
+       resets = <&scmi_reset RST_SCMI_MCU>,
+                <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
+       reset-names =  "mcu_rst", "hold_boot";
 };
 
 &rcc {

diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index 3541a17..66ed5f9 100644 (file)
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -103,21 +103,23 @@
        vref-supply = <&vdda>;
        status = "disabled";
        adc1: adc@0 {
-               st,adc-channels = <0 1 6>;
-               /* 16.5 ck_cycles sampling time */
-               st,min-sample-time-nsecs = <400>;
                status = "okay";
+               channel@0 {
+                       reg = <0>;
+                       /* 16.5 ck_cycles sampling time */
+                       st,min-sample-time-ns = <400>;
+               };
+               channel@1 {
+                       reg = <1>;
+                       st,min-sample-time-ns = <400>;
+               };
+               channel@6 {
+                       reg = <6>;
+                       st,min-sample-time-ns = <400>;
+               };
        };
 };
 
-&cpu0{
-       cpu-supply = <&vddcore>;
-};
-
-&cpu1{
-       cpu-supply = <&vddcore>;
-};
-
 &crc1 {
        status = "okay";
 };

diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/dts/stm32mp157c-ev1-scmi.dts
index 3b9dd6f..813086e 100644 (file)
--- a/arch/arm/dts/stm32mp157c-ev1-scmi.dts
+++ b/arch/arm/dts/stm32mp157c-ev1-scmi.dts
@@ -66,8 +66,11 @@
        resets = <&scmi_reset RST_SCMI_MDMA>;
 };
 
-&mlahb {
-       resets = <&scmi_reset RST_SCMI_MCU>;
+&m4_rproc {
+       /delete-property/ st,syscfg-holdboot;
+       resets = <&scmi_reset RST_SCMI_MCU>,
+                <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
+       reset-names =  "mcu_rst", "hold_boot";
 };
 
 &rcc {

diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
index ba8e9d9..cd9c3ff 100644 (file)
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/dts/stm32mp157c-ev1.dts
@@ -100,26 +100,11 @@
 };
 
 &dsi {
-       phy-dsi-supply = <&reg18>;
+       #address-cells = <1>;
+       #size-cells = <0>;
        status = "okay";
 
-       ports {
-               port@0 {
-                       reg = <0>;
-                       dsi_in: endpoint {
-                               remote-endpoint = <&ltdc_ep0_out>;
-                       };
-               };
-
-               port@1 {
-                       reg = <1>;
-                       dsi_out: endpoint {
-                               remote-endpoint = <&dsi_panel_in>;
-                       };
-               };
-       };
-
-       panel-dsi@0 {
+       panel@0 {
                compatible = "raydium,rm68200";
                reg = <0>;
                reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
@@ -135,6 +120,14 @@
        };
 };
 
+&dsi_in {
+       remote-endpoint = <&ltdc_ep0_out>;
+};
+
+&dsi_out {
+       remote-endpoint = <&dsi_panel_in>;
+};
+
 &ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rgmii_pins_a>;
@@ -185,7 +178,9 @@
                reg = <0x3c>;
                clocks = <&clk_ext_camera>;
                clock-names = "xclk";
+               AVDD-supply = <&v2v8>;
                DOVDD-supply = <&v2v8>;
+               DVDD-supply = <&v2v8>;
                powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
                reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
                rotation = <180>;
@@ -239,8 +234,7 @@
        status = "okay";
 
        port {
-               ltdc_ep0_out: endpoint@0 {
-                       reg = <0>;
+               ltdc_ep0_out: endpoint {
                        remote-endpoint = <&dsi_in>;
                };
        };

diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi
index f4de6c0..511113f 100644 (file)
--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi
@@ -93,28 +93,39 @@
 
 &adc {
        pinctrl-names = "default";
-       pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
+       pinctrl-0 = <&adc12_usb_cc_pins_a>;
        vdd-supply = <&vdd>;
        vdda-supply = <&vdd>;
        vref-supply = <&vrefbuf>;
-       status = "disabled";
+       status = "okay";
        adc1: adc@0 {
+               status = "okay";
                /*
                 * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
                 * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
                 * 5 * (56 + 47kOhms) * 5pF => 2.5us.
                 * Use arbitrary margin here (e.g. 5us).
                 */
-               st,min-sample-time-nsecs = <5000>;
-               /* AIN connector, USB Type-C CC1 & CC2 */
-               st,adc-channels = <0 1 6 13 18 19>;
-               status = "okay";
+               channel@18 {
+                       reg = <18>;
+                       st,min-sample-time-ns = <5000>;
+               };
+               channel@19 {
+                       reg = <19>;
+                       st,min-sample-time-ns = <5000>;
+               };
        };
        adc2: adc@100 {
-               /* AIN connector, USB Type-C CC1 & CC2 */
-               st,adc-channels = <0 1 2 6 18 19>;
-               st,min-sample-time-nsecs = <5000>;
                status = "okay";
+               /* USB Type-C CC1 & CC2 */
+               channel@18 {
+                       reg = <18>;
+                       st,min-sample-time-ns = <5000>;
+               };
+               channel@19 {
+                       reg = <19>;
+                       st,min-sample-time-ns = <5000>;
+               };
        };
 };
 
@@ -133,14 +144,6 @@
        status = "okay";
 };
 
-&cpu0{
-       cpu-supply = <&vddcore>;
-};
-
-&cpu1{
-       cpu-supply = <&vddcore>;
-};
-
 &ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rgmii_pins_a>;
@@ -443,7 +446,7 @@
        i2s2_port: port {
                i2s2_endpoint: endpoint {
                        remote-endpoint = <&sii9022_tx_endpoint>;
-                       format = "i2s";
+                       dai-format = "i2s";
                        mclk-fs = <256>;
                };
        };
@@ -465,8 +468,7 @@
        status = "okay";
 
        port {
-               ltdc_ep0_out: endpoint@0 {
-                       reg = <0>;
+               ltdc_ep0_out: endpoint {
                        remote-endpoint = <&sii9022_in>;
                };
        };

diff --git a/arch/arm/mach-k3/j721e/dev-data.c b/arch/arm/mach-k3/j721e/dev-data.c
index 97f017f..b0adb18 100644 (file)
--- a/arch/arm/mach-k3/j721e/dev-data.c
+++ b/arch/arm/mach-k3/j721e/dev-data.c
@@ -56,6 +56,7 @@ static struct ti_dev soc_dev_list[] = {
        PSC_DEV(4, &soc_lpsc_list[8]),
        PSC_DEV(202, &soc_lpsc_list[9]),
        PSC_DEV(203, &soc_lpsc_list[10]),
+       PSC_DEV(35, &soc_lpsc_list[11]),
        PSC_DEV(102, &soc_lpsc_list[11]),
        PSC_DEV(103, &soc_lpsc_list[11]),
        PSC_DEV(104, &soc_lpsc_list[11]),

diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index b616457..b1f7e25 100644 (file)
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -228,6 +228,18 @@ void board_init_f(ulong dummy)
        if (!ret)
                pinctrl_select_state(dev, "default");
 
+       /*
+        * Force probe of clk_k3 driver here to ensure basic default clock
+        * configuration is always done.
+        */
+       if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
+               ret = uclass_get_device_by_driver(UCLASS_CLK,
+                                                 DM_DRIVER_GET(ti_clk),
+                                                 &dev);
+               if (ret)
+                       panic("Failed to initialize clk-k3!\n");
+       }
+
        /*
         * Load, start up, and configure system controller firmware. Provide
         * the U-Boot console init function to the SYSFW post-PM configuration
@@ -241,18 +253,6 @@ void board_init_f(ulong dummy)
        do_dt_magic();
 #endif
 
-       /*
-        * Force probe of clk_k3 driver here to ensure basic default clock
-        * configuration is always done.
-        */
-       if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
-               ret = uclass_get_device_by_driver(UCLASS_CLK,
-                                                 DM_DRIVER_GET(ti_clk),
-                                                 &dev);
-               if (ret)
-                       panic("Failed to initialize clk-k3!\n");
-       }
-
        /* Prepare console output */
        preloader_console_init();
 

diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index 341d095..d1f662d 100644 (file)
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -230,8 +230,9 @@ static void board_get_coding_straps(void)
 
        gpio_free_list_nodev(gpio, ret);
 
-       printf("Code:  SoM:rev=%d,ddr3=%d Board:rev=%d\n",
-               somcode, ddr3code, brdcode);
+       if (CONFIG_IS_ENABLED(DISPLAY_PRINT))
+               printf("Code:  SoM:rev=%d,ddr3=%d Board:rev=%d\n",
+                      somcode, ddr3code, brdcode);
 }
 
 int board_stm32mp1_ddr_config_name_match(struct udevice *dev,

diff --git a/board/st/common/Makefile b/board/st/common/Makefile
index c960829..b01245e 100644 (file)
--- a/board/st/common/Makefile
+++ b/board/st/common/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
 
 ifeq ($(CONFIG_ARCH_STM32MP),y)
 obj-$(CONFIG_SET_DFU_ALT_INFO) += stm32mp_dfu.o
+obj-$(CONFIG_$(SPL_)DFU_VIRT) += stm32mp_dfu_virt.o
 endif
 
 obj-$(CONFIG_TYPEC_STUSB160X) += stusb160x.o

diff --git a/board/st/common/stm32mp_dfu.c b/board/st/common/stm32mp_dfu.c
index faee953..a8eb8d5 100644 (file)
--- a/board/st/common/stm32mp_dfu.c
+++ b/board/st/common/stm32mp_dfu.c
@@ -148,108 +148,14 @@ void set_dfu_alt_info(char *interface, char *devstr)
                        board_get_alt_info_mtd(mtd, buf);
        }
 
-       if (IS_ENABLED(CONFIG_DFU_VIRT) &&
-           IS_ENABLED(CMD_STM32PROG_USB)) {
-               strncat(buf, "&virt 0=OTP", DFU_ALT_BUF_LEN);
+       if (IS_ENABLED(CONFIG_DFU_VIRT)) {
+               /* virtual device id 0 is aligned with stm32mp_dfu_virt.c */
+               strlcat(buf, "&virt 0=OTP", DFU_ALT_BUF_LEN);
 
                if (IS_ENABLED(CONFIG_PMIC_STPMIC1))
-                       strncat(buf, "&virt 1=PMIC", DFU_ALT_BUF_LEN);
+                       strlcat(buf, "&virt 1=PMIC", DFU_ALT_BUF_LEN);
        }
 
        env_set("dfu_alt_info", buf);
        puts("DFU alt info setting: done\n");
 }
-
-#if CONFIG_IS_ENABLED(DFU_VIRT)
-#include <dfu.h>
-#include <power/stpmic1.h>
-
-static int dfu_otp_read(u64 offset, u8 *buffer, long *size)
-{
-       struct udevice *dev;
-       int ret;
-
-       ret = uclass_get_device_by_driver(UCLASS_MISC,
-                                         DM_DRIVER_GET(stm32mp_bsec),
-                                         &dev);
-       if (ret)
-               return ret;
-
-       ret = misc_read(dev, offset + STM32_BSEC_OTP_OFFSET, buffer, *size);
-       if (ret >= 0) {
-               *size = ret;
-               ret = 0;
-       }
-
-       return 0;
-}
-
-static int dfu_pmic_read(u64 offset, u8 *buffer, long *size)
-{
-       int ret;
-#ifdef CONFIG_PMIC_STPMIC1
-       struct udevice *dev;
-
-       ret = uclass_get_device_by_driver(UCLASS_MISC,
-                                         DM_DRIVER_GET(stpmic1_nvm),
-                                         &dev);
-       if (ret)
-               return ret;
-
-       ret = misc_read(dev, 0xF8 + offset, buffer, *size);
-       if (ret >= 0) {
-               *size = ret;
-               ret = 0;
-       }
-       if (ret == -EACCES) {
-               *size = 0;
-               ret = 0;
-       }
-#else
-       log_err("PMIC update not supported");
-       ret = -EOPNOTSUPP;
-#endif
-
-       return ret;
-}
-
-int dfu_read_medium_virt(struct dfu_entity *dfu, u64 offset,
-                        void *buf, long *len)
-{
-       switch (dfu->data.virt.dev_num) {
-       case 0x0:
-               return dfu_otp_read(offset, buf, len);
-       case 0x1:
-               return dfu_pmic_read(offset, buf, len);
-       }
-
-       if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
-           dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
-               return stm32prog_read_medium_virt(dfu, offset, buf, len);
-
-       *len = 0;
-       return 0;
-}
-
-int dfu_write_medium_virt(struct dfu_entity *dfu, u64 offset,
-                         void *buf, long *len)
-{
-       if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
-           dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
-               return stm32prog_write_medium_virt(dfu, offset, buf, len);
-
-       return -EOPNOTSUPP;
-}
-
-int __weak dfu_get_medium_size_virt(struct dfu_entity *dfu, u64 *size)
-{
-       if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
-           dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
-               return stm32prog_get_medium_size_virt(dfu, size);
-
-       *size = SZ_1K;
-
-       return 0;
-}
-
-#endif

diff --git a/board/st/common/stm32mp_dfu_virt.c b/board/st/common/stm32mp_dfu_virt.c
new file mode 100644 (file)
index 0000000..f0f9960
--- /dev/null
+++ b/board/st/common/stm32mp_dfu_virt.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <dfu.h>
+#include <dm.h>
+#include <misc.h>
+#include <asm/arch/stm32prog.h>
+#include <power/stpmic1.h>
+
+static int dfu_otp_read(u64 offset, u8 *buffer, long *size)
+{
+       struct udevice *dev;
+       int ret;
+
+       ret = uclass_get_device_by_driver(UCLASS_MISC,
+                                         DM_DRIVER_GET(stm32mp_bsec),
+                                         &dev);
+       if (ret)
+               return ret;
+
+       ret = misc_read(dev, offset + STM32_BSEC_OTP_OFFSET, buffer, *size);
+       if (ret >= 0) {
+               *size = ret;
+               ret = 0;
+       }
+
+       return 0;
+}
+
+static int dfu_pmic_read(u64 offset, u8 *buffer, long *size)
+{
+       int ret;
+       struct udevice *dev;
+
+       if (!IS_ENABLED(CONFIG_PMIC_STPMIC1)) {
+               log_err("PMIC update not supported");
+               return -EOPNOTSUPP;
+       }
+
+       ret = uclass_get_device_by_driver(UCLASS_MISC,
+                                         DM_DRIVER_GET(stpmic1_nvm),
+                                         &dev);
+       if (ret)
+               return ret;
+
+       ret = misc_read(dev, 0xF8 + offset, buffer, *size);
+       if (ret >= 0) {
+               *size = ret;
+               ret = 0;
+       }
+       if (ret == -EACCES) {
+               *size = 0;
+               ret = 0;
+       }
+
+       return ret;
+}
+
+int dfu_read_medium_virt(struct dfu_entity *dfu, u64 offset,
+                        void *buf, long *len)
+{
+       switch (dfu->data.virt.dev_num) {
+       case 0x0:
+               return dfu_otp_read(offset, buf, len);
+       case 0x1:
+               return dfu_pmic_read(offset, buf, len);
+       }
+
+       if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
+           dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
+               return stm32prog_read_medium_virt(dfu, offset, buf, len);
+
+       *len = 0;
+       return 0;
+}
+
+int dfu_write_medium_virt(struct dfu_entity *dfu, u64 offset,
+                         void *buf, long *len)
+{
+       if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
+           dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
+               return stm32prog_write_medium_virt(dfu, offset, buf, len);
+
+       return -EOPNOTSUPP;
+}
+
+int dfu_get_medium_size_virt(struct dfu_entity *dfu, u64 *size)
+{
+       if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
+           dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
+               return stm32prog_get_medium_size_virt(dfu, size);
+
+       *size = SZ_1K;
+
+       return 0;
+}

diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 4cfb29e..0f96660 100644 (file)
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -14,7 +14,6 @@
 #include <serial.h>
 #include <spl.h>
 #include <splash.h>
-#include <st_logo_data.h>
 #include <video.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
@@ -134,10 +133,5 @@ int board_init(void)
        }
 #endif
 
-#if defined(CONFIG_CMD_BMP)
-       bmp_display((ulong)stmicroelectronics_uboot_logo_8bit_rle,
-                   BMP_ALIGN_CENTER, BMP_ALIGN_CENTER);
-#endif /* CONFIG_CMD_BMP */
-
        return 0;
 }

diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index b685c1f..25a1033 100644 (file)
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -140,7 +140,6 @@ CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
-CONFIG_HBMC_AM654=y
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y

diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index cf7bc87..d974be2 100644 (file)
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -127,7 +127,6 @@ CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
-CONFIG_HBMC_AM654=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_STMICRO=y

diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 1fb30d8..3c3a0d2 100644 (file)
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -56,13 +56,13 @@ CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_STM32_QSPI=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
 CONFIG_BACKLIGHT_GPIO=y
 CONFIG_VIDEO_STM32=y
 CONFIG_VIDEO_STM32_MAX_XRES=480
-CONFIG_VIDEO_STM32_MAX_YRES=640
+CONFIG_VIDEO_STM32_MAX_YRES=272
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_VIDEO_BMP_RLE8=y
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y

diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig
index 25ea254..1b8b5a1 100644 (file)
--- a/configs/stm32f746-disco_spl_defconfig
+++ b/configs/stm32f746-disco_spl_defconfig
@@ -82,13 +82,13 @@ CONFIG_DM_SPI=y
 CONFIG_STM32_QSPI=y
 CONFIG_SPL_TIMER=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
 CONFIG_BACKLIGHT_GPIO=y
 CONFIG_VIDEO_STM32=y
 CONFIG_VIDEO_STM32_MAX_XRES=480
-CONFIG_VIDEO_STM32_MAX_YRES=640
+CONFIG_VIDEO_STM32_MAX_YRES=272
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_VIDEO_BMP_RLE8=y
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y

diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig
index a92032d..3514a78 100644 (file)
--- a/configs/stm32f769-disco_defconfig
+++ b/configs/stm32f769-disco_defconfig
@@ -56,6 +56,7 @@ CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_STM32_QSPI=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
 CONFIG_BACKLIGHT_GPIO=y
 CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
 CONFIG_VIDEO_STM32=y
@@ -64,7 +65,6 @@ CONFIG_VIDEO_STM32_MAX_XRES=480
 CONFIG_VIDEO_STM32_MAX_YRES=800
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_VIDEO_BMP_RLE8=y
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y

diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig
index deb7963..9b926b2 100644 (file)
--- a/configs/stm32f769-disco_spl_defconfig
+++ b/configs/stm32f769-disco_spl_defconfig
@@ -82,6 +82,7 @@ CONFIG_DM_SPI=y
 CONFIG_STM32_QSPI=y
 CONFIG_SPL_TIMER=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
 CONFIG_BACKLIGHT_GPIO=y
 CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
 CONFIG_VIDEO_STM32=y
@@ -90,7 +91,6 @@ CONFIG_VIDEO_STM32_MAX_XRES=480
 CONFIG_VIDEO_STM32_MAX_YRES=800
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_VIDEO_BMP_RLE8=y
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y

diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig
index 4e83753..387dc6a 100644 (file)
--- a/configs/stm32mp13_defconfig
+++ b/configs/stm32mp13_defconfig
@@ -10,6 +10,7 @@ CONFIG_DDR_CACHEABLE_SIZE=0x8000000
 CONFIG_CMD_STM32KEY=y
 CONFIG_TARGET_ST_STM32MP13x=y
 CONFIG_ENV_OFFSET_REDUND=0x940000
+CONFIG_CMD_STM32PROG=y
 # CONFIG_ARMV7_NONSEC is not set
 CONFIG_SYS_LOAD_ADDR=0xc2000000
 CONFIG_SYS_MEMTEST_START=0xc0000000
@@ -32,6 +33,8 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_LSBLK=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_TIME=y
@@ -49,6 +52,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_DEV=-1
 CONFIG_ENV_MMC_USE_DT=y
 CONFIG_CLK_SCMI=y
+CONFIG_SET_DFU_ALT_INFO=y
 CONFIG_GPIO_HOG=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_STM32F7=y
@@ -58,6 +62,8 @@ CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_STM32_SDMMC2=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
+CONFIG_PHY=y
+CONFIG_PHY_STM32_USBPHYC=y
 CONFIG_PINCONF=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
@@ -65,6 +71,7 @@ CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_REGULATOR_SCMI=y
 CONFIG_RESET_SCMI=y
 CONFIG_DM_RNG=y
+CONFIG_RNG_STM32=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_STM32=y
 CONFIG_SERIAL_RX_BUFFER=y
@@ -72,6 +79,20 @@ CONFIG_SYSRESET_PSCI=y
 CONFIG_TEE=y
 CONFIG_OPTEE=y
 # CONFIG_OPTEE_TA_AVB is not set
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_ONBOARD_HUB=y
+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0483
+CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_ERRNO_STR=y
 # CONFIG_LMB_USE_MAX_REGIONS is not set
 CONFIG_LMB_MEMORY_REGIONS=2

diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index af008c8..67258e2 100644 (file)
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -150,7 +150,7 @@ CONFIG_DM_REGULATOR_STM32_VREFBUF=y
 CONFIG_DM_REGULATOR_STPMIC1=y
 CONFIG_REMOTEPROC_STM32_COPRO=y
 CONFIG_DM_RNG=y
-CONFIG_RNG_STM32MP1=y
+CONFIG_RNG_STM32=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_STM32=y
 CONFIG_SERIAL_RX_BUFFER=y

diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig
index d279071..261557b 100644 (file)
--- a/configs/stm32mp15_defconfig
+++ b/configs/stm32mp15_defconfig
@@ -123,7 +123,7 @@ CONFIG_DM_REGULATOR_SCMI=y
 CONFIG_REMOTEPROC_STM32_COPRO=y
 CONFIG_RESET_SCMI=y
 CONFIG_DM_RNG=y
-CONFIG_RNG_STM32MP1=y
+CONFIG_RNG_STM32=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_STM32=y
 CONFIG_SERIAL_RX_BUFFER=y

diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 85cb132..5a031e7 100644 (file)
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -123,7 +123,7 @@ CONFIG_DM_REGULATOR_STPMIC1=y
 CONFIG_REMOTEPROC_STM32_COPRO=y
 CONFIG_RESET_SCMI=y
 CONFIG_DM_RNG=y
-CONFIG_RNG_STM32MP1=y
+CONFIG_RNG_STM32=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_STM32=y
 CONFIG_SERIAL_RX_BUFFER=y

diff --git a/doc/develop/index.rst b/doc/develop/index.rst
index 0d12484..003cdfc 100644 (file)
--- a/doc/develop/index.rst
+++ b/doc/develop/index.rst
@@ -88,7 +88,7 @@ Refactoring
 
    checkpatch
    coccinelle
-   moveconfig
+   qconfig
 
 Code quality
 ------------

diff --git a/doc/develop/moveconfig.rst b/doc/develop/qconfig.rst
similarity index 59%
rename from doc/develop/moveconfig.rst
rename to doc/develop/qconfig.rst
index ad8596e..8efb1eb 100644 (file)
--- a/doc/develop/moveconfig.rst
+++ b/doc/develop/qconfig.rst
@@ -1,148 +1,87 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-moveconfig - Migrating and querying CONFIG options
-==================================================
+qconfig - Querying CONFIG options
+=================================
 
-Since Kconfig was introduced to U-Boot, we have worked on moving
-config options from headers to Kconfig (defconfig).
+It is not possible to see all the CONFIG options used by a board without
+building its `.config` file. This tool allows this to be done efficiently for
+all boards, or a subset, writing the results to a unified database file.
 
-This tool intends to help this tremendous work.
+This database can be queried, to find boards which used a certain combination
+of options, to aid in discovering Kconfig options which imply others.
 
-Installing
-----------
-
-You may need to install 'python3-asteval' for the 'asteval' module.
-
-Usage
------
-
-First, you must edit the Kconfig to add the menu entries for the configs
-you are moving.
-
-Then run this tool giving CONFIG names you want to move.
-For example, if you want to move CONFIG_CMD_USB and CONFIG_TEXT_BASE,
-simply type as follows::
-
-  $ tools/moveconfig.py CONFIG_CMD_USB CONFIG_TEXT_BASE
-
-The tool walks through all the defconfig files and move the given CONFIGs.
-
-The log is also displayed on the terminal.
-
-The log is printed for each defconfig as follows::
-
-  <defconfig_name>
-     <action1>
-     <action2>
-     <action3>
-     ...
-
-`<defconfig_name>` is the name of the defconfig.
-
-`<action*>` shows what the tool did for that defconfig.
-It looks like one of the following:
+The tool also permits syncing of defconfigs, which corrects the ordering and
+drops options which are implied by others.
 
- - Move 'CONFIG\_... '
-   This config option was moved to the defconfig
+Finally, it allows scanning the source code to look for inconsistencies in the
+use of Kconfig options.
 
- - CONFIG\_... is not defined in Kconfig.  Do nothing.
-   The entry for this CONFIG was not found in Kconfig.  The option is not
-   defined in the config header, either.  So, this case can be just skipped.
-
- - CONFIG\_... is not defined in Kconfig (suspicious).  Do nothing.
-   This option is defined in the config header, but its entry was not found
-   in Kconfig.
-   There are two common cases:
-
-     - You forgot to create an entry for the CONFIG before running
-       this tool, or made a typo in a CONFIG passed to this tool.
-     - The entry was hidden due to unmet 'depends on'.
-
-   The tool does not know if the result is reasonable, so please check it
-   manually.
-
- - 'CONFIG\_...' is the same as the define in Kconfig.  Do nothing.
-   The define in the config header matched the one in Kconfig.
-   We do not need to touch it.
-
- - Compiler is missing.  Do nothing.
-   The compiler specified for this architecture was not found
-   in your PATH environment.
-   (If -e option is passed, the tool exits immediately.)
-
- - Failed to process.
-   An error occurred during processing this defconfig.  Skipped.
-   (If -e option is passed, the tool exits immediately on error.)
-
-Finally, you will be asked, Clean up headers? [y/n]:
-
-If you say 'y' here, the unnecessary config defines are removed
-from the config headers (include/configs/\*.h).
-It just uses the regex method, so you should not rely on it.
-Just in case, please do 'git diff' to see what happened.
+Installation
+------------
 
+You may need to install 'python3-asteval' for the 'asteval' module.
 
 How does it work?
 -----------------
 
-This tool runs configuration and builds include/autoconf.mk for every
-defconfig.  The config options defined in Kconfig appear in the .config
-file (unless they are hidden because of unmet dependency.)
+When building a database (`-b`), this tool runs configuration and builds
+include/autoconf.mk for every defconfig.  The config options defined in Kconfig
+appear in the .config file (unless they are hidden because of unmet dependency.)
 On the other hand, the config options defined by board headers are seen
-in include/autoconf.mk.  The tool looks for the specified options in both
-of them to decide the appropriate action for the options.  If the given
-config option is found in the .config, but its value does not match the
-one from the board header, the config option in the .config is replaced
-with the define in the board header.  Then, the .config is synced by
-"make savedefconfig" and the defconfig is updated with it.
-
-For faster processing, this tool handles multi-threading.  It creates
+in include/autoconf.mk.
+
+When resyncing defconfigs (`-s`) the .config is synced by "make savedefconfig"
+and the defconfig is updated with it.
+
+For faster processing, this tool is multi-threaded.  It creates
 separate build directories where the out-of-tree build is run.  The
 temporary build directories are automatically created and deleted as
 needed.  The number of threads are chosen based on the number of the CPU
 cores of your system although you can change it via -j (--jobs) option.
 
+Note that `*.config` fragments are not supported.
 
 Toolchains
 ----------
 
-Appropriate toolchain are necessary to generate include/autoconf.mk
+Appropriate toolchains are necessary to generate include/autoconf.mk
 for all the architectures supported by U-Boot.  Most of them are available
-at the kernel.org site, some are not provided by kernel.org. This tool uses
-the same tools as buildman, so see that tool for setup (e.g. --fetch-arch).
+at the kernel.org site. This tool uses the same tools as
+:doc:`../build/buildman`, so you can use `buildman --fetch-arch` to fetch
+toolchains.
 
 
-Tips and trips
---------------
+Examples
+--------
 
 To sync only X86 defconfigs::
 
-   ./tools/moveconfig.py -s -d <(grep -l X86 configs/*)
+   ./tools/qconfig.py -s -d <(grep -l X86 configs/*)
 
 or::
 
-   grep -l X86 configs/* | ./tools/moveconfig.py -s -d -
+   grep -l X86 configs/* | ./tools/qconfig.py -s -d -
 
 To process CONFIG_CMD_FPGAD only for a subset of configs based on path match::
 
    ls configs/{hrcon*,iocon*,strider*} | \
-       ./tools/moveconfig.py -Cy CONFIG_CMD_FPGAD -d -
+       ./tools/qconfig.py -C CONFIG_CMD_FPGAD -d -
 
 
 Finding boards with particular CONFIG combinations
 --------------------------------------------------
 
-You can use `moveconfig.py` to figure out which boards have a CONFIG enabled, or
+You can use `qconfig.py` to figure out which boards have a CONFIG enabled, or
 which do not. To use it, first build a database::
 
-    ./tools/moveconfig.py -b
+    ./tools/qconfig.py -b
 
 Then you can run queries using the `-f` flag followed by a list of CONFIG terms.
 Each term is CONFIG name, with or without a tilde (~) prefix. The tool searches
 for boards which match the CONFIG name, or do not match if tilde is used. For
 example, to find boards which enabled CONFIG_SCSI but not CONFIG_BLK::
 
-    tools/moveconfig.py -f SCSI ~BLK
+    tools/qconfig.py -f SCSI ~BLK
     3 matches
     pg_wcom_seli8_defconfig highbank_defconfig pg_wcom_expu1_defconfig
 
@@ -158,11 +97,11 @@ each of the x86 defconfig files.
 
 This tool can help find such configs. To use it, first build a database::
 
-    ./tools/moveconfig.py -b
+    ./tools/qconfig.py -b
 
 Then try to query it::
 
-   ./tools/moveconfig.py -i CONFIG_I8042_KEYB
+   ./tools/qconfig.py -i CONFIG_I8042_KEYB
    CONFIG_I8042_KEYB found in 33/5155 defconfigs
    28 : CONFIG_X86
    28 : CONFIG_SA_PCIEX_LENGTH
@@ -193,12 +132,12 @@ indicates that CONFIG_I8042_KEYB is not needed for the remaining 5 boards. Many
 of the options listed are not suitable as they are not related. E.g. it would be
 odd for CONFIG_RAMBASE to imply CONFIG_I8042_KEYB.
 
-Using this search you can reduce the size of moveconfig patches.
+Using this search you can reduce the size of qconfig patches.
 
 You can automatically add 'imply' statements in the Kconfig with the -a
 option::
 
-    ./tools/moveconfig.py -s -i CONFIG_SCSI \
+    ./tools/qconfig.py -s -i CONFIG_SCSI \
             -a CONFIG_ARCH_LS1021A,CONFIG_ARCH_LS1043A
 
 This will add 'imply SCSI' to the two CONFIG options mentioned, assuming that
@@ -220,7 +159,7 @@ the size of their defconfig files.
 
 If you want to add an 'imply' to every imply config in the list, you can use::
 
-    ./tools/moveconfig.py -s -i CONFIG_SCSI -a all
+    ./tools/qconfig.py -s -i CONFIG_SCSI -a all
 
 To control which ones are displayed, use -I <list> where list is a list of
 options (use '-I help' to see possible options and their meaning).
@@ -230,7 +169,7 @@ To skip showing you options that already have an 'imply' attached, use -A.
 When you have finished adding 'imply' options you can regenerate the
 defconfig files for affected boards with something like::
 
-    git show --stat | ./tools/moveconfig.py -s -d -
+    git show --stat | ./tools/qconfig.py -s -d -
 
 This will regenerate only those defconfigs changed in the current commit.
 If you start with (say) 100 defconfigs being changed in the commit, and add
@@ -241,9 +180,9 @@ number of defconfigs changed in the commit.
 Available options
 -----------------
 
- -c, --color
-   Surround each portion of the log with escape sequences to display it
-   in color on the terminal.
+ --nocolour
+   Disables colouring of output. This is normally used when writing to a
+   terminal.
 
  -C, --commit
    Create a git commit with the changes when the operation is complete. A
@@ -275,9 +214,6 @@ Available options
    because SPL related options (mostly prefixed with CONFIG_SPL\_) are
    sometimes blocked by CONFIG_SPL_BUILD ifdef conditionals.
 
- -H, --headers-only
-   Only cleanup the headers; skip the defconfig processing
-
  -j, --jobs
    Specify the number of threads to run simultaneously.  If not specified,
    the number of threads is the same as the number of CPU cores.
@@ -293,10 +229,6 @@ Available options
  -v, --verbose
    Show any build errors as boards are built
 
- -y, --yes
-   Instead of prompting, automatically go ahead with all operations. This
-   includes cleaning up headers, the config whitelist and the README.
-
 To see the complete list of supported options, run::
 
-  tools/moveconfig.py -h
+  tools/qconfig.py -h

diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c
index 6150287..f3ac8c7 100644 (file)
--- a/drivers/clk/stm32/clk-stm32mp1.c
+++ b/drivers/clk/stm32/clk-stm32mp1.c
@@ -72,6 +72,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define RCC_PLL2CSGR           0xA4
 #define RCC_I2C46CKSELR                0xC0
 #define RCC_SPI6CKSELR         0xC4
+#define RCC_UART1CKSELR                0xC8
 #define RCC_CPERCKSELR         0xD0
 #define RCC_STGENCKSELR                0xD4
 #define RCC_DDRITFCR           0xD8
@@ -317,6 +318,7 @@ enum stm32mp1_parent_sel {
        _SPI45_SEL,
        _SPI6_SEL,
        _RTC_SEL,
+       _UART1_SEL,
        _PARENT_SEL_NB,
        _UNKNOWN_SEL = 0xff,
 };
@@ -557,6 +559,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
        STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
        STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
        STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL),
        STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
        STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 16, BSEC, _UNKNOWN_SEL),
        STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
@@ -602,6 +605,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
+static const u8 uart1_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER,
+                                       _PLL4_Q, _HSE_KER};
 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
                                        _HSE_KER};
 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
@@ -659,6 +664,7 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
        STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
                            (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
                            rtc_parents),
+       STM32MP1_CLK_PARENT(_UART1_SEL, RCC_UART1CKSELR, 0, 0x7, uart1_parents),
 };
 
 #ifdef STM32MP1_CLOCK_TREE_INIT
@@ -786,6 +792,7 @@ char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
        [_SPI1_SEL] = "SPI1",
        [_SPI45_SEL] = "SPI45",
        [_RTC_SEL] = "RTC",
+       [_UART1_SEL] = "UART1",
 };
 
 static const struct stm32mp1_clk_data stm32mp1_data = {

diff --git a/drivers/core/dump.c b/drivers/core/dump.c
index 4023b39..8411248 100644 (file)
--- a/drivers/core/dump.c
+++ b/drivers/core/dump.c
@@ -90,9 +90,8 @@ static void dm_dump_tree_single(struct udevice *dev, bool sort)
        int dev_count, uclasses;
        struct udevice **devs = NULL;
 
-       dm_get_stats(&dev_count, &uclasses);
-
        if (sort) {
+               dm_get_stats(&dev_count, &uclasses);
                devs = calloc(dev_count, sizeof(struct udevice *));
                if (!devs) {
                        printf("(out of memory)\n");

diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 72f572d..166bd78 100644 (file)
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -2690,6 +2690,8 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
 const
 struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct udevice *sci_dev)
 {
+       int ret;
+
        if (!sci_dev)
                return ERR_PTR(-EINVAL);
 
@@ -2703,6 +2705,11 @@ struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct udevice *sci_dev)
        if (!handle)
                return ERR_PTR(-EINVAL);
 
+       ret = ti_sci_cmd_get_revision(handle);
+
+       if (ret)
+               return ERR_PTR(-EINVAL);
+
        return handle;
 }
 
@@ -2825,11 +2832,9 @@ static int ti_sci_probe(struct udevice *dev)
        list_add_tail(&info->list, &ti_sci_list);
        ti_sci_setup_ops(info);
 
-       ret = ti_sci_cmd_get_revision(&info->handle);
-
        INIT_LIST_HEAD(&info->dev_list);
 
-       return ret;
+       return 0;
 }
 
 /**

diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c
index 61bc002..a82b1db 100644 (file)
--- a/drivers/ram/stm32mp1/stm32mp1_ram.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ram.c
@@ -127,7 +127,8 @@ static int stm32mp1_ddr_setup(struct udevice *dev)
                dev_dbg(dev, "no st,mem-name\n");
                return -EINVAL;
        }
-       printf("RAM: %s\n", config.info.name);
+       if (CONFIG_IS_ENABLED(DISPLAY_PRINT))
+               printf("RAM: %s\n", config.info.name);
 
        for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
                ret = ofnode_read_u32_array(node, param[idx].name,

diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index 5deb5db..24666bf 100644 (file)
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -48,11 +48,11 @@ config RNG_OPTEE
          accessible to normal world but reserved and used by the OP-TEE
          to avoid the weakness of a software PRNG.
 
-config RNG_STM32MP1
-       bool "Enable random number generator for STM32MP1"
-       depends on ARCH_STM32MP
+config RNG_STM32
+       bool "Enable random number generator for STM32"
+       depends on ARCH_STM32 || ARCH_STM32MP
        help
-         Enable STM32MP1 rng driver.
+         Enable STM32 rng driver.
 
 config RNG_ROCKCHIP
        bool "Enable random number generator for rockchip crypto rng"

diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 78f6105..192f911 100644 (file)
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
 obj-$(CONFIG_RNG_MSM) += msm_rng.o
 obj-$(CONFIG_RNG_NPCM) += npcm_rng.o
 obj-$(CONFIG_RNG_OPTEE) += optee_rng.o
-obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
+obj-$(CONFIG_RNG_STM32) += stm32_rng.o
 obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
 obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
 obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o

diff --git a/drivers/rng/stm32_rng.c b/drivers/rng/stm32_rng.c
new file mode 100644 (file)
index 0000000..c397b4d
--- /dev/null
+++ b/drivers/rng/stm32_rng.c
@@ -0,0 +1,408 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#define LOG_CATEGORY UCLASS_RNG
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <log.h>
+#include <reset.h>
+#include <rng.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+
+#define RNG_CR                 0x00
+#define RNG_CR_RNGEN           BIT(2)
+#define RNG_CR_CED             BIT(5)
+#define RNG_CR_CONFIG1         GENMASK(11, 8)
+#define RNG_CR_NISTC           BIT(12)
+#define RNG_CR_CONFIG2         GENMASK(15, 13)
+#define RNG_CR_CLKDIV_SHIFT    16
+#define RNG_CR_CLKDIV          GENMASK(19, 16)
+#define RNG_CR_CONFIG3         GENMASK(25, 20)
+#define RNG_CR_CONDRST         BIT(30)
+#define RNG_CR_ENTROPY_SRC_MASK        (RNG_CR_CONFIG1 | RNG_CR_NISTC | RNG_CR_CONFIG2 | RNG_CR_CONFIG3)
+#define RNG_CR_CONFIG_MASK     (RNG_CR_ENTROPY_SRC_MASK | RNG_CR_CED | RNG_CR_CLKDIV)
+
+#define RNG_SR         0x04
+#define RNG_SR_SEIS    BIT(6)
+#define RNG_SR_CEIS    BIT(5)
+#define RNG_SR_SECS    BIT(2)
+#define RNG_SR_DRDY    BIT(0)
+
+#define RNG_DR         0x08
+
+#define RNG_NSCR               0x0C
+#define RNG_NSCR_MASK          GENMASK(17, 0)
+
+#define RNG_HTCR       0x10
+
+#define RNG_NB_RECOVER_TRIES   3
+
+/*
+ * struct stm32_rng_data - RNG compat data
+ *
+ * @max_clock_rate:    Max RNG clock frequency, in Hertz
+ * @cr:                        Entropy source configuration
+ * @nscr:              Noice sources control configuration
+ * @htcr:              Health tests configuration
+ * @has_cond_reset:    True if conditionnal reset is supported
+ *
+ */
+struct stm32_rng_data {
+       uint max_clock_rate;
+       u32 cr;
+       u32 nscr;
+       u32 htcr;
+       bool has_cond_reset;
+};
+
+struct stm32_rng_plat {
+       fdt_addr_t base;
+       struct clk clk;
+       struct reset_ctl rst;
+       const struct stm32_rng_data *data;
+       bool ced;
+};
+
+/*
+ * Extracts from the STM32 RNG specification when RNG supports CONDRST.
+ *
+ * When a noise source (or seed) error occurs, the RNG stops generating
+ * random numbers and sets to “1” both SEIS and SECS bits to indicate
+ * that a seed error occurred. (...)
+ *
+ * 1. Software reset by writing CONDRST at 1 and at 0 (see bitfield
+ * description for details). This step is needed only if SECS is set.
+ * Indeed, when SEIS is set and SECS is cleared it means RNG performed
+ * the reset automatically (auto-reset).
+ * 2. If SECS was set in step 1 (no auto-reset) wait for CONDRST
+ * to be cleared in the RNG_CR register, then confirm that SEIS is
+ * cleared in the RNG_SR register. Otherwise just clear SEIS bit in
+ * the RNG_SR register.
+ * 3. If SECS was set in step 1 (no auto-reset) wait for SECS to be
+ * cleared by RNG. The random number generation is now back to normal.
+ */
+static int stm32_rng_conceal_seed_error_cond_reset(struct stm32_rng_plat *pdata)
+{
+       u32 sr = readl_relaxed(pdata->base + RNG_SR);
+       u32 cr = readl_relaxed(pdata->base + RNG_CR);
+       int err;
+
+       if (sr & RNG_SR_SECS) {
+               /* Conceal by resetting the subsystem (step 1.) */
+               writel_relaxed(cr | RNG_CR_CONDRST, pdata->base + RNG_CR);
+               writel_relaxed(cr & ~RNG_CR_CONDRST, pdata->base + RNG_CR);
+       } else {
+               /* RNG auto-reset (step 2.) */
+               writel_relaxed(sr & ~RNG_SR_SEIS, pdata->base + RNG_SR);
+               return 0;
+       }
+
+       err = readl_relaxed_poll_timeout(pdata->base + RNG_SR, sr, !(sr & RNG_CR_CONDRST), 100000);
+       if (err) {
+               log_err("%s: timeout %x\n", __func__, sr);
+               return err;
+       }
+
+       /* Check SEIS is cleared (step 2.) */
+       if (readl_relaxed(pdata->base + RNG_SR) & RNG_SR_SEIS)
+               return -EINVAL;
+
+       err = readl_relaxed_poll_timeout(pdata->base + RNG_SR, sr, !(sr & RNG_SR_SECS), 100000);
+       if (err) {
+               log_err("%s: timeout %x\n", __func__, sr);
+               return err;
+       }
+
+       return 0;
+}
+
+/*
+ * Extracts from the STM32 RNG specification, when CONDRST is not supported
+ *
+ * When a noise source (or seed) error occurs, the RNG stops generating
+ * random numbers and sets to “1” both SEIS and SECS bits to indicate
+ * that a seed error occurred. (...)
+ *
+ * The following sequence shall be used to fully recover from a seed
+ * error after the RNG initialization:
+ * 1. Clear the SEIS bit by writing it to “0”.
+ * 2. Read out 12 words from the RNG_DR register, and discard each of
+ * them in order to clean the pipeline.
+ * 3. Confirm that SEIS is still cleared. Random number generation is
+ * back to normal.
+ */
+static int stm32_rng_conceal_seed_error_sw_reset(struct stm32_rng_plat *pdata)
+{
+       uint i = 0;
+       u32 sr = readl_relaxed(pdata->base + RNG_SR);
+
+       writel_relaxed(sr & ~RNG_SR_SEIS, pdata->base + RNG_SR);
+
+       for (i = 12; i != 0; i--)
+               (void)readl_relaxed(pdata->base + RNG_DR);
+
+       if (readl_relaxed(pdata->base + RNG_SR) & RNG_SR_SEIS)
+               return -EINVAL;
+
+       return 0;
+}
+
+static int stm32_rng_conceal_seed_error(struct stm32_rng_plat *pdata)
+{
+       log_debug("Concealing RNG seed error\n");
+
+       if (pdata->data->has_cond_reset)
+               return stm32_rng_conceal_seed_error_cond_reset(pdata);
+       else
+               return stm32_rng_conceal_seed_error_sw_reset(pdata);
+};
+
+static int stm32_rng_read(struct udevice *dev, void *data, size_t len)
+{
+       int retval;
+       u32 sr, reg;
+       size_t increment;
+       struct stm32_rng_plat *pdata = dev_get_plat(dev);
+       uint tries = 0;
+
+       while (len > 0) {
+               retval = readl_poll_timeout(pdata->base + RNG_SR, sr,
+                                           sr, 10000);
+               if (retval) {
+                       log_err("%s: Timeout RNG no data",  __func__);
+                       return retval;
+               }
+
+               if (sr != RNG_SR_DRDY) {
+                       if (sr & RNG_SR_SEIS) {
+                               retval = stm32_rng_conceal_seed_error(pdata);
+                               tries++;
+                               if (retval || tries > RNG_NB_RECOVER_TRIES) {
+                                       log_err("%s: Couldn't recover from seed error",  __func__);
+                                       return -ENOTRECOVERABLE;
+                               }
+
+                               /* Start again */
+                               continue;
+                       }
+
+                       if (sr & RNG_SR_CEIS) {
+                               log_info("RNG clock too slow");
+                               writel_relaxed(0, pdata->base + RNG_SR);
+                       }
+               }
+
+               /*
+                * Once the DRDY bit is set, the RNG_DR register can
+                * be read up to four consecutive times.
+                */
+               reg = readl(pdata->base + RNG_DR);
+               /* Late seed error case: DR being 0 is an error status */
+               if (!reg) {
+                       retval = stm32_rng_conceal_seed_error(pdata);
+                       tries++;
+
+                       if (retval || tries > RNG_NB_RECOVER_TRIES) {
+                               log_err("%s: Couldn't recover from seed error",  __func__);
+                               return -ENOTRECOVERABLE;
+                       }
+
+                       /* Start again */
+                       continue;
+               }
+
+               increment = min(len, sizeof(u32));
+               memcpy(data, &reg, increment);
+               data += increment;
+               len -= increment;
+
+               tries = 0;
+       }
+
+       return 0;
+}
+
+static uint stm32_rng_clock_freq_restrain(struct stm32_rng_plat *pdata)
+{
+       ulong clock_rate = 0;
+       uint clock_div = 0;
+
+       clock_rate = clk_get_rate(&pdata->clk);
+
+       /*
+        * Get the exponent to apply on the CLKDIV field in RNG_CR register.
+        * No need to handle the case when clock-div > 0xF as it is physically
+        * impossible.
+        */
+       while ((clock_rate >> clock_div) > pdata->data->max_clock_rate)
+               clock_div++;
+
+       log_debug("RNG clk rate : %lu\n", clk_get_rate(&pdata->clk) >> clock_div);
+
+       return clock_div;
+}
+
+static int stm32_rng_init(struct stm32_rng_plat *pdata)
+{
+       int err;
+       u32 cr, sr;
+
+       err = clk_enable(&pdata->clk);
+       if (err)
+               return err;
+
+       cr = readl(pdata->base + RNG_CR);
+
+       /*
+        * Keep default RNG configuration if none was specified, that is when conf.cr is set to 0.
+        */
+       if (pdata->data->has_cond_reset && pdata->data->cr) {
+               uint clock_div = stm32_rng_clock_freq_restrain(pdata);
+
+               cr &= ~RNG_CR_CONFIG_MASK;
+               cr |= RNG_CR_CONDRST | (pdata->data->cr & RNG_CR_ENTROPY_SRC_MASK) |
+                     (clock_div << RNG_CR_CLKDIV_SHIFT);
+               if (pdata->ced)
+                       cr &= ~RNG_CR_CED;
+               else
+                       cr |= RNG_CR_CED;
+               writel(cr, pdata->base + RNG_CR);
+
+               /* Health tests and noise control registers */
+               writel_relaxed(pdata->data->htcr, pdata->base + RNG_HTCR);
+               writel_relaxed(pdata->data->nscr & RNG_NSCR_MASK, pdata->base + RNG_NSCR);
+
+               cr &= ~RNG_CR_CONDRST;
+               cr |= RNG_CR_RNGEN;
+               writel(cr, pdata->base + RNG_CR);
+               err = readl_poll_timeout(pdata->base + RNG_CR, cr,
+                                        (!(cr & RNG_CR_CONDRST)), 10000);
+               if (err) {
+                       log_err("%s: Timeout!",  __func__);
+                       return err;
+               }
+       } else {
+               if (pdata->data->has_cond_reset)
+                       cr |= RNG_CR_CONDRST;
+
+               if (pdata->ced)
+                       cr &= ~RNG_CR_CED;
+               else
+                       cr |= RNG_CR_CED;
+
+               writel(cr, pdata->base + RNG_CR);
+
+               if (pdata->data->has_cond_reset)
+                       cr &= ~RNG_CR_CONDRST;
+
+               cr |= RNG_CR_RNGEN;
+
+               writel(cr, pdata->base + RNG_CR);
+       }
+
+       /* clear error indicators */
+       writel(0, pdata->base + RNG_SR);
+
+       err = readl_poll_timeout(pdata->base + RNG_SR, sr,
+                                sr & RNG_SR_DRDY, 10000);
+       if (err)
+               log_err("%s: Timeout!",  __func__);
+
+       return err;
+}
+
+static int stm32_rng_cleanup(struct stm32_rng_plat *pdata)
+{
+       writel(0, pdata->base + RNG_CR);
+
+       return clk_disable(&pdata->clk);
+}
+
+static int stm32_rng_probe(struct udevice *dev)
+{
+       struct stm32_rng_plat *pdata = dev_get_plat(dev);
+
+       pdata->data = (struct stm32_rng_data *)dev_get_driver_data(dev);
+
+       reset_assert(&pdata->rst);
+       udelay(20);
+       reset_deassert(&pdata->rst);
+
+       return stm32_rng_init(pdata);
+}
+
+static int stm32_rng_remove(struct udevice *dev)
+{
+       struct stm32_rng_plat *pdata = dev_get_plat(dev);
+
+       return stm32_rng_cleanup(pdata);
+}
+
+static int stm32_rng_of_to_plat(struct udevice *dev)
+{
+       struct stm32_rng_plat *pdata = dev_get_plat(dev);
+       int err;
+
+       pdata->base = dev_read_addr(dev);
+       if (!pdata->base)
+               return -ENOMEM;
+
+       err = clk_get_by_index(dev, 0, &pdata->clk);
+       if (err)
+               return err;
+
+       err = reset_get_by_index(dev, 0, &pdata->rst);
+       if (err)
+               return err;
+
+       pdata->ced = dev_read_bool(dev, "clock-error-detect");
+
+       return 0;
+}
+
+static const struct dm_rng_ops stm32_rng_ops = {
+       .read = stm32_rng_read,
+};
+
+static const struct stm32_rng_data stm32mp13_rng_data = {
+       .has_cond_reset = true,
+       .max_clock_rate = 48000000,
+       .htcr = 0x969D,
+       .nscr = 0x2B5BB,
+       .cr = 0xF00D00,
+};
+
+static const struct stm32_rng_data stm32_rng_data = {
+       .has_cond_reset = false,
+       .max_clock_rate = 3000000,
+       /* Not supported */
+       .htcr = 0,
+       .nscr = 0,
+       .cr = 0,
+};
+
+static const struct udevice_id stm32_rng_match[] = {
+       {.compatible = "st,stm32mp13-rng", .data = (ulong)&stm32mp13_rng_data},
+       {.compatible = "st,stm32-rng", .data = (ulong)&stm32_rng_data},
+       {},
+};
+
+U_BOOT_DRIVER(stm32_rng) = {
+       .name = "stm32-rng",
+       .id = UCLASS_RNG,
+       .of_match = stm32_rng_match,
+       .ops = &stm32_rng_ops,
+       .probe = stm32_rng_probe,
+       .remove = stm32_rng_remove,
+       .plat_auto      = sizeof(struct stm32_rng_plat),
+       .of_to_plat = stm32_rng_of_to_plat,
+};

diff --git a/drivers/rng/stm32mp1_rng.c b/drivers/rng/stm32mp1_rng.c
deleted file mode 100644 (file)
index 89da78c..0000000
--- a/drivers/rng/stm32mp1_rng.c
+++ /dev/null
@@ -1,198 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (c) 2019, Linaro Limited
- */
-
-#define LOG_CATEGORY UCLASS_RNG
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <log.h>
-#include <reset.h>
-#include <rng.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-
-#include <asm/io.h>
-#include <linux/iopoll.h>
-#include <linux/kernel.h>
-
-#define RNG_CR         0x00
-#define RNG_CR_RNGEN   BIT(2)
-#define RNG_CR_CED     BIT(5)
-#define RNG_CR_CONDRST BIT(30)
-
-#define RNG_SR         0x04
-#define RNG_SR_SEIS    BIT(6)
-#define RNG_SR_CEIS    BIT(5)
-#define RNG_SR_SECS    BIT(2)
-#define RNG_SR_DRDY    BIT(0)
-
-#define RNG_DR         0x08
-
-struct stm32_rng_data {
-       bool has_cond_reset;
-};
-
-struct stm32_rng_plat {
-       fdt_addr_t base;
-       struct clk clk;
-       struct reset_ctl rst;
-       const struct stm32_rng_data *data;
-};
-
-static int stm32_rng_read(struct udevice *dev, void *data, size_t len)
-{
-       int retval, i;
-       u32 sr, count, reg;
-       size_t increment;
-       struct stm32_rng_plat *pdata = dev_get_plat(dev);
-
-       while (len > 0) {
-               retval = readl_poll_timeout(pdata->base + RNG_SR, sr,
-                                           sr & RNG_SR_DRDY, 10000);
-               if (retval)
-                       return retval;
-
-               if (sr & (RNG_SR_SEIS | RNG_SR_SECS)) {
-                       /* As per SoC TRM */
-                       clrbits_le32(pdata->base + RNG_SR, RNG_SR_SEIS);
-                       for (i = 0; i < 12; i++)
-                               readl(pdata->base + RNG_DR);
-                       if (readl(pdata->base + RNG_SR) & RNG_SR_SEIS) {
-                               log_err("RNG Noise");
-                               return -EIO;
-                       }
-                       /* start again */
-                       continue;
-               }
-
-               /*
-                * Once the DRDY bit is set, the RNG_DR register can
-                * be read four consecutive times.
-                */
-               count = 4;
-               while (len && count) {
-                       reg = readl(pdata->base + RNG_DR);
-                       memcpy(data, &reg, min(len, sizeof(u32)));
-                       increment = min(len, sizeof(u32));
-                       data += increment;
-                       len -= increment;
-                       count--;
-               }
-       }
-
-       return 0;
-}
-
-static int stm32_rng_init(struct stm32_rng_plat *pdata)
-{
-       int err;
-       u32 cr, sr;
-
-       err = clk_enable(&pdata->clk);
-       if (err)
-               return err;
-
-       cr = readl(pdata->base + RNG_CR);
-
-       /* Disable CED */
-       cr |= RNG_CR_CED;
-       if (pdata->data->has_cond_reset) {
-               cr |= RNG_CR_CONDRST;
-               writel(cr, pdata->base + RNG_CR);
-               cr &= ~RNG_CR_CONDRST;
-               writel(cr, pdata->base + RNG_CR);
-               err = readl_poll_timeout(pdata->base + RNG_CR, cr,
-                                        (!(cr & RNG_CR_CONDRST)), 10000);
-               if (err)
-                       return err;
-       }
-
-       /* clear error indicators */
-       writel(0, pdata->base + RNG_SR);
-
-       cr |= RNG_CR_RNGEN;
-       writel(cr, pdata->base + RNG_CR);
-
-       err = readl_poll_timeout(pdata->base + RNG_SR, sr,
-                                sr & RNG_SR_DRDY, 10000);
-       return err;
-}
-
-static int stm32_rng_cleanup(struct stm32_rng_plat *pdata)
-{
-       writel(0, pdata->base + RNG_CR);
-
-       return clk_disable(&pdata->clk);
-}
-
-static int stm32_rng_probe(struct udevice *dev)
-{
-       struct stm32_rng_plat *pdata = dev_get_plat(dev);
-
-       pdata->data = (struct stm32_rng_data *)dev_get_driver_data(dev);
-
-       reset_assert(&pdata->rst);
-       udelay(20);
-       reset_deassert(&pdata->rst);
-
-       return stm32_rng_init(pdata);
-}
-
-static int stm32_rng_remove(struct udevice *dev)
-{
-       struct stm32_rng_plat *pdata = dev_get_plat(dev);
-
-       return stm32_rng_cleanup(pdata);
-}
-
-static int stm32_rng_of_to_plat(struct udevice *dev)
-{
-       struct stm32_rng_plat *pdata = dev_get_plat(dev);
-       int err;
-
-       pdata->base = dev_read_addr(dev);
-       if (!pdata->base)
-               return -ENOMEM;
-
-       err = clk_get_by_index(dev, 0, &pdata->clk);
-       if (err)
-               return err;
-
-       err = reset_get_by_index(dev, 0, &pdata->rst);
-       if (err)
-               return err;
-
-       return 0;
-}
-
-static const struct dm_rng_ops stm32_rng_ops = {
-       .read = stm32_rng_read,
-};
-
-static const struct stm32_rng_data stm32mp13_rng_data = {
-       .has_cond_reset = true,
-};
-
-static const struct stm32_rng_data stm32_rng_data = {
-       .has_cond_reset = false,
-};
-
-static const struct udevice_id stm32_rng_match[] = {
-       {.compatible = "st,stm32mp13-rng", .data = (ulong)&stm32mp13_rng_data},
-       {.compatible = "st,stm32-rng", .data = (ulong)&stm32_rng_data},
-       {},
-};
-
-U_BOOT_DRIVER(stm32_rng) = {
-       .name = "stm32-rng",
-       .id = UCLASS_RNG,
-       .of_match = stm32_rng_match,
-       .ops = &stm32_rng_ops,
-       .probe = stm32_rng_probe,
-       .remove = stm32_rng_remove,
-       .plat_auto      = sizeof(struct stm32_rng_plat),
-       .of_to_plat = stm32_rng_of_to_plat,
-};

diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 9bf01ca..00ec9ef 100644 (file)
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -23,6 +23,10 @@
 #define BOOT_TARGET_DEVICES(func) \
        func(MMC, mmc, 0)
 
+#define STM32F746_BOARD_EXTRA_ENV \
+       "splashimage=0xC0448000\0" \
+       "splashpos=m,m\0"
+
 #include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS                         \
                        "kernel_addr_r=0xC0008000\0"            \
@@ -31,7 +35,8 @@
                        "scriptaddr=0xC0418000\0"               \
                        "pxefile_addr_r=0xC0428000\0" \
                        "ramdisk_addr_r=0xC0438000\0"           \
-                       BOOTENV
+                       BOOTENV \
+                       STM32F746_BOARD_EXTRA_ENV
 
 #define CFG_SYS_UBOOT_BASE             (CFG_SYS_FLASH_BASE + \
                                         CONFIG_SPL_PAD_TO)

diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h
index 7c59c69..5b0658c 100644 (file)
--- a/include/configs/stm32mp13_common.h
+++ b/include/configs/stm32mp13_common.h
@@ -35,16 +35,27 @@
 #define BOOT_TARGET_MMC1(func)
 #endif
 
+#ifdef CONFIG_CMD_USB
+#define BOOT_TARGET_USB(func)  func(USB, usb, 0)
+#else
+#define BOOT_TARGET_USB(func)
+#endif
+
 #define BOOT_TARGET_DEVICES(func)      \
        BOOT_TARGET_MMC1(func)          \
-       BOOT_TARGET_MMC0(func)
+       BOOT_TARGET_MMC0(func)          \
+       BOOT_TARGET_USB(func)
 
 /*
  * default bootcmd for stm32mp13:
+ * for serial/usb: execute the stm32prog command
  * for mmc boot (eMMC, SD card), distro boot on the same mmc device
  */
 #define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
        "echo \"Boot over ${boot_device}${boot_instance}!\";" \
+       "if test ${boot_device} = serial || test ${boot_device} = usb;" \
+       "then stm32prog ${boot_device} ${boot_instance}; " \
+       "else " \
                "run env_check;" \
                "if test ${boot_device} = mmc;" \
                "then env set boot_targets \"mmc${boot_instance}\"; fi;" \

diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h
index 9192169..8ff8822 100644 (file)
--- a/include/configs/stm32mp15_dh_dhsom.h
+++ b/include/configs/stm32mp15_dh_dhsom.h
@@ -20,7 +20,26 @@
 
 #define STM32MP_BOARD_EXTRA_ENV \
        "usb_pgood_delay=1000\0" \
-       "update_sf=" /* Erase SPI NOR and install U-Boot from SD */     \
+       "dh_update_sd_to_emmc=" /* Install U-Boot from SD to eMMC */    \
+               "setexpr loadaddr1 ${loadaddr} + 0x1000000 && "         \
+               "load mmc 0:4 ${loadaddr1} boot/u-boot-spl.stm32 && "   \
+               "setexpr sblkcnt ${filesize} + 0x1ff && "               \
+               "setexpr sblkcnt ${sblkcnt} / 0x200 && "                \
+               "load mmc 0:4 ${loadaddr} boot/u-boot.itb && "          \
+               "setexpr ublkcnt ${filesize} + 0x1ff && "               \
+               "setexpr ublkcnt ${ublkcnt} / 0x200 && "                \
+               "mmc partconf 1 1 1 1 && mmc dev 1 1 && "               \
+               "mmc write ${loadaddr1} 0 ${sblkcnt} && "               \
+               "mmc dev 1 2 && "                                       \
+               "mmc write ${loadaddr1} 0 ${sblkcnt} && "               \
+               "mmc dev 1 && "                                         \
+               "gpt write mmc 1 'name=ssbl,size=2MiB' && "             \
+               "mmc write ${loadaddr} 0x22 ${ublkcnt} && "             \
+               "mmc partconf 1 1 1 0 && "                              \
+               "setenv loadaddr1 && "                                  \
+               "setenv sblkcnt && "                                    \
+               "setenv ublkcnt\0"                                      \
+       "dh_update_sd_to_sf=" /* Erase SPI NOR and install U-Boot from SD */ \
                "setexpr loadaddr1 ${loadaddr} + 0x1000000 && "         \
                "load mmc 0:4 ${loadaddr1} /boot/u-boot-spl.stm32 && "  \
                "env set filesize1 ${filesize} && "                     \
@@ -29,7 +48,9 @@
                "sf update ${loadaddr1} 0 ${filesize1} && "             \
                "sf update ${loadaddr1} 0x40000 ${filesize1} && "       \
                "sf update ${loadaddr} 0x80000 ${filesize} && "         \
-               "env set filesize1 && env set loadaddr1\0"
+               "env set filesize1 && env set loadaddr1\0"              \
+       "update_sf=run dh_update_sd_to_sf\0"
+
 
 #include <configs/stm32mp15_common.h>
 

diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
index 25e8cfd..0a5324b 100644 (file)
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 /*
  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
  * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.

diff --git a/include/dt-bindings/clock/stm32mp13-clks.h b/include/dt-bindings/clock/stm32mp13-clks.h
index da4cb75..0bd7b54 100644 (file)
--- a/include/dt-bindings/clock/stm32mp13-clks.h
+++ b/include/dt-bindings/clock/stm32mp13-clks.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
 /*
  * Copyright (C) STMicroelectronics 2020 - All Rights Reserved
  * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.

diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h
index ba5cb74..a4e4f92 100644 (file)
--- a/include/dt-bindings/mfd/stm32f7-rcc.h
+++ b/include/dt-bindings/mfd/stm32f7-rcc.h
@@ -64,6 +64,7 @@
 #define STM32F7_RCC_APB1_TIM14         8
 #define STM32F7_RCC_APB1_LPTIM1                9
 #define STM32F7_RCC_APB1_WWDG          11
+#define STM32F7_RCC_APB1_CAN3          13
 #define STM32F7_RCC_APB1_SPI2          14
 #define STM32F7_RCC_APB1_SPI3          15
 #define STM32F7_RCC_APB1_SPDIFRX       16

diff --git a/include/dt-bindings/regulator/st,stm32mp13-regulator.h b/include/dt-bindings/regulator/st,stm32mp13-regulator.h
new file mode 100644 (file)
index 0000000..b3a974d
--- /dev/null
+++ b/include/dt-bindings/regulator/st,stm32mp13-regulator.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H
+#define __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H
+
+/* SCMI voltage domains identifiers */
+
+/* SOC Internal regulators */
+#define VOLTD_SCMI_REG11               0
+#define VOLTD_SCMI_REG18               1
+#define VOLTD_SCMI_USB33               2
+#define VOLTD_SCMI_SDMMC1_IO           3
+#define VOLTD_SCMI_SDMMC2_IO           4
+#define VOLTD_SCMI_VREFBUF             5
+
+/* STPMIC1 regulators */
+#define VOLTD_SCMI_STPMIC1_BUCK1       6
+#define VOLTD_SCMI_STPMIC1_BUCK2       7
+#define VOLTD_SCMI_STPMIC1_BUCK3       8
+#define VOLTD_SCMI_STPMIC1_BUCK4       9
+#define VOLTD_SCMI_STPMIC1_LDO1                10
+#define VOLTD_SCMI_STPMIC1_LDO2                11
+#define VOLTD_SCMI_STPMIC1_LDO3                12
+#define VOLTD_SCMI_STPMIC1_LDO4                13
+#define VOLTD_SCMI_STPMIC1_LDO5                14
+#define VOLTD_SCMI_STPMIC1_LDO6                15
+#define VOLTD_SCMI_STPMIC1_VREFDDR     16
+#define VOLTD_SCMI_STPMIC1_BOOST       17
+#define VOLTD_SCMI_STPMIC1_PWR_SW1     18
+#define VOLTD_SCMI_STPMIC1_PWR_SW2     19
+
+/* External regulators */
+#define VOLTD_SCMI_REGU0               20
+#define VOLTD_SCMI_REGU1               21
+#define VOLTD_SCMI_REGU2               22
+#define VOLTD_SCMI_REGU3               23
+#define VOLTD_SCMI_REGU4               24
+
+#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H */

diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h
index 4ffa7c3..9071f13 100644 (file)
--- a/include/dt-bindings/reset/stm32mp1-resets.h
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 /*
  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
  * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.

diff --git a/include/dt-bindings/reset/stm32mp13-resets.h b/include/dt-bindings/reset/stm32mp13-resets.h
index 1b83a01..ecb37c7 100644 (file)
--- a/include/dt-bindings/reset/stm32mp13-resets.h
+++ b/include/dt-bindings/reset/stm32mp13-resets.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
 /*
  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
  * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.

diff --git a/include/st_logo_data.h b/include/st_logo_data.h
deleted file mode 100644 (file)
index b53fa1c..0000000
--- a/include/st_logo_data.h
+++ /dev/null
@@ -1,3265 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
- * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
- *           Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
- */
-
-/*
- * file generated from picture
- * tools/logos/stmicroelectronics_uboot_logo_8bit_rle.bmp
- */
-
-unsigned char stmicroelectronics_uboot_logo_8bit_rle[] = {
-0x42, 0x4d, 0x5c, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7a, 0x04,
-0x00, 0x00, 0x6c, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x60, 0x01,
-0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe2, 0x93,
-0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x01,
-0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x42, 0x47, 0x52, 0x73, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0xff, 0xff, 0xff, 0x00, 0xae, 0x82, 0x3a, 0x00, 0xa5, 0x7b,
-0x37, 0x00, 0xfe, 0xfe, 0xfe, 0x00, 0xac, 0x80, 0x39, 0x00, 0x4e, 0x1b,
-0x02, 0x00, 0xb7, 0x88, 0x3b, 0x00, 0x4f, 0x1c, 0x02, 0x00, 0xb3, 0x85,
-0x3a, 0x00, 0xe1, 0xaa, 0x35, 0x00, 0x86, 0x62, 0x1f, 0x00, 0x65, 0x4a,
-0x13, 0x00, 0xa9, 0x7e, 0x38, 0x00, 0xff, 0xfe, 0xff, 0x00, 0x77, 0x55,
-0x13, 0x00, 0xbe, 0x91, 0x47, 0x00, 0xbc, 0x8d, 0x3d, 0x00, 0xfe, 0xfd,
-0xfd, 0x00, 0xa3, 0x7a, 0x38, 0x00, 0xbd, 0x8e, 0x42, 0x00, 0xa7, 0x7d,
-0x39, 0x00, 0x72, 0x52, 0x14, 0x00, 0xbc, 0x8d, 0x40, 0x00, 0x84, 0x60,
-0x1e, 0x00, 0xba, 0x8a, 0x3c, 0x00, 0x75, 0x53, 0x13, 0x00, 0x87, 0x62,
-0x11, 0x00, 0x85, 0x60, 0x10, 0x00, 0x7e, 0x5b, 0x12, 0x00, 0xb4, 0x86,
-0x3a, 0x00, 0x8c, 0x6a, 0x35, 0x00, 0xb1, 0x84, 0x3b, 0x00, 0xaa, 0x7f,
-0x3a, 0x00, 0xbc, 0x8c, 0x3c, 0x00, 0x85, 0x64, 0x34, 0x00, 0xb9, 0x89,
-0x3b, 0x00, 0x93, 0x69, 0x0e, 0x00, 0x8d, 0x65, 0x0e, 0x00, 0xfd, 0xfd,
-0xfc, 0x00, 0xa0, 0x78, 0x37, 0x00, 0x81, 0x5d, 0x12, 0x00, 0x9e, 0x76,
-0x36, 0x00, 0xbe, 0x90, 0x45, 0x00, 0x94, 0x6a, 0x0b, 0x00, 0x8b, 0x64,
-0x10, 0x00, 0x68, 0x4c, 0x14, 0x00, 0x8b, 0x69, 0x35, 0x00, 0x82, 0x5e,
-0x11, 0x00, 0x90, 0x6c, 0x35, 0x00, 0x89, 0x63, 0x0f, 0x00, 0xaf, 0x83,
-0x39, 0x00, 0xa2, 0x75, 0x06, 0x00, 0x96, 0x6b, 0x0d, 0x00, 0x7b, 0x59,
-0x12, 0x00, 0x9c, 0x70, 0x08, 0x00, 0x99, 0x73, 0x37, 0x00, 0xb0, 0x83,
-0x39, 0x00, 0x84, 0x60, 0x11, 0x00, 0x80, 0x5c, 0x14, 0x00, 0x91, 0x68,
-0x0c, 0x00, 0x6a, 0x4d, 0x14, 0x00, 0xc3, 0x99, 0x54, 0x00, 0x92, 0x6e,
-0x36, 0x00, 0x9a, 0x6e, 0x0b, 0x00, 0x8a, 0x68, 0x34, 0x00, 0xc0, 0x94,
-0x4b, 0x00, 0x98, 0x6c, 0x09, 0x00, 0x8f, 0x67, 0x0f, 0x00, 0x82, 0x62,
-0x34, 0x00, 0x7d, 0x5a, 0x15, 0x00, 0xc5, 0x9f, 0x5f, 0x00, 0xbb, 0x8b,
-0x3b, 0x00, 0xc8, 0xa7, 0x6a, 0x00, 0xc0, 0x95, 0x4e, 0x00, 0x87, 0x66,
-0x34, 0x00, 0x9f, 0x72, 0x06, 0x00, 0xbf, 0x93, 0x49, 0x00, 0xfd, 0xfb,
-0xfc, 0x00, 0xc7, 0xa4, 0x66, 0x00, 0x7a, 0x57, 0x13, 0x00, 0xc4, 0x9d,
-0x5a, 0x00, 0x83, 0x5f, 0x13, 0x00, 0x9c, 0x75, 0x36, 0x00, 0x7f, 0x60,
-0x32, 0x00, 0xb5, 0x87, 0x3c, 0x00, 0xc3, 0x9b, 0x57, 0x00, 0xc8, 0xa5,
-0x69, 0x00, 0x72, 0x55, 0x25, 0x00, 0xb9, 0x8a, 0x3a, 0x00, 0x94, 0x70,
-0x36, 0x00, 0xa2, 0x79, 0x36, 0x00, 0x7f, 0x5c, 0x12, 0x00, 0x97, 0x72,
-0x37, 0x00, 0x6c, 0x4e, 0x14, 0x00, 0xc5, 0x9e, 0x5d, 0x00, 0xca, 0xa9,
-0x6c, 0x00, 0xc5, 0xa3, 0x64, 0x00, 0x9e, 0x72, 0x0b, 0x00, 0xad, 0x81,
-0x3a, 0x00, 0x8e, 0x6b, 0x36, 0x00, 0xc6, 0xa1, 0x62, 0x00, 0x7c, 0x5f,
-0x31, 0x00, 0x6f, 0x50, 0x14, 0x00, 0xc1, 0x96, 0x50, 0x00, 0xd9, 0xc4,
-0x9f, 0x00, 0xcd, 0xbe, 0xa9, 0x00, 0xaa, 0x98, 0x7f, 0x00, 0xf6, 0xf3,
-0xf1, 0x00, 0xb9, 0x9b, 0x62, 0x00, 0x6a, 0x4c, 0x19, 0x00, 0x76, 0x59,
-0x29, 0x00, 0x79, 0x57, 0x15, 0x00, 0x6e, 0x4f, 0x13, 0x00, 0xfb, 0xf9,
-0xf9, 0x00, 0xae, 0x8d, 0x53, 0x00, 0x78, 0x5c, 0x2e, 0x00, 0xb2, 0x91,
-0x55, 0x00, 0xe8, 0xe1, 0xdc, 0x00, 0x8b, 0x69, 0x2e, 0x00, 0xc0, 0x9f,
-0x62, 0x00, 0xc1, 0x97, 0x52, 0x00, 0x52, 0x20, 0x06, 0x00, 0xbe, 0x9c,
-0x60, 0x00, 0xa1, 0x79, 0x38, 0x00, 0xed, 0xe8, 0xe5, 0x00, 0xdc, 0xc8,
-0xa6, 0x00, 0xd6, 0xca, 0xb9, 0x00, 0x80, 0x5e, 0x1d, 0x00, 0xb6, 0x95,
-0x58, 0x00, 0xb5, 0x97, 0x60, 0x00, 0x92, 0x75, 0x41, 0x00, 0x6f, 0x51,
-0x1d, 0x00, 0xc9, 0xba, 0xb2, 0x00, 0xa2, 0x88, 0x7b, 0x00, 0x82, 0x5e,
-0x1a, 0x00, 0x89, 0x67, 0x56, 0x00, 0xb0, 0x93, 0x5d, 0x00, 0x67, 0x4a,
-0x00, 0x00, 0xad, 0x9c, 0x81, 0x00, 0xd1, 0xbc, 0x9a, 0x00, 0x84, 0x64,
-0x2c, 0x00, 0x6e, 0x53, 0x25, 0x00, 0xf2, 0xee, 0xeb, 0x00, 0xbe, 0xa0,
-0x69, 0x00, 0xd5, 0xbf, 0x9b, 0x00, 0xba, 0x99, 0x5c, 0x00, 0x5a, 0x2a,
-0x12, 0x00, 0x7d, 0x5e, 0x29, 0x00, 0xbc, 0xa9, 0x9f, 0x00, 0x56, 0x24,
-0x0b, 0x00, 0xd0, 0xc2, 0xba, 0x00, 0x64, 0x37, 0x21, 0x00, 0x6a, 0x3f,
-0x29, 0x00, 0xd6, 0xcb, 0xc4, 0x00, 0xe4, 0xdc, 0xd7, 0x00, 0x6f, 0x45,
-0x30, 0x00, 0x6d, 0x4e, 0x03, 0x00, 0xca, 0xab, 0x72, 0x00, 0x64, 0x49,
-0x13, 0x00, 0xa5, 0x8c, 0x7f, 0x00, 0xed, 0xcc, 0x86, 0x00, 0xf8, 0xea,
-0xcd, 0x00, 0xfc, 0xf7, 0xec, 0x00, 0xfc, 0xf9, 0xf3, 0x00, 0x77, 0x4f,
-0x3b, 0x00, 0x8e, 0x71, 0x3c, 0x00, 0x92, 0x73, 0x3b, 0x00, 0xc6, 0xa8,
-0x6f, 0x00, 0xa8, 0x8a, 0x53, 0x00, 0x97, 0x79, 0x6a, 0x00, 0xa9, 0x80,
-0x3e, 0x00, 0xb2, 0x7e, 0x04, 0x00, 0x7b, 0x56, 0x0d, 0x00, 0xee, 0xe7,
-0xde, 0x00, 0x74, 0x51, 0x02, 0x00, 0xa4, 0x84, 0x4a, 0x00, 0xf6, 0xe4,
-0xbf, 0x00, 0xdc, 0xd2, 0xc8, 0x00, 0xe0, 0xd7, 0xd0, 0x00, 0xe9, 0xbf,
-0x68, 0x00, 0x9d, 0x7d, 0x43, 0x00, 0x5f, 0x31, 0x19, 0x00, 0xb3, 0x9d,
-0x92, 0x00, 0xb8, 0x8a, 0x40, 0x00, 0x9e, 0x82, 0x4f, 0x00, 0x92, 0x6d,
-0x2e, 0x00, 0x65, 0x4a, 0x11, 0x00, 0x97, 0x7b, 0x48, 0x00, 0xbf, 0x93,
-0x41, 0x00, 0x7d, 0x57, 0x44, 0x00, 0x80, 0x5c, 0x02, 0x00, 0x83, 0x5f,
-0x4e, 0x00, 0x97, 0x71, 0x30, 0x00, 0xab, 0x89, 0x4d, 0x00, 0x9d, 0x81,
-0x73, 0x00, 0x87, 0x64, 0x24, 0x00, 0x90, 0x70, 0x61, 0x00, 0xc6, 0xb5,
-0xac, 0x00, 0xab, 0x7e, 0x2d, 0x00, 0xa7, 0x7b, 0x1b, 0x00, 0xb8, 0x89,
-0x26, 0x00, 0xe3, 0xb1, 0x45, 0x00, 0x9c, 0x74, 0x2e, 0x00, 0x7a, 0x57,
-0x01, 0x00, 0xc2, 0xa4, 0x6e, 0x00, 0x86, 0x60, 0x01, 0x00, 0x60, 0x41,
-0x00, 0x00, 0xba, 0xa5, 0x83, 0x00, 0xce, 0xb8, 0x93, 0x00, 0xb6, 0x84,
-0x17, 0x00, 0xf8, 0xf1, 0xe4, 0x00, 0x73, 0x53, 0x0c, 0x00, 0xa7, 0x91,
-0x6b, 0x00, 0xa9, 0x78, 0x04, 0x00, 0xc1, 0xaf, 0xa6, 0x00, 0xac, 0x93,
-0x87, 0x00, 0xf2, 0xda, 0xa8, 0x00, 0xe3, 0xd2, 0xb7, 0x00, 0xeb, 0xc5,
-0x75, 0x00, 0xb8, 0xa5, 0x96, 0x00, 0x93, 0x68, 0x01, 0x00, 0xbb, 0x8d,
-0x32, 0x00, 0xc5, 0x9c, 0x55, 0x00, 0x9c, 0x72, 0x22, 0x00, 0xa5, 0x78,
-0x29, 0x00, 0xb3, 0x83, 0x2d, 0x00, 0xe7, 0xbd, 0x61, 0x00, 0xf0, 0xd4,
-0x99, 0x00, 0x9a, 0x6d, 0x02, 0x00, 0x78, 0x58, 0x1f, 0x00, 0xf9, 0xef,
-0xd8, 0x00, 0xeb, 0xe0, 0xd1, 0x00, 0xf4, 0xdf, 0xb3, 0x00, 0xe2, 0xad,
-0x3d, 0x00, 0xc3, 0xae, 0x8c, 0x00, 0xcf, 0xb1, 0x7e, 0x00, 0xe8, 0xd9,
-0xc2, 0x00, 0x89, 0x6d, 0x3c, 0x00, 0x85, 0x69, 0x37, 0x00, 0x8d, 0x64,
-0x01, 0x00, 0x90, 0x69, 0x23, 0x00, 0xc4, 0xb3, 0x99, 0x00, 0xc2, 0x9c,
-0x50, 0x00, 0xb9, 0x8d, 0x44, 0x00, 0xa0, 0x87, 0x5e, 0x00, 0xa8, 0x8f,
-0x82, 0x00, 0xaf, 0x98, 0x8d, 0x00, 0xb1, 0x9a, 0x73, 0x00, 0xb3, 0x8a,
-0x48, 0x00, 0xe5, 0xb5, 0x4f, 0x00, 0xd6, 0xbb, 0x8e, 0x00, 0xbb, 0x92,
-0x4c, 0x00, 0x86, 0x62, 0x19, 0x00, 0xe1, 0xa9, 0x35, 0x00, 0xe6, 0xb9,
-0x59, 0x00, 0xdb, 0xb3, 0x61, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
-0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
-0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
-0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
-0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
-0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
-0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
-0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
-0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
-0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
-0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
-0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
-0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
-0xdb, 0x00, 0x01, 0x4d, 0x01, 0x4d, 0x0a, 0x00, 0x00, 0x03, 0x26, 0x4d,
-0x03, 0x00, 0xf6, 0x00, 0x00, 0x00, 0xd9, 0x00, 0x01, 0x03, 0x03, 0x00,
-0x00, 0x0a, 0x4d, 0x9a, 0x96, 0xc5, 0x94, 0xb6, 0xd6, 0x96, 0xb2, 0x8e,
-0x03, 0x00, 0x01, 0x26, 0xf5, 0x00, 0x00, 0x00, 0xdb, 0x00, 0x00, 0x0e,
-0x9a, 0xb6, 0x87, 0x9b, 0x79, 0x07, 0x07, 0x05, 0x05, 0x07, 0x97, 0xbd,
-0x85, 0x96, 0xf7, 0x00, 0x00, 0x00, 0xd6, 0x00, 0x00, 0x06, 0x03, 0x00,
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-0x54, 0x54, 0x03, 0x06, 0x01, 0x23, 0x01, 0x23, 0x04, 0x18, 0x00, 0x04,
-0x47, 0x47, 0x21, 0x47, 0x03, 0x21, 0x00, 0x04, 0x10, 0x10, 0x16, 0x16,
-0x04, 0x13, 0x04, 0x2a, 0x06, 0x0f, 0x03, 0x4c, 0x03, 0x41, 0x03, 0x49,
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-0x06, 0x4e, 0x05, 0x56, 0x12, 0x48, 0x06, 0x56, 0x05, 0x4e, 0x07, 0x64,
-0x06, 0x46, 0x04, 0x5e, 0x07, 0x50, 0x05, 0x55, 0x03, 0x3d, 0x00, 0x03,
-0x78, 0x3d, 0x3d, 0x00, 0x03, 0x78, 0x03, 0x67, 0x04, 0x49, 0x05, 0x41,
-0x01, 0x4c, 0x01, 0x4c, 0x06, 0x0f, 0x03, 0x2a, 0x05, 0x13, 0x03, 0x16,
-0x01, 0x10, 0x01, 0x10, 0x04, 0x21, 0x01, 0x47, 0x04, 0x18, 0x01, 0x23,
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-0x00, 0x05, 0x1f, 0x38, 0x38, 0x32, 0x32, 0x00, 0x03, 0x01, 0x01, 0x62,
-0x03, 0x04, 0x03, 0x20, 0x03, 0x0c, 0x04, 0x14, 0x00, 0x0a, 0x02, 0x5a,
-0xaa, 0x91, 0x6c, 0x6c, 0x81, 0xd9, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00,
-0x87, 0x00, 0x00, 0x05, 0xb2, 0xea, 0xa8, 0xb4, 0xb4, 0x00, 0x03, 0xaf,
-0x01, 0xa8, 0x03, 0xaf, 0x00, 0x04, 0xb4, 0xb4, 0x12, 0x7b, 0x03, 0x5a,
-0x01, 0x02, 0x01, 0x12, 0x04, 0x02, 0x01, 0x14, 0x01, 0x14, 0x04, 0x0c,
-0x01, 0x20, 0x01, 0x20, 0x04, 0x04, 0x03, 0x01, 0x00, 0x05, 0x32, 0x32,
-0x38, 0x38, 0x1f, 0x00, 0x05, 0x08, 0x00, 0x03, 0x1d, 0x54, 0x1d, 0x00,
-0x03, 0x06, 0x03, 0x23, 0x01, 0x18, 0x01, 0x18, 0x03, 0x47, 0x01, 0x21,
-0x01, 0x47, 0x04, 0x21, 0x00, 0x04, 0x10, 0x10, 0x16, 0x16, 0x04, 0x13,
-0x04, 0x2a, 0x05, 0x0f, 0x01, 0x4c, 0x01, 0x4c, 0x05, 0x41, 0x04, 0x49,
-0x04, 0x67, 0x01, 0x78, 0x01, 0x78, 0x08, 0x3d, 0x05, 0x55, 0x05, 0x50,
-0x04, 0x5e, 0x07, 0x46, 0x04, 0x64, 0x08, 0x4e, 0x03, 0x56, 0x13, 0x48,
-0x06, 0x56, 0x06, 0x4e, 0x01, 0x64, 0x01, 0x4e, 0x04, 0x64, 0x07, 0x46,
-0x05, 0x5e, 0x04, 0x50, 0x04, 0x55, 0x01, 0x3d, 0x01, 0x55, 0x03, 0x3d,
-0x06, 0x78, 0x04, 0x67, 0x01, 0x49, 0x01, 0x49, 0x05, 0x41, 0x03, 0x4c,
-0x05, 0x0f, 0x04, 0x2a, 0x03, 0x13, 0x04, 0x16, 0x00, 0x04, 0x10, 0x10,
-0x21, 0x21, 0x05, 0x47, 0x01, 0x58, 0x01, 0x58, 0x03, 0x23, 0x04, 0x06,
-0x04, 0x1d, 0x04, 0x08, 0x03, 0x38, 0x00, 0x03, 0x32, 0x01, 0x01, 0x00,
-0x05, 0x04, 0x06, 0x0c, 0x07, 0x02, 0x00, 0x08, 0x5a, 0x5a, 0x74, 0x8f,
-0x8f, 0x80, 0xd0, 0x4d, 0x29, 0x00, 0x00, 0x00, 0x85, 0x00, 0x00, 0x07,
-0x03, 0x00, 0x00, 0x0d, 0x75, 0x8b, 0x88, 0x00, 0x04, 0xaf, 0x06, 0xa8,
-0x03, 0xaf, 0x03, 0xaa, 0x03, 0x14, 0x0c, 0xaa, 0x01, 0x62, 0x06, 0x01,
-0x07, 0x1f, 0x06, 0x54, 0x01, 0x06, 0x04, 0xb7, 0x03, 0x18, 0x03, 0x16,
-0x01, 0x10, 0x03, 0x16, 0x04, 0xf3, 0x00, 0x04, 0x13, 0xf3, 0xf3, 0x2a,
-0x08, 0x0f, 0x00, 0x05, 0x4c, 0x4c, 0xfb, 0xfb, 0x41, 0x00, 0x06, 0x49,
-0x01, 0x67, 0x01, 0x67, 0x09, 0x78, 0x03, 0x3d, 0x07, 0x55, 0x05, 0x50,
-0x06, 0x5e, 0x06, 0x46, 0x03, 0x64, 0x05, 0x60, 0x07, 0x4e, 0x10, 0x56,
-0x04, 0x4e, 0x00, 0x04, 0x60, 0x60, 0x4e, 0x4e, 0x04, 0x60, 0x04, 0x64,
-0x0a, 0x46, 0x01, 0x5e, 0x01, 0x5e, 0x05, 0x50, 0x07, 0x55, 0x03, 0x3d,
-0x00, 0x03, 0x78, 0x3d, 0x3d, 0x00, 0x07, 0x78, 0x01, 0x67, 0x01, 0x67,
-0x06, 0x49, 0x01, 0x41, 0x07, 0x4c, 0x05, 0x0f, 0x03, 0x2a, 0x06, 0x13,
-0x06, 0x16, 0x00, 0x03, 0xb7, 0xb7, 0x16, 0x00, 0x08, 0xb7, 0x06, 0x54,
-0x08, 0x1f, 0x04, 0x01, 0x00, 0x04, 0x62, 0xaa, 0x62, 0xaa, 0x03, 0x20,
-0x03, 0xaa, 0x00, 0x0b, 0x14, 0x14, 0x02, 0xf8, 0x8f, 0xcc, 0x8f, 0xcc,
-0xe7, 0x00, 0x03, 0x00, 0x27, 0x00, 0x00, 0x00, 0x86, 0x00, 0x01, 0x0d,
-0x01, 0x11, 0x03, 0x00, 0x00, 0x05, 0x6b, 0x7e, 0xcf, 0x88, 0xa8, 0x00,
-0x03, 0xaf, 0x03, 0xa8, 0x03, 0x72, 0x06, 0xa8, 0x00, 0x06, 0x72, 0xa8,
-0xa8, 0x72, 0x72, 0xa8, 0x23, 0x72, 0x1d, 0x74, 0x13, 0x80, 0x00, 0x04,
-0x81, 0x80, 0x80, 0x81, 0x04, 0x80, 0x1b, 0x81, 0x00, 0x04, 0x91, 0x91,
-0x81, 0x91, 0x34, 0x6c, 0x03, 0x7a, 0x01, 0x6c, 0x22, 0x7a, 0x03, 0x77,
-0x00, 0x03, 0x7a, 0x7a, 0x77, 0x00, 0x03, 0x7a, 0x05, 0x77, 0x01, 0x7a,
-0x2a, 0x77, 0x03, 0xcc, 0x00, 0x04, 0x91, 0xd9, 0x00, 0x03, 0x27, 0x00,
-0x00, 0x00, 0x8e, 0x00, 0x00, 0x0b, 0x8e, 0x7e, 0xea, 0x8f, 0x88, 0xa8,
-0xaf, 0xaf, 0xa8, 0x72, 0x72, 0x00, 0x3d, 0x88, 0x2c, 0x81, 0x01, 0x6c,
-0x09, 0x81, 0x01, 0x6c, 0x03, 0x81, 0x2e, 0x6c, 0x28, 0x8f, 0x1c, 0xcc,
-0x01, 0xa7, 0x03, 0xcc, 0x00, 0x05, 0xa7, 0xcc, 0xa7, 0xa7, 0xcc, 0x00,
-0x14, 0xa7, 0x13, 0x9d, 0x00, 0x07, 0xa7, 0x9d, 0x9d, 0x77, 0xec, 0x00,
-0x03, 0x00, 0x27, 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x08, 0x6b, 0xb2,
-0x7d, 0xd0, 0xea, 0xcc, 0x81, 0x88, 0x12, 0xc1, 0x00, 0x03, 0x72, 0x72,
-0xc1, 0x00, 0x24, 0x72, 0x01, 0x74, 0x03, 0x72, 0x01, 0x74, 0x01, 0x72,
-0x27, 0x74, 0x2c, 0x80, 0x01, 0x91, 0x01, 0x80, 0x23, 0x91, 0x05, 0x7a,
-0x01, 0x91, 0x18, 0x7a, 0x04, 0x77, 0x01, 0x7a, 0x1b, 0x77, 0x01, 0x60,
-0x01, 0x64, 0x24, 0x60, 0x00, 0x05, 0x77, 0xfa, 0x6b, 0x00, 0x0d, 0x00,
-0x27, 0x00, 0x00, 0x00, 0x95, 0x00, 0x00, 0x08, 0x71, 0x7c, 0xe7, 0xec,
-0x7e, 0x7d, 0x68, 0x90, 0x45, 0x8b, 0x00, 0x03, 0x90, 0x90, 0x8b, 0x00,
-0x2b, 0x90, 0x01, 0x68, 0x04, 0x90, 0x4d, 0x68, 0x00, 0x03, 0x7d, 0x7d,
-0x68, 0x00, 0x4f, 0x7d, 0x00, 0x04, 0xd9, 0x8e, 0x00, 0x0d, 0x28, 0x00,
-0x00, 0x00, 0x9d, 0x00, 0xff, 0x0d, 0x18, 0x0d, 0x2c, 0x00, 0x00, 0x00,
-0x95, 0x00, 0x01, 0x0d, 0x03, 0x03, 0x00, 0x03, 0x11, 0x11, 0x0d, 0x00,
-0xff, 0x00, 0x1a, 0x00, 0x01, 0x0d, 0x2a, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
-0xe1, 0x00, 0x00, 0x01
-};

diff --git a/tools/logos/stm32f746-disco.bmp b/tools/logos/stm32f746-disco.bmp
new file mode 100644 (file)
index 0000000..c1ef4fb
Binary files /dev/null and b/tools/logos/stm32f746-disco.bmp differ

diff --git a/tools/moveconfig.py b/tools/qconfig.py
similarity index 65%
rename from tools/moveconfig.py
rename to tools/qconfig.py
index 6cbecc3..04118d9 100755 (executable)
--- a/tools/moveconfig.py
+++ b/tools/qconfig.py
@@ -5,17 +5,14 @@
 #
 
 """
-Move config options from headers to defconfig files.
+Build and query a Kconfig database for boards.
 
 See doc/develop/moveconfig.rst for documentation.
 """
 
 from argparse import ArgumentParser
-import asteval
 import collections
 from contextlib import ExitStack
-import copy
-import difflib
 import doctest
 import filecmp
 import fnmatch
@@ -32,9 +29,11 @@ import threading
 import time
 import unittest
 
+import asteval
 from buildman import bsettings
 from buildman import kconfiglib
 from buildman import toolchain
+from u_boot_pylib import terminal
 
 SHOW_GNU_MAKE = 'scripts/show-gnu-make'
 SLEEP_TIME=0.03
@@ -44,30 +43,9 @@ STATE_DEFCONFIG = 1
 STATE_AUTOCONF = 2
 STATE_SAVEDEFCONFIG = 3
 
-ACTION_MOVE = 0
-ACTION_NO_ENTRY = 1
-ACTION_NO_ENTRY_WARN = 2
-ACTION_NO_CHANGE = 3
-
-COLOR_BLACK        = '0;30'
-COLOR_RED          = '0;31'
-COLOR_GREEN        = '0;32'
-COLOR_BROWN        = '0;33'
-COLOR_BLUE         = '0;34'
-COLOR_PURPLE       = '0;35'
-COLOR_CYAN         = '0;36'
-COLOR_LIGHT_GRAY   = '0;37'
-COLOR_DARK_GRAY    = '1;30'
-COLOR_LIGHT_RED    = '1;31'
-COLOR_LIGHT_GREEN  = '1;32'
-COLOR_YELLOW       = '1;33'
-COLOR_LIGHT_BLUE   = '1;34'
-COLOR_LIGHT_PURPLE = '1;35'
-COLOR_LIGHT_CYAN   = '1;36'
-COLOR_WHITE        = '1;37'
-
 AUTO_CONF_PATH = 'include/config/auto.conf'
-CONFIG_DATABASE = 'moveconfig.db'
+CONFIG_DATABASE = 'qconfig.db'
+FAILED_LIST = 'qconfig.failed'
 
 CONFIG_LEN = len('CONFIG_')
 
@@ -196,111 +174,6 @@ def get_all_defconfigs():
 
     return defconfigs
 
-def color_text(color_enabled, color, string):
-    """Return colored string."""
-    if color_enabled:
-        # LF should not be surrounded by the escape sequence.
-        # Otherwise, additional whitespace or line-feed might be printed.
-        return '\n'.join([ '\033[' + color + 'm' + s + '\033[0m' if s else ''
-                           for s in string.split('\n') ])
-    return string
-
-def show_diff(alines, blines, file_path, color_enabled):
-    """Show unidified diff.
-
-    Args:
-       alines (list of str): A list of lines (before)
-       blines (list of str): A list of lines (after)
-       file_path (str): Path to the file
-       color_enabled (bool): Display the diff in color
-    """
-    diff = difflib.unified_diff(alines, blines,
-                                fromfile=os.path.join('a', file_path),
-                                tofile=os.path.join('b', file_path))
-
-    for line in diff:
-        if line.startswith('-') and not line.startswith('--'):
-            print(color_text(color_enabled, COLOR_RED, line))
-        elif line.startswith('+') and not line.startswith('++'):
-            print(color_text(color_enabled, COLOR_GREEN, line))
-        else:
-            print(line)
-
-def extend_matched_lines(lines, matched, pre_patterns, post_patterns,
-                         extend_pre, extend_post):
-    """Extend matched lines if desired patterns are found before/after already
-    matched lines.
-
-    Args:
-      lines (list of str): list of lines handled.
-      matched (list of int): list of line numbers that have been already
-          matched (will be updated by this function)
-      pre_patterns (list of re.Pattern): list of regular expression that should
-          be matched as preamble
-      post_patterns (list of re.Pattern): list of regular expression that should
-          be matched as postamble
-      extend_pre (bool): Add the line number of matched preamble to the matched
-          list
-      extend_post (bool): Add the line number of matched postamble to the
-          matched list
-    """
-    extended_matched = []
-
-    j = matched[0]
-
-    for i in matched:
-        if i == 0 or i < j:
-            continue
-        j = i
-        while j in matched:
-            j += 1
-        if j >= len(lines):
-            break
-
-        for pat in pre_patterns:
-            if pat.search(lines[i - 1]):
-                break
-        else:
-            # not matched
-            continue
-
-        for pat in post_patterns:
-            if pat.search(lines[j]):
-                break
-        else:
-            # not matched
-            continue
-
-        if extend_pre:
-            extended_matched.append(i - 1)
-        if extend_post:
-            extended_matched.append(j)
-
-    matched += extended_matched
-    matched.sort()
-
-def confirm(args, prompt):
-    """Ask the user to confirm something
-
-    Args:
-        args (Namespace ): program arguments
-
-    Returns:
-        bool: True to confirm, False to cancel/stop
-    """
-    if not args.yes:
-        while True:
-            choice = input(f'{prompt} [y/n]: ')
-            choice = choice.lower()
-            print(choice)
-            if choice in ('y', 'n'):
-                break
-
-        if choice == 'n':
-            return False
-
-    return True
-
 def write_file(fname, data):
     """Write data to a file
 
@@ -321,7 +194,7 @@ def read_file(fname, as_lines=True, skip_unicode=False):
 
     Args:
         fname (str): Filename to read from
-        as_lines: Return file contents as a list of lines
+        as_lines (bool): Return file contents as a list of lines
         skip_unicode (bool): True to report unicode errors and continue
 
     Returns:
@@ -336,163 +209,13 @@ def read_file(fname, as_lines=True, skip_unicode=False):
         try:
             if as_lines:
                 return [line.rstrip('\n') for line in inf.readlines()]
-            else:
-                return inf.read()
-        except UnicodeDecodeError as e:
+            return inf.read()
+        except UnicodeDecodeError as exc:
             if not skip_unicode:
                 raise
-            print("Failed on file %s': %s" % (fname, e))
+            print(f"Failed on file '{fname}: {exc}")
             return None
 
-def cleanup_empty_blocks(header_path, args):
-    """Clean up empty conditional blocks
-
-    Args:
-      header_path (str): path to the cleaned file.
-      args (Namespace): program arguments
-    """
-    pattern = re.compile(r'^\s*#\s*if.*$\n^\s*#\s*endif.*$\n*', flags=re.M)
-    data = read_file(header_path, as_lines=False, skip_unicode=True)
-    if data is None:
-        return
-
-    new_data = pattern.sub('\n', data)
-
-    show_diff(data.splitlines(True), new_data.splitlines(True), header_path,
-              args.color)
-
-    if args.dry_run:
-        return
-
-    if new_data != data:
-        write_file(header_path, new_data)
-
-def cleanup_one_header(header_path, patterns, args):
-    """Clean regex-matched lines away from a file.
-
-    Args:
-      header_path: path to the cleaned file.
-      patterns: list of regex patterns.  Any lines matching to these
-                patterns are deleted.
-      args (Namespace): program arguments
-    """
-    lines = read_file(header_path, skip_unicode=True)
-    if lines is None:
-        return
-
-    matched = []
-    for i, line in enumerate(lines):
-        if i - 1 in matched and lines[i - 1].endswith('\\'):
-            matched.append(i)
-            continue
-        for pattern in patterns:
-            if pattern.search(line):
-                matched.append(i)
-                break
-
-    if not matched:
-        return
-
-    # remove empty #ifdef ... #endif, successive blank lines
-    pattern_if = re.compile(r'#\s*if(def|ndef)?\b') #  #if, #ifdef, #ifndef
-    pattern_elif = re.compile(r'#\s*el(if|se)\b')   #  #elif, #else
-    pattern_endif = re.compile(r'#\s*endif\b')      #  #endif
-    pattern_blank = re.compile(r'^\s*$')            #  empty line
-
-    while True:
-        old_matched = copy.copy(matched)
-        extend_matched_lines(lines, matched, [pattern_if],
-                             [pattern_endif], True, True)
-        extend_matched_lines(lines, matched, [pattern_elif],
-                             [pattern_elif, pattern_endif], True, False)
-        extend_matched_lines(lines, matched, [pattern_if, pattern_elif],
-                             [pattern_blank], False, True)
-        extend_matched_lines(lines, matched, [pattern_blank],
-                             [pattern_elif, pattern_endif], True, False)
-        extend_matched_lines(lines, matched, [pattern_blank],
-                             [pattern_blank], True, False)
-        if matched == old_matched:
-            break
-
-    tolines = copy.copy(lines)
-
-    for i in reversed(matched):
-        tolines.pop(i)
-
-    show_diff(lines, tolines, header_path, args.color)
-
-    if args.dry_run:
-        return
-
-    write_file(header_path, tolines)
-
-def cleanup_headers(configs, args):
-    """Delete config defines from board headers.
-
-    Args:
-      configs: A list of CONFIGs to remove.
-      args (Namespace): program arguments
-    """
-    if not confirm(args, 'Clean up headers?'):
-        return
-
-    patterns = []
-    for config in configs:
-        patterns.append(re.compile(r'#\s*define\s+%s\b' % config))
-        patterns.append(re.compile(r'#\s*undef\s+%s\b' % config))
-
-    for dir in 'include', 'arch', 'board':
-        for (dirpath, dirnames, filenames) in os.walk(dir):
-            if dirpath == os.path.join('include', 'generated'):
-                continue
-            for filename in filenames:
-                if not filename.endswith(('~', '.dts', '.dtsi', '.bin',
-                                          '.elf','.aml','.dat')):
-                    header_path = os.path.join(dirpath, filename)
-                    # This file contains UTF-16 data and no CONFIG symbols
-                    if header_path == 'include/video_font_data.h':
-                        continue
-                    cleanup_one_header(header_path, patterns, args)
-                    cleanup_empty_blocks(header_path, args)
-
-def find_matching(patterns, line):
-    for pat in patterns:
-        if pat.search(line):
-            return True
-    return False
-
-def cleanup_readme(configs, args):
-    """Delete config description in README
-
-    Args:
-      configs: A list of CONFIGs to remove.
-      args (Namespace): program arguments
-    """
-    if not confirm(args, 'Clean up README?'):
-        return
-
-    patterns = []
-    for config in configs:
-        patterns.append(re.compile(r'^\s+%s' % config))
-
-    lines = read_file('README')
-
-    found = False
-    newlines = []
-    for line in lines:
-        if not found:
-            found = find_matching(patterns, line)
-            if found:
-                continue
-
-        if found and re.search(r'^\s+CONFIG', line):
-            found = False
-
-        if not found:
-            newlines.append(line)
-
-    write_file('README', newlines)
-
 def try_expand(line):
     """If value looks like an expression, try expanding it
     Otherwise just return the existing value
@@ -506,10 +229,10 @@ def try_expand(line):
         val= val.strip('\"')
         if re.search(r'[*+-/]|<<|SZ_+|\(([^\)]+)\)', val):
             newval = hex(aeval(val))
-            print('\tExpanded expression %s to %s' % (val, newval))
+            print(f'\tExpanded expression {val} to {newval}')
             return cfg+'='+newval
     except:
-        print('\tFailed to expand expression in %s' % line)
+        print(f'\tFailed to expand expression in {line}')
 
     return line
 
@@ -519,23 +242,36 @@ class Progress:
 
     """Progress Indicator"""
 
-    def __init__(self, total):
+    def __init__(self, col, total):
         """Create a new progress indicator.
 
         Args:
-          total: A number of defconfig files to process.
+            color_enabled (bool): True for colour output
+            total (int): A number of defconfig files to process.
         """
+        self.col = col
         self.current = 0
+        self.good = 0
         self.total = total
 
-    def inc(self):
-        """Increment the number of processed defconfig files."""
+    def inc(self, success):
+        """Increment the number of processed defconfig files.
 
+        Args:
+            success (bool): True if processing succeeded
+        """
+        self.good += success
         self.current += 1
 
     def show(self):
         """Display the progress."""
-        print(' %d defconfigs out of %d\r' % (self.current, self.total), end=' ')
+        if self.current != self.total:
+            line = self.col.build(self.col.GREEN, f'{self.good:5d}')
+            line += self.col.build(self.col.RED,
+                                   f'{self.current - self.good:5d}')
+            line += self.col.build(self.col.MAGENTA,
+                                   f'/{self.total - self.current}')
+            print(f'{line}  \r', end='')
         sys.stdout.flush()
 
 
@@ -559,15 +295,13 @@ class KconfigParser:
     re_arch = re.compile(r'CONFIG_SYS_ARCH="(.*)"')
     re_cpu = re.compile(r'CONFIG_SYS_CPU="(.*)"')
 
-    def __init__(self, configs, args, build_dir):
+    def __init__(self, args, build_dir):
         """Create a new parser.
 
         Args:
-          configs: A list of CONFIGs to move.
           args (Namespace): program arguments
           build_dir: Build directory.
         """
-        self.configs = configs
         self.args = args
         self.dotconfig = os.path.join(build_dir, '.config')
         self.autoconf = os.path.join(build_dir, 'include', 'autoconf.mk')
@@ -585,13 +319,13 @@ class KconfigParser:
         arch = ''
         cpu = ''
         for line in read_file(self.dotconfig):
-            m = self.re_arch.match(line)
-            if m:
-                arch = m.group(1)
+            m_arch = self.re_arch.match(line)
+            if m_arch:
+                arch = m_arch.group(1)
                 continue
-            m = self.re_cpu.match(line)
-            if m:
-                cpu = m.group(1)
+            m_cpu = self.re_cpu.match(line)
+            if m_cpu:
+                cpu = m_cpu.group(1)
 
         if not arch:
             return None
@@ -602,155 +336,6 @@ class KconfigParser:
 
         return arch
 
-    def parse_one_config(self, config, dotconfig_lines, autoconf_lines):
-        """Parse .config, defconfig, include/autoconf.mk for one config.
-
-        This function looks for the config options in the lines from
-        defconfig, .config, and include/autoconf.mk in order to decide
-        which action should be taken for this defconfig.
-
-        Args:
-          config: CONFIG name to parse.
-          dotconfig_lines: lines from the .config file.
-          autoconf_lines: lines from the include/autoconf.mk file.
-
-        Returns:
-          A tupple of the action for this defconfig and the line
-          matched for the config.
-        """
-        not_set = '# %s is not set' % config
-
-        for line in autoconf_lines:
-            line = line.rstrip()
-            if line.startswith(config + '='):
-                new_val = line
-                break
-        else:
-            new_val = not_set
-
-        new_val = try_expand(new_val)
-
-        for line in dotconfig_lines:
-            line = line.rstrip()
-            if line.startswith(config + '=') or line == not_set:
-                old_val = line
-                break
-        else:
-            if new_val == not_set:
-                return (ACTION_NO_ENTRY, config)
-            else:
-                return (ACTION_NO_ENTRY_WARN, config)
-
-        # If this CONFIG is neither bool nor trisate
-        if old_val[-2:] != '=y' and old_val[-2:] != '=m' and old_val != not_set:
-            # tools/scripts/define2mk.sed changes '1' to 'y'.
-            # This is a problem if the CONFIG is int type.
-            # Check the type in Kconfig and handle it correctly.
-            if new_val[-2:] == '=y':
-                new_val = new_val[:-1] + '1'
-
-        return (ACTION_NO_CHANGE if old_val == new_val else ACTION_MOVE,
-                new_val)
-
-    def update_dotconfig(self):
-        """Parse files for the config options and update the .config.
-
-        This function parses the generated .config and include/autoconf.mk
-        searching the target options.
-        Move the config option(s) to the .config as needed.
-
-        Args:
-          defconfig: defconfig name.
-
-        Returns:
-          Return a tuple of (updated flag, log string).
-          The "updated flag" is True if the .config was updated, False
-          otherwise.  The "log string" shows what happend to the .config.
-        """
-
-        results = []
-        updated = False
-        suspicious = False
-        rm_files = [self.config_autoconf, self.autoconf]
-
-        if self.args.spl:
-            if os.path.exists(self.spl_autoconf):
-                autoconf_path = self.spl_autoconf
-                rm_files.append(self.spl_autoconf)
-            else:
-                for f in rm_files:
-                    os.remove(f)
-                return (updated, suspicious,
-                        color_text(self.args.color, COLOR_BROWN,
-                                   "SPL is not enabled.  Skipped.") + '\n')
-        else:
-            autoconf_path = self.autoconf
-
-        dotconfig_lines = read_file(self.dotconfig)
-
-        autoconf_lines = read_file(autoconf_path)
-
-        for config in self.configs:
-            result = self.parse_one_config(config, dotconfig_lines,
-                                           autoconf_lines)
-            results.append(result)
-
-        log = ''
-
-        for (action, value) in results:
-            if action == ACTION_MOVE:
-                actlog = "Move '%s'" % value
-                log_color = COLOR_LIGHT_GREEN
-            elif action == ACTION_NO_ENTRY:
-                actlog = '%s is not defined in Kconfig.  Do nothing.' % value
-                log_color = COLOR_LIGHT_BLUE
-            elif action == ACTION_NO_ENTRY_WARN:
-                actlog = '%s is not defined in Kconfig (suspicious).  Do nothing.' % value
-                log_color = COLOR_YELLOW
-                suspicious = True
-            elif action == ACTION_NO_CHANGE:
-                actlog = "'%s' is the same as the define in Kconfig.  Do nothing." \
-                         % value
-                log_color = COLOR_LIGHT_PURPLE
-            else:
-                sys.exit('Internal Error. This should not happen.')
-
-            log += color_text(self.args.color, log_color, actlog) + '\n'
-
-        with open(self.dotconfig, 'a', encoding='utf-8') as out:
-            for (action, value) in results:
-                if action == ACTION_MOVE:
-                    out.write(value + '\n')
-                    updated = True
-
-        self.results = results
-        for f in rm_files:
-            os.remove(f)
-
-        return (updated, suspicious, log)
-
-    def check_defconfig(self):
-        """Check the defconfig after savedefconfig
-
-        Returns:
-          Return additional log if moved CONFIGs were removed again by
-          'make savedefconfig'.
-        """
-
-        log = ''
-
-        defconfig_lines = read_file(self.defconfig)
-
-        for (action, value) in self.results:
-            if action != ACTION_MOVE:
-                continue
-            if not value in defconfig_lines:
-                log += color_text(self.args.color, COLOR_YELLOW,
-                                  "'%s' was removed by savedefconfig.\n" %
-                                  value)
-
-        return log
-
 
 class DatabaseThread(threading.Thread):
     """This thread processes results from Slot threads.
@@ -788,13 +373,12 @@ class Slot:
     for faster processing.
     """
 
-    def __init__(self, toolchains, configs, args, progress, devnull,
-                make_cmd, reference_src_dir, db_queue):
+    def __init__(self, toolchains, args, progress, devnull, make_cmd,
+                 reference_src_dir, db_queue, col):
         """Create a new process slot.
 
         Args:
           toolchains: Toolchains object containing toolchains.
-          configs: A list of CONFIGs to move.
           args: Program arguments
           progress: A progress indicator.
           devnull: A file object of '/dev/null'.
@@ -802,6 +386,7 @@ class Slot:
           reference_src_dir: Determine the true starting config state from this
                              source tree.
           db_queue: output queue to write config info for the database
+          col (terminal.Color): Colour object
         """
         self.toolchains = toolchains
         self.args = args
@@ -811,10 +396,14 @@ class Slot:
         self.make_cmd = (make_cmd, 'O=' + self.build_dir)
         self.reference_src_dir = reference_src_dir
         self.db_queue = db_queue
-        self.parser = KconfigParser(configs, args, self.build_dir)
+        self.col = col
+        self.parser = KconfigParser(args, self.build_dir)
         self.state = STATE_IDLE
         self.failed_boards = set()
-        self.suspicious_boards = set()
+        self.defconfig = None
+        self.log = []
+        self.current_src_dir = None
+        self.proc = None
 
     def __del__(self):
         """Delete the working directory
@@ -827,7 +416,7 @@ class Slot:
         If the subprocess is still running, wait until it finishes.
         """
         if self.state != STATE_IDLE:
-            while self.ps.poll() == None:
+            while self.proc.poll() is None:
                 pass
         shutil.rmtree(self.build_dir)
 
@@ -839,7 +428,7 @@ class Slot:
         the slot is occupied (i.e. the current subprocess is still running).
 
         Args:
-          defconfig: defconfig name.
+          defconfig (str): defconfig name.
 
         Returns:
           Return True on success or False on failure
@@ -848,7 +437,7 @@ class Slot:
             return False
 
         self.defconfig = defconfig
-        self.log = ''
+        self.log = []
         self.current_src_dir = self.reference_src_dir
         self.do_defconfig()
         return True
@@ -872,10 +461,10 @@ class Slot:
         if self.state == STATE_IDLE:
             return True
 
-        if self.ps.poll() == None:
+        if self.proc.poll() is None:
             return False
 
-        if self.ps.poll() != 0:
+        if self.proc.poll() != 0:
             self.handle_error()
         elif self.state == STATE_DEFCONFIG:
             if self.reference_src_dir and not self.current_src_dir:
@@ -895,16 +484,16 @@ class Slot:
         else:
             sys.exit('Internal Error. This should not happen.')
 
-        return True if self.state == STATE_IDLE else False
+        return self.state == STATE_IDLE
 
     def handle_error(self):
         """Handle error cases."""
 
-        self.log += color_text(self.args.color, COLOR_LIGHT_RED,
-                               'Failed to process.\n')
+        self.log.append(self.col.build(self.col.RED, 'Failed to process',
+                                       bright=True))
         if self.args.verbose:
-            self.log += color_text(self.args.color, COLOR_LIGHT_CYAN,
-                                   self.ps.stderr.read().decode())
+            for line in self.proc.stderr.read().decode().splitlines():
+                self.log.append(self.col.build(self.col.CYAN, line, True))
         self.finish(False)
 
     def do_defconfig(self):
@@ -912,9 +501,9 @@ class Slot:
 
         cmd = list(self.make_cmd)
         cmd.append(self.defconfig)
-        self.ps = subprocess.Popen(cmd, stdout=self.devnull,
-                                   stderr=subprocess.PIPE,
-                                   cwd=self.current_src_dir)
+        self.proc = subprocess.Popen(cmd, stdout=self.devnull,
+                                     stderr=subprocess.PIPE,
+                                     cwd=self.current_src_dir)
         self.state = STATE_DEFCONFIG
 
     def do_autoconf(self):
@@ -922,20 +511,21 @@ class Slot:
 
         arch = self.parser.get_arch()
         try:
-            toolchain = self.toolchains.Select(arch)
+            tchain = self.toolchains.Select(arch)
         except ValueError:
-            self.log += color_text(self.args.color, COLOR_YELLOW,
-                    "Tool chain for '%s' is missing.  Do nothing.\n" % arch)
+            self.log.append(self.col.build(
+                self.col.YELLOW,
+                f"Tool chain for '{arch}' is missing: do nothing"))
             self.finish(False)
             return
-        env = toolchain.MakeEnvironment(False)
+        env = tchain.MakeEnvironment(False)
 
         cmd = list(self.make_cmd)
         cmd.append('KCONFIG_IGNORE_DUPLICATES=1')
         cmd.append(AUTO_CONF_PATH)
-        self.ps = subprocess.Popen(cmd, stdout=self.devnull, env=env,
-                                   stderr=subprocess.PIPE,
-                                   cwd=self.current_src_dir)
+        self.proc = subprocess.Popen(cmd, stdout=self.devnull, env=env,
+                                     stderr=subprocess.PIPE,
+                                     cwd=self.current_src_dir)
         self.state = STATE_AUTOCONF
 
     def do_build_db(self):
@@ -950,41 +540,25 @@ class Slot:
 
     def do_savedefconfig(self):
         """Update the .config and run 'make savedefconfig'."""
-
-        (updated, suspicious, log) = self.parser.update_dotconfig()
-        if suspicious:
-            self.suspicious_boards.add(self.defconfig)
-        self.log += log
-
-        if not self.args.force_sync and not updated:
+        if not self.args.force_sync:
             self.finish(True)
             return
-        if updated:
-            self.log += color_text(self.args.color, COLOR_LIGHT_GREEN,
-                                   'Syncing by savedefconfig...\n')
-        else:
-            self.log += 'Syncing by savedefconfig (forced by option)...\n'
 
         cmd = list(self.make_cmd)
         cmd.append('savedefconfig')
-        self.ps = subprocess.Popen(cmd, stdout=self.devnull,
-                                   stderr=subprocess.PIPE)
+        self.proc = subprocess.Popen(cmd, stdout=self.devnull,
+                                     stderr=subprocess.PIPE)
         self.state = STATE_SAVEDEFCONFIG
 
     def update_defconfig(self):
         """Update the input defconfig and go back to the idle state."""
-
-        log = self.parser.check_defconfig()
-        if log:
-            self.suspicious_boards.add(self.defconfig)
-            self.log += log
         orig_defconfig = os.path.join('configs', self.defconfig)
         new_defconfig = os.path.join(self.build_dir, 'defconfig')
         updated = not filecmp.cmp(orig_defconfig, new_defconfig)
 
         if updated:
-            self.log += color_text(self.args.color, COLOR_LIGHT_BLUE,
-                                   'defconfig was updated.\n')
+            self.log.append(
+                self.col.build(self.col.BLUE, 'defconfig updated', bright=True))
 
         if not self.args.dry_run and updated:
             shutil.move(new_defconfig, orig_defconfig)
@@ -994,25 +568,30 @@ class Slot:
         """Display log along with progress and go to the idle state.
 
         Args:
-          success: Should be True when the defconfig was processed
+          success (bool): Should be True when the defconfig was processed
                    successfully, or False when it fails.
         """
         # output at least 30 characters to hide the "* defconfigs out of *".
-        log = self.defconfig.ljust(30) + '\n'
+        name = self.defconfig[:-len('_defconfig')]
+        if self.log:
+
+            # Put the first log line on the first line
+            log = name.ljust(20) + ' ' + self.log[0]
 
-        log += '\n'.join([ '    ' + s for s in self.log.split('\n') ])
-        # Some threads are running in parallel.
-        # Print log atomically to not mix up logs from different threads.
-        print(log, file=(sys.stdout if success else sys.stderr))
+            if len(self.log) > 1:
+                log += '\n' + '\n'.join(['    ' + s for s in self.log[1:]])
+            # Some threads are running in parallel.
+            # Print log atomically to not mix up logs from different threads.
+            print(log, file=(sys.stdout if success else sys.stderr))
 
         if not success:
             if self.args.exit_on_error:
                 sys.exit('Exit on error.')
             # If --exit-on-error flag is not set, skip this board and continue.
             # Record the failed board.
-            self.failed_boards.add(self.defconfig)
+            self.failed_boards.add(name)
 
-        self.progress.inc()
+        self.progress.inc(success)
         self.progress.show()
         self.state = STATE_IDLE
 
@@ -1021,42 +600,38 @@ class Slot:
         """
         return self.failed_boards
 
-    def get_suspicious_boards(self):
-        """Returns a set of boards (defconfigs) with possible misconversion.
-        """
-        return self.suspicious_boards - self.failed_boards
-
 class Slots:
 
     """Controller of the array of subprocess slots."""
 
-    def __init__(self, toolchains, configs, args, progress,
-                reference_src_dir, db_queue):
+    def __init__(self, toolchains, args, progress, reference_src_dir, db_queue,
+                 col):
         """Create a new slots controller.
 
         Args:
-          toolchains: Toolchains object containing toolchains.
-          configs: A list of CONFIGs to move.
-          args: Program arguments
-          progress: A progress indicator.
-          reference_src_dir: Determine the true starting config state from this
-                             source tree.
-          db_queue: output queue to write config info for the database
+            toolchains (Toolchains): Toolchains object containing toolchains
+            args (Namespace): Program arguments
+            progress (Progress): A progress indicator.
+            reference_src_dir (str): Determine the true starting config state
+                from this source tree (None for none)
+            db_queue (Queue): output queue to write config info for the database
+            col (terminal.Color): Colour object
         """
         self.args = args
         self.slots = []
+        self.progress = progress
+        self.col = col
         devnull = subprocess.DEVNULL
         make_cmd = get_make_cmd()
-        for i in range(args.jobs):
-            self.slots.append(Slot(toolchains, configs, args, progress,
-                                  devnull, make_cmd, reference_src_dir,
-                                  db_queue))
+        for _ in range(args.jobs):
+            self.slots.append(Slot(toolchains, args, progress, devnull,
+                                   make_cmd, reference_src_dir, db_queue, col))
 
     def add(self, defconfig):
         """Add a new subprocess if a vacant slot is found.
 
         Args:
-          defconfig: defconfig name to be put into.
+          defconfig (str): defconfig name to be put into.
 
         Returns:
           Return True on success or False on failure
@@ -1089,42 +664,17 @@ class Slots:
                 ret = False
         return ret
 
-    def show_failed_boards(self):
-        """Display all of the failed boards (defconfigs)."""
+    def write_failed_boards(self):
+        """Show the results of processing"""
         boards = set()
-        output_file = 'moveconfig.failed'
 
         for slot in self.slots:
             boards |= slot.get_failed_boards()
 
         if boards:
-            boards = '\n'.join(boards) + '\n'
-            msg = 'The following boards were not processed due to error:\n'
-            msg += boards
-            msg += '(the list has been saved in %s)\n' % output_file
-            print(color_text(self.args.color, COLOR_LIGHT_RED,
-                                            msg), file=sys.stderr)
+            boards = '\n'.join(sorted(boards)) + '\n'
+            write_file(FAILED_LIST, boards)
 
-            write_file(output_file, boards)
-
-    def show_suspicious_boards(self):
-        """Display all boards (defconfigs) with possible misconversion."""
-        boards = set()
-        output_file = 'moveconfig.suspicious'
-
-        for slot in self.slots:
-            boards |= slot.get_suspicious_boards()
-
-        if boards:
-            boards = '\n'.join(boards) + '\n'
-            msg = 'The following boards might have been converted incorrectly.\n'
-            msg += 'It is highly recommended to check them manually:\n'
-            msg += boards
-            msg += '(the list has been saved in %s)\n' % output_file
-            print(color_text(self.args.color, COLOR_YELLOW,
-                                            msg), file=sys.stderr)
-
-            write_file(output_file, boards)
 
 class ReferenceSource:
 
@@ -1140,8 +690,9 @@ class ReferenceSource:
         print('Cloning git repo to a separate work directory...')
         subprocess.check_output(['git', 'clone', os.getcwd(), '.'],
                                 cwd=self.src_dir)
-        print("Checkout '%s' to build the original autoconf.mk." % \
-            subprocess.check_output(['git', 'rev-parse', '--short', commit]).strip())
+        rev = subprocess.check_output(['git', 'rev-parse', '--short',
+                                       commit]).strip()
+        print(f"Checkout '{rev}' to build the original autoconf.mk.")
         subprocess.check_output(['git', 'checkout', commit],
                                 stderr=subprocess.STDOUT, cwd=self.src_dir)
 
@@ -1160,24 +711,18 @@ class ReferenceSource:
 
         return self.src_dir
 
-def move_config(toolchains, configs, args, db_queue):
-    """Move config options to defconfig files.
+def move_config(toolchains, args, db_queue, col):
+    """Build database or sync config options to defconfig files.
 
     Args:
-      configs: A list of CONFIGs to move.
-      args: Program arguments
-    """
-    if len(configs) == 0:
-        if args.force_sync:
-            print('No CONFIG is specified. You are probably syncing defconfigs.', end=' ')
-        elif args.build_db:
-            print('Building %s database' % CONFIG_DATABASE)
-        else:
-            print('Neither CONFIG nor --force-sync is specified. Nothing will happen.', end=' ')
-    else:
-        print('Move ' + ', '.join(configs), end=' ')
-    print('(jobs: %d)\n' % args.jobs)
+        toolchains (Toolchains): Toolchains to use
+        args (Namespace): Program arguments
+        db_queue (Queue): Queue for database updates
+        col (terminal.Color): Colour object
 
+    Returns:
+        Progress: Progress indicator
+    """
     if args.git_ref:
         reference_src = ReferenceSource(args.git_ref)
         reference_src_dir = reference_src.get_dir()
@@ -1189,9 +734,8 @@ def move_config(toolchains, configs, args, db_queue):
     else:
         defconfigs = get_all_defconfigs()
 
-    progress = Progress(len(defconfigs))
-    slots = Slots(toolchains, configs, args, progress, reference_src_dir,
-                  db_queue)
+    progress = Progress(col, len(defconfigs))
+    slots = Slots(toolchains, args, progress, reference_src_dir, db_queue, col)
 
     # Main loop to process defconfig files:
     #  Add a new subprocess into a vacant slot.
@@ -1206,25 +750,24 @@ def move_config(toolchains, configs, args, db_queue):
     while not slots.empty():
         time.sleep(SLEEP_TIME)
 
-    print('')
-    slots.show_failed_boards()
-    slots.show_suspicious_boards()
+    slots.write_failed_boards()
+    return progress
 
 def find_kconfig_rules(kconf, config, imply_config):
     """Check whether a config has a 'select' or 'imply' keyword
 
     Args:
-        kconf: Kconfiglib.Kconfig object
-        config: Name of config to check (without CONFIG_ prefix)
-        imply_config: Implying config (without CONFIG_ prefix) which may or
-            may not have an 'imply' for 'config')
+        kconf (Kconfiglib.Kconfig): Kconfig object
+        config (str): Name of config to check (without CONFIG_ prefix)
+        imply_config (str): Implying config (without CONFIG_ prefix) which may
+            or may not have an 'imply' for 'config')
 
     Returns:
         Symbol object for 'config' if found, else None
     """
     sym = kconf.syms.get(imply_config)
     if sym:
-        for sel, cond in (sym.selects + sym.implies):
+        for sel, _ in (sym.selects + sym.implies):
             if sel.name == config:
                 return sym
     return None
@@ -1236,54 +779,55 @@ def check_imply_rule(kconf, config, imply_config):
     to add an 'imply' for 'config' to that part of the Kconfig.
 
     Args:
-        kconf: Kconfiglib.Kconfig object
-        config: Name of config to check (without CONFIG_ prefix)
-        imply_config: Implying config (without CONFIG_ prefix) which may or
-            may not have an 'imply' for 'config')
+        kconf (Kconfiglib.Kconfig): Kconfig object
+        config (str): Name of config to check (without CONFIG_ prefix)
+        imply_config (str): Implying config (without CONFIG_ prefix) which may
+            or may not have an 'imply' for 'config')
 
     Returns:
         tuple:
-            filename of Kconfig file containing imply_config, or None if none
-            line number within the Kconfig file, or 0 if none
-            message indicating the result
+            str: filename of Kconfig file containing imply_config, or None if
+                none
+            int: line number within the Kconfig file, or 0 if none
+            str: message indicating the result
     """
     sym = kconf.syms.get(imply_config)
     if not sym:
         return 'cannot find sym'
     nodes = sym.nodes
     if len(nodes) != 1:
-        return '%d locations' % len(nodes)
+        return f'{len(nodes)} locations'
     node = nodes[0]
     fname, linenum = node.filename, node.linenr
     cwd = os.getcwd()
     if cwd and fname.startswith(cwd):
         fname = fname[len(cwd) + 1:]
-    file_line = ' at %s:%d' % (fname, linenum)
+    file_line = f' at {fname}:{linenum}'
     data = read_file(fname)
-    if data[linenum - 1] != 'config %s' % imply_config:
-        return None, 0, 'bad sym format %s%s' % (data[linenum], file_line)
-    return fname, linenum, 'adding%s' % file_line
+    if data[linenum - 1] != f'config {imply_config}':
+        return None, 0, f'bad sym format {data[linenum]}{file_line})'
+    return fname, linenum, f'adding{file_line}'
 
 def add_imply_rule(config, fname, linenum):
     """Add a new 'imply' option to a Kconfig
 
     Args:
-        config: config option to add an imply for (without CONFIG_ prefix)
-        fname: Kconfig filename to update
-        linenum: Line number to place the 'imply' before
+        config (str): config option to add an imply for (without CONFIG_ prefix)
+        fname (str): Kconfig filename to update
+        linenum (int): Line number to place the 'imply' before
 
     Returns:
         Message indicating the result
     """
-    file_line = ' at %s:%d' % (fname, linenum)
+    file_line = f' at {fname}:{linenum}'
     data = read_file(fname)
     linenum -= 1
 
     for offset, line in enumerate(data[linenum:]):
         if line.strip().startswith('help') or not line:
-            data.insert(linenum + offset, '\timply %s' % config)
+            data.insert(linenum + offset, f'\timply {config}')
             write_file(fname, data)
-            return 'added%s' % file_line
+            return f'added{file_line}'
 
     return 'could not insert%s'
 
@@ -1356,7 +900,7 @@ def do_imply_config(config_list, add_imply, imply_flags, skip_added,
     all x86 boards will have that option, avoiding adding CONFIG_CMD_IRQ to
     each of the x86 defconfig files.
 
-    This function uses the moveconfig database to find such options. It
+    This function uses the qconfig database to find such options. It
     displays a list of things that could possibly imply those in the list.
     The algorithm ignores any that start with CONFIG_TARGET since these
     typically refer to only a few defconfigs (often one). It also does not
@@ -1392,21 +936,20 @@ def do_imply_config(config_list, add_imply, imply_flags, skip_added,
     if add_imply and add_imply != 'all':
         add_imply = add_imply.split(',')
 
-    all_configs, all_defconfigs, config_db, defconfig_db = read_database()
+    all_configs, all_defconfigs, _, defconfig_db = read_database()
 
     # Work through each target config option in turn, independently
     for config in config_list:
         defconfigs = defconfig_db.get(config)
         if not defconfigs:
-            print('%s not found in any defconfig' % config)
+            print(f'{config} not found in any defconfig')
             continue
 
         # Get the set of defconfigs without this one (since a config cannot
         # imply itself)
         non_defconfigs = all_defconfigs - defconfigs
         num_defconfigs = len(defconfigs)
-        print('%s found in %d/%d defconfigs' % (config, num_defconfigs,
-                                                len(all_configs)))
+        print(f'{config} found in {num_defconfigs}/{len(all_configs)} defconfigs')
 
         # This will hold the results: key=config, value=defconfigs containing it
         imply_configs = {}
@@ -1452,7 +995,7 @@ def do_imply_config(config_list, add_imply, imply_flags, skip_added,
                             # skip imply_config because prev is a superset
                             skip = True
                             break
-                        elif count > prev_count:
+                        if count > prev_count:
                             # delete prev because imply_config is a superset
                             del imply_configs[prev]
                 if not skip:
@@ -1487,7 +1030,7 @@ def do_imply_config(config_list, add_imply, imply_flags, skip_added,
                         fname, linenum = nodes[0].filename, nodes[0].linenr
                         if cwd and fname.startswith(cwd):
                             fname = fname[len(cwd) + 1:]
-                        kconfig_info = '%s:%d' % (fname, linenum)
+                        kconfig_info = f'{fname}:{linenum}'
                         if skip_added:
                             show = False
                 else:
@@ -1513,8 +1056,8 @@ def do_imply_config(config_list, add_imply, imply_flags, skip_added,
                             add_list[fname].append(linenum)
 
             if show and kconfig_info != 'skip':
-                print('%5d : %-30s%-25s %s' % (num_common, iconfig.ljust(30),
-                                              kconfig_info, missing_str))
+                print(f'{num_common:5d} : '
+                      f'{iconfig.ljust(30):-30s}{kconfig_info:-25s} {missing_str}')
 
         # Having collected a list of things to add, now we add them. We process
         # each file from the largest line number to the smallest so that
@@ -1553,7 +1096,7 @@ def do_find_config(config_list):
             is preceded by a tilde (~) then it must be false, otherwise it must
             be true)
     """
-    all_configs, all_defconfigs, config_db, defconfig_db = read_database()
+    _, all_defconfigs, config_db, _ = read_database()
 
     # Start with all defconfigs
     out = all_defconfigs
@@ -1597,19 +1140,19 @@ def prefix_config(cfg):
     >>> prefix_config('A123')
     'CONFIG_A123'
     """
-    op = ''
+    oper = ''
     if cfg[0] == '~':
-        op = cfg[0]
+        oper = cfg[0]
         cfg = cfg[1:]
     if not cfg.startswith('CONFIG_'):
         cfg = 'CONFIG_' + cfg
-    return op + cfg
+    return oper + cfg
 
 
-RE_MK_CONFIGS = re.compile('CONFIG_(\$\(SPL_(?:TPL_)?\))?([A-Za-z0-9_]*)')
-RE_IFDEF = re.compile('(ifdef|ifndef)')
-RE_C_CONFIGS = re.compile('CONFIG_([A-Za-z0-9_]*)')
-RE_CONFIG_IS = re.compile('CONFIG_IS_ENABLED\(([A-Za-z0-9_]*)\)')
+RE_MK_CONFIGS = re.compile(r'CONFIG_(\$\(SPL_(?:TPL_)?\))?([A-Za-z0-9_]*)')
+RE_IFDEF = re.compile(r'(ifdef|ifndef)')
+RE_C_CONFIGS = re.compile(r'CONFIG_([A-Za-z0-9_]*)')
+RE_CONFIG_IS = re.compile(r'CONFIG_IS_ENABLED\(([A-Za-z0-9_]*)\)')
 
 class ConfigUse:
     def __init__(self, cfg, is_spl, fname, rest):
@@ -1651,14 +1194,12 @@ def scan_makefiles(fnames):
     fname_uses = {}
     for fname, rest in fnames:
         m_iter = RE_MK_CONFIGS.finditer(rest)
-        found = False
-        for m in m_iter:
-            found = True
-            real_opt = m.group(2)
+        for mat in m_iter:
+            real_opt = mat.group(2)
             if real_opt == '':
                 continue
             is_spl = False
-            if m.group(1):
+            if mat.group(1):
                 is_spl = True
             use = ConfigUse(real_opt, is_spl, fname, rest)
             if fname not in fname_uses:
@@ -1694,10 +1235,12 @@ def scan_src_files(fnames):
     >>> RE_CONFIG_IS.search('#if CONFIG_IS_ENABLED(OF_PLATDATA)').groups()
     ('OF_PLATDATA',)
     """
+    fname = None
+    rest = None
+
     def add_uses(m_iter, is_spl):
-        for m in m_iter:
-            found = True
-            real_opt = m.group(1)
+        for mat in m_iter:
+            real_opt = mat.group(1)
             if real_opt == '':
                 continue
             use = ConfigUse(real_opt, is_spl, fname, rest)
@@ -1754,7 +1297,7 @@ def do_scan_source(path, do_update):
         """
         # Make sure we know about all the options
         not_found = collections.defaultdict(list)
-        for use, rest in all_uses.items():
+        for use, _ in all_uses.items():
             name = use.cfg
             if name in IGNORE_SYMS:
                 continue
@@ -1766,7 +1309,6 @@ def do_scan_source(path, do_update):
                 # If it is an SPL symbol, try prepending all SPL_ prefixes to
                 # find at least one SPL symbol
                 if use.is_spl:
-                    add_to_dict = False
                     for prefix in SPL_PREFIXES:
                         try_name = prefix + name
                         sym = kconf.syms.get(try_name)
@@ -1784,7 +1326,6 @@ def do_scan_source(path, do_update):
                 elif not use.is_spl:
                     check = False
             else: # MODE_NORMAL
-                debug = False
                 sym = kconf.syms.get(name)
                 if not sym:
                     proper_name = is_not_proper(name)
@@ -1825,7 +1366,7 @@ def do_scan_source(path, do_update):
     print(f'Scanning source in {path}')
     args = ['git', 'grep', '-E', r'IS_ENABLED|\bCONFIG']
     with subprocess.Popen(args, stdout=subprocess.PIPE) as proc:
-        out, err = proc.communicate()
+        out, _ = proc.communicate()
     lines = out.splitlines()
     re_fname = re.compile('^([^:]*):(.*)')
     src_list = []
@@ -1859,7 +1400,7 @@ def do_scan_source(path, do_update):
             print(f'Not sure how to handle file {fname}')
 
     # Scan the Makefiles
-    all_uses, fname_uses = scan_makefiles(mk_list)
+    all_uses, _ = scan_makefiles(mk_list)
 
     spl_not_found = set()
     proper_not_found = set()
@@ -1872,15 +1413,15 @@ def do_scan_source(path, do_update):
     print('\nCONFIG options present in Makefiles but not Kconfig (SPL):')
     not_found = check_not_found(all_uses, MODE_SPL)
     show_uses(not_found)
-    spl_not_found |= set([is_not_proper(key) or key for key in not_found.keys()])
+    spl_not_found |= {is_not_proper(key) or key for key in not_found.keys()}
 
     print('\nCONFIG options used as Proper in Makefiles but without a non-SPL_ variant:')
     not_found = check_not_found(all_uses, MODE_PROPER)
     show_uses(not_found)
-    proper_not_found |= set([key for key in not_found.keys()])
+    proper_not_found |= {not_found.keys()}
 
     # Scan the source code
-    all_uses, fname_uses = scan_src_files(src_list)
+    all_uses, _ = scan_src_files(src_list)
 
     # Make sure we know about all the options
     print('\nCONFIG options present in source but not Kconfig:')
@@ -1890,12 +1431,12 @@ def do_scan_source(path, do_update):
     print('\nCONFIG options present in source but not Kconfig (SPL):')
     not_found = check_not_found(all_uses, MODE_SPL)
     show_uses(not_found)
-    spl_not_found |= set([is_not_proper(key) or key for key in not_found.keys()])
+    spl_not_found |= {is_not_proper(key) or key for key in not_found.keys()}
 
     print('\nCONFIG options used as Proper in source but without a non-SPL_ variant:')
     not_found = check_not_found(all_uses, MODE_PROPER)
     show_uses(not_found)
-    proper_not_found |= set([key for key in not_found.keys()])
+    proper_not_found |= {not_found.keys()}
 
     print('\nCONFIG options used as SPL but without an SPL_ variant:')
     for item in sorted(spl_not_found):
@@ -1907,12 +1448,14 @@ def do_scan_source(path, do_update):
 
     # Write out the updated information
     if do_update:
-        with open(os.path.join(path, 'scripts', 'conf_nospl'), 'w') as out:
+        with open(os.path.join(path, 'scripts', 'conf_nospl'), 'w',
+                  encoding='utf-8') as out:
             print('# These options should not be enabled in SPL builds\n',
                   file=out)
             for item in sorted(spl_not_found):
                 print(item, file=out)
-        with open(os.path.join(path, 'scripts', 'conf_noproper'), 'w') as out:
+        with open(os.path.join(path, 'scripts', 'conf_noproper'), 'w',
+                  encoding='utf-8') as out:
             print('# These options should not be enabled in Proper builds\n',
                   file=out)
             for item in sorted(proper_not_found):
@@ -1938,10 +1481,10 @@ doc/develop/moveconfig.rst for documentation.'''
                       'implying others')
     parser.add_argument('-b', '--build-db', action='store_true', default=False,
                       help='build a CONFIG database')
-    parser.add_argument('-c', '--color', action='store_true', default=False,
-                      help='display the log in color')
     parser.add_argument('-C', '--commit', action='store_true', default=False,
                       help='Create a git commit for the operation')
+    parser.add_argument('--nocolour', action='store_true', default=False,
+                      help="don't display the log in colour")
     parser.add_argument('-d', '--defconfigs', type=str,
                       help='a file containing a list of defconfigs to move, '
                       "one per line (for example 'snow_defconfig') "
@@ -1951,9 +1494,6 @@ doc/develop/moveconfig.rst for documentation.'''
                       help='exit immediately on any error')
     parser.add_argument('-f', '--find', action='store_true', default=False,
                       help='Find boards with a given config combination')
-    parser.add_argument('-H', '--headers-only', dest='cleanup_headers_only',
-                      action='store_true', default=False,
-                      help='only cleanup the headers')
     parser.add_argument('-i', '--imply', action='store_true', default=False,
                       help='find options which imply others')
     parser.add_argument('-I', '--imply-flags', type=str, default='',
@@ -1981,26 +1521,27 @@ doc/develop/moveconfig.rst for documentation.'''
     parser.add_argument('configs', nargs='*')
 
     args = parser.parse_args()
-    configs = args.configs
 
     if args.test:
         sys.argv = [sys.argv[0]]
-        fail, count = doctest.testmod()
+        fail, _ = doctest.testmod()
         if fail:
             return 1
         unittest.main()
 
+    col = terminal.Color(terminal.COLOR_NEVER if args.nocolour
+                         else terminal.COLOR_IF_TERMINAL)
+
     if args.scan_source:
         do_scan_source(os.getcwd(), args.update)
-        return
+        return 0
 
-    if not any((len(configs), args.force_sync, args.build_db, args.imply,
-                args.find)):
+    if not any((args.force_sync, args.build_db, args.imply, args.find)):
         parser.print_usage()
         sys.exit(1)
 
     # prefix the option name with CONFIG_ if missing
-    configs = [prefix_config(cfg) for cfg in configs]
+    configs = [prefix_config(cfg) for cfg in args.configs]
 
     check_top_directory()
 
@@ -2013,40 +1554,36 @@ doc/develop/moveconfig.rst for documentation.'''
             for flag in args.imply_flags.split(','):
                 bad = flag not in IMPLY_FLAGS
                 if bad:
-                    print("Invalid flag '%s'" % flag)
+                    print(f"Invalid flag '{flag}'")
                 if flag == 'help' or bad:
                     print("Imply flags: (separate with ',')")
                     for name, info in IMPLY_FLAGS.items():
-                        print(' %-15s: %s' % (name, info[1]))
+                        print(f' {name:-15s}: {info[1]}')
                     parser.print_usage()
                     sys.exit(1)
                 imply_flags |= IMPLY_FLAGS[flag][0]
 
         do_imply_config(configs, args.add_imply, imply_flags, args.skip_added)
-        return
+        return 0
 
     if args.find:
         do_find_config(configs)
-        return
+        return 0
 
+    # We are either building the database or forcing a sync of defconfigs
     config_db = {}
     db_queue = queue.Queue()
-    t = DatabaseThread(config_db, db_queue)
-    t.setDaemon(True)
-    t.start()
-
-    if not args.cleanup_headers_only:
-        check_clean_directory()
-        bsettings.setup('')
-        toolchains = toolchain.Toolchains()
-        toolchains.GetSettings()
-        toolchains.Scan(verbose=False)
-        move_config(toolchains, configs, args, db_queue)
-        db_queue.join()
-
-    if configs:
-        cleanup_headers(configs, args)
-        cleanup_readme(configs, args)
+    dbt = DatabaseThread(config_db, db_queue)
+    dbt.daemon = True
+    dbt.start()
+
+    check_clean_directory()
+    bsettings.setup('')
+    toolchains = toolchain.Toolchains()
+    toolchains.GetSettings()
+    toolchains.Scan(verbose=False)
+    progress = move_config(toolchains, args, db_queue, col)
+    db_queue.join()
 
     if args.commit:
         subprocess.call(['git', 'add', '-u'])
@@ -2060,13 +1597,28 @@ doc/develop/moveconfig.rst for documentation.'''
             msg += '\n\nRsync all defconfig files using moveconfig.py'
         subprocess.call(['git', 'commit', '-s', '-m', msg])
 
+    failed = progress.total - progress.good
+    failure = f'{failed} failed, ' if failed else ''
     if args.build_db:
-        with open(CONFIG_DATABASE, 'w', encoding='utf-8') as fd:
+        with open(CONFIG_DATABASE, 'w', encoding='utf-8') as outf:
             for defconfig, configs in config_db.items():
-                fd.write('%s\n' % defconfig)
+                outf.write(f'{defconfig}\n')
                 for config in sorted(configs.keys()):
-                    fd.write('   %s=%s\n' % (config, configs[config]))
-                fd.write('\n')
+                    outf.write(f'   {config}={configs[config]}\n')
+                outf.write('\n')
+        print(col.build(
+            col.RED if failed else col.GREEN,
+            f'{failure}{len(config_db)} boards written to {CONFIG_DATABASE}'))
+    else:
+        if failed:
+            print(col.build(col.RED, f'{failure}see {FAILED_LIST}', True))
+        else:
+            # Add enough spaces to overwrite the progress indicator
+            print(col.build(
+                col.GREEN, f'{progress.total} processed        ', bright=True))
+
+    return 0
+
 
 if __name__ == '__main__':
     sys.exit(main())