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(parent: c7c4fe0) | patch
Exynos5: clock: Update the equation to calculate PLL output frequency
authorAkshay Saraswat <akshay.s@samsung.com>
Fri, 22 Mar 2013 02:26:36 +0000 (02:26 +0000)
committerMinkyu Kang <mk7.kang@samsung.com>
Tue, 21 May 2013 11:17:30 +0000 (20:17 +0900)
commit234370cab4b2f096e095fe8f3284fd39740a4023
tree1ce12817aa13a62f65562f5b9191de5956e4a892tree | snapshot
parentc7c4fe072eeb95852f4a015df3c1a39b37caae51commit | diff
Exynos5: clock: Update the equation to calculate PLL output frequency

According to the latest exynos5 user manual, the equation for
calculating PLL output was changed to
FOUT= MDIV x FIN/(PDIV x 2^SDIV)
earlier it was
FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
So updating the clock code accordingly.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
arch/arm/cpu/armv7/exynos/clock.c diff | blob | history
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