X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=drivers%2Fnet%2Fwireless%2Fath%2Fath9k%2Feeprom_9287.c;h=90d771fa2dea26b4523ac2b20c2b3df5b5d27d3a;hb=ca2c68cc7bc80fc4504fb420df04cce99c9ee6ec;hp=343fc9f946dbc7dcb6b613cad3cff3b2bb12e84e;hpb=e6625fa48e6580a74b7e700efd7e6463e282810b;p=pandora-kernel.git diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c index 343fc9f946db..90d771fa2dea 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c +++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c @@ -14,6 +14,7 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ +#include #include "hw.h" #include "ar9002_phy.h" @@ -75,6 +76,111 @@ static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah) return __ath9k_hw_ar9287_fill_eeprom(ah); } +#if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS) +static u32 ar9287_dump_modal_eeprom(char *buf, u32 len, u32 size, + struct modal_eep_ar9287_header *modal_hdr) +{ + PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]); + PR_EEP("Chain1 Ant. Control", modal_hdr->antCtrlChain[1]); + PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon); + PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]); + PR_EEP("Chain1 Ant. Gain", modal_hdr->antennaGainCh[1]); + PR_EEP("Switch Settle", modal_hdr->switchSettling); + PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]); + PR_EEP("Chain1 TxRxAtten", modal_hdr->txRxAttenCh[1]); + PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]); + PR_EEP("Chain1 RxTxMargin", modal_hdr->rxTxMarginCh[1]); + PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize); + PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff); + PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn); + PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn); + PR_EEP("CCA Threshold)", modal_hdr->thresh62); + PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]); + PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]); + PR_EEP("xpdGain", modal_hdr->xpdGain); + PR_EEP("External PD", modal_hdr->xpd); + PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]); + PR_EEP("Chain1 I Coefficient", modal_hdr->iqCalICh[1]); + PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]); + PR_EEP("Chain1 Q Coefficient", modal_hdr->iqCalQCh[1]); + PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap); + PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl); + PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart); + PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn); + PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc); + PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]); + PR_EEP("Chain1 bswAtten", modal_hdr->bswAtten[1]); + PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]); + PR_EEP("Chain1 bswMargin", modal_hdr->bswMargin[1]); + PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40); + PR_EEP("AR92x7 Version", modal_hdr->version); + PR_EEP("DriverBias1", modal_hdr->db1); + PR_EEP("DriverBias2", modal_hdr->db1); + PR_EEP("CCK OutputBias", modal_hdr->ob_cck); + PR_EEP("PSK OutputBias", modal_hdr->ob_psk); + PR_EEP("QAM OutputBias", modal_hdr->ob_qam); + PR_EEP("PAL_OFF OutputBias", modal_hdr->ob_pal_off); + + return len; +} + +static u32 ath9k_hw_ar9287_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, + u8 *buf, u32 len, u32 size) +{ + struct ar9287_eeprom *eep = &ah->eeprom.map9287; + struct base_eep_ar9287_header *pBase = &eep->baseEepHeader; + + if (!dump_base_hdr) { + len += snprintf(buf + len, size - len, + "%20s :\n", "2GHz modal Header"); + len += ar9287_dump_modal_eeprom(buf, len, size, + &eep->modalHeader); + goto out; + } + + PR_EEP("Major Version", pBase->version >> 12); + PR_EEP("Minor Version", pBase->version & 0xFFF); + PR_EEP("Checksum", pBase->checksum); + PR_EEP("Length", pBase->length); + PR_EEP("RegDomain1", pBase->regDmn[0]); + PR_EEP("RegDomain2", pBase->regDmn[1]); + PR_EEP("TX Mask", pBase->txMask); + PR_EEP("RX Mask", pBase->rxMask); + PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A)); + PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G)); + PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags & + AR5416_OPFLAGS_N_2G_HT20)); + PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags & + AR5416_OPFLAGS_N_2G_HT40)); + PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags & + AR5416_OPFLAGS_N_5G_HT20)); + PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags & + AR5416_OPFLAGS_N_5G_HT40)); + PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01)); + PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF); + PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF); + PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF); + PR_EEP("Power Table Offset", pBase->pwrTableOffset); + PR_EEP("OpenLoop Power Ctrl", pBase->openLoopPwrCntl); + + len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress", + pBase->macAddr); + +out: + if (len > size) + len = size; + + return len; +} +#else +static u32 ath9k_hw_ar9287_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, + u8 *buf, u32 len, u32 size) +{ + return 0; +} +#endif + + static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah) { u32 sum = 0, el, integer; @@ -195,11 +301,11 @@ static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah, case EEP_NFTHRESH_2: return pModal->noiseFloorThreshCh[0]; case EEP_MAC_LSW: - return pBase->macAddr[0] << 8 | pBase->macAddr[1]; + return get_unaligned_be16(pBase->macAddr); case EEP_MAC_MID: - return pBase->macAddr[2] << 8 | pBase->macAddr[3]; + return get_unaligned_be16(pBase->macAddr + 2); case EEP_MAC_MSW: - return pBase->macAddr[4] << 8 | pBase->macAddr[5]; + return get_unaligned_be16(pBase->macAddr + 4); case EEP_REG_0: return pBase->regDmn[0]; case EEP_REG_1: @@ -230,6 +336,9 @@ static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah, return pBase->tempSensSlopePalOn; else return 0; + case EEP_ANTENNA_GAIN_2G: + return max_t(u8, pModal->antennaGainCh[0], + pModal->antennaGainCh[1]); default: return 0; } @@ -306,8 +415,7 @@ static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah, } static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah, - struct ath9k_channel *chan, - int16_t *pTxPowerIndexOffset) + struct ath9k_channel *chan) { struct cal_data_per_freq_ar9287 *pRawDataset; struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop; @@ -434,10 +542,7 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah, (672 << 2) + regChainOffset; for (j = 0; j < 32; j++) { - reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) - | ((pdadcValues[4*j + 1] & 0xFF) << 8) - | ((pdadcValues[4*j + 2] & 0xFF) << 16) - | ((pdadcValues[4*j + 3] & 0xFF) << 24); + reg32 = get_unaligned_le32(&pdadcValues[4 * j]); REG_WRITE(ah, regOffset, reg32); regOffset += 4; @@ -446,16 +551,13 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah, REGWRITE_BUFFER_FLUSH(ah); } } - - *pTxPowerIndexOffset = 0; } static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl, - u16 AntennaReduction, - u16 twiceMaxRegulatoryPower, + u16 antenna_reduction, u16 powerLimit) { #define CMP_CTL \ @@ -469,12 +571,8 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah, #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 - struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); u16 twiceMaxEdgePower = MAX_RATE_POWER; - static const u16 tpScaleReductionTable[5] = - { 0, 3, 6, 9, MAX_RATE_POWER }; int i; - int16_t twiceLargestAntenna; struct cal_ctl_data_ar9287 *rep; struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} }, targetPowerCck = {0, {0, 0, 0, 0} }; @@ -482,7 +580,7 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah, targetPowerCckExt = {0, {0, 0, 0, 0} }; struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0} }; - u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; + u16 scaledPower = 0, minCtlPower; static const u16 ctlModesFor11g[] = { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 @@ -497,24 +595,7 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah, tx_chainmask = ah->txchainmask; ath9k_hw_get_channel_centers(ah, chan, ¢ers); - - /* Compute TxPower reduction due to Antenna Gain */ - twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0], - pEepData->modalHeader.antennaGainCh[1]); - twiceLargestAntenna = (int16_t)min((AntennaReduction) - - twiceLargestAntenna, 0); - - /* - * scaledPower is the minimum of the user input power level - * and the regulatory allowed power level. - */ - maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; - - if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) - maxRegAllowedPower -= - (tpScaleReductionTable[(regulatory->tp_scale)] * 2); - - scaledPower = min(powerLimit, maxRegAllowedPower); + scaledPower = powerLimit - antenna_reduction; /* * Reduce scaled Power by number of chains active @@ -715,14 +796,12 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah, static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, - u8 twiceMaxRegulatoryPower, u8 powerLimit, bool test) { struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader; int16_t ratesArray[Ar5416RateSize]; - int16_t txPowerIndexOffset = 0; u8 ht40PowerIncForPdadc = 2; int i; @@ -735,14 +814,12 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah, ath9k_hw_set_ar9287_power_per_rate_table(ah, chan, &ratesArray[0], cfgCtl, twiceAntennaReduction, - twiceMaxRegulatoryPower, powerLimit); - ath9k_hw_set_ar9287_power_cal_table(ah, chan, &txPowerIndexOffset); + ath9k_hw_set_ar9287_power_cal_table(ah, chan); regulatory->max_power_level = 0; for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { - ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); if (ratesArray[i] > MAX_RATE_POWER) ratesArray[i] = MAX_RATE_POWER; @@ -753,17 +830,8 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah, if (test) return; - if (IS_CHAN_2GHZ(chan)) - i = rate1l; - else - i = rate6mb; - - regulatory->max_power_level = ratesArray[i]; - - if (AR_SREV_9280_20_OR_LATER(ah)) { - for (i = 0; i < Ar5416RateSize; i++) - ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2; - } + for (i = 0; i < Ar5416RateSize; i++) + ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2; ENABLE_REGWRITE_BUFFER(ah); @@ -853,11 +921,6 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah, REGWRITE_BUFFER_FLUSH(ah); } -static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah, - struct ath9k_channel *chan) -{ -} - static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah, struct ath9k_channel *chan) { @@ -1005,10 +1068,10 @@ const struct eeprom_ops eep_ar9287_ops = { .check_eeprom = ath9k_hw_ar9287_check_eeprom, .get_eeprom = ath9k_hw_ar9287_get_eeprom, .fill_eeprom = ath9k_hw_ar9287_fill_eeprom, + .dump_eeprom = ath9k_hw_ar9287_dump_eeprom, .get_eeprom_ver = ath9k_hw_ar9287_get_eeprom_ver, .get_eeprom_rev = ath9k_hw_ar9287_get_eeprom_rev, .set_board_values = ath9k_hw_ar9287_set_board_values, - .set_addac = ath9k_hw_ar9287_set_addac, .set_txpower = ath9k_hw_ar9287_set_txpower, .get_spur_channel = ath9k_hw_ar9287_get_spur_channel };