X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=arch%2Fmips%2Fkernel%2Firq.c;h=6045b9a51a35f74e218db115dc98b4554670b1e2;hb=7e2225d860772aaa07e1cebca6a5aa6f93f9aa91;hp=aeded6c17de52af0ed308cacd953aa3936363f14;hpb=1f8a6b658a943b4f04a1fc7b3a420360202c86cd;p=pandora-kernel.git diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index aeded6c17de5..6045b9a51a35 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -44,8 +44,6 @@ again: return irq; } -EXPORT_SYMBOL_GPL(allocate_irqno); - /* * Allocate the 16 legacy interrupts for i8259 devices. This happens early * in the kernel initialization so treating allocation failure as BUG() is @@ -66,28 +64,18 @@ void free_irqno(unsigned int irq) smp_mb__after_clear_bit(); } -EXPORT_SYMBOL_GPL(free_irqno); - /* * 'what should we do if we get a hw irq event on an illegal vector'. * each architecture has to answer this themselves. */ void ack_bad_irq(unsigned int irq) { + smtc_im_ack_irq(irq); printk("unexpected IRQ # %d\n", irq); } atomic_t irq_err_count; -#ifdef CONFIG_MIPS_MT_SMTC -/* - * SMTC Kernel needs to manipulate low-level CPU interrupt mask - * in do_IRQ. These are passed in setup_irq_smtc() and stored - * in this table. - */ -unsigned long irq_hwmask[NR_IRQS]; -#endif /* CONFIG_MIPS_MT_SMTC */ - /* * Generic, controller-independent functions: */ @@ -101,7 +89,7 @@ int show_interrupts(struct seq_file *p, void *v) if (i == 0) { seq_printf(p, " "); for_each_online_cpu(j) - seq_printf(p, "CPU%d ",j); + seq_printf(p, "CPU%d ", j); seq_putc(p, '\n'); } @@ -110,7 +98,7 @@ int show_interrupts(struct seq_file *p, void *v) action = irq_desc[i].action; if (!action) goto skip; - seq_printf(p, "%3d: ",i); + seq_printf(p, "%3d: ", i); #ifndef CONFIG_SMP seq_printf(p, "%10u ", kstat_irqs(i)); #else @@ -153,6 +141,11 @@ __setup("nokgdb", nokgdb); void __init init_IRQ(void) { + int i; + + for (i = 0; i < NR_IRQS; i++) + set_irq_noprobe(i); + arch_init_irq(); #ifdef CONFIG_KGDB