X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=arch%2Fblackfin%2Fmach-bf518%2Finclude%2Fmach%2Fbfin_serial_5xx.h;h=0fb2ce5d840e14ae73ba9058d19e4da9f3bd0733;hb=049da6393fb30b62e418beb59a74dfcad513fc6d;hp=e21c1c3e4ec7e8129b87989c81e49f9f4001a6a0;hpb=5412b5399e095730008a14f2107331b2123733e4;p=pandora-kernel.git diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h index e21c1c3e4ec7..0fb2ce5d840e 100644 --- a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h @@ -53,9 +53,9 @@ #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) -#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) -#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) -#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) +#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin)) +#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) +#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) @@ -87,6 +87,7 @@ struct bfin_serial_port { struct uart_port port; unsigned int old_status; + int status_irq; unsigned int lsr; #ifdef CONFIG_SERIAL_BFIN_DMA int tx_done; @@ -125,6 +126,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; + int uart_status_irq; #ifdef CONFIG_SERIAL_BFIN_DMA unsigned int uart_tx_dma_channel; unsigned int uart_rx_dma_channel; @@ -140,6 +142,7 @@ struct bfin_serial_res bfin_serial_resource[] = { { 0xFFC00400, IRQ_UART0_RX, + IRQ_UART0_ERROR, #ifdef CONFIG_SERIAL_BFIN_DMA CH_UART0_TX, CH_UART0_RX, @@ -154,6 +157,7 @@ struct bfin_serial_res bfin_serial_resource[] = { { 0xFFC02000, IRQ_UART1_RX, + IRQ_UART1_ERROR, #ifdef CONFIG_SERIAL_BFIN_DMA CH_UART1_TX, CH_UART1_RX,