X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=arch%2Farm%2Fmach-s5pc100%2Fsetup-ide.c;h=223aae044466f59f46d8d9aa614c3b07e51a80a8;hb=17f490bcedd7b6677140b2d49efe9e9e6b84de60;hp=83575671fb598510beedd045ce31f67197f79713;hpb=763008c4357b73c8d18396dfd8d79dc58fa3f99d;p=pandora-kernel.git

diff --git a/arch/arm/mach-s5pc100/setup-ide.c b/arch/arm/mach-s5pc100/setup-ide.c
index 83575671fb59..223aae044466 100644
--- a/arch/arm/mach-s5pc100/setup-ide.c
+++ b/arch/arm/mach-s5pc100/setup-ide.c
@@ -17,52 +17,39 @@
 #include <mach/regs-clock.h>
 #include <plat/gpio-cfg.h>
 
+static void s5pc100_ide_cfg_gpios(unsigned int base, unsigned int nr)
+{
+	s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4));
+
+	for (; nr > 0; nr--, base++)
+		s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
+}
+
 void s5pc100_ide_setup_gpio(void)
 {
 	u32 reg;
-	u32 gpio = 0;
 
 	/* Independent CF interface, CF chip select configuration */
 	reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f);
 	writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG);
 
 	/* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
-	for (gpio = S5PC100_GPJ0(0); gpio <= S5PC100_GPJ0(7); gpio++) {
-		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
-		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-	}
+	s5pc100_ide_cfg_gpios(S5PC100_GPJ0(0), 8);
 
 	/*CF_Data[0 - 7] */
-	for (gpio = S5PC100_GPJ2(0); gpio <= S5PC100_GPJ2(7); gpio++) {
-		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
-		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-	}
+	s5pc100_ide_cfg_gpios(S5PC100_GPJ2(0), 8);
 
 	/* CF_Data[8 - 15] */
-	for (gpio = S5PC100_GPJ3(0); gpio <= S5PC100_GPJ3(7); gpio++) {
-		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
-		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-	}
+	s5pc100_ide_cfg_gpios(S5PC100_GPJ3(0), 8);
 
 	/* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
-	for (gpio = S5PC100_GPJ4(0); gpio <= S5PC100_GPJ4(3); gpio++) {
-		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
-		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-	}
+	s5pc100_ide_cfg_gpios(S5PC100_GPJ4(0), 4);
 
 	/* EBI_OE, EBI_WE */
-	for (gpio = S5PC100_GPK0(6); gpio <= S5PC100_GPK0(7); gpio++)
-		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0));
+	s3c_gpio_cfgpin_range(S5PC100_GPK0(6), 2, S3C_GPIO_SFN(0));
 
 	/* CF_OE, CF_WE */
-	for (gpio = S5PC100_GPK1(6); gpio <= S5PC100_GPK1(7); gpio++) {
-		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-	}
+	s3c_gpio_cfgrange_nopull(S5PC100_GPK1(6), 8, S3C_GPIO_SFN(2));
 
 	/* CF_CD */
 	s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2));