X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=arch%2Farm%2Fmach-davinci%2Finclude%2Fmach%2Fedma.h;h=eb8bfd7925e78cc49b163debac7a6149c8f10ad7;hb=a3ccf63ee643ef243cbf8918da8b3f9238f10029;hp=24a379239d7f836c3794af1e5d8218dac37463f4;hpb=1da1daed813c534263a87ffc36d5b775e65231ad;p=pandora-kernel.git

diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index 24a379239d7f..eb8bfd7925e7 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -139,6 +139,54 @@ struct edmacc_param {
 #define DAVINCI_DMA_PWM1                 53
 #define DAVINCI_DMA_PWM2                 54
 
+/* DA830 specific EDMA3 information */
+#define EDMA_DA830_NUM_DMACH		32
+#define EDMA_DA830_NUM_TCC		32
+#define EDMA_DA830_NUM_PARAMENTRY	128
+#define EDMA_DA830_NUM_EVQUE		2
+#define EDMA_DA830_NUM_TC		2
+#define EDMA_DA830_CHMAP_EXIST		0
+#define EDMA_DA830_NUM_REGIONS		4
+#define DA830_DMACH2EVENT_MAP0		0x000FC03Fu
+#define DA830_DMACH2EVENT_MAP1		0x00000000u
+#define DA830_EDMA_ARM_OWN		0x30FFCCFFu
+
+/* DA830 specific EDMA3 Events Information */
+enum DA830_edma_ch {
+	DA830_DMACH_MCASP0_RX,
+	DA830_DMACH_MCASP0_TX,
+	DA830_DMACH_MCASP1_RX,
+	DA830_DMACH_MCASP1_TX,
+	DA830_DMACH_MCASP2_RX,
+	DA830_DMACH_MCASP2_TX,
+	DA830_DMACH_GPIO_BNK0INT,
+	DA830_DMACH_GPIO_BNK1INT,
+	DA830_DMACH_UART0_RX,
+	DA830_DMACH_UART0_TX,
+	DA830_DMACH_TMR64P0_EVTOUT12,
+	DA830_DMACH_TMR64P0_EVTOUT34,
+	DA830_DMACH_UART1_RX,
+	DA830_DMACH_UART1_TX,
+	DA830_DMACH_SPI0_RX,
+	DA830_DMACH_SPI0_TX,
+	DA830_DMACH_MMCSD_RX,
+	DA830_DMACH_MMCSD_TX,
+	DA830_DMACH_SPI1_RX,
+	DA830_DMACH_SPI1_TX,
+	DA830_DMACH_DMAX_EVTOUT6,
+	DA830_DMACH_DMAX_EVTOUT7,
+	DA830_DMACH_GPIO_BNK2INT,
+	DA830_DMACH_GPIO_BNK3INT,
+	DA830_DMACH_I2C0_RX,
+	DA830_DMACH_I2C0_TX,
+	DA830_DMACH_I2C1_RX,
+	DA830_DMACH_I2C1_TX,
+	DA830_DMACH_GPIO_BNK4INT,
+	DA830_DMACH_GPIO_BNK5INT,
+	DA830_DMACH_UART2_RX,
+	DA830_DMACH_UART2_TX
+};
+
 /*ch_status paramater of callback function possible values*/
 #define DMA_COMPLETE 1
 #define DMA_CC_ERROR 2
@@ -162,6 +210,8 @@ enum fifo_width {
 enum dma_event_q {
 	EVENTQ_0 = 0,
 	EVENTQ_1 = 1,
+	EVENTQ_2 = 2,
+	EVENTQ_3 = 3,
 	EVENTQ_DEFAULT = -1
 };
 
@@ -170,8 +220,15 @@ enum sync_dimension {
 	ABSYNC = 1
 };
 
+#define EDMA_CTLR_CHAN(ctlr, chan)	(((ctlr) << 16) | (chan))
+#define EDMA_CTLR(i)			((i) >> 16)
+#define EDMA_CHAN_SLOT(i)		((i) & 0xffff)
+
 #define EDMA_CHANNEL_ANY		-1	/* for edma_alloc_channel() */
 #define EDMA_SLOT_ANY			-1	/* for edma_alloc_slot() */
+#define EDMA_CONT_PARAMS_ANY		 1001
+#define EDMA_CONT_PARAMS_FIXED_EXACT	 1002
+#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
 
 /* alloc/free DMA channels and their dedicated parameter RAM slots */
 int edma_alloc_channel(int channel,
@@ -180,9 +237,13 @@ int edma_alloc_channel(int channel,
 void edma_free_channel(unsigned channel);
 
 /* alloc/free parameter RAM slots */
-int edma_alloc_slot(int slot);
+int edma_alloc_slot(unsigned ctlr, int slot);
 void edma_free_slot(unsigned slot);
 
+/* alloc/free a set of contiguous parameter RAM slots */
+int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
+int edma_free_cont_slots(unsigned slot, int count);
+
 /* calls that operate on part of a parameter RAM slot */
 void edma_set_src(unsigned slot, dma_addr_t src_port,
 				enum address_mode mode, enum fifo_width);
@@ -216,9 +277,13 @@ struct edma_soc_info {
 	unsigned	n_region;
 	unsigned	n_slot;
 	unsigned	n_tc;
+	unsigned	n_cc;
+	enum dma_event_q	default_queue;
 
 	/* list of channels with no even trigger; terminated by "-1" */
 	const s8	*noevent;
+	const s8	(*queue_tc_mapping)[2];
+	const s8	(*queue_priority_mapping)[2];
 };
 
 #endif