X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=Documentation%2Farm%2FSharp-LH%2FIOBarrier;h=2e953e228f4d7295d4f847cf531fb1719cc64a35;hb=a247b5d594aafe3a0121ae658a974cbea32e18d6;hp=c0d8853672dc9e533e4be07c573c5e2918331038;hpb=b885b27ce67013a7aa7f4181fdd916a29c623850;p=pandora-kernel.git

diff --git a/Documentation/arm/Sharp-LH/IOBarrier b/Documentation/arm/Sharp-LH/IOBarrier
index c0d8853672dc..2e953e228f4d 100644
--- a/Documentation/arm/Sharp-LH/IOBarrier
+++ b/Documentation/arm/Sharp-LH/IOBarrier
@@ -32,7 +32,7 @@ BARRIER IO before the access to the SMC chip because the AEN latch
 only needs occurs after the SMC IO write cycle.  The routines that
 implement this work-around make an additional concession which is to
 disable interrupts during the IO sequence.  Other hardware devices
-(the LogicPD CPLD) have registers in the same the physical memory
+(the LogicPD CPLD) have registers in the same physical memory
 region as the SMC chip.  An interrupt might allow an access to one of
 those registers while SMC IO is being performed.