X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=Documentation%2FDocBook%2Fuio-howto.tmpl;h=df87d1b93605ac54cf400bd7b8d44b0866d0789a;hb=eda3d8f5604860aae1bb9996bb5efc4213778369;hp=fdd7f4f887b75ba7bc96b7ab81b9abc7d3348d73;hpb=e1cca7e8d484390169777b423a7fe46c7021fec1;p=pandora-kernel.git
diff --git a/Documentation/DocBook/uio-howto.tmpl b/Documentation/DocBook/uio-howto.tmpl
index fdd7f4f887b7..df87d1b93605 100644
--- a/Documentation/DocBook/uio-howto.tmpl
+++ b/Documentation/DocBook/uio-howto.tmpl
@@ -21,6 +21,18 @@
+
+ 2006-2008
+ Hans-Jürgen Koch.
+
+
+
+
+This documentation is Free Software licensed under the terms of the
+GPL version 2.
+
+
+
2006-12-11
@@ -29,6 +41,12 @@
+
+ 0.5
+ 2008-05-22
+ hjk
+ Added description of write() function.
+
0.4
2007-11-26
@@ -57,20 +75,9 @@
-
+
About this document
-
-
-Copyright and License
-
- Copyright (c) 2006 by Hans-Jürgen Koch.
-
-This documentation is Free Software licensed under the terms of the
-GPL version 2.
-
-
-
Translations
@@ -189,6 +196,30 @@ interested in translating it, please email me
represents the total interrupt count. You can use this number
to figure out if you missed some interrupts.
+
+ For some hardware that has more than one interrupt source internally,
+ but not separate IRQ mask and status registers, there might be
+ situations where userspace cannot determine what the interrupt source
+ was if the kernel handler disables them by writing to the chip's IRQ
+ register. In such a case, the kernel has to disable the IRQ completely
+ to leave the chip's register untouched. Now the userspace part can
+ determine the cause of the interrupt, but it cannot re-enable
+ interrupts. Another cornercase is chips where re-enabling interrupts
+ is a read-modify-write operation to a combined IRQ status/acknowledge
+ register. This would be racy if a new interrupt occurred
+ simultaneously.
+
+
+ To address these problems, UIO also implements a write() function. It
+ is normally not used and can be ignored for hardware that has only a
+ single interrupt source or has separate IRQ mask and status registers.
+ If you need it, however, a write to /dev/uioX
+ will call the irqcontrol() function implemented
+ by the driver. You have to write a 32-bit value that is usually either
+ 0 or 1 to disable or enable interrupts. If a driver does not implement
+ irqcontrol(), write() will
+ return with -ENOSYS.
+
To handle interrupts properly, your custom kernel module can
@@ -362,6 +393,14 @@ device is actually used.
open(), you will probably also want a custom
release() function.
+
+
+int (*irqcontrol)(struct uio_info *info, s32 irq_on)
+: Optional. If you need to be able to enable or disable
+interrupts from userspace by writing to /dev/uioX,
+you can implement this function. The parameter irq_on
+will be 0 to disable interrupts and 1 to enable them.
+