static inline int get_hub_status_data(struct uhci_hcd *uhci, char *buf)
{
int port;
+ int mask = RWC_BITS;
+
+ /* Some boards (both VIA and Intel apparently) report bogus
+ * overcurrent indications, causing massive log spam unless
+ * we completely ignore them. This doesn't seem to be a problem
+ * with the chipset so much as with the way it is connected on
+ * the motherboard; if the overcurrent input is left to float
+ * then it may constantly register false positives. */
+ if (ignore_oc)
+ mask &= ~USBPORTSC_OCC;
*buf = 0;
for (port = 0; port < uhci->rh_numports; ++port) {
- if ((inw(uhci->io_addr + USBPORTSC1 + port * 2) & RWC_BITS) ||
+ if ((inw(uhci->io_addr + USBPORTSC1 + port * 2) & mask) ||
test_bit(port, &uhci->port_c_suspend))
*buf |= (1 << (port + 1));
}
unsigned long port_addr)
{
int status;
+ int i;
- if (test_bit(port, &uhci->suspended_ports)) {
+ if (inw(port_addr) & (USBPORTSC_SUSP | USBPORTSC_RD)) {
CLR_RH_PORTSTAT(USBPORTSC_SUSP | USBPORTSC_RD);
- clear_bit(port, &uhci->suspended_ports);
- clear_bit(port, &uhci->resuming_ports);
- set_bit(port, &uhci->port_c_suspend);
+ if (test_bit(port, &uhci->resuming_ports))
+ set_bit(port, &uhci->port_c_suspend);
/* The controller won't actually turn off the RD bit until
* it has had a chance to send a low-speed EOP sequence,
- * which takes 3 bit times (= 2 microseconds). We'll delay
- * slightly longer for good luck. */
- udelay(4);
+ * which is supposed to take 3 bit times (= 2 microseconds).
+ * Experiments show that some controllers take longer, so
+ * we'll poll for completion. */
+ for (i = 0; i < 10; ++i) {
+ if (!(inw(port_addr) & USBPORTSC_RD))
+ break;
+ udelay(1);
+ }
+ }
+ clear_bit(port, &uhci->resuming_ports);
+}
+
+/* Wait for the UHCI controller in HP's iLO2 server management chip.
+ * It can take up to 250 us to finish a reset and set the CSC bit.
+ */
+static void wait_for_HP(unsigned long port_addr)
+{
+ int i;
+
+ for (i = 10; i < 250; i += 10) {
+ if (inw(port_addr) & USBPORTSC_CSC)
+ return;
+ udelay(10);
}
+ /* Log a warning? */
}
static void uhci_check_ports(struct uhci_hcd *uhci)
CLR_RH_PORTSTAT(USBPORTSC_PR);
udelay(10);
+ /* HP's server management chip requires
+ * a longer delay. */
+ if (to_pci_dev(uhci_dev(uhci))->vendor ==
+ PCI_VENDOR_ID_HP)
+ wait_for_HP(port_addr);
+
/* If the port was enabled before, turning
* reset on caused a port enable change.
* Turning reset off causes a port connect
{
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
unsigned long flags;
- int status;
+ int status = 0;
spin_lock_irqsave(&uhci->lock, flags);
- if (uhci->hc_inaccessible) {
- status = 0;
- goto done;
- }
+ uhci_scan_schedule(uhci);
+ if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) || uhci->dead)
+ goto done;
uhci_check_ports(uhci);
+
status = get_hub_status_data(uhci, buf);
switch (uhci->rh_state) {
u16 wPortChange, wPortStatus;
unsigned long flags;
- if (uhci->hc_inaccessible)
+ if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) || uhci->dead)
return -ETIMEDOUT;
spin_lock_irqsave(&uhci->lock, flags);
wPortChange |= USB_PORT_STAT_C_CONNECTION;
if (status & USBPORTSC_PEC)
wPortChange |= USB_PORT_STAT_C_ENABLE;
- if (status & USBPORTSC_OCC)
+ if ((status & USBPORTSC_OCC) && !ignore_oc)
wPortChange |= USB_PORT_STAT_C_OVERCURRENT;
if (test_bit(port, &uhci->port_c_suspend)) {
wPortChange |= USB_PORT_STAT_C_SUSPEND;
lstatus |= 1;
}
- if (test_bit(port, &uhci->suspended_ports))
- lstatus |= 2;
if (test_bit(port, &uhci->resuming_ports))
lstatus |= 4;
switch (wValue) {
case USB_PORT_FEAT_SUSPEND:
- set_bit(port, &uhci->suspended_ports);
SET_RH_PORTSTAT(USBPORTSC_SUSP);
OK(0);
case USB_PORT_FEAT_RESET:
CLR_RH_PORTSTAT(USBPORTSC_PEC);
OK(0);
case USB_PORT_FEAT_SUSPEND:
- if (test_bit(port, &uhci->suspended_ports) &&
- !test_and_set_bit(port,
+ if (!(inw(port_addr) & USBPORTSC_SUSP)) {
+
+ /* Make certain the port isn't suspended */
+ uhci_finish_suspend(uhci, port, port_addr);
+ } else if (!test_and_set_bit(port,
&uhci->resuming_ports)) {
SET_RH_PORTSTAT(USBPORTSC_RD);