Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6

[pandora-kernel.git] / drivers / gpu / drm / radeon / evergreend.h

diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 36d32d8..9aaa3f0 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -98,6 +98,7 @@
 #define                BUF_SWAP_32BIT                                  (2 << 16)
 #define        CP_RB_RPTR                                      0x8700
 #define        CP_RB_RPTR_ADDR                                 0xC10C
+#define                RB_RPTR_SWAP(x)                                 ((x) << 0)
 #define        CP_RB_RPTR_ADDR_HI                              0xC110
 #define        CP_RB_RPTR_WR                                   0xC108
 #define        CP_RB_WPTR                                      0xC114
@@ -240,6 +241,7 @@
 #define                FORCE_EOV_MAX_CLK_CNT(x)                        ((x) << 0)
 #define                FORCE_EOV_MAX_REZ_CNT(x)                        ((x) << 16)
 #define PA_SC_LINE_STIPPLE                             0x28A0C
+#define        PA_SU_LINE_STIPPLE_VALUE                        0x8A60
 #define        PA_SC_LINE_STIPPLE_STATE                        0x8B10
 
 #define        SCRATCH_REG0                                    0x8500
@@ -652,6 +654,7 @@
 #define        PACKET3_DISPATCH_DIRECT                         0x15
 #define        PACKET3_DISPATCH_INDIRECT                       0x16
 #define        PACKET3_INDIRECT_BUFFER_END                     0x17
+#define        PACKET3_MODE_CONTROL                            0x18
 #define        PACKET3_SET_PREDICATION                         0x20
 #define        PACKET3_REG_RMW                                 0x21
 #define        PACKET3_COND_EXEC                               0x22
@@ -752,13 +755,21 @@
 
 #define SQ_CONST_MEM_BASE                              0x8df8
 
+#define SQ_ESGS_RING_BASE                              0x8c40
 #define SQ_ESGS_RING_SIZE                              0x8c44
+#define SQ_GSVS_RING_BASE                              0x8c48
 #define SQ_GSVS_RING_SIZE                              0x8c4c
+#define SQ_ESTMP_RING_BASE                             0x8c50
 #define SQ_ESTMP_RING_SIZE                             0x8c54
+#define SQ_GSTMP_RING_BASE                             0x8c58
 #define SQ_GSTMP_RING_SIZE                             0x8c5c
+#define SQ_VSTMP_RING_BASE                             0x8c60
 #define SQ_VSTMP_RING_SIZE                             0x8c64
+#define SQ_PSTMP_RING_BASE                             0x8c68
 #define SQ_PSTMP_RING_SIZE                             0x8c6c
+#define SQ_LSTMP_RING_BASE                             0x8e10
 #define SQ_LSTMP_RING_SIZE                             0x8e14
+#define SQ_HSTMP_RING_BASE                             0x8e18
 #define SQ_HSTMP_RING_SIZE                             0x8e1c
 #define VGT_TF_RING_SIZE                               0x8988
 
@@ -1090,5 +1101,14 @@
 #define SQ_TEX_RESOURCE_WORD6_0                         0x30018
 #define SQ_TEX_RESOURCE_WORD7_0                         0x3001c
 
+/* cayman 3D regs */
+#define CAYMAN_VGT_OFFCHIP_LDS_BASE                    0x89B0
+#define CAYMAN_DB_EQAA                                 0x28804
+#define CAYMAN_DB_DEPTH_INFO                           0x2803C
+#define CAYMAN_PA_SC_AA_CONFIG                         0x28BE0
+#define         CAYMAN_MSAA_NUM_SAMPLES_SHIFT           0
+#define         CAYMAN_MSAA_NUM_SAMPLES_MASK            0x7
+/* cayman packet3 addition */
+#define        CAYMAN_PACKET3_DEALLOC_STATE                    0x14
 
 #endif