#ifndef __MACH_MX27_H__
#define __MACH_MX27_H__
+#ifndef __ASSEMBLER__
+#include <linux/io.h>
+#endif
+
#define MX27_AIPI_BASE_ADDR 0x10000000
#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000
#define MX27_AIPI_SIZE SZ_1M
#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
+#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
+#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
+#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
+#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
+
#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
/* IRAM */
IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \
IMX_IO_ADDRESS(x, MX27_X_MEMC))
+#ifndef __ASSEMBLER__
+static inline void mx27_setup_weimcs(size_t cs,
+ unsigned upper, unsigned lower, unsigned addional)
+{
+ __raw_writel(upper, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs)));
+ __raw_writel(lower, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs)));
+ __raw_writel(addional, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs)));
+}
+#endif
+
/* fixed interrupt numbers */
#define MX27_INT_I2C2 1
#define MX27_INT_GPT6 2