2 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3 * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 extern void imx_gpio_mode (int gpio_mode);
38 struct system_control_regs {
65 /* Chip Select Registers */
67 u32 cs0u; /* Chip Select 0 Upper Register */
68 u32 cs0l; /* Chip Select 0 Lower Register */
69 u32 cs0a; /* Chip Select 0 Addition Register */
71 u32 cs1u; /* Chip Select 1 Upper Register */
72 u32 cs1l; /* Chip Select 1 Lower Register */
73 u32 cs1a; /* Chip Select 1 Addition Register */
75 u32 cs2u; /* Chip Select 2 Upper Register */
76 u32 cs2l; /* Chip Select 2 Lower Register */
77 u32 cs2a; /* Chip Select 2 Addition Register */
79 u32 cs3u; /* Chip Select 3 Upper Register */
80 u32 cs3l; /* Chip Select 3 Lower Register */
81 u32 cs3a; /* Chip Select 3 Addition Register */
83 u32 cs4u; /* Chip Select 4 Upper Register */
84 u32 cs4l; /* Chip Select 4 Lower Register */
85 u32 cs4a; /* Chip Select 4 Addition Register */
87 u32 cs5u; /* Chip Select 5 Upper Register */
88 u32 cs5l; /* Chip Select 5 Lower Register */
89 u32 cs5a; /* Chip Select 5 Addition Register */
91 u32 eim; /* WEIM Configuration Register */
94 /* SDRAM Controller registers */
96 /* Enhanced SDRAM Control Register 0 */
98 /* Enhanced SDRAM Configuration Register 0 */
100 /* Enhanced SDRAM Control Register 1 */
102 /* Enhanced SDRAM Configuration Register 1 */
104 /* Enhanced SDRAM Miscellanious Register */
108 /* Watchdog Registers*/
117 u32 cscr; /* Clock Source Control Register */
118 u32 mpctl0; /* MCU PLL Control Register 0 */
119 u32 mpctl1; /* MCU PLL Control Register 1 */
120 u32 spctl0; /* System PLL Control Register 0 */
121 u32 spctl1; /* System PLL Control Register 1 */
122 u32 osc26mctl; /* Oscillator 26M Register */
123 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
124 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
125 u32 pccr0; /* Peripheral Clock Control Register 0 */
126 u32 pccr1; /* Peripheral Clock Control Register 1 */
127 u32 ccsr; /* Clock Control Status Register */
131 * Definitions for the clocksource registers
143 * GPIO Module and I/O Multiplexer
175 /* IIM Control Registers */
193 u32 iim_bank_area0[0x100];
197 #define IMX_IO_BASE 0x10000000
199 #define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
200 #define IMX_WDT_BASE (0x02000 + IMX_IO_BASE)
201 #define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE)
202 #define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE)
203 #define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE)
204 #define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE)
205 #define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE)
206 #define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE)
207 #define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE)
208 #define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE)
209 #define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE)
210 #define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE)
211 #define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE)
212 #define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE)
213 #define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE)
214 #define IMX_I2C2_BASE (0x1D000 + IMX_IO_BASE)
215 #define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE)
216 #define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE)
217 #define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
218 #define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE)
219 #define IMX_IIM_BASE (0x28000 + IMX_IO_BASE)
220 #define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE)
222 #define IMX_ESD_BASE (0xD8001000)
223 #define IMX_WEIM_BASE (0xD8002000)
225 /* FMCR System Control bit definition*/
226 #define UART4_RXD_CTL (1 << 25)
227 #define UART4_RTS_CTL (1 << 24)
228 #define KP_COL6_CTL (1 << 18)
229 #define KP_ROW7_CTL (1 << 17)
230 #define KP_ROW6_CTL (1 << 16)
231 #define PC_WAIT_B_CTL (1 << 14)
232 #define PC_READY_CTL (1 << 13)
233 #define PC_VS1_CTL (1 << 12)
234 #define PC_VS2_CTL (1 << 11)
235 #define PC_BVD1_CTL (1 << 10)
236 #define PC_BVD2_CTL (1 << 9)
237 #define IOS16_CTL (1 << 8)
238 #define NF_FMS (1 << 5)
239 #define NF_16BIT_SEL (1 << 4)
240 #define SLCDC_SEL (1 << 2)
241 #define SDCS1_SEL (1 << 1)
242 #define SDCS0_SEL (1 << 0)
245 /* important definition of some bits of WCR */
248 #define CSCR_MPEN (1 << 0)
249 #define CSCR_SPEN (1 << 1)
250 #define CSCR_FPM_EN (1 << 2)
251 #define CSCR_OSC26M_DIS (1 << 3)
252 #define CSCR_OSC26M_DIV1P5 (1 << 4)
255 #define CSCR_ARM_SRC_MPLL (1 << 15)
256 #define CSCR_MCU_SEL (1 << 16)
257 #define CSCR_SP_SEL (1 << 17)
258 #define CSCR_MPLL_RESTART (1 << 18)
259 #define CSCR_SPLL_RESTART (1 << 19)
260 #define CSCR_MSHC_SEL (1 << 20)
261 #define CSCR_H264_SEL (1 << 21)
262 #define CSCR_SSI1_SEL (1 << 22)
263 #define CSCR_SSI2_SEL (1 << 23)
266 #define CSCR_UPDATE_DIS (1 << 31)
268 #define MPCTL1_BRMO (1 << 6)
269 #define MPCTL1_LF (1 << 15)
271 #define PCCR0_SSI2_EN (1 << 0)
272 #define PCCR0_SSI1_EN (1 << 1)
273 #define PCCR0_SLCDC_EN (1 << 2)
274 #define PCCR0_SDHC3_EN (1 << 3)
275 #define PCCR0_SDHC2_EN (1 << 4)
276 #define PCCR0_SDHC1_EN (1 << 5)
277 #define PCCR0_SDC_EN (1 << 6)
278 #define PCCR0_SAHARA_EN (1 << 7)
279 #define PCCR0_RTIC_EN (1 << 8)
280 #define PCCR0_RTC_EN (1 << 9)
281 #define PCCR0_PWM_EN (1 << 11)
282 #define PCCR0_OWIRE_EN (1 << 12)
283 #define PCCR0_MSHC_EN (1 << 13)
284 #define PCCR0_LCDC_EN (1 << 14)
285 #define PCCR0_KPP_EN (1 << 15)
286 #define PCCR0_IIM_EN (1 << 16)
287 #define PCCR0_I2C2_EN (1 << 17)
288 #define PCCR0_I2C1_EN (1 << 18)
289 #define PCCR0_GPT6_EN (1 << 19)
290 #define PCCR0_GPT5_EN (1 << 20)
291 #define PCCR0_GPT4_EN (1 << 21)
292 #define PCCR0_GPT3_EN (1 << 22)
293 #define PCCR0_GPT2_EN (1 << 23)
294 #define PCCR0_GPT1_EN (1 << 24)
295 #define PCCR0_GPIO_EN (1 << 25)
296 #define PCCR0_FEC_EN (1 << 26)
297 #define PCCR0_EMMA_EN (1 << 27)
298 #define PCCR0_DMA_EN (1 << 28)
299 #define PCCR0_CSPI3_EN (1 << 29)
300 #define PCCR0_CSPI2_EN (1 << 30)
301 #define PCCR0_CSPI1_EN (1 << 31)
303 #define PCCR1_MSHC_BAUDEN (1 << 2)
304 #define PCCR1_NFC_BAUDEN (1 << 3)
305 #define PCCR1_SSI2_BAUDEN (1 << 4)
306 #define PCCR1_SSI1_BAUDEN (1 << 5)
307 #define PCCR1_H264_BAUDEN (1 << 6)
308 #define PCCR1_PERCLK4_EN (1 << 7)
309 #define PCCR1_PERCLK3_EN (1 << 8)
310 #define PCCR1_PERCLK2_EN (1 << 9)
311 #define PCCR1_PERCLK1_EN (1 << 10)
312 #define PCCR1_HCLK_USB (1 << 11)
313 #define PCCR1_HCLK_SLCDC (1 << 12)
314 #define PCCR1_HCLK_SAHARA (1 << 13)
315 #define PCCR1_HCLK_RTIC (1 << 14)
316 #define PCCR1_HCLK_LCDC (1 << 15)
317 #define PCCR1_HCLK_H264 (1 << 16)
318 #define PCCR1_HCLK_FEC (1 << 17)
319 #define PCCR1_HCLK_EMMA (1 << 18)
320 #define PCCR1_HCLK_EMI (1 << 19)
321 #define PCCR1_HCLK_DMA (1 << 20)
322 #define PCCR1_HCLK_CSI (1 << 21)
323 #define PCCR1_HCLK_BROM (1 << 22)
324 #define PCCR1_HCLK_ATA (1 << 23)
325 #define PCCR1_WDT_EN (1 << 24)
326 #define PCCR1_USB_EN (1 << 25)
327 #define PCCR1_UART6_EN (1 << 26)
328 #define PCCR1_UART5_EN (1 << 27)
329 #define PCCR1_UART4_EN (1 << 28)
330 #define PCCR1_UART3_EN (1 << 29)
331 #define PCCR1_UART2_EN (1 << 30)
332 #define PCCR1_UART1_EN (1 << 31)
334 /* SDRAM Controller registers bitfields */
335 #define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
336 #define ESDCTL_BL (1 << 7)
337 #define ESDCTL_FP (1 << 8)
338 #define ESDCTL_PWDT(x) (((x) & 3) << 10)
339 #define ESDCTL_SREFR(x) (((x) & 7) << 13)
340 #define ESDCTL_DSIZ_16_UPPER (0 << 16)
341 #define ESDCTL_DSIZ_16_LOWER (1 << 16)
342 #define ESDCTL_DSIZ_32 (2 << 16)
343 #define ESDCTL_COL8 (0 << 20)
344 #define ESDCTL_COL9 (1 << 20)
345 #define ESDCTL_COL10 (2 << 20)
346 #define ESDCTL_ROW11 (0 << 24)
347 #define ESDCTL_ROW12 (1 << 24)
348 #define ESDCTL_ROW13 (2 << 24)
349 #define ESDCTL_ROW14 (3 << 24)
350 #define ESDCTL_ROW15 (4 << 24)
351 #define ESDCTL_SP (1 << 27)
352 #define ESDCTL_SMODE_NORMAL (0 << 28)
353 #define ESDCTL_SMODE_PRECHARGE (1 << 28)
354 #define ESDCTL_SMODE_AUTO_REF (2 << 28)
355 #define ESDCTL_SMODE_LOAD_MODE (3 << 28)
356 #define ESDCTL_SMODE_MAN_REF (4 << 28)
357 #define ESDCTL_SDE (1 << 31)
359 #define ESDCFG_TRC(x) (((x) & 0xf) << 0)
360 #define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
361 #define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
362 #define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
363 #define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
364 #define ESDCFG_TWR (1 << 15)
365 #define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
366 #define ESDCFG_TRP(x) (((x) & 0x3) << 18)
367 #define ESDCFG_TWTR (1 << 20)
368 #define ESDCFG_TXP(x) (((x) & 0x3) << 21)
370 #define ESDMISC_RST (1 << 1)
371 #define ESDMISC_MDDREN (1 << 2)
372 #define ESDMISC_MDDR_DL_RST (1 << 3)
373 #define ESDMISC_MDDR_MDIS (1 << 4)
374 #define ESDMISC_LHD (1 << 5)
375 #define ESDMISC_MA10_SHARE (1 << 6)
376 #define ESDMISC_SDRAM_RDY (1 << 31)
378 #define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5)
379 #define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
380 #define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
381 #define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
382 #define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
383 #define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
384 #define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
385 #define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
386 #define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
388 #define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
389 #define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
390 #define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
391 #define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
392 #define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
393 #define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
394 #define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
395 #define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
396 #define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
397 #define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
398 #define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
399 #define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
400 #define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
401 #define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
402 #define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
403 #define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
404 #define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
405 #define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
407 #define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
408 #define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
409 #define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
410 #define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
411 #define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4)
412 #define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
413 #define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7)
414 #define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
415 #define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9)
416 #define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
417 #define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11)
418 #define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
419 #define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13)
420 #define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
421 #define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
422 #define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18)
423 #define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19)
424 #define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20)
425 #define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21)
426 #define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22)
427 #define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23)
428 #define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
429 #define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
430 #define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
431 #define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
432 #define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
433 #define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
434 #define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
435 #define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
436 #define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
437 #define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
439 /* Clocksource Bitfields */
440 #define TCTL_SWR (1 << 15) /* Software reset */
441 #define TCTL_FRR (1 << 8) /* Freerun / restart */
442 #define TCTL_CAP (3 << 6) /* Capture Edge */
443 #define TCTL_OM (1 << 5) /* output mode */
444 #define TCTL_IRQEN (1 << 4) /* interrupt enable */
445 #define TCTL_CLKSOURCE 1 /* Clock source bit position */
446 #define TCTL_TEN 1 /* Timer enable */
447 #define TPRER_PRES 0xff /* Prescale */
448 #define TSTAT_CAPT (1 << 1) /* Capture event */
449 #define TSTAT_COMP 1 /* Compare event */
451 #define GPIO_PIN_MASK 0x1f
453 #define GPIO_PORT_SHIFT 5
454 #define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
456 #define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT)
457 #define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT)
458 #define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT)
459 #define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT)
460 #define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT)
461 #define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT)
463 #define GPIO_OUT (1 << 8)
464 #define GPIO_IN (0 << 8)
465 #define GPIO_PUEN (1 << 9)
467 #define GPIO_PF (1 << 10)
468 #define GPIO_AF (1 << 11)
470 #define GPIO_OCR_SHIFT 12
471 #define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
472 #define GPIO_AIN (0 << GPIO_OCR_SHIFT)
473 #define GPIO_BIN (1 << GPIO_OCR_SHIFT)
474 #define GPIO_CIN (2 << GPIO_OCR_SHIFT)
475 #define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
477 #define GPIO_AOUT_SHIFT 14
478 #define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
479 #define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
480 #define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
481 #define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
482 #define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
484 #define GPIO_BOUT_SHIFT 16
485 #define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
486 #define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
487 #define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
488 #define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
489 #define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
491 #define IIM_STAT_BUSY (1 << 7)
492 #define IIM_STAT_PRGD (1 << 1)
493 #define IIM_STAT_SNSD (1 << 0)
494 #define IIM_ERR_PRGE (1 << 7)
495 #define IIM_ERR_WPE (1 << 6)
496 #define IIM_ERR_OPE (1 << 5)
497 #define IIM_ERR_RPE (1 << 4)
498 #define IIM_ERR_WLRE (1 << 3)
499 #define IIM_ERR_SNSE (1 << 2)
500 #define IIM_ERR_PARITYE (1 << 1)
502 /* Definitions for i.MX27 TO2 */
504 #define IIM0_SCC_KEY 11
507 #endif /* _IMX_REGS_H */